Thomas Lyp
Initial commit
Revision 0:bb348c97df44, committed 2020-09-16
- Comitter:
- lypinator
- Date:
- Wed Sep 16 01:11:49 2020 +0000
- Commit message:
- Added PWM
Changed in this revision
diff -r 000000000000 -r bb348c97df44 FastPWM.lib --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/FastPWM.lib Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,1 @@ +https://os.mbed.com/users/Sissors/code/FastPWM/#d6c2b73d71f5
diff -r 000000000000 -r bb348c97df44 MemoryController.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MemoryController.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,593 @@
+#include "MemoryController.h"
+
+
+
+
+
+ //Notes : May have to add pull-up resistor to busy line (see page 25 of data sheet)
+ // Must initialize device by sending reset command at power-on (page 36)
+ // Chip uses 3.3V logic :( sad face
+ // Collumn Address can be sent up to 4320 (0x10E0) to be valid.
+ // Pages are programmed at a time (4320 Bytes per page)
+// Blocks are erased at a time (128 Pages each, 1024 Blocks in total)
+
+
+
+
+
+
+
+//******************************************************************************
+MemoryController::MemoryController(DigitalOut CE,DigitalOut CLE,DigitalOut ALE,DigitalOut WE,DigitalOut RE,DigitalOut WP,PinName *DQ, DigitalIn RDY):
+m_CE(CE), m_CLE(CLE), m_ALE(ALE), m_WE(WE), m_RE(RE), m_WP(WP), m_DQ(DQ), m_RDY(RDY)
+{
+}
+
+
+//******************************************************************************
+MemoryController::~MemoryController(void)
+{
+ //empty block
+}
+
+void MemoryController::setDQ(const char set, bool *values){
+ for (int i = 0;i<8;i++){
+ values[i] = ((set >> i) & 1);
+ }
+}
+
+void MemoryController::ResetDevice(){
+ //CMD 0xFF, wait
+
+ bool DQOut[8];
+ m_WE =1;
+ m_CE = 0;
+ m_WP =1;
+ m_CLE = 0;
+ m_RE = 1;
+ setDQ(MemoryController::RESET, DQOut);
+ for(int i = 0;i<8;i++){
+ printf("%i\r\n",DQOut[i]);
+ }
+ //Set DQs
+ DigitalOut dq1(m_DQ[0],DQOut[0]);
+ DigitalOut dq2(m_DQ[1],DQOut[1]);
+ DigitalOut dq3(m_DQ[2],DQOut[2]);
+ DigitalOut dq4(m_DQ[3],DQOut[3]);
+ DigitalOut dq5(m_DQ[4],DQOut[4]);
+ DigitalOut dq6(m_DQ[5],DQOut[5]);
+ DigitalOut dq7(m_DQ[6],DQOut[6]);
+ DigitalOut dq8(m_DQ[7],DQOut[7]);
+ wait(1);
+ m_CLE =1;
+ m_WE = 0;
+ wait_ms(1);
+ m_WE =1;
+ wait_us(5);
+ //m_CLE = 0;
+ /*m_WE = 0;
+ wait_us(1);
+ m_WE = 1;
+ wait_us(10);
+ m_CLE = 0;
+ m_CE = 1;*/
+ //while(m_RDY ==1);
+ while(m_RDY != 1){
+ printf("Writing\r\n");
+ }
+ //setLogicStandby();
+ printf("System Reset -- Ready to rock and roll\r\n");
+}
+
+void MemoryController::ReadPage(DataAddress &address, char *DataOut){
+ //Start CMD 00, AADR c1, ADDR c2, ADDR r1, ADDR r2, ADDR r3, CMD 0x30, wait for rdy=1, data out
+ while (m_RDY == 0); //Bus is Busy, do not write yet
+ startPageRead(address);
+ //WriteAddressPage(address);
+ //endPageRead();
+ ReadData(DataOut);
+ setLogicStandby();
+ printf("Page Read Complete\r\n");
+}
+
+void MemoryController::sendPageData(char *DataIn){
+ setLogicDataOut();
+ DigitalOut dq1(m_DQ[0],0);
+ DigitalOut dq2(m_DQ[1],0);
+ DigitalOut dq3(m_DQ[2],0);
+ DigitalOut dq4(m_DQ[3],0);
+ DigitalOut dq5(m_DQ[4],0);
+ DigitalOut dq6(m_DQ[5],0);
+ DigitalOut dq7(m_DQ[6],0);
+ DigitalOut dq8(m_DQ[7],0);
+ wait_us(1);
+ int time =1;
+ Timer timer1;
+ timer1.start();
+ while(m_RDY == 0);
+ for (int i=0;i < 4320;i++){
+ bool DQOut[8];
+ setDQ(DataIn[i], DQOut);
+ dq1=DQOut[0];
+ dq2=DQOut[1];
+ dq3=DQOut[2];
+ dq4=DQOut[3];
+ dq5=DQOut[4];
+ dq6=DQOut[5];
+ dq7=DQOut[6];
+ dq8=DQOut[7];
+ m_WE = 0;
+ while(timer1.read_us() < time);
+ m_WE = 1;
+ time++;
+ while(timer1.read_us() < time);
+ time++;
+ }
+}
+
+void MemoryController::ReadData(char *DataOut){
+ setLogicDataOut();
+ DigitalIn dq1(m_DQ[0]);
+ DigitalIn dq2(m_DQ[1]);
+ DigitalIn dq3(m_DQ[2]);
+ DigitalIn dq4(m_DQ[3]);
+ DigitalIn dq5(m_DQ[4]);
+ DigitalIn dq6(m_DQ[5]);
+ DigitalIn dq7(m_DQ[6]);
+ DigitalIn dq8(m_DQ[7]);
+ Data dataOut;
+ wait_us(1);
+ while(m_RDY == 0);
+ m_RE = 0;
+ wait_us(1);
+ int time =1;
+ Timer timer1;
+ timer1.start();
+ for (int i=0;i < 4320;i++){
+ m_RE = 1;
+ dataOut.bits.dq1 = dq1;
+ dataOut.bits.dq2 = dq2;
+ dataOut.bits.dq3 = dq3;
+ dataOut.bits.dq4 = dq4;
+ dataOut.bits.dq5 = dq5;
+ dataOut.bits.dq6 = dq6;
+ dataOut.bits.dq7 = dq7;
+ dataOut.bits.dq8 = dq8;
+ DataOut[i] = dataOut.all;
+ while(timer1.read_us()<time);
+ m_RE = 0;
+ time++;
+ while(timer1.read_us() <time);
+ time++;
+ }
+}
+
+void MemoryController::startPageRead(DataAddress &address){
+ bool DQOut[8];
+ Timer timer1;
+ timer1.start();
+ setDQ(MemoryController::READADDRINIT, DQOut);
+ setLogicCommandInput();
+ m_WE =1;
+ while (timer1.read_us() < 1);
+ //Set DQs
+ DigitalOut dq1(m_DQ[0],DQOut[0]);
+ DigitalOut dq2(m_DQ[1],DQOut[1]);
+ DigitalOut dq3(m_DQ[2],DQOut[2]);
+ DigitalOut dq4(m_DQ[3],DQOut[3]);
+ DigitalOut dq5(m_DQ[4],DQOut[4]);
+ DigitalOut dq6(m_DQ[5],DQOut[5]);
+ DigitalOut dq7(m_DQ[6],DQOut[6]);
+ DigitalOut dq8(m_DQ[7],0);
+ m_WE = 0;
+ while (timer1.read_us() < 2);
+ wait_us(30);
+ m_WE = 1;
+ while(timer1.read_us() < 3);
+ m_WE=0;
+ setLogicAddressInput();
+ //collumn 1
+ setDQ(address.col1, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 5);
+ m_WE = 1;
+ while(timer1.read_us() < 6);
+ m_WE = 0;
+
+ //collumn 2
+ setDQ(address.col2, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 7);
+ m_WE = 1;
+ while(timer1.read_us() < 8);
+ m_WE =0;
+
+ //page
+ setDQ(address.page, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 9);
+ m_WE = 1;
+ while(timer1.read_us() < 10);
+ m_WE = 0;
+
+ //Block1
+ setDQ(address.block1, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 11);
+ m_WE = 1;
+ while(timer1.read_us() < 12);
+ m_WE = 0;
+
+ //Block2
+ setDQ(address.block2, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 13);
+ m_WE = 1;
+ while(timer1.read_us() < 14);
+ m_ALE = 0;
+ wait_us(1);
+ m_WE = 0;
+ wait_us(1);
+ //setLogicCommandInput();
+ setDQ(MemoryController::READADDREND, DQOut);
+ //Set DQs
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ m_CLE = 1;
+ wait_us(30);
+ m_WE = 1;
+ wait_us(10);
+ //while(timer1.read_us() < 17);
+}
+
+void MemoryController::startPageWrite(DataAddress &address){
+ bool DQOut[8];
+ Timer timer1;
+ timer1.start();
+ setDQ(MemoryController::WRITEPAGEINIT, DQOut);
+ setLogicCommandInput();
+ m_WE =1;
+ while (timer1.read_us() < 1);
+ //Set DQs
+ DigitalOut dq1(m_DQ[0],DQOut[0]);
+ DigitalOut dq2(m_DQ[1],DQOut[1]);
+ DigitalOut dq3(m_DQ[2],DQOut[2]);
+ DigitalOut dq4(m_DQ[3],DQOut[3]);
+ DigitalOut dq5(m_DQ[4],DQOut[4]);
+ DigitalOut dq6(m_DQ[5],DQOut[5]);
+ DigitalOut dq7(m_DQ[6],DQOut[6]);
+ DigitalOut dq8(m_DQ[7],DQOut[7]);
+ m_WE = 0;
+ while (timer1.read_us() < 2);
+ m_WE = 1;
+ while(timer1.read_us() < 3);
+ setLogicAddressInput();
+ m_WE=0;
+ //collumn 1
+ setDQ(address.col1, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 5);
+ m_WE = 1;
+ while(timer1.read_us() < 6);
+ m_WE = 0;
+
+ //collumn 2
+ setDQ(address.col2, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 7);
+ m_WE = 1;
+ while(timer1.read_us() < 8);
+ m_WE =0;
+
+ //page
+ setDQ(address.page, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 9);
+ m_WE = 1;
+ while(timer1.read_us() < 10);
+ m_WE = 0;
+
+ //Block1
+ setDQ(address.block1, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 11);
+ m_WE = 1;
+ while(timer1.read_us() < 12);
+ m_WE = 0;
+
+ //Block2
+ setDQ(address.block2, DQOut);
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 13);
+ m_WE = 1;
+ while(timer1.read_us() < 14);
+}
+
+void MemoryController::endPageRead(){
+ bool DQOut[8];
+ Timer timer1;
+ setDQ(MemoryController::READADDREND, DQOut);
+ setLogicCommandInput();
+ timer1.start();
+ //Set DQs
+ DigitalOut dq1(m_DQ[0],DQOut[0]);
+ DigitalOut dq2(m_DQ[1],DQOut[1]);
+ DigitalOut dq3(m_DQ[2],DQOut[2]);
+ DigitalOut dq4(m_DQ[3],DQOut[3]);
+ DigitalOut dq5(m_DQ[4],DQOut[4]);
+ DigitalOut dq6(m_DQ[5],DQOut[5]);
+ DigitalOut dq7(m_DQ[6],DQOut[6]);
+ DigitalOut dq8(m_DQ[7],DQOut[7]);
+ while(timer1.read_us() < 1);
+ m_WE = 1;
+ while(timer1.read_us() < 2);
+}
+
+void MemoryController::endPageWrite(){
+ bool DQOut[8];
+ Timer timer1;
+ setDQ(MemoryController::WRITEPAGEEND, DQOut);
+ setLogicCommandInput();
+ timer1.start();
+ //Set DQs
+ DigitalOut dq1(m_DQ[0],DQOut[0]);
+ DigitalOut dq2(m_DQ[1],DQOut[1]);
+ DigitalOut dq3(m_DQ[2],DQOut[2]);
+ DigitalOut dq4(m_DQ[3],DQOut[3]);
+ DigitalOut dq5(m_DQ[4],DQOut[4]);
+ DigitalOut dq6(m_DQ[5],DQOut[5]);
+ DigitalOut dq7(m_DQ[6],DQOut[6]);
+ DigitalOut dq8(m_DQ[7],DQOut[7]);
+ while(timer1.read_us() < 1);
+ m_WE = 1;
+ while(timer1.read_us() < 2);
+}
+
+void MemoryController::WriteAddressBlock(DataAddress &address){
+
+}
+
+void MemoryController::WriteAddressPage(DataAddress &address){
+ bool DQOut[8];
+ Timer timer1;
+ timer1.start();
+
+ //collumn 1
+ setDQ(address.col1, DQOut);
+ setLogicAddressInput();
+ DigitalOut dq1(m_DQ[0],DQOut[0]);
+ DigitalOut dq2(m_DQ[1],DQOut[1]);
+ DigitalOut dq3(m_DQ[2],DQOut[2]);
+ DigitalOut dq4(m_DQ[3],DQOut[3]);
+ DigitalOut dq5(m_DQ[4],DQOut[4]);
+ DigitalOut dq6(m_DQ[5],DQOut[5]);
+ DigitalOut dq7(m_DQ[6],DQOut[6]);
+ DigitalOut dq8(m_DQ[7],DQOut[7]);
+ while(timer1.read_us() < 1);
+ m_WE = 1;
+ while(timer1.read_us() < 2);
+ m_WE = 0;
+
+ //collumn 2
+ setDQ(address.col2, DQOut);
+ setLogicAddressInput();
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 3);
+ m_WE = 1;
+ while(timer1.read_us() < 4);
+ m_WE =0;
+
+ //page
+ setDQ(address.page, DQOut);
+ setLogicAddressInput();
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 5);
+ m_WE = 1;
+ while(timer1.read_us() < 6);
+ m_WE = 0;
+
+ //Block1
+ setDQ(address.block1, DQOut);
+ setLogicAddressInput();
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 7);
+ m_WE = 1;
+ while(timer1.read_us() < 8);
+ m_WE = 0;
+
+ //Block2
+ setDQ(address.block2, DQOut);
+ setLogicAddressInput();
+ dq1 = DQOut[0];
+ dq2 = DQOut[1];
+ dq3 = DQOut[2];
+ dq4 = DQOut[3];
+ dq5 = DQOut[4];
+ dq6 = DQOut[5];
+ dq7 = DQOut[6];
+ dq8 = DQOut[7];
+ while(timer1.read_us() < 9);
+ m_WE = 1;
+ while(timer1.read_us() < 10);
+ m_WE = 0;
+
+}
+
+void MemoryController::ProgramPage(DataAddress &address, char *DataIn){
+ //CMD 0x80, AADR c1, ADDR c2, ADDR r1, ADDR r2, ADDR r3, Page Data, CMD 0x10
+ while (m_RDY == 0);
+ startPageWrite(address);
+ //WriteAddressPage(address);
+ sendPageData(DataIn);
+ endPageWrite();
+ setLogicStandby();
+ printf("Page Write Complete\r\n");
+
+}
+
+void MemoryController::EraseBlock(DataAddress &address){
+ //CMD 0x60, ADDR R1, ADDR r2, ADDR r3, CMD oxD1
+ while (m_RDY == 0);
+
+
+}
+
+void MemoryController::setLogicStandby(){
+ m_CE = 1;
+ m_CLE = 0;
+ m_ALE = 0;
+ m_WE = 0;
+ m_RE = 0;
+ m_WP = 0;
+}
+
+void MemoryController::setLogicBusIdle(){
+ m_CE = 0;
+ m_CLE = 0;
+ m_ALE = 0;
+ m_WE = 1;
+ m_RE = 1;
+ m_WP = 0;
+}
+
+void MemoryController::setLogicCommandInput(){
+ m_CE = 0;
+ m_CLE = 1;
+ m_ALE = 0;
+ m_WE = 0; //rising edge
+ m_RE = 1;
+ m_WP = 1;
+}
+
+void MemoryController::setLogicAddressInput(){
+ m_CE = 0;
+ m_CLE = 0;
+ m_ALE = 1;
+ m_WE = 0; //rising edge
+ m_RE = 1;
+ m_WP = 1;
+}
+
+void MemoryController::setLogicDataInput(){
+ m_CE = 0;
+ m_CLE = 0;
+ m_ALE = 0;
+ m_WE = 1; //rising edge
+ m_RE = 1;
+ m_WP = 1;
+}
+
+void MemoryController::setLogicDataOut(){
+ m_CE = 0;
+ m_CLE = 0;
+ m_ALE = 0;
+ m_WE = 1;
+ m_RE = 1; //falling edge
+ m_WP = 0;
+}
+
+void MemoryController::setLogicWriteProtect(){
+ m_CE = 0;
+ m_CLE = 0;
+ m_ALE = 0;
+ m_WE = 0;
+ m_RE = 0;
+ m_WP = 0;
+}
\ No newline at end of file
diff -r 000000000000 -r bb348c97df44 MemoryController.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MemoryController.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,127 @@
+#ifndef __MemoryController_H_
+#define __MemoryController_H_
+
+#include "mbed.h"
+
+class MemoryController
+{
+
+public:
+
+ enum Commands_e
+ {
+ RESET = 0xFF,
+ READADDRINIT = 0x00,
+ READADDREND = 0x30,
+ WRITEPAGEINIT = 0x80,
+ WRITEPAGEEND = 0x10,
+ ERASEBLOCKINIT = 0x60,
+ ERASEBLOCKEND = 0xD1
+ };
+
+ union Data{
+ uint8_t all;
+ struct BitField_s
+ {
+ uint8_t dq1 : 1;
+ uint8_t dq2 : 1;
+ uint8_t dq3 : 1;
+ uint8_t dq4 : 1;
+ uint8_t dq5 : 1;
+ uint8_t dq6 : 1;
+ uint8_t dq7 : 1;
+ uint8_t dq8 : 1;
+ }bits;
+ };
+
+ struct DataAddress {
+ char col1;
+ char col2;
+ char page;
+ char block1;
+ char block2;
+ } Address;
+
+ MemoryController(DigitalOut CE,DigitalOut CLE,DigitalOut ALE,DigitalOut WE,DigitalOut RE,DigitalOut WP,PinName *DQ, DigitalIn RDY);
+
+ /** @brief Destructor */
+ ~MemoryController(void);
+
+ /**
+ * @brief Set Dq Bus to char value (8 bits) used for command writes and address writes
+ * @param[IN] set - Value to set DQ array to
+ * @param[OUT] values - Array where values are held (8 bits of 1's and 0's to set DQ)
+ */
+ void setDQ(const char set, bool *values);
+
+ /**
+ * @brief Used at initialization of Device
+ */
+ void ResetDevice();
+
+ void startPageRead(DataAddress &address);
+
+ void endPageRead();
+
+ void ReadData(char *DataOut);
+
+ void sendPageData(char *DataIn);
+
+ void startPageWrite(DataAddress &address);
+
+ void endPageWrite();
+
+
+ /**
+ * @brief Used to send address for block erase (3 bytes)
+ */
+ void MemoryController::WriteAddressBlock(DataAddress &address);
+
+ /**
+ * @brief Used to send address data for read/write page (5 bytes)
+ */
+ void MemoryController::WriteAddressPage(DataAddress &address);
+
+
+ /**
+ * @brief Read Page of Data (4320 bytes)
+ * @param[IN] address - address to read data from
+ * @param[OUT] DataOut - Array to write data into
+ */
+ void ReadPage(DataAddress &address, char *DataOut);
+
+ /**
+ * @brief Program 1 page (4320 bytes)
+ * @param[IN] adderess - address to program data to
+ * @param[IN] DataIn - Array pointer to data being written into page
+ */
+ void ProgramPage(DataAddress &address, char *DataIn);
+
+ /**
+ * @brief Earse 1 block (128 pages)
+ * @param[IN] address - Only row address characters for erasing block, no collumn needed
+ * @return 0 on success, 1 on failure
+ */
+ void EraseBlock(DataAddress &address);
+
+ void setLogicStandby();
+
+ void setLogicBusIdle();
+
+ void setLogicCommandInput();
+
+ void setLogicAddressInput();
+
+ void setLogicDataInput();
+
+ void setLogicDataOut();
+
+ void setLogicWriteProtect();
+
+private:
+ PinName *m_DQ;
+ DigitalOut m_CE, m_CLE, m_ALE, m_WE, m_RE, m_WP;
+ DigitalIn m_RDY;
+};
+
+#endif /* __MemoryController_H_ */
\ No newline at end of file
diff -r 000000000000 -r bb348c97df44 main.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,142 @@
+#include "mbed.h"
+#include "MemoryController.h"
+#include "FastPWM.h"
+
+DigitalOut CE(PA_5);
+DigitalOut CLE(PA_6);
+DigitalOut ALE(PA_7);
+DigitalOut WE(PA_8);
+DigitalOut RE(PA_9);
+DigitalOut WP(PA_10);
+DigitalIn RDY(PA_3);
+
+FastPWM PWMTrial(PC_12);
+
+//Not sure what to do here
+
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+
+ /* USER CODE END Error_Handler_Debug */
+}
+
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+DigitalOut led(LED1);
+
+int main()
+{
+ wait(1);
+ printf("Program Begin\r\n");
+ PWMTrial.pulsewidth_ticks(50);
+ PWMTrial.period_ticks(100);
+ PWMTrial.write(0.5);
+
+ /*
+ //Initialize
+ PinName DQ[8];
+ DQ[0] = PA_13;
+ DQ[1] = PA_14;
+ DQ[2] = PA_15;
+ DQ[3] = PB_7;
+ DQ[4] = PC_13;
+ DQ[5] = PC_11;
+ DQ[6] = PA_0;
+ DQ[7] = PA_1;
+
+ MemoryController mem(CE,CLE,ALE,WE,RE,WP,DQ,RDY);
+ char *dataOutput;
+ //Reserve Output Data Space
+ dataOutput = (char*)malloc(4321 * sizeof(char));
+ //Set Test Address
+ mem.Address.col1 = 0x02;
+ mem.Address.col2 = 0x02;
+ mem.Address.page = 0x02;
+ mem.Address.block1= 0x02;
+ mem.Address.block2= 0x02;
+
+
+ //Initialize the device
+ printf("Reset Being\r\n");
+ mem.ResetDevice();
+ printf("ResetComplete\r\n");
+ wait_us(100);
+
+ //read a page
+ printf("Bein Page Read\r\n");
+ dataOutput[0] = 1;
+ dataOutput[1] = 2;
+ printf("%i, %i\r\n",dataOutput[0],dataOutput[1]);
+ mem.ReadPage(mem.Address, dataOutput);
+ printf("Page Read Complete\r\n");
+
+ printf("Printing Data Values\r\n");
+ for(int i =0; i<128;i++){
+ printf("%i\r\n",dataOutput[i]);
+ }
+
+ for (int i=0; i<128;i++){
+ dataOutput[i]=i;
+ }
+ printf("Program New Values\r\n");
+ mem.ProgramPage(mem.Address, dataOutput);
+ for(int i = 0;i<150;i++){
+ dataOutput[i] = 0;
+ }
+ printf("Reading New Values\r\n");
+ mem.ReadPage(mem.Address,dataOutput);
+ for(int i =0;i<150;i++){
+ printf("%i\r\n",dataOutput[i]);
+ }
+ */
+ //write that page
+
+ //read that page
+
+ //erase that page
+
+ //read that page
+
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/LICENSE --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/LICENSE Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,165 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. Definitions. + +"License" shall mean the terms and conditions for use, reproduction, and +distribution as defined by Sections 1 through 9 of this document. + +"Licensor" shall mean the copyright owner or entity authorized by the copyright +owner that is granting the License. + +"Legal Entity" shall mean the union of the acting entity and all other entities +that control, are controlled by, or are under common control with that entity. +For the purposes of this definition, "control" means (i) the power, direct or +indirect, to cause the direction or management of such entity, whether by +contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the +outstanding shares, or (iii) beneficial ownership of such entity. + +"You" (or "Your") shall mean an individual or Legal Entity exercising +permissions granted by this License. + +"Source" form shall mean the preferred form for making modifications, including +but not limited to software source code, documentation source, and configuration +files. + +"Object" form shall mean any form resulting from mechanical transformation or +translation of a Source form, including but not limited to compiled object code, +generated documentation, and conversions to other media types. + +"Work" shall mean the work of authorship, whether in Source or Object form, made +available under the License, as indicated by a copyright notice that is included +in or attached to the work (an example is provided in the Appendix below). + +"Derivative Works" shall mean any work, whether in Source or Object form, that +is based on (or derived from) the Work and for which the editorial revisions, +annotations, elaborations, or other modifications represent, as a whole, an +original work of authorship. For the purposes of this License, Derivative Works +shall not include works that remain separable from, or merely link (or bind by +name) to the interfaces of, the Work and Derivative Works thereof. + +"Contribution" shall mean any work of authorship, including the original version +of the Work and any modifications or additions to that Work or Derivative Works +thereof, that is intentionally submitted to Licensor for inclusion in the Work +by the copyright owner or by an individual or Legal Entity authorized to submit +on behalf of the copyright owner. For the purposes of this definition, +"submitted" means any form of electronic, verbal, or written communication sent +to the Licensor or its representatives, including but not limited to +communication on electronic mailing lists, source code control systems, and +issue tracking systems that are managed by, or on behalf of, the Licensor for +the purpose of discussing and improving the Work, but excluding communication +that is conspicuously marked or otherwise designated in writing by the copyright +owner as "Not a Contribution." + +"Contributor" shall mean Licensor and any individual or Legal Entity on behalf +of whom a Contribution has been received by Licensor and subsequently +incorporated within the Work. + +2. Grant of Copyright License. + +Subject to the terms and conditions of this License, each Contributor hereby +grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, +irrevocable copyright license to reproduce, prepare Derivative Works of, +publicly display, publicly perform, sublicense, and distribute the Work and such +Derivative Works in Source or Object form. + +3. Grant of Patent License. + +Subject to the terms and conditions of this License, each Contributor hereby +grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, +irrevocable (except as stated in this section) patent license to make, have +made, use, offer to sell, sell, import, and otherwise transfer the Work, where +such license applies only to those patent claims licensable by such Contributor +that are necessarily infringed by their Contribution(s) alone or by combination +of their Contribution(s) with the Work to which such Contribution(s) was +submitted. If You institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the Work or a +Contribution incorporated within the Work constitutes direct or contributory +patent infringement, then any patent licenses granted to You under this License +for that Work shall terminate as of the date such litigation is filed. + +4. Redistribution. + +You may reproduce and distribute copies of the Work or Derivative Works thereof +in any medium, with or without modifications, and in Source or Object form, +provided that You meet the following conditions: + +You must give any other recipients of the Work or Derivative Works a copy of +this License; and +You must cause any modified files to carry prominent notices stating that You +changed the files; and +You must retain, in the Source form of any Derivative Works that You distribute, +all copyright, patent, trademark, and attribution notices from the Source form +of the Work, excluding those notices that do not pertain to any part of the +Derivative Works; and +If the Work includes a "NOTICE" text file as part of its distribution, then any +Derivative Works that You distribute must include a readable copy of the +attribution notices contained within such NOTICE file, excluding those notices +that do not pertain to any part of the Derivative Works, in at least one of the +following places: within a NOTICE text file distributed as part of the +Derivative Works; within the Source form or documentation, if provided along +with the Derivative Works; or, within a display generated by the Derivative +Works, if and wherever such third-party notices normally appear. The contents of +the NOTICE file are for informational purposes only and do not modify the +License. You may add Your own attribution notices within Derivative Works that +You distribute, alongside or as an addendum to the NOTICE text from the Work, +provided that such additional attribution notices cannot be construed as +modifying the License. +You may add Your own copyright statement to Your modifications and may provide +additional or different license terms and conditions for use, reproduction, or +distribution of Your modifications, or for any such Derivative Works as a whole, +provided Your use, reproduction, and distribution of the Work otherwise complies +with the conditions stated in this License. + +5. Submission of Contributions. + +Unless You explicitly state otherwise, any Contribution intentionally submitted +for inclusion in the Work by You to the Licensor shall be under the terms and +conditions of this License, without any additional terms or conditions. +Notwithstanding the above, nothing herein shall supersede or modify the terms of +any separate license agreement you may have executed with Licensor regarding +such Contributions. + +6. Trademarks. + +This License does not grant permission to use the trade names, trademarks, +service marks, or product names of the Licensor, except as required for +reasonable and customary use in describing the origin of the Work and +reproducing the content of the NOTICE file. + +7. Disclaimer of Warranty. + +Unless required by applicable law or agreed to in writing, Licensor provides the +Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, +including, without limitation, any warranties or conditions of TITLE, +NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are +solely responsible for determining the appropriateness of using or +redistributing the Work and assume any risks associated with Your exercise of +permissions under this License. + +8. Limitation of Liability. + +In no event and under no legal theory, whether in tort (including negligence), +contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be +liable to You for damages, including any direct, indirect, special, incidental, +or consequential damages of any character arising as a result of this License or +out of the use or inability to use the Work (including but not limited to +damages for loss of goodwill, work stoppage, computer failure or malfunction, or +any and all other commercial damages or losses), even if such Contributor has +been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to +offer, and charge a fee for, acceptance of support, warranty, indemnity, or +other liability obligations and/or rights consistent with this License. However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability.
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/RTE_Components.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/cmsis/RTE_Components.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,26 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +#define CMSIS_device_header <cmsis.h> + +#if defined(MBED_CONF_RTOS_PRESENT) +#include "mbed_rtx_conf.h" +#endif +#include "mbed_cmsis_conf.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_armcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_armcc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,544 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.2
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1))
+ #define __ARM_ARCH_7A__ 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE __forceinline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+
+/* ########################## Core Instruction Access ######################### */
+/**
+ \brief No Operation
+ */
+#define __NOP __nop
+
+/**
+ \brief Wait For Interrupt
+ */
+#define __WFI __wfi
+
+/**
+ \brief Wait For Event
+ */
+#define __WFE __wfe
+
+/**
+ \brief Send Event
+ */
+#define __SEV __sev
+
+/**
+ \brief Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+/**
+ \brief Breakpoint
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+/**
+ \brief Reverse bit order of value
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+/**
+ \brief Count leading zeros
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+/* ########################### Core Function Access ########################### */
+
+/**
+ \brief Get FPSCR (Floating Point Status/Control)
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+/**
+ \brief Set FPSCR (Floating Point Status/Control)
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+/** \brief Get CPSR (Current Program Status Register)
+ \return CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+ register uint32_t __regCPSR __ASM("cpsr");
+ return(__regCPSR);
+}
+
+
+/** \brief Set CPSR (Current Program Status Register)
+ \param [in] cpsr CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+ register uint32_t __regCPSR __ASM("cpsr");
+ __regCPSR = cpsr;
+}
+
+/** \brief Get Mode
+ \return Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void)
+{
+ return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief Set Mode
+ \param [in] mode Mode value to set
+ */
+__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
+{
+ MOV r1, lr
+ MSR CPSR_C, r0
+ BX r1
+}
+
+/** \brief Get Stack Pointer
+ \return Stack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP(void)
+{
+ MOV r0, sp
+ BX lr
+}
+
+/** \brief Set Stack Pointer
+ \param [in] stack Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
+{
+ MOV sp, r0
+ BX lr
+}
+
+
+/** \brief Get USR/SYS Stack Pointer
+ \return USR/SYSStack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
+{
+ ARM
+ PRESERVE8
+
+ MRS R1, CPSR
+ CPS #0x1F ;no effect in USR mode
+ MOV R0, SP
+ MSR CPSR_c, R1 ;no effect in USR mode
+ ISB
+ BX LR
+}
+
+/** \brief Set USR/SYS Stack Pointer
+ \param [in] topOfProcStack USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
+{
+ ARM
+ PRESERVE8
+
+ MRS R1, CPSR
+ CPS #0x1F ;no effect in USR mode
+ MOV SP, R0
+ MSR CPSR_c, R1 ;no effect in USR mode
+ ISB
+ BX LR
+}
+
+/** \brief Get FPEXC (Floating Point Exception Control Register)
+ \return Floating Point Exception Control Register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+ register uint32_t __regfpexc __ASM("fpexc");
+ return(__regfpexc);
+#else
+ return(0);
+#endif
+}
+
+/** \brief Set FPEXC (Floating Point Exception Control Register)
+ \param [in] fpexc Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+ register uint32_t __regfpexc __ASM("fpexc");
+ __regfpexc = (fpexc);
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
+#define __get_CP64(cp, op1, Rt, CRm) \
+ do { \
+ uint32_t ltmp, htmp; \
+ __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+ (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
+ } while(0)
+
+#define __set_CP64(cp, op1, Rt, CRm) \
+ do { \
+ const uint64_t tmp = (Rt); \
+ const uint32_t ltmp = (uint32_t)(tmp); \
+ const uint32_t htmp = (uint32_t)(tmp >> 32U); \
+ __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+ } while(0)
+
+#include "cmsis_cp15.h"
+
+/** \brief Enable Floating Point Unit
+
+ Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE __ASM void __FPU_Enable(void)
+{
+ ARM
+
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ MRC p15,0,R1,c1,c0,2
+ ORR R1,R1,#0x00F00000
+ MCR p15,0,R1,c1,c0,2
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ ISB
+
+ //Enable VFP/NEON
+ VMRS R1,FPEXC
+ ORR R1,R1,#0x40000000
+ VMSR FPEXC,R1
+
+ //Initialise VFP/NEON registers to 0
+ MOV R2,#0
+
+ //Initialise D16 registers to 0
+ VMOV D0, R2,R2
+ VMOV D1, R2,R2
+ VMOV D2, R2,R2
+ VMOV D3, R2,R2
+ VMOV D4, R2,R2
+ VMOV D5, R2,R2
+ VMOV D6, R2,R2
+ VMOV D7, R2,R2
+ VMOV D8, R2,R2
+ VMOV D9, R2,R2
+ VMOV D10,R2,R2
+ VMOV D11,R2,R2
+ VMOV D12,R2,R2
+ VMOV D13,R2,R2
+ VMOV D14,R2,R2
+ VMOV D15,R2,R2
+
+ IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+ //Initialise D32 registers to 0
+ VMOV D16,R2,R2
+ VMOV D17,R2,R2
+ VMOV D18,R2,R2
+ VMOV D19,R2,R2
+ VMOV D20,R2,R2
+ VMOV D21,R2,R2
+ VMOV D22,R2,R2
+ VMOV D23,R2,R2
+ VMOV D24,R2,R2
+ VMOV D25,R2,R2
+ VMOV D26,R2,R2
+ VMOV D27,R2,R2
+ VMOV D28,R2,R2
+ VMOV D29,R2,R2
+ VMOV D30,R2,R2
+ VMOV D31,R2,R2
+ ENDIF
+
+ //Initialise FPSCR to a known state
+ VMRS R2,FPSCR
+ LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ AND R2,R2,R3
+ VMSR FPSCR,R2
+
+ BX LR
+}
+
+#endif /* __CMSIS_ARMCC_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_armclang.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_armclang.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,503 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.2
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE __attribute__((always_inline))
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+
+/* ########################## Core Instruction Access ######################### */
+/**
+ \brief No Operation
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ */
+#define __WFI __builtin_arm_wfi
+
+/**
+ \brief Wait For Event
+ */
+#define __WFE __builtin_arm_wfe
+
+/**
+ \brief Send Event
+ */
+#define __SEV __builtin_arm_sev
+
+/**
+ \brief Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __builtin_arm_isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __builtin_arm_dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __builtin_arm_dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+/**
+ \brief Reverse bit order of value
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/* ########################### Core Function Access ########################### */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#define __get_FPSCR __builtin_arm_get_fpscr
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#define __set_FPSCR __builtin_arm_set_fpscr
+
+/** \brief Get CPSR Register
+ \return CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+ uint32_t result;
+ __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+ return(result);
+}
+
+/** \brief Set CPSR Register
+ \param [in] cpsr CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief Get Mode
+ \return Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+ return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief Set Mode
+ \param [in] mode Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+ __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief Get Stack Pointer
+ \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP()
+{
+ uint32_t result;
+ __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
+ return result;
+}
+
+/** \brief Set Stack Pointer
+ \param [in] stack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+ __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief Get USR/SYS Stack Pointer
+ \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr()
+{
+ uint32_t cpsr;
+ uint32_t result;
+ __ASM volatile(
+ "MRS %0, cpsr \n"
+ "CPS #0x1F \n" // no effect in USR mode
+ "MOV %1, sp \n"
+ "MSR cpsr_c, %2 \n" // no effect in USR mode
+ "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+ );
+ return result;
+}
+
+/** \brief Set USR/SYS Stack Pointer
+ \param [in] topOfProcStack USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+ uint32_t cpsr;
+ __ASM volatile(
+ "MRS %0, cpsr \n"
+ "CPS #0x1F \n" // no effect in USR mode
+ "MOV sp, %1 \n"
+ "MSR cpsr_c, %2 \n" // no effect in USR mode
+ "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+ );
+}
+
+/** \brief Get FPEXC
+ \return Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+ uint32_t result;
+ __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+/** \brief Set FPEXC
+ \param [in] fpexc Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief Enable Floating Point Unit
+
+ Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+ __ASM volatile(
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ " MRC p15,0,R1,c1,c0,2 \n"
+ " ORR R1,R1,#0x00F00000 \n"
+ " MCR p15,0,R1,c1,c0,2 \n"
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ " ISB \n"
+
+ //Enable VFP/NEON
+ " VMRS R1,FPEXC \n"
+ " ORR R1,R1,#0x40000000 \n"
+ " VMSR FPEXC,R1 \n"
+
+ //Initialise VFP/NEON registers to 0
+ " MOV R2,#0 \n"
+
+ //Initialise D16 registers to 0
+ " VMOV D0, R2,R2 \n"
+ " VMOV D1, R2,R2 \n"
+ " VMOV D2, R2,R2 \n"
+ " VMOV D3, R2,R2 \n"
+ " VMOV D4, R2,R2 \n"
+ " VMOV D5, R2,R2 \n"
+ " VMOV D6, R2,R2 \n"
+ " VMOV D7, R2,R2 \n"
+ " VMOV D8, R2,R2 \n"
+ " VMOV D9, R2,R2 \n"
+ " VMOV D10,R2,R2 \n"
+ " VMOV D11,R2,R2 \n"
+ " VMOV D12,R2,R2 \n"
+ " VMOV D13,R2,R2 \n"
+ " VMOV D14,R2,R2 \n"
+ " VMOV D15,R2,R2 \n"
+
+#if __ARM_NEON == 1
+ //Initialise D32 registers to 0
+ " VMOV D16,R2,R2 \n"
+ " VMOV D17,R2,R2 \n"
+ " VMOV D18,R2,R2 \n"
+ " VMOV D19,R2,R2 \n"
+ " VMOV D20,R2,R2 \n"
+ " VMOV D21,R2,R2 \n"
+ " VMOV D22,R2,R2 \n"
+ " VMOV D23,R2,R2 \n"
+ " VMOV D24,R2,R2 \n"
+ " VMOV D25,R2,R2 \n"
+ " VMOV D26,R2,R2 \n"
+ " VMOV D27,R2,R2 \n"
+ " VMOV D28,R2,R2 \n"
+ " VMOV D29,R2,R2 \n"
+ " VMOV D30,R2,R2 \n"
+ " VMOV D31,R2,R2 \n"
+#endif
+
+ //Initialise FPSCR to a known state
+ " VMRS R2,FPSCR \n"
+ " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ " AND R2,R2,R3 \n"
+ " VMSR FPSCR,R2 "
+ );
+}
+
+#endif /* __CMSIS_ARMCLANG_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_compiler.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_compiler.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.2
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include "cmsis_iccarm.h"
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __UNALIGNED_UINT32
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __UNALIGNED_UINT32
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef CMSIS_DEPRECATED
+ #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.
+ #define CMSIS_DEPRECATED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __UNALIGNED_UINT32
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_cp15.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_cp15.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,514 @@
+/**************************************************************************//**
+ * @file cmsis_cp15.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.1
+ * @date 07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_CP15_H
+#define __CMSIS_CP15_H
+
+/** \brief Get ACTLR
+ \return Auxiliary Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 1, 0, 1);
+ return(result);
+}
+
+/** \brief Set ACTLR
+ \param [in] actlr Auxiliary Control value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
+{
+ __set_CP(15, 0, actlr, 1, 0, 1);
+}
+
+/** \brief Get CPACR
+ \return Coprocessor Access Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 1, 0, 2);
+ return result;
+}
+
+/** \brief Set CPACR
+ \param [in] cpacr Coprocessor Access Control value to set
+ */
+__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
+{
+ __set_CP(15, 0, cpacr, 1, 0, 2);
+}
+
+/** \brief Get DFSR
+ \return Data Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 5, 0, 0);
+ return result;
+}
+
+/** \brief Set DFSR
+ \param [in] dfsr Data Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
+{
+ __set_CP(15, 0, dfsr, 5, 0, 0);
+}
+
+/** \brief Get IFSR
+ \return Instruction Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 5, 0, 1);
+ return result;
+}
+
+/** \brief Set IFSR
+ \param [in] ifsr Instruction Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
+{
+ __set_CP(15, 0, ifsr, 5, 0, 1);
+}
+
+/** \brief Get ISR
+ \return Interrupt Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ISR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 12, 1, 0);
+ return result;
+}
+
+/** \brief Get CBAR
+ \return Configuration Base Address register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
+{
+ uint32_t result;
+ __get_CP(15, 4, result, 15, 0, 0);
+ return result;
+}
+
+/** \brief Get TTBR0
+
+ This function returns the value of the Translation Table Base Register 0.
+
+ \return Translation Table Base Register 0 value
+ */
+__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 2, 0, 0);
+ return result;
+}
+
+/** \brief Set TTBR0
+
+ This function assigns the given value to the Translation Table Base Register 0.
+
+ \param [in] ttbr0 Translation Table Base Register 0 value to set
+ */
+__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
+{
+ __set_CP(15, 0, ttbr0, 2, 0, 0);
+}
+
+/** \brief Get DACR
+
+ This function returns the value of the Domain Access Control Register.
+
+ \return Domain Access Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DACR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 3, 0, 0);
+ return result;
+}
+
+/** \brief Set DACR
+
+ This function assigns the given value to the Domain Access Control Register.
+
+ \param [in] dacr Domain Access Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
+{
+ __set_CP(15, 0, dacr, 3, 0, 0);
+}
+
+/** \brief Set SCTLR
+
+ This function assigns the given value to the System Control Register.
+
+ \param [in] sctlr System Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
+{
+ __set_CP(15, 0, sctlr, 1, 0, 0);
+}
+
+/** \brief Get SCTLR
+ \return System Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 1, 0, 0);
+ return result;
+}
+
+/** \brief Set ACTRL
+ \param [in] actrl Auxiliary Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
+{
+ __set_CP(15, 0, actrl, 1, 0, 1);
+}
+
+/** \brief Get ACTRL
+ \return Auxiliary Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 1, 0, 1);
+ return result;
+}
+
+/** \brief Get MPIDR
+
+ This function returns the value of the Multiprocessor Affinity Register.
+
+ \return Multiprocessor Affinity Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 0, 0, 5);
+ return result;
+}
+
+/** \brief Get VBAR
+
+ This function returns the value of the Vector Base Address Register.
+
+ \return Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 12, 0, 0);
+ return result;
+}
+
+/** \brief Set VBAR
+
+ This function assigns the given value to the Vector Base Address Register.
+
+ \param [in] vbar Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
+{
+ __set_CP(15, 0, vbar, 12, 0, 0);
+}
+
+/** \brief Get MVBAR
+
+ This function returns the value of the Monitor Vector Base Address Register.
+
+ \return Monitor Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 12, 0, 1);
+ return result;
+}
+
+/** \brief Set MVBAR
+
+ This function assigns the given value to the Monitor Vector Base Address Register.
+
+ \param [in] mvbar Monitor Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
+{
+ __set_CP(15, 0, mvbar, 12, 0, 1);
+}
+
+#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
+ defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
+ defined(DOXYGEN)
+
+/** \brief Set CNTFRQ
+
+ This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+ \param [in] value CNTFRQ Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
+{
+ __set_CP(15, 0, value, 14, 0, 0);
+}
+
+/** \brief Get CNTFRQ
+
+ This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+ \return CNTFRQ Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 14, 0 , 0);
+ return result;
+}
+
+/** \brief Set CNTP_TVAL
+
+ This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+ \param [in] value CNTP_TVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
+{
+ __set_CP(15, 0, value, 14, 2, 0);
+}
+
+/** \brief Get CNTP_TVAL
+
+ This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+ \return CNTP_TVAL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 14, 2, 0);
+ return result;
+}
+
+/** \brief Get CNTPCT
+
+ This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
+
+ \return CNTPCT Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
+{
+ uint64_t result;
+ __get_CP64(15, 0, result, 14);
+ return result;
+}
+
+/** \brief Set CNTP_CVAL
+
+ This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+ \param [in] value CNTP_CVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
+{
+ __set_CP64(15, 2, value, 14);
+}
+
+/** \brief Get CNTP_CVAL
+
+ This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+ \return CNTP_CVAL Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
+{
+ uint64_t result;
+ __get_CP64(15, 2, result, 14);
+ return result;
+}
+
+/** \brief Set CNTP_CTL
+
+ This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+ \param [in] value CNTP_CTL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
+{
+ __set_CP(15, 0, value, 14, 2, 1);
+}
+
+/** \brief Get CNTP_CTL register
+ \return CNTP_CTL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
+{
+ uint32_t result;
+ __get_CP(15, 0, result, 14, 2, 1);
+ return result;
+}
+
+#endif
+
+/** \brief Set TLBIALL
+
+ TLB Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
+{
+ __set_CP(15, 0, value, 8, 7, 0);
+}
+
+/** \brief Set BPIALL.
+
+ Branch Predictor Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 5, 6);
+}
+
+/** \brief Set ICIALLU
+
+ Instruction Cache Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 5, 0);
+}
+
+/** \brief Set DCCMVAC
+
+ Data cache clean
+ */
+__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 10, 1);
+}
+
+/** \brief Set DCIMVAC
+
+ Data cache invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 6, 1);
+}
+
+/** \brief Set DCCIMVAC
+
+ Data cache clean and invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
+{
+ __set_CP(15, 0, value, 7, 14, 1);
+}
+
+/** \brief Set CSSELR
+ */
+__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
+{
+// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
+ __set_CP(15, 2, value, 0, 0, 0);
+}
+
+/** \brief Get CSSELR
+ \return CSSELR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
+{
+ uint32_t result;
+// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
+ __get_CP(15, 2, result, 0, 0, 0);
+ return result;
+}
+
+/** \brief Set CCSIDR
+ \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
+ */
+CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
+{
+ __set_CSSELR(value);
+}
+
+/** \brief Get CCSIDR
+ \return CCSIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
+{
+ uint32_t result;
+// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
+ __get_CP(15, 1, result, 0, 0, 0);
+ return result;
+}
+
+/** \brief Get CLIDR
+ \return CLIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
+{
+ uint32_t result;
+// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
+ __get_CP(15, 1, result, 0, 0, 1);
+ return result;
+}
+
+/** \brief Set DCISW
+ */
+__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
+{
+// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
+ __set_CP(15, 0, value, 7, 6, 2);
+}
+
+/** \brief Set DCCSW
+ */
+__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
+{
+// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
+ __set_CP(15, 0, value, 7, 10, 2);
+}
+
+/** \brief Set DCCISW
+ */
+__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
+{
+// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
+ __set_CP(15, 0, value, 7, 14, 2);
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_gcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_gcc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,675 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler specific macros, functions, instructions
+ * @version V1.0.1
+ * @date 07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE __attribute__((always_inline))
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+
+/* ########################## Core Instruction Access ######################### */
+/**
+ \brief No Operation
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+/**
+ \brief Wait For Event
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+/**
+ \brief Send Event
+ */
+#define __SEV() __ASM volatile ("sev")
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+ __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
+ return result;
+}
+#endif
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U) {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+/**
+ \brief Count leading zeros
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+/* ########################### Core Function Access ########################### */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+*/
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+ #else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+ #endif
+ #else
+ return(0U);
+ #endif
+}
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+*/
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+ #else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ #endif
+ #else
+ (void)fpscr;
+ #endif
+}
+
+/** \brief Get CPSR Register
+ \return CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+ uint32_t result;
+ __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+ return(result);
+}
+
+/** \brief Set CPSR Register
+ \param [in] cpsr CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief Get Mode
+ \return Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+ return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief Set Mode
+ \param [in] mode Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+ __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief Get Stack Pointer
+ \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
+{
+ uint32_t result;
+ __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
+ return result;
+}
+
+/** \brief Set Stack Pointer
+ \param [in] stack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+ __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief Get USR/SYS Stack Pointer
+ \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
+{
+ uint32_t cpsr = __get_CPSR();
+ uint32_t result;
+ __ASM volatile(
+ "CPS #0x1F \n"
+ "MOV %0, sp " : "=r"(result) : : "memory"
+ );
+ __set_CPSR(cpsr);
+ __ISB();
+ return result;
+}
+
+/** \brief Set USR/SYS Stack Pointer
+ \param [in] topOfProcStack USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+ uint32_t cpsr = __get_CPSR();
+ __ASM volatile(
+ "CPS #0x1F \n"
+ "MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
+ );
+ __set_CPSR(cpsr);
+ __ISB();
+}
+
+/** \brief Get FPEXC
+ \return Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+ uint32_t result;
+ __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+/** \brief Set FPEXC
+ \param [in] fpexc Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+ __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief Enable Floating Point Unit
+
+ Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+ __ASM volatile(
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ " MRC p15,0,R1,c1,c0,2 \n"
+ " ORR R1,R1,#0x00F00000 \n"
+ " MCR p15,0,R1,c1,c0,2 \n"
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ " ISB \n"
+
+ //Enable VFP/NEON
+ " VMRS R1,FPEXC \n"
+ " ORR R1,R1,#0x40000000 \n"
+ " VMSR FPEXC,R1 \n"
+
+ //Initialise VFP/NEON registers to 0
+ " MOV R2,#0 \n"
+
+ //Initialise D16 registers to 0
+ " VMOV D0, R2,R2 \n"
+ " VMOV D1, R2,R2 \n"
+ " VMOV D2, R2,R2 \n"
+ " VMOV D3, R2,R2 \n"
+ " VMOV D4, R2,R2 \n"
+ " VMOV D5, R2,R2 \n"
+ " VMOV D6, R2,R2 \n"
+ " VMOV D7, R2,R2 \n"
+ " VMOV D8, R2,R2 \n"
+ " VMOV D9, R2,R2 \n"
+ " VMOV D10,R2,R2 \n"
+ " VMOV D11,R2,R2 \n"
+ " VMOV D12,R2,R2 \n"
+ " VMOV D13,R2,R2 \n"
+ " VMOV D14,R2,R2 \n"
+ " VMOV D15,R2,R2 \n"
+
+#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
+ //Initialise D32 registers to 0
+ " VMOV D16,R2,R2 \n"
+ " VMOV D17,R2,R2 \n"
+ " VMOV D18,R2,R2 \n"
+ " VMOV D19,R2,R2 \n"
+ " VMOV D20,R2,R2 \n"
+ " VMOV D21,R2,R2 \n"
+ " VMOV D22,R2,R2 \n"
+ " VMOV D23,R2,R2 \n"
+ " VMOV D24,R2,R2 \n"
+ " VMOV D25,R2,R2 \n"
+ " VMOV D26,R2,R2 \n"
+ " VMOV D27,R2,R2 \n"
+ " VMOV D28,R2,R2 \n"
+ " VMOV D29,R2,R2 \n"
+ " VMOV D30,R2,R2 \n"
+ " VMOV D31,R2,R2 \n"
+#endif
+
+ //Initialise FPSCR to a known state
+ " VMRS R2,FPSCR \n"
+ " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ " AND R2,R2,R3 \n"
+ " VMSR FPSCR,R2 "
+ );
+}
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,559 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.5
+ * @date 10. January 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#pragma language=extended
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_7A__
+/* Macro already defined */
+#else
+ #if defined(__ARM7A__)
+ #define __ARM_ARCH_7A__ 1
+ #endif
+#endif
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ /* Needs IAR language extensions */
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ /* Needs IAR language extensions */
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ /* Needs IAR language extensions */
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #define __RESTRICT restrict
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef CMSIS_DEPRECATED
+ #define CMSIS_DEPRECATED __attribute__((deprecated))
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma language=save
+ #pragma language=extended
+ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+ {
+ return *(__packed uint16_t*)(ptr);
+ }
+ #pragma language=restore
+ #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma language=save
+ #pragma language=extended
+ __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+ {
+ *(__packed uint16_t*)(ptr) = val;;
+ }
+ #pragma language=restore
+ #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma language=save
+ #pragma language=extended
+ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+ {
+ return *(__packed uint32_t*)(ptr);
+ }
+ #pragma language=restore
+ #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma language=save
+ #pragma language=extended
+ __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+ {
+ *(__packed uint32_t*)(ptr) = val;;
+ }
+ #pragma language=restore
+ #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#if 0
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma language=save
+ #pragma language=extended
+ __packed struct __iar_u32 { uint32_t v; };
+ #pragma language=restore
+ #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+ #if __FPU_PRESENT
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #endif
+
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE))
+
+ #define __get_CPSR() (__arm_rsr("CPSR"))
+ #define __get_mode() (__get_CPSR() & 0x1FU)
+
+ #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE)))
+ #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE)))
+
+
+ #define __get_FPEXC() (__arm_rsr("FPEXC"))
+ #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE))
+
+ #define __get_CP(cp, op1, RT, CRn, CRm, op2) \
+ ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
+
+ #define __set_CP(cp, op1, RT, CRn, CRm, op2) \
+ (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
+
+ #define __get_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
+
+ #define __set_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
+
+ #include "cmsis_cp15.h"
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #define __SSAT __iar_builtin_SSAT
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #define __USAT __iar_builtin_USAT
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if !__FPU_PRESENT
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if !__FPU_PRESENT
+ #define __get_FPSCR() (0)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ __IAR_FT void __set_mode(uint32_t mode)
+ {
+ __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
+ }
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ __IAR_FT uint32_t __get_FPEXC(void)
+ {
+ #if (__FPU_PRESENT == 1)
+ uint32_t result;
+ __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+ return(result);
+ #else
+ return(0);
+ #endif
+ }
+
+ __IAR_FT void __set_FPEXC(uint32_t fpexc)
+ {
+ #if (__FPU_PRESENT == 1)
+ __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+ #endif
+ }
+
+
+ #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
+ __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+ #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
+ __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+ #define __get_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
+ #define __set_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
+
+ #include "cmsis_cp15.h"
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+
+__IAR_FT uint32_t __get_SP_usr(void)
+{
+ uint32_t cpsr;
+ uint32_t result;
+ __ASM volatile(
+ "MRS %0, cpsr \n"
+ "CPS #0x1F \n" // no effect in USR mode
+ "MOV %1, sp \n"
+ "MSR cpsr_c, %2 \n" // no effect in USR mode
+ "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+ );
+ return result;
+}
+
+__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
+{
+ uint32_t cpsr;
+ __ASM volatile(
+ "MRS %0, cpsr \n"
+ "CPS #0x1F \n" // no effect in USR mode
+ "MOV sp, %1 \n"
+ "MSR cpsr_c, %2 \n" // no effect in USR mode
+ "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+ );
+}
+
+#define __get_mode() (__get_CPSR() & 0x1FU)
+
+__STATIC_INLINE
+void __FPU_Enable(void)
+{
+ __ASM volatile(
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ " MRC p15,0,R1,c1,c0,2 \n"
+ " ORR R1,R1,#0x00F00000 \n"
+ " MCR p15,0,R1,c1,c0,2 \n"
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ " ISB \n"
+
+ //Enable VFP/NEON
+ " VMRS R1,FPEXC \n"
+ " ORR R1,R1,#0x40000000 \n"
+ " VMSR FPEXC,R1 \n"
+
+ //Initialise VFP/NEON registers to 0
+ " MOV R2,#0 \n"
+
+ //Initialise D16 registers to 0
+ " VMOV D0, R2,R2 \n"
+ " VMOV D1, R2,R2 \n"
+ " VMOV D2, R2,R2 \n"
+ " VMOV D3, R2,R2 \n"
+ " VMOV D4, R2,R2 \n"
+ " VMOV D5, R2,R2 \n"
+ " VMOV D6, R2,R2 \n"
+ " VMOV D7, R2,R2 \n"
+ " VMOV D8, R2,R2 \n"
+ " VMOV D9, R2,R2 \n"
+ " VMOV D10,R2,R2 \n"
+ " VMOV D11,R2,R2 \n"
+ " VMOV D12,R2,R2 \n"
+ " VMOV D13,R2,R2 \n"
+ " VMOV D14,R2,R2 \n"
+ " VMOV D15,R2,R2 \n"
+
+#ifdef __ARM_ADVANCED_SIMD__
+ //Initialise D32 registers to 0
+ " VMOV D16,R2,R2 \n"
+ " VMOV D17,R2,R2 \n"
+ " VMOV D18,R2,R2 \n"
+ " VMOV D19,R2,R2 \n"
+ " VMOV D20,R2,R2 \n"
+ " VMOV D21,R2,R2 \n"
+ " VMOV D22,R2,R2 \n"
+ " VMOV D23,R2,R2 \n"
+ " VMOV D24,R2,R2 \n"
+ " VMOV D25,R2,R2 \n"
+ " VMOV D26,R2,R2 \n"
+ " VMOV D27,R2,R2 \n"
+ " VMOV D28,R2,R2 \n"
+ " VMOV D29,R2,R2 \n"
+ " VMOV D30,R2,R2 \n"
+ " VMOV D31,R2,R2 \n"
+#endif
+
+ //Initialise FPSCR to a known state
+ " VMRS R2,FPSCR \n"
+ " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ " AND R2,R2,R3 \n"
+ " VMSR FPSCR,R2 \n");
+}
+
+
+
+#undef __IAR_FT
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_A/core_ca.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_A/core_ca.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2616 @@
+/**************************************************************************//**
+ * @file core_ca.h
+ * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
+ * @version V1.00
+ * @date 22. Feb 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CA_H_GENERIC
+#define __CORE_CA_H_GENERIC
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+
+/* CMSIS CA definitions */
+#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */
+#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
+#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
+ __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CA_H_DEPENDANT
+#define __CORE_CA_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+ /* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CA_REV
+ #define __CA_REV 0x0000U
+ #warning "__CA_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __GIC_PRESENT
+ #define __GIC_PRESENT 1U
+ #warning "__GIC_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __TIM_PRESENT
+ #define __TIM_PRESENT 1U
+ #warning "__TIM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __L2C_PRESENT
+ #define __L2C_PRESENT 0U
+ #warning "__L2C_PRESENT not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+ #define __I volatile /*!< \brief Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< \brief Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< \brief Defines 'write only' permissions */
+#define __IO volatile /*!< \brief Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
+#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
+#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
+#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
+
+ /*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - CPSR
+ - CP15 Registers
+ - L2C-310 Cache Controller
+ - Generic Interrupt Controller Distributor
+ - Generic Interrupt Controller Interface
+ ******************************************************************************/
+
+/* Core Register CPSR */
+typedef union
+{
+ struct
+ {
+ uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
+ uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
+ uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
+ uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
+ uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
+ uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
+ uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
+ uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
+ RESERVED(0:4, uint32_t)
+ uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
+ uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
+ uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} CPSR_Type;
+
+
+
+/* CPSR Register Definitions */
+#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
+#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
+
+#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
+#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
+
+#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
+#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
+
+#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
+#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
+
+#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
+#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
+
+#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
+#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
+
+#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
+#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
+
+#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
+#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
+
+#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
+#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
+
+#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
+#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
+
+#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
+#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
+
+#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
+#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
+
+#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
+#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
+
+#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
+#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
+
+#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
+#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
+
+#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */
+#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
+#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */
+#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */
+#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */
+#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */
+#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */
+#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */
+#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */
+
+/* CP15 Register SCTLR */
+typedef union
+{
+ struct
+ {
+ uint32_t M:1; /*!< \brief bit: 0 MMU enable */
+ uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
+ uint32_t C:1; /*!< \brief bit: 2 Cache enable */
+ RESERVED(0:2, uint32_t)
+ uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
+ RESERVED(1:1, uint32_t)
+ uint32_t B:1; /*!< \brief bit: 7 Endianness model */
+ RESERVED(2:2, uint32_t)
+ uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
+ uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
+ uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
+ uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
+ uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
+ RESERVED(3:2, uint32_t)
+ uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
+ RESERVED(4:1, uint32_t)
+ uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
+ uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
+ uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
+ uint32_t U:1; /*!< \brief bit: 22 Alignment model */
+ RESERVED(5:1, uint32_t)
+ uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
+ uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
+ RESERVED(6:1, uint32_t)
+ uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
+ uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
+ uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
+ uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
+ RESERVED(7:1, uint32_t)
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} SCTLR_Type;
+
+#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
+#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
+
+#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
+#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
+
+#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
+#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
+
+#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
+#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
+
+#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
+#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
+
+#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
+#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
+
+#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
+#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
+
+#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
+#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
+
+#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
+#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
+
+#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
+#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
+
+#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
+#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
+
+#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
+#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
+
+#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
+#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
+
+#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
+#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
+
+#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
+#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
+
+#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
+#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
+
+#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
+#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
+
+#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
+#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
+
+#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
+#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
+
+#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
+#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
+
+#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
+#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
+
+/* CP15 Register ACTLR */
+typedef union
+{
+#if __CORTEX_A == 5 || defined(DOXYGEN)
+ /** \brief Structure used for bit access on Cortex-A5 */
+ struct
+ {
+ uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
+ RESERVED(0:5, uint32_t)
+ uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
+ uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
+ RESERVED(1:2, uint32_t)
+ uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
+ uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */
+ uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
+ uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
+ uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */
+ uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */
+ uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */
+ RESERVED(3:9, uint32_t)
+ uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */
+ RESERVED(7:3, uint32_t)
+ } b;
+#endif
+#if __CORTEX_A == 7 || defined(DOXYGEN)
+ /** \brief Structure used for bit access on Cortex-A7 */
+ struct
+ {
+ RESERVED(0:6, uint32_t)
+ uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
+ RESERVED(1:3, uint32_t)
+ uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
+ uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */
+ uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
+ uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
+ uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */
+ RESERVED(3:12, uint32_t)
+ uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */
+ RESERVED(7:3, uint32_t)
+ } b;
+#endif
+#if __CORTEX_A == 9 || defined(DOXYGEN)
+ /** \brief Structure used for bit access on Cortex-A9 */
+ struct
+ {
+ uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
+ RESERVED(0:1, uint32_t)
+ uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */
+ uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */
+ RESERVED(1:2, uint32_t)
+ uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
+ uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
+ uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */
+ uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */
+ RESERVED(7:22, uint32_t)
+ } b;
+#endif
+ uint32_t w; /*!< \brief Type used for word access */
+} ACTLR_Type;
+
+#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */
+#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */
+
+#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */
+#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */
+
+#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */
+#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */
+
+#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */
+#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */
+
+#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */
+#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */
+
+#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */
+#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */
+
+#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */
+#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */
+
+#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */
+#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */
+
+#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */
+#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */
+
+#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */
+#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */
+
+#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */
+#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */
+
+#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */
+#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */
+
+#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */
+#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */
+
+#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */
+#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */
+
+#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */
+#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */
+
+#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */
+#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */
+
+#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */
+#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */
+
+#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */
+#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */
+
+#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */
+#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */
+
+/* CP15 Register CPACR */
+typedef union
+{
+ struct
+ {
+ uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */
+ uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */
+ uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */
+ uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */
+ uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */
+ uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */
+ uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */
+ uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */
+ uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */
+ uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */
+ uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
+ uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
+ uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */
+ uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */
+ uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */
+ RESERVED(0:1, uint32_t)
+ uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
+ uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} CPACR_Type;
+
+#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
+#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
+
+#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
+#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */
+#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */
+#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */
+
+#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */
+#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */
+#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */
+
+/* CP15 Register DFSR */
+typedef union
+{
+ struct
+ {
+ uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
+ uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
+ RESERVED(0:1, uint32_t)
+ uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
+ uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
+ uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
+ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
+ uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
+ RESERVED(1:18, uint32_t)
+ } s; /*!< \brief Structure used for bit access in short format */
+ struct
+ {
+ uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */
+ RESERVED(0:3, uint32_t)
+ uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
+ RESERVED(1:1, uint32_t)
+ uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
+ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
+ uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
+ RESERVED(2:18, uint32_t)
+ } l; /*!< \brief Structure used for bit access in long format */
+ uint32_t w; /*!< \brief Type used for word access */
+} DFSR_Type;
+
+#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
+#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
+
+#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
+#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
+
+#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
+#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
+
+#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
+#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
+
+#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */
+#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */
+
+#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
+#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
+
+#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
+#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
+
+#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */
+#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */
+
+/* CP15 Register IFSR */
+typedef union
+{
+ struct
+ {
+ uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
+ RESERVED(0:5, uint32_t)
+ uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
+ uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
+ RESERVED(1:1, uint32_t)
+ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
+ RESERVED(2:19, uint32_t)
+ } s; /*!< \brief Structure used for bit access in short format */
+ struct
+ {
+ uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */
+ RESERVED(0:3, uint32_t)
+ uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
+ RESERVED(1:2, uint32_t)
+ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
+ RESERVED(2:19, uint32_t)
+ } l; /*!< \brief Structure used for bit access in long format */
+ uint32_t w; /*!< \brief Type used for word access */
+} IFSR_Type;
+
+#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
+#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
+
+#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
+#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
+
+#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */
+#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */
+
+#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
+#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
+
+#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */
+#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */
+
+/* CP15 Register ISR */
+typedef union
+{
+ struct
+ {
+ RESERVED(0:6, uint32_t)
+ uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
+ uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
+ uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
+ RESERVED(1:23, uint32_t)
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} ISR_Type;
+
+#define ISR_A_Pos 13U /*!< \brief ISR: A Position */
+#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
+
+#define ISR_I_Pos 12U /*!< \brief ISR: I Position */
+#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
+
+#define ISR_F_Pos 11U /*!< \brief ISR: F Position */
+#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
+
+/* DACR Register */
+#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */
+#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */
+#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */
+#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */
+#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param [in] field Name of the register bit field.
+ \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param [in] field Name of the register bit field.
+ \param [in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+
+/**
+ \brief Union type to access the L2C_310 Cache Controller.
+*/
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+typedef struct
+{
+ __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */
+ __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */
+ RESERVED(0[0x3e], uint32_t)
+ __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */
+ __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */
+ RESERVED(1[0x3e], uint32_t)
+ __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */
+ __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */
+ __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */
+ RESERVED(2[0x2], uint32_t)
+ __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */
+ __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */
+ __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */
+ __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */
+ RESERVED(3[0x143], uint32_t)
+ __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */
+ RESERVED(4[0xf], uint32_t)
+ __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */
+ RESERVED(6[2], uint32_t)
+ __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */
+ RESERVED(5[0xc], uint32_t)
+ __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */
+ RESERVED(7[1], uint32_t)
+ __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */
+ __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */
+ RESERVED(8[0xc], uint32_t)
+ __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */
+ RESERVED(9[1], uint32_t)
+ __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */
+ __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */
+ RESERVED(10[0x40], uint32_t)
+ __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */
+ __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */
+ __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */
+ __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */
+ __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */
+ __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */
+ __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */
+ __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */
+ __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */
+ __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */
+ __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */
+ __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */
+ __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */
+ __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */
+ __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */
+ __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */
+ RESERVED(11[0x4], uint32_t)
+ __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */
+ __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */
+ RESERVED(12[0xaa], uint32_t)
+ __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */
+ __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */
+ RESERVED(13[0xce], uint32_t)
+ __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */
+} L2C_310_TypeDef;
+
+#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
+#endif
+
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+
+/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
+*/
+typedef struct
+{
+ __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */
+ __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
+ RESERVED(0, uint32_t)
+ __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */
+ RESERVED(1[11], uint32_t)
+ __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */
+ RESERVED(2, uint32_t)
+ __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */
+ RESERVED(3, uint32_t)
+ __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */
+ RESERVED(4, uint32_t)
+ __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */
+ RESERVED(5[9], uint32_t)
+ __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */
+ __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
+ __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
+ __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
+ __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
+ __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */
+ __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
+ __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */
+ RESERVED(6, uint32_t)
+ __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */
+ RESERVED(7, uint32_t)
+ __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */
+ __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
+ RESERVED(8[32], uint32_t)
+ __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */
+ __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */
+ RESERVED(9[3], uint32_t)
+ __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
+ __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */
+ RESERVED(10[5236], uint32_t)
+ __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */
+} GICDistributor_Type;
+
+#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
+
+/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
+*/
+typedef struct
+{
+ __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */
+ __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */
+ __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */
+ __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
+ __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */
+ __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */
+ __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
+ __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */
+ __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
+ __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
+ __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
+ __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */
+ RESERVED(1[40], uint32_t)
+ __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */
+ __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
+ RESERVED(2[3], uint32_t)
+ __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */
+ RESERVED(3[960], uint32_t)
+ __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */
+} GICInterface_Type;
+
+#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */
+#endif
+
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Structure type to access the Private Timer
+*/
+typedef struct
+{
+ __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
+ __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
+ __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
+ __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
+ RESERVED(0[4], uint32_t)
+ __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
+ __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
+ __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
+ __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
+ __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
+ __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
+} Timer_Type;
+#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */
+#endif
+#endif
+
+ /*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - L1 Cache Functions
+ - L2C-310 Cache Controller Functions
+ - PL1 Timer Functions
+ - GIC Functions
+ - MMU Functions
+ ******************************************************************************/
+
+/* ########################## L1 Cache functions ################################# */
+
+/** \brief Enable Caches by setting I and C bits in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_EnableCaches(void) {
+ __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
+ __ISB();
+}
+
+/** \brief Disable Caches by clearing I and C bits in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_DisableCaches(void) {
+ __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
+ __ISB();
+}
+
+/** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
+ __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
+ __ISB();
+}
+
+/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
+*/
+__STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
+ __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
+ __ISB();
+}
+
+/** \brief Invalidate entire branch predictor array
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
+ __set_BPIALL(0);
+ __DSB(); //ensure completion of the invalidation
+ __ISB(); //ensure instruction fetch path sees new state
+}
+
+/** \brief Invalidate the whole instruction cache
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
+ __set_ICIALLU(0);
+ __DSB(); //ensure completion of the invalidation
+ __ISB(); //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief Clean data cache line by address.
+* \param [in] va Pointer to data to clear the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
+ __set_DCCMVAC((uint32_t)va);
+ __DMB(); //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief Invalidate data cache line by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
+ __set_DCIMVAC((uint32_t)va);
+ __DMB(); //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief Clean and Invalidate data cache by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
+ __set_DCCIMVAC((uint32_t)va);
+ __DMB(); //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief Calculate log2 rounded up
+* - log(0) => 0
+* - log(1) => 0
+* - log(2) => 1
+* - log(3) => 2
+* - log(4) => 2
+* - log(5) => 3
+* : :
+* - log(16) => 4
+* - log(32) => 5
+* : :
+* \param [in] n input value parameter
+* \return log2(n)
+*/
+__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
+{
+ if (n < 2U) {
+ return 0U;
+ }
+ uint8_t log = 0U;
+ uint32_t t = n;
+ while(t > 1U)
+ {
+ log++;
+ t >>= 1U;
+ }
+ if (n & 1U) { log++; }
+ return log;
+}
+
+/** \brief Apply cache maintenance to given cache level.
+* \param [in] level cache level to be maintained
+* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+*/
+__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
+{
+ uint32_t Dummy;
+ uint32_t ccsidr;
+ uint32_t num_sets;
+ uint32_t num_ways;
+ uint32_t shift_way;
+ uint32_t log2_linesize;
+ int32_t log2_num_ways;
+
+ Dummy = level << 1U;
+ /* set csselr, select ccsidr register */
+ __set_CSSELR(Dummy);
+ /* get current ccsidr register */
+ ccsidr = __get_CCSIDR();
+ num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
+ num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
+ log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
+ log2_num_ways = __log2_up(num_ways);
+ if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
+ return; // FATAL ERROR
+ }
+ shift_way = 32U - (uint32_t)log2_num_ways;
+ for(int32_t way = num_ways-1; way >= 0; way--)
+ {
+ for(int32_t set = num_sets-1; set >= 0; set--)
+ {
+ Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
+ switch (maint)
+ {
+ case 0U: __set_DCISW(Dummy); break;
+ case 1U: __set_DCCSW(Dummy); break;
+ default: __set_DCCISW(Dummy); break;
+ }
+ }
+ }
+ __DMB();
+}
+
+/** \brief Clean and Invalidate the entire data or unified cache
+* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+*/
+__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
+ uint32_t clidr;
+ uint32_t cache_type;
+ clidr = __get_CLIDR();
+ for(uint32_t i = 0U; i<7U; i++)
+ {
+ cache_type = (clidr >> i*3U) & 0x7UL;
+ if ((cache_type >= 2U) && (cache_type <= 4U))
+ {
+ __L1C_MaintainDCacheSetWay(i, op);
+ }
+ }
+}
+
+/** \brief Clean and Invalidate the entire data or unified cache
+* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+* \deprecated Use generic L1C_CleanInvalidateCache instead.
+*/
+CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
+ L1C_CleanInvalidateCache(op);
+}
+
+/** \brief Invalidate the whole data cache.
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
+ L1C_CleanInvalidateCache(0);
+}
+
+/** \brief Clean the whole data cache.
+ */
+__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
+ L1C_CleanInvalidateCache(1);
+}
+
+/** \brief Clean and invalidate the whole data cache.
+ */
+__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
+ L1C_CleanInvalidateCache(2);
+}
+
+/* ########################## L2 Cache functions ################################# */
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+/** \brief Cache Sync operation by writing CACHE_SYNC register.
+*/
+__STATIC_INLINE void L2C_Sync(void)
+{
+ L2C_310->CACHE_SYNC = 0x0;
+}
+
+/** \brief Read cache controller cache ID from CACHE_ID register.
+ * \return L2C_310_TypeDef::CACHE_ID
+ */
+__STATIC_INLINE int L2C_GetID (void)
+{
+ return L2C_310->CACHE_ID;
+}
+
+/** \brief Read cache controller cache type from CACHE_TYPE register.
+* \return L2C_310_TypeDef::CACHE_TYPE
+*/
+__STATIC_INLINE int L2C_GetType (void)
+{
+ return L2C_310->CACHE_TYPE;
+}
+
+/** \brief Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_InvAllByWay (void)
+{
+ unsigned int assoc;
+
+ if (L2C_310->AUX_CNT & (1U << 16U)) {
+ assoc = 16U;
+ } else {
+ assoc = 8U;
+ }
+
+ L2C_310->INV_WAY = (1U << assoc) - 1U;
+ while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
+
+ L2C_Sync();
+}
+
+/** \brief Clean and Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_CleanInvAllByWay (void)
+{
+ unsigned int assoc;
+
+ if (L2C_310->AUX_CNT & (1U << 16U)) {
+ assoc = 16U;
+ } else {
+ assoc = 8U;
+ }
+
+ L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
+ while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
+
+ L2C_Sync();
+}
+
+/** \brief Enable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Enable(void)
+{
+ L2C_310->CONTROL = 0;
+ L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
+ L2C_310->DEBUG_CONTROL = 0;
+ L2C_310->DATA_LOCK_0_WAY = 0;
+ L2C_310->CACHE_SYNC = 0;
+ L2C_310->CONTROL = 0x01;
+ L2C_Sync();
+}
+
+/** \brief Disable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Disable(void)
+{
+ L2C_310->CONTROL = 0x00;
+ L2C_Sync();
+}
+
+/** \brief Invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_InvPa (void *pa)
+{
+ L2C_310->INV_LINE_PA = (unsigned int)pa;
+ L2C_Sync();
+}
+
+/** \brief Clean cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanPa (void *pa)
+{
+ L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
+ L2C_Sync();
+}
+
+/** \brief Clean and invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanInvPa (void *pa)
+{
+ L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
+ L2C_Sync();
+}
+#endif
+
+/* ########################## GIC functions ###################################### */
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+
+/** \brief Enable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_EnableDistributor(void)
+{
+ GICDistributor->CTLR |= 1U;
+}
+
+/** \brief Disable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_DisableDistributor(void)
+{
+ GICDistributor->CTLR &=~1U;
+}
+
+/** \brief Read the GIC's TYPER register.
+* \return GICDistributor_Type::TYPER
+*/
+__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
+{
+ return (GICDistributor->TYPER);
+}
+
+/** \brief Reads the GIC's IIDR register.
+* \return GICDistributor_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
+{
+ return (GICDistributor->IIDR);
+}
+
+/** \brief Sets the GIC's ITARGETSR register for the given interrupt.
+* \param [in] IRQn Interrupt to be configured.
+* \param [in] cpu_target CPU interfaces to assign this interrupt to.
+*/
+__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+ uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+ GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the GIC's ITARGETSR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return GICDistributor_Type::ITARGETSR
+*/
+__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+ return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Enable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_EnableInterface(void)
+{
+ GICInterface->CTLR |= 1U; //enable interface
+}
+
+/** \brief Disable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_DisableInterface(void)
+{
+ GICInterface->CTLR &=~1U; //disable distributor
+}
+
+/** \brief Read the CPU's IAR register.
+* \return GICInterface_Type::IAR
+*/
+__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
+{
+ return (IRQn_Type)(GICInterface->IAR);
+}
+
+/** \brief Writes the given interrupt number to the CPU's EOIR register.
+* \param [in] IRQn The interrupt to be signaled as finished.
+*/
+__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+ GICInterface->EOIR = IRQn;
+}
+
+/** \brief Enables the given interrupt using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt enable status using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
+*/
+__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+
+/** \brief Disables the given interrupt using GIC's ICENABLER register.
+* \param [in] IRQn The interrupt to be disabled.
+*/
+__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt pending status from GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not pending, 1 - interrupt is pendig.
+*/
+__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ uint32_t pend;
+
+ if (IRQn >= 16U) {
+ pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+ } else {
+ // INTID 0-15 Software Generated Interrupt
+ pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+ // No CPU identification offered
+ if (pend != 0U) {
+ pend = 1U;
+ } else {
+ pend = 0U;
+ }
+ }
+
+ return (pend);
+}
+
+/** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if (IRQn >= 16U) {
+ GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+ } else {
+ // INTID 0-15 Software Generated Interrupt
+ GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+ // Forward the interrupt to the CPU interface that requested it
+ GICDistributor->SGIR = (IRQn | 0x02000000U);
+ }
+}
+
+/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if (IRQn >= 16U) {
+ GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+ } else {
+ // INTID 0-15 Software Generated Interrupt
+ GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+ }
+}
+
+/** \brief Sets the interrupt configuration using GIC's ICFGR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+* Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
+{
+ uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
+ uint32_t shift = (IRQn % 16U) << 1U;
+
+ icfgr &= (~(3U << shift));
+ icfgr |= ( int_config << shift);
+
+ GICDistributor->ICFGR[IRQn / 16U] = icfgr;
+}
+
+/** \brief Get the interrupt configuration from the GIC's ICFGR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+* Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
+{
+ return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
+}
+
+/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] priority The priority for the interrupt, lower values denote higher priorities.
+*/
+__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+ GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be queried.
+*/
+__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+ return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Set the interrupt priority mask using CPU's PMR register.
+* \param [in] priority Priority mask to be set.
+*/
+__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
+{
+ GICInterface->PMR = priority & 0xFFUL; //set priority mask
+}
+
+/** \brief Read the current interrupt priority mask from CPU's PMR register.
+* \result GICInterface_Type::PMR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
+{
+ return GICInterface->PMR;
+}
+
+/** \brief Configures the group priority and subpriority split point using CPU's BPR register.
+* \param [in] binary_point Amount of bits used as subpriority.
+*/
+__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+ GICInterface->BPR = binary_point & 7U; //set binary point
+}
+
+/** \brief Read the current group priority and subpriority split point from CPU's BPR register.
+* \return GICInterface_Type::BPR
+*/
+__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
+{
+ return GICInterface->BPR;
+}
+
+/** \brief Get the status for a given interrupt.
+* \param [in] IRQn The interrupt to get status for.
+* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
+*/
+__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+ uint32_t pending, active;
+
+ active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
+ pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
+
+ return ((active<<1U) | pending);
+}
+
+/** \brief Generate a software interrupt using GIC's SGIR register.
+* \param [in] IRQn Software interrupt to be generated.
+* \param [in] target_list List of CPUs the software interrupt should be forwarded to.
+* \param [in] filter_list Filter to be applied to determine interrupt receivers.
+*/
+__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+ GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
+}
+
+/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
+* \return GICInterface_Type::HPPIR
+*/
+__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
+{
+ return GICInterface->HPPIR;
+}
+
+/** \brief Provides information about the implementer and revision of the CPU interface.
+* \return GICInterface_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
+{
+ return GICInterface->IIDR;
+}
+
+/** \brief Set the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
+{
+ uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
+ uint32_t shift = (IRQn % 32U);
+
+ igroupr &= (~(1U << shift));
+ igroupr |= ( (group & 1U) << shift);
+
+ GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
+}
+#define GIC_SetSecurity GIC_SetGroup
+
+/** \brief Get the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
+{
+ return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+#define GIC_GetSecurity GIC_GetGroup
+
+/** \brief Initialize the interrupt distributor.
+*/
+__STATIC_INLINE void GIC_DistInit(void)
+{
+ uint32_t i;
+ uint32_t num_irq = 0U;
+ uint32_t priority_field;
+
+ //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+ //configuring all of the interrupts as Secure.
+
+ //Disable interrupt forwarding
+ GIC_DisableDistributor();
+ //Get the maximum number of interrupts that the GIC supports
+ num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
+
+ /* Priority level is implementation defined.
+ To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+ priority field and read back the value stored.*/
+ GIC_SetPriority((IRQn_Type)0U, 0xFFU);
+ priority_field = GIC_GetPriority((IRQn_Type)0U);
+
+ for (i = 32U; i < num_irq; i++)
+ {
+ //Disable the SPI interrupt
+ GIC_DisableIRQ((IRQn_Type)i);
+ //Set level-sensitive (and N-N model)
+ GIC_SetConfiguration((IRQn_Type)i, 0U);
+ //Set priority
+ GIC_SetPriority((IRQn_Type)i, priority_field/2U);
+ //Set target list to CPU0
+ GIC_SetTarget((IRQn_Type)i, 1U);
+ }
+ //Enable distributor
+ GIC_EnableDistributor();
+}
+
+/** \brief Initialize the CPU's interrupt interface
+*/
+__STATIC_INLINE void GIC_CPUInterfaceInit(void)
+{
+ uint32_t i;
+ uint32_t priority_field;
+
+ //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+ //configuring all of the interrupts as Secure.
+
+ //Disable interrupt forwarding
+ GIC_DisableInterface();
+
+ /* Priority level is implementation defined.
+ To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+ priority field and read back the value stored.*/
+ GIC_SetPriority((IRQn_Type)0U, 0xFFU);
+ priority_field = GIC_GetPriority((IRQn_Type)0U);
+
+ //SGI and PPI
+ for (i = 0U; i < 32U; i++)
+ {
+ if(i > 15U) {
+ //Set level-sensitive (and N-N model) for PPI
+ GIC_SetConfiguration((IRQn_Type)i, 0U);
+ }
+ //Disable SGI and PPI interrupts
+ GIC_DisableIRQ((IRQn_Type)i);
+ //Set priority
+ GIC_SetPriority((IRQn_Type)i, priority_field/2U);
+ }
+ //Enable interface
+ GIC_EnableInterface();
+ //Set binary point to 0
+ GIC_SetBinaryPoint(0U);
+ //Set priority mask
+ GIC_SetInterfacePriorityMask(0xFFU);
+}
+
+/** \brief Initialize and enable the GIC
+*/
+__STATIC_INLINE void GIC_Enable(void)
+{
+ GIC_DistInit();
+ GIC_CPUInterfaceInit(); //per CPU
+}
+#endif
+
+/* ########################## Generic Timer functions ############################ */
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+
+/* PL1 Physical Timer */
+#if (__CORTEX_A == 7U) || defined(DOXYGEN)
+
+/** \brief Physical Timer Control register */
+typedef union
+{
+ struct
+ {
+ uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */
+ uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */
+ uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */
+ RESERVED(0:29, uint32_t)
+ } b; /*!< \brief Structure used for bit access */
+ uint32_t w; /*!< \brief Type used for word access */
+} CNTP_CTL_Type;
+
+/** \brief Configures the frequency the timer shall run at.
+* \param [in] value The timer frequency in Hz.
+*/
+__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
+{
+ __set_CNTFRQ(value);
+ __ISB();
+}
+
+/** \brief Sets the reset value of the timer.
+* \param [in] value The value the timer is loaded with.
+*/
+__STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
+{
+ __set_CNTP_TVAL(value);
+ __ISB();
+}
+
+/** \brief Get the current counter value.
+* \return Current counter value.
+*/
+__STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
+{
+ return(__get_CNTP_TVAL());
+}
+
+/** \brief Get the current physical counter value.
+* \return Current physical counter value.
+*/
+__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
+{
+ return(__get_CNTPCT());
+}
+
+/** \brief Set the physical compare value.
+* \param [in] value New physical timer compare value.
+*/
+__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
+{
+ __set_CNTP_CVAL(value);
+ __ISB();
+}
+
+/** \brief Get the physical compare value.
+* \return Physical compare value.
+*/
+__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
+{
+ return(__get_CNTP_CVAL());
+}
+
+/** \brief Configure the timer by setting the control value.
+* \param [in] value New timer control value.
+*/
+__STATIC_INLINE void PL1_SetControl(uint32_t value)
+{
+ __set_CNTP_CTL(value);
+ __ISB();
+}
+
+/** \brief Get the control value.
+* \return Control value.
+*/
+__STATIC_INLINE uint32_t PL1_GetControl(void)
+{
+ return(__get_CNTP_CTL());
+}
+#endif
+
+/* Private Timer */
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Set the load value to timers LOAD register.
+* \param [in] value The load value to be set.
+*/
+__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
+{
+ PTIM->LOAD = value;
+}
+
+/** \brief Get the load value from timers LOAD register.
+* \return Timer_Type::LOAD
+*/
+__STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
+{
+ return(PTIM->LOAD);
+}
+
+/** \brief Set current counter value from its COUNTER register.
+*/
+__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
+{
+ PTIM->COUNTER = value;
+}
+
+/** \brief Get current counter value from timers COUNTER register.
+* \result Timer_Type::COUNTER
+*/
+__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
+{
+ return(PTIM->COUNTER);
+}
+
+/** \brief Configure the timer using its CONTROL register.
+* \param [in] value The new configuration value to be set.
+*/
+__STATIC_INLINE void PTIM_SetControl(uint32_t value)
+{
+ PTIM->CONTROL = value;
+}
+
+/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
+* \return Timer_Type::CONTROL
+*/
+__STATIC_INLINE uint32_t PTIM_GetControl(void)
+{
+ return(PTIM->CONTROL);
+}
+
+/** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
+* \return 0 - flag is not set, 1- flag is set
+*/
+__STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
+{
+ return (PTIM->ISR & 1UL);
+}
+
+/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
+*/
+__STATIC_INLINE void PTIM_ClearEventFlag(void)
+{
+ PTIM->ISR = 1;
+}
+#endif
+#endif
+
+/* ########################## MMU functions ###################################### */
+
+#define SECTION_DESCRIPTOR (0x2)
+#define SECTION_MASK (0xFFFFFFFC)
+
+#define SECTION_TEXCB_MASK (0xFFFF8FF3)
+#define SECTION_B_SHIFT (2)
+#define SECTION_C_SHIFT (3)
+#define SECTION_TEX0_SHIFT (12)
+#define SECTION_TEX1_SHIFT (13)
+#define SECTION_TEX2_SHIFT (14)
+
+#define SECTION_XN_MASK (0xFFFFFFEF)
+#define SECTION_XN_SHIFT (4)
+
+#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
+#define SECTION_DOMAIN_SHIFT (5)
+
+#define SECTION_P_MASK (0xFFFFFDFF)
+#define SECTION_P_SHIFT (9)
+
+#define SECTION_AP_MASK (0xFFFF73FF)
+#define SECTION_AP_SHIFT (10)
+#define SECTION_AP2_SHIFT (15)
+
+#define SECTION_S_MASK (0xFFFEFFFF)
+#define SECTION_S_SHIFT (16)
+
+#define SECTION_NG_MASK (0xFFFDFFFF)
+#define SECTION_NG_SHIFT (17)
+
+#define SECTION_NS_MASK (0xFFF7FFFF)
+#define SECTION_NS_SHIFT (19)
+
+#define PAGE_L1_DESCRIPTOR (0x1)
+#define PAGE_L1_MASK (0xFFFFFFFC)
+
+#define PAGE_L2_4K_DESC (0x2)
+#define PAGE_L2_4K_MASK (0xFFFFFFFD)
+
+#define PAGE_L2_64K_DESC (0x1)
+#define PAGE_L2_64K_MASK (0xFFFFFFFC)
+
+#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
+#define PAGE_4K_B_SHIFT (2)
+#define PAGE_4K_C_SHIFT (3)
+#define PAGE_4K_TEX0_SHIFT (6)
+#define PAGE_4K_TEX1_SHIFT (7)
+#define PAGE_4K_TEX2_SHIFT (8)
+
+#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
+#define PAGE_64K_B_SHIFT (2)
+#define PAGE_64K_C_SHIFT (3)
+#define PAGE_64K_TEX0_SHIFT (12)
+#define PAGE_64K_TEX1_SHIFT (13)
+#define PAGE_64K_TEX2_SHIFT (14)
+
+#define PAGE_TEXCB_MASK (0xFFFF8FF3)
+#define PAGE_B_SHIFT (2)
+#define PAGE_C_SHIFT (3)
+#define PAGE_TEX_SHIFT (12)
+
+#define PAGE_XN_4K_MASK (0xFFFFFFFE)
+#define PAGE_XN_4K_SHIFT (0)
+#define PAGE_XN_64K_MASK (0xFFFF7FFF)
+#define PAGE_XN_64K_SHIFT (15)
+
+#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
+#define PAGE_DOMAIN_SHIFT (5)
+
+#define PAGE_P_MASK (0xFFFFFDFF)
+#define PAGE_P_SHIFT (9)
+
+#define PAGE_AP_MASK (0xFFFFFDCF)
+#define PAGE_AP_SHIFT (4)
+#define PAGE_AP2_SHIFT (9)
+
+#define PAGE_S_MASK (0xFFFFFBFF)
+#define PAGE_S_SHIFT (10)
+
+#define PAGE_NG_MASK (0xFFFFF7FF)
+#define PAGE_NG_SHIFT (11)
+
+#define PAGE_NS_MASK (0xFFFFFFF7)
+#define PAGE_NS_SHIFT (3)
+
+#define OFFSET_1M (0x00100000)
+#define OFFSET_64K (0x00010000)
+#define OFFSET_4K (0x00001000)
+
+#define DESCRIPTOR_FAULT (0x00000000)
+
+/* Attributes enumerations */
+
+/* Region size attributes */
+typedef enum
+{
+ SECTION,
+ PAGE_4k,
+ PAGE_64k,
+} mmu_region_size_Type;
+
+/* Region type attributes */
+typedef enum
+{
+ NORMAL,
+ DEVICE,
+ SHARED_DEVICE,
+ NON_SHARED_DEVICE,
+ STRONGLY_ORDERED
+} mmu_memory_Type;
+
+/* Region cacheability attributes */
+typedef enum
+{
+ NON_CACHEABLE,
+ WB_WA,
+ WT,
+ WB_NO_WA,
+} mmu_cacheability_Type;
+
+/* Region parity check attributes */
+typedef enum
+{
+ ECC_DISABLED,
+ ECC_ENABLED,
+} mmu_ecc_check_Type;
+
+/* Region execution attributes */
+typedef enum
+{
+ EXECUTE,
+ NON_EXECUTE,
+} mmu_execute_Type;
+
+/* Region global attributes */
+typedef enum
+{
+ GLOBAL,
+ NON_GLOBAL,
+} mmu_global_Type;
+
+/* Region shareability attributes */
+typedef enum
+{
+ NON_SHARED,
+ SHARED,
+} mmu_shared_Type;
+
+/* Region security attributes */
+typedef enum
+{
+ SECURE,
+ NON_SECURE,
+} mmu_secure_Type;
+
+/* Region access attributes */
+typedef enum
+{
+ NO_ACCESS,
+ RW,
+ READ,
+} mmu_access_Type;
+
+/* Memory Region definition */
+typedef struct RegionStruct {
+ mmu_region_size_Type rg_t;
+ mmu_memory_Type mem_t;
+ uint8_t domain;
+ mmu_cacheability_Type inner_norm_t;
+ mmu_cacheability_Type outer_norm_t;
+ mmu_ecc_check_Type e_t;
+ mmu_execute_Type xn_t;
+ mmu_global_Type g_t;
+ mmu_secure_Type sec_t;
+ mmu_access_Type priv_t;
+ mmu_access_Type user_t;
+ mmu_shared_Type sh_t;
+
+} mmu_region_attributes_Type;
+
+//Following macros define the descriptors and attributes
+//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
+#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
+#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
+#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RO. Sect_Normal_Cod, but not executable
+#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
+#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
+#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RW. Sect_Device_RO, but writeable
+#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Page_4k_Device_RW. Shared device, not executable, rw, domain 0
+#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = SHARED_DEVICE; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+//Page_64k_Device_RW. Shared device, not executable, rw, domain 0
+#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = SHARED_DEVICE; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+/** \brief Set section execution-never attribute
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
+{
+ *descriptor_l1 &= SECTION_XN_MASK;
+ *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
+ return 0;
+}
+
+/** \brief Set section domain
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] domain Section domain
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
+{
+ *descriptor_l1 &= SECTION_DOMAIN_MASK;
+ *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
+ return 0;
+}
+
+/** \brief Set section parity check
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+ *descriptor_l1 &= SECTION_P_MASK;
+ *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+ return 0;
+}
+
+/** \brief Set section access privileges
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] user User Level Access: NO_ACCESS, RW, READ
+ \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
+ \param [in] afe Access flag enable
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+ uint32_t ap = 0;
+
+ if (afe == 0) { //full access
+ if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+ else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
+ else if ((priv == RW) && (user == READ)) { ap = 0x2; }
+ else if ((priv == RW) && (user == RW)) { ap = 0x3; }
+ else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+ else if ((priv == READ) && (user == READ)) { ap = 0x7; }
+ }
+
+ else { //Simplified access
+ if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
+ else if ((priv == RW) && (user == RW)) { ap = 0x3; }
+ else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+ else if ((priv == READ) && (user == READ)) { ap = 0x7; }
+ }
+
+ *descriptor_l1 &= SECTION_AP_MASK;
+ *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
+ *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
+
+ return 0;
+}
+
+/** \brief Set section shareability
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] s_bit Section shareability: NON_SHARED, SHARED
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
+{
+ *descriptor_l1 &= SECTION_S_MASK;
+ *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
+ return 0;
+}
+
+/** \brief Set section Global attribute
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
+{
+ *descriptor_l1 &= SECTION_NG_MASK;
+ *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
+ return 0;
+}
+
+/** \brief Set section Security attribute
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+ *descriptor_l1 &= SECTION_NS_MASK;
+ *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
+ return 0;
+}
+
+/* Page 4k or 64k */
+/** \brief Set 4k/64k page execution-never attribute
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
+ \param [in] page Page size: PAGE_4k, PAGE_64k,
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
+{
+ if (page == PAGE_4k)
+ {
+ *descriptor_l2 &= PAGE_XN_4K_MASK;
+ *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
+ }
+ else
+ {
+ *descriptor_l2 &= PAGE_XN_64K_MASK;
+ *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
+ }
+ return 0;
+}
+
+/** \brief Set 4k/64k page domain
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] domain Page domain
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
+{
+ *descriptor_l1 &= PAGE_DOMAIN_MASK;
+ *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
+ return 0;
+}
+
+/** \brief Set 4k/64k page parity check
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+ *descriptor_l1 &= SECTION_P_MASK;
+ *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+ return 0;
+}
+
+/** \brief Set 4k/64k page access privileges
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] user User Level Access: NO_ACCESS, RW, READ
+ \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
+ \param [in] afe Access flag enable
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+ uint32_t ap = 0;
+
+ if (afe == 0) { //full access
+ if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+ else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
+ else if ((priv == RW) && (user == READ)) { ap = 0x2; }
+ else if ((priv == RW) && (user == RW)) { ap = 0x3; }
+ else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+ else if ((priv == READ) && (user == READ)) { ap = 0x6; }
+ }
+
+ else { //Simplified access
+ if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
+ else if ((priv == RW) && (user == RW)) { ap = 0x3; }
+ else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+ else if ((priv == READ) && (user == READ)) { ap = 0x7; }
+ }
+
+ *descriptor_l2 &= PAGE_AP_MASK;
+ *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
+ *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
+
+ return 0;
+}
+
+/** \brief Set 4k/64k page shareability
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
+{
+ *descriptor_l2 &= PAGE_S_MASK;
+ *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
+ return 0;
+}
+
+/** \brief Set 4k/64k page Global attribute
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
+{
+ *descriptor_l2 &= PAGE_NG_MASK;
+ *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
+ return 0;
+}
+
+/** \brief Set 4k/64k page Security attribute
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+ *descriptor_l1 &= PAGE_NS_MASK;
+ *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
+ return 0;
+}
+
+/** \brief Set Section memory attributes
+
+ \param [out] descriptor_l1 L1 descriptor.
+ \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+ \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+ \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
+{
+ *descriptor_l1 &= SECTION_TEXCB_MASK;
+
+ if (STRONGLY_ORDERED == mem)
+ {
+ return 0;
+ }
+ else if (SHARED_DEVICE == mem)
+ {
+ *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+ }
+ else if (NON_SHARED_DEVICE == mem)
+ {
+ *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
+ }
+ else if (NORMAL == mem)
+ {
+ *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
+ switch(inner)
+ {
+ case NON_CACHEABLE:
+ break;
+ case WB_WA:
+ *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+ break;
+ case WT:
+ *descriptor_l1 |= 1 << SECTION_C_SHIFT;
+ break;
+ case WB_NO_WA:
+ *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
+ break;
+ }
+ switch(outer)
+ {
+ case NON_CACHEABLE:
+ break;
+ case WB_WA:
+ *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
+ break;
+ case WT:
+ *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
+ break;
+ case WB_NO_WA:
+ *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
+ break;
+ }
+ }
+ return 0;
+}
+
+/** \brief Set 4k/64k page memory attributes
+
+ \param [out] descriptor_l2 L2 descriptor.
+ \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+ \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+ \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+ \param [in] page Page size
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
+{
+ *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
+
+ if (page == PAGE_64k)
+ {
+ //same as section
+ MMU_MemorySection(descriptor_l2, mem, outer, inner);
+ }
+ else
+ {
+ if (STRONGLY_ORDERED == mem)
+ {
+ return 0;
+ }
+ else if (SHARED_DEVICE == mem)
+ {
+ *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+ }
+ else if (NON_SHARED_DEVICE == mem)
+ {
+ *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
+ }
+ else if (NORMAL == mem)
+ {
+ *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
+ switch(inner)
+ {
+ case NON_CACHEABLE:
+ break;
+ case WB_WA:
+ *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+ break;
+ case WT:
+ *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
+ break;
+ case WB_NO_WA:
+ *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
+ break;
+ }
+ switch(outer)
+ {
+ case NON_CACHEABLE:
+ break;
+ case WB_WA:
+ *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
+ break;
+ case WT:
+ *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
+ break;
+ case WB_NO_WA:
+ *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/** \brief Create a L1 section descriptor
+
+ \param [out] descriptor L1 descriptor
+ \param [in] reg Section attributes
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
+{
+ *descriptor = 0;
+
+ MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
+ MMU_XNSection(descriptor,reg.xn_t);
+ MMU_DomainSection(descriptor, reg.domain);
+ MMU_PSection(descriptor, reg.e_t);
+ MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
+ MMU_SharedSection(descriptor,reg.sh_t);
+ MMU_GlobalSection(descriptor,reg.g_t);
+ MMU_SecureSection(descriptor,reg.sec_t);
+ *descriptor &= SECTION_MASK;
+ *descriptor |= SECTION_DESCRIPTOR;
+
+ return 0;
+}
+
+
+/** \brief Create a L1 and L2 4k/64k page descriptor
+
+ \param [out] descriptor L1 descriptor
+ \param [out] descriptor2 L2 descriptor
+ \param [in] reg 4k/64k page attributes
+
+ \return 0
+*/
+__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
+{
+ *descriptor = 0;
+ *descriptor2 = 0;
+
+ switch (reg.rg_t)
+ {
+ case PAGE_4k:
+ MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
+ MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
+ MMU_DomainPage(descriptor, reg.domain);
+ MMU_PPage(descriptor, reg.e_t);
+ MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+ MMU_SharedPage(descriptor2,reg.sh_t);
+ MMU_GlobalPage(descriptor2,reg.g_t);
+ MMU_SecurePage(descriptor,reg.sec_t);
+ *descriptor &= PAGE_L1_MASK;
+ *descriptor |= PAGE_L1_DESCRIPTOR;
+ *descriptor2 &= PAGE_L2_4K_MASK;
+ *descriptor2 |= PAGE_L2_4K_DESC;
+ break;
+
+ case PAGE_64k:
+ MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
+ MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
+ MMU_DomainPage(descriptor, reg.domain);
+ MMU_PPage(descriptor, reg.e_t);
+ MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+ MMU_SharedPage(descriptor2,reg.sh_t);
+ MMU_GlobalPage(descriptor2,reg.g_t);
+ MMU_SecurePage(descriptor,reg.sec_t);
+ *descriptor &= PAGE_L1_MASK;
+ *descriptor |= PAGE_L1_DESCRIPTOR;
+ *descriptor2 &= PAGE_L2_64K_MASK;
+ *descriptor2 |= PAGE_L2_64K_DESC;
+ break;
+
+ case SECTION:
+ //error
+ break;
+ }
+
+ return 0;
+}
+
+/** \brief Create a 1MB Section
+
+ \param [in] ttb Translation table base address
+ \param [in] base_address Section base address
+ \param [in] count Number of sections to create
+ \param [in] descriptor_l1 L1 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
+{
+ uint32_t offset;
+ uint32_t entry;
+ uint32_t i;
+
+ offset = base_address >> 20;
+ entry = (base_address & 0xFFF00000) | descriptor_l1;
+
+ //4 bytes aligned
+ ttb = ttb + offset;
+
+ for (i = 0; i < count; i++ )
+ {
+ //4 bytes aligned
+ *ttb++ = entry;
+ entry += OFFSET_1M;
+ }
+}
+
+/** \brief Create a 4k page entry
+
+ \param [in] ttb L1 table base address
+ \param [in] base_address 4k base address
+ \param [in] count Number of 4k pages to create
+ \param [in] descriptor_l1 L1 descriptor (region attributes)
+ \param [in] ttb_l2 L2 table base address
+ \param [in] descriptor_l2 L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+
+ uint32_t offset, offset2;
+ uint32_t entry, entry2;
+ uint32_t i;
+
+ offset = base_address >> 20;
+ entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+ //4 bytes aligned
+ ttb += offset;
+ //create l1_entry
+ *ttb = entry;
+
+ offset2 = (base_address & 0xff000) >> 12;
+ ttb_l2 += offset2;
+ entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
+ for (i = 0; i < count; i++ )
+ {
+ //4 bytes aligned
+ *ttb_l2++ = entry2;
+ entry2 += OFFSET_4K;
+ }
+}
+
+/** \brief Create a 64k page entry
+
+ \param [in] ttb L1 table base address
+ \param [in] base_address 64k base address
+ \param [in] count Number of 64k pages to create
+ \param [in] descriptor_l1 L1 descriptor (region attributes)
+ \param [in] ttb_l2 L2 table base address
+ \param [in] descriptor_l2 L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+ uint32_t offset, offset2;
+ uint32_t entry, entry2;
+ uint32_t i,j;
+
+
+ offset = base_address >> 20;
+ entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+ //4 bytes aligned
+ ttb += offset;
+ //create l1_entry
+ *ttb = entry;
+
+ offset2 = (base_address & 0xff000) >> 12;
+ ttb_l2 += offset2;
+ entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
+ for (i = 0; i < count; i++ )
+ {
+ //create 16 entries
+ for (j = 0; j < 16; j++)
+ {
+ //4 bytes aligned
+ *ttb_l2++ = entry2;
+ }
+ entry2 += OFFSET_64K;
+ }
+}
+
+/** \brief Enable MMU
+*/
+__STATIC_INLINE void MMU_Enable(void)
+{
+ // Set M bit 0 to enable the MMU
+ // Set AFE bit to enable simplified access permissions model
+ // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+ __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+ __ISB();
+}
+
+/** \brief Disable MMU
+*/
+__STATIC_INLINE void MMU_Disable(void)
+{
+ // Clear M bit 0 to disable the MMU
+ __set_SCTLR( __get_SCTLR() & ~1);
+ __ISB();
+}
+
+/** \brief Invalidate entire unified TLB
+*/
+
+__STATIC_INLINE void MMU_InvalidateTLB(void)
+{
+ __set_TLBIALL(0);
+ __DSB(); //ensure completion of the invalidation
+ __ISB(); //ensure instruction fetch path sees new state
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_A/irq_ctrl.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/cmsis/TARGET_CORTEX_A/irq_ctrl.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,186 @@ +/**************************************************************************//** + * @file irq_ctrl.h + * @brief Interrupt Controller API header file + * @version V1.0.0 + * @date 23. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#include <stdint.h> + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,410 @@
+/**************************************************************************//**
+ * @file irq_ctrl_gic.c
+ * @brief Interrupt controller handling implementation for GIC
+ * @version V1.0.1
+ * @date 9. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#include "irq_ctrl.h"
+
+#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
+
+/// Number of implemented interrupt lines
+#ifndef IRQ_GIC_LINE_COUNT
+#define IRQ_GIC_LINE_COUNT (1020U)
+#endif
+
+static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
+static uint32_t IRQ_ID0;
+
+/// Initialize interrupt controller.
+__WEAK int32_t IRQ_Initialize (void) {
+ uint32_t i;
+
+ for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+ IRQTable[i] = (IRQHandler_t)NULL;
+ }
+ GIC_Enable();
+ return (0);
+}
+
+
+/// Register interrupt handler.
+__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ IRQTable[irqn] = handler;
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Get the registered interrupt handler.
+__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+ IRQHandler_t h;
+
+ // Ignore CPUID field (software generated interrupts)
+ irqn &= 0x3FFU;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ h = IRQTable[irqn];
+ } else {
+ h = (IRQHandler_t)0;
+ }
+
+ return (h);
+}
+
+
+/// Enable interrupt.
+__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_EnableIRQ ((IRQn_Type)irqn);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Disable interrupt.
+__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_DisableIRQ ((IRQn_Type)irqn);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Get interrupt enable state.
+__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+ uint32_t enable;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+ } else {
+ enable = 0U;
+ }
+
+ return (enable);
+}
+
+
+/// Configure interrupt request mode.
+__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+ uint32_t val;
+ uint8_t cfg;
+ uint8_t secure;
+ uint8_t cpu;
+ int32_t status = 0;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ // Check triggering mode
+ val = (mode & IRQ_MODE_TRIG_Msk);
+
+ if (val == IRQ_MODE_TRIG_LEVEL) {
+ cfg = 0x00U;
+ } else if (val == IRQ_MODE_TRIG_EDGE) {
+ cfg = 0x02U;
+ } else {
+ cfg = 0x00U;
+ status = -1;
+ }
+
+ // Check interrupt type
+ val = mode & IRQ_MODE_TYPE_Msk;
+
+ if (val != IRQ_MODE_TYPE_IRQ) {
+ status = -1;
+ }
+
+ // Check interrupt domain
+ val = mode & IRQ_MODE_DOMAIN_Msk;
+
+ if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+ secure = 0U;
+ } else {
+ // Check security extensions support
+ val = GIC_DistributorInfo() & (1UL << 10U);
+
+ if (val != 0U) {
+ // Security extensions are supported
+ secure = 1U;
+ } else {
+ secure = 0U;
+ status = -1;
+ }
+ }
+
+ // Check interrupt CPU targets
+ val = mode & IRQ_MODE_CPU_Msk;
+
+ if (val == IRQ_MODE_CPU_ALL) {
+ cpu = 0xFFU;
+ } else {
+ cpu = val >> IRQ_MODE_CPU_Pos;
+ }
+
+ // Apply configuration if no mode error
+ if (status == 0) {
+ GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+ GIC_SetTarget ((IRQn_Type)irqn, cpu);
+
+ if (secure != 0U) {
+ GIC_SetGroup ((IRQn_Type)irqn, secure);
+ }
+ }
+ }
+
+ return (status);
+}
+
+
+/// Get interrupt mode configuration.
+__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+ uint32_t mode;
+ uint32_t val;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ mode = IRQ_MODE_TYPE_IRQ;
+
+ // Get trigger mode
+ val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+ if ((val & 2U) != 0U) {
+ // Corresponding interrupt is edge triggered
+ mode |= IRQ_MODE_TRIG_EDGE;
+ } else {
+ // Corresponding interrupt is level triggered
+ mode |= IRQ_MODE_TRIG_LEVEL;
+ }
+
+ // Get interrupt CPU targets
+ mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+ } else {
+ mode = IRQ_MODE_ERROR;
+ }
+
+ return (mode);
+}
+
+
+/// Get ID number of current interrupt request (IRQ).
+__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
+ IRQn_ID_t irqn;
+ uint32_t prio;
+
+ /* Dummy read to avoid GIC 390 errata 801120 */
+ GIC_GetHighPendingIRQ();
+
+ irqn = GIC_AcknowledgePending();
+
+ __DSB();
+
+ /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */
+ /* The following workaround code is for a single-core system. It would be */
+ /* different in a multi-core system. */
+ /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
+ /* so unlock it, otherwise service the interrupt as normal. */
+ /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */
+ /* so will not occur here. */
+
+ if ((irqn == 0) || (irqn >= 0x3FE)) {
+ /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
+ prio = GIC_GetPriority((IRQn_Type)0);
+ GIC_SetPriority ((IRQn_Type)0, prio);
+
+ __DSB();
+
+ if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
+ /* If the ID is 0, is active and has not been seen before */
+ IRQ_ID0 = 1U;
+ }
+ /* End of Workaround GIC 390 errata 733075 */
+ }
+
+ return (irqn);
+}
+
+
+/// Get ID number of current fast interrupt request (FIQ).
+__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
+ return ((IRQn_ID_t)-1);
+}
+
+
+/// Signal end of interrupt processing.
+__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+ int32_t status;
+ IRQn_Type irq = (IRQn_Type)irqn;
+
+ irqn &= 0x3FFU;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_EndInterrupt (irq);
+
+ if (irqn == 0) {
+ IRQ_ID0 = 0U;
+ }
+
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Set interrupt pending flag.
+__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_SetPendingIRQ ((IRQn_Type)irqn);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+/// Get interrupt pending flag.
+__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+ uint32_t pending;
+
+ if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+ } else {
+ pending = 0U;
+ }
+
+ return (pending & 1U);
+}
+
+
+/// Clear interrupt pending flag.
+__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+ int32_t status;
+
+ if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Set interrupt priority value.
+__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+ int32_t status;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ GIC_SetPriority ((IRQn_Type)irqn, priority);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Get interrupt priority.
+__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+ uint32_t priority;
+
+ if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+ priority = GIC_GetPriority ((IRQn_Type)irqn);
+ } else {
+ priority = IRQ_PRIORITY_ERROR;
+ }
+
+ return (priority);
+}
+
+
+/// Set priority masking threshold.
+__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
+ GIC_SetInterfacePriorityMask (priority);
+ return (0);
+}
+
+
+/// Get priority masking threshold
+__WEAK uint32_t IRQ_GetPriorityMask (void) {
+ return GIC_GetInterfacePriorityMask();
+}
+
+
+/// Set priority grouping field split point
+__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+ int32_t status;
+
+ if (bits == IRQ_PRIORITY_Msk) {
+ bits = 7U;
+ }
+
+ if (bits < 8U) {
+ GIC_SetBinaryPoint (7U - bits);
+ status = 0;
+ } else {
+ status = -1;
+ }
+
+ return (status);
+}
+
+
+/// Get priority grouping field split point
+__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
+ uint32_t bp;
+
+ bp = GIC_GetBinaryPoint() & 0x07U;
+
+ return (7U - bp);
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/TOOLCHAIN_IAR/cmain.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/TOOLCHAIN_IAR/cmain.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,101 @@ +/************************************************** + * + * Part two of the system initialization code, contains C-level + * initialization, thumb-2 only variant. + * + * $Revision: 59783 $ + * + **************************************************/ +/* Copyright 2008-2017, IAR Systems AB. + This source code is the property of IAR Systems. The source code may only + be used together with the IAR Embedded Workbench. Redistribution and use + in source and binary forms, with or without modification, is permitted + provided that the following conditions are met: + - Redistributions of source code, in whole or in part, must retain the + above copyright notice, this list of conditions and the disclaimer below. + - IAR Systems name may not be used to endorse or promote products + derived from this software without specific prior written permission. + + THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ + +; -------------------------------------------------- +; Module ?cmain, C-level initialization. +; + + + SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2) + SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2) + + SECTION .text:CODE:NOROOT(2) + + PUBLIC __cmain + ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world... + PUBLIC ?main + EXTWEAK __iar_data_init3 + EXTWEAK __iar_argc_argv + EXTERN __low_level_init + EXTERN __call_ctors + EXTERN main + EXTERN exit + EXTERN __iar_dynamic_initialization + EXTERN mbed_sdk_init + EXTERN mbed_main + EXTERN SystemInit + + THUMB +__cmain: +?main: + +; Initialize segments. +; __segment_init and __low_level_init are assumed to use the same +; instruction set and to be reachable by BL from the ICODE segment +; (it is safest to link them in segment ICODE). + + FUNCALL __cmain, __low_level_init + bl __low_level_init + cmp r0,#0 + beq ?l1 + FUNCALL __cmain, __iar_data_init3 + bl __iar_data_init3 + MOVS r0,#0 ; No parameters + FUNCALL __cmain, mbed_sdk_init + BL mbed_sdk_init + MOVS r0,#0 ; No parameters + FUNCALL __cmain, __iar_dynamic_initialization + BL __iar_dynamic_initialization ; C++ dynamic initialization + +?l1: + REQUIRE ?l3 + + SECTION .text:CODE:NOROOT(2) + + PUBLIC _main + PUBLIC _call_main + THUMB + +__iar_init$$done: ; Copy initialization is done + +?l3: +_call_main: + MOVS r0,#0 ; No parameters + FUNCALL __cmain, __iar_argc_argv + BL __iar_argc_argv ; Maybe setup command line + + MOVS r0,#0 ; No parameters + FUNCALL __cmain, mbed_main + BL mbed_main + + FUNCALL __cmain, main + BL main +_main: + FUNCALL __cmain, exit + BL exit + + END
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/arm_math.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/arm_math.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,7190 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_math.h
+ * Description: Public header file for CMSIS DSP Library
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+ * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+ * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+ *
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - ARM_MATH_ARMV8MxL:
+ *
+ * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
+ * on ARMv8M Mainline target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+ *
+ * - __DSP_PRESENT:
+ *
+ * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+ *
+ * <hr>
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ * <hr>
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+ #include "core_armv8mbl.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+ #include "core_armv8mml.h"
+ #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+ #define ARM_MATH_DSP
+ #endif
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#if 0
+ /*
+ * @brief C custom defined PKHBT for unavailable DSP extension
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
+ uint32_t x,
+ uint32_t y,
+ uint32_t leftshift)
+ {
+ return ( ((x ) & 0x0000FFFFUL) |
+ ((y << leftshift) & 0xFFFF0000UL) );
+ }
+
+ /*
+ * @brief C custom defined PKHTB for unavailable DSP extension
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
+ uint32_t x,
+ uint32_t y,
+ uint32_t rightshift)
+ {
+ return ( ((x ) & 0xFFFF0000UL) |
+ ((y >> rightshift) & 0x0000FFFFUL) );
+ }
+#endif
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_armcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_armcc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,870 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_armclang.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_armclang.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1877 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ register uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ register uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ register uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ register uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_compiler.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_compiler.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_gcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_gcc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2088 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.3
+ * @date 16. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ register uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ register uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ register uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ register uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,913 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.5
+ * @date 10. January 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #define __RESTRICT restrict
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_version.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/cmsis_version.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_armv8mbl.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_armv8mbl.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1896 @@
+/**************************************************************************//**
+ * @file core_armv8mbl.h
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MBL
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MBL_REV
+ #define __ARMv8MBL_REV 0x0000U
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_armv8mml.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_armv8mml.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2960 @@
+/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MML_REV
+ #define __ARMv8MML_REV 0x0000U
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm0.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm0.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,888 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.3
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm0plus.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm0plus.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1023 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm23.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm23.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1899 @@
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM23_REV
+ #define __CM23_REV 0x0000U
+ #warning "__CM23_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
+
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm3.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm3.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1933 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V5.0.5
+ * @date 08. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (3U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
+
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm33.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm33.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2963 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.0.5
+ * @date 08. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_PCS_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
+
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm4.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm4.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2118 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.0.5
+ * @date 08. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
+
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm7.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cm7.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2660 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V5.0.5
+ * @date 08. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (7U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
+
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ register uint32_t ccsidr;
+ register uint32_t sets;
+ register uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cmSecureAccess.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_cmSecureAccess.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,201 @@ +/**************************************************************************//** + * @file core_cmSecureAccess.h + * @brief CMSIS Cortex-M Core Secure Access Header File + * @version XXX + * @date 10. June 2016 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2016 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CM_SECURE_ACCESS_H +#define __CORE_CM_SECURE_ACCESS_H + + +/* ########################### Core Secure Access ########################### */ + +#ifdef FEATURE_UVISOR +#include "uvisor-lib/uvisor-lib.h" + +/* Secure uVisor implementation. */ + +/** Set the value at the target address. + * + * Equivalent to: `*address = value`. + * @param address[in] Target address + * @param value[in] Value to write at the address location. + */ +#define SECURE_WRITE(address, value) \ + uvisor_write(public_box, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL) + +/** Get the value at the target address. + * + * @param address[in] Target address + * @returns The value `*address`. + */ +#define SECURE_READ(address) \ + uvisor_read(public_box, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL) + +/** Get the selected bits at the target address. + * + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + * @returns The value `*address & mask`. + */ +#define SECURE_BITS_GET(address, mask) \ + UVISOR_BITS_GET(public_box, UVISOR_RGW_SHARED, address, mask) + +/** Check the selected bits at the target address. + * + * @param address[in] Address at which to check the bits + * @param mask[in] Bits to select out of the target address + * @returns The value `((*address & mask) == mask)`. + */ +#define SECURE_BITS_CHECK(address, mask) \ + UVISOR_BITS_CHECK(public_box, UVISOR_RGW_SHARED, address, mask) + +/** Set the selected bits to 1 at the target address. + * + * Equivalent to: `*address |= mask`. + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + */ +#define SECURE_BITS_SET(address, mask) \ + UVISOR_BITS_SET(public_box, UVISOR_RGW_SHARED, address, mask) + +/** Clear the selected bits at the target address. + * + * Equivalent to: `*address &= ~mask`. + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + */ +#define SECURE_BITS_CLEAR(address, mask) \ + UVISOR_BITS_CLEAR(public_box, UVISOR_RGW_SHARED, address, mask) + +/** Set the selected bits at the target address to the given value. + * + * Equivalent to: `*address = (*address & ~mask) | (value & mask)`. + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + * @param value[in] Value to write at the address location. Note: The value + * must be already shifted to the correct bit position + */ +#define SECURE_BITS_SET_VALUE(address, mask, value) \ + UVISOR_BITS_SET_VALUE(public_box, UVISOR_RGW_SHARED, address, mask, value) + +/** Toggle the selected bits at the target address. + * + * Equivalent to: `*address ^= mask`. + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + */ +#define SECURE_BITS_TOGGLE(address, mask) \ + UVISOR_BITS_TOGGLE(public_box, UVISOR_RGW_SHARED, address, mask) + +#else + +/* Insecure fallback implementation. */ + +/** Set the value at the target address. + * + * Equivalent to: `*address = value`. + * @param address[in] Target address + * @param value[in] Value to write at the address location. + */ +#define SECURE_WRITE(address, value) \ + *(address) = (value) + +/** Get the value at the target address. + * + * @param address[in] Target address + * @returns The value `*address`. + */ +#define SECURE_READ(address) \ + (*(address)) + +/** Get the selected bits at the target address. + * + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + * @returns The value `*address & mask`. + */ +#define SECURE_BITS_GET(address, mask) \ + (*(address) & (mask)) + +/** Check the selected bits at the target address. + * + * @param address[in] Address at which to check the bits + * @param mask[in] Bits to select out of the target address + * @returns The value `((*address & mask) == mask)`. + */ +#define SECURE_BITS_CHECK(address, mask) \ + ((*(address) & (mask)) == (mask)) + +/** Set the selected bits to 1 at the target address. + * + * Equivalent to: `*address |= mask`. + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + */ +#define SECURE_BITS_SET(address, mask) \ + *(address) |= (mask) + +/** Clear the selected bits at the target address. + * + * Equivalent to: `*address &= ~mask`. + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + */ +#define SECURE_BITS_CLEAR(address, mask) \ + *(address) &= ~(mask) + +/** Set the selected bits at the target address to the given value. + * + * Equivalent to: `*address = (*address & ~mask) | (value & mask)`. + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + * @param value[in] Value to write at the address location. Note: The value + * must be already shifted to the correct bit position + */ +#define SECURE_BITS_SET_VALUE(address, mask, value) \ + *(address) = (*(address) & ~(mask)) | ((value) & (mask)) + +/** Toggle the selected bits at the target address. + * + * Equivalent to: `*address ^= mask`. + * @param address[in] Target address + * @param mask[in] Bits to select out of the target address + */ +#define SECURE_BITS_TOGGLE(address, mask) \ + *(address) ^= (mask) + +#endif + +#endif /* __CORE_CM_SECURE_ACCESS_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_sc000.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_sc000.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1016 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V5.0.3
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/core_sc300.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/core_sc300.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1903 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V5.0.3
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/mbed_tz_context.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/mbed_tz_context.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,212 @@
+/******************************************************************************
+ * @file tz_context.c
+ * @brief Context Management for Armv8-M TrustZone - Sample implementation
+ * @version V1.1.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date: 15. October 2016
+ * $Revision: 1.1.0
+ *
+ * Project: TrustZone for ARMv8-M
+ * Title: Context Management for ARMv8-M TrustZone - Sample implementation
+ *
+ *---------------------------------------------------------------------------*/
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "tz_context.h"
+
+/// Number of process slots (threads may call secure library code)
+#ifndef TZ_PROCESS_STACK_SLOTS
+#define TZ_PROCESS_STACK_SLOTS 8U
+#endif
+
+/// Stack size of the secure library code
+#ifndef TZ_PROCESS_STACK_SIZE
+#define TZ_PROCESS_STACK_SIZE 256U
+#endif
+
+typedef struct {
+ uint32_t sp_top; // stack space top
+ uint32_t sp_limit; // stack space limit
+ uint32_t sp; // current stack pointer
+} stack_info_t;
+
+static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
+static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
+static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
+
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_InitContextSystem_S (void) {
+ uint32_t n;
+
+ if (__get_IPSR() == 0U) {
+ return 0U; // Thread Mode
+ }
+
+ for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
+ ProcessStackInfo[n].sp = 0U;
+ ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
+ ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
+ *((uint32_t *)ProcessStackMemory[n]) = n + 1U;
+ }
+ *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
+
+ ProcessStackFreeSlot = 0U;
+
+ // Default process stack pointer and stack limit
+ __set_PSPLIM((uint32_t)ProcessStackMemory);
+ __set_PSP ((uint32_t)ProcessStackMemory);
+
+ // Privileged Thread Mode using PSP
+ __set_CONTROL(0x02U);
+
+ return 1U; // Success
+}
+
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+__attribute__((cmse_nonsecure_entry))
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
+ uint32_t slot;
+
+ (void)module; // Ignore (fixed Stack size)
+
+ if (__get_IPSR() == 0U) {
+ return 0U; // Thread Mode
+ }
+
+ if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
+ return 0U; // No slot available
+ }
+
+ slot = ProcessStackFreeSlot;
+ ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
+
+ ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
+
+ return (slot + 1U);
+}
+
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
+ uint32_t slot;
+
+ if (__get_IPSR() == 0U) {
+ return 0U; // Thread Mode
+ }
+
+ if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+ return 0U; // Invalid ID
+ }
+
+ slot = id - 1U;
+
+ if (ProcessStackInfo[slot].sp == 0U) {
+ return 0U; // Inactive slot
+ }
+ ProcessStackInfo[slot].sp = 0U;
+
+ *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
+ ProcessStackFreeSlot = slot;
+
+ return 1U; // Success
+}
+
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
+ uint32_t slot;
+
+ if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+ return 0U; // Thread Mode or using Main Stack for threads
+ }
+
+ if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+ return 0U; // Invalid ID
+ }
+
+ slot = id - 1U;
+
+ if (ProcessStackInfo[slot].sp == 0U) {
+ return 0U; // Inactive slot
+ }
+
+ // Setup process stack pointer and stack limit
+ __set_PSPLIM(ProcessStackInfo[slot].sp_limit);
+ __set_PSP (ProcessStackInfo[slot].sp);
+
+ return 1U; // Success
+}
+
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
+ uint32_t slot;
+ uint32_t sp;
+
+ if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+ return 0U; // Thread Mode or using Main Stack for threads
+ }
+
+ if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+ return 0U; // Invalid ID
+ }
+
+ slot = id - 1U;
+
+ if (ProcessStackInfo[slot].sp == 0U) {
+ return 0U; // Inactive slot
+ }
+
+ sp = __get_PSP();
+ if ((sp < ProcessStackInfo[slot].sp_limit) ||
+ (sp > ProcessStackInfo[slot].sp_top)) {
+ return 0U; // SP out of range
+ }
+ ProcessStackInfo[slot].sp = sp;
+
+ // Default process stack pointer and stack limit
+ __set_PSPLIM((uint32_t)ProcessStackMemory);
+ __set_PSP ((uint32_t)ProcessStackMemory);
+
+ return 1U; // Success
+}
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/mpu_armv7.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/mpu_armv7.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,197 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
+
+#define ARM_MPU_AP_NONE 0U
+#define ARM_MPU_AP_PRIV 1U
+#define ARM_MPU_AP_URO 2U
+#define ARM_MPU_AP_FULL 3U
+#define ARM_MPU_AP_PRO 5U
+#define ARM_MPU_AP_RO 6U
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (MPU_RASR_ENABLE_Msk))
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/mpu_armv8.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/mpu_armv8.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ ((BASE & MPU_RBAR_BASE_Pos) | \
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/TARGET_CORTEX_M/tz_context.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/cmsis/TARGET_CORTEX_M/tz_context.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include <stdint.h> + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/cmsis/mbed_cmsis_conf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/cmsis/mbed_cmsis_conf.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,35 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2012 ARM Limited + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_CMSIS_CONF_H +#define MBED_CMSIS_CONF_H + +#ifndef MBED_CONF_TZ_PROCESS_STACK_SIZE +#define MBED_CONF_TZ_PROCESS_STACK_SIZE 512 +#endif +#ifndef MBED_CONF_TZ_PROCESS_STACK_SLOTS +#define MBED_CONF_TZ_PROCESS_STACK_SLOTS 8 +#endif + +#define TZ_PROCESS_STACK_SLOTS MBED_CONF_TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SIZE MBED_CONF_TZ_PROCESS_STACK_SIZE + +#endif /* MBED_CMSIS_CONF_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/AnalogIn.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/AnalogIn.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,27 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "drivers/AnalogIn.h"
+
+#if DEVICE_ANALOGIN
+
+namespace mbed {
+
+SingletonPtr<PlatformMutex> AnalogIn::_mutex;
+
+};
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/AnalogIn.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/AnalogIn.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,137 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_H
+#define MBED_ANALOGIN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_ANALOGIN) || defined(DOXYGEN_ONLY)
+
+#include "hal/analogin_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An analog input, used for reading the voltage on a pin
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Print messages when the AnalogIn is greater than 50%
+ *
+ * #include "mbed.h"
+ *
+ * AnalogIn temperature(p20);
+ *
+ * int main() {
+ * while(1) {
+ * if(temperature > 0.5) {
+ * printf("Too hot! (%f)", temperature.read());
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class AnalogIn {
+
+public:
+
+ /** Create an AnalogIn, connected to the specified pin
+ *
+ * @param pin AnalogIn pin to connect to
+ */
+ AnalogIn(PinName pin)
+ {
+ lock();
+ analogin_init(&_adc, pin);
+ unlock();
+ }
+
+ /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @returns A floating-point value representing the current input voltage, measured as a percentage
+ */
+ float read()
+ {
+ lock();
+ float ret = analogin_read(&_adc);
+ unlock();
+ return ret;
+ }
+
+ /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+ *
+ * @returns
+ * 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+ */
+ unsigned short read_u16()
+ {
+ lock();
+ unsigned short ret = analogin_read_u16(&_adc);
+ unlock();
+ return ret;
+ }
+
+ /** An operator shorthand for read()
+ *
+ * The float() operator can be used as a shorthand for read() to simplify common code sequences
+ *
+ * Example:
+ * @code
+ * float x = volume.read();
+ * float x = volume;
+ *
+ * if(volume.read() > 0.25) { ... }
+ * if(volume > 0.25) { ... }
+ * @endcode
+ */
+ operator float()
+ {
+ // Underlying call is thread safe
+ return read();
+ }
+
+ virtual ~AnalogIn()
+ {
+ // Do nothing
+ }
+
+protected:
+
+ virtual void lock()
+ {
+ _mutex->lock();
+ }
+
+ virtual void unlock()
+ {
+ _mutex->unlock();
+ }
+
+ analogin_t _adc;
+ static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/AnalogOut.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/AnalogOut.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,163 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_H
+#define MBED_ANALOGOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_ANALOGOUT) || defined(DOXYGEN_ONLY)
+
+#include "hal/analogout_api.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An analog output, used for setting the voltage on a pin
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Make a sawtooth output
+ *
+ * #include "mbed.h"
+ *
+ * AnalogOut tri(p18);
+ * int main() {
+ * while(1) {
+ * tri = tri + 0.01;
+ * wait_us(1);
+ * if(tri == 1) {
+ * tri = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class AnalogOut {
+
+public:
+
+ /** Create an AnalogOut connected to the specified pin
+ *
+ * @param pin AnalogOut pin to connect to
+ */
+ AnalogOut(PinName pin)
+ {
+ analogout_init(&_dac, pin);
+ }
+
+ /** Set the output voltage, specified as a percentage (float)
+ *
+ * @param value A floating-point value representing the output voltage,
+ * specified as a percentage. The value should lie between
+ * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+ * Values outside this range will be saturated to 0.0f or 1.0f.
+ */
+ void write(float value)
+ {
+ lock();
+ analogout_write(&_dac, value);
+ unlock();
+ }
+
+ /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+ *
+ * @param value 16-bit unsigned short representing the output voltage,
+ * normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+ */
+ void write_u16(unsigned short value)
+ {
+ lock();
+ analogout_write_u16(&_dac, value);
+ unlock();
+ }
+
+ /** Return the current output voltage setting, measured as a percentage (float)
+ *
+ * @returns
+ * A floating-point value representing the current voltage being output on the pin,
+ * measured as a percentage. The returned value will lie between
+ * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+ *
+ * @note
+ * This value may not match exactly the value set by a previous write().
+ */
+ float read()
+ {
+ lock();
+ float ret = analogout_read(&_dac);
+ unlock();
+ return ret;
+ }
+
+ /** An operator shorthand for write()
+ * \sa AnalogOut::write()
+ */
+ AnalogOut &operator= (float percent)
+ {
+ // Underlying write call is thread safe
+ write(percent);
+ return *this;
+ }
+
+ /** An operator shorthand for write()
+ * \sa AnalogOut::write()
+ */
+ AnalogOut &operator= (AnalogOut &rhs)
+ {
+ // Underlying write call is thread safe
+ write(rhs.read());
+ return *this;
+ }
+
+ /** An operator shorthand for read()
+ * \sa AnalogOut::read()
+ */
+ operator float()
+ {
+ // Underlying read call is thread safe
+ return read();
+ }
+
+ virtual ~AnalogOut()
+ {
+ // Do nothing
+ }
+
+protected:
+
+ virtual void lock()
+ {
+ _mutex.lock();
+ }
+
+ virtual void unlock()
+ {
+ _mutex.unlock();
+ }
+
+ dac_t _dac;
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/BusIn.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/BusIn.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/BusIn.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15)
+{
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i = 0; i < 16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusIn::BusIn(PinName pins[16])
+{
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i = 0; i < 16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusIn::~BusIn()
+{
+ // No lock needed in the destructor
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+int BusIn::read()
+{
+ int v = 0;
+ lock();
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ unlock();
+ return v;
+}
+
+void BusIn::mode(PinMode pull)
+{
+ lock();
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->mode(pull);
+ }
+ }
+ unlock();
+}
+
+void BusIn::lock()
+{
+ _mutex.lock();
+}
+
+void BusIn::unlock()
+{
+ _mutex.unlock();
+}
+
+BusIn::operator int()
+{
+ // Underlying read is thread safe
+ return read();
+}
+
+DigitalIn &BusIn::operator[](int index)
+{
+ // No lock needed since _pin is not modified outside the constructor
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/BusIn.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/BusIn.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,128 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSIN_H
+#define MBED_BUSIN_H
+
+#include "platform/platform.h"
+#include "drivers/DigitalIn.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input bus, used for reading the state of a collection of pins
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class BusIn : private NonCopyable<BusIn> {
+
+public:
+ /* Group: Configuration Methods */
+
+ /** Create an BusIn, connected to the specified pins
+ *
+ * @param p0 DigitalIn pin to connect to bus bit
+ * @param p1 DigitalIn pin to connect to bus bit
+ * @param p2 DigitalIn pin to connect to bus bit
+ * @param p3 DigitalIn pin to connect to bus bit
+ * @param p4 DigitalIn pin to connect to bus bit
+ * @param p5 DigitalIn pin to connect to bus bit
+ * @param p6 DigitalIn pin to connect to bus bit
+ * @param p7 DigitalIn pin to connect to bus bit
+ * @param p8 DigitalIn pin to connect to bus bit
+ * @param p9 DigitalIn pin to connect to bus bit
+ * @param p10 DigitalIn pin to connect to bus bit
+ * @param p11 DigitalIn pin to connect to bus bit
+ * @param p12 DigitalIn pin to connect to bus bit
+ * @param p13 DigitalIn pin to connect to bus bit
+ * @param p14 DigitalIn pin to connect to bus bit
+ * @param p15 DigitalIn pin to connect to bus bit
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+
+ /** Create an BusIn, connected to the specified pins
+ *
+ * @param pins An array of pins to connect to bus bit
+ */
+ BusIn(PinName pins[16]);
+
+ virtual ~BusIn();
+
+ /** Read the value of the input bus
+ *
+ * @returns
+ * An integer with each bit corresponding to the value read from the associated DigitalIn pin
+ */
+ int read();
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask()
+ {
+ // No lock needed since _nc_mask is not modified outside the constructor
+ return _nc_mask;
+ }
+
+ /** A shorthand for read()
+ * \sa DigitalIn::read()
+ */
+ operator int();
+
+ /** Access to particular bit in random-iterator fashion
+ * @param index Position of bit
+ */
+ DigitalIn &operator[](int index);
+
+protected:
+ DigitalIn *_pin[16];
+
+ /* Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ PlatformMutex _mutex;
+
+private:
+ virtual void lock();
+ virtual void unlock();
+};
+
+} // namespace mbed
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/BusInOut.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/BusInOut.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,152 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/BusInOut.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15)
+{
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i = 0; i < 16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusInOut::BusInOut(PinName pins[16])
+{
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i = 0; i < 16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusInOut::~BusInOut()
+{
+ // No lock needed in the destructor
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+void BusInOut::write(int value)
+{
+ lock();
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->write((value >> i) & 1);
+ }
+ }
+ unlock();
+}
+
+int BusInOut::read()
+{
+ lock();
+ int v = 0;
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ unlock();
+ return v;
+}
+
+void BusInOut::output()
+{
+ lock();
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->output();
+ }
+ }
+ unlock();
+}
+
+void BusInOut::input()
+{
+ lock();
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->input();
+ }
+ }
+ unlock();
+}
+
+void BusInOut::mode(PinMode pull)
+{
+ lock();
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->mode(pull);
+ }
+ }
+ unlock();
+}
+
+BusInOut &BusInOut::operator= (int v)
+{
+ // Underlying write is thread safe
+ write(v);
+ return *this;
+}
+
+BusInOut &BusInOut::operator= (BusInOut &rhs)
+{
+ // Underlying read is thread safe
+ write(rhs.read());
+ return *this;
+}
+
+DigitalInOut &BusInOut::operator[](int index)
+{
+ // No lock needed since _pin is not modified outside the constructor
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+BusInOut::operator int()
+{
+ // Underlying read is thread safe
+ return read();
+}
+
+void BusInOut::lock()
+{
+ _mutex.lock();
+}
+
+void BusInOut::unlock()
+{
+ _mutex.unlock();
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/BusInOut.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/BusInOut.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,144 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSINOUT_H
+#define MBED_BUSINOUT_H
+
+#include "drivers/DigitalInOut.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input output bus, used for setting the state of a collection of pins
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class BusInOut : private NonCopyable<BusInOut> {
+
+public:
+
+ /** Create an BusInOut, connected to the specified pins
+ *
+ * @param p0 DigitalInOut pin to connect to bus bit
+ * @param p1 DigitalInOut pin to connect to bus bit
+ * @param p2 DigitalInOut pin to connect to bus bit
+ * @param p3 DigitalInOut pin to connect to bus bit
+ * @param p4 DigitalInOut pin to connect to bus bit
+ * @param p5 DigitalInOut pin to connect to bus bit
+ * @param p6 DigitalInOut pin to connect to bus bit
+ * @param p7 DigitalInOut pin to connect to bus bit
+ * @param p8 DigitalInOut pin to connect to bus bit
+ * @param p9 DigitalInOut pin to connect to bus bit
+ * @param p10 DigitalInOut pin to connect to bus bit
+ * @param p11 DigitalInOut pin to connect to bus bit
+ * @param p12 DigitalInOut pin to connect to bus bit
+ * @param p13 DigitalInOut pin to connect to bus bit
+ * @param p14 DigitalInOut pin to connect to bus bit
+ * @param p15 DigitalInOut pin to connect to bus bit
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ /** Create an BusInOut, connected to the specified pins
+ *
+ * @param pins An array of pins to construct a BusInOut from
+ */
+ BusInOut(PinName pins[16]);
+
+ virtual ~BusInOut();
+
+ /* Group: Access Methods */
+
+ /** Write the value to the output bus
+ *
+ * @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
+ */
+ void write(int value);
+
+ /** Read the value currently output on the bus
+ *
+ * @returns
+ * An integer with each bit corresponding to associated DigitalInOut pin setting
+ */
+ int read();
+
+ /** Set as an output
+ */
+ void output();
+
+ /** Set as an input
+ */
+ void input();
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask()
+ {
+ // No lock needed since _nc_mask is not modified outside the constructor
+ return _nc_mask;
+ }
+
+ /** A shorthand for write()
+ * \sa BusInOut::write()
+ */
+ BusInOut &operator= (int v);
+ BusInOut &operator= (BusInOut &rhs);
+
+ /** Access to particular bit in random-iterator fashion
+ * @param index Bit Position
+ */
+ DigitalInOut &operator[](int index);
+
+ /** A shorthand for read()
+ * \sa BusInOut::read()
+ */
+ operator int();
+
+protected:
+ virtual void lock();
+ virtual void unlock();
+ DigitalInOut *_pin[16];
+
+ /* Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/BusOut.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/BusOut.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/BusOut.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15)
+{
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i = 0; i < 16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusOut::BusOut(PinName pins[16])
+{
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i = 0; i < 16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusOut::~BusOut()
+{
+ // No lock needed in the destructor
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+void BusOut::write(int value)
+{
+ lock();
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->write((value >> i) & 1);
+ }
+ }
+ unlock();
+}
+
+int BusOut::read()
+{
+ lock();
+ int v = 0;
+ for (int i = 0; i < 16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ unlock();
+ return v;
+}
+
+BusOut &BusOut::operator= (int v)
+{
+ // Underlying write is thread safe
+ write(v);
+ return *this;
+}
+
+BusOut &BusOut::operator= (BusOut &rhs)
+{
+ // Underlying write is thread safe
+ write(rhs.read());
+ return *this;
+}
+
+DigitalOut &BusOut::operator[](int index)
+{
+ // No lock needed since _pin is not modified outside the constructor
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+BusOut::operator int()
+{
+ // Underlying read is thread safe
+ return read();
+}
+
+void BusOut::lock()
+{
+ _mutex.lock();
+}
+
+void BusOut::unlock()
+{
+ _mutex.unlock();
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/BusOut.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/BusOut.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,128 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSOUT_H
+#define MBED_BUSOUT_H
+
+#include "drivers/DigitalOut.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital output bus, used for setting the state of a collection of pins
+ * @ingroup drivers
+ */
+class BusOut : private NonCopyable<BusOut> {
+
+public:
+
+ /** Create an BusOut, connected to the specified pins
+ *
+ * @param p0 DigitalOut pin to connect to bus bit
+ * @param p1 DigitalOut pin to connect to bus bit
+ * @param p2 DigitalOut pin to connect to bus bit
+ * @param p3 DigitalOut pin to connect to bus bit
+ * @param p4 DigitalOut pin to connect to bus bit
+ * @param p5 DigitalOut pin to connect to bus bit
+ * @param p6 DigitalOut pin to connect to bus bit
+ * @param p7 DigitalOut pin to connect to bus bit
+ * @param p8 DigitalOut pin to connect to bus bit
+ * @param p9 DigitalOut pin to connect to bus bit
+ * @param p10 DigitalOut pin to connect to bus bit
+ * @param p11 DigitalOut pin to connect to bus bit
+ * @param p12 DigitalOut pin to connect to bus bit
+ * @param p13 DigitalOut pin to connect to bus bit
+ * @param p14 DigitalOut pin to connect to bus bit
+ * @param p15 DigitalOut pin to connect to bus bit
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ /** Create an BusOut, connected to the specified pins
+ *
+ * @param pins An array of pins to connect to bus the bit
+ */
+ BusOut(PinName pins[16]);
+
+ virtual ~BusOut();
+
+ /** Write the value to the output bus
+ *
+ * @param value An integer specifying a bit to write for every corresponding DigitalOut pin
+ */
+ void write(int value);
+
+ /** Read the value currently output on the bus
+ *
+ * @returns
+ * An integer with each bit corresponding to associated DigitalOut pin setting
+ */
+ int read();
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask()
+ {
+ // No lock needed since _nc_mask is not modified outside the constructor
+ return _nc_mask;
+ }
+
+ /** A shorthand for write()
+ * \sa BusOut::write()
+ */
+ BusOut &operator= (int v);
+ BusOut &operator= (BusOut &rhs);
+
+ /** Access to particular bit in random-iterator fashion
+ * @param index Bit Position
+ */
+ DigitalOut &operator[](int index);
+
+ /** A shorthand for read()
+ * \sa BusOut::read()
+ */
+ operator int();
+
+protected:
+ virtual void lock();
+ virtual void unlock();
+ DigitalOut *_pin[16];
+
+ /* Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/CAN.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/CAN.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,172 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/CAN.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+#include "platform/mbed_power_mgmt.h"
+
+namespace mbed {
+
+CAN::CAN(PinName rd, PinName td) : _can(), _irq()
+{
+ // No lock needed in constructor
+
+ for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
+ _irq[i] = NULL;
+ }
+
+ can_init(&_can, rd, td);
+ can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::CAN(PinName rd, PinName td, int hz) : _can(), _irq()
+{
+ // No lock needed in constructor
+
+ for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
+ _irq[i] = NULL;
+ }
+
+ can_init_freq(&_can, rd, td, hz);
+ can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::~CAN()
+{
+ // No lock needed in destructor
+
+ // Detaching interrupts releases the sleep lock if it was locked
+ for (int irq = 0; irq < IrqCnt; irq++) {
+ attach(NULL, (IrqType)irq);
+ }
+ can_irq_free(&_can);
+ can_free(&_can);
+}
+
+int CAN::frequency(int f)
+{
+ lock();
+ int ret = can_frequency(&_can, f);
+ unlock();
+ return ret;
+}
+
+int CAN::write(CANMessage msg)
+{
+ lock();
+ int ret = can_write(&_can, msg, 0);
+ unlock();
+ return ret;
+}
+
+int CAN::read(CANMessage &msg, int handle)
+{
+ lock();
+ int ret = can_read(&_can, &msg, handle);
+ unlock();
+ return ret;
+}
+
+void CAN::reset()
+{
+ lock();
+ can_reset(&_can);
+ unlock();
+}
+
+unsigned char CAN::rderror()
+{
+ lock();
+ int ret = can_rderror(&_can);
+ unlock();
+ return ret;
+}
+
+unsigned char CAN::tderror()
+{
+ lock();
+ int ret = can_tderror(&_can);
+ unlock();
+ return ret;
+}
+
+void CAN::monitor(bool silent)
+{
+ lock();
+ can_monitor(&_can, (silent) ? 1 : 0);
+ unlock();
+}
+
+int CAN::mode(Mode mode)
+{
+ lock();
+ int ret = can_mode(&_can, (CanMode)mode);
+ unlock();
+ return ret;
+}
+
+int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle)
+{
+ lock();
+ int ret = can_filter(&_can, id, mask, format, handle);
+ unlock();
+ return ret;
+}
+
+void CAN::attach(Callback<void()> func, IrqType type)
+{
+ lock();
+ if (func) {
+ // lock deep sleep only the first time
+ if (!_irq[(CanIrqType)type]) {
+ sleep_manager_lock_deep_sleep();
+ }
+ _irq[(CanIrqType)type] = func;
+ can_irq_set(&_can, (CanIrqType)type, 1);
+ } else {
+ // unlock deep sleep only the first time
+ if (_irq[(CanIrqType)type]) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ _irq[(CanIrqType)type] = NULL;
+ can_irq_set(&_can, (CanIrqType)type, 0);
+ }
+ unlock();
+}
+
+void CAN::_irq_handler(uint32_t id, CanIrqType type)
+{
+ CAN *handler = (CAN *)id;
+ if (handler->_irq[type]) {
+ handler->_irq[type].call();
+ }
+}
+
+void CAN::lock()
+{
+ _mutex.lock();
+}
+
+void CAN::unlock()
+{
+ _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/CAN.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/CAN.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,304 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_CAN) || defined(DOXYGEN_ONLY)
+
+#include "hal/can_api.h"
+#include "platform/Callback.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** CANMessage class
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class CANMessage : public CAN_Message {
+
+public:
+ /** Creates empty CAN message.
+ */
+ CANMessage() : CAN_Message()
+ {
+ len = 8;
+ type = CANData;
+ format = CANStandard;
+ id = 0;
+ memset(data, 0, 8);
+ }
+
+ /** Creates CAN message with specific content.
+ *
+ * @param _id Message ID
+ * @param _data Mesaage Data
+ * @param _len Message Data length
+ * @param _type Type of Data: Use enum CANType for valid parameter values
+ * @param _format Data Format: Use enum CANFormat for valid parameter values
+ */
+ CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard)
+ {
+ len = _len & 0xF;
+ type = _type;
+ format = _format;
+ id = _id;
+ memcpy(data, _data, _len);
+ }
+
+ /** Creates CAN remote message.
+ *
+ * @param _id Message ID
+ * @param _format Data Format: Use enum CANType for valid parameter values
+ */
+ CANMessage(int _id, CANFormat _format = CANStandard)
+ {
+ len = 0;
+ type = CANRemote;
+ format = _format;
+ id = _id;
+ memset(data, 0, 8);
+ }
+};
+
+/** A can bus client, used for communicating with can devices
+ * @ingroup drivers
+ */
+class CAN : private NonCopyable<CAN> {
+
+public:
+ /** Creates an CAN interface connected to specific pins.
+ *
+ * @param rd read from transmitter
+ * @param td transmit to transmitter
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * Ticker ticker;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ * CAN can1(p9, p10);
+ * CAN can2(p30, p29);
+ *
+ * char counter = 0;
+ *
+ * void send() {
+ * if(can1.write(CANMessage(1337, &counter, 1))) {
+ * printf("Message sent: %d\n", counter);
+ * counter++;
+ * }
+ * led1 = !led1;
+ * }
+ *
+ * int main() {
+ * ticker.attach(&send, 1);
+ * CANMessage msg;
+ * while(1) {
+ * if(can2.read(msg)) {
+ * printf("Message received: %d\n\n", msg.data[0]);
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+ CAN(PinName rd, PinName td);
+
+ /** Initialize CAN interface and set the frequency
+ *
+ * @param rd the rd pin
+ * @param td the td pin
+ * @param hz the bus frequency in hertz
+ */
+ CAN(PinName rd, PinName td, int hz);
+
+ virtual ~CAN();
+
+ /** Set the frequency of the CAN interface
+ *
+ * @param hz The bus frequency in hertz
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise
+ */
+ int frequency(int hz);
+
+ /** Write a CANMessage to the bus.
+ *
+ * @param msg The CANMessage to write.
+ *
+ * @returns
+ * 0 if write failed,
+ * 1 if write was successful
+ */
+ int write(CANMessage msg);
+
+ /** Read a CANMessage from the bus.
+ *
+ * @param msg A CANMessage to read to.
+ * @param handle message filter handle (0 for any message)
+ *
+ * @returns
+ * 0 if no message arrived,
+ * 1 if message arrived
+ */
+ int read(CANMessage &msg, int handle = 0);
+
+ /** Reset CAN interface.
+ *
+ * To use after error overflow.
+ */
+ void reset();
+
+ /** Puts or removes the CAN interface into silent monitoring mode
+ *
+ * @param silent boolean indicating whether to go into silent mode or not
+ */
+ void monitor(bool silent);
+
+ enum Mode {
+ Reset = 0,
+ Normal,
+ Silent,
+ LocalTest,
+ GlobalTest,
+ SilentTest
+ };
+
+ /** Change CAN operation to the specified mode
+ *
+ * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+ *
+ * @returns
+ * 0 if mode change failed or unsupported,
+ * 1 if mode change was successful
+ */
+ int mode(Mode mode);
+
+ /** Filter out incomming messages
+ *
+ * @param id the id to filter on
+ * @param mask the mask applied to the id
+ * @param format format to filter on (Default CANAny)
+ * @param handle message filter handle (Optional)
+ *
+ * @returns
+ * 0 if filter change failed or unsupported,
+ * new filter handle if successful
+ */
+ int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
+
+ /** Detects read errors - Used to detect read overflow errors.
+ *
+ * @returns number of read errors
+ */
+ unsigned char rderror();
+
+ /** Detects write errors - Used to detect write overflow errors.
+ *
+ * @returns number of write errors
+ */
+ unsigned char tderror();
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq,
+ EwIrq,
+ DoIrq,
+ WuIrq,
+ EpIrq,
+ AlIrq,
+ BeIrq,
+ IdIrq,
+
+ IrqCnt
+ };
+
+ /** Attach a function to call whenever a CAN frame received interrupt is
+ * generated.
+ *
+ * This function locks the deep sleep while a callback is attached
+ *
+ * @param func A pointer to a void function, or 0 to set as none
+ * @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+ */
+ void attach(Callback<void()> func, IrqType type = RxIrq);
+
+ /** Attach a member function to call whenever a CAN frame received interrupt
+ * is generated.
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), type).
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), type).")
+ void attach(T *obj, void (T::*method)(), IrqType type = RxIrq)
+ {
+ // Underlying call thread safe
+ attach(callback(obj, method), type);
+ }
+
+ /** Attach a member function to call whenever a CAN frame received interrupt
+ * is generated.
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), type).
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), type).")
+ void attach(T *obj, void (*method)(T *), IrqType type = RxIrq)
+ {
+ // Underlying call thread safe
+ attach(callback(obj, method), type);
+ }
+
+ static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+ virtual void lock();
+ virtual void unlock();
+ can_t _can;
+ Callback<void()> _irq[IrqCnt];
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif // MBED_CAN_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/DigitalIn.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/DigitalIn.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALIN_H
+#define MBED_DIGITALIN_H
+
+#include "platform/platform.h"
+
+#include "hal/gpio_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input, used for reading the state of a pin
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Flash an LED while a DigitalIn is true
+ *
+ * #include "mbed.h"
+ *
+ * DigitalIn enable(p5);
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * if(enable) {
+ * led = !led;
+ * }
+ * wait(0.25);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class DigitalIn {
+
+public:
+ /** Create a DigitalIn connected to the specified pin
+ *
+ * @param pin DigitalIn pin to connect to
+ */
+ DigitalIn(PinName pin) : gpio()
+ {
+ // No lock needed in the constructor
+ gpio_init_in(&gpio, pin);
+ }
+
+ /** Create a DigitalIn connected to the specified pin
+ *
+ * @param pin DigitalIn pin to connect to
+ * @param mode the initial mode of the pin
+ */
+ DigitalIn(PinName pin, PinMode mode) : gpio()
+ {
+ // No lock needed in the constructor
+ gpio_init_in_ex(&gpio, pin, mode);
+ }
+ /** Read the input, represented as 0 or 1 (int)
+ *
+ * @returns
+ * An integer representing the state of the input pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read()
+ {
+ // Thread safe / atomic HAL call
+ return gpio_read(&gpio);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode pull)
+ {
+ core_util_critical_section_enter();
+ gpio_mode(&gpio, pull);
+ core_util_critical_section_exit();
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected()
+ {
+ // Thread safe / atomic HAL call
+ return gpio_is_connected(&gpio);
+ }
+
+ /** An operator shorthand for read()
+ * \sa DigitalIn::read()
+ */
+ operator int()
+ {
+ // Underlying read is thread safe
+ return read();
+ }
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/DigitalInOut.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/DigitalInOut.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALINOUT_H
+#define MBED_DIGITALINOUT_H
+
+#include "platform/platform.h"
+
+#include "hal/gpio_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input/output, used for setting or reading a bi-directional pin
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class DigitalInOut {
+
+public:
+ /** Create a DigitalInOut connected to the specified pin
+ *
+ * @param pin DigitalInOut pin to connect to
+ */
+ DigitalInOut(PinName pin) : gpio()
+ {
+ // No lock needed in the constructor
+ gpio_init_in(&gpio, pin);
+ }
+
+ /** Create a DigitalInOut connected to the specified pin
+ *
+ * @param pin DigitalInOut pin to connect to
+ * @param direction the initial direction of the pin
+ * @param mode the initial mode of the pin
+ * @param value the initial value of the pin if is an output
+ */
+ DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio()
+ {
+ // No lock needed in the constructor
+ gpio_init_inout(&gpio, pin, direction, mode, value);
+ }
+
+ /** Set the output, specified as 0 or 1 (int)
+ *
+ * @param value An integer specifying the pin output value,
+ * 0 for logical 0, 1 (or any other non-zero value) for logical 1
+ */
+ void write(int value)
+ {
+ // Thread safe / atomic HAL call
+ gpio_write(&gpio, value);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * an integer representing the output setting of the pin if it is an output,
+ * or read the input if set as an input
+ */
+ int read()
+ {
+ // Thread safe / atomic HAL call
+ return gpio_read(&gpio);
+ }
+
+ /** Set as an output
+ */
+ void output()
+ {
+ core_util_critical_section_enter();
+ gpio_dir(&gpio, PIN_OUTPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Set as an input
+ */
+ void input()
+ {
+ core_util_critical_section_enter();
+ gpio_dir(&gpio, PIN_INPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode pull)
+ {
+ core_util_critical_section_enter();
+ gpio_mode(&gpio, pull);
+ core_util_critical_section_exit();
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected()
+ {
+ // Thread safe / atomic HAL call
+ return gpio_is_connected(&gpio);
+ }
+
+ /** A shorthand for write()
+ * \sa DigitalInOut::write()
+ */
+ DigitalInOut &operator= (int value)
+ {
+ // Underlying write is thread safe
+ write(value);
+ return *this;
+ }
+
+ /** A shorthand for write()
+ * \sa DigitalInOut::write()
+ */
+ DigitalInOut &operator= (DigitalInOut &rhs)
+ {
+ core_util_critical_section_enter();
+ write(rhs.read());
+ core_util_critical_section_exit();
+ return *this;
+ }
+
+ /** A shorthand for read()
+ * \sa DigitalInOut::read()
+ */
+ operator int()
+ {
+ // Underlying call is thread safe
+ return read();
+ }
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/DigitalOut.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/DigitalOut.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,141 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALOUT_H
+#define MBED_DIGITALOUT_H
+
+#include "platform/platform.h"
+#include "hal/gpio_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital output, used for setting the state of a pin
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle a LED
+ * #include "mbed.h"
+ *
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * led = !led;
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class DigitalOut {
+
+public:
+ /** Create a DigitalOut connected to the specified pin
+ *
+ * @param pin DigitalOut pin to connect to
+ */
+ DigitalOut(PinName pin) : gpio()
+ {
+ // No lock needed in the constructor
+ gpio_init_out(&gpio, pin);
+ }
+
+ /** Create a DigitalOut connected to the specified pin
+ *
+ * @param pin DigitalOut pin to connect to
+ * @param value the initial pin value
+ */
+ DigitalOut(PinName pin, int value) : gpio()
+ {
+ // No lock needed in the constructor
+ gpio_init_out_ex(&gpio, pin, value);
+ }
+
+ /** Set the output, specified as 0 or 1 (int)
+ *
+ * @param value An integer specifying the pin output value,
+ * 0 for logical 0, 1 (or any other non-zero value) for logical 1
+ */
+ void write(int value)
+ {
+ // Thread safe / atomic HAL call
+ gpio_write(&gpio, value);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * an integer representing the output setting of the pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read()
+ {
+ // Thread safe / atomic HAL call
+ return gpio_read(&gpio);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected()
+ {
+ // Thread safe / atomic HAL call
+ return gpio_is_connected(&gpio);
+ }
+
+ /** A shorthand for write()
+ * \sa DigitalOut::write()
+ */
+ DigitalOut &operator= (int value)
+ {
+ // Underlying write is thread safe
+ write(value);
+ return *this;
+ }
+
+ /** A shorthand for write()
+ * \sa DigitalOut::write()
+ */
+ DigitalOut &operator= (DigitalOut &rhs)
+ {
+ core_util_critical_section_enter();
+ write(rhs.read());
+ core_util_critical_section_exit();
+ return *this;
+ }
+
+ /** A shorthand for read()
+ * \sa DigitalOut::read()
+ */
+ operator int()
+ {
+ // Underlying call is thread safe
+ return read();
+ }
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Ethernet.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Ethernet.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,97 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Ethernet.h"
+
+#if DEVICE_ETHERNET
+
+#include "hal/ethernet_api.h"
+
+namespace mbed {
+
+Ethernet::Ethernet()
+{
+ ethernet_init();
+}
+
+Ethernet::~Ethernet()
+{
+ ethernet_free();
+}
+
+int Ethernet::write(const char *data, int size)
+{
+ return ethernet_write(data, size);
+}
+
+int Ethernet::send()
+{
+ return ethernet_send();
+}
+
+int Ethernet::receive()
+{
+ return ethernet_receive();
+}
+
+int Ethernet::read(char *data, int size)
+{
+ return ethernet_read(data, size);
+}
+
+void Ethernet::address(char *mac)
+{
+ return ethernet_address(mac);
+}
+
+int Ethernet::link()
+{
+ return ethernet_link();
+}
+
+void Ethernet::set_link(Mode mode)
+{
+ int speed = -1;
+ int duplex = 0;
+
+ switch (mode) {
+ case AutoNegotiate :
+ speed = -1;
+ duplex = 0;
+ break;
+ case HalfDuplex10 :
+ speed = 0;
+ duplex = 0;
+ break;
+ case FullDuplex10 :
+ speed = 0;
+ duplex = 1;
+ break;
+ case HalfDuplex100 :
+ speed = 1;
+ duplex = 0;
+ break;
+ case FullDuplex100 :
+ speed = 1;
+ duplex = 1;
+ break;
+ }
+
+ ethernet_set_link(speed, duplex);
+}
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Ethernet.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Ethernet.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,176 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_H
+#define MBED_ETHERNET_H
+
+#include "platform/platform.h"
+#include "platform/NonCopyable.h"
+
+#if defined (DEVICE_ETHERNET) || defined(DOXYGEN_ONLY)
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An ethernet interface, to use with the ethernet pins.
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Read destination and source from every ethernet packet
+ *
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ * char buf[0x600];
+ *
+ * while(1) {
+ * int size = eth.receive();
+ * if(size > 0) {
+ * eth.read(buf, size);
+ * printf("Destination: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ * buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ * printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ * buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
+ * }
+ *
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Ethernet : private NonCopyable<Ethernet> {
+
+public:
+
+ /** Initialise the ethernet interface.
+ */
+ Ethernet();
+
+ /** Powers the hardware down.
+ */
+ virtual ~Ethernet();
+
+ enum Mode {
+ AutoNegotiate,
+ HalfDuplex10,
+ FullDuplex10,
+ HalfDuplex100,
+ FullDuplex100
+ };
+
+ /** Writes into an outgoing ethernet packet.
+ *
+ * It will append size bytes of data to the previously written bytes.
+ *
+ * @param data An array to write.
+ * @param size The size of data.
+ *
+ * @returns
+ * The number of written bytes.
+ */
+ int write(const char *data, int size);
+
+ /** Send an outgoing ethernet packet.
+ *
+ * After filling in the data in an ethernet packet it must be send.
+ * Send will provide a new packet to write to.
+ *
+ * @returns
+ * 0 if the sending was failed,
+ * or the size of the packet successfully sent.
+ */
+ int send();
+
+ /** Receives an arrived ethernet packet.
+ *
+ * Receiving an ethernet packet will drop the last received ethernet packet
+ * and make a new ethernet packet ready to read.
+ * If no ethernet packet is arrived it will return 0.
+ *
+ * @returns
+ * 0 if no ethernet packet is arrived,
+ * or the size of the arrived packet.
+ */
+ int receive();
+
+ /** Read from an received ethernet packet.
+ *
+ * After receive returned a number bigger than 0 it is
+ * possible to read bytes from this packet.
+ *
+ * @param data Pointer to data packet
+ * @param size Size of data to be read.
+ * @returns The number of byte read.
+ *
+ * @note It is possible to use read multiple times.
+ * Each time read will start reading after the last read byte before.
+ *
+ */
+ int read(char *data, int size);
+
+ /** Gives the ethernet address of the mbed.
+ *
+ * @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
+ */
+ void address(char *mac);
+
+ /** Returns if an ethernet link is present or not. It takes a while after Ethernet initialization to show up.
+ *
+ * @returns
+ * 0 if no ethernet link is present,
+ * 1 if an ethernet link is present.
+ *
+ * Example:
+ * @code
+ * // Using the Ethernet link function
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ * wait(1); // Needed after startup.
+ * if (eth.link()) {
+ * printf("online\n");
+ * } else {
+ * printf("offline\n");
+ * }
+ * }
+ * @endcode
+ */
+ int link();
+
+ /** Sets the speed and duplex parameters of an ethernet link
+ *
+ * - AutoNegotiate Auto negotiate speed and duplex
+ * - HalfDuplex10 10 Mbit, half duplex
+ * - FullDuplex10 10 Mbit, full duplex
+ * - HalfDuplex100 100 Mbit, half duplex
+ * - FullDuplex100 100 Mbit, full duplex
+ *
+ * @param mode the speed and duplex mode to set the link to:
+ */
+ void set_link(Mode mode);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/FlashIAP.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/FlashIAP.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,208 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <algorithm>
+#include "FlashIAP.h"
+#include "mbed_assert.h"
+
+
+#ifdef DEVICE_FLASH
+
+namespace mbed {
+
+SingletonPtr<PlatformMutex> FlashIAP::_mutex;
+
+static inline bool is_aligned(uint32_t number, uint32_t alignment)
+{
+ if ((number % alignment) != 0) {
+ return false;
+ } else {
+ return true;
+ }
+}
+
+FlashIAP::FlashIAP()
+{
+
+}
+
+FlashIAP::~FlashIAP()
+{
+
+}
+
+int FlashIAP::init()
+{
+ int ret = 0;
+ _mutex->lock();
+ if (flash_init(&_flash)) {
+ ret = -1;
+ }
+ uint32_t page_size = get_page_size();
+ _page_buf = new uint8_t[page_size];
+
+ _mutex->unlock();
+ return ret;
+}
+
+int FlashIAP::deinit()
+{
+ int ret = 0;
+ _mutex->lock();
+ if (flash_free(&_flash)) {
+ ret = -1;
+ }
+ delete[] _page_buf;
+ _mutex->unlock();
+ return ret;
+}
+
+
+int FlashIAP::read(void *buffer, uint32_t addr, uint32_t size)
+{
+ int32_t ret = -1;
+ _mutex->lock();
+ ret = flash_read(&_flash, addr, (uint8_t *) buffer, size);
+ _mutex->unlock();
+ return ret;
+}
+
+int FlashIAP::program(const void *buffer, uint32_t addr, uint32_t size)
+{
+ uint32_t page_size = get_page_size();
+ uint32_t flash_size = flash_get_size(&_flash);
+ uint32_t flash_start_addr = flash_get_start_address(&_flash);
+ uint32_t chunk, prog_size;
+ const uint8_t *buf = (uint8_t *) buffer;
+ const uint8_t *prog_buf;
+
+ // addr should be aligned to page size
+ if (!is_aligned(addr, page_size) || (!buffer) ||
+ ((addr + size) > (flash_start_addr + flash_size))) {
+ return -1;
+ }
+
+ int ret = 0;
+ _mutex->lock();
+ while (size) {
+ uint32_t current_sector_size = flash_get_sector_size(&_flash, addr);
+ bool unaligned_src = (((size_t) buf / sizeof(uint32_t) * sizeof(uint32_t)) != (size_t) buf);
+ chunk = std::min(current_sector_size - (addr % current_sector_size), size);
+ // Need to use the internal page buffer in any of these two cases:
+ // 1. Size is not page aligned
+ // 2. Source buffer is not aligned to uint32_t. This is not supported by many targets (although
+ // the pointer they accept is of uint8_t).
+ if (unaligned_src || (chunk < page_size)) {
+ chunk = std::min(chunk, page_size);
+ memcpy(_page_buf, buf, chunk);
+ if (chunk < page_size) {
+ memset(_page_buf + chunk, 0xFF, page_size - chunk);
+ }
+ prog_buf = _page_buf;
+ prog_size = page_size;
+ } else {
+ chunk = chunk / page_size * page_size;
+ prog_buf = buf;
+ prog_size = chunk;
+ }
+ if (flash_program_page(&_flash, addr, prog_buf, prog_size)) {
+ ret = -1;
+ break;
+ }
+ size -= chunk;
+ addr += chunk;
+ buf += chunk;
+ }
+ _mutex->unlock();
+
+ return ret;
+}
+
+bool FlashIAP::is_aligned_to_sector(uint32_t addr, uint32_t size)
+{
+ uint32_t current_sector_size = flash_get_sector_size(&_flash, addr);
+ if (!is_aligned(size, current_sector_size) ||
+ !is_aligned(addr, current_sector_size)) {
+ return false;
+ } else {
+ return true;
+ }
+}
+
+int FlashIAP::erase(uint32_t addr, uint32_t size)
+{
+ uint32_t current_sector_size;
+ uint32_t flash_size = flash_get_size(&_flash);
+ uint32_t flash_start_addr = flash_get_start_address(&_flash);
+ uint32_t flash_end_addr = flash_start_addr + flash_size;
+ uint32_t erase_end_addr = addr + size;
+
+ if (erase_end_addr > flash_end_addr) {
+ return -1;
+ } else if (erase_end_addr < flash_end_addr) {
+ uint32_t following_sector_size = flash_get_sector_size(&_flash, erase_end_addr);
+ if (!is_aligned(erase_end_addr, following_sector_size)) {
+ return -1;
+ }
+ }
+
+ int32_t ret = 0;
+ _mutex->lock();
+ while (size) {
+ ret = flash_erase_sector(&_flash, addr);
+ if (ret != 0) {
+ ret = -1;
+ break;
+ }
+ current_sector_size = flash_get_sector_size(&_flash, addr);
+ size -= current_sector_size;
+ addr += current_sector_size;
+ }
+ _mutex->unlock();
+ return ret;
+}
+
+uint32_t FlashIAP::get_page_size() const
+{
+ return flash_get_page_size(&_flash);
+}
+
+uint32_t FlashIAP::get_sector_size(uint32_t addr) const
+{
+ return flash_get_sector_size(&_flash, addr);
+}
+
+uint32_t FlashIAP::get_flash_start() const
+{
+ return flash_get_start_address(&_flash);
+}
+
+uint32_t FlashIAP::get_flash_size() const
+{
+ return flash_get_size(&_flash);
+}
+
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/FlashIAP.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/FlashIAP.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FLASHIAP_H
+#define MBED_FLASHIAP_H
+
+#if defined (DEVICE_FLASH) || defined(DOXYGEN_ONLY)
+
+#include "flash_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+
+/** \addtogroup drivers */
+
+/** Flash IAP driver. It invokes flash HAL functions.
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class FlashIAP : private NonCopyable<FlashIAP> {
+public:
+ FlashIAP();
+ ~FlashIAP();
+
+ /** Initialize a flash IAP device
+ *
+ * Should be called once per lifetime of the object.
+ * @return 0 on success or a negative error code on failure
+ */
+ int init();
+
+ /** Deinitialize a flash IAP device
+ *
+ * @return 0 on success or a negative error code on failure
+ */
+ int deinit();
+
+ /** Read data from a flash device.
+ *
+ * This method invokes memcpy - reads number of bytes from the address
+ *
+ * @param buffer Buffer to write to
+ * @param addr Flash address to begin reading from
+ * @param size Size to read in bytes
+ * @return 0 on success, negative error code on failure
+ */
+ int read(void *buffer, uint32_t addr, uint32_t size);
+
+ /** Program data to pages
+ *
+ * The sectors must have been erased prior to being programmed
+ *
+ * @param buffer Buffer of data to be written
+ * @param addr Address of a page to begin writing to
+ * @param size Size to write in bytes, must be a multiple of program size
+ * @return 0 on success, negative error code on failure
+ */
+ int program(const void *buffer, uint32_t addr, uint32_t size);
+
+ /** Erase sectors
+ *
+ * The state of an erased sector is undefined until it has been programmed
+ *
+ * @param addr Address of a sector to begin erasing, must be a multiple of the sector size
+ * @param size Size to erase in bytes, must be a multiple of the sector size
+ * @return 0 on success, negative error code on failure
+ */
+ int erase(uint32_t addr, uint32_t size);
+
+ /** Get the sector size at the defined address
+ *
+ * Sector size might differ at address ranges.
+ * An example <0-0x1000, sector size=1024; 0x10000-0x20000, size=2048>
+ *
+ * @param addr Address of or inside the sector to query
+ * @return Size of a sector in bytes or MBED_FLASH_INVALID_SIZE if not mapped
+ */
+ uint32_t get_sector_size(uint32_t addr) const;
+
+ /** Get the flash start address
+ *
+ * @return Flash start address
+ */
+ uint32_t get_flash_start() const;
+
+ /** Get the flash size
+ *
+ * @return Flash size
+ */
+ uint32_t get_flash_size() const;
+
+ /** Get the program page size
+ *
+ * The page size defines the writable page size
+ * @return Size of a program page in bytes
+ */
+ uint32_t get_page_size() const;
+
+private:
+
+ /* Check if address and size are aligned to a sector
+ *
+ * @param addr Address of block to check for alignment
+ * @param size Size of block to check for alignment
+ * @return true if the block is sector aligned, false otherwise
+ */
+ bool is_aligned_to_sector(uint32_t addr, uint32_t size);
+
+ flash_t _flash;
+ uint8_t *_page_buf;
+ static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} /* namespace mbed */
+
+#endif /* DEVICE_FLASH */
+
+#endif /* MBED_FLASHIAP_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/I2C.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/I2C.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,198 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/I2C.h"
+
+#if DEVICE_I2C
+
+#if DEVICE_I2C_ASYNCH
+#include "platform/mbed_power_mgmt.h"
+#endif
+
+namespace mbed {
+
+I2C *I2C::_owner = NULL;
+SingletonPtr<PlatformMutex> I2C::_mutex;
+
+I2C::I2C(PinName sda, PinName scl) :
+#if DEVICE_I2C_ASYNCH
+ _irq(this), _usage(DMA_USAGE_NEVER), _deep_sleep_locked(false),
+#endif
+ _i2c(), _hz(100000)
+{
+ // No lock needed in the constructor
+
+ // The init function also set the frequency to 100000
+ i2c_init(&_i2c, sda, scl);
+
+ // Used to avoid unnecessary frequency updates
+ _owner = this;
+}
+
+void I2C::frequency(int hz)
+{
+ lock();
+ _hz = hz;
+
+ // We want to update the frequency even if we are already the bus owners
+ i2c_frequency(&_i2c, _hz);
+
+ // Updating the frequency of the bus we become the owners of it
+ _owner = this;
+ unlock();
+}
+
+void I2C::aquire()
+{
+ lock();
+ if (_owner != this) {
+ i2c_frequency(&_i2c, _hz);
+ _owner = this;
+ }
+ unlock();
+}
+
+// write - Master Transmitter Mode
+int I2C::write(int address, const char *data, int length, bool repeated)
+{
+ lock();
+ aquire();
+
+ int stop = (repeated) ? 0 : 1;
+ int written = i2c_write(&_i2c, address, data, length, stop);
+
+ unlock();
+ return length != written;
+}
+
+int I2C::write(int data)
+{
+ lock();
+ int ret = i2c_byte_write(&_i2c, data);
+ unlock();
+ return ret;
+}
+
+// read - Master Receiver Mode
+int I2C::read(int address, char *data, int length, bool repeated)
+{
+ lock();
+ aquire();
+
+ int stop = (repeated) ? 0 : 1;
+ int read = i2c_read(&_i2c, address, data, length, stop);
+
+ unlock();
+ return length != read;
+}
+
+int I2C::read(int ack)
+{
+ lock();
+ int ret;
+ if (ack) {
+ ret = i2c_byte_read(&_i2c, 0);
+ } else {
+ ret = i2c_byte_read(&_i2c, 1);
+ }
+ unlock();
+ return ret;
+}
+
+void I2C::start(void)
+{
+ lock();
+ i2c_start(&_i2c);
+ unlock();
+}
+
+void I2C::stop(void)
+{
+ lock();
+ i2c_stop(&_i2c);
+ unlock();
+}
+
+void I2C::lock()
+{
+ _mutex->lock();
+}
+
+void I2C::unlock()
+{
+ _mutex->unlock();
+}
+
+#if DEVICE_I2C_ASYNCH
+
+int I2C::transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t &callback, int event, bool repeated)
+{
+ lock();
+ if (i2c_active(&_i2c)) {
+ unlock();
+ return -1; // transaction ongoing
+ }
+ lock_deep_sleep();
+ aquire();
+
+ _callback = callback;
+ int stop = (repeated) ? 0 : 1;
+ _irq.callback(&I2C::irq_handler_asynch);
+ i2c_transfer_asynch(&_i2c, (void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length, address, stop, _irq.entry(), event, _usage);
+ unlock();
+ return 0;
+}
+
+void I2C::abort_transfer(void)
+{
+ lock();
+ i2c_abort_asynch(&_i2c);
+ unlock_deep_sleep();
+ unlock();
+}
+
+void I2C::irq_handler_asynch(void)
+{
+ int event = i2c_irq_handler_asynch(&_i2c);
+ if (_callback && event) {
+ _callback.call(event);
+ }
+ if (event) {
+ unlock_deep_sleep();
+ }
+
+}
+
+void I2C::lock_deep_sleep()
+{
+ if (_deep_sleep_locked == false) {
+ sleep_manager_lock_deep_sleep();
+ _deep_sleep_locked = true;
+ }
+}
+
+void I2C::unlock_deep_sleep()
+{
+ if (_deep_sleep_locked == true) {
+ sleep_manager_unlock_deep_sleep();
+ _deep_sleep_locked = false;
+ }
+}
+
+#endif
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/I2C.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/I2C.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,208 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_H
+#define MBED_I2C_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_I2C) || defined(DOXYGEN_ONLY)
+
+#include "hal/i2c_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+#if DEVICE_I2C_ASYNCH
+#include "platform/CThunk.h"
+#include "hal/dma_api.h"
+#include "platform/FunctionPointer.h"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An I2C Master, used for communicating with I2C slave devices
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Read from I2C slave at address 0x62
+ *
+ * #include "mbed.h"
+ *
+ * I2C i2c(p28, p27);
+ *
+ * int main() {
+ * int address = 0x62;
+ * char data[2];
+ * i2c.read(address, data, 2);
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class I2C : private NonCopyable<I2C> {
+
+public:
+ enum RxStatus {
+ NoData,
+ MasterGeneralCall,
+ MasterWrite,
+ MasterRead
+ };
+
+ enum Acknowledge {
+ NoACK = 0,
+ ACK = 1
+ };
+
+ /** Create an I2C Master interface, connected to the specified pins
+ *
+ * @param sda I2C data line pin
+ * @param scl I2C clock line pin
+ */
+ I2C(PinName sda, PinName scl);
+
+ /** Set the frequency of the I2C interface
+ *
+ * @param hz The bus frequency in hertz
+ */
+ void frequency(int hz);
+
+ /** Read from an I2C slave
+ *
+ * Performs a complete read transaction. The bottom bit of
+ * the address is forced to 1 to indicate a read.
+ *
+ * @param address 8-bit I2C slave address [ addr | 1 ]
+ * @param data Pointer to the byte-array to read data in to
+ * @param length Number of bytes to read
+ * @param repeated Repeated start, true - don't send stop at end
+ *
+ * @returns
+ * 0 on success (ack),
+ * non-0 on failure (nack)
+ */
+ int read(int address, char *data, int length, bool repeated = false);
+
+ /** Read a single byte from the I2C bus
+ *
+ * @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
+ *
+ * @returns
+ * the byte read
+ */
+ int read(int ack);
+
+ /** Write to an I2C slave
+ *
+ * Performs a complete write transaction. The bottom bit of
+ * the address is forced to 0 to indicate a write.
+ *
+ * @param address 8-bit I2C slave address [ addr | 0 ]
+ * @param data Pointer to the byte-array data to send
+ * @param length Number of bytes to send
+ * @param repeated Repeated start, true - do not send stop at end
+ *
+ * @returns
+ * 0 on success (ack),
+ * non-0 on failure (nack)
+ */
+ int write(int address, const char *data, int length, bool repeated = false);
+
+ /** Write single byte out on the I2C bus
+ *
+ * @param data data to write out on bus
+ *
+ * @returns
+ * '0' - NAK was received
+ * '1' - ACK was received,
+ * '2' - timeout
+ */
+ int write(int data);
+
+ /** Creates a start condition on the I2C bus
+ */
+
+ void start(void);
+
+ /** Creates a stop condition on the I2C bus
+ */
+ void stop(void);
+
+ /** Acquire exclusive access to this I2C bus
+ */
+ virtual void lock(void);
+
+ /** Release exclusive access to this I2C bus
+ */
+ virtual void unlock(void);
+
+ virtual ~I2C()
+ {
+ // Do nothing
+ }
+
+#if DEVICE_I2C_ASYNCH
+
+ /** Start non-blocking I2C transfer.
+ *
+ * This function locks the deep sleep until any event has occurred
+ *
+ * @param address 8/10 bit I2C slave address
+ * @param tx_buffer The TX buffer with data to be transfered
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data
+ * @param rx_length The length of RX buffer in bytes
+ * @param event The logical OR of events to modify
+ * @param callback The event callback function
+ * @param repeated Repeated start, true - do not send stop at end
+ * @return Zero if the transfer has started, or -1 if I2C peripheral is busy
+ */
+ int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t &callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);
+
+ /** Abort the on-going I2C transfer
+ */
+ void abort_transfer();
+
+protected:
+ /** Lock deep sleep only if it is not yet locked */
+ void lock_deep_sleep();
+
+ /** Unlock deep sleep only if it has been locked */
+ void unlock_deep_sleep();
+
+ void irq_handler_asynch(void);
+ event_callback_t _callback;
+ CThunk<I2C> _irq;
+ DMAUsage _usage;
+ bool _deep_sleep_locked;
+#endif
+
+protected:
+ void aquire();
+
+ i2c_t _i2c;
+ static I2C *_owner;
+ int _hz;
+ static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/I2CSlave.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/I2CSlave.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,72 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/I2CSlave.h"
+
+#if DEVICE_I2CSLAVE
+
+namespace mbed {
+
+I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c()
+{
+ i2c_init(&_i2c, sda, scl);
+ i2c_frequency(&_i2c, 100000);
+ i2c_slave_mode(&_i2c, 1);
+}
+
+void I2CSlave::frequency(int hz)
+{
+ i2c_frequency(&_i2c, hz);
+}
+
+void I2CSlave::address(int address)
+{
+ int addr = (address & 0xFF) | 1;
+ i2c_slave_address(&_i2c, 0, addr, 0);
+}
+
+int I2CSlave::receive(void)
+{
+ return i2c_slave_receive(&_i2c);
+}
+
+int I2CSlave::read(char *data, int length)
+{
+ return i2c_slave_read(&_i2c, data, length) != length;
+}
+
+int I2CSlave::read(void)
+{
+ return i2c_byte_read(&_i2c, 0);
+}
+
+int I2CSlave::write(const char *data, int length)
+{
+ return i2c_slave_write(&_i2c, data, length) != length;
+}
+
+int I2CSlave::write(int data)
+{
+ return i2c_byte_write(&_i2c, data);
+}
+
+void I2CSlave::stop(void)
+{
+ i2c_stop(&_i2c);
+}
+
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/I2CSlave.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/I2CSlave.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_SLAVE_H
+#define MBED_I2C_SLAVE_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_I2CSLAVE) || defined(DOXYGEN_ONLY)
+
+#include "hal/i2c_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An I2C Slave, used for communicating with an I2C Master device
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Simple I2C responder
+ * #include <mbed.h>
+ *
+ * I2CSlave slave(p9, p10);
+ *
+ * int main() {
+ * char buf[10];
+ * char msg[] = "Slave!";
+ *
+ * slave.address(0xA0);
+ * while (1) {
+ * int i = slave.receive();
+ * switch (i) {
+ * case I2CSlave::ReadAddressed:
+ * slave.write(msg, strlen(msg) + 1); // Includes null char
+ * break;
+ * case I2CSlave::WriteGeneral:
+ * slave.read(buf, 10);
+ * printf("Read G: %s\n", buf);
+ * break;
+ * case I2CSlave::WriteAddressed:
+ * slave.read(buf, 10);
+ * printf("Read A: %s\n", buf);
+ * break;
+ * }
+ * for(int i = 0; i < 10; i++) buf[i] = 0; // Clear buffer
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class I2CSlave {
+
+public:
+ enum RxStatus {
+ NoData = 0,
+ ReadAddressed = 1,
+ WriteGeneral = 2,
+ WriteAddressed = 3
+ };
+
+ /** Create an I2C Slave interface, connected to the specified pins.
+ *
+ * @param sda I2C data line pin
+ * @param scl I2C clock line pin
+ */
+ I2CSlave(PinName sda, PinName scl);
+
+ /** Set the frequency of the I2C interface
+ *
+ * @param hz The bus frequency in hertz
+ */
+ void frequency(int hz);
+
+ /** Checks to see if this I2C Slave has been addressed.
+ *
+ * @returns
+ * A status indicating if the device has been addressed, and how
+ * - NoData - the slave has not been addressed
+ * - ReadAddressed - the master has requested a read from this slave
+ * - WriteAddressed - the master is writing to this slave
+ * - WriteGeneral - the master is writing to all slave
+ */
+ int receive(void);
+
+ /** Read from an I2C master.
+ *
+ * @param data pointer to the byte array to read data in to
+ * @param length maximum number of bytes to read
+ *
+ * @returns
+ * 0 on success,
+ * non-0 otherwise
+ */
+ int read(char *data, int length);
+
+ /** Read a single byte from an I2C master.
+ *
+ * @returns
+ * the byte read
+ */
+ int read(void);
+
+ /** Write to an I2C master.
+ *
+ * @param data pointer to the byte array to be transmitted
+ * @param length the number of bytes to transmite
+ *
+ * @returns
+ * 0 on success,
+ * non-0 otherwise
+ */
+ int write(const char *data, int length);
+
+ /** Write a single byte to an I2C master.
+ *
+ * @param data the byte to write
+ *
+ * @returns
+ * '1' if an ACK was received,
+ * '0' otherwise
+ */
+ int write(int data);
+
+ /** Sets the I2C slave address.
+ *
+ * @param address The address to set for the slave (ignoring the least
+ * signifcant bit). If set to 0, the slave will only respond to the
+ * general call address.
+ */
+ void address(int address);
+
+ /** Reset the I2C slave back into the known ready receiving state.
+ */
+ void stop(void);
+
+protected:
+ i2c_t _i2c;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/InterruptIn.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/InterruptIn.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,138 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/InterruptIn.h"
+
+#if DEVICE_INTERRUPTIN
+
+namespace mbed {
+
+// Note: This single-parameter constructor exists to maintain binary
+// compatibility.
+// If not for that, we could simplify by having only the 2-param
+// constructor, with a default value for the PinMode.
+InterruptIn::InterruptIn(PinName pin) : gpio(),
+ gpio_irq(),
+ _rise(NULL),
+ _fall(NULL)
+{
+ // No lock needed in the constructor
+ irq_init(pin);
+ gpio_init_in(&gpio, pin);
+}
+
+InterruptIn::InterruptIn(PinName pin, PinMode mode) :
+ gpio(),
+ gpio_irq(),
+ _rise(NULL),
+ _fall(NULL)
+{
+ // No lock needed in the constructor
+ irq_init(pin);
+ gpio_init_in_ex(&gpio, pin, mode);
+}
+
+void InterruptIn::irq_init(PinName pin)
+{
+ gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
+}
+
+InterruptIn::~InterruptIn()
+{
+ // No lock needed in the destructor
+ gpio_irq_free(&gpio_irq);
+}
+
+int InterruptIn::read()
+{
+ // Read only
+ return gpio_read(&gpio);
+}
+
+void InterruptIn::mode(PinMode pull)
+{
+ core_util_critical_section_enter();
+ gpio_mode(&gpio, pull);
+ core_util_critical_section_exit();
+}
+
+void InterruptIn::rise(Callback<void()> func)
+{
+ core_util_critical_section_enter();
+ if (func) {
+ _rise = func;
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ } else {
+ _rise = NULL;
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+ }
+ core_util_critical_section_exit();
+}
+
+void InterruptIn::fall(Callback<void()> func)
+{
+ core_util_critical_section_enter();
+ if (func) {
+ _fall = func;
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ } else {
+ _fall = NULL;
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+ }
+ core_util_critical_section_exit();
+}
+
+void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event)
+{
+ InterruptIn *handler = (InterruptIn *)id;
+ switch (event) {
+ case IRQ_RISE:
+ if (handler->_rise) {
+ handler->_rise();
+ }
+ break;
+ case IRQ_FALL:
+ if (handler->_fall) {
+ handler->_fall();
+ }
+ break;
+ case IRQ_NONE:
+ break;
+ }
+}
+
+void InterruptIn::enable_irq()
+{
+ core_util_critical_section_enter();
+ gpio_irq_enable(&gpio_irq);
+ core_util_critical_section_exit();
+}
+
+void InterruptIn::disable_irq()
+{
+ core_util_critical_section_enter();
+ gpio_irq_disable(&gpio_irq);
+ core_util_critical_section_exit();
+}
+
+InterruptIn::operator int()
+{
+ // Underlying call is atomic
+ return read();
+}
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/InterruptIn.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/InterruptIn.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,175 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTIN_H
+#define MBED_INTERRUPTIN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY)
+
+#include "hal/gpio_api.h"
+#include "hal/gpio_irq_api.h"
+#include "platform/Callback.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital interrupt input, used to call a function on a rising or falling edge
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Flash an LED while waiting for events
+ *
+ * #include "mbed.h"
+ *
+ * InterruptIn event(p16);
+ * DigitalOut led(LED1);
+ *
+ * void trigger() {
+ * printf("triggered!\n");
+ * }
+ *
+ * int main() {
+ * event.rise(&trigger);
+ * while(1) {
+ * led = !led;
+ * wait(0.25);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class InterruptIn : private NonCopyable<InterruptIn> {
+
+public:
+
+ /** Create an InterruptIn connected to the specified pin
+ *
+ * @param pin InterruptIn pin to connect to
+ */
+ InterruptIn(PinName pin);
+
+ /** Create an InterruptIn connected to the specified pin,
+ * and the pin configured to the specified mode.
+ *
+ * @param pin InterruptIn pin to connect to
+ * @param mode The mode to set the pin to (PullUp/PullDown/etc.)
+ */
+ InterruptIn(PinName pin, PinMode mode);
+
+ virtual ~InterruptIn();
+
+ /** Read the input, represented as 0 or 1 (int)
+ *
+ * @returns
+ * An integer representing the state of the input pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read();
+
+ /** An operator shorthand for read()
+ */
+ operator int();
+
+
+ /** Attach a function to call when a rising edge occurs on the input
+ *
+ * @param func A pointer to a void function, or 0 to set as none
+ */
+ void rise(Callback<void()> func);
+
+ /** Attach a member function to call when a rising edge occurs on the input
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @deprecated
+ * The rise function does not support cv-qualifiers. Replaced by
+ * rise(callback(obj, method)).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The rise function does not support cv-qualifiers. Replaced by "
+ "rise(callback(obj, method)).")
+ void rise(T *obj, M method)
+ {
+ core_util_critical_section_enter();
+ rise(callback(obj, method));
+ core_util_critical_section_exit();
+ }
+
+ /** Attach a function to call when a falling edge occurs on the input
+ *
+ * @param func A pointer to a void function, or 0 to set as none
+ */
+ void fall(Callback<void()> func);
+
+ /** Attach a member function to call when a falling edge occurs on the input
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @deprecated
+ * The rise function does not support cv-qualifiers. Replaced by
+ * rise(callback(obj, method)).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The fall function does not support cv-qualifiers. Replaced by "
+ "fall(callback(obj, method)).")
+ void fall(T *obj, M method)
+ {
+ core_util_critical_section_enter();
+ fall(callback(obj, method));
+ core_util_critical_section_exit();
+ }
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Enable IRQ. This method depends on hw implementation, might enable one
+ * port interrupts. For further information, check gpio_irq_enable().
+ */
+ void enable_irq();
+
+ /** Disable IRQ. This method depends on hw implementation, might disable one
+ * port interrupts. For further information, check gpio_irq_disable().
+ */
+ void disable_irq();
+
+ static void _irq_handler(uint32_t id, gpio_irq_event event);
+
+protected:
+ gpio_t gpio;
+ gpio_irq_t gpio_irq;
+
+ Callback<void()> _rise;
+ Callback<void()> _fall;
+
+ void irq_init(PinName pin);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/InterruptManager.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/InterruptManager.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,157 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#if defined(NVIC_NUM_VECTORS)
+
+// Suppress deprecation warnings since this whole
+// class is deprecated already
+#include "mbed_toolchain.h"
+#undef MBED_DEPRECATED_SINCE
+#define MBED_DEPRECATED_SINCE(...)
+
+#include "drivers/InterruptManager.h"
+#include "platform/mbed_critical.h"
+#include <string.h>
+
+#define CHAIN_INITIAL_SIZE 4
+
+namespace mbed {
+
+typedef void (*pvoidf)(void);
+
+InterruptManager *InterruptManager::_instance = (InterruptManager *)NULL;
+
+InterruptManager *InterruptManager::get()
+{
+
+ if (NULL == _instance) {
+ InterruptManager *temp = new InterruptManager();
+
+ // Atomically set _instance
+ core_util_critical_section_enter();
+ if (NULL == _instance) {
+ _instance = temp;
+ }
+ core_util_critical_section_exit();
+
+ // Another thread got there first so delete ours
+ if (temp != _instance) {
+ delete temp;
+ }
+
+ }
+ return _instance;
+}
+
+InterruptManager::InterruptManager()
+{
+ // No mutex needed in constructor
+ memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain *));
+}
+
+void InterruptManager::destroy()
+{
+ // Not a good idea to call this unless NO interrupt at all
+ // is under the control of the handler; otherwise, a system crash
+ // is very likely to occur
+ if (NULL != _instance) {
+ delete _instance;
+ _instance = (InterruptManager *)NULL;
+ }
+}
+
+InterruptManager::~InterruptManager()
+{
+ for (int i = 0; i < NVIC_NUM_VECTORS; i++)
+ if (NULL != _chains[i]) {
+ delete _chains[i];
+ }
+}
+
+bool InterruptManager::must_replace_vector(IRQn_Type irq)
+{
+ lock();
+
+ int ret = false;
+ int irq_pos = get_irq_index(irq);
+ if (NULL == _chains[irq_pos]) {
+ _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
+ _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
+ ret = true;
+ }
+ unlock();
+ return ret;
+}
+
+pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front)
+{
+ lock();
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
+ if (change) {
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ }
+ unlock();
+ return pf;
+}
+
+bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq)
+{
+ int irq_pos = get_irq_index(irq);
+ bool ret = false;
+
+ lock();
+ if (_chains[irq_pos] != NULL) {
+ if (_chains[irq_pos]->remove(handler)) {
+ ret = true;
+ }
+ }
+ unlock();
+
+ return ret;
+}
+
+void InterruptManager::irq_helper()
+{
+ _chains[__get_IPSR()]->call();
+}
+
+int InterruptManager::get_irq_index(IRQn_Type irq)
+{
+ // Pure function - no lock needed
+ return (int)irq + NVIC_USER_IRQ_OFFSET;
+}
+
+void InterruptManager::static_irq_helper()
+{
+ InterruptManager::get()->irq_helper();
+}
+
+void InterruptManager::lock()
+{
+ _mutex.lock();
+}
+
+void InterruptManager::unlock()
+{
+ _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/InterruptManager.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/InterruptManager.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,205 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "platform/CallChain.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+#include <string.h>
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Use this singleton if you need to chain interrupt handlers.
+ * @deprecated Do not use this class. This class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ * led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ * led2 = !led1;
+ * }
+ *
+ * int main() {
+ * led1 = led2 = 0;
+ * flipper.attach(&flip, 1.0);
+ * InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class InterruptManager : private NonCopyable<InterruptManager> {
+public:
+ /** Get the instance of InterruptManager Class
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @return the only instance of this class
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ static InterruptManager *get();
+
+ /** Destroy the current instance of the interrupt manager
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ static void destroy();
+
+ /** Add a handler for an interrupt at the end of the handler list
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq)
+ {
+ // Underlying call is thread safe
+ return add_common(function, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq)
+ {
+ // Underlying call is thread safe
+ return add_common(function, irq, true);
+ }
+
+ /** Add a handler for an interrupt at the end of the handler list
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ pFunctionPointer_t add_handler(T *tptr, void (T::*mptr)(void), IRQn_Type irq)
+ {
+ // Underlying call is thread safe
+ return add_common(tptr, mptr, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ pFunctionPointer_t add_handler_front(T *tptr, void (T::*mptr)(void), IRQn_Type irq)
+ {
+ // Underlying call is thread safe
+ return add_common(tptr, mptr, irq, true);
+ }
+
+ /** Remove a handler from an interrupt
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @param handler the function object for the handler to remove
+ * @param irq the interrupt number
+ *
+ * @returns
+ * true if the handler was found and removed, false otherwise
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+ InterruptManager();
+ ~InterruptManager();
+
+ void lock();
+ void unlock();
+
+ template<typename T>
+ pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front = false)
+ {
+ _mutex.lock();
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+ if (change) {
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ }
+ _mutex.unlock();
+ return pf;
+ }
+
+ pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front = false);
+ bool must_replace_vector(IRQn_Type irq);
+ int get_irq_index(IRQn_Type irq);
+ void irq_helper();
+ void add_helper(void (*function)(void), IRQn_Type irq, bool front = false);
+ static void static_irq_helper();
+
+ CallChain *_chains[NVIC_NUM_VECTORS];
+ static InterruptManager *_instance;
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/LowPowerTicker.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/LowPowerTicker.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTICKER_H
+#define MBED_LOWPOWERTICKER_H
+
+#include "platform/platform.h"
+#include "drivers/Ticker.h"
+#include "platform/NonCopyable.h"
+
+#if defined (DEVICE_LPTICKER) || defined(DOXYGEN_ONLY)
+
+#include "hal/lp_ticker_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Low Power Ticker
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class LowPowerTicker : public Ticker, private NonCopyable<LowPowerTicker> {
+
+public:
+ LowPowerTicker() : Ticker(get_lp_ticker_data())
+ {
+ }
+
+ virtual ~LowPowerTicker()
+ {
+ }
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/LowPowerTimeout.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/LowPowerTimeout.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMEOUT_H
+#define MBED_LOWPOWERTIMEOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_LPTICKER) || defined(DOXYGEN_ONLY)
+
+#include "hal/lp_ticker_api.h"
+#include "drivers/LowPowerTicker.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Low Power Timout
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class LowPowerTimeout : public LowPowerTicker, private NonCopyable<LowPowerTimeout> {
+
+private:
+ virtual void handler(void)
+ {
+ _function.call();
+ }
+};
+
+}
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/LowPowerTimer.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/LowPowerTimer.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMER_H
+#define MBED_LOWPOWERTIMER_H
+
+#include "platform/platform.h"
+#include "drivers/Timer.h"
+#include "platform/NonCopyable.h"
+
+#if defined (DEVICE_LPTICKER) || defined(DOXYGEN_ONLY)
+
+#include "hal/lp_ticker_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Low power timer
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class LowPowerTimer : public Timer, private NonCopyable<LowPowerTimer> {
+
+public:
+ LowPowerTimer() : Timer(get_lp_ticker_data())
+ {
+ }
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/MbedCRC.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/MbedCRC.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+#include "drivers/TableCRC.h"
+#include "drivers/MbedCRC.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+/** @{*/
+
+/* Default values for different types of polynomials
+*/
+template<>
+MbedCRC<POLY_32BIT_ANSI, 32>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+ _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+ _crc_table((uint32_t *)Table_CRC_32bit_ANSI)
+{
+ mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_8BIT_CCITT, 8>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+ _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+ _crc_table((uint32_t *)Table_CRC_8bit_CCITT)
+{
+ mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_7BIT_SD, 7>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+ _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+ _crc_table((uint32_t *)Table_CRC_7Bit_SD)
+{
+ mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_16BIT_CCITT, 16>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+ _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+ _crc_table((uint32_t *)Table_CRC_16bit_CCITT)
+{
+ mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_16BIT_IBM, 16>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+ _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+ _crc_table((uint32_t *)Table_CRC_16bit_IBM)
+{
+ mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_32BIT_ANSI, 32>::MbedCRC():
+ _initial_value(~(0x0)), _final_xor(~(0x0)), _reflect_data(true), _reflect_remainder(true),
+ _crc_table((uint32_t *)Table_CRC_32bit_ANSI)
+{
+ mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_16BIT_IBM, 16>::MbedCRC():
+ _initial_value(0), _final_xor(0), _reflect_data(true), _reflect_remainder(true),
+ _crc_table((uint32_t *)Table_CRC_16bit_IBM)
+{
+ mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_16BIT_CCITT, 16>::MbedCRC():
+ _initial_value(~(0x0)), _final_xor(0), _reflect_data(false), _reflect_remainder(false),
+ _crc_table((uint32_t *)Table_CRC_16bit_CCITT)
+{
+ mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_7BIT_SD, 7>::MbedCRC():
+ _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false),
+ _crc_table((uint32_t *)Table_CRC_7Bit_SD)
+{
+ mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_8BIT_CCITT, 8>::MbedCRC():
+ _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false),
+ _crc_table((uint32_t *)Table_CRC_8bit_CCITT)
+{
+ mbed_crc_ctor();
+}
+
+/** @}*/
+} // namespace mbed
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/MbedCRC.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/MbedCRC.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,466 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CRC_API_H
+#define MBED_CRC_API_H
+
+#include "drivers/TableCRC.h"
+#include "hal/crc_api.h"
+#include "platform/mbed_assert.h"
+
+/* This is invalid warning from the compiler for below section of code
+if ((width < 8) && (NULL == _crc_table)) {
+ p_crc = (uint32_t)(p_crc << (8 - width));
+}
+Compiler warns of the shift operation with width as it is width=(std::uint8_t),
+but we check for ( width < 8) before performing shift, so it should not be an issue.
+*/
+#if defined ( __CC_ARM )
+#pragma diag_suppress 62 // Shift count is negative
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wshift-count-negative"
+#elif defined (__ICCARM__)
+#pragma diag_suppress=Pe062 // Shift count is negative
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+/** @{*/
+
+/** CRC object provides CRC generation through hardware/software
+ *
+ * ROM polynomial tables for supported polynomials (:: crc_polynomial_t) will be used for
+ * software CRC computation, if ROM tables are not available then CRC is computed runtime
+ * bit by bit for all data input.
+ *
+ * @tparam polynomial CRC polynomial value in hex
+ * @tparam width CRC polynomial width
+ *
+ * Example: Compute CRC data
+ * @code
+ *
+ * #include "mbed.h"
+ *
+ * int main() {
+ * MbedCRC<POLY_32BIT_ANSI, 32> ct;
+ *
+ * char test[] = "123456789";
+ * uint32_t crc = 0;
+ *
+ * printf("\nPolynomial = 0x%lx Width = %d \n", ct.get_polynomial(), ct.get_width());
+ *
+ * ct.compute((void *)test, strlen((const char*)test), &crc);
+ *
+ * printf("The CRC of data \"123456789\" is : 0x%lx\n", crc);
+ * return 0;
+ * }
+ * @endcode
+ * Example: Compute CRC with data available in parts
+ * @code
+ *
+ * #include "mbed.h"
+ * int main() {
+ * MbedCRC<POLY_32BIT_ANSI, 32> ct;
+ *
+ * char test[] = "123456789";
+ * uint32_t crc = 0;
+ *
+ * printf("\nPolynomial = 0x%lx Width = %d \n", ct.get_polynomial(), ct.get_width());
+ *
+ * ct.compute_partial_start(&crc);
+ * ct.compute_partial((void *)&test, 4, &crc);
+ * ct.compute_partial((void *)&test[4], 5, &crc);
+ * ct.compute_partial_stop(&crc);
+ *
+ * printf("The CRC of data \"123456789\" is : 0x%lx\n", crc);
+ * return 0;
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+
+template <uint32_t polynomial = POLY_32BIT_ANSI, uint8_t width = 32>
+class MbedCRC {
+public:
+ enum CrcMode { HARDWARE = 0, TABLE, BITWISE };
+
+public:
+ typedef uint64_t crc_data_size_t;
+
+ /** Lifetime of CRC object
+ *
+ * @param initial_xor Inital value/seed to Xor
+ * @param final_xor Final Xor value
+ * @param reflect_data
+ * @param reflect_remainder
+ * @note Default constructor without any arguments is valid only for supported CRC polynomials. :: crc_polynomial_t
+ * MbedCRC <POLY_7BIT_SD, 7> ct; --- Valid POLY_7BIT_SD
+ * MbedCRC <0x1021, 16> ct; --- Valid POLY_16BIT_CCITT
+ * MbedCRC <POLY_16BIT_CCITT, 32> ct; --- Invalid, compilation error
+ * MbedCRC <POLY_16BIT_CCITT, 32> ct (i,f,rd,rr) Consturctor can be used for not supported polynomials
+ * MbedCRC<POLY_16BIT_CCITT, 16> sd(0, 0, false, false); Constructor can also be used for supported
+ * polynomials with different intial/final/reflect values
+ *
+ */
+ MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder) :
+ _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data),
+ _reflect_remainder(reflect_remainder), _crc_table(NULL)
+ {
+ mbed_crc_ctor();
+ }
+ MbedCRC();
+ virtual ~MbedCRC()
+ {
+ // Do nothing
+ }
+
+ /** Compute CRC for the data input
+ *
+ * @param buffer Data bytes
+ * @param size Size of data
+ * @param crc CRC is the output value
+ * @return 0 on success, negative error code on failure
+ */
+ int32_t compute(void *buffer, crc_data_size_t size, uint32_t *crc)
+ {
+ MBED_ASSERT(crc != NULL);
+ int32_t status;
+ if (0 != (status = compute_partial_start(crc))) {
+ *crc = 0;
+ return status;
+ }
+ if (0 != (status = compute_partial(buffer, size, crc))) {
+ *crc = 0;
+ return status;
+ }
+ if (0 != (status = compute_partial_stop(crc))) {
+ *crc = 0;
+ return status;
+ }
+ return 0;
+ }
+
+ /** Compute partial CRC for the data input.
+ *
+ * CRC data if not available fully, CRC can be computed in parts with available data.
+ * Previous CRC output should be passed as argument to the current compute_partial call.
+ * @pre: Call \ref compute_partial_start to start the partial CRC calculation.
+ * @post: Call \ref compute_partial_stop to get the final CRC value.
+ *
+ * @param buffer Data bytes
+ * @param size Size of data
+ * @param crc CRC value is intermediate CRC value filled by API.
+ * @return 0 on success or a negative error code on failure
+ * @note: CRC as output in compute_partial is not final CRC value, call @ref compute_partial_stop
+ * to get final correct CRC value.
+ */
+ int32_t compute_partial(void *buffer, crc_data_size_t size, uint32_t *crc)
+ {
+ switch (_mode) {
+ case HARDWARE:
+#ifdef DEVICE_CRC
+ hal_crc_compute_partial((uint8_t *)buffer, size);
+#endif // DEVICE_CRC
+ *crc = 0;
+ return 0;
+ case TABLE:
+ return table_compute_partial(buffer, size, crc);
+ case BITWISE:
+ return bitwise_compute_partial(buffer, size, crc);
+ }
+
+ return -1;
+ }
+
+ /** Compute partial start, indicate start of partial computation
+ *
+ * This API should be called before performing any partial computation
+ * with compute_partial API.
+ *
+ * @param crc Initial CRC value set by the API
+ * @return 0 on success or a negative in case of failure
+ * @note: CRC is an out parameter and must be reused with compute_partial
+ * and compute_partial_stop without any modifications in application.
+ */
+ int32_t compute_partial_start(uint32_t *crc)
+ {
+ MBED_ASSERT(crc != NULL);
+
+#ifdef DEVICE_CRC
+ if (_mode == HARDWARE) {
+ crc_mbed_config_t config;
+ config.polynomial = polynomial;
+ config.width = width;
+ config.initial_xor = _initial_value;
+ config.final_xor = _final_xor;
+ config.reflect_in = _reflect_data;
+ config.reflect_out = _reflect_remainder;
+
+ hal_crc_compute_partial_start(&config);
+ }
+#endif // DEVICE_CRC
+
+ *crc = _initial_value;
+ return 0;
+ }
+
+ /** Get the final CRC value of partial computation.
+ *
+ * CRC value available in partial computation is not correct CRC, as some
+ * algorithms require remainder to be reflected and final value to be XORed
+ * This API is used to perform final computation to get correct CRC value.
+ *
+ * @param crc CRC result
+ */
+ int32_t compute_partial_stop(uint32_t *crc)
+ {
+ MBED_ASSERT(crc != NULL);
+
+ if (_mode == HARDWARE) {
+#ifdef DEVICE_CRC
+ *crc = hal_crc_get_result();
+ return 0;
+#else
+ return -1;
+#endif
+ }
+
+ uint32_t p_crc = *crc;
+ if ((width < 8) && (NULL == _crc_table)) {
+ p_crc = (uint32_t)(p_crc << (8 - width));
+ }
+ *crc = (reflect_remainder(p_crc) ^ _final_xor) & get_crc_mask();
+ return 0;
+ }
+
+ /** Get the current CRC polynomial
+ *
+ * @return Polynomial value
+ */
+ uint32_t get_polynomial(void) const
+ {
+ return polynomial;
+ }
+
+ /** Get the current CRC width
+ *
+ * @return CRC width
+ */
+ uint8_t get_width(void) const
+ {
+ return width;
+ }
+
+private:
+ uint32_t _initial_value;
+ uint32_t _final_xor;
+ bool _reflect_data;
+ bool _reflect_remainder;
+ uint32_t *_crc_table;
+ CrcMode _mode;
+
+ /** Get the current CRC data size
+ *
+ * @return CRC data size in bytes
+ */
+ uint8_t get_data_size(void) const
+ {
+ return (width <= 8 ? 1 : (width <= 16 ? 2 : 4));
+ }
+
+ /** Get the top bit of current CRC
+ *
+ * @return Top bit is set high for respective data width of current CRC
+ * Top bit for CRC width less then 8 bits will be set as 8th bit.
+ */
+ uint32_t get_top_bit(void) const
+ {
+ return (width < 8 ? (1u << 7) : (uint32_t)(1ul << (width - 1)));
+ }
+
+ /** Get the CRC data mask
+ *
+ * @return CRC data mask is generated based on current CRC width
+ */
+ uint32_t get_crc_mask(void) const
+ {
+ return (width < 8 ? ((1u << 8) - 1) : (uint32_t)((uint64_t)(1ull << width) - 1));
+ }
+
+ /** Final value of CRC is reflected
+ *
+ * @param data final crc value, which should be reflected
+ * @return Reflected CRC value
+ */
+ uint32_t reflect_remainder(uint32_t data) const
+ {
+ if (_reflect_remainder) {
+ uint32_t reflection = 0x0;
+ uint8_t const nBits = (width < 8 ? 8 : width);
+
+ for (uint8_t bit = 0; bit < nBits; ++bit) {
+ if (data & 0x01) {
+ reflection |= (1 << ((nBits - 1) - bit));
+ }
+ data = (data >> 1);
+ }
+ return (reflection);
+ } else {
+ return data;
+ }
+ }
+
+ /** Data bytes are reflected
+ *
+ * @param data value to be reflected
+ * @return Reflected data value
+ */
+ uint32_t reflect_bytes(uint32_t data) const
+ {
+ if (_reflect_data) {
+ uint32_t reflection = 0x0;
+
+ for (uint8_t bit = 0; bit < 8; ++bit) {
+ if (data & 0x01) {
+ reflection |= (1 << (7 - bit));
+ }
+ data = (data >> 1);
+ }
+ return (reflection);
+ } else {
+ return data;
+ }
+ }
+
+ /** Bitwise CRC computation
+ *
+ * @param buffer data buffer
+ * @param size size of the data
+ * @param crc CRC value is filled in, but the value is not the final
+ * @return 0 on success or a negative error code on failure
+ */
+ int32_t bitwise_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const
+ {
+ MBED_ASSERT(crc != NULL);
+ MBED_ASSERT(buffer != NULL);
+
+ const uint8_t *data = static_cast<const uint8_t *>(buffer);
+ uint32_t p_crc = *crc;
+
+ if (width < 8) {
+ uint8_t data_byte;
+ for (crc_data_size_t byte = 0; byte < size; byte++) {
+ data_byte = reflect_bytes(data[byte]);
+ for (uint8_t bit = 8; bit > 0; --bit) {
+ p_crc <<= 1;
+ if ((data_byte ^ p_crc) & get_top_bit()) {
+ p_crc ^= polynomial;
+ }
+ data_byte <<= 1;
+ }
+ }
+ } else {
+ for (crc_data_size_t byte = 0; byte < size; byte++) {
+ p_crc ^= (reflect_bytes(data[byte]) << (width - 8));
+
+ // Perform modulo-2 division, a bit at a time
+ for (uint8_t bit = 8; bit > 0; --bit) {
+ if (p_crc & get_top_bit()) {
+ p_crc = (p_crc << 1) ^ polynomial;
+ } else {
+ p_crc = (p_crc << 1);
+ }
+ }
+ }
+ }
+ *crc = p_crc & get_crc_mask();
+ return 0;
+ }
+
+ /** CRC computation using ROM tables
+ *
+ * @param buffer data buffer
+ * @param size size of the data
+ * @param crc CRC value is filled in, but the value is not the final
+ * @return 0 on success or a negative error code on failure
+ */
+ int32_t table_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const
+ {
+ MBED_ASSERT(crc != NULL);
+ MBED_ASSERT(buffer != NULL);
+
+ const uint8_t *data = static_cast<const uint8_t *>(buffer);
+ uint32_t p_crc = *crc;
+ uint8_t data_byte = 0;
+
+ if (width <= 8) {
+ uint8_t *crc_table = (uint8_t *)_crc_table;
+ for (crc_data_size_t byte = 0; byte < size; byte++) {
+ data_byte = reflect_bytes(data[byte]) ^ p_crc;
+ p_crc = crc_table[data_byte];
+ }
+ } else if (width <= 16) {
+ uint16_t *crc_table = (uint16_t *)_crc_table;
+ for (crc_data_size_t byte = 0; byte < size; byte++) {
+ data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8));
+ p_crc = crc_table[data_byte] ^ (p_crc << 8);
+ }
+ } else {
+ uint32_t *crc_table = (uint32_t *)_crc_table;
+ for (crc_data_size_t byte = 0; byte < size; byte++) {
+ data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8));
+ p_crc = crc_table[data_byte] ^ (p_crc << 8);
+ }
+ }
+ *crc = p_crc & get_crc_mask();
+ return 0;
+ }
+
+ /** Constructor init called from all specialized cases of constructor
+ * Note: All construtor common code should be in this function.
+ */
+ void mbed_crc_ctor(void)
+ {
+ MBED_STATIC_ASSERT(width <= 32, "Max 32-bit CRC supported");
+
+ _mode = (_crc_table != NULL) ? TABLE : BITWISE;
+
+#ifdef DEVICE_CRC
+ crc_mbed_config_t config;
+ config.polynomial = polynomial;
+ config.width = width;
+ config.initial_xor = _initial_value;
+ config.final_xor = _final_xor;
+ config.reflect_in = _reflect_data;
+ config.reflect_out = _reflect_remainder;
+
+ if (hal_crc_is_supported(&config)) {
+ _mode = HARDWARE;
+ }
+#endif
+ }
+};
+
+#if defined ( __CC_ARM )
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#elif defined (__ICCARM__)
+#endif
+
+/** @}*/
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/PortIn.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/PortIn.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTIN_H
+#define MBED_PORTIN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PORTIN) || defined(DOXYGEN_ONLY)
+
+#include "hal/port_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A multiple pin digital input
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Switch on an LED if any of mbed pins 21-26 is high
+ *
+ * #include "mbed.h"
+ *
+ * PortIn p(Port2, 0x0000003F); // p21-p26
+ * DigitalOut ind(LED4);
+ *
+ * int main() {
+ * while(1) {
+ * int pins = p.read();
+ * if(pins) {
+ * ind = 1;
+ * } else {
+ * ind = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class PortIn {
+public:
+
+ /** Create an PortIn, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortIn(PortName port, int mask = 0xFFFFFFFF)
+ {
+ core_util_critical_section_enter();
+ port_init(&_port, port, mask, PIN_INPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated port pin setting
+ */
+ int read()
+ {
+ return port_read(&_port);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode mode)
+ {
+ core_util_critical_section_enter();
+ port_mode(&_port, mode);
+ core_util_critical_section_exit();
+ }
+
+ /** A shorthand for read()
+ */
+ operator int()
+ {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/PortInOut.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/PortInOut.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,131 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTINOUT_H
+#define MBED_PORTINOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PORTINOUT) || defined(DOXYGEN_ONLY)
+
+#include "hal/port_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class PortInOut {
+public:
+
+ /** Create an PortInOut, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortInOut(PortName port, int mask = 0xFFFFFFFF)
+ {
+ core_util_critical_section_enter();
+ port_init(&_port, port, mask, PIN_INPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Write the value to the output port
+ *
+ * @param value An integer specifying a bit to write for every corresponding port pin
+ */
+ void write(int value)
+ {
+ port_write(&_port, value);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated port pin setting
+ */
+ int read()
+ {
+ return port_read(&_port);
+ }
+
+ /** Set as an output
+ */
+ void output()
+ {
+ core_util_critical_section_enter();
+ port_dir(&_port, PIN_OUTPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Set as an input
+ */
+ void input()
+ {
+ core_util_critical_section_enter();
+ port_dir(&_port, PIN_INPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode mode)
+ {
+ core_util_critical_section_enter();
+ port_mode(&_port, mode);
+ core_util_critical_section_exit();
+ }
+
+ /** A shorthand for write()
+ * \sa PortInOut::write()
+ */
+ PortInOut &operator= (int value)
+ {
+ write(value);
+ return *this;
+ }
+
+ /** A shorthand for write()
+ * \sa PortInOut::write()
+ */
+ PortInOut &operator= (PortInOut &rhs)
+ {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ * \sa PortInOut::read()
+ */
+ operator int()
+ {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/PortOut.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/PortOut.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTOUT_H
+#define MBED_PORTOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PORTOUT) || defined(DOXYGEN_ONLY)
+
+#include "hal/port_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+/** A multiple pin digital out
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle all four LEDs
+ *
+ * #include "mbed.h"
+ *
+ * // LED1 = P1.18 LED2 = P1.20 LED3 = P1.21 LED4 = P1.23
+ * #define LED_MASK 0x00B40000
+ *
+ * PortOut ledport(Port1, LED_MASK);
+ *
+ * int main() {
+ * while(1) {
+ * ledport = LED_MASK;
+ * wait(1);
+ * ledport = 0;
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class PortOut {
+public:
+
+ /** Create an PortOut, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortOut(PortName port, int mask = 0xFFFFFFFF)
+ {
+ core_util_critical_section_enter();
+ port_init(&_port, port, mask, PIN_OUTPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Write the value to the output port
+ *
+ * @param value An integer specifying a bit to write for every corresponding PortOut pin
+ */
+ void write(int value)
+ {
+ port_write(&_port, value);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated PortOut pin setting
+ */
+ int read()
+ {
+ return port_read(&_port);
+ }
+
+ /** A shorthand for write()
+ * \sa PortOut::write()
+ */
+ PortOut &operator= (int value)
+ {
+ write(value);
+ return *this;
+ }
+
+ /** A shorthand for read()
+ * \sa PortOut::read()
+ */
+ PortOut &operator= (PortOut &rhs)
+ {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ * \sa PortOut::read()
+ */
+ operator int()
+ {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/PwmOut.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/PwmOut.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,227 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_H
+#define MBED_PWMOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PWMOUT) || defined(DOXYGEN_ONLY)
+#include "hal/pwmout_api.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_power_mgmt.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A pulse-width modulation digital output
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example
+ * @code
+ * // Fade a led on.
+ * #include "mbed.h"
+ *
+ * PwmOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * led = led + 0.01;
+ * wait(0.2);
+ * if(led == 1.0) {
+ * led = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class PwmOut {
+
+public:
+
+ /** Create a PwmOut connected to the specified pin
+ *
+ * @param pin PwmOut pin to connect to
+ */
+ PwmOut(PinName pin) : _deep_sleep_locked(false)
+ {
+ core_util_critical_section_enter();
+ pwmout_init(&_pwm, pin);
+ core_util_critical_section_exit();
+ }
+
+ ~PwmOut()
+ {
+ core_util_critical_section_enter();
+ unlock_deep_sleep();
+ core_util_critical_section_exit();
+ }
+
+ /** Set the ouput duty-cycle, specified as a percentage (float)
+ *
+ * @param value A floating-point value representing the output duty-cycle,
+ * specified as a percentage. The value should lie between
+ * 0.0f (representing on 0%) and 1.0f (representing on 100%).
+ * Values outside this range will be saturated to 0.0f or 1.0f.
+ */
+ void write(float value)
+ {
+ core_util_critical_section_enter();
+ lock_deep_sleep();
+ pwmout_write(&_pwm, value);
+ core_util_critical_section_exit();
+ }
+
+ /** Return the current output duty-cycle setting, measured as a percentage (float)
+ *
+ * @returns
+ * A floating-point value representing the current duty-cycle being output on the pin,
+ * measured as a percentage. The returned value will lie between
+ * 0.0f (representing on 0%) and 1.0f (representing on 100%).
+ *
+ * @note
+ * This value may not match exactly the value set by a previous write().
+ */
+ float read()
+ {
+ core_util_critical_section_enter();
+ float val = pwmout_read(&_pwm);
+ core_util_critical_section_exit();
+ return val;
+ }
+
+ /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
+ *
+ * @param seconds Change the period of a PWM signal in seconds (float) without modifying the duty cycle
+ * @note
+ * The resolution is currently in microseconds; periods smaller than this
+ * will be set to zero.
+ */
+ void period(float seconds)
+ {
+ core_util_critical_section_enter();
+ pwmout_period(&_pwm, seconds);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
+ * @param ms Change the period of a PWM signal in milli-seconds without modifying the duty cycle
+ */
+ void period_ms(int ms)
+ {
+ core_util_critical_section_enter();
+ pwmout_period_ms(&_pwm, ms);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
+ * @param us Change the period of a PWM signal in micro-seconds without modifying the duty cycle
+ */
+ void period_us(int us)
+ {
+ core_util_critical_section_enter();
+ pwmout_period_us(&_pwm, us);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
+ * @param seconds Change the pulse width of a PWM signal specified in seconds (float)
+ */
+ void pulsewidth(float seconds)
+ {
+ core_util_critical_section_enter();
+ pwmout_pulsewidth(&_pwm, seconds);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
+ * @param ms Change the pulse width of a PWM signal specified in milli-seconds
+ */
+ void pulsewidth_ms(int ms)
+ {
+ core_util_critical_section_enter();
+ pwmout_pulsewidth_ms(&_pwm, ms);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
+ * @param us Change the pulse width of a PWM signal specified in micro-seconds
+ */
+ void pulsewidth_us(int us)
+ {
+ core_util_critical_section_enter();
+ pwmout_pulsewidth_us(&_pwm, us);
+ core_util_critical_section_exit();
+ }
+
+ /** A operator shorthand for write()
+ * \sa PwmOut::write()
+ */
+ PwmOut &operator= (float value)
+ {
+ // Underlying call is thread safe
+ write(value);
+ return *this;
+ }
+
+ /** A operator shorthand for write()
+ * \sa PwmOut::write()
+ */
+ PwmOut &operator= (PwmOut &rhs)
+ {
+ // Underlying call is thread safe
+ write(rhs.read());
+ return *this;
+ }
+
+ /** An operator shorthand for read()
+ * \sa PwmOut::read()
+ */
+ operator float()
+ {
+ // Underlying call is thread safe
+ return read();
+ }
+
+protected:
+ /** Lock deep sleep only if it is not yet locked */
+ void lock_deep_sleep()
+ {
+ if (_deep_sleep_locked == false) {
+ sleep_manager_lock_deep_sleep();
+ _deep_sleep_locked = true;
+ }
+ }
+
+ /** Unlock deep sleep in case it is locked */
+ void unlock_deep_sleep()
+ {
+ if (_deep_sleep_locked == true) {
+ sleep_manager_unlock_deep_sleep();
+ _deep_sleep_locked = false;
+ }
+ }
+
+ pwmout_t _pwm;
+ bool _deep_sleep_locked;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/RawSerial.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/RawSerial.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/RawSerial.h"
+#include "platform/mbed_wait_api.h"
+#include <stdio.h>
+#include <cstdarg>
+
+
+#if DEVICE_SERIAL
+
+#define STRING_STACK_LIMIT 120
+
+namespace mbed {
+
+RawSerial::RawSerial(PinName tx, PinName rx, int baud) : SerialBase(tx, rx, baud)
+{
+ // No lock needed in the constructor
+}
+
+int RawSerial::getc()
+{
+ lock();
+ int ret = _base_getc();
+ unlock();
+ return ret;
+}
+
+int RawSerial::putc(int c)
+{
+ lock();
+ int ret = _base_putc(c);
+ unlock();
+ return ret;
+}
+
+int RawSerial::puts(const char *str)
+{
+ lock();
+ while (*str) {
+ putc(*str ++);
+ }
+ unlock();
+ return 0;
+}
+
+// Experimental support for printf in RawSerial. No Stream inheritance
+// means we can't call printf() directly, so we use sprintf() instead.
+// We only call malloc() for the sprintf() buffer if the buffer
+// length is above a certain threshold, otherwise we use just the stack.
+int RawSerial::printf(const char *format, ...)
+{
+ lock();
+ std::va_list arg;
+ va_start(arg, format);
+ // ARMCC microlib does not properly handle a size of 0.
+ // As a workaround supply a dummy buffer with a size of 1.
+ char dummy_buf[1];
+ int len = vsnprintf(dummy_buf, sizeof(dummy_buf), format, arg);
+ if (len < STRING_STACK_LIMIT) {
+ char temp[STRING_STACK_LIMIT];
+ vsprintf(temp, format, arg);
+ puts(temp);
+ } else {
+ char *temp = new char[len + 1];
+ vsprintf(temp, format, arg);
+ puts(temp);
+ delete[] temp;
+ }
+ va_end(arg);
+ unlock();
+ return len;
+}
+
+/** Acquire exclusive access to this serial port
+ */
+void RawSerial::lock()
+{
+ // No lock used - external synchronization required
+}
+
+/** Release exclusive access to this serial port
+ */
+void RawSerial::unlock()
+{
+ // No lock used - external synchronization required
+}
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/RawSerial.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/RawSerial.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RAW_SERIAL_H
+#define MBED_RAW_SERIAL_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
+
+#include "drivers/SerialBase.h"
+#include "hal/serial_api.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A serial port (UART) for communication with other serial devices
+ * This is a variation of the Serial class that doesn't use streams,
+ * thus making it safe to use in interrupt handlers with the RTOS.
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Send a char to the PC
+ *
+ * #include "mbed.h"
+ *
+ * RawSerial pc(USBTX, USBRX);
+ *
+ * int main() {
+ * pc.putc('A');
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class RawSerial: public SerialBase, private NonCopyable<RawSerial> {
+
+public:
+ /** Create a RawSerial port, connected to the specified transmit and receive pins, with the specified baud.
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ RawSerial(PinName tx, PinName rx, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
+
+ /** Write a char to the serial port
+ *
+ * @param c The char to write
+ *
+ * @returns The written char or -1 if an error occurred
+ */
+ int putc(int c);
+
+ /** Read a char from the serial port
+ *
+ * @returns The char read from the serial port
+ */
+ int getc();
+
+ /** Write a string to the serial port
+ *
+ * @param str The string to write
+ *
+ * @returns 0 if the write succeeds, EOF for error
+ */
+ int puts(const char *str);
+
+ int printf(const char *format, ...);
+
+protected:
+
+ /* Acquire exclusive access to this serial port
+ */
+ virtual void lock(void);
+
+ /* Release exclusive access to this serial port
+ */
+ virtual void unlock(void);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/SPI.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/SPI.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,275 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/SPI.h"
+#include "platform/mbed_critical.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "platform/mbed_power_mgmt.h"
+#endif
+
+#if DEVICE_SPI
+
+namespace mbed {
+
+#if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
+CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
+#endif
+
+SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+ _spi(),
+#if DEVICE_SPI_ASYNCH
+ _irq(this),
+ _usage(DMA_USAGE_NEVER),
+ _deep_sleep_locked(false),
+#endif
+ _bits(8),
+ _mode(0),
+ _hz(1000000),
+ _write_fill(SPI_FILL_CHAR)
+{
+ // No lock needed in the constructor
+
+ spi_init(&_spi, mosi, miso, sclk, ssel);
+ _acquire();
+}
+
+void SPI::format(int bits, int mode)
+{
+ lock();
+ _bits = bits;
+ _mode = mode;
+ // If changing format while you are the owner then just
+ // update format, but if owner is changed then even frequency should be
+ // updated which is done by acquire.
+ if (_owner == this) {
+ spi_format(&_spi, _bits, _mode, 0);
+ } else {
+ _acquire();
+ }
+ unlock();
+}
+
+void SPI::frequency(int hz)
+{
+ lock();
+ _hz = hz;
+ // If changing format while you are the owner then just
+ // update frequency, but if owner is changed then even frequency should be
+ // updated which is done by acquire.
+ if (_owner == this) {
+ spi_frequency(&_spi, _hz);
+ } else {
+ _acquire();
+ }
+ unlock();
+}
+
+SPI *SPI::_owner = NULL;
+SingletonPtr<PlatformMutex> SPI::_mutex;
+
+// ignore the fact there are multiple physical spis, and always update if it wasn't us last
+void SPI::aquire()
+{
+ lock();
+ if (_owner != this) {
+ spi_format(&_spi, _bits, _mode, 0);
+ spi_frequency(&_spi, _hz);
+ _owner = this;
+ }
+ unlock();
+}
+
+// Note: Private function with no locking
+void SPI::_acquire()
+{
+ if (_owner != this) {
+ spi_format(&_spi, _bits, _mode, 0);
+ spi_frequency(&_spi, _hz);
+ _owner = this;
+ }
+}
+
+int SPI::write(int value)
+{
+ lock();
+ _acquire();
+ int ret = spi_master_write(&_spi, value);
+ unlock();
+ return ret;
+}
+
+int SPI::write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length)
+{
+ lock();
+ _acquire();
+ int ret = spi_master_block_write(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, _write_fill);
+ unlock();
+ return ret;
+}
+
+void SPI::lock()
+{
+ _mutex->lock();
+}
+
+void SPI::unlock()
+{
+ _mutex->unlock();
+}
+
+void SPI::set_default_write_value(char data)
+{
+ lock();
+ _write_fill = data;
+ unlock();
+}
+
+#if DEVICE_SPI_ASYNCH
+
+int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event)
+{
+ if (spi_active(&_spi)) {
+ return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+ }
+ start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+ return 0;
+}
+
+void SPI::abort_transfer()
+{
+ spi_abort_asynch(&_spi);
+ unlock_deep_sleep();
+#if TRANSACTION_QUEUE_SIZE_SPI
+ dequeue_transaction();
+#endif
+}
+
+
+void SPI::clear_transfer_buffer()
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+ _transaction_buffer.reset();
+#endif
+}
+
+void SPI::abort_all_transfers()
+{
+ clear_transfer_buffer();
+ abort_transfer();
+}
+
+int SPI::set_dma_usage(DMAUsage usage)
+{
+ if (spi_active(&_spi)) {
+ return -1;
+ }
+ _usage = usage;
+ return 0;
+}
+
+int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event)
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+ transaction_t t;
+
+ t.tx_buffer = const_cast<void *>(tx_buffer);
+ t.tx_length = tx_length;
+ t.rx_buffer = rx_buffer;
+ t.rx_length = rx_length;
+ t.event = event;
+ t.callback = callback;
+ t.width = bit_width;
+ Transaction<SPI> transaction(this, t);
+ if (_transaction_buffer.full()) {
+ return -1; // the buffer is full
+ } else {
+ core_util_critical_section_enter();
+ _transaction_buffer.push(transaction);
+ if (!spi_active(&_spi)) {
+ dequeue_transaction();
+ }
+ core_util_critical_section_exit();
+ return 0;
+ }
+#else
+ return -1;
+#endif
+}
+
+void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event)
+{
+ lock_deep_sleep();
+ _acquire();
+ _callback = callback;
+ _irq.callback(&SPI::irq_handler_asynch);
+ spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event, _usage);
+}
+
+void SPI::lock_deep_sleep()
+{
+ if (_deep_sleep_locked == false) {
+ sleep_manager_lock_deep_sleep();
+ _deep_sleep_locked = true;
+ }
+}
+
+void SPI::unlock_deep_sleep()
+{
+ if (_deep_sleep_locked == true) {
+ sleep_manager_unlock_deep_sleep();
+ _deep_sleep_locked = false;
+ }
+}
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+void SPI::start_transaction(transaction_t *data)
+{
+ start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
+}
+
+void SPI::dequeue_transaction()
+{
+ Transaction<SPI> t;
+ if (_transaction_buffer.pop(t)) {
+ SPI *obj = t.get_object();
+ transaction_t *data = t.get_transaction();
+ obj->start_transaction(data);
+ }
+}
+
+#endif
+
+void SPI::irq_handler_asynch(void)
+{
+ int event = spi_irq_handler_asynch(&_spi);
+ if (_callback && (event & SPI_EVENT_ALL)) {
+ unlock_deep_sleep();
+ _callback.call(event & SPI_EVENT_ALL);
+ }
+#if TRANSACTION_QUEUE_SIZE_SPI
+ if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
+ // SPI peripheral is free (event happened), dequeue transaction
+ dequeue_transaction();
+ }
+#endif
+}
+
+#endif
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/SPI.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/SPI.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,309 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_H
+#define MBED_SPI_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SPI) || defined(DOXYGEN_ONLY)
+
+#include "platform/PlatformMutex.h"
+#include "hal/spi_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/NonCopyable.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "platform/CThunk.h"
+#include "hal/dma_api.h"
+#include "platform/CircularBuffer.h"
+#include "platform/FunctionPointer.h"
+#include "platform/Transaction.h"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A SPI Master, used for communicating with SPI slave devices
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Most SPI devices will also require Chip Select and Reset signals. These
+ * can be controlled using DigitalOut pins
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Send a byte to a SPI slave, and record the response
+ *
+ * #include "mbed.h"
+ *
+ * // hardware ssel (where applicable)
+ * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * // software ssel
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
+ * DigitalOut cs(p8); // ssel
+ *
+ * int main() {
+ * // hardware ssel (where applicable)
+ * //int response = device.write(0xFF);
+ *
+ * device.lock();
+ * // software ssel
+ * cs = 0;
+ * int response = device.write(0xFF);
+ * cs = 1;
+ * device.unlock();
+ *
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class SPI : private NonCopyable<SPI> {
+
+public:
+
+ /** Create a SPI master connected to the specified pins
+ *
+ * mosi or miso can be specified as NC if not used
+ *
+ * @param mosi SPI Master Out, Slave In pin
+ * @param miso SPI Master In, Slave Out pin
+ * @param sclk SPI Clock pin
+ * @param ssel SPI chip select pin
+ */
+ SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel = NC);
+
+ /** Configure the data transmission format
+ *
+ * @param bits Number of bits per SPI frame (4 - 16)
+ * @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ * 0 | 0 0
+ * 1 | 0 1
+ * 2 | 1 0
+ * 3 | 1 1
+ * @endcode
+ */
+ void format(int bits, int mode = 0);
+
+ /** Set the spi bus clock frequency
+ *
+ * @param hz SCLK frequency in hz (default = 1MHz)
+ */
+ void frequency(int hz = 1000000);
+
+ /** Write to the SPI Slave and return the response
+ *
+ * @param value Data to be sent to the SPI slave
+ *
+ * @returns
+ * Response from the SPI slave
+ */
+ virtual int write(int value);
+
+ /** Write to the SPI Slave and obtain the response
+ *
+ * The total number of bytes sent and received will be the maximum of
+ * tx_length and rx_length. The bytes written will be padded with the
+ * value 0xff.
+ *
+ * @param tx_buffer Pointer to the byte-array of data to write to the device
+ * @param tx_length Number of bytes to write, may be zero
+ * @param rx_buffer Pointer to the byte-array of data to read from the device
+ * @param rx_length Number of bytes to read, may be zero
+ * @returns
+ * The number of bytes written and read from the device. This is
+ * maximum of tx_length and rx_length.
+ */
+ virtual int write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length);
+
+ /** Acquire exclusive access to this SPI bus
+ */
+ virtual void lock(void);
+
+ /** Release exclusive access to this SPI bus
+ */
+ virtual void unlock(void);
+
+ /** Set default write data
+ * SPI requires the master to send some data during a read operation.
+ * Different devices may require different default byte values.
+ * For example: A SD Card requires default bytes to be 0xFF.
+ *
+ * @param data Default character to be transmitted while read operation
+ */
+ void set_default_write_value(char data);
+
+#if DEVICE_SPI_ASYNCH
+
+ /** Start non-blocking SPI transfer using 8bit buffers.
+ *
+ * This function locks the deep sleep until any event has occurred
+ *
+ * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+ * the default SPI value is sent
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+ * received data are ignored
+ * @param rx_length The length of RX buffer in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of events to modify. Look at spi hal header file for SPI events.
+ * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
+ */
+ template<typename Type>
+ int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t &callback, int event = SPI_EVENT_COMPLETE)
+ {
+ if (spi_active(&_spi)) {
+ return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type) * 8, callback, event);
+ }
+ start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type) * 8, callback, event);
+ return 0;
+ }
+
+ /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
+ */
+ void abort_transfer();
+
+ /** Clear the transaction buffer
+ */
+ void clear_transfer_buffer();
+
+ /** Clear the transaction buffer and abort on-going transfer.
+ */
+ void abort_all_transfers();
+
+ /** Configure DMA usage suggestion for non-blocking transfers
+ *
+ * @param usage The usage DMA hint for peripheral
+ * @return Zero if the usage was set, -1 if a transaction is on-going
+ */
+ int set_dma_usage(DMAUsage usage);
+
+protected:
+ /** SPI IRQ handler
+ *
+ */
+ void irq_handler_asynch(void);
+
+ /** Common transfer method
+ *
+ * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+ * the default SPI value is sent
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+ * received data are ignored
+ * @param rx_length The length of RX buffer in bytes
+ * @param bit_width The buffers element width
+ * @param callback The event callback function
+ * @param event The logical OR of events to modify
+ * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
+ */
+ int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event);
+
+ /**
+ *
+ * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+ * the default SPI value is sent
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+ * received data are ignored
+ * @param rx_length The length of RX buffer in bytes
+ * @param bit_width The buffers element width
+ * @param callback The event callback function
+ * @param event The logical OR of events to modify
+ * @return Zero if a transfer was added to the queue, or -1 if the queue is full
+ */
+ int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event);
+
+ /** Configures a callback, spi peripheral and initiate a new transfer
+ *
+ * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+ * the default SPI value is sent
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+ * received data are ignored
+ * @param rx_length The length of RX buffer in bytes
+ * @param bit_width The buffers element width
+ * @param callback The event callback function
+ * @param event The logical OR of events to modify
+ */
+ void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event);
+
+private:
+ /** Lock deep sleep only if it is not yet locked */
+ void lock_deep_sleep();
+
+ /** Unlock deep sleep in case it is locked */
+ void unlock_deep_sleep();
+
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+ /** Start a new transaction
+ *
+ * @param data Transaction data
+ */
+ void start_transaction(transaction_t *data);
+
+ /** Dequeue a transaction
+ *
+ */
+ void dequeue_transaction();
+ static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
+#endif
+
+#endif
+
+public:
+ virtual ~SPI()
+ {
+ }
+
+protected:
+ spi_t _spi;
+
+#if DEVICE_SPI_ASYNCH
+ CThunk<SPI> _irq;
+ event_callback_t _callback;
+ DMAUsage _usage;
+ bool _deep_sleep_locked;
+#endif
+
+ void aquire(void);
+ static SPI *_owner;
+ static SingletonPtr<PlatformMutex> _mutex;
+ int _bits;
+ int _mode;
+ int _hz;
+ char _write_fill;
+
+private:
+ /* Private acquire function without locking/unlocking
+ * Implemented in order to avoid duplicate locking and boost performance
+ */
+ void _acquire(void);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/SPISlave.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/SPISlave.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/SPISlave.h"
+
+#if DEVICE_SPISLAVE
+
+namespace mbed {
+
+SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+ _spi(),
+ _bits(8),
+ _mode(0),
+ _hz(1000000)
+{
+ spi_init(&_spi, mosi, miso, sclk, ssel);
+ spi_format(&_spi, _bits, _mode, 1);
+ spi_frequency(&_spi, _hz);
+}
+
+void SPISlave::format(int bits, int mode)
+{
+ _bits = bits;
+ _mode = mode;
+ spi_format(&_spi, _bits, _mode, 1);
+}
+
+void SPISlave::frequency(int hz)
+{
+ _hz = hz;
+ spi_frequency(&_spi, _hz);
+}
+
+int SPISlave::receive(void)
+{
+ return (spi_slave_receive(&_spi));
+}
+
+int SPISlave::read(void)
+{
+ return (spi_slave_read(&_spi));
+}
+
+void SPISlave::reply(int value)
+{
+ spi_slave_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/SPISlave.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/SPISlave.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPISLAVE_H
+#define MBED_SPISLAVE_H
+
+#include "platform/platform.h"
+#include "platform/NonCopyable.h"
+
+#if defined (DEVICE_SPISLAVE) || defined(DOXYGEN_ONLY)
+
+#include "hal/spi_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A SPI slave, used for communicating with a SPI Master device
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Reply to a SPI master as slave
+ *
+ * #include "mbed.h"
+ *
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * int main() {
+ * device.reply(0x00); // Prime SPI with first reply
+ * while(1) {
+ * if(device.receive()) {
+ * int v = device.read(); // Read byte from master
+ * v = (v + 1) % 0x100; // Add one to it, modulo 256
+ * device.reply(v); // Make this the next reply
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class SPISlave : private NonCopyable<SPISlave> {
+
+public:
+
+ /** Create a SPI slave connected to the specified pins
+ *
+ * mosi or miso can be specified as NC if not used
+ *
+ * @param mosi SPI Master Out, Slave In pin
+ * @param miso SPI Master In, Slave Out pin
+ * @param sclk SPI Clock pin
+ * @param ssel SPI chip select pin
+ */
+ SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+ /** Configure the data transmission format
+ *
+ * @param bits Number of bits per SPI frame (4 - 16)
+ * @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ * 0 | 0 0
+ * 1 | 0 1
+ * 2 | 1 0
+ * 3 | 1 1
+ * @endcode
+ */
+ void format(int bits, int mode = 0);
+
+ /** Set the spi bus clock frequency
+ *
+ * @param hz SCLK frequency in hz (default = 1MHz)
+ */
+ void frequency(int hz = 1000000);
+
+ /** Polls the SPI to see if data has been received
+ *
+ * @returns
+ * 0 if no data,
+ * 1 otherwise
+ */
+ int receive(void);
+
+ /** Retrieve data from receive buffer as slave
+ *
+ * @returns
+ * the data in the receive buffer
+ */
+ int read(void);
+
+ /** Fill the transmission buffer with the value to be written out
+ * as slave on the next received message from the master.
+ *
+ * @param value the data to be transmitted next
+ */
+ void reply(int value);
+
+protected:
+ spi_t _spi;
+
+ int _bits;
+ int _mode;
+ int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Serial.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Serial.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Serial.h"
+#include "platform/mbed_wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+Serial::Serial(PinName tx, PinName rx, const char *name, int baud) : SerialBase(tx, rx, baud), Stream(name)
+{
+}
+
+Serial::Serial(PinName tx, PinName rx, int baud): SerialBase(tx, rx, baud), Stream(NULL)
+{
+}
+
+int Serial::_getc()
+{
+ // Mutex is already held
+ return _base_getc();
+}
+
+int Serial::_putc(int c)
+{
+ // Mutex is already held
+ return _base_putc(c);
+}
+
+void Serial::lock()
+{
+ _mutex.lock();
+}
+
+void Serial::unlock()
+{
+ _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Serial.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Serial.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
+
+#include "Stream.h"
+#include "SerialBase.h"
+#include "PlatformMutex.h"
+#include "serial_api.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ * pc.printf("Hello World\n");
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Serial : public SerialBase, public Stream, private NonCopyable<Serial> {
+
+public:
+#if DEVICE_SERIAL_ASYNCH
+ using SerialBase::read;
+ using SerialBase::write;
+#endif
+
+ /** Create a Serial port, connected to the specified transmit and receive pins
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ * @param name The name of the stream associated with this serial port (optional)
+ * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ Serial(PinName tx, PinName rx, const char *name = NULL, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
+
+
+ /** Create a Serial port, connected to the specified transmit and receive pins, with the specified baud
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ * @param baud The baud rate of the serial port
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ Serial(PinName tx, PinName rx, int baud);
+
+ /* Stream gives us a FileHandle with non-functional poll()/readable()/writable. Pass through
+ * the calls from the SerialBase instead for backwards compatibility. This problem is
+ * part of why Stream and Serial should be deprecated.
+ */
+ bool readable()
+ {
+ return SerialBase::readable();
+ }
+ bool writable()
+ {
+ return SerialBase::writeable();
+ }
+ bool writeable()
+ {
+ return SerialBase::writeable();
+ }
+
+protected:
+ virtual int _getc();
+ virtual int _putc(int c);
+ virtual void lock();
+ virtual void unlock();
+
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/SerialBase.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/SerialBase.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,305 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/SerialBase.h"
+#include "platform/mbed_wait_api.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_power_mgmt.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+SerialBase::SerialBase(PinName tx, PinName rx, int baud) :
+#if DEVICE_SERIAL_ASYNCH
+ _thunk_irq(this), _tx_usage(DMA_USAGE_NEVER),
+ _rx_usage(DMA_USAGE_NEVER), _tx_callback(NULL),
+ _rx_callback(NULL),
+#endif
+ _serial(), _baud(baud)
+{
+ // No lock needed in the constructor
+
+ for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
+ _irq[i] = NULL;
+ }
+
+ serial_init(&_serial, tx, rx);
+ serial_baud(&_serial, _baud);
+ serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
+}
+
+void SerialBase::baud(int baudrate)
+{
+ lock();
+ serial_baud(&_serial, baudrate);
+ _baud = baudrate;
+ unlock();
+}
+
+void SerialBase::format(int bits, Parity parity, int stop_bits)
+{
+ lock();
+ serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
+ unlock();
+}
+
+int SerialBase::readable()
+{
+ lock();
+ int ret = serial_readable(&_serial);
+ unlock();
+ return ret;
+}
+
+
+int SerialBase::writeable()
+{
+ lock();
+ int ret = serial_writable(&_serial);
+ unlock();
+ return ret;
+}
+
+void SerialBase::attach(Callback<void()> func, IrqType type)
+{
+ lock();
+ // Disable interrupts when attaching interrupt handler
+ core_util_critical_section_enter();
+ if (func) {
+ // lock deep sleep only the first time
+ if (!_irq[type]) {
+ sleep_manager_lock_deep_sleep();
+ }
+ _irq[type] = func;
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ } else {
+ // unlock deep sleep only the first time
+ if (_irq[type]) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ _irq[type] = NULL;
+ serial_irq_set(&_serial, (SerialIrq)type, 0);
+ }
+ core_util_critical_section_exit();
+ unlock();
+}
+
+void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type)
+{
+ SerialBase *handler = (SerialBase *)id;
+ if (handler->_irq[irq_type]) {
+ handler->_irq[irq_type]();
+ }
+}
+
+int SerialBase::_base_getc()
+{
+ // Mutex is already held
+ return serial_getc(&_serial);
+}
+
+int SerialBase::_base_putc(int c)
+{
+ // Mutex is already held
+ serial_putc(&_serial, c);
+ return c;
+}
+
+void SerialBase::send_break()
+{
+ lock();
+ // Wait for 1.5 frames before clearing the break condition
+ // This will have different effects on our platforms, but should
+ // ensure that we keep the break active for at least one frame.
+ // We consider a full frame (1 start bit + 8 data bits bits +
+ // 1 parity bit + 2 stop bits = 12 bits) for computation.
+ // One bit time (in us) = 1000000/_baud
+ // Twelve bits: 12000000/baud delay
+ // 1.5 frames: 18000000/baud delay
+ serial_break_set(&_serial);
+ wait_us(18000000 / _baud);
+ serial_break_clear(&_serial);
+ unlock();
+}
+
+void SerialBase::lock()
+{
+ // Stub
+}
+
+void SerialBase:: unlock()
+{
+ // Stub
+}
+
+SerialBase::~SerialBase()
+{
+ // No lock needed in destructor
+
+ // Detaching interrupts releases the sleep lock if it was locked
+ for (int irq = 0; irq < IrqCnt; irq++) {
+ attach(NULL, (IrqType)irq);
+ }
+}
+
+#if DEVICE_SERIAL_FC
+void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2)
+{
+ lock();
+ FlowControl flow_type = (FlowControl)type;
+ switch (type) {
+ case RTS:
+ serial_set_flow_control(&_serial, flow_type, flow1, NC);
+ break;
+
+ case CTS:
+ serial_set_flow_control(&_serial, flow_type, NC, flow1);
+ break;
+
+ case RTSCTS:
+ case Disabled:
+ serial_set_flow_control(&_serial, flow_type, flow1, flow2);
+ break;
+
+ default:
+ break;
+ }
+ unlock();
+}
+#endif
+
+#if DEVICE_SERIAL_ASYNCH
+
+int SerialBase::write(const uint8_t *buffer, int length, const event_callback_t &callback, int event)
+{
+ if (serial_tx_active(&_serial)) {
+ return -1; // transaction ongoing
+ }
+ start_write((void *)buffer, length, 8, callback, event);
+ return 0;
+}
+
+int SerialBase::write(const uint16_t *buffer, int length, const event_callback_t &callback, int event)
+{
+ if (serial_tx_active(&_serial)) {
+ return -1; // transaction ongoing
+ }
+ start_write((void *)buffer, length, 16, callback, event);
+ return 0;
+}
+
+void SerialBase::start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t &callback, int event)
+{
+ _tx_callback = callback;
+
+ _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+ sleep_manager_lock_deep_sleep();
+ serial_tx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, _tx_usage);
+}
+
+void SerialBase::abort_write(void)
+{
+ // rx might still be active
+ if (_rx_callback) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ _tx_callback = NULL;
+ serial_tx_abort_asynch(&_serial);
+}
+
+void SerialBase::abort_read(void)
+{
+ // tx might still be active
+ if (_tx_callback) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ _rx_callback = NULL;
+ serial_rx_abort_asynch(&_serial);
+}
+
+int SerialBase::set_dma_usage_tx(DMAUsage usage)
+{
+ if (serial_tx_active(&_serial)) {
+ return -1;
+ }
+ _tx_usage = usage;
+ return 0;
+}
+
+int SerialBase::set_dma_usage_rx(DMAUsage usage)
+{
+ if (serial_tx_active(&_serial)) {
+ return -1;
+ }
+ _rx_usage = usage;
+ return 0;
+}
+
+int SerialBase::read(uint8_t *buffer, int length, const event_callback_t &callback, int event, unsigned char char_match)
+{
+ if (serial_rx_active(&_serial)) {
+ return -1; // transaction ongoing
+ }
+ start_read((void *)buffer, length, 8, callback, event, char_match);
+ return 0;
+}
+
+
+int SerialBase::read(uint16_t *buffer, int length, const event_callback_t &callback, int event, unsigned char char_match)
+{
+ if (serial_rx_active(&_serial)) {
+ return -1; // transaction ongoing
+ }
+ start_read((void *)buffer, length, 16, callback, event, char_match);
+ return 0;
+}
+
+
+void SerialBase::start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t &callback, int event, unsigned char char_match)
+{
+ _rx_callback = callback;
+ _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+ sleep_manager_lock_deep_sleep();
+ serial_rx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, char_match, _rx_usage);
+}
+
+void SerialBase::interrupt_handler_asynch(void)
+{
+ int event = serial_irq_handler_asynch(&_serial);
+ int rx_event = event & SERIAL_EVENT_RX_MASK;
+ bool unlock_deepsleep = false;
+
+ if (_rx_callback && rx_event) {
+ unlock_deepsleep = true;
+ _rx_callback.call(rx_event);
+ }
+
+ int tx_event = event & SERIAL_EVENT_TX_MASK;
+ if (_tx_callback && tx_event) {
+ unlock_deepsleep = true;
+ _tx_callback.call(tx_event);
+ }
+ // unlock if tx or rx events are generated
+ if (unlock_deepsleep) {
+ sleep_manager_unlock_deep_sleep();
+ }
+}
+
+#endif
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/SerialBase.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/SerialBase.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIALBASE_H
+#define MBED_SERIALBASE_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
+
+#include "Callback.h"
+#include "serial_api.h"
+#include "mbed_toolchain.h"
+#include "platform/NonCopyable.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A base class for serial port implementations
+ * Can't be instantiated directly (use Serial or RawSerial)
+ *
+ * @note Synchronization level: Set by subclass
+ * @ingroup drivers
+ */
+class SerialBase : private NonCopyable<SerialBase> {
+
+public:
+ /** Set the baud rate of the serial port
+ *
+ * @param baudrate The baudrate of the serial port (default = 9600).
+ */
+ void baud(int baudrate);
+
+ enum Parity {
+ None = 0,
+ Odd,
+ Even,
+ Forced1,
+ Forced0
+ };
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq,
+
+ IrqCnt
+ };
+
+ enum Flow {
+ Disabled = 0,
+ RTS,
+ CTS,
+ RTSCTS
+ };
+
+ /** Set the transmission format used by the serial port
+ *
+ * @param bits The number of bits in a word (5-8; default = 8)
+ * @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
+ * @param stop_bits The number of stop bits (1 or 2; default = 1)
+ */
+ void format(int bits = 8, Parity parity = SerialBase::None, int stop_bits = 1);
+
+ /** Determine if there is a character available to read
+ *
+ * @returns
+ * 1 if there is a character available to read,
+ * 0 otherwise
+ */
+ int readable();
+
+ /** Determine if there is space available to write a character
+ *
+ * @returns
+ * 1 if there is space to write a character,
+ * 0 otherwise
+ */
+ int writeable();
+
+ /** Attach a function to call whenever a serial interrupt is generated
+ *
+ * @param func A pointer to a void function, or 0 to set as none
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ */
+ void attach(Callback<void()> func, IrqType type = RxIrq);
+
+ /** Attach a member function to call whenever a serial interrupt is generated
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), type).
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), type).")
+ void attach(T *obj, void (T::*method)(), IrqType type = RxIrq)
+ {
+ attach(callback(obj, method), type);
+ }
+
+ /** Attach a member function to call whenever a serial interrupt is generated
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), type).
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), type).")
+ void attach(T *obj, void (*method)(T *), IrqType type = RxIrq)
+ {
+ attach(callback(obj, method), type);
+ }
+
+ /** Generate a break condition on the serial line
+ */
+ void send_break();
+
+protected:
+
+ /** Acquire exclusive access to this serial port
+ */
+ virtual void lock(void);
+
+ /** Release exclusive access to this serial port
+ */
+ virtual void unlock(void);
+
+public:
+
+#if DEVICE_SERIAL_FC
+ /** Set the flow control type on the serial port
+ *
+ * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+ * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+ * @param flow2 the second flow control pin (CTS for RTSCTS)
+ */
+ void set_flow_control(Flow type, PinName flow1 = NC, PinName flow2 = NC);
+#endif
+
+ static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+#if DEVICE_SERIAL_ASYNCH
+
+ /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
+ *
+ * This function locks the deep sleep until any event has occurred
+ *
+ * @param buffer The buffer where received data will be stored
+ * @param length The buffer length in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of TX events
+ */
+ int write(const uint8_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+ /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
+ *
+ * This function locks the deep sleep until any event has occurred
+ *
+ * @param buffer The buffer where received data will be stored
+ * @param length The buffer length in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of TX events
+ */
+ int write(const uint16_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+ /** Abort the on-going write transfer
+ */
+ void abort_write();
+
+ /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
+ *
+ * This function locks the deep sleep until any event has occurred
+ *
+ * @param buffer The buffer where received data will be stored
+ * @param length The buffer length in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of RX events
+ * @param char_match The matching character
+ */
+ int read(uint8_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+ /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
+ *
+ * This function locks the deep sleep until any event has occurred
+ *
+ * @param buffer The buffer where received data will be stored
+ * @param length The buffer length in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of RX events
+ * @param char_match The matching character
+ */
+ int read(uint16_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+ /** Abort the on-going read transfer
+ */
+ void abort_read();
+
+ /** Configure DMA usage suggestion for non-blocking TX transfers
+ *
+ * @param usage The usage DMA hint for peripheral
+ * @return Zero if the usage was set, -1 if a transaction is on-going
+ */
+ int set_dma_usage_tx(DMAUsage usage);
+
+ /** Configure DMA usage suggestion for non-blocking RX transfers
+ *
+ * @param usage The usage DMA hint for peripheral
+ * @return Zero if the usage was set, -1 if a transaction is on-going
+ */
+ int set_dma_usage_rx(DMAUsage usage);
+
+protected:
+ void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t &callback, int event, unsigned char char_match);
+ void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t &callback, int event);
+ void interrupt_handler_asynch(void);
+#endif
+
+protected:
+ SerialBase(PinName tx, PinName rx, int baud);
+ virtual ~SerialBase();
+
+ int _base_getc();
+ int _base_putc(int c);
+
+#if DEVICE_SERIAL_ASYNCH
+ CThunk<SerialBase> _thunk_irq;
+ DMAUsage _tx_usage;
+ DMAUsage _rx_usage;
+ event_callback_t _tx_callback;
+ event_callback_t _rx_callback;
+#endif
+
+ serial_t _serial;
+ Callback<void()> _irq[IrqCnt];
+ int _baud;
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/SerialWireOutput.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/SerialWireOutput.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(DEVICE_ITM)
+
+#include "hal/itm_api.h"
+#include "platform/FileHandle.h"
+
+namespace mbed {
+
+class SerialWireOutput : public FileHandle {
+
+public:
+
+ SerialWireOutput(void)
+ {
+ /* Initialize ITM using internal init function. */
+ mbed_itm_init();
+ }
+
+ virtual ssize_t write(const void *buffer, size_t size)
+ {
+ mbed_itm_send_block(ITM_PORT_SWO, buffer, size);
+
+ return size;
+ }
+
+ virtual ssize_t read(void *buffer, size_t size)
+ {
+ /* Reading is not supported by this file handle */
+ return -EBADF;
+ }
+
+ virtual off_t seek(off_t offset, int whence = SEEK_SET)
+ {
+ /* Seeking is not support by this file handler */
+ return -ESPIPE;
+ }
+
+ virtual off_t size()
+ {
+ /* Size is not defined for this file handle */
+ return -EINVAL;
+ }
+
+ virtual int isatty()
+ {
+ /* File handle is used for terminal output */
+ return true;
+ }
+
+ virtual int close()
+ {
+ return 0;
+ }
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/TableCRC.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/TableCRC.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,147 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include "drivers/TableCRC.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+/** @{*/
+
+extern const uint8_t Table_CRC_7Bit_SD[MBED_CRC_TABLE_SIZE] = {
+ 0x0, 0x12, 0x24, 0x36, 0x48, 0x5a, 0x6c, 0x7e, 0x90, 0x82, 0xb4, 0xa6, 0xd8, 0xca, 0xfc, 0xee,
+ 0x32, 0x20, 0x16, 0x4, 0x7a, 0x68, 0x5e, 0x4c, 0xa2, 0xb0, 0x86, 0x94, 0xea, 0xf8, 0xce, 0xdc,
+ 0x64, 0x76, 0x40, 0x52, 0x2c, 0x3e, 0x8, 0x1a, 0xf4, 0xe6, 0xd0, 0xc2, 0xbc, 0xae, 0x98, 0x8a,
+ 0x56, 0x44, 0x72, 0x60, 0x1e, 0xc, 0x3a, 0x28, 0xc6, 0xd4, 0xe2, 0xf0, 0x8e, 0x9c, 0xaa, 0xb8,
+ 0xc8, 0xda, 0xec, 0xfe, 0x80, 0x92, 0xa4, 0xb6, 0x58, 0x4a, 0x7c, 0x6e, 0x10, 0x2, 0x34, 0x26,
+ 0xfa, 0xe8, 0xde, 0xcc, 0xb2, 0xa0, 0x96, 0x84, 0x6a, 0x78, 0x4e, 0x5c, 0x22, 0x30, 0x6, 0x14,
+ 0xac, 0xbe, 0x88, 0x9a, 0xe4, 0xf6, 0xc0, 0xd2, 0x3c, 0x2e, 0x18, 0xa, 0x74, 0x66, 0x50, 0x42,
+ 0x9e, 0x8c, 0xba, 0xa8, 0xd6, 0xc4, 0xf2, 0xe0, 0xe, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 0x70,
+ 0x82, 0x90, 0xa6, 0xb4, 0xca, 0xd8, 0xee, 0xfc, 0x12, 0x0, 0x36, 0x24, 0x5a, 0x48, 0x7e, 0x6c,
+ 0xb0, 0xa2, 0x94, 0x86, 0xf8, 0xea, 0xdc, 0xce, 0x20, 0x32, 0x4, 0x16, 0x68, 0x7a, 0x4c, 0x5e,
+ 0xe6, 0xf4, 0xc2, 0xd0, 0xae, 0xbc, 0x8a, 0x98, 0x76, 0x64, 0x52, 0x40, 0x3e, 0x2c, 0x1a, 0x8,
+ 0xd4, 0xc6, 0xf0, 0xe2, 0x9c, 0x8e, 0xb8, 0xaa, 0x44, 0x56, 0x60, 0x72, 0xc, 0x1e, 0x28, 0x3a,
+ 0x4a, 0x58, 0x6e, 0x7c, 0x2, 0x10, 0x26, 0x34, 0xda, 0xc8, 0xfe, 0xec, 0x92, 0x80, 0xb6, 0xa4,
+ 0x78, 0x6a, 0x5c, 0x4e, 0x30, 0x22, 0x14, 0x6, 0xe8, 0xfa, 0xcc, 0xde, 0xa0, 0xb2, 0x84, 0x96,
+ 0x2e, 0x3c, 0xa, 0x18, 0x66, 0x74, 0x42, 0x50, 0xbe, 0xac, 0x9a, 0x88, 0xf6, 0xe4, 0xd2, 0xc0,
+ 0x1c, 0xe, 0x38, 0x2a, 0x54, 0x46, 0x70, 0x62, 0x8c, 0x9e, 0xa8, 0xba, 0xc4, 0xd6, 0xe0, 0xf2
+};
+
+extern const uint8_t Table_CRC_8bit_CCITT[MBED_CRC_TABLE_SIZE] = {
+ 0x0, 0x7, 0xe, 0x9, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d,
+ 0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d,
+ 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd,
+ 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd,
+ 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea,
+ 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a,
+ 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x3, 0x4, 0xd, 0xa,
+ 0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a,
+ 0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4,
+ 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec, 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4,
+ 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44,
+ 0x19, 0x1e, 0x17, 0x10, 0x5, 0x2, 0xb, 0xc, 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34,
+ 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63,
+ 0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x6, 0x1, 0x8, 0xf, 0x1a, 0x1d, 0x14, 0x13,
+ 0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83,
+ 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3
+};
+
+extern const uint16_t Table_CRC_16bit_CCITT[MBED_CRC_TABLE_SIZE] = {
+ 0x0, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, 0x8108, 0x9129, 0xa14a, 0xb16b,
+ 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, 0x1231, 0x210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
+ 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, 0x2462, 0x3443, 0x420, 0x1401,
+ 0x64e6, 0x74c7, 0x44a4, 0x5485, 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
+ 0x3653, 0x2672, 0x1611, 0x630, 0x76d7, 0x66f6, 0x5695, 0x46b4, 0xb75b, 0xa77a, 0x9719, 0x8738,
+ 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x840, 0x1861, 0x2802, 0x3823,
+ 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, 0x5af5, 0x4ad4, 0x7ab7, 0x6a96,
+ 0x1a71, 0xa50, 0x3a33, 0x2a12, 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
+ 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0xc60, 0x1c41, 0xedae, 0xfd8f, 0xcdec, 0xddcd,
+ 0xad2a, 0xbd0b, 0x8d68, 0x9d49, 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0xe70,
+ 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, 0x9188, 0x81a9, 0xb1ca, 0xa1eb,
+ 0xd10c, 0xc12d, 0xf14e, 0xe16f, 0x1080, 0xa1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
+ 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, 0x2b1, 0x1290, 0x22f3, 0x32d2,
+ 0x4235, 0x5214, 0x6277, 0x7256, 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
+ 0x34e2, 0x24c3, 0x14a0, 0x481, 0x7466, 0x6447, 0x5424, 0x4405, 0xa7db, 0xb7fa, 0x8799, 0x97b8,
+ 0xe75f, 0xf77e, 0xc71d, 0xd73c, 0x26d3, 0x36f2, 0x691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
+ 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, 0x5844, 0x4865, 0x7806, 0x6827,
+ 0x18c0, 0x8e1, 0x3882, 0x28a3, 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
+ 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0xaf1, 0x1ad0, 0x2ab3, 0x3a92, 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d,
+ 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0xcc1,
+ 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, 0x6e17, 0x7e36, 0x4e55, 0x5e74,
+ 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0
+};
+
+extern const uint16_t Table_CRC_16bit_IBM[MBED_CRC_TABLE_SIZE] = {
+ 0x0, 0x8005, 0x800f, 0xa, 0x801b, 0x1e, 0x14, 0x8011, 0x8033, 0x36, 0x3c, 0x8039,
+ 0x28, 0x802d, 0x8027, 0x22, 0x8063, 0x66, 0x6c, 0x8069, 0x78, 0x807d, 0x8077, 0x72,
+ 0x50, 0x8055, 0x805f, 0x5a, 0x804b, 0x4e, 0x44, 0x8041, 0x80c3, 0xc6, 0xcc, 0x80c9,
+ 0xd8, 0x80dd, 0x80d7, 0xd2, 0xf0, 0x80f5, 0x80ff, 0xfa, 0x80eb, 0xee, 0xe4, 0x80e1,
+ 0xa0, 0x80a5, 0x80af, 0xaa, 0x80bb, 0xbe, 0xb4, 0x80b1, 0x8093, 0x96, 0x9c, 0x8099,
+ 0x88, 0x808d, 0x8087, 0x82, 0x8183, 0x186, 0x18c, 0x8189, 0x198, 0x819d, 0x8197, 0x192,
+ 0x1b0, 0x81b5, 0x81bf, 0x1ba, 0x81ab, 0x1ae, 0x1a4, 0x81a1, 0x1e0, 0x81e5, 0x81ef, 0x1ea,
+ 0x81fb, 0x1fe, 0x1f4, 0x81f1, 0x81d3, 0x1d6, 0x1dc, 0x81d9, 0x1c8, 0x81cd, 0x81c7, 0x1c2,
+ 0x140, 0x8145, 0x814f, 0x14a, 0x815b, 0x15e, 0x154, 0x8151, 0x8173, 0x176, 0x17c, 0x8179,
+ 0x168, 0x816d, 0x8167, 0x162, 0x8123, 0x126, 0x12c, 0x8129, 0x138, 0x813d, 0x8137, 0x132,
+ 0x110, 0x8115, 0x811f, 0x11a, 0x810b, 0x10e, 0x104, 0x8101, 0x8303, 0x306, 0x30c, 0x8309,
+ 0x318, 0x831d, 0x8317, 0x312, 0x330, 0x8335, 0x833f, 0x33a, 0x832b, 0x32e, 0x324, 0x8321,
+ 0x360, 0x8365, 0x836f, 0x36a, 0x837b, 0x37e, 0x374, 0x8371, 0x8353, 0x356, 0x35c, 0x8359,
+ 0x348, 0x834d, 0x8347, 0x342, 0x3c0, 0x83c5, 0x83cf, 0x3ca, 0x83db, 0x3de, 0x3d4, 0x83d1,
+ 0x83f3, 0x3f6, 0x3fc, 0x83f9, 0x3e8, 0x83ed, 0x83e7, 0x3e2, 0x83a3, 0x3a6, 0x3ac, 0x83a9,
+ 0x3b8, 0x83bd, 0x83b7, 0x3b2, 0x390, 0x8395, 0x839f, 0x39a, 0x838b, 0x38e, 0x384, 0x8381,
+ 0x280, 0x8285, 0x828f, 0x28a, 0x829b, 0x29e, 0x294, 0x8291, 0x82b3, 0x2b6, 0x2bc, 0x82b9,
+ 0x2a8, 0x82ad, 0x82a7, 0x2a2, 0x82e3, 0x2e6, 0x2ec, 0x82e9, 0x2f8, 0x82fd, 0x82f7, 0x2f2,
+ 0x2d0, 0x82d5, 0x82df, 0x2da, 0x82cb, 0x2ce, 0x2c4, 0x82c1, 0x8243, 0x246, 0x24c, 0x8249,
+ 0x258, 0x825d, 0x8257, 0x252, 0x270, 0x8275, 0x827f, 0x27a, 0x826b, 0x26e, 0x264, 0x8261,
+ 0x220, 0x8225, 0x822f, 0x22a, 0x823b, 0x23e, 0x234, 0x8231, 0x8213, 0x216, 0x21c, 0x8219
+};
+
+extern const uint32_t Table_CRC_32bit_ANSI[MBED_CRC_TABLE_SIZE] = {
+ 0x0, 0x4c11db7, 0x9823b6e, 0xd4326d9, 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005,
+ 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd,
+ 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75,
+ 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd,
+ 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5,
+ 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d,
+ 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95,
+ 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d,
+ 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072,
+ 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, 0x18aeb13, 0x54bf6a4, 0x808d07d, 0xcc9cdca,
+ 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02,
+ 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba,
+ 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692,
+ 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a,
+ 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2,
+ 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a,
+ 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb,
+ 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53,
+ 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b,
+ 0x315d626, 0x7d4cb91, 0xa97ed48, 0xe56f0ff, 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623,
+ 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b,
+ 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3,
+ 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b,
+ 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3,
+ 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c,
+ 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24,
+ 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, 0x29f3d35, 0x65e2082, 0xb1d065b, 0xfdc1bec,
+ 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654,
+ 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c,
+ 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4,
+ 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c,
+ 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4
+};
+
+/** @}*/
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/TableCRC.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/TableCRC.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,37 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TABLE_CRC_H
+#define TABLE_CRC_H
+
+#include <stdint.h>
+
+namespace mbed {
+/** \addtogroup drivers */
+/** @{*/
+
+#define MBED_CRC_TABLE_SIZE 256
+
+extern const uint8_t Table_CRC_7Bit_SD[MBED_CRC_TABLE_SIZE];
+extern const uint8_t Table_CRC_8bit_CCITT[MBED_CRC_TABLE_SIZE];
+extern const uint16_t Table_CRC_16bit_CCITT[MBED_CRC_TABLE_SIZE];
+extern const uint16_t Table_CRC_16bit_IBM[MBED_CRC_TABLE_SIZE];
+extern const uint32_t Table_CRC_32bit_ANSI[MBED_CRC_TABLE_SIZE];
+
+/** @}*/
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Ticker.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Ticker.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Ticker.h"
+
+#include "drivers/TimerEvent.h"
+#include "platform/FunctionPointer.h"
+#include "hal/ticker_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+void Ticker::detach()
+{
+ core_util_critical_section_enter();
+ remove();
+ // unlocked only if we were attached (we locked it) and this is not low power ticker
+ if (_function && _lock_deepsleep) {
+ sleep_manager_unlock_deep_sleep();
+ }
+
+ _function = 0;
+ core_util_critical_section_exit();
+}
+
+void Ticker::setup(us_timestamp_t t)
+{
+ core_util_critical_section_enter();
+ remove();
+ _delay = t;
+ insert_absolute(_delay + ticker_read_us(_ticker_data));
+ core_util_critical_section_exit();
+}
+
+void Ticker::handler()
+{
+ insert_absolute(event.timestamp + _delay);
+ if (_function) {
+ _function();
+ }
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Ticker.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Ticker.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_H
+#define MBED_TICKER_H
+
+#include "drivers/TimerEvent.h"
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/NonCopyable.h"
+#include "platform/mbed_power_mgmt.h"
+#include "hal/lp_ticker_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A Ticker is used to call a function at a recurring interval
+ *
+ * You can use as many separate Ticker objects as you require.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle the blinking led after 5 seconds
+ *
+ * #include "mbed.h"
+ *
+ * Ticker timer;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * int flip = 0;
+ *
+ * void attime() {
+ * flip = !flip;
+ * }
+ *
+ * int main() {
+ * timer.attach(&attime, 5);
+ * while(1) {
+ * if(flip == 0) {
+ * led1 = !led1;
+ * } else {
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Ticker : public TimerEvent, private NonCopyable<Ticker> {
+
+public:
+ Ticker() : TimerEvent(), _function(0), _lock_deepsleep(true)
+ {
+ }
+
+ // When low power ticker is in use, then do not disable deep-sleep.
+ Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0), _lock_deepsleep(true)
+ {
+#if DEVICE_LPTICKER
+ _lock_deepsleep = (data != get_lp_ticker_data());
+#endif
+ }
+
+ /** Attach a function to be called by the Ticker, specifying the interval in seconds
+ *
+ * @param func pointer to the function to be called
+ * @param t the time between calls in seconds
+ */
+ void attach(Callback<void()> func, float t)
+ {
+ attach_us(func, t * 1000000.0f);
+ }
+
+ /** Attach a member function to be called by the Ticker, specifying the interval in seconds
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param t the time between calls in seconds
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), t).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), t).")
+ void attach(T *obj, M method, float t)
+ {
+ attach(callback(obj, method), t);
+ }
+
+ /** Attach a function to be called by the Ticker, specifying the interval in micro-seconds
+ *
+ * @param func pointer to the function to be called
+ * @param t the time between calls in micro-seconds
+ *
+ * @note setting @a t to a value shorter that it takes to process the ticker callback
+ * will cause the system to hang. Ticker callback will be called constantly with no time
+ * for threads scheduling.
+ *
+ */
+ void attach_us(Callback<void()> func, us_timestamp_t t)
+ {
+ core_util_critical_section_enter();
+ // lock only for the initial callback setup and this is not low power ticker
+ if (!_function && _lock_deepsleep) {
+ sleep_manager_lock_deep_sleep();
+ }
+ _function = func;
+ setup(t);
+ core_util_critical_section_exit();
+ }
+
+ /** Attach a member function to be called by the Ticker, specifying the interval in micro-seconds
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param t the time between calls in micro-seconds
+ * @deprecated
+ * The attach_us function does not support cv-qualifiers. Replaced by
+ * attach_us(callback(obj, method), t).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach_us function does not support cv-qualifiers. Replaced by "
+ "attach_us(callback(obj, method), t).")
+ void attach_us(T *obj, M method, us_timestamp_t t)
+ {
+ attach_us(Callback<void()>(obj, method), t);
+ }
+
+ virtual ~Ticker()
+ {
+ detach();
+ }
+
+ /** Detach the function
+ */
+ void detach();
+
+protected:
+ void setup(us_timestamp_t t);
+ virtual void handler();
+
+protected:
+ us_timestamp_t _delay; /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
+ Callback<void()> _function; /**< Callback. */
+ bool _lock_deepsleep; /**< Flag which indicates if deep-sleep should be disabled. */
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Timeout.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Timeout.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,27 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Timeout.h"
+
+namespace mbed {
+
+void Timeout::handler()
+{
+ Callback<void()> local = _function;
+ detach();
+ local.call();
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Timeout.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Timeout.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEOUT_H
+#define MBED_TIMEOUT_H
+
+#include "drivers/Ticker.h"
+#include "platform/NonCopyable.h"
+#include "platform/mbed_power_mgmt.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A Timeout is used to call a function at a point in the future
+ *
+ * You can use as many seperate Timeout objects as you require.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Blink until timeout.
+ *
+ * #include "mbed.h"
+ *
+ * Timeout timeout;
+ * DigitalOut led(LED1);
+ *
+ * int on = 1;
+ *
+ * void attimeout() {
+ * on = 0;
+ * }
+ *
+ * int main() {
+ * timeout.attach(&attimeout, 5);
+ * while(on) {
+ * led = !led;
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Timeout : public Ticker, private NonCopyable<Timeout> {
+
+protected:
+ virtual void handler();
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Timer.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Timer.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Timer.h"
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+#include "platform/mbed_critical.h"
+#include "hal/lp_ticker_api.h"
+
+namespace mbed {
+
+Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()), _lock_deepsleep(true)
+{
+ reset();
+}
+
+Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data), _lock_deepsleep(true)
+{
+ reset();
+#if DEVICE_LPTICKER
+ _lock_deepsleep = (data != get_lp_ticker_data());
+#endif
+}
+
+Timer::~Timer()
+{
+ core_util_critical_section_enter();
+ if (_running) {
+ if (_lock_deepsleep) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ }
+ _running = 0;
+ core_util_critical_section_exit();
+}
+
+void Timer::start()
+{
+ core_util_critical_section_enter();
+ if (!_running) {
+ if (_lock_deepsleep) {
+ sleep_manager_lock_deep_sleep();
+ }
+ _start = ticker_read_us(_ticker_data);
+ _running = 1;
+ }
+ core_util_critical_section_exit();
+}
+
+void Timer::stop()
+{
+ core_util_critical_section_enter();
+ _time += slicetime();
+ if (_running) {
+ if (_lock_deepsleep) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ }
+ _running = 0;
+ core_util_critical_section_exit();
+}
+
+int Timer::read_us()
+{
+ return read_high_resolution_us();
+}
+
+float Timer::read()
+{
+ return (float)read_us() / 1000000.0f;
+}
+
+int Timer::read_ms()
+{
+ return read_high_resolution_us() / 1000;
+}
+
+us_timestamp_t Timer::read_high_resolution_us()
+{
+ core_util_critical_section_enter();
+ us_timestamp_t time = _time + slicetime();
+ core_util_critical_section_exit();
+ return time;
+}
+
+us_timestamp_t Timer::slicetime()
+{
+ us_timestamp_t ret = 0;
+ core_util_critical_section_enter();
+ if (_running) {
+ ret = ticker_read_us(_ticker_data) - _start;
+ }
+ core_util_critical_section_exit();
+ return ret;
+}
+
+void Timer::reset()
+{
+ core_util_critical_section_enter();
+ _start = ticker_read_us(_ticker_data);
+ _time = 0;
+ core_util_critical_section_exit();
+}
+
+Timer::operator float()
+{
+ return read();
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/Timer.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/Timer.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMER_H
+#define MBED_TIMER_H
+
+#include "platform/platform.h"
+#include "hal/ticker_api.h"
+#include "platform/NonCopyable.h"
+#include "platform/mbed_power_mgmt.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A general purpose timer
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Count the time to toggle a LED
+ *
+ * #include "mbed.h"
+ *
+ * Timer timer;
+ * DigitalOut led(LED1);
+ * int begin, end;
+ *
+ * int main() {
+ * timer.start();
+ * begin = timer.read_us();
+ * led = !led;
+ * end = timer.read_us();
+ * printf("Toggle the led takes %d us", end - begin);
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Timer : private NonCopyable<Timer> {
+
+public:
+ Timer();
+ Timer(const ticker_data_t *data);
+ ~Timer();
+
+ /** Start the timer
+ */
+ void start();
+
+ /** Stop the timer
+ */
+ void stop();
+
+ /** Reset the timer to 0.
+ *
+ * If it was already counting, it will continue
+ */
+ void reset();
+
+ /** Get the time passed in seconds
+ *
+ * @returns Time passed in seconds
+ */
+ float read();
+
+ /** Get the time passed in milli-seconds
+ *
+ * @returns Time passed in milli seconds
+ */
+ int read_ms();
+
+ /** Get the time passed in micro-seconds
+ *
+ * @returns Time passed in micro seconds
+ */
+ int read_us();
+
+ /** An operator shorthand for read()
+ */
+ operator float();
+
+ /** Get in a high resolution type the time passed in micro-seconds.
+ */
+ us_timestamp_t read_high_resolution_us();
+
+protected:
+ us_timestamp_t slicetime();
+ int _running; // whether the timer is running
+ us_timestamp_t _start; // the start time of the latest slice
+ us_timestamp_t _time; // any accumulated time from previous slices
+ const ticker_data_t *_ticker_data;
+ bool _lock_deepsleep; // flag which indicates if deep-sleep should be disabled
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/TimerEvent.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/TimerEvent.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/TimerEvent.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+
+namespace mbed {
+
+TimerEvent::TimerEvent() : event(), _ticker_data(get_us_ticker_data())
+{
+ ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+TimerEvent::TimerEvent(const ticker_data_t *data) : event(), _ticker_data(data)
+{
+ ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+void TimerEvent::irq(uint32_t id)
+{
+ TimerEvent *timer_event = (TimerEvent *)id;
+ timer_event->handler();
+}
+
+TimerEvent::~TimerEvent()
+{
+ remove();
+}
+
+// insert in to linked list
+void TimerEvent::insert(timestamp_t timestamp)
+{
+ ticker_insert_event(_ticker_data, &event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::insert_absolute(us_timestamp_t timestamp)
+{
+ ticker_insert_event_us(_ticker_data, &event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::remove()
+{
+ ticker_remove_event(_ticker_data, &event);
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/TimerEvent.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/TimerEvent.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,84 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEREVENT_H
+#define MBED_TIMEREVENT_H
+
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Base abstraction for timer interrupts
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class TimerEvent : private NonCopyable<TimerEvent> {
+public:
+ TimerEvent();
+ TimerEvent(const ticker_data_t *data);
+
+ /** The handler registered with the underlying timer interrupt
+ *
+ * @param id Timer Event ID
+ */
+ static void irq(uint32_t id);
+
+ /** Destruction removes it...
+ */
+ virtual ~TimerEvent();
+
+protected:
+ // The handler called to service the timer event of the derived class
+ virtual void handler() = 0;
+
+ /** Set relative timestamp of the internal event.
+ * @param timestamp event's us timestamp
+ *
+ * @warning
+ * Do not insert more than one timestamp.
+ * The same @a event object is used for every @a insert/insert_absolute call.
+ *
+ * @warning
+ * Ticker's present timestamp is used for reference. For timestamps
+ * from the past the event is scheduled after ticker's overflow.
+ * For reference @see convert_timestamp
+ */
+ void insert(timestamp_t timestamp);
+
+ /** Set absolute timestamp of the internal event.
+ * @param timestamp event's us timestamp
+ *
+ * @warning
+ * Do not insert more than one timestamp.
+ * The same @a event object is used for every @a insert/insert_absolute call.
+ */
+ void insert_absolute(us_timestamp_t timestamp);
+
+ /** Remove timestamp.
+ */
+ void remove();
+
+ ticker_event_t event;
+
+ const ticker_data_t *_ticker_data;
+};
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/UARTSerial.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/UARTSerial.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,342 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if (DEVICE_SERIAL && DEVICE_INTERRUPTIN)
+
+#include <errno.h>
+#include "UARTSerial.h"
+#include "platform/mbed_poll.h"
+
+#if MBED_CONF_RTOS_PRESENT
+#include "rtos/Thread.h"
+#else
+#include "platform/mbed_wait_api.h"
+#endif
+
+namespace mbed {
+
+UARTSerial::UARTSerial(PinName tx, PinName rx, int baud) :
+ SerialBase(tx, rx, baud),
+ _blocking(true),
+ _tx_irq_enabled(false),
+ _rx_irq_enabled(true),
+ _dcd_irq(NULL)
+{
+ /* Attatch IRQ routines to the serial device. */
+ SerialBase::attach(callback(this, &UARTSerial::rx_irq), RxIrq);
+}
+
+UARTSerial::~UARTSerial()
+{
+ delete _dcd_irq;
+}
+
+void UARTSerial::dcd_irq()
+{
+ wake();
+}
+
+void UARTSerial::set_baud(int baud)
+{
+ SerialBase::baud(baud);
+}
+
+void UARTSerial::set_data_carrier_detect(PinName dcd_pin, bool active_high)
+{
+ delete _dcd_irq;
+ _dcd_irq = NULL;
+
+ if (dcd_pin != NC) {
+ _dcd_irq = new InterruptIn(dcd_pin);
+ if (active_high) {
+ _dcd_irq->fall(callback(this, &UARTSerial::dcd_irq));
+ } else {
+ _dcd_irq->rise(callback(this, &UARTSerial::dcd_irq));
+ }
+ }
+}
+
+void UARTSerial::set_format(int bits, Parity parity, int stop_bits)
+{
+ api_lock();
+ SerialBase::format(bits, parity, stop_bits);
+ api_unlock();
+}
+
+#if DEVICE_SERIAL_FC
+void UARTSerial::set_flow_control(Flow type, PinName flow1, PinName flow2)
+{
+ api_lock();
+ SerialBase::set_flow_control(type, flow1, flow2);
+ api_unlock();
+}
+#endif
+
+int UARTSerial::close()
+{
+ /* Does not let us pass a file descriptor. So how to close ?
+ * Also, does it make sense to close a device type file descriptor*/
+ return 0;
+}
+
+int UARTSerial::isatty()
+{
+ return 1;
+
+}
+
+off_t UARTSerial::seek(off_t offset, int whence)
+{
+ /*XXX lseek can be done theoratically, but is it sane to mark positions on a dynamically growing/shrinking
+ * buffer system (from an interrupt context) */
+ return -ESPIPE;
+}
+
+int UARTSerial::sync()
+{
+ api_lock();
+
+ while (!_txbuf.empty()) {
+ api_unlock();
+ // Doing better than wait would require TxIRQ to also do wake() when becoming empty. Worth it?
+ wait_ms(1);
+ api_lock();
+ }
+
+ api_unlock();
+
+ return 0;
+}
+
+void UARTSerial::sigio(Callback<void()> func)
+{
+ core_util_critical_section_enter();
+ _sigio_cb = func;
+ if (_sigio_cb) {
+ short current_events = poll(0x7FFF);
+ if (current_events) {
+ _sigio_cb();
+ }
+ }
+ core_util_critical_section_exit();
+}
+
+ssize_t UARTSerial::write(const void *buffer, size_t length)
+{
+ size_t data_written = 0;
+ const char *buf_ptr = static_cast<const char *>(buffer);
+
+ if (length == 0) {
+ return 0;
+ }
+
+ api_lock();
+
+ // Unlike read, we should write the whole thing if blocking. POSIX only
+ // allows partial as a side-effect of signal handling; it normally tries to
+ // write everything if blocking. Without signals we can always write all.
+ while (data_written < length) {
+
+ if (_txbuf.full()) {
+ if (!_blocking) {
+ break;
+ }
+ do {
+ api_unlock();
+ wait_ms(1); // XXX todo - proper wait, WFE for non-rtos ?
+ api_lock();
+ } while (_txbuf.full());
+ }
+
+ while (data_written < length && !_txbuf.full()) {
+ _txbuf.push(*buf_ptr++);
+ data_written++;
+ }
+
+ core_util_critical_section_enter();
+ if (!_tx_irq_enabled) {
+ UARTSerial::tx_irq(); // only write to hardware in one place
+ if (!_txbuf.empty()) {
+ SerialBase::attach(callback(this, &UARTSerial::tx_irq), TxIrq);
+ _tx_irq_enabled = true;
+ }
+ }
+ core_util_critical_section_exit();
+ }
+
+ api_unlock();
+
+ return data_written != 0 ? (ssize_t) data_written : (ssize_t) - EAGAIN;
+}
+
+ssize_t UARTSerial::read(void *buffer, size_t length)
+{
+ size_t data_read = 0;
+
+ char *ptr = static_cast<char *>(buffer);
+
+ if (length == 0) {
+ return 0;
+ }
+
+ api_lock();
+
+ while (_rxbuf.empty()) {
+ if (!_blocking) {
+ api_unlock();
+ return -EAGAIN;
+ }
+ api_unlock();
+ wait_ms(1); // XXX todo - proper wait, WFE for non-rtos ?
+ api_lock();
+ }
+
+ while (data_read < length && !_rxbuf.empty()) {
+ _rxbuf.pop(*ptr++);
+ data_read++;
+ }
+
+ core_util_critical_section_enter();
+ if (!_rx_irq_enabled) {
+ UARTSerial::rx_irq(); // only read from hardware in one place
+ if (!_rxbuf.full()) {
+ SerialBase::attach(callback(this, &UARTSerial::rx_irq), RxIrq);
+ _rx_irq_enabled = true;
+ }
+ }
+ core_util_critical_section_exit();
+
+ api_unlock();
+
+ return data_read;
+}
+
+bool UARTSerial::hup() const
+{
+ return _dcd_irq && _dcd_irq->read() != 0;
+}
+
+void UARTSerial::wake()
+{
+ if (_sigio_cb) {
+ _sigio_cb();
+ }
+}
+
+short UARTSerial::poll(short events) const
+{
+
+ short revents = 0;
+ /* Check the Circular Buffer if space available for writing out */
+
+
+ if (!_rxbuf.empty()) {
+ revents |= POLLIN;
+ }
+
+ /* POLLHUP and POLLOUT are mutually exclusive */
+ if (hup()) {
+ revents |= POLLHUP;
+ } else if (!_txbuf.full()) {
+ revents |= POLLOUT;
+ }
+
+ /*TODO Handle other event types */
+
+ return revents;
+}
+
+void UARTSerial::lock()
+{
+ // This is the override for SerialBase.
+ // No lock required as we only use SerialBase from interrupt or from
+ // inside our own critical section.
+}
+
+void UARTSerial::unlock()
+{
+ // This is the override for SerialBase.
+}
+
+void UARTSerial::api_lock(void)
+{
+ _mutex.lock();
+}
+
+void UARTSerial::api_unlock(void)
+{
+ _mutex.unlock();
+}
+
+void UARTSerial::rx_irq(void)
+{
+ bool was_empty = _rxbuf.empty();
+
+ /* Fill in the receive buffer if the peripheral is readable
+ * and receive buffer is not full. */
+ while (!_rxbuf.full() && SerialBase::readable()) {
+ char data = SerialBase::_base_getc();
+ _rxbuf.push(data);
+ }
+
+ if (_rx_irq_enabled && _rxbuf.full()) {
+ SerialBase::attach(NULL, RxIrq);
+ _rx_irq_enabled = false;
+ }
+
+ /* Report the File handler that data is ready to be read from the buffer. */
+ if (was_empty && !_rxbuf.empty()) {
+ wake();
+ }
+}
+
+// Also called from write to start transfer
+void UARTSerial::tx_irq(void)
+{
+ bool was_full = _txbuf.full();
+ char data;
+
+ /* Write to the peripheral if there is something to write
+ * and if the peripheral is available to write. */
+ while (SerialBase::writeable() && _txbuf.pop(data)) {
+ SerialBase::_base_putc(data);
+ }
+
+ if (_tx_irq_enabled && _txbuf.empty()) {
+ SerialBase::attach(NULL, TxIrq);
+ _tx_irq_enabled = false;
+ }
+
+ /* Report the File handler that data can be written to peripheral. */
+ if (was_full && !_txbuf.full() && !hup()) {
+ wake();
+ }
+}
+
+void UARTSerial::wait_ms(uint32_t millisec)
+{
+ /* wait_ms implementation for RTOS spins until exact microseconds - we
+ * want to just sleep until next tick.
+ */
+#if MBED_CONF_RTOS_PRESENT
+ rtos::Thread::wait(millisec);
+#else
+ ::wait_ms(millisec);
+#endif
+}
+} //namespace mbed
+
+#endif //(DEVICE_SERIAL && DEVICE_INTERRUPTIN)
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/UARTSerial.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/UARTSerial.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,279 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_UARTSERIAL_H
+#define MBED_UARTSERIAL_H
+
+#include "platform/platform.h"
+
+#if (DEVICE_SERIAL && DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY)
+
+#include "FileHandle.h"
+#include "SerialBase.h"
+#include "InterruptIn.h"
+#include "PlatformMutex.h"
+#include "serial_api.h"
+#include "CircularBuffer.h"
+#include "platform/NonCopyable.h"
+
+#ifndef MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE
+#define MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE 256
+#endif
+
+#ifndef MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE
+#define MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE 256
+#endif
+
+namespace mbed {
+
+/** \addtogroup drivers */
+
+/** Class providing buffered UART communication functionality using separate circular buffer for send and receive channels
+ *
+ * @ingroup drivers
+ */
+
+class UARTSerial : private SerialBase, public FileHandle, private NonCopyable<UARTSerial> {
+
+public:
+
+ /** Create a UARTSerial port, connected to the specified transmit and receive pins, with a particular baud rate.
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
+ */
+ UARTSerial(PinName tx, PinName rx, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
+ virtual ~UARTSerial();
+
+ /** Equivalent to POSIX poll(). Derived from FileHandle.
+ * Provides a mechanism to multiplex input/output over a set of file handles.
+ */
+ virtual short poll(short events) const;
+
+ /* Resolve ambiguities versus our private SerialBase
+ * (for writable, spelling differs, but just in case)
+ */
+ using FileHandle::readable;
+ using FileHandle::writable;
+
+ /** Write the contents of a buffer to a file
+ *
+ * Follows POSIX semantics:
+ *
+ * * if blocking, block until all data is written
+ * * if no data can be written, and non-blocking set, return -EAGAIN
+ * * if some data can be written, and non-blocking set, write partial
+ *
+ * @param buffer The buffer to write from
+ * @param length The number of bytes to write
+ * @return The number of bytes written, negative error on failure
+ */
+ virtual ssize_t write(const void *buffer, size_t length);
+
+ /** Read the contents of a file into a buffer
+ *
+ * Follows POSIX semantics:
+ *
+ * * if no data is available, and non-blocking set return -EAGAIN
+ * * if no data is available, and blocking set, wait until data is available
+ * * If any data is available, call returns immediately
+ *
+ * @param buffer The buffer to read in to
+ * @param length The number of bytes to read
+ * @return The number of bytes read, 0 at end of file, negative error on failure
+ */
+ virtual ssize_t read(void *buffer, size_t length);
+
+ /** Close a file
+ *
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int close();
+
+ /** Check if the file in an interactive terminal device
+ *
+ * @return True if the file is a terminal
+ * @return False if the file is not a terminal
+ * @return Negative error code on failure
+ */
+ virtual int isatty();
+
+ /** Move the file position to a given offset from from a given location
+ *
+ * Not valid for a device type FileHandle like UARTSerial.
+ * In case of UARTSerial, returns ESPIPE
+ *
+ * @param offset The offset from whence to move to
+ * @param whence The start of where to seek
+ * SEEK_SET to start from beginning of file,
+ * SEEK_CUR to start from current position in file,
+ * SEEK_END to start from end of file
+ * @return The new offset of the file, negative error code on failure
+ */
+ virtual off_t seek(off_t offset, int whence);
+
+ /** Flush any buffers associated with the file
+ *
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int sync();
+
+ /** Set blocking or non-blocking mode
+ * The default is blocking.
+ *
+ * @param blocking true for blocking mode, false for non-blocking mode.
+ */
+ virtual int set_blocking(bool blocking)
+ {
+ _blocking = blocking;
+ return 0;
+ }
+
+ /** Check current blocking or non-blocking mode for file operations.
+ *
+ * @return true for blocking mode, false for non-blocking mode.
+ */
+ virtual bool is_blocking() const
+ {
+ return _blocking;
+ }
+
+ /** Register a callback on state change of the file.
+ *
+ * The specified callback will be called on state changes such as when
+ * the file can be written to or read from.
+ *
+ * The callback may be called in an interrupt context and should not
+ * perform expensive operations.
+ *
+ * Note! This is not intended as an attach-like asynchronous api, but rather
+ * as a building block for constructing such functionality.
+ *
+ * The exact timing of when the registered function
+ * is called is not guaranteed and susceptible to change. It should be used
+ * as a cue to make read/write/poll calls to find the current state.
+ *
+ * @param func Function to call on state change
+ */
+ virtual void sigio(Callback<void()> func);
+
+ /** Setup interrupt handler for DCD line
+ *
+ * If DCD line is connected, an IRQ handler will be setup.
+ * Does nothing if DCD is NC, i.e., not connected.
+ *
+ * @param dcd_pin Pin-name for DCD
+ * @param active_high a boolean set to true if DCD polarity is active low
+ */
+ void set_data_carrier_detect(PinName dcd_pin, bool active_high = false);
+
+ /** Set the baud rate
+ *
+ * @param baud The baud rate
+ */
+ void set_baud(int baud);
+
+ // Expose private SerialBase::Parity as UARTSerial::Parity
+ using SerialBase::Parity;
+ // In C++11, we wouldn't need to also have using directives for each value
+ using SerialBase::None;
+ using SerialBase::Odd;
+ using SerialBase::Even;
+ using SerialBase::Forced1;
+ using SerialBase::Forced0;
+
+ /** Set the transmission format used by the serial port
+ *
+ * @param bits The number of bits in a word (5-8; default = 8)
+ * @param parity The parity used (None, Odd, Even, Forced1, Forced0; default = None)
+ * @param stop_bits The number of stop bits (1 or 2; default = 1)
+ */
+ void set_format(int bits = 8, Parity parity = UARTSerial::None, int stop_bits = 1);
+
+#if DEVICE_SERIAL_FC
+ // For now use the base enum - but in future we may have extra options
+ // such as XON/XOFF or manual GPIO RTSCTS.
+ using SerialBase::Flow;
+ // In C++11, we wouldn't need to also have using directives for each value
+ using SerialBase::Disabled;
+ using SerialBase::RTS;
+ using SerialBase::CTS;
+ using SerialBase::RTSCTS;
+
+ /** Set the flow control type on the serial port
+ *
+ * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+ * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+ * @param flow2 the second flow control pin (CTS for RTSCTS)
+ */
+ void set_flow_control(Flow type, PinName flow1 = NC, PinName flow2 = NC);
+#endif
+
+private:
+
+ void wait_ms(uint32_t millisec);
+
+ /** SerialBase lock override */
+ virtual void lock(void);
+
+ /** SerialBase unlock override */
+ virtual void unlock(void);
+
+ /** Acquire mutex */
+ virtual void api_lock(void);
+
+ /** Release mutex */
+ virtual void api_unlock(void);
+
+ /** Software serial buffers
+ * By default buffer size is 256 for TX and 256 for RX. Configurable through mbed_app.json
+ */
+ CircularBuffer<char, MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE> _rxbuf;
+ CircularBuffer<char, MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE> _txbuf;
+
+ PlatformMutex _mutex;
+
+ Callback<void()> _sigio_cb;
+
+ bool _blocking;
+ bool _tx_irq_enabled;
+ bool _rx_irq_enabled;
+ InterruptIn *_dcd_irq;
+
+ /** Device Hanged up
+ * Determines if the device hanged up on us.
+ *
+ * @return True, if hanged up
+ */
+ bool hup() const;
+
+ /** ISRs for serial
+ * Routines to handle interrupts on serial pins.
+ * Copies data into Circular Buffer.
+ * Reports the state change to File handle.
+ */
+ void tx_irq(void);
+ void rx_irq(void);
+
+ void wake(void);
+
+ void dcd_irq(void);
+
+};
+} //namespace mbed
+
+#endif //(DEVICE_SERIAL && DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY)
+#endif //MBED_UARTSERIAL_H
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/drivers/mbed_lib.json
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/drivers/mbed_lib.json Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,13 @@
+{
+ "name": "drivers",
+ "config": {
+ "uart-serial-txbuf-size": {
+ "help": "Default TX buffer size for a UARTSerial instance (unit Bytes))",
+ "value": 256
+ },
+ "uart-serial-rxbuf-size": {
+ "help": "Default RX buffer size for a UARTSerial instance (unit Bytes))",
+ "value": 256
+ }
+ }
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,263 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "flash_data.h"
+#include "mbed_critical.h"
+#include "mbed_toolchain.h"
+
+#ifndef DOMAIN_NS
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#include <arm_cmse.h>
+#endif
+
+#define MBED_FLASH_ALGO_ERASE 1UL
+#define MBED_FLASH_ALGO_PROGRAM 2UL
+
+extern uint32_t SystemCoreClock;
+
+/*
+ This binary blob (thumb code) sets r9 (static base) as the code we are jumping to
+ is PIC (position independent code).
+
+ These are the instructions (r0 is a pointer to arg_t):
+ push {r5, lr, r4}
+ mov r5, r9
+ push {r5}
+ ldr r5, [r0, #20]
+ ldr r3, [r0, #16]
+ mov r9, r3
+ ldr r3, [r0, #12]
+ ldr r2, [r0, #8]
+ ldr r1, [r0, #4]
+ ldr r0, [r0, #0]
+ blx r5
+ pop {r5}
+ mov r9, r5
+ pop {r4-r5, pc}
+ bx r14
+*/
+static uint32_t jump_to_flash_algo[] = {
+ 0x464DB530,
+ 0x6945B420,
+ 0x46996903,
+ 0x688268C3,
+ 0x68006841,
+ 0xBC2047A8,
+ 0xBD3046A9
+};
+
+// should be called within critical section
+static int32_t flash_algo_init(flash_t *obj, uint32_t address, uint32_t function)
+{
+ args_t arguments = {
+ .r0 = address,
+ .r1 = SystemCoreClock,
+ .r2 = function,
+ .r3 = 0,
+ .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+ .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->init
+ };
+ return ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+}
+
+// should be called within critical section
+static int32_t flash_algo_uninit(flash_t *obj, uint32_t address, uint32_t function)
+{
+ args_t arguments = {
+ .r0 = address,
+ .r1 = SystemCoreClock,
+ .r2 = function,
+ .r3 = 0,
+ .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+ .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->uninit
+ };
+ return ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/* Check if address range [start_addr, end_addr] is in non-secure flash
+ *
+ * @param obj The flash object
+ * @param start_addr Start address to check
+ * @param end_addr End address to check. Could be the same as start_addr to just check start_addr
+ * for e.g. flash_erase_sector.
+ * @return 0 for success, -1 for error
+ */
+static int32_t flash_check_nonsecure(flash_t *obj, uint32_t start_addr, uint32_t end_addr)
+{
+ /* Check if end address wraps around */
+ if (end_addr < start_addr) {
+ return -1;
+ }
+
+ /* Check if start address is in non-secure flash */
+ if ((start_addr < obj->target_config_ns->flash_start) ||
+ (start_addr >= (obj->target_config_ns->flash_start + obj->target_config_ns->flash_size))) {
+ return -1;
+ }
+
+ /* Check if end address is in non-secure flash */
+ if (end_addr != start_addr) {
+ if ((end_addr < obj->target_config_ns->flash_start) ||
+ (end_addr >= (obj->target_config_ns->flash_start + obj->target_config_ns->flash_size))) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+MBED_NONSECURE_ENTRY int32_t flash_init(flash_t *obj)
+{
+ flash_set_target_config(obj);
+ return 0;
+}
+
+MBED_NONSECURE_ENTRY int32_t flash_free(flash_t *obj)
+{
+ return 0;
+}
+
+MBED_NONSECURE_ENTRY int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (cmse_nonsecure_caller()) {
+ // Confine non-secure access to non-secure flash
+ if (flash_check_nonsecure(obj, address, address)) {
+ return -1;
+ }
+ }
+#endif
+
+ core_util_critical_section_enter();
+ flash_algo_init(obj, address, MBED_FLASH_ALGO_ERASE);
+
+ args_t arguments = {
+ .r0 = address,
+ .r1 = 0,
+ .r2 = 0,
+ .r3 = 0,
+ .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+ .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->erase_sector
+ };
+ int32_t ret = ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+
+ flash_algo_uninit(obj, address, MBED_FLASH_ALGO_ERASE);
+ core_util_critical_section_exit();
+ return ret ? -1 : 0;
+}
+
+MBED_NONSECURE_ENTRY int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (cmse_nonsecure_caller()) {
+ // Confine non-secure access to non-secure flash
+ if (flash_check_nonsecure(obj, address, address + size - 1)) {
+ return -1;
+ }
+ }
+#endif
+
+ core_util_critical_section_enter();
+ flash_algo_init(obj, address, MBED_FLASH_ALGO_PROGRAM);
+
+ args_t arguments = {
+ .r0 = address,
+ .r1 = size,
+ .r2 = (uint32_t)data,
+ .r3 = 0,
+ .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+ .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->program_page
+ };
+ int32_t ret = ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+
+ flash_algo_uninit(obj, address, MBED_FLASH_ALGO_PROGRAM);
+ core_util_critical_section_exit();
+ return ret ? -1 : 0;
+}
+
+MBED_NONSECURE_ENTRY uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (cmse_nonsecure_caller()) {
+ const sector_info_t *sectors = obj->target_config_ns->sectors;
+
+ if (address >= obj->target_config_ns->flash_start + obj->target_config_ns->flash_size) {
+ return MBED_FLASH_INVALID_SIZE;
+ }
+
+ int sector_index = obj->target_config_ns->sector_info_count - 1;
+ for (; sector_index >= 0; sector_index--) {
+ if (address >= sectors[sector_index].start) {
+ return sectors[sector_index].size;
+ }
+ }
+ return MBED_FLASH_INVALID_SIZE;
+ }
+#endif
+
+ const sector_info_t *sectors = obj->target_config->sectors;
+
+ if (address >= obj->target_config->flash_start + obj->target_config->flash_size) {
+ return MBED_FLASH_INVALID_SIZE;
+ }
+
+ int sector_index = obj->target_config->sector_info_count - 1;
+ for (; sector_index >= 0; sector_index--) {
+ if (address >= sectors[sector_index].start) {
+ return sectors[sector_index].size;
+ }
+ }
+ return MBED_FLASH_INVALID_SIZE;
+}
+
+MBED_NONSECURE_ENTRY uint32_t flash_get_page_size(const flash_t *obj)
+{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (cmse_nonsecure_caller()) {
+ return obj->target_config_ns->page_size;
+ }
+#endif
+
+ return obj->target_config->page_size;
+}
+
+MBED_NONSECURE_ENTRY uint32_t flash_get_start_address(const flash_t *obj)
+{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (cmse_nonsecure_caller()) {
+ return obj->target_config_ns->flash_start;
+ }
+#endif
+
+ return obj->target_config->flash_start;
+}
+
+MBED_NONSECURE_ENTRY uint32_t flash_get_size(const flash_t *obj)
+{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ if (cmse_nonsecure_caller()) {
+ return obj->target_config_ns->flash_size;
+ }
+#endif
+
+ return obj->target_config->flash_size;
+}
+
+#endif // #ifndef DOMAIN_NS
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FLASH_DATA_H
+#define MBED_FLASH_DATA_H
+
+#include <stdint.h>
+
+/** Target flash algorithm structure
+ */
+typedef struct {
+ const uint32_t init; /**< Init function address */
+ const uint32_t uninit; /**< Uninit function address */
+ const uint32_t erase_sector; /**< Erase sector function address */
+ const uint32_t program_page; /**< Program page function address */
+ const uint32_t static_base; /**< Static base address */
+ uint32_t *algo_blob; /**< Pointer to flash algo binary blob */
+} flash_algo_t;
+
+/** Sector information structure
+ */
+typedef struct {
+ const uint32_t start; /**< Sector start address */
+ const uint32_t size; /**< Sector size */
+} sector_info_t;
+
+/** Flash configuration structure
+ */
+typedef struct {
+ const uint32_t page_size; /**< The minimum program page size that can be written */
+ const uint32_t flash_start; /**< Start address of the flash <0, flash_size) */
+ const uint32_t flash_size; /**< Flash size. The size is accumulative sum of all sector sizes */
+ const sector_info_t *sectors; /**< List of sectors - sector can vary in sizes */
+ const uint32_t sector_info_count; /**< Number of sectors */
+} flash_target_config_t;
+
+/** Target flash configuration
+ * For targets not supporting TrustZone, its flash_set_target_config must define target_config.
+ * For targets supporting TrustZone, it has the following requirements:
+ * -# Flash IAP H/W can only configure to secure. It can access both secure/non-secure flash.
+ * -# Flash IAP port is for secure build only. It exports secure functions for non-secure build.
+ * -# In Flash IAP port, flash_set_target_config must define both target_config/target_config_ns for secure/non-secure flash respectively.
+ * -# Non-secure application can access its non-secure flash only through secure flash IAP functions. It cannot access secure flash.
+ */
+struct flash_s {
+ const flash_target_config_t *target_config; /**< Normal/secure flash configuration structure for targets not supporting/supporting TrustZone */
+#if defined(__CORTEX_M23) || defined(__CORTEX_M33)
+ const flash_target_config_t *target_config_ns; /**< Non-secure flash configuration structure for targets supporting TrustZone */
+#endif
+ const flash_algo_t *flash_algo;
+};
+
+/** Flash algo argument structure
+ * Contains all registers that should be preserved
+ */
+typedef struct {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r9;
+ uint32_t pc;
+} args_t;
+
+typedef int32_t (*flash_algo_jump_t)(args_t *);
+
+// prototypes for flash algo CMSIS API
+
+typedef int (*CMSIS_Algo_Function_Init)(unsigned long adr, unsigned long clk, unsigned long fnc);
+typedef int (*CMSIS_Algo_Function_UnInit)(unsigned long fnc);
+typedef int (*CMSIS_Algo_Function_EraseSector)(unsigned long adr);
+typedef int (*CMSIS_Algo_Function_EraseChip)(void);
+typedef int (*CMSIS_Algo_Function_ProgramPage)(unsigned long adr, unsigned long sz, unsigned char *buf);
+typedef unsigned long (*CMSIS_Algo_Function_Verify)(unsigned long adr, unsigned long sz, unsigned char *buf);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set target configuration
+ */
+void flash_set_target_config(flash_t *obj);
+
+#ifdef __cplusplus
+};
+#endif
+
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/analogin_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/analogin_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,71 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_API_H
+#define MBED_ANALOGIN_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Analogin hal structure. analogin_s is declared in the target's hal
+ */
+typedef struct analogin_s analogin_t;
+
+/**
+ * \defgroup hal_analogin Analogin hal functions
+ * @{
+ */
+
+/** Initialize the analogin peripheral
+ *
+ * Configures the pin used by analogin.
+ * @param obj The analogin object to initialize
+ * @param pin The analogin pin name
+ */
+void analogin_init(analogin_t *obj, PinName pin);
+
+/** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @param obj The analogin object
+ * @return A floating value representing the current input voltage
+ */
+float analogin_read(analogin_t *obj);
+
+/** Read the value from analogin pin, represented as an unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16bit value representing the current input voltage
+ */
+uint16_t analogin_read_u16(analogin_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/analogout_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/analogout_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,93 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_API_H
+#define MBED_ANALOGOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Analogout hal structure. dac_s is declared in the target's hal
+ */
+typedef struct dac_s dac_t;
+
+/**
+ * \defgroup hal_analogout Analogout hal functions
+ * @{
+ */
+
+/** Initialize the analogout peripheral
+ *
+ * Configures the pin used by analogout.
+ * @param obj The analogout object to initialize
+ * @param pin The analogout pin name
+ */
+void analogout_init(dac_t *obj, PinName pin);
+
+/** Release the analogout object
+ *
+ * Note: This is not currently used in the mbed-drivers
+ * @param obj The analogout object
+ */
+void analogout_free(dac_t *obj);
+
+/** Set the output voltage, specified as a percentage (float)
+ *
+ * @param obj The analogin object
+ * @param value The floating-point output voltage to be set
+ */
+void analogout_write(dac_t *obj, float value);
+
+/** Set the output voltage, specified as unsigned 16-bit
+ *
+ * @param obj The analogin object
+ * @param value The unsigned 16-bit output voltage to be set
+ */
+void analogout_write_u16(dac_t *obj, uint16_t value);
+
+/** Read the current voltage value on the pin
+ *
+ * @param obj The analogin object
+ * @return A floating-point value representing the current voltage on the pin,
+ * measured as a percentage
+ */
+float analogout_read(dac_t *obj);
+
+/** Read the current voltage value on the pin, as a normalized unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16-bit value representing the current voltage on the pin
+ */
+uint16_t analogout_read_u16(dac_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/buffer.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/buffer.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,35 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUFFER_H
+#define MBED_BUFFER_H
+
+#include <stddef.h>
+
+/** Generic buffer structure
+ */
+typedef struct buffer_s {
+ void *buffer; /**< the pointer to a buffer */
+ size_t length; /**< the buffer length */
+ size_t pos; /**< actual buffer position */
+ uint8_t width; /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
+} buffer_t;
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/can_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/can_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,86 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_API_H
+#define MBED_CAN_API_H
+
+#include "device.h"
+
+#if DEVICE_CAN
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "hal/can_helper.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ IRQ_RX,
+ IRQ_TX,
+ IRQ_ERROR,
+ IRQ_OVERRUN,
+ IRQ_WAKEUP,
+ IRQ_PASSIVE,
+ IRQ_ARB,
+ IRQ_BUS,
+ IRQ_READY
+} CanIrqType;
+
+
+typedef enum {
+ MODE_RESET,
+ MODE_NORMAL,
+ MODE_SILENT,
+ MODE_TEST_LOCAL,
+ MODE_TEST_GLOBAL,
+ MODE_TEST_SILENT
+} CanMode;
+
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
+
+typedef struct can_s can_t;
+
+void can_init(can_t *obj, PinName rd, PinName td);
+void can_init_freq(can_t *obj, PinName rd, PinName td, int hz);
+void can_free(can_t *obj);
+int can_frequency(can_t *obj, int hz);
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id);
+void can_irq_free(can_t *obj);
+void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable);
+
+int can_write(can_t *obj, CAN_Message, int cc);
+int can_read(can_t *obj, CAN_Message *msg, int handle);
+int can_mode(can_t *obj, CanMode mode);
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
+void can_reset(can_t *obj);
+unsigned char can_rderror(can_t *obj);
+unsigned char can_tderror(can_t *obj);
+void can_monitor(can_t *obj, int silent);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif // MBED_CAN_API_H
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/can_helper.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/can_helper.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,77 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_HELPER_H
+#define MBED_CAN_HELPER_H
+
+#if DEVICE_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *
+ * \enum CANFormat
+ *
+ * \brief Values that represent CAN Format
+**/
+enum CANFormat {
+ CANStandard = 0,
+ CANExtended = 1,
+ CANAny = 2
+};
+typedef enum CANFormat CANFormat;
+
+/**
+ *
+ * \enum CANType
+ *
+ * \brief Values that represent CAN Type
+**/
+enum CANType {
+ CANData = 0,
+ CANRemote = 1
+};
+typedef enum CANType CANType;
+
+/**
+ *
+ * \struct CAN_Message
+ *
+ * \brief Holder for single CAN message.
+ *
+**/
+struct CAN_Message {
+ unsigned int id; // 29 bit identifier
+ unsigned char data[8]; // Data field
+ unsigned char len; // Length of data field in bytes
+ CANFormat format; // Format ::CANFormat
+ CANType type; // Type ::CANType
+};
+typedef struct CAN_Message CAN_Message;
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+#endif // MBED_CAN_HELPER_H
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/crc_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/crc_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,244 @@
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CRC_HAL_API_H
+#define MBED_CRC_HAL_API_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+/** CRC Polynomial value
+ *
+ * Different polynomial values supported
+ */
+typedef enum crc_polynomial {
+ POLY_OTHER = 0,
+ POLY_8BIT_CCITT = 0x07, // x8+x2+x+1
+ POLY_7BIT_SD = 0x9, // x7+x3+1;
+ POLY_16BIT_CCITT = 0x1021, // x16+x12+x5+1
+ POLY_16BIT_IBM = 0x8005, // x16+x15+x2+1
+ POLY_32BIT_ANSI = 0x04C11DB7, // x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
+} crc_polynomial_t;
+
+typedef struct crc_mbed_config {
+ /** CRC Polynomial. Example polynomial: 0x21 = 0010_0011 = x^5+x+1 */
+ uint32_t polynomial;
+ /** CRC Bit Width */
+ uint32_t width;
+ /** Initial seed value for the computation. */
+ uint32_t initial_xor;
+ /** Final xor value for the computation. */
+ uint32_t final_xor;
+ /** Reflect bits on input. */
+ bool reflect_in;
+ /** Reflect bits in final result before returning. */
+ bool reflect_out;
+} crc_mbed_config_t;
+
+#ifdef DEVICE_CRC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_crc Hardware CRC
+ *
+ * The Hardware CRC HAL API provides a low-level interface to the Hardware CRC
+ * module of a target platform.
+ *
+ * # Defined behaviour
+ *
+ * * Function hal_crc_is_supported() returns true if platform supports hardware
+ * CRC for the given polynomial/width - verified by test ::crc_is_supported_test.
+ * * Function hal_crc_is_supported() returns false if platform does not support hardware
+ * CRC for the given polynomial/width - verified by test ::crc_is_supported_test.
+ * * Function hal_crc_is_supported() returns false if given pointer to configuration
+ * structure is undefined (NULL) - verified by test ::crc_is_supported_invalid_param_test.
+ * * If CRC module does not support one of the following settings: initial_xor, final_xor
+ * reflect_in, reflect_out, then these operations should be handled by the driver
+ * - Verified by test ::crc_calc_single_test.
+ * * Platform which supports hardware CRC must be able to handle at least one of the predefined
+ * polynomial/width configurations that can be constructed in the MbedCRC class: POLY_8BIT_CCITT,
+ * POLY_7BIT_SD, POLY_16BIT_CCITT, POLY_16BIT_IBM, POLY_32BIT_ANSI
+ * - verified by test ::crc_is_supported_test, ::crc_calc_single_test.
+ * * Function hal_crc_compute_partial_start() configures CRC module with the given configuration
+ * - Verified by test ::crc_calc_single_test.
+ * * Calling hal_crc_compute_partial_start() without finalising the
+ * CRC calculation overrides the current configuration - Verified by test ::crc_reconfigure_test.
+ * * Function hal_crc_compute_partial() writes data to the CRC module - verified by test ::crc_calc_single_test.
+ * * Function hal_crc_compute_partial() can be call multiple times in succession in order to
+ * provide additional data to CRC module - verified by test ::crc_calc_multi_test.
+ * * Function hal_crc_compute_partial() does nothing if pointer to buffer is undefined or
+ * data length is equal to 0 - verified by test ::crc_compute_partial_invalid_param_test.
+ * * Function hal_crc_get_result() returns the checksum result from the CRC module
+ * - verified by tests ::crc_calc_single_test, ::crc_calc_multi_test, ::crc_reconfigure_test.
+ *
+ * # Undefined behaviour
+ *
+ * * Calling hal_crc_compute_partial_start() function with invalid (unsupported) polynomial.
+ * * Calling hal_crc_compute_partial() or hal_crc_get_result() functions before hal_crc_compute_partial_start().
+ * * Calling hal_crc_get_result() function multiple times.
+ *
+ * # Non-functional requirements
+ *
+ * * CRC configuration provides the following settings:
+ * * polynomial - CRC Polynomial,
+ * * width - CRC bit width,
+ * * initial_xor - seed value for the computation,
+ * * final_xor - final xor value for the computation,
+ * * reflect_in - reflect bits on input,
+ * * reflect_out - reflect bits in final result before returning.
+ *
+ * # Potential bugs
+ *
+ * @{
+ */
+
+/**
+ * \defgroup hal_crc_tests crc hal tests
+ * The crc HAL tests ensure driver conformance to defined behaviour.
+ *
+ * To run the crc hal tests use the command:
+ *
+ * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-crc*
+ *
+ */
+
+/** Determine if the current platform supports hardware CRC for given polynomial
+ *
+ * The purpose of this function is to inform the CRC Platform API whether the
+ * current platform has a hardware CRC module and that it can support the
+ * requested polynomial.
+ *
+ * Supported polynomials are restricted to the named polynomials that can be
+ * constructed in the MbedCRC class, POLY_8BIT_CCITT, POLY_7BIT_SD,
+ * POLY_16BIT_CCITT, POLY_16BIT_IBM and POLY_32BIT_ANSI.
+ *
+ * The current platform must support the given polynomials default parameters
+ * in order to return a true response. These include: reflect in, reflect out,
+ * initial xor and final xor. For example, POLY_32BIT_ANSI requires an initial
+ * and final xor of 0xFFFFFFFF, and reflection of both input and output. If any
+ * of these settings cannot be configured, the polynomial is not supported.
+ *
+ * This function is thread safe; it safe to call from multiple contexts if
+ * required.
+ *
+ * \param config Contains CRC configuration parameters for initializing the
+ * hardware CRC module. For example, polynomial and initial seed
+ * values.
+ *
+ * \return True if running if the polynomial is supported, false if not.
+ */
+bool hal_crc_is_supported(const crc_mbed_config_t *config);
+
+/** Initialize the hardware CRC module with the given polynomial
+ *
+ * After calling this function, the CRC HAL module is ready to receive data
+ * using the hal_crc_compute_partial() function. The CRC module on the board
+ * is configured internally with the specified configuration and is ready
+ * to receive data.
+ *
+ * The platform configures itself based on the default configuration
+ * parameters of the input polynomial.
+ *
+ * This function must be called before calling hal_crc_compute_partial().
+ *
+ * This function must be called with a valid polynomial supported by the
+ * platform. The polynomial must be checked for support using the
+ * hal_crc_is_supported() function.
+ *
+ * Calling hal_crc_compute_partial_start() multiple times without finalizing the
+ * CRC calculation with hal_crc_get_result() overrides the current
+ * configuration and state, and the intermediate result of the computation is
+ * lost.
+ *
+ * This function is not thread safe. A CRC calculation must not be started from
+ * two different threads or contexts at the same time; calling this function
+ * from two different contexts may lead to configurations being overwritten and
+ * results being lost.
+ *
+ * \param config Contains CRC configuration parameters for initializing the
+ * hardware CRC module. For example, polynomial and initial seed
+ * values.
+ */
+void hal_crc_compute_partial_start(const crc_mbed_config_t *config);
+
+/** Writes data to the current CRC module.
+ *
+ * Writes input data buffer bytes to the CRC data register. The CRC module
+ * must interpret the data as an array of bytes.
+ *
+ * The final transformations are not applied to the data; the CRC module must
+ * retain the intermediate result so that additional calls to this function
+ * can be made, appending the additional data to the calculation.
+ *
+ * To obtain the final result of the CRC calculation, hal_crc_get_result() is
+ * called to apply the final transformations to the data.
+ *
+ * If the function is passed an undefined pointer, or the size of the buffer is
+ * specified to be 0, this function does nothing and returns.
+ *
+ * This function can be called multiple times in succession. This can be used
+ * to calculate the CRC result of streamed data.
+ *
+ * This function is not thread safe. There is only one instance of the CRC
+ * module active at a time. Calling this function from multiple contexts
+ * appends different data to the same, single instance of the module, which causes an
+ * erroneous value to be calculated.
+ *
+ * \param data Input data stream to be written into the CRC calculation
+ * \param size Size of the data stream in bytes
+ */
+void hal_crc_compute_partial(const uint8_t *data, const size_t size);
+
+/* Reads the checksum result from the CRC module.
+ *
+ * Reads the final checksum result for the final checksum value. The returned
+ * value is cast as an unsigned 32-bit integer. The actual size of the returned
+ * result depends on the polynomial used to configure the CRC module.
+ *
+ * Additional transformations that are used in the default configuration of the
+ * input polynomial are applied to the result before it is returned from this
+ * function. These transformations include: the final xor being appended to the
+ * calculation, and the result being reflected if required.
+ *
+ * Calling this function multiple times is undefined. The first call to this
+ * function returns the final result of the CRC calculation. The return
+ * value on successive calls is undefined because the contents of the register after
+ * accessing them is platform-specific.
+ *
+ * This function is not thread safe. There is only one instance of the CRC
+ * module active at a time. Calling this function from multiple contexts may
+ * return incorrect data or affect the current state of the module.
+ *
+ * \return The final CRC checksum after the reflections and final calculations
+ * have been applied.
+ */
+uint32_t hal_crc_get_result(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif // DEVICE_CRC
+#endif // MBED_CRC_HAL_API_H
+
+/**@}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/critical_section_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/critical_section_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,107 @@
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CRITICAL_SECTION_API_H
+#define MBED_CRITICAL_SECTION_API_H
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_critical Critical Section HAL functions
+ * @{
+ */
+
+/**
+ * Mark the start of a critical section
+ *
+ * This function will be called by core_util_critical_section_enter() each time
+ * the application requests to enter a critical section. The purpose of the
+ * critical section is to ensure mutual-exclusion synchronisation of the
+ * processor by preventing any change in processor control, the default
+ * behaviour requires storing the state of interrupts in the system before
+ * disabling them.
+ *
+ * The critical section code supports nesting. When a thread has entered a
+ * critical section it can make additional calls to
+ * core_util_critical_section_enter() without deadlocking itself. The critical
+ * section driver API tracks the number of nested calls to the critical section.
+ * The critical section will only be exited when
+ * core_util_critical_section_exit() has been called once for each time it
+ * entered the critical section.
+ *
+ * On the first call to enter a critical section this function MUST store the
+ * state of any interrupts or other application settings it will modify to
+ * facilitate the critical section.
+ *
+ * Each successive call to enter the critical section MUST ignore storing or
+ * modifying any application state.
+ *
+ * The default implementation of this function which will save the current state
+ * of interrupts before disabling them. This implementation can be found in
+ * mbed_critical_section_api.c. This behaviour is can be overridden on a per
+ * platform basis by providing a different implementation within the correct
+ * targets directory.
+ */
+void hal_critical_section_enter(void);
+
+
+/** Mark the end of a critical section.
+ *
+ * The purpose of this function is to restore any state that was modified upon
+ * entering the critical section, allowing other threads or interrupts to change
+ * the processor control.
+ *
+ * This function will be called once by core_util_critical_section_exit() per
+ * critical section on last call to exit. When called, the application MUST
+ * restore the saved interrupt/application state that was saved when entering
+ * the critical section.
+ *
+ * There is a default implementation of this function, it will restore the state
+ * of interrupts that were previously saved when hal_critical_section_enter was
+ * first called, this implementation can be found in
+ * mbed_critical_section_api.c. This behaviour is overridable by providing a
+ * different function implementation within the correct targets directory.
+ */
+void hal_critical_section_exit(void);
+
+
+/** Determine if the application is currently running in a critical section
+ *
+ * The purpose of this function is to inform the caller whether or not the
+ * application is running in a critical section. This is done by checking if
+ * the current interrupt state has been saved in the underlying implementation,
+ * this could also be done by checking the state of the interrupts at the time
+ * of calling.
+ *
+ * @return True if running in a critical section, false if not.
+ */
+bool hal_in_critical_section(void);
+
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MBED_CRITICAL_SECTION_API_H
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/dma_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/dma_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,50 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DMA_API_H
+#define MBED_DMA_API_H
+
+#include <stdint.h>
+
+#define DMA_ERROR_OUT_OF_CHANNELS (-1)
+
+typedef enum {
+ DMA_USAGE_NEVER,
+ DMA_USAGE_OPPORTUNISTIC,
+ DMA_USAGE_ALWAYS,
+ DMA_USAGE_TEMPORARY_ALLOCATED,
+ DMA_USAGE_ALLOCATED
+} DMAUsage;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void dma_init(void);
+
+int dma_channel_allocate(uint32_t capabilities);
+
+int dma_channel_free(int channelid);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/ethernet_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/ethernet_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,68 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_API_H
+#define MBED_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+int ethernet_init(void);
+void ethernet_free(void);
+
+// write size bytes from data to ethernet buffer
+// return num bytes written
+// or -1 if size is too big
+int ethernet_write(const char *data, int size);
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_send(void);
+
+// receive from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_receive(void);
+
+// read size bytes in to data, return actual num bytes read (0..size)
+// if data == NULL, throw the bytes away
+int ethernet_read(char *data, int size);
+
+// get the ethernet address
+void ethernet_address(char *mac);
+
+// see if the link is up
+int ethernet_link(void);
+
+// force link settings
+void ethernet_set_link(int speed, int duplex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/flash_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/flash_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,130 @@
+/** \addtogroup hal */
+/** @{*/
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FLASH_API_H
+#define MBED_FLASH_API_H
+
+#include "device.h"
+#include <stdint.h>
+
+#if DEVICE_FLASH
+
+#define MBED_FLASH_INVALID_SIZE 0xFFFFFFFF
+
+typedef struct flash_s flash_t;
+
+#if TARGET_FLASH_CMSIS_ALGO
+#include "flash_data.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup flash_hal Flash HAL API
+ * @{
+ */
+
+/** Initialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_init(flash_t *obj);
+
+/** Uninitialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_free(flash_t *obj);
+
+/** Erase one sector starting at defined address
+ *
+ * The address should be at sector boundary. This function does not do any check for address alignments
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_erase_sector(flash_t *obj, uint32_t address);
+
+/** Read data starting at defined address
+ *
+ * This function has a WEAK implementation using memcpy for backwards compatibility.
+ * @param obj The flash object
+ * @param address Address to begin reading from
+ * @param data The buffer to read data into
+ * @param size The number of bytes to read
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size);
+
+/** Program pages starting at defined address
+ *
+ * The pages should not cross multiple sectors.
+ * This function does not do any check for address alignments or if size is aligned to a page size.
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @param data The data buffer to be programmed
+ * @param size The number of bytes to program
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size);
+
+/** Get sector size
+ *
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return The size of a sector
+ */
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address);
+
+/** Get page size
+ *
+ * The page size defines the writable page size
+ * @param obj The flash object
+ * @return The size of a page
+ */
+uint32_t flash_get_page_size(const flash_t *obj);
+
+/** Get start address for the flash region
+ *
+ * @param obj The flash object
+ * @return The start address for the flash region
+ */
+uint32_t flash_get_start_address(const flash_t *obj);
+
+/** Get the flash region size
+ *
+ * @param obj The flash object
+ * @return The flash region size
+ */
+uint32_t flash_get_size(const flash_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/gpio_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/gpio_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,133 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include <stdint.h>
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_gpio GPIO HAL functions
+ * @{
+ */
+
+/** Set the given pin as GPIO
+ *
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+/* Checks if gpio object is connected (pin was not initialized with NC)
+ * @param pin The pin to be set as GPIO
+ * @return 0 if port is initialized with NC
+ **/
+int gpio_is_connected(const gpio_t *obj);
+
+/** Initialize the GPIO pin
+ *
+ * @param obj The GPIO object to initialize
+ * @param pin The GPIO pin to initialize
+ */
+void gpio_init(gpio_t *obj, PinName pin);
+
+/** Set the input pin mode
+ *
+ * @param obj The GPIO object
+ * @param mode The pin mode to be set
+ */
+void gpio_mode(gpio_t *obj, PinMode mode);
+
+/** Set the pin direction
+ *
+ * @param obj The GPIO object
+ * @param direction The pin direction to be set
+ */
+void gpio_dir(gpio_t *obj, PinDirection direction);
+
+/** Set the output value
+ *
+ * @param obj The GPIO object
+ * @param value The value to be set
+ */
+void gpio_write(gpio_t *obj, int value);
+
+/** Read the input value
+ *
+ * @param obj The GPIO object
+ * @return An integer value 1 or 0
+ */
+int gpio_read(gpio_t *obj);
+
+// the following functions are generic and implemented in the common gpio.c file
+// TODO: fix, will be moved to the common gpio header file
+
+/** Init the input pin and set mode to PullDefault
+ *
+ * @param gpio The GPIO object
+ * @param pin The pin name
+ */
+void gpio_init_in(gpio_t *gpio, PinName pin);
+
+/** Init the input pin and set the mode
+ *
+ * @param gpio The GPIO object
+ * @param pin The pin name
+ * @param mode The pin mode to be set
+ */
+void gpio_init_in_ex(gpio_t *gpio, PinName pin, PinMode mode);
+
+/** Init the output pin as an output, with predefined output value 0
+ *
+ * @param gpio The GPIO object
+ * @param pin The pin name
+ * @return An integer value 1 or 0
+ */
+void gpio_init_out(gpio_t *gpio, PinName pin);
+
+/** Init the pin as an output and set the output value
+ *
+ * @param gpio The GPIO object
+ * @param pin The pin name
+ * @param value The value to be set
+ */
+void gpio_init_out_ex(gpio_t *gpio, PinName pin, int value);
+
+/** Init the pin to be in/out
+ *
+ * @param gpio The GPIO object
+ * @param pin The pin name
+ * @param direction The pin direction to be set
+ * @param mode The pin mode to be set
+ * @param value The value to be set for an output pin
+ */
+void gpio_init_inout(gpio_t *gpio, PinName pin, PinDirection direction, PinMode mode, int value);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/gpio_irq_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/gpio_irq_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,97 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_IRQ_API_H
+#define MBED_GPIO_IRQ_API_H
+
+#include "device.h"
+
+#if DEVICE_INTERRUPTIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO IRQ events
+ */
+typedef enum {
+ IRQ_NONE,
+ IRQ_RISE,
+ IRQ_FALL
+} gpio_irq_event;
+
+/** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL
+ */
+typedef struct gpio_irq_s gpio_irq_t;
+
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
+
+/**
+ * \defgroup hal_gpioirq GPIO IRQ HAL functions
+ * @{
+ */
+
+/** Initialize the GPIO IRQ pin
+ *
+ * @param obj The GPIO object to initialize
+ * @param pin The GPIO pin name
+ * @param handler The handler to be attached to GPIO IRQ
+ * @param id The object ID (id != 0, 0 is reserved)
+ * @return -1 if pin is NC, 0 otherwise
+ */
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
+
+/** Release the GPIO IRQ PIN
+ *
+ * @param obj The gpio object
+ */
+void gpio_irq_free(gpio_irq_t *obj);
+
+/** Enable/disable pin IRQ event
+ *
+ * @param obj The GPIO object
+ * @param event The GPIO IRQ event
+ * @param enable The enable flag
+ */
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
+
+/** Enable GPIO IRQ
+ *
+ * This is target dependent, as it might enable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_enable(gpio_irq_t *obj);
+
+/** Disable GPIO IRQ
+ *
+ * This is target dependent, as it might disable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_disable(gpio_irq_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/i2c_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/i2c_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,254 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+#include "hal/buffer.h"
+
+#if DEVICE_I2C_ASYNCH
+#include "hal/dma_api.h"
+#endif
+
+#if DEVICE_I2C
+
+/**
+ * @defgroup hal_I2CEvents I2C Events Macros
+ *
+ * @{
+ */
+#define I2C_EVENT_ERROR (1 << 1)
+#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2)
+#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3)
+#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
+#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+/** Asynch I2C HAL structure
+ */
+typedef struct {
+ struct i2c_s i2c; /**< Target specific I2C structure */
+ struct buffer_s tx_buff; /**< Tx buffer */
+ struct buffer_s rx_buff; /**< Rx buffer */
+} i2c_t;
+
+#else
+/** Non-asynch I2C HAL structure
+ */
+typedef struct i2c_s i2c_t;
+
+#endif
+
+enum {
+ I2C_ERROR_NO_SLAVE = -1,
+ I2C_ERROR_BUS_BUSY = -2
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralI2C I2C Configuration Functions
+ * @{
+ */
+
+/** Initialize the I2C peripheral. It sets the default parameters for I2C
+ * peripheral, and configures its specifieds pins.
+ *
+ * @param obj The I2C object
+ * @param sda The sda pin
+ * @param scl The scl pin
+ */
+void i2c_init(i2c_t *obj, PinName sda, PinName scl);
+
+/** Configure the I2C frequency
+ *
+ * @param obj The I2C object
+ * @param hz Frequency in Hz
+ */
+void i2c_frequency(i2c_t *obj, int hz);
+
+/** Send START command
+ *
+ * @param obj The I2C object
+ */
+int i2c_start(i2c_t *obj);
+
+/** Send STOP command
+ *
+ * @param obj The I2C object
+ */
+int i2c_stop(i2c_t *obj);
+
+/** Blocking reading data
+ *
+ * @param obj The I2C object
+ * @param address 7-bit address (last bit is 1)
+ * @param data The buffer for receiving
+ * @param length Number of bytes to read
+ * @param stop Stop to be generated after the transfer is done
+ * @return Number of read bytes
+ */
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
+
+/** Blocking sending data
+ *
+ * @param obj The I2C object
+ * @param address 7-bit address (last bit is 0)
+ * @param data The buffer for sending
+ * @param length Number of bytes to write
+ * @param stop Stop to be generated after the transfer is done
+ * @return
+ * zero or non-zero - Number of written bytes
+ * negative - I2C_ERROR_XXX status
+ */
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
+
+/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop()
+ *
+ * @param obj The I2C object
+ */
+void i2c_reset(i2c_t *obj);
+
+/** Read one byte
+ *
+ * @param obj The I2C object
+ * @param last Acknoledge
+ * @return The read byte
+ */
+int i2c_byte_read(i2c_t *obj, int last);
+
+/** Write one byte
+ *
+ * @param obj The I2C object
+ * @param data Byte to be written
+ * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout.
+ */
+int i2c_byte_write(i2c_t *obj, int data);
+
+/**@}*/
+
+#if DEVICE_I2CSLAVE
+
+/**
+ * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
+ * @{
+ */
+
+/** Configure I2C as slave or master.
+ * @param obj The I2C object
+ * @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive
+ * @return non-zero if a value is available
+ */
+void i2c_slave_mode(i2c_t *obj, int enable_slave);
+
+/** Check to see if the I2C slave has been addressed.
+ * @param obj The I2C object
+ * @return The status - 1 - read addresses, 2 - write to all slaves,
+ * 3 write addressed, 0 - the slave has not been addressed
+ */
+int i2c_slave_receive(i2c_t *obj);
+
+/** Configure I2C as slave or master.
+ * @param obj The I2C object
+ * @param data The buffer for receiving
+ * @param length Number of bytes to read
+ * @return non-zero if a value is available
+ */
+int i2c_slave_read(i2c_t *obj, char *data, int length);
+
+/** Configure I2C as slave or master.
+ * @param obj The I2C object
+ * @param data The buffer for sending
+ * @param length Number of bytes to write
+ * @return non-zero if a value is available
+ */
+int i2c_slave_write(i2c_t *obj, const char *data, int length);
+
+/** Configure I2C address.
+ * @param obj The I2C object
+ * @param idx Currently not used
+ * @param address The address to be set
+ * @param mask Currently not used
+ */
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+
+#endif
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+
+/**
+ * \defgroup hal_AsynchI2C Asynchronous I2C Hardware Abstraction Layer
+ * @{
+ */
+
+/** Start I2C asynchronous transfer
+ *
+ * @param obj The I2C object
+ * @param tx The transmit buffer
+ * @param tx_length The number of bytes to transmit
+ * @param rx The receive buffer
+ * @param rx_length The number of bytes to receive
+ * @param address The address to be set - 7bit or 9bit
+ * @param stop If true, stop will be generated after the transfer is done
+ * @param handler The I2C IRQ handler to be set
+ * @param event Event mask for the transfer. See \ref hal_I2CEvents
+ * @param hint DMA hint usage
+ */
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *
+ * @param obj The I2C object which holds the transfer information
+ * @return Event flags if a transfer termination condition was met, otherwise return 0.
+ */
+uint32_t i2c_irq_handler_asynch(i2c_t *obj);
+
+/** Attempts to determine if the I2C peripheral is already in use
+ *
+ * @param obj The I2C object
+ * @return Non-zero if the I2C module is active or zero if it is not
+ */
+uint8_t i2c_active(i2c_t *obj);
+
+/** Abort asynchronous transfer
+ *
+ * This function does not perform any check - that should happen in upper layers.
+ * @param obj The I2C object
+ */
+void i2c_abort_asynch(i2c_t *obj);
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/itm_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/itm_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,102 @@
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_ITM_API_H
+#define MBED_ITM_API_H
+
+#if defined(DEVICE_ITM)
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup itm_hal Instrumented Trace Macrocell HAL API
+ * @{
+ */
+
+enum {
+ ITM_PORT_SWO = 0
+};
+
+/**
+ * @brief Target specific initialization function.
+ * This function is responsible for initializing and configuring
+ * the debug clock for the ITM and setting up the SWO pin for
+ * debug output.
+ *
+ * The only Cortex-M register that should be modified is the clock
+ * prescaler in TPI->ACPR.
+ *
+ * The generic mbed_itm_init initialization function will setup:
+ *
+ * ITM->LAR
+ * ITM->TPR
+ * ITM->TCR
+ * ITM->TER
+ * TPI->SPPR
+ * TPI->FFCR
+ * DWT->CTRL
+ *
+ * for SWO output on stimulus port 0.
+ */
+void itm_init(void);
+
+/**
+ * @brief Initialization function for both generic registers and target specific clock and pin.
+ */
+void mbed_itm_init(void);
+
+/**
+ * @brief Send data over ITM stimulus port.
+ *
+ * @param[in] port The stimulus port to send data over.
+ * @param[in] data The 32-bit data to send.
+ *
+ * The data is written as a single 32-bit write to the port.
+ *
+ * @return value of data sent.
+ */
+uint32_t mbed_itm_send(uint32_t port, uint32_t data);
+
+/**
+ * @brief Send a block of data over ITM stimulus port.
+ *
+ * @param[in] port The stimulus port to send data over.
+ * @param[in] data The block of data to send.
+ * @param[in] len The number of bytes of data to send.
+ *
+ * The data is written using multiple appropriately-sized port accesses for
+ * efficient transfer.
+ */
+void mbed_itm_send_block(uint32_t port, const void *data, size_t len);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif /* MBED_ITM_API_H */
+
+/**@}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/lp_ticker_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/lp_ticker_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,247 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LPTICKER_API_H
+#define MBED_LPTICKER_API_H
+
+#include "device.h"
+
+#if DEVICE_LPTICKER
+
+#include "hal/ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_lp_ticker Low Power Ticker
+ * Low level interface to the low power ticker of a target
+ *
+ * # Defined behavior
+ * * Has a reported frequency between 4KHz and 64KHz - verified by ::lp_ticker_info_test
+ * * Has a counter that is at least 12 bits wide - verified by ::lp_ticker_info_test
+ * * Continues operating in deep sleep mode - verified by ::lp_ticker_deepsleep_test
+ * * All behavior defined by the @ref hal_ticker_shared "ticker specification"
+ *
+ * # Undefined behavior
+ * * See the @ref hal_ticker_shared "ticker specification"
+ * * Calling any function other than lp_ticker_init after calling lp_ticker_free
+ *
+ * # Potential bugs
+ * * Glitches due to ripple counter - Verified by ::lp_ticker_glitch_test
+ *
+ * @see hal_lp_ticker_tests
+ *
+ * @{
+ */
+
+/**
+ * \defgroup hal_lp_ticker_tests Low Power Ticker tests
+ * Tests to validate the proper implementation of the low power ticker
+ *
+ * To run the low power ticker hal tests use the command:
+ *
+ * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*,tests-mbed_hal-lp_ticker*
+ *
+ */
+
+typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
+
+/** Set low power ticker IRQ handler
+ *
+ * @param ticker_irq_handler IRQ handler to be connected
+ *
+ * @return previous ticker IRQ handler
+ *
+ * @note by default IRQ handler is set to ::ticker_irq_handler
+ * @note this function is primarily for testing purposes and it's not required part of HAL implementation
+ *
+ */
+ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler);
+
+/** Get low power ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t *get_lp_ticker_data(void);
+
+/** The wrapper for ticker_irq_handler, to pass lp ticker's data
+ *
+ */
+void lp_ticker_irq_handler(void);
+
+/* HAL lp ticker */
+
+/** Initialize the low power ticker
+ *
+ * Initialize or re-initialize the ticker. This resets all the
+ * clocking and prescaler registers, along with disabling
+ * the compare interrupt.
+ *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_init()
+ * {
+ * // Enable clock gate so processor can read LPTMR registers
+ * POWER_CTRL |= POWER_CTRL_LPTMR_Msk;
+ *
+ * // Disable the timer and ensure it is powered down
+ * LPTMR_CTRL &= ~(LPTMR_CTRL_ENABLE_Msk | LPTMR_CTRL_COMPARE_ENABLE_Msk);
+ *
+ * // Configure divisors - no division necessary
+ * LPTMR_PRESCALE = 0;
+ * LPTMR_CTRL |= LPTMR_CTRL_ENABLE_Msk;
+ *
+ * // Install the interrupt handler
+ * NVIC_SetVector(LPTMR_IRQn, (uint32_t)lp_ticker_irq_handler);
+ * NVIC_EnableIRQ(LPTMR_IRQn);
+ * }
+ * @endcode
+ */
+void lp_ticker_init(void);
+
+/** Deinitialize the lower power ticker
+ *
+ * Powerdown the lp ticker in preparation for sleep, powerdown, or reset.
+ *
+ * After calling this function no other ticker functions should be called except
+ * lp_ticker_init(). Calling any function other than init after freeing is
+ * undefined.
+ *
+ * @note This function stops the ticker from counting.
+ */
+void lp_ticker_free(void);
+
+/** Read the current tick
+ *
+ * If no rollover has occurred, the seconds passed since lp_ticker_init()
+ * was called can be found by dividing the ticks returned by this function
+ * by the frequency returned by ::lp_ticker_get_info.
+ *
+ * @return The current timer's counter value in ticks
+ *
+ * Pseudo Code:
+ * @code
+ * uint32_t lp_ticker_read()
+ * {
+ * uint16_t count;
+ * uint16_t last_count;
+ *
+ * // Loop until the same tick is read twice since this
+ * // is ripple counter on a different clock domain.
+ * count = LPTMR_COUNT;
+ * do {
+ * last_count = count;
+ * count = LPTMR_COUNT;
+ * } while (last_count != count);
+ *
+ * return count;
+ * }
+ * @endcode
+ */
+uint32_t lp_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in ticks to be set
+ *
+ * @note no special handling needs to be done for times in the past
+ * as the common timer code will detect this and call
+ * lp_ticker_fire_interrupt() if this is the case
+ *
+ * @note calling this function with timestamp of more than the supported
+ * number of bits returned by ::lp_ticker_get_info results in undefined
+ * behavior.
+ *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_set_interrupt(timestamp_t timestamp)
+ * {
+ * LPTMR_COMPARE = timestamp;
+ * LPTMR_CTRL |= LPTMR_CTRL_COMPARE_ENABLE_Msk;
+ * }
+ * @endcode
+ */
+void lp_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable low power ticker interrupt
+ *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_disable_interrupt(void)
+ * {
+ * // Disable the compare interrupt
+ * LPTMR_CTRL &= ~LPTMR_CTRL_COMPARE_ENABLE_Msk;
+ * }
+ * @endcode
+ */
+void lp_ticker_disable_interrupt(void);
+
+/** Clear the low power ticker interrupt
+ *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_clear_interrupt(void)
+ * {
+ * // Write to the ICR (interrupt clear register) of the LPTMR
+ * LPTMR_ICR = LPTMR_ICR_COMPARE_Msk;
+ * }
+ * @endcode
+ */
+void lp_ticker_clear_interrupt(void);
+
+/** Set pending interrupt that should be fired right away.
+ *
+ * Pseudo Code:
+ * @code
+ * void lp_ticker_fire_interrupt(void)
+ * {
+ * NVIC_SetPendingIRQ(LPTMR_IRQn);
+ * }
+ * @endcode
+ */
+void lp_ticker_fire_interrupt(void);
+
+/** Get frequency and counter bits of this ticker.
+ *
+ * Pseudo Code:
+ * @code
+ * const ticker_info_t* lp_ticker_get_info()
+ * {
+ * static const ticker_info_t info = {
+ * 32768, // 32KHz
+ * 16 // 16 bit counter
+ * };
+ * return &info;
+ * }
+ * @endcode
+ */
+const ticker_info_t *lp_ticker_get_info(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_critical_section_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_critical_section_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "hal/critical_section_api.h"
+#include "platform/mbed_assert.h"
+#include "platform/mbed_toolchain.h"
+
+#include <stdbool.h>
+
+static volatile bool critical_interrupts_enabled = false;
+static volatile bool state_saved = false;
+
+static bool are_interrupts_enabled(void)
+{
+#if defined(__CORTEX_A9)
+ return ((__get_CPSR() & 0x80) == 0);
+#else
+ return ((__get_PRIMASK() & 0x1) == 0);
+#endif
+}
+
+
+MBED_WEAK void hal_critical_section_enter(void)
+{
+ const bool interrupt_state = are_interrupts_enabled();
+
+ __disable_irq();
+
+ if (state_saved == true) {
+ return;
+ }
+
+ critical_interrupts_enabled = interrupt_state;
+ state_saved = true;
+}
+
+MBED_WEAK void hal_critical_section_exit(void)
+{
+#ifndef FEATURE_UVISOR
+ // Interrupts must be disabled on invoking an exit from a critical section
+ MBED_ASSERT(!are_interrupts_enabled());
+#endif
+ state_saved = false;
+
+ // Restore the IRQs to their state prior to entering the critical section
+ if (critical_interrupts_enabled == true) {
+ __enable_irq();
+ }
+}
+
+MBED_WEAK bool hal_in_critical_section(void)
+{
+ return (state_saved == true);
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_flash_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_flash_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "hal/flash_api.h"
+
+#if DEVICE_FLASH
+
+#include "platform/mbed_toolchain.h"
+#include <string.h>
+
+MBED_WEAK int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size)
+{
+ memcpy(data, (const void *)address, size);
+ return 0;
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_gpio.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/gpio_api.h"
+
+static inline void _gpio_init_in(gpio_t *gpio, PinName pin, PinMode mode)
+{
+ gpio_init(gpio, pin);
+ if (pin != NC) {
+ gpio_dir(gpio, PIN_INPUT);
+ gpio_mode(gpio, mode);
+ }
+}
+
+static inline void _gpio_init_out(gpio_t *gpio, PinName pin, PinMode mode, int value)
+{
+ gpio_init(gpio, pin);
+ if (pin != NC) {
+ gpio_write(gpio, value);
+ gpio_dir(gpio, PIN_OUTPUT);
+ gpio_mode(gpio, mode);
+ }
+}
+
+void gpio_init_in(gpio_t *gpio, PinName pin)
+{
+ gpio_init_in_ex(gpio, pin, PullDefault);
+}
+
+void gpio_init_in_ex(gpio_t *gpio, PinName pin, PinMode mode)
+{
+ _gpio_init_in(gpio, pin, mode);
+}
+
+void gpio_init_out(gpio_t *gpio, PinName pin)
+{
+ gpio_init_out_ex(gpio, pin, 0);
+}
+
+void gpio_init_out_ex(gpio_t *gpio, PinName pin, int value)
+{
+ _gpio_init_out(gpio, pin, PullNone, value);
+}
+
+void gpio_init_inout(gpio_t *gpio, PinName pin, PinDirection direction, PinMode mode, int value)
+{
+ if (direction == PIN_INPUT) {
+ _gpio_init_in(gpio, pin, mode);
+ if (pin != NC) {
+ gpio_write(gpio, value); // we prepare the value in case it is switched later
+ }
+ } else {
+ _gpio_init_out(gpio, pin, mode, value);
+ }
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_itm_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_itm_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,133 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(DEVICE_ITM)
+
+#include "hal/itm_api.h"
+#include "cmsis.h"
+
+#include <stdbool.h>
+
+#ifndef ITM_STIM_FIFOREADY_Msk
+#define ITM_STIM_FIFOREADY_Msk 1
+#endif
+
+#define ITM_ENABLE_WRITE 0xC5ACCE55
+
+#define SWO_NRZ 0x02
+#define SWO_STIMULUS_PORT 0x01
+
+void mbed_itm_init(void)
+{
+ static bool do_init = true;
+
+ if (do_init) {
+ do_init = false;
+
+ itm_init();
+
+ /* Enable write access to ITM registers. */
+ ITM->LAR = ITM_ENABLE_WRITE;
+
+ /* Trace Port Interface Selected Pin Protocol Register. */
+ TPI->SPPR = (SWO_NRZ << TPI_SPPR_TXMODE_Pos);
+
+ /* Trace Port Interface Formatter and Flush Control Register */
+ TPI->FFCR = (1 << TPI_FFCR_TrigIn_Pos);
+
+ /* Data Watchpoint and Trace Control Register */
+ DWT->CTRL = (1 << DWT_CTRL_CYCTAP_Pos) |
+ (0xF << DWT_CTRL_POSTINIT_Pos) |
+ (0xF << DWT_CTRL_POSTPRESET_Pos) |
+ (1 << DWT_CTRL_CYCCNTENA_Pos);
+
+ /* Trace Privilege Register.
+ * Disable access to trace channel configuration from non-privileged mode.
+ */
+ ITM->TPR = 0x0;
+
+ /* Trace Control Register */
+ ITM->TCR = (1 << ITM_TCR_TraceBusID_Pos) |
+ (1 << ITM_TCR_DWTENA_Pos) |
+ (1 << ITM_TCR_SYNCENA_Pos) |
+ (1 << ITM_TCR_ITMENA_Pos);
+
+ /* Trace Enable Register */
+ ITM->TER = SWO_STIMULUS_PORT;
+ }
+}
+
+static void itm_out8(uint32_t port, uint8_t data)
+{
+ /* Wait until port is available */
+ while ((ITM->PORT[port].u32 & ITM_STIM_FIFOREADY_Msk) == 0) {
+ __NOP();
+ }
+
+ /* write data to port */
+ ITM->PORT[port].u8 = data;
+}
+
+static void itm_out32(uint32_t port, uint32_t data)
+{
+ /* Wait until port is available */
+ while ((ITM->PORT[port].u32 & ITM_STIM_FIFOREADY_Msk) == 0) {
+ __NOP();
+ }
+
+ /* write data to port */
+ ITM->PORT[port].u32 = data;
+}
+
+uint32_t mbed_itm_send(uint32_t port, uint32_t data)
+{
+ /* Check if ITM and port is enabled */
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & (1UL << port)) != 0UL)) { /* ITM Port enabled */
+ itm_out32(port, data);
+ }
+
+ return data;
+}
+
+void mbed_itm_send_block(uint32_t port, const void *data, size_t len)
+{
+ const char *ptr = data;
+
+ /* Check if ITM and port is enabled */
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & (1UL << port)) != 0UL)) { /* ITM Port enabled */
+ /* Output single byte at a time until data is aligned */
+ while ((((uintptr_t) ptr) & 3) && len != 0) {
+ itm_out8(port, *ptr++);
+ len--;
+ }
+
+ /* Output bulk of data one word at a time */
+ while (len >= 4) {
+ itm_out32(port, *(const uint32_t *) ptr);
+ ptr += 4;
+ len -= 4;
+ }
+
+ /* Output any trailing bytes */
+ while (len != 0) {
+ itm_out8(port, *ptr++);
+ len--;
+ }
+ }
+}
+#endif // defined(DEVICE_ITM)
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_lp_ticker_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_lp_ticker_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/lp_ticker_api.h"
+
+#if DEVICE_LPTICKER
+
+void lp_ticker_set_interrupt_wrapper(timestamp_t timestamp);
+
+static ticker_event_queue_t events = { 0 };
+
+static ticker_irq_handler_type irq_handler = ticker_irq_handler;
+
+static const ticker_interface_t lp_interface = {
+ .init = lp_ticker_init,
+ .read = lp_ticker_read,
+ .disable_interrupt = lp_ticker_disable_interrupt,
+ .clear_interrupt = lp_ticker_clear_interrupt,
+#if LPTICKER_DELAY_TICKS > 0
+ .set_interrupt = lp_ticker_set_interrupt_wrapper,
+#else
+ .set_interrupt = lp_ticker_set_interrupt,
+#endif
+ .fire_interrupt = lp_ticker_fire_interrupt,
+ .get_info = lp_ticker_get_info,
+};
+
+static const ticker_data_t lp_data = {
+ .interface = &lp_interface,
+ .queue = &events,
+};
+
+const ticker_data_t *get_lp_ticker_data(void)
+{
+ return &lp_data;
+}
+
+ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler)
+{
+ ticker_irq_handler_type prev_irq_handler = irq_handler;
+
+ irq_handler = ticker_irq_handler;
+
+ return prev_irq_handler;
+}
+
+void lp_ticker_irq_handler(void)
+{
+ if (irq_handler) {
+ irq_handler(&lp_data);
+ }
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_lp_ticker_wrapper.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_lp_ticker_wrapper.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,156 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/lp_ticker_api.h"
+
+#if DEVICE_LPTICKER && (LPTICKER_DELAY_TICKS > 0)
+
+#include "Timeout.h"
+#include "mbed_critical.h"
+
+static const timestamp_t min_delta = LPTICKER_DELAY_TICKS;
+
+static bool init = false;
+static bool pending = false;
+static bool timeout_pending = false;
+static timestamp_t last_set_interrupt = 0;
+static timestamp_t last_request = 0;
+static timestamp_t next = 0;
+
+static timestamp_t mask;
+static timestamp_t reschedule_us;
+
+// Do not use SingletonPtr since this must be initialized in a critical section
+static mbed::Timeout *timeout;
+static uint64_t timeout_data[sizeof(mbed::Timeout) / 8];
+
+/**
+ * Initialize variables
+ */
+static void init_local()
+{
+ MBED_ASSERT(core_util_in_critical_section());
+
+ const ticker_info_t *info = lp_ticker_get_info();
+ if (info->bits >= 32) {
+ mask = 0xffffffff;
+ } else {
+ mask = ((uint64_t)1 << info->bits) - 1;
+ }
+
+ // Round us_per_tick up
+ timestamp_t us_per_tick = (1000000 + info->frequency - 1) / info->frequency;
+
+ // Add 1 tick to the min delta for the case where the clock transitions after you read it
+ // Add 4 microseconds to round up the micro second ticker time (which has a frequency of at least 250KHz - 4us period)
+ reschedule_us = (min_delta + 1) * us_per_tick + 4;
+
+ timeout = new (timeout_data) mbed::Timeout();
+}
+
+/**
+ * Call lp_ticker_set_interrupt with a value that is guaranteed to fire
+ *
+ * Assumptions
+ * -Only one low power clock tick can pass from the last read (last_read)
+ * -The closest an interrupt can fire is max_delta + 1
+ *
+ * @param last_read The last value read from lp_ticker_read
+ * @param timestamp The timestamp to trigger the interrupt at
+ */
+static void set_interrupt_safe(timestamp_t last_read, timestamp_t timestamp)
+{
+ MBED_ASSERT(core_util_in_critical_section());
+ uint32_t delta = (timestamp - last_read) & mask;
+ if (delta < min_delta + 2) {
+ timestamp = (last_read + min_delta + 2) & mask;
+ }
+ lp_ticker_set_interrupt(timestamp);
+}
+
+/**
+ * Set the low power ticker match time when hardware is ready
+ *
+ * This event is scheduled to set the lp timer after the previous write
+ * has taken effect and it is safe to write a new value without blocking.
+ * If the time has already passed then this function fires and interrupt
+ * immediately.
+ */
+static void set_interrupt_later()
+{
+ core_util_critical_section_enter();
+
+ timestamp_t current = lp_ticker_read();
+ if (_ticker_match_interval_passed(last_request, current, next)) {
+ lp_ticker_fire_interrupt();
+ } else {
+ set_interrupt_safe(current, next);
+ last_set_interrupt = lp_ticker_read();
+ }
+ timeout_pending = false;
+
+ core_util_critical_section_exit();
+}
+
+/**
+ * Wrapper around lp_ticker_set_interrupt to prevent blocking
+ *
+ * Problems this function is solving:
+ * 1. Interrupt may not fire if set earlier than LPTICKER_DELAY_TICKS low power clock cycles
+ * 2. Setting the interrupt back-to-back will block
+ *
+ * This wrapper function prevents lp_ticker_set_interrupt from being called
+ * back-to-back and blocking while the first write is in progress. This function
+ * avoids that problem by scheduling a timeout event if the lp ticker is in the
+ * middle of a write operation.
+ *
+ * @param timestamp Time to call ticker irq
+ * @note this is a utility function and it's not required part of HAL implementation
+ */
+extern "C" void lp_ticker_set_interrupt_wrapper(timestamp_t timestamp)
+{
+ core_util_critical_section_enter();
+
+ if (!init) {
+ init_local();
+ init = true;
+ }
+
+ timestamp_t current = lp_ticker_read();
+ if (pending) {
+ // Check if pending should be cleared
+ if (((current - last_set_interrupt) & mask) >= min_delta) {
+ pending = false;
+ }
+ }
+
+ if (pending || timeout_pending) {
+ next = timestamp;
+ last_request = current;
+ if (!timeout_pending) {
+ timeout->attach_us(set_interrupt_later, reschedule_us);
+ timeout_pending = true;
+ }
+ } else {
+ // Schedule immediately if nothing is pending
+ set_interrupt_safe(current, timestamp);
+ last_set_interrupt = lp_ticker_read();
+ pending = true;
+ }
+
+ core_util_critical_section_exit();
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_pinmap_common.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_pinmap_common.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/pinmap.h"
+#include "platform/mbed_error.h"
+
+void pinmap_pinout(PinName pin, const PinMap *map)
+{
+ if (pin == NC) {
+ return;
+ }
+
+ while (map->pin != NC) {
+ if (map->pin == pin) {
+ pin_function(pin, map->function);
+
+ pin_mode(pin, PullNone);
+ return;
+ }
+ map++;
+ }
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "could not pinout", pin);
+}
+
+uint32_t pinmap_merge(uint32_t a, uint32_t b)
+{
+ // both are the same (inc both NC)
+ if (a == b) {
+ return a;
+ }
+
+ // one (or both) is not connected
+ if (a == (uint32_t)NC) {
+ return b;
+ }
+ if (b == (uint32_t)NC) {
+ return a;
+ }
+
+ // mis-match error case
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap mis-match", a);
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap *map)
+{
+ while (map->pin != NC) {
+ if (map->pin == pin) {
+ return map->peripheral;
+ }
+ map++;
+ }
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap *map)
+{
+ uint32_t peripheral = (uint32_t)NC;
+
+ if (pin == (PinName)NC) {
+ return (uint32_t)NC;
+ }
+ peripheral = pinmap_find_peripheral(pin, map);
+ if ((uint32_t)NC == peripheral) { // no mapping available
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap not found for peripheral", peripheral);
+ }
+ return peripheral;
+}
+
+uint32_t pinmap_find_function(PinName pin, const PinMap *map)
+{
+ while (map->pin != NC) {
+ if (map->pin == pin) {
+ return map->function;
+ }
+ map++;
+ }
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_function(PinName pin, const PinMap *map)
+{
+ uint32_t function = (uint32_t)NC;
+
+ if (pin == (PinName)NC) {
+ return (uint32_t)NC;
+ }
+ function = pinmap_find_function(pin, map);
+ if ((uint32_t)NC == function) { // no mapping available
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap not found for function", function);
+ }
+ return function;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_sleep_manager.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_sleep_manager.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,237 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_assert.h"
+#include "mbed_power_mgmt.h"
+#include "mbed_critical.h"
+#include "sleep_api.h"
+#include "mbed_error.h"
+#include "mbed_debug.h"
+#include "mbed_stats.h"
+#include "lp_ticker_api.h"
+#include <limits.h>
+#include <stdio.h>
+#include "mbed_stats.h"
+
+
+#if DEVICE_SLEEP
+
+// deep sleep locking counter. A target is allowed to deep sleep if counter == 0
+static uint16_t deep_sleep_lock = 0U;
+static us_timestamp_t sleep_time = 0;
+static us_timestamp_t deep_sleep_time = 0;
+
+#if defined(MBED_CPU_STATS_ENABLED) && defined(DEVICE_LPTICKER)
+static ticker_data_t *sleep_ticker = NULL;
+#endif
+
+static inline us_timestamp_t read_us(void)
+{
+#if defined(MBED_CPU_STATS_ENABLED) && defined(DEVICE_LPTICKER)
+ if (NULL == sleep_ticker) {
+ sleep_ticker = (ticker_data_t *)get_lp_ticker_data();
+ }
+ return ticker_read_us(sleep_ticker);
+#else
+ return 0;
+#endif
+}
+
+us_timestamp_t mbed_time_idle(void)
+{
+ return (sleep_time + deep_sleep_time);
+}
+
+us_timestamp_t mbed_uptime(void)
+{
+ return read_us();
+}
+
+us_timestamp_t mbed_time_sleep(void)
+{
+ return sleep_time;
+}
+
+us_timestamp_t mbed_time_deepsleep(void)
+{
+ return deep_sleep_time;
+}
+
+#ifdef MBED_SLEEP_TRACING_ENABLED
+
+// Number of drivers that can be stored in the structure
+#define STATISTIC_COUNT 10
+
+typedef struct sleep_statistic {
+ const char *identifier;
+ uint8_t count;
+} sleep_statistic_t;
+
+static sleep_statistic_t sleep_stats[STATISTIC_COUNT];
+
+static sleep_statistic_t *sleep_tracker_find(const char *const filename)
+{
+ for (int i = 0; i < STATISTIC_COUNT; ++i) {
+ if (sleep_stats[i].identifier == filename) {
+ return &sleep_stats[i];
+ }
+ }
+
+ return NULL;
+}
+
+static sleep_statistic_t *sleep_tracker_add(const char *const filename)
+{
+ for (int i = 0; i < STATISTIC_COUNT; ++i) {
+ if (sleep_stats[i].identifier == NULL) {
+ sleep_stats[i].identifier = filename;
+
+ return &sleep_stats[i];
+ }
+ }
+
+ debug("No free indexes left to use in mbed sleep tracker.\r\n");
+
+ return NULL;
+}
+
+static void sleep_tracker_print_stats(void)
+{
+ debug("Sleep locks held:\r\n");
+ for (int i = 0; i < STATISTIC_COUNT; ++i) {
+ if (sleep_stats[i].count == 0) {
+ continue;
+ }
+
+ if (sleep_stats[i].identifier == NULL) {
+ return;
+ }
+
+ debug("[id: %s, count: %u]\r\n", sleep_stats[i].identifier,
+ sleep_stats[i].count);
+ }
+}
+
+void sleep_tracker_lock(const char *const filename, int line)
+{
+ sleep_statistic_t *stat = sleep_tracker_find(filename);
+
+ // Entry for this driver does not exist, create one.
+ if (stat == NULL) {
+ stat = sleep_tracker_add(filename);
+ }
+
+ core_util_atomic_incr_u8(&stat->count, 1);
+
+ debug("LOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock);
+}
+
+void sleep_tracker_unlock(const char *const filename, int line)
+{
+ sleep_statistic_t *stat = sleep_tracker_find(filename);
+
+ // Entry for this driver does not exist, something went wrong.
+ if (stat == NULL) {
+ debug("Unlocking sleep for driver that was not previously locked: %s, ln: %i\r\n", filename, line);
+ return;
+ }
+
+ core_util_atomic_decr_u8(&stat->count, 1);
+
+ debug("UNLOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock);
+}
+
+#endif // MBED_SLEEP_TRACING_ENABLED
+
+void sleep_manager_lock_deep_sleep_internal(void)
+{
+ core_util_critical_section_enter();
+ if (deep_sleep_lock == USHRT_MAX) {
+ core_util_critical_section_exit();
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_OVERFLOW), "DeepSleepLock overflow (> USHRT_MAX)", deep_sleep_lock);
+ }
+ core_util_atomic_incr_u16(&deep_sleep_lock, 1);
+ core_util_critical_section_exit();
+}
+
+void sleep_manager_unlock_deep_sleep_internal(void)
+{
+ core_util_critical_section_enter();
+ if (deep_sleep_lock == 0) {
+ core_util_critical_section_exit();
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_UNDERFLOW), "DeepSleepLock underflow (< 0)", deep_sleep_lock);
+ }
+ core_util_atomic_decr_u16(&deep_sleep_lock, 1);
+ core_util_critical_section_exit();
+}
+
+bool sleep_manager_can_deep_sleep(void)
+{
+ return deep_sleep_lock == 0 ? true : false;
+}
+
+void sleep_manager_sleep_auto(void)
+{
+#ifdef MBED_SLEEP_TRACING_ENABLED
+ sleep_tracker_print_stats();
+#endif
+ core_util_critical_section_enter();
+ us_timestamp_t start = read_us();
+ bool deep = false;
+
+// debug profile should keep debuggers attached, no deep sleep allowed
+#ifdef MBED_DEBUG
+ hal_sleep();
+#else
+ if (sleep_manager_can_deep_sleep()) {
+ deep = true;
+ hal_deepsleep();
+ } else {
+ hal_sleep();
+ }
+#endif
+
+ us_timestamp_t end = read_us();
+ if (true == deep) {
+ deep_sleep_time += end - start;
+ } else {
+ sleep_time += end - start;
+ }
+ core_util_critical_section_exit();
+}
+
+#else
+
+// locking is valid only if DEVICE_SLEEP is defined
+// we provide empty implementation
+
+void sleep_manager_lock_deep_sleep_internal(void)
+{
+
+}
+
+void sleep_manager_unlock_deep_sleep_internal(void)
+{
+
+}
+
+bool sleep_manager_can_deep_sleep(void)
+{
+ // no sleep implemented
+ return false;
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_ticker_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_ticker_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,432 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include <stddef.h>
+#include "hal/ticker_api.h"
+#include "platform/mbed_critical.h"
+#include "mbed_assert.h"
+
+static void schedule_interrupt(const ticker_data_t *const ticker);
+static void update_present_time(const ticker_data_t *const ticker);
+
+/*
+ * Initialize a ticker instance.
+ */
+static void initialize(const ticker_data_t *ticker)
+{
+ // return if the queue has already been initialized, in that case the
+ // interface used by the queue is already initialized.
+ if (ticker->queue->initialized) {
+ return;
+ }
+
+ ticker->interface->init();
+
+ const ticker_info_t *info = ticker->interface->get_info();
+ uint32_t frequency = info->frequency;
+ if (info->frequency == 0) {
+ MBED_ASSERT(0);
+ frequency = 1000000;
+ }
+
+ uint8_t frequency_shifts = 0;
+ for (uint8_t i = 31; i > 0; --i) {
+ if ((1 << i) == frequency) {
+ frequency_shifts = i;
+ break;
+ }
+ }
+
+ uint32_t bits = info->bits;
+ if ((info->bits > 32) || (info->bits < 4)) {
+ MBED_ASSERT(0);
+ bits = 32;
+ }
+ uint32_t max_delta = 0x7 << (bits - 4); // 7/16th
+ uint64_t max_delta_us =
+ ((uint64_t)max_delta * 1000000 + frequency - 1) / frequency;
+
+ ticker->queue->event_handler = NULL;
+ ticker->queue->head = NULL;
+ ticker->queue->tick_last_read = ticker->interface->read();
+ ticker->queue->tick_remainder = 0;
+ ticker->queue->frequency = frequency;
+ ticker->queue->frequency_shifts = frequency_shifts;
+ ticker->queue->bitmask = ((uint64_t)1 << bits) - 1;
+ ticker->queue->max_delta = max_delta;
+ ticker->queue->max_delta_us = max_delta_us;
+ ticker->queue->present_time = 0;
+ ticker->queue->dispatching = false;
+ ticker->queue->initialized = true;
+
+ update_present_time(ticker);
+ schedule_interrupt(ticker);
+}
+
+/**
+ * Set the event handler function of a ticker instance.
+ */
+static void set_handler(const ticker_data_t *const ticker, ticker_event_handler handler)
+{
+ ticker->queue->event_handler = handler;
+}
+
+/*
+ * Convert a 32 bit timestamp into a 64 bit timestamp.
+ *
+ * A 64 bit timestamp is used as the point of time of reference while the
+ * timestamp to convert is relative to this point of time.
+ *
+ * The lower 32 bits of the timestamp returned will be equal to the timestamp to
+ * convert.
+ *
+ * If the timestamp to convert is less than the lower 32 bits of the time
+ * reference then the timestamp to convert is seen as an overflowed value and
+ * the upper 32 bit of the timestamp returned will be equal to the upper 32 bit
+ * of the reference point + 1.
+ * Otherwise, the upper 32 bit returned will be equal to the upper 32 bit of the
+ * reference point.
+ *
+ * @param ref: The 64 bit timestamp of reference.
+ * @param timestamp: The timestamp to convert.
+ */
+static us_timestamp_t convert_timestamp(us_timestamp_t ref, timestamp_t timestamp)
+{
+ bool overflow = timestamp < ((timestamp_t) ref) ? true : false;
+
+ us_timestamp_t result = (ref & ~((us_timestamp_t)UINT32_MAX)) | timestamp;
+ if (overflow) {
+ result += (1ULL << 32);
+ }
+
+ return result;
+}
+
+/**
+ * Update the present timestamp value of a ticker.
+ */
+static void update_present_time(const ticker_data_t *const ticker)
+{
+ ticker_event_queue_t *queue = ticker->queue;
+ uint32_t ticker_time = ticker->interface->read();
+ if (ticker_time == ticker->queue->tick_last_read) {
+ // No work to do
+ return;
+ }
+
+ uint64_t elapsed_ticks = (ticker_time - queue->tick_last_read) & queue->bitmask;
+ queue->tick_last_read = ticker_time;
+
+ uint64_t elapsed_us;
+ if (1000000 == queue->frequency) {
+ // Optimized for 1MHz
+
+ elapsed_us = elapsed_ticks;
+ } else if (0 != queue->frequency_shifts) {
+ // Optimized for frequencies divisible by 2
+ uint64_t us_x_ticks = elapsed_ticks * 1000000;
+ elapsed_us = us_x_ticks >> queue->frequency_shifts;
+
+ // Update remainder
+ queue->tick_remainder += us_x_ticks - (elapsed_us << queue->frequency_shifts);
+ if (queue->tick_remainder >= queue->frequency) {
+ elapsed_us += 1;
+ queue->tick_remainder -= queue->frequency;
+ }
+ } else {
+ // General case
+
+ uint64_t us_x_ticks = elapsed_ticks * 1000000;
+ elapsed_us = us_x_ticks / queue->frequency;
+
+ // Update remainder
+ queue->tick_remainder += us_x_ticks - elapsed_us * queue->frequency;
+ if (queue->tick_remainder >= queue->frequency) {
+ elapsed_us += 1;
+ queue->tick_remainder -= queue->frequency;
+ }
+ }
+
+ // Update current time
+ queue->present_time += elapsed_us;
+}
+
+/**
+ * Given the absolute timestamp compute the hal tick timestamp.
+ */
+static timestamp_t compute_tick(const ticker_data_t *const ticker, us_timestamp_t timestamp)
+{
+ ticker_event_queue_t *queue = ticker->queue;
+ us_timestamp_t delta_us = timestamp - queue->present_time;
+
+ timestamp_t delta = ticker->queue->max_delta;
+ if (delta_us <= ticker->queue->max_delta_us) {
+ // Checking max_delta_us ensures the operation will not overflow
+
+ if (1000000 == queue->frequency) {
+ // Optimized for 1MHz
+
+ delta = delta_us;
+ if (delta > ticker->queue->max_delta) {
+ delta = ticker->queue->max_delta;
+ }
+ } else if (0 != queue->frequency_shifts) {
+ // Optimized frequencies divisible by 2
+
+ delta = (delta_us << ticker->queue->frequency_shifts) / 1000000;
+ if (delta > ticker->queue->max_delta) {
+ delta = ticker->queue->max_delta;
+ }
+ } else {
+ // General case
+
+ delta = delta_us * queue->frequency / 1000000;
+ if (delta > ticker->queue->max_delta) {
+ delta = ticker->queue->max_delta;
+ }
+ }
+ }
+ return (queue->tick_last_read + delta) & queue->bitmask;
+}
+
+/**
+ * Return 1 if the tick has incremented to or past match_tick, otherwise 0.
+ */
+int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick)
+{
+ if (match_tick > prev_tick) {
+ return (cur_tick >= match_tick) || (cur_tick < prev_tick);
+ } else {
+ return (cur_tick < prev_tick) && (cur_tick >= match_tick);
+ }
+}
+
+/**
+ * Compute the time when the interrupt has to be triggered and schedule it.
+ *
+ * If there is no event in the queue or the next event to execute is in more
+ * than ticker.queue.max_delta ticks from now then the ticker irq will be
+ * scheduled in ticker.queue.max_delta ticks. Otherwise the irq will be
+ * scheduled to happen when the running counter reach the timestamp of the
+ * first event in the queue.
+ *
+ * @note If there is no event in the queue then the interrupt is scheduled to
+ * in ticker.queue.max_delta. This is necessary to keep track
+ * of the timer overflow.
+ */
+static void schedule_interrupt(const ticker_data_t *const ticker)
+{
+ ticker_event_queue_t *queue = ticker->queue;
+ if (ticker->queue->dispatching) {
+ // Don't schedule the next interrupt until dispatching is
+ // finished. This prevents repeated calls to interface->set_interrupt
+ return;
+ }
+
+ update_present_time(ticker);
+
+ if (ticker->queue->head) {
+ us_timestamp_t present = ticker->queue->present_time;
+ us_timestamp_t match_time = ticker->queue->head->timestamp;
+
+ // if the event at the head of the queue is in the past then schedule
+ // it immediately.
+ if (match_time <= present) {
+ ticker->interface->fire_interrupt();
+ return;
+ }
+
+ timestamp_t match_tick = compute_tick(ticker, match_time);
+ // The time has been checked to be future, but it could still round
+ // to the last tick as a result of us to ticks conversion
+ if (match_tick == queue->tick_last_read) {
+ // Match time has already expired so fire immediately
+ ticker->interface->fire_interrupt();
+ return;
+ }
+
+ ticker->interface->set_interrupt(match_tick);
+ timestamp_t cur_tick = ticker->interface->read();
+
+ if (_ticker_match_interval_passed(queue->tick_last_read, cur_tick, match_tick)) {
+ ticker->interface->fire_interrupt();
+ }
+ } else {
+ uint32_t match_tick =
+ (queue->tick_last_read + queue->max_delta) & queue->bitmask;
+ ticker->interface->set_interrupt(match_tick);
+ }
+}
+
+void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler)
+{
+ initialize(ticker);
+
+ core_util_critical_section_enter();
+ set_handler(ticker, handler);
+ core_util_critical_section_exit();
+}
+
+void ticker_irq_handler(const ticker_data_t *const ticker)
+{
+ core_util_critical_section_enter();
+
+ ticker->interface->clear_interrupt();
+
+ /* Go through all the pending TimerEvents */
+ ticker->queue->dispatching = true;
+ while (1) {
+ if (ticker->queue->head == NULL) {
+ break;
+ }
+
+ // update the current timestamp used by the queue
+ update_present_time(ticker);
+
+ if (ticker->queue->head->timestamp <= ticker->queue->present_time) {
+ // This event was in the past:
+ // point to the following one and execute its handler
+ ticker_event_t *p = ticker->queue->head;
+ ticker->queue->head = ticker->queue->head->next;
+ if (ticker->queue->event_handler != NULL) {
+ (*ticker->queue->event_handler)(p->id); // NOTE: the handler can set new events
+ }
+ /* Note: We continue back to examining the head because calling the
+ * event handler may have altered the chain of pending events. */
+ } else {
+ break;
+ }
+ }
+ ticker->queue->dispatching = false;
+
+ schedule_interrupt(ticker);
+
+ core_util_critical_section_exit();
+}
+
+void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id)
+{
+ core_util_critical_section_enter();
+
+ // update the current timestamp
+ update_present_time(ticker);
+ us_timestamp_t absolute_timestamp = convert_timestamp(
+ ticker->queue->present_time,
+ timestamp
+ );
+
+ // defer to ticker_insert_event_us
+ ticker_insert_event_us(
+ ticker,
+ obj, absolute_timestamp, id
+ );
+
+ core_util_critical_section_exit();
+}
+
+void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id)
+{
+ core_util_critical_section_enter();
+
+ // update the current timestamp
+ update_present_time(ticker);
+
+ // initialise our data
+ obj->timestamp = timestamp;
+ obj->id = id;
+
+ /* Go through the list until we either reach the end, or find
+ an element this should come before (which is possibly the
+ head). */
+ ticker_event_t *prev = NULL, *p = ticker->queue->head;
+ while (p != NULL) {
+ /* check if we come before p */
+ if (timestamp < p->timestamp) {
+ break;
+ }
+ /* go to the next element */
+ prev = p;
+ p = p->next;
+ }
+
+ /* if we're at the end p will be NULL, which is correct */
+ obj->next = p;
+
+ /* if prev is NULL we're at the head */
+ if (prev == NULL) {
+ ticker->queue->head = obj;
+ schedule_interrupt(ticker);
+ } else {
+ prev->next = obj;
+ }
+
+ core_util_critical_section_exit();
+}
+
+void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj)
+{
+ core_util_critical_section_enter();
+
+ // remove this object from the list
+ if (ticker->queue->head == obj) {
+ // first in the list, so just drop me
+ ticker->queue->head = obj->next;
+ schedule_interrupt(ticker);
+ } else {
+ // find the object before me, then drop me
+ ticker_event_t *p = ticker->queue->head;
+ while (p != NULL) {
+ if (p->next == obj) {
+ p->next = obj->next;
+ break;
+ }
+ p = p->next;
+ }
+ }
+
+ core_util_critical_section_exit();
+}
+
+timestamp_t ticker_read(const ticker_data_t *const ticker)
+{
+ return ticker_read_us(ticker);
+}
+
+us_timestamp_t ticker_read_us(const ticker_data_t *const ticker)
+{
+ initialize(ticker);
+
+ core_util_critical_section_enter();
+ update_present_time(ticker);
+ core_util_critical_section_exit();
+
+ return ticker->queue->present_time;
+}
+
+int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp)
+{
+ int ret = 0;
+
+ /* if head is NULL, there are no pending events */
+ core_util_critical_section_enter();
+ if (data->queue->head != NULL) {
+ *timestamp = data->queue->head->timestamp;
+ ret = 1;
+ }
+ core_util_critical_section_exit();
+
+ return ret;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/mbed_us_ticker_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/mbed_us_ticker_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/us_ticker_api.h"
+
+static ticker_event_queue_t events = { 0 };
+
+static ticker_irq_handler_type irq_handler = ticker_irq_handler;
+
+static const ticker_interface_t us_interface = {
+ .init = us_ticker_init,
+ .read = us_ticker_read,
+ .disable_interrupt = us_ticker_disable_interrupt,
+ .clear_interrupt = us_ticker_clear_interrupt,
+ .set_interrupt = us_ticker_set_interrupt,
+ .fire_interrupt = us_ticker_fire_interrupt,
+ .get_info = us_ticker_get_info,
+};
+
+static const ticker_data_t us_data = {
+ .interface = &us_interface,
+ .queue = &events
+};
+
+const ticker_data_t *get_us_ticker_data(void)
+{
+ return &us_data;
+}
+
+ticker_irq_handler_type set_us_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler)
+{
+ ticker_irq_handler_type prev_irq_handler = irq_handler;
+
+ irq_handler = ticker_irq_handler;
+
+ return prev_irq_handler;
+}
+
+void us_ticker_irq_handler(void)
+{
+ if (irq_handler) {
+ irq_handler(&us_data);
+ }
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/pinmap.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/pinmap.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,50 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINMAP_H
+#define MBED_PINMAP_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ int peripheral;
+ int function;
+} PinMap;
+
+void pin_function(PinName pin, int function);
+void pin_mode(PinName pin, PinMode mode);
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap *map);
+uint32_t pinmap_function(PinName pin, const PinMap *map);
+uint32_t pinmap_merge(uint32_t a, uint32_t b);
+void pinmap_pinout(PinName pin, const PinMap *map);
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap *map);
+uint32_t pinmap_find_function(PinName pin, const PinMap *map);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/port_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/port_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,93 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTMAP_H
+#define MBED_PORTMAP_H
+
+#include "device.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Port HAL structure. port_s is declared in the target's HAL
+ */
+typedef struct port_s port_t;
+
+/**
+ * \defgroup hal_port Port HAL functions
+ * @{
+ */
+
+/** Get the pin name from the port's pin number
+ *
+ * @param port The port name
+ * @param pin_n The pin number within the specified port
+ * @return The pin name for the port's pin number
+ */
+PinName port_pin(PortName port, int pin_n);
+
+/** Initilize the port
+ *
+ * @param obj The port object to initialize
+ * @param port The port name
+ * @param mask The bitmask to identify which bits in the port should be included (0 - ignore)
+ * @param dir The port direction
+ */
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir);
+
+/** Set the input port mode
+ *
+ * @param obj The port object
+ * @param mode THe port mode to be set
+ */
+void port_mode(port_t *obj, PinMode mode);
+
+/** Set port direction (in/out)
+ *
+ * @param obj The port object
+ * @param dir The port direction to be set
+ */
+void port_dir(port_t *obj, PinDirection dir);
+
+/** Write value to the port
+ *
+ * @param obj The port object
+ * @param value The value to be set
+ */
+void port_write(port_t *obj, int value);
+
+/** Read the current value on the port
+ *
+ * @param obj The port object
+ * @return An integer with each bit corresponding to an associated port pin setting
+ */
+int port_read(port_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/pwmout_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/pwmout_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,120 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_API_H
+#define MBED_PWMOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_PWMOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Pwmout hal structure. pwmout_s is declared in the target's hal
+ */
+typedef struct pwmout_s pwmout_t;
+
+/**
+ * \defgroup hal_pwmout Pwmout hal functions
+ * @{
+ */
+
+/** Initialize the pwm out peripheral and configure the pin
+ *
+ * @param obj The pwmout object to initialize
+ * @param pin The pwmout pin to initialize
+ */
+void pwmout_init(pwmout_t *obj, PinName pin);
+
+/** Deinitialize the pwmout object
+ *
+ * @param obj The pwmout object
+ */
+void pwmout_free(pwmout_t *obj);
+
+/** Set the output duty-cycle in range <0.0f, 1.0f>
+ *
+ * Value 0.0f represents 0 percentage, 1.0f represents 100 percent.
+ * @param obj The pwmout object
+ * @param percent The floating-point percentage number
+ */
+void pwmout_write(pwmout_t *obj, float percent);
+
+/** Read the current float-point output duty-cycle
+ *
+ * @param obj The pwmout object
+ * @return A floating-point output duty-cycle
+ */
+float pwmout_read(pwmout_t *obj);
+
+/** Set the PWM period specified in seconds, keeping the duty cycle the same
+ *
+ * Periods smaller than microseconds (the lowest resolution) are set to zero.
+ * @param obj The pwmout object
+ * @param seconds The floating-point seconds period
+ */
+void pwmout_period(pwmout_t *obj, float seconds);
+
+/** Set the PWM period specified in miliseconds, keeping the duty cycle the same
+ *
+ * @param obj The pwmout object
+ * @param ms The milisecond period
+ */
+void pwmout_period_ms(pwmout_t *obj, int ms);
+
+/** Set the PWM period specified in microseconds, keeping the duty cycle the same
+ *
+ * @param obj The pwmout object
+ * @param us The microsecond period
+ */
+void pwmout_period_us(pwmout_t *obj, int us);
+
+/** Set the PWM pulsewidth specified in seconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param seconds The floating-point pulsewidth in seconds
+ */
+void pwmout_pulsewidth(pwmout_t *obj, float seconds);
+
+/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param ms The floating-point pulsewidth in miliseconds
+ */
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms);
+
+/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param us The floating-point pulsewidth in microseconds
+ */
+void pwmout_pulsewidth_us(pwmout_t *obj, int us);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/rtc_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/rtc_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,187 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/** \addtogroup hal */
+/** @{*/
+
+#ifndef MBED_RTC_API_H
+#define MBED_RTC_API_H
+
+#include "device.h"
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_rtc RTC hal
+ *
+ * The RTC hal provides a low level interface to the Real Time Counter (RTC) of a
+ * target.
+ *
+ * # Defined behaviour
+ * * The function ::rtc_init is safe to call repeatedly - Verified by test ::rtc_init_test.
+ * * RTC accuracy is at least 10% - Verified by test ::rtc_accuracy_test.
+ * * Init/free doesn't stop RTC from counting - Verified by test ::rtc_persist_test.
+ * * Software reset doesn't stop RTC from counting - Verified by test ::rtc_reset_test.
+ * * Sleep modes don't stop RTC from counting - Verified by test ::rtc_sleep_test.
+ * * Shutdown mode doesn't stop RTC from counting - Not verified.
+ * * The functions ::rtc_write/::rtc_read provides availability to set/get RTC time
+ * - Verified by test ::rtc_write_read_test.
+ * * The functions ::rtc_isenabled returns 1 if the RTC is counting and the time has been set,
+ * 0 otherwise - Verified by test ::rtc_enabled_test.
+ *
+ * # Undefined behaviour
+ * * Calling any function other than ::rtc_init before the initialisation of the RTC
+ *
+ * # Potential bugs
+ * * Incorrect overflow handling - Verified by ::rtc_range_test
+ * * Glitches due to ripple counter - Verified by ::rtc_glitch_test
+ *
+ * @see hal_rtc_tests
+ *
+ * @{
+ */
+
+/**
+ * \defgroup hal_rtc_tests RTC hal tests
+ * The RTC test validate proper implementation of the RTC hal.
+ *
+ * To run the RTC hal tests use the command:
+ *
+ * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-rtc*
+ */
+
+
+/** Initialize the RTC peripheral
+ *
+ * Powerup the RTC in perpetration for access. This function must be called
+ * before any other RTC functions ares called. This does not change the state
+ * of the RTC. It just enables access to it.
+ *
+ * @note This function is safe to call repeatedly - Tested by ::rtc_init_test
+ *
+ * Example Implementation Pseudo Code:
+ * @code
+ * void rtc_init()
+ * {
+ * // Enable clock gate so processor can read RTC registers
+ * POWER_CTRL |= POWER_CTRL_RTC_Msk;
+ *
+ * // See if the RTC is already setup
+ * if (!(RTC_STATUS & RTC_STATUS_COUNTING_Msk)) {
+ *
+ * // Setup the RTC clock source
+ * RTC_CTRL |= RTC_CTRL_CLK32_Msk;
+ * }
+ * }
+ * @endcode
+ */
+void rtc_init(void);
+
+/** Deinitialize RTC
+ *
+ * Powerdown the RTC in preparation for sleep, powerdown or reset. That should only
+ * affect the CPU domain and not the time keeping logic.
+ * After this function is called no other RTC functions should be called
+ * except for ::rtc_init.
+ *
+ * @note This function does not stop the RTC from counting - Tested by ::rtc_persist_test
+ *
+ * Example Implementation Pseudo Code:
+ * @code
+ * void rtc_free()
+ * {
+ * // Disable clock gate since processor no longer needs to read RTC registers
+ * POWER_CTRL &= ~POWER_CTRL_RTC_Msk;
+ * }
+ * @endcode
+ */
+void rtc_free(void);
+
+/** Check if the RTC has the time set and is counting
+ *
+ * @retval 0 The time reported by the RTC is not valid
+ * @retval 1 The time has been set the RTC is counting
+ *
+ * Example Implementation Pseudo Code:
+ * @code
+ * int rtc_isenabled()
+ * {
+ * if (RTC_STATUS & RTC_STATUS_COUNTING_Msk) {
+ * return 1;
+ * } else {
+ * return 0;
+ * }
+ * }
+ * @endcode
+ */
+int rtc_isenabled(void);
+
+/** Get the current time from the RTC peripheral
+ *
+ * @return The current time in seconds
+ *
+ * @note Some RTCs are not synchronized with the main clock. If
+ * this is the case with your RTC then you must read the RTC time
+ * in a loop to prevent reading the wrong time due to a glitch.
+ * The test ::rtc_glitch_test is intended to catch this bug.
+ *
+ * Example implementation for an unsynchronized ripple counter:
+ * @code
+ * time_t rtc_read()
+ * {
+ * uint32_t val;
+ * uint32_t last_val;
+ *
+ * // Loop until the same value is read twice
+ * val = RTC_SECONDS;
+ * do {
+ * last_val = val;
+ * val = RTC_SECONDS;
+ * } while (last_val != val);
+ *
+ * return (time_t)val;
+ * }
+ * @endcode
+ */
+time_t rtc_read(void);
+
+/** Write the current time in seconds to the RTC peripheral
+ *
+ * @param t The current time to be set in seconds.
+ *
+ * Example Implementation Pseudo Code:
+ * @code
+ * void rtc_write(time_t t)
+ * {
+ * RTC_SECONDS = t;
+ * }
+ * @endcode
+ */
+void rtc_write(time_t t);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/serial_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/serial_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,307 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+#include "hal/buffer.h"
+#include "hal/dma_api.h"
+
+#if DEVICE_SERIAL
+
+#define SERIAL_EVENT_TX_SHIFT (2)
+#define SERIAL_EVENT_RX_SHIFT (8)
+
+#define SERIAL_EVENT_TX_MASK (0x00FC)
+#define SERIAL_EVENT_RX_MASK (0x3F00)
+
+#define SERIAL_EVENT_ERROR (1 << 1)
+
+/**
+ * @defgroup SerialTXEvents Serial TX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))
+#define SERIAL_EVENT_TX_ALL (SERIAL_EVENT_TX_COMPLETE)
+/**@}*/
+
+/**
+ * @defgroup SerialRXEvents Serial RX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_RX_COMPLETE (1 << (SERIAL_EVENT_RX_SHIFT + 0))
+#define SERIAL_EVENT_RX_OVERRUN_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 1))
+#define SERIAL_EVENT_RX_FRAMING_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 2))
+#define SERIAL_EVENT_RX_PARITY_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 3))
+#define SERIAL_EVENT_RX_OVERFLOW (1 << (SERIAL_EVENT_RX_SHIFT + 4))
+#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))
+#define SERIAL_EVENT_RX_ALL (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \
+ SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \
+ SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)
+/**@}*/
+
+#define SERIAL_RESERVED_CHAR_MATCH (255)
+
+typedef enum {
+ ParityNone = 0,
+ ParityOdd = 1,
+ ParityEven = 2,
+ ParityForced1 = 3,
+ ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+ RxIrq,
+ TxIrq
+} SerialIrq;
+
+typedef enum {
+ FlowControlNone,
+ FlowControlRTS,
+ FlowControlCTS,
+ FlowControlRTSCTS
+} FlowControl;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+#if DEVICE_SERIAL_ASYNCH
+/** Asynch serial HAL structure
+ */
+typedef struct {
+ struct serial_s serial; /**< Target specific serial structure */
+ struct buffer_s tx_buff; /**< TX buffer */
+ struct buffer_s rx_buff; /**< RX buffer */
+ uint8_t char_match; /**< Character to be matched */
+ uint8_t char_found; /**< State of the matched character */
+} serial_t;
+
+#else
+/** Non-asynch serial HAL structure
+ */
+typedef struct serial_s serial_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralSerial Serial Configuration Functions
+ * @{
+ */
+
+/** Initialize the serial peripheral. It sets the default parameters for serial
+ * peripheral, and configures its specifieds pins.
+ *
+ * @param obj The serial object
+ * @param tx The TX pin name
+ * @param rx The RX pin name
+ */
+void serial_init(serial_t *obj, PinName tx, PinName rx);
+
+/** Release the serial peripheral, not currently invoked. It requires further
+ * resource management.
+ *
+ * @param obj The serial object
+ */
+void serial_free(serial_t *obj);
+
+/** Configure the baud rate
+ *
+ * @param obj The serial object
+ * @param baudrate The baud rate to be configured
+ */
+void serial_baud(serial_t *obj, int baudrate);
+
+/** Configure the format. Set the number of bits, parity and the number of stop bits
+ *
+ * @param obj The serial object
+ * @param data_bits The number of data bits
+ * @param parity The parity
+ * @param stop_bits The number of stop bits
+ */
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+/** The serial interrupt handler registration
+ *
+ * @param obj The serial object
+ * @param handler The interrupt handler which will be invoked when the interrupt fires
+ * @param id The SerialBase object
+ */
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+
+/** Configure serial interrupt. This function is used for word-approach
+ *
+ * @param obj The serial object
+ * @param irq The serial IRQ type (RX or TX)
+ * @param enable Set to non-zero to enable events, or zero to disable them
+ */
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);
+
+/** Get character. This is a blocking call, waiting for a character
+ *
+ * @param obj The serial object
+ */
+int serial_getc(serial_t *obj);
+
+/** Send a character. This is a blocking call, waiting for a peripheral to be available
+ * for writing
+ *
+ * @param obj The serial object
+ * @param c The character to be sent
+ */
+void serial_putc(serial_t *obj, int c);
+
+/** Check if the serial peripheral is readable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be read, 0 if nothing to read
+ */
+int serial_readable(serial_t *obj);
+
+/** Check if the serial peripheral is writable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be written, 0 otherwise.
+ */
+int serial_writable(serial_t *obj);
+
+/** Clear the serial peripheral
+ *
+ * @param obj The serial object
+ */
+void serial_clear(serial_t *obj);
+
+/** Set the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_set(serial_t *obj);
+
+/** Clear the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_clear(serial_t *obj);
+
+/** Configure the TX pin for UART function.
+ *
+ * @param tx The pin name used for TX
+ */
+void serial_pinout_tx(PinName tx);
+
+/** Configure the serial for the flow control. It sets flow control in the hardware
+ * if a serial peripheral supports it, otherwise software emulation is used.
+ *
+ * @param obj The serial object
+ * @param type The type of the flow control. Look at the available FlowControl types.
+ * @param rxflow The TX pin name
+ * @param txflow The RX pin name
+ */
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
+
+#if DEVICE_SERIAL_ASYNCH
+
+/**@}*/
+
+/**
+ * \defgroup hal_AsynchSerial Asynchronous Serial Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,
+ * tx_buff
+ *
+ * @param obj The serial object
+ * @param tx The transmit buffer
+ * @param tx_length The number of bytes to transmit
+ * @param tx_width Deprecated argument
+ * @param handler The serial handler
+ * @param event The logical OR of events to be registered
+ * @param hint A suggestion for how to use DMA with this transfer
+ * @return Returns number of data transfered, otherwise returns 0
+ */
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** Begin asynchronous RX transfer (enable interrupt for data collecting)
+ * The used buffer is specified in the serial object - rx_buff
+ *
+ * @param obj The serial object
+ * @param rx The receive buffer
+ * @param rx_length The number of bytes to receive
+ * @param rx_width Deprecated argument
+ * @param handler The serial handler
+ * @param event The logical OR of events to be registered
+ * @param handler The serial handler
+ * @param char_match A character in range 0-254 to be matched
+ * @param hint A suggestion for how to use DMA with this transfer
+ */
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);
+
+/** Attempts to determine if the serial peripheral is already in use for TX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_tx_active(serial_t *obj);
+
+/** Attempts to determine if the serial peripheral is already in use for RX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_rx_active(serial_t *obj);
+
+/** The asynchronous TX and RX handler.
+ *
+ * @param obj The serial object
+ * @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0
+ */
+int serial_irq_handler_asynch(serial_t *obj);
+
+/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
+ * flushes the TX hardware buffer if TX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_tx_abort_asynch(serial_t *obj);
+
+/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and
+ * flushes the RX hardware buffer if RX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_rx_abort_asynch(serial_t *obj);
+
+/**@}*/
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/sleep_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/sleep_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,102 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_API_H
+#define MBED_SLEEP_API_H
+
+#include "device.h"
+
+#if DEVICE_SLEEP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_sleep sleep hal requirements
+ * Low level interface to the sleep mode of a target.
+ *
+ * # Defined behaviour
+ *
+ * * Sleep mode
+ * * wake-up time should be less than 10 us - Verified by sleep_usticker_test().
+ * * the processor can be woken up by any internal peripheral interrupt - Verified by sleep_usticker_test().
+ * * all peripherals operate as in run mode - not verified.
+ * * the processor can be woken up by external pin interrupt - not verified.
+ * * Deep sleep
+ * * the wake-up time should be less than 10 ms - Verified by deepsleep_lpticker_test().
+ * * lp ticker should wake up a target from this mode - Verified by deepsleep_lpticker_test().
+ * * RTC should wake up a target from this mode - not verified.
+ * * an external interrupt on a pin should wake up a target from this mode - not verified.
+ * * a watchdog timer should wake up a target from this mode - not verified.
+ * * High-speed clocks are turned off - Verified by deepsleep_high_speed_clocks_turned_off_test().
+ * * RTC keeps time - Verified by rtc_sleep_test().
+ *
+ * # Undefined behaviour
+ *
+ * * peripherals aside from RTC, GPIO and lp ticker result in undefined behaviour in deep sleep.
+ * @{
+ */
+
+/**
+ * \defgroup hal_sleep_tests sleep hal tests
+ * The sleep HAL tests ensure driver conformance to defined behaviour.
+ *
+ * To run the sleep hal tests use the command:
+ *
+ * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-sleep*
+ *
+ */
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep. In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * The wake-up time shall be less than 10 us.
+ *
+ */
+void hal_sleep(void);
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and high frequency clocks.
+ * All state is still maintained.
+ *
+ * The processor can only be woken up by low power ticker, RTC, an external interrupt on a pin or a watchdog timer.
+ *
+ * The wake-up time shall be less than 10 ms.
+ */
+void hal_deepsleep(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/**@}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/spi_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/spi_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,238 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_API_H
+#define MBED_SPI_API_H
+
+#include "device.h"
+#include "hal/dma_api.h"
+#include "hal/buffer.h"
+
+#if DEVICE_SPI
+
+#define SPI_EVENT_ERROR (1 << 1)
+#define SPI_EVENT_COMPLETE (1 << 2)
+#define SPI_EVENT_RX_OVERFLOW (1 << 3)
+#define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
+
+#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
+
+#define SPI_FILL_WORD (0xFFFF)
+#define SPI_FILL_CHAR (0xFF)
+
+#if DEVICE_SPI_ASYNCH
+/** Asynch SPI HAL structure
+ */
+typedef struct {
+ struct spi_s spi; /**< Target specific SPI structure */
+ struct buffer_s tx_buff; /**< Tx buffer */
+ struct buffer_s rx_buff; /**< Rx buffer */
+} spi_t;
+
+#else
+/** Non-asynch SPI HAL structure
+ */
+typedef struct spi_s spi_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralSPI SPI Configuration Functions
+ * @{
+ */
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj The SPI object to initialize
+ * @param[in] mosi The pin to use for MOSI
+ * @param[in] miso The pin to use for MISO
+ * @param[in] sclk The pin to use for SCLK
+ * @param[in] ssel The pin to use for SSEL
+ */
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+/** Release a SPI object
+ *
+ * TODO: spi_free is currently unimplemented
+ * This will require reference counting at the C++ level to be safe
+ *
+ * Return the pins owned by the SPI object to their reset state
+ * Disable the SPI peripheral
+ * Disable the SPI clock
+ * @param[in] obj The SPI object to deinitialize
+ */
+void spi_free(spi_t *obj);
+
+/** Configure the SPI format
+ *
+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
+ * The default bit order is MSB.
+ * @param[in,out] obj The SPI object to configure
+ * @param[in] bits The number of bits per frame
+ * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
+ * @param[in] slave Zero for master mode or non-zero for slave mode
+ */
+void spi_format(spi_t *obj, int bits, int mode, int slave);
+
+/** Set the SPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock
+ * Configures the SPI peripheral's baud rate
+ * @param[in,out] obj The SPI object to configure
+ * @param[in] hz The baud rate in Hz
+ */
+void spi_frequency(spi_t *obj, int hz);
+
+/**@}*/
+/**
+ * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Write a byte out in master mode and receive a value
+ *
+ * @param[in] obj The SPI peripheral to use for sending
+ * @param[in] value The value to send
+ * @return Returns the value received during send
+ */
+int spi_master_write(spi_t *obj, int value);
+
+/** Write a block out in master mode and receive a value
+ *
+ * The total number of bytes sent and received will be the maximum of
+ * tx_length and rx_length. The bytes written will be padded with the
+ * value 0xff.
+ *
+ * @param[in] obj The SPI peripheral to use for sending
+ * @param[in] tx_buffer Pointer to the byte-array of data to write to the device
+ * @param[in] tx_length Number of bytes to write, may be zero
+ * @param[in] rx_buffer Pointer to the byte-array of data to read from the device
+ * @param[in] rx_length Number of bytes to read, may be zero
+ * @param[in] write_fill Default data transmitted while performing a read
+ * @returns
+ * The number of bytes written and read from the device. This is
+ * maximum of tx_length and rx_length.
+ */
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill);
+
+/** Check if a value is available to read
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if a value is available
+ */
+int spi_slave_receive(spi_t *obj);
+
+/** Get a received value out of the SPI receive buffer in slave mode
+ *
+ * Blocks until a value is available
+ * @param[in] obj The SPI peripheral to read
+ * @return The value received
+ */
+int spi_slave_read(spi_t *obj);
+
+/** Write a value to the SPI peripheral in slave mode
+ *
+ * Blocks until the SPI peripheral can be written to
+ * @param[in] obj The SPI peripheral to write
+ * @param[in] value The value to write
+ */
+void spi_slave_write(spi_t *obj, int value);
+
+/** Checks if the specified SPI peripheral is in use
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if the peripheral is currently transmitting
+ */
+int spi_busy(spi_t *obj);
+
+/** Get the module number
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return The module number
+ */
+uint8_t spi_get_module(spi_t *obj);
+
+/**@}*/
+
+#if DEVICE_SPI_ASYNCH
+/**
+ * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
+ *
+ * @param[in] obj The SPI object that holds the transfer information
+ * @param[in] tx The transmit buffer
+ * @param[in] tx_length The number of bytes to transmit
+ * @param[in] rx The receive buffer
+ * @param[in] rx_length The number of bytes to receive
+ * @param[in] bit_width The bit width of buffer words
+ * @param[in] event The logical OR of events to be registered
+ * @param[in] handler SPI interrupt handler
+ * @param[in] hint A suggestion for how to use DMA with this transfer
+ */
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *
+ * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
+ * conditions, such as buffer overflows or transfer complete.
+ * @param[in] obj The SPI object that holds the transfer information
+ * @return Event flags if a transfer termination condition was met; otherwise 0.
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj);
+
+/** Attempts to determine if the SPI peripheral is already in use
+ *
+ * If a temporary DMA channel has been allocated, peripheral is in use.
+ * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
+ * channel were allocated.
+ * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
+ * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
+ * there are any bytes in the FIFOs.
+ * @param[in] obj The SPI object to check for activity
+ * @return Non-zero if the SPI port is active or zero if it is not.
+ */
+uint8_t spi_active(spi_t *obj);
+
+/** Abort an SPI transfer
+ *
+ * @param obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj);
+
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // SPI_DEVICE
+
+#endif // MBED_SPI_API_H
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/storage_abstraction/Driver_Common.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/storage_abstraction/Driver_Common.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,60 @@
+
+/** \addtogroup hal */
+/** @{*/
+/*
+ * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_COMMON_H
+#define __DRIVER_COMMON_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/****** This file has been deprecated since mbed-os-5.5 *****/
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+ uint16_t api; ///< API version
+ uint16_t drv; ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK 0 ///< Operation succeeded
+#define ARM_DRIVER_ERROR -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors
+
+/**
+\brief General power states
+*/
+typedef enum _ARM_POWER_STATE {
+ ARM_POWER_OFF, ///< Power off: no operation possible
+ ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
+ ARM_POWER_FULL ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* __DRIVER_COMMON_H */
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/storage_abstraction/Driver_Storage.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/storage_abstraction/Driver_Storage.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,775 @@
+
+/** \addtogroup hal */
+/** @{*/
+/*
+ * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_STORAGE_H
+#define __DRIVER_STORAGE_H
+
+#include <stdint.h>
+
+/****** This file has been deprecated since mbed-os-5.5 *****/
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "Driver_Common.h"
+
+#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,00) /* API version */
+
+
+#define _ARM_Driver_Storage_(n) Driver_Storage##n
+#define ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)
+
+#define ARM_STORAGE_INVALID_OFFSET (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's
+ ///< address space). A storage block may never start at this address.
+
+#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL) ///< Invalid address within the processor's memory address space.
+ ///< Refer to memory-mapped storage, i.e. < \ref ARM_DRIVER_STORAGE::ResolveAddress().
+
+/****** Storage specific error codes *****/
+#define ARM_STORAGE_ERROR_NOT_ERASABLE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.
+#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.
+#define ARM_STORAGE_ERROR_PROTECTED (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.
+#define ARM_STORAGE_ERROR_RUNTIME_OR_INTEGRITY_FAILURE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Runtime or sanity-check failure.
+
+/**
+ * \brief Attributes of the storage range within a storage block.
+ */
+typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {
+ uint32_t erasable : 1; ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.
+ ///< @note: if 'erasable' is 0--i.e. the 'erase' operation isn't available--then
+ ///< 'erase_unit' (see below) is immaterial and should be 0.
+ uint32_t programmable : 1; ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.
+ ///< Writes are typically achieved through the ProgramData operation (following an erase);
+ ///< if storage isn't erasable (see 'erasable' above) but is memory-mapped
+ ///< (i.e. 'memory_mapped'), it can be written directly using memory-store operations.
+ uint32_t executable : 1; ///< This storage block can hold program data; the processor can fetch and execute code
+ ///< sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO).
+ uint32_t protectable : 1; ///< The entire block can be protected from program and erase operations. Once protection
+ ///< is enabled for a block, its 'erasable' and 'programmable' bits are turned off.
+ uint32_t reserved : 28;
+ uint32_t erase_unit; ///< Minimum erase size in bytes.
+ ///< The offset of the start of the erase-range should also be aligned with this value.
+ ///< Applicable if the 'erasable' attribute is set for the block.
+ ///< @note: if 'erasable' (see above) is 0--i.e. the 'erase' operation isn't available--then
+ ///< 'erase_unit' is immaterial and should be 0.
+ uint32_t protection_unit; ///< Minimum protectable size in bytes. Applicable if the 'protectable'
+ ///< attribute is set for the block. This should be a divisor of the block's size. A
+ ///< block can be considered to be made up of consecutive, individually-protectable fragments.
+} ARM_STORAGE_BLOCK_ATTRIBUTES;
+
+/**
+ * \brief A storage block is a range of memory with uniform attributes. Storage blocks
+ * combine to make up the address map of a storage controller.
+ */
+typedef struct _ARM_STORAGE_BLOCK {
+ uint64_t addr; ///< This is the start address of the storage block. It is
+ ///< expressed as an offset from the start of the storage map
+ ///< maintained by the owning storage controller.
+ uint64_t size; ///< This is the size of the storage block, in units of bytes.
+ ///< Together with addr, it describes a range [addr, addr+size).
+ ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.
+} ARM_STORAGE_BLOCK;
+
+/**
+ * The check for a valid ARM_STORAGE_BLOCK.
+ */
+#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))
+
+/**
+ * \brief Values for encoding storage memory-types with respect to programmability.
+ *
+ * Please ensure that the maximum of the following memory types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.
+ */
+#define ARM_STORAGE_PROGRAMMABILITY_RAM (0x0)
+#define ARM_STORAGE_PROGRAMMABILITY_ROM (0x1) ///< Read-only memory.
+#define ARM_STORAGE_PROGRAMMABILITY_WORM (0x2) ///< write-once-read-only-memory (WORM).
+#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE (0x3) ///< re-programmable based on erase. Supports multiple writes.
+
+/**
+ * Values for encoding data-retention levels for storage blocks.
+ *
+ * Please ensure that the maximum of the following retention types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.
+ */
+#define ARM_RETENTION_WHILE_DEVICE_ACTIVE (0x0) ///< Data is retained only during device activity.
+#define ARM_RETENTION_ACROSS_SLEEP (0x1) ///< Data is retained across processor sleep.
+#define ARM_RETENTION_ACROSS_DEEP_SLEEP (0x2) ///< Data is retained across processor deep-sleep.
+#define ARM_RETENTION_BATTERY_BACKED (0x3) ///< Data is battery-backed. Device can be powered off.
+#define ARM_RETENTION_NVM (0x4) ///< Data is retained in non-volatile memory.
+
+/**
+ * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.
+ */
+typedef struct _ARM_STORAGE_SECURITY_FEATURES {
+ uint32_t acls : 1; ///< Protection against internal software attacks using ACLs.
+ uint32_t rollback_protection : 1; ///< Roll-back protection. Set to true if the creator of the storage
+ ///< can ensure that an external attacker can't force an
+ ///< older firmware to run or to revert back to a previous state.
+ uint32_t tamper_proof : 1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).
+ uint32_t internal_flash : 1; ///< Internal flash.
+ uint32_t reserved1 : 12;
+
+ /**
+ * Encode support for hardening against various classes of attacks.
+ */
+ uint32_t software_attacks : 1; ///< device software (malware running on the device).
+ uint32_t board_level_attacks : 1; ///< board level attacks (debug probes, copy protection fuses.)
+ uint32_t chip_level_attacks : 1; ///< chip level attacks (tamper-protection).
+ uint32_t side_channel_attacks : 1; ///< side channel attacks.
+ uint32_t reserved2 : 12;
+} ARM_STORAGE_SECURITY_FEATURES;
+
+#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */
+
+/**
+ * \brief Storage information. This contains device-metadata. It is the return
+ * value from calling GetInfo() on the storage driver.
+ *
+ * \details These fields serve a different purpose than the ones contained in
+ * \ref ARM_STORAGE_CAPABILITIES, which is another structure containing
+ * device-level metadata. ARM_STORAGE_CAPABILITIES describes the API
+ * capabilities, whereas ARM_STORAGE_INFO describes the device. Furthermore
+ * ARM_STORAGE_CAPABILITIES fits within a single word, and is designed to be
+ * passed around by value; ARM_STORAGE_INFO, on the other hand, contains
+ * metadata which doesn't fit into a single word and requires the use of
+ * pointers to be moved around.
+ */
+typedef struct _ARM_STORAGE_INFO {
+ uint64_t total_storage; ///< Total available storage, in bytes.
+ uint32_t program_unit; ///< Minimum programming size in bytes.
+ ///< The offset of the start of the program-range should also be aligned with this value.
+ ///< Applicable only if the 'programmable' attribute is set for a block.
+ ///< @note: setting program_unit to 0 has the effect of disabling the size and alignment
+ ///< restrictions (setting it to 1 also has the same effect).
+ uint32_t optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers
+ ///< have internal buffers into which to receive data. Writing in chunks of
+ ///< 'optimal_program_unit' would achieve maximum programming speed.
+ ///< Applicable only if the 'programmable' attribute is set for the underlying block(s).
+ uint32_t program_cycles; ///< A measure of endurance for reprogramming.
+ ///< Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.
+ uint32_t erased_value : 1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).
+ uint32_t memory_mapped : 1; ///< This storage device has a mapping onto the processor's memory address space.
+ ///< @note: For a memory-mapped block which isn't erasable but is programmable (i.e. if
+ ///< 'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to
+ ///< the memory-mapped storage without going through the ProgramData operation.
+ uint32_t programmability : 4; ///< A value to indicate storage programmability.
+ uint32_t retention_level : 4;
+ uint32_t reserved : 22;
+ ARM_STORAGE_SECURITY_FEATURES security; ///< \ref ARM_STORAGE_SECURITY_FEATURES
+} ARM_STORAGE_INFO;
+
+/**
+\brief Operating status of the storage controller.
+*/
+typedef struct _ARM_STORAGE_STATUS {
+ uint32_t busy : 1; ///< Controller busy flag
+ uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
+} ARM_STORAGE_STATUS;
+
+/**
+ * \brief Storage Driver API Capabilities.
+ *
+ * This data structure is designed to fit within a single word so that it can be
+ * fetched cheaply using a call to driver->GetCapabilities().
+ */
+typedef struct _ARM_STORAGE_CAPABILITIES {
+ uint32_t asynchronous_ops : 1; ///< Used to indicate if APIs like initialize,
+ ///< read, erase, program, etc. can operate in asynchronous mode.
+ ///< Setting this bit to 1 means that the driver is capable
+ ///< of launching asynchronous operations; command completion is
+ ///< signaled by the invocation of a completion callback. If
+ ///< set to 1, drivers may still complete asynchronous
+ ///< operations synchronously as necessary--in which case they
+ ///< return a positive error code to indicate synchronous completion.
+ uint32_t erase_all : 1; ///< Supports EraseAll operation.
+ uint32_t reserved : 30;
+} ARM_STORAGE_CAPABILITIES;
+
+/**
+ * Command opcodes for Storage. Completion callbacks use these codes to refer to
+ * completing commands. Refer to \ref ARM_Storage_Callback_t.
+ */
+typedef enum _ARM_STORAGE_OPERATION {
+ ARM_STORAGE_OPERATION_GET_VERSION,
+ ARM_STORAGE_OPERATION_GET_CAPABILITIES,
+ ARM_STORAGE_OPERATION_INITIALIZE,
+ ARM_STORAGE_OPERATION_UNINITIALIZE,
+ ARM_STORAGE_OPERATION_POWER_CONTROL,
+ ARM_STORAGE_OPERATION_READ_DATA,
+ ARM_STORAGE_OPERATION_PROGRAM_DATA,
+ ARM_STORAGE_OPERATION_ERASE,
+ ARM_STORAGE_OPERATION_ERASE_ALL,
+ ARM_STORAGE_OPERATION_GET_STATUS,
+ ARM_STORAGE_OPERATION_GET_INFO,
+ ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,
+ ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,
+ ARM_STORAGE_OPERATION_GET_BLOCK
+} ARM_STORAGE_OPERATION;
+
+/**
+ * Declaration of the callback-type for command completion.
+ *
+ * @param [in] status
+ * A code to indicate the status of the completed operation. For data
+ * transfer operations, the status field is overloaded in case of
+ * success to return the count of items successfully transferred; this
+ * can be done safely because error codes are negative values.
+ *
+ * @param [in] operation
+ * The command op-code. This value isn't essential for the callback in
+ * the presence of the command instance-id, but it is expected that
+ * this information could be a quick and useful filter.
+ */
+typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);
+
+/**
+ * This is the set of operations constituting the Storage driver. Their
+ * implementation is platform-specific, and needs to be supplied by the
+ * porting effort.
+ *
+ * Some APIs within `ARM_DRIVER_STORAGE` will always operate synchronously:
+ * GetVersion, GetCapabilities, GetStatus, GetInfo, ResolveAddress,
+ * GetNextBlock, and GetBlock. This means that control returns to the caller
+ * with a relevant status code only after the completion of the operation (or
+ * the discovery of a failure condition).
+ *
+ * The remainder of the APIs: Initialize, Uninitialize, PowerControl, ReadData,
+ * ProgramData, Erase, EraseAll, can function asynchronously if the underlying
+ * controller supports it--i.e. if ARM_STORAGE_CAPABILITIES::asynchronous_ops is
+ * set. In the case of asynchronous operation, the invocation returns early
+ * (with ARM_DRIVER_OK) and results in a completion callback later. If
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is not set, then all such APIs
+ * execute synchronously, and control returns to the caller with a status code
+ * only after the completion of the operation (or the discovery of a failure
+ * condition).
+ *
+ * If ARM_STORAGE_CAPABILITIES::asynchronous_ops is set, a storage driver may
+ * still choose to execute asynchronous operations in a synchronous manner. If
+ * so, the driver returns a positive value to indicate successful synchronous
+ * completion (or an error code in case of failure) and no further invocation of
+ * completion callback should be expected. The expected return value for
+ * synchronous completion of such asynchronous operations varies depending on
+ * the operation. For operations involving data access, it often equals the
+ * amount of data transferred or affected. For non data-transfer operations,
+ * such as EraseAll or Initialize, it is usually 1.
+ *
+ * Here's a code snippet to suggest how asynchronous APIs might be used by
+ * callers to handle both synchronous and asynchronous execution by the
+ * underlying storage driver:
+ * \code
+ * ASSERT(ARM_DRIVER_OK == 0); // this is a precondition; it doesn't need to be put in code
+ * int32_t returnValue = drv->asynchronousAPI(...);
+ * if (returnValue < ARM_DRIVER_OK) {
+ * // handle error.
+ * } else if (returnValue == ARM_DRIVER_OK) {
+ * ASSERT(drv->GetCapabilities().asynchronous_ops == 1);
+ * // handle early return from asynchronous execution; remainder of the work is done in the callback handler.
+ * } else {
+ * ASSERT(returnValue == EXPECTED_RETURN_VALUE_FOR_SYNCHRONOUS_COMPLETION);
+ * // handle synchronous completion.
+ * }
+ * \endcode
+ */
+typedef struct _ARM_DRIVER_STORAGE {
+ /**
+ * \brief Get driver version.
+ *
+ * The function GetVersion() returns version information of the driver implementation in ARM_DRIVER_VERSION.
+ *
+ * - API version is the version of the CMSIS-Driver specification used to implement this driver.
+ * - Driver version is source code version of the actual driver implementation.
+ *
+ * Example:
+ * \code
+ * extern ARM_DRIVER_STORAGE *drv_info;
+ *
+ * void read_version (void) {
+ * ARM_DRIVER_VERSION version;
+ *
+ * version = drv_info->GetVersion ();
+ * if (version.api < 0x10A) { // requires at minimum API version 1.10 or higher
+ * // error handling
+ * return;
+ * }
+ * }
+ * \endcode
+ *
+ * @return \ref ARM_DRIVER_VERSION.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ *
+ * @note The function GetVersion() can be called any time to obtain the
+ * required information from the driver (even before initialization). It
+ * always returns the same information.
+ */
+ ARM_DRIVER_VERSION (*GetVersion)(void);
+
+ /**
+ * \brief Get driver capabilities.
+ *
+ * \details The function GetCapabilities() returns information about
+ * capabilities in this driver implementation. The data fields of the struct
+ * ARM_STORAGE_CAPABILITIES encode various capabilities, for example if the device
+ * is able to execute operations asynchronously.
+ *
+ * Example:
+ * \code
+ * extern ARM_DRIVER_STORAGE *drv_info;
+ *
+ * void read_capabilities (void) {
+ * ARM_STORAGE_CAPABILITIES drv_capabilities;
+ *
+ * drv_capabilities = drv_info->GetCapabilities ();
+ * // interrogate capabilities
+ *
+ * }
+ * \endcode
+ *
+ * @return \ref ARM_STORAGE_CAPABILITIES.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ *
+ * @note The function GetCapabilities() can be called any time to obtain the
+ * required information from the driver (even before initialization). It
+ * always returns the same information.
+ */
+ ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);
+
+ /**
+ * \brief Initialize the Storage Interface.
+ *
+ * The function Initialize is called when the middleware component starts
+ * operation. In addition to bringing the controller to a ready state,
+ * Initialize() receives a callback handler to be invoked upon completion of
+ * asynchronous operations.
+ *
+ * Initialize() needs to be called explicitly before
+ * powering the peripheral using PowerControl(), and before initiating other
+ * accesses to the storage controller.
+ *
+ * The function performs the following operations:
+ * - Initializes the resources needed for the Storage interface.
+ * - Registers the \ref ARM_Storage_Callback_t callback function.
+ *
+ * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
+ * drv->Initialize (...); // Allocate I/O pins
+ * drv->PowerControl (ARM_POWER_FULL); // Power up peripheral, setup IRQ/DMA
+ *
+ * - Initialize() typically allocates the I/O resources (pins) for the
+ * peripheral. The function can be called multiple times; if the I/O resources
+ * are already initialized it performs no operation and just returns with
+ * ARM_DRIVER_OK.
+ *
+ * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
+ * interrupt (NVIC) and optionally DMA. The function can be called multiple
+ * times; if the registers are already set it performs no operation and just
+ * returns with ARM_DRIVER_OK.
+ *
+ * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
+ * drv->PowerControl (ARM_POWER_OFF); // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
+ * drv->Uninitialize (...); // Release I/O pins
+ *
+ * The functions PowerControl and Uninitialize always execute and can be used
+ * to put the peripheral into a Safe State, for example after any data
+ * transmission errors. To restart the peripheral in an error condition,
+ * you should first execute the Stop Sequence and then the Start Sequence.
+ *
+ * @param [in] callback
+ * Caller-defined callback to be invoked upon command completion
+ * for asynchronous APIs (including the completion of
+ * initialization). Use a NULL pointer when no callback
+ * signals are required.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with a status value of ARM_DRIVER_OK or an error-code. In the
+ * case of synchronous execution, control returns after completion with a
+ * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*Initialize)(ARM_Storage_Callback_t callback);
+
+ /**
+ * \brief De-initialize the Storage Interface.
+ *
+ * The function Uninitialize() de-initializes the resources of Storage interface.
+ *
+ * It is called when the middleware component stops operation, and wishes to
+ * release the software resources used by the interface.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with a status value of ARM_DRIVER_OK or an error-code. In the
+ * case of synchronous execution, control returns after completion with a
+ * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*Uninitialize)(void);
+
+ /**
+ * \brief Control the Storage interface power.
+ *
+ * The function \b ARM_Storage_PowerControl operates the power modes of the Storage interface.
+ *
+ * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
+ * drv->Initialize (...); // Allocate I/O pins
+ * drv->PowerControl (ARM_POWER_FULL); // Power up peripheral, setup IRQ/DMA
+ *
+ * - Initialize() typically allocates the I/O resources (pins) for the
+ * peripheral. The function can be called multiple times; if the I/O resources
+ * are already initialized it performs no operation and just returns with
+ * ARM_DRIVER_OK.
+ *
+ * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
+ * interrupt (NVIC) and optionally DMA. The function can be called multiple
+ * times; if the registers are already set it performs no operation and just
+ * returns with ARM_DRIVER_OK.
+ *
+ * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
+ *
+ * drv->PowerControl (ARM_POWER_OFF); // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
+ * drv->Uninitialize (...); // Release I/O pins
+ *
+ * The functions PowerControl and Uninitialize always execute and can be used
+ * to put the peripheral into a Safe State, for example after any data
+ * transmission errors. To restart the peripheral in an error condition,
+ * you should first execute the Stop Sequence and then the Start Sequence.
+ *
+ * @param state
+ * \ref ARM_POWER_STATE. The target power-state for the storage controller.
+ * The parameter state can have the following values:
+ * - ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts
+ * (NVIC) and optionally DMA. Can be called multiple times. If the peripheral
+ * is already in this mode, then the function performs no operation and returns
+ * with ARM_DRIVER_OK.
+ * - ARM_POWER_LOW : may use power saving. Returns ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.
+ * - ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with a status value of ARM_DRIVER_OK or an error-code. In the
+ * case of synchronous execution, control returns after completion with a
+ * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*PowerControl)(ARM_POWER_STATE state);
+
+ /**
+ * \brief read the contents of a given address range from the storage device.
+ *
+ * \details Read the contents of a range of storage memory into a buffer
+ * supplied by the caller. The buffer is owned by the caller and should
+ * remain accessible for the lifetime of this command.
+ *
+ * @param [in] addr
+ * This specifies the address from where to read data.
+ *
+ * @param [out] data
+ * The destination of the read operation. The buffer
+ * is owned by the caller and should remain accessible for the
+ * lifetime of this command.
+ *
+ * @param [in] size
+ * The number of bytes requested to read. The data buffer
+ * should be at least as large as this size.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with the number of successfully transferred bytes passed in as
+ * the 'status' parameter. In the case of synchronous execution, control
+ * returns after completion with a positive transfer-count. Return values
+ * less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*ReadData)(uint64_t addr, void *data, uint32_t size);
+
+ /**
+ * \brief program (write into) the contents of a given address range of the storage device.
+ *
+ * \details Write the contents of a given memory buffer into a range of
+ * storage memory. In the case of flash memory, the destination range in
+ * storage memory typically has its contents in an erased state from a
+ * preceding erase operation. The source memory buffer is owned by the
+ * caller and should remain accessible for the lifetime of this command.
+ *
+ * @param [in] addr
+ * This is the start address of the range to be written into. It
+ * needs to be aligned to the device's \em program_unit
+ * specified in \ref ARM_STORAGE_INFO.
+ *
+ * @param [in] data
+ * The source of the write operation. The buffer is owned by the
+ * caller and should remain accessible for the lifetime of this
+ * command.
+ *
+ * @param [in] size
+ * The number of bytes requested to be written. The buffer
+ * should be at least as large as this size. \note 'size' should
+ * be a multiple of the device's 'program_unit' (see \ref
+ * ARM_STORAGE_INFO).
+ *
+ * @note It is best for the middleware to write in units of
+ * 'optimal_program_unit' (\ref ARM_STORAGE_INFO) of the device.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with the number of successfully transferred bytes passed in as
+ * the 'status' parameter. In the case of synchronous execution, control
+ * returns after completion with a positive transfer-count. Return values
+ * less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*ProgramData)(uint64_t addr, const void *data, uint32_t size);
+
+ /**
+ * @brief Erase Storage range.
+ *
+ * @details This function erases a range of storage specified by [addr, addr +
+ * size). Both 'addr' and 'addr + size' should align with the
+ * 'erase_unit'(s) of the respective owning storage block(s) (see \ref
+ * ARM_STORAGE_BLOCK and \ref ARM_STORAGE_BLOCK_ATTRIBUTES). The range to
+ * be erased will have its contents returned to the un-programmed state--
+ * i.e. to 'erased_value' (see \ref ARM_STORAGE_BLOCK_ATTRIBUTES), which
+ * is usually 1 to indicate the pattern of all ones: 0xFF.
+ *
+ * @param [in] addr
+ * This is the start-address of the range to be erased. It must
+ * start at an 'erase_unit' boundary of the underlying block.
+ *
+ * @param [in] size
+ * Size (in bytes) of the range to be erased. 'addr + size'
+ * must be aligned with the 'erase_unit' of the underlying
+ * block.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return
+ * If the range to be erased doesn't align with the erase_units of the
+ * respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is returned.
+ * If any part of the range is protected, ARM_STORAGE_ERROR_PROTECTED is
+ * returned. If any part of the range is not erasable,
+ * ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All such sanity-check
+ * failures result in the error code being returned synchronously and the
+ * storage bytes within the range remain unaffected.
+ * Otherwise the function executes in the following ways:
+ * If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with the number of successfully erased bytes passed in as
+ * the 'status' parameter. In the case of synchronous execution, control
+ * returns after completion with a positive erase-count. Return values
+ * less than ARM_DRIVER_OK (0) signify errors.
+ *
+ * @note Erase() may return a smaller (positive) value than the size of the
+ * requested range. The returned value indicates the actual number of bytes
+ * erased. It is the caller's responsibility to follow up with an appropriate
+ * request to complete the operation.
+ *
+ * @note in the case of a failed erase (except when
+ * ARM_DRIVER_ERROR_PARAMETER, ARM_STORAGE_ERROR_PROTECTED, or
+ * ARM_STORAGE_ERROR_NOT_ERASABLE is returned synchronously), the
+ * requested range should be assumed to be in an unknown state. The
+ * previous contents may not be retained.
+ */
+ int32_t (*Erase)(uint64_t addr, uint32_t size);
+
+ /**
+ * @brief Erase complete storage. Optional function for faster erase of the complete device.
+ *
+ * This optional function erases the complete device. If the device does not
+ * support global erase then the function returns the error value \ref
+ * ARM_DRIVER_ERROR_UNSUPPORTED. The data field \em 'erase_all' = 1
+ * of the structure \ref ARM_STORAGE_CAPABILITIES encodes that
+ * ARM_STORAGE_EraseAll is supported.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return
+ * If any part of the storage range is protected,
+ * ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the storage
+ * range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All
+ * such sanity-check failures result in the error code being returned
+ * synchronously and the storage bytes within the range remain unaffected.
+ * Otherwise the function executes in the following ways:
+ * If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with ARM_DRIVER_OK passed in as the 'status' parameter. In the
+ * case of synchronous execution, control returns after completion with a
+ * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*EraseAll)(void);
+
+ /**
+ * @brief Get the status of the current (or previous) command executed by the
+ * storage controller; stored in the structure \ref ARM_STORAGE_STATUS.
+ *
+ * @return
+ * The status of the underlying controller.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ */
+ ARM_STORAGE_STATUS (*GetStatus)(void);
+
+ /**
+ * @brief Get information about the Storage device; stored in the structure \ref ARM_STORAGE_INFO.
+ *
+ * @param [out] info
+ * A caller-supplied buffer capable of being filled in with an
+ * \ref ARM_STORAGE_INFO.
+ *
+ * @return ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level
+ * metadata about the storage controller is filled into the supplied
+ * buffer, else an appropriate error value.
+ *
+ * @note It is the caller's responsibility to ensure that the buffer passed in
+ * is able to be initialized with a \ref ARM_STORAGE_INFO.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ */
+ int32_t (*GetInfo)(ARM_STORAGE_INFO *info);
+
+ /**
+ * \brief For memory-mapped storage, resolve an address relative to
+ * the storage controller into a memory address.
+ *
+ * @param addr
+ * This is the address for which we want a resolution to the
+ * processor's physical address space. It is an offset from the
+ * start of the storage map maintained by the owning storage
+ * controller.
+ *
+ * @return
+ * The resolved address in the processor's address space; else
+ * ARM_STORAGE_INVALID_ADDRESS, if no resolution is possible.
+ *
+ * @note This API returns synchronously. The invocation should return quickly,
+ * and result in a resolved address.
+ */
+ uint32_t (*ResolveAddress)(uint64_t addr);
+
+ /**
+ * @brief Advance to the successor of the current block (iterator), or fetch
+ * the first block (if 'prev_block' is passed in as NULL).
+ *
+ * @details This helper function fetches (an iterator to) the next block (or
+ * the first block if 'prev_block' is passed in as NULL). In the failure
+ * case, a terminating, invalid block iterator is filled into the out
+ * parameter: 'next_block'. In combination with \ref
+ * ARM_STORAGE_VALID_BLOCK(), it can be used to iterate over the sequence
+ * of blocks within the storage map:
+ *
+ * \code
+ * ARM_STORAGE_BLOCK block;
+ * for (drv->GetNextBlock(NULL, &block); ARM_STORAGE_VALID_BLOCK(&block); drv->GetNextBlock(&block, &block)) {
+ * // make use of block
+ * }
+ * \endcode
+ *
+ * @param[in] prev_block
+ * An existing block (iterator) within the same storage
+ * controller. The memory buffer holding this block is owned
+ * by the caller. This pointer may be NULL; if so, the
+ * invocation fills in the first block into the out parameter:
+ * 'next_block'.
+ *
+ * @param[out] next_block
+ * A caller-owned buffer large enough to be filled in with
+ * the following ARM_STORAGE_BLOCK. It is legal to provide the
+ * same buffer using 'next_block' as was passed in with 'prev_block'. It
+ * is also legal to pass a NULL into this parameter if the
+ * caller isn't interested in populating a buffer with the next
+ * block--i.e. if the caller only wishes to establish the
+ * presence of a next block.
+ *
+ * @return ARM_DRIVER_OK if a valid next block is found (or first block, if
+ * prev_block is passed as NULL); upon successful operation, the contents
+ * of the next (or first) block are filled into the buffer pointed to by
+ * the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is
+ * guaranteed to be true. Upon reaching the end of the sequence of blocks
+ * (iterators), or in case the driver is unable to fetch information about
+ * the next (or first) block, an error (negative) value is returned and an
+ * invalid StorageBlock is populated into the supplied buffer. If
+ * prev_block is NULL, the first block is returned.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ */
+ int32_t (*GetNextBlock)(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);
+
+ /**
+ * @brief Find the storage block (iterator) encompassing a given storage address.
+ *
+ * @param[in] addr
+ * Storage address in bytes.
+ *
+ * @param[out] block
+ * A caller-owned buffer large enough to be filled in with the
+ * ARM_STORAGE_BLOCK encapsulating the given address. This value
+ * can also be passed in as NULL if the caller isn't interested
+ * in populating a buffer with the block--if the caller only
+ * wishes to establish the presence of a containing storage
+ * block.
+ *
+ * @return ARM_DRIVER_OK if a containing storage-block is found. In this case,
+ * if block is non-NULL, the buffer pointed to by it is populated with
+ * the contents of the storage block--i.e. if block is valid and a block is
+ * found, ARM_STORAGE_VALID_BLOCK(block) would return true following this
+ * call. If there is no storage block containing the given offset, or in
+ * case the driver is unable to resolve an address to a storage-block, an
+ * error (negative) value is returned and an invalid StorageBlock is
+ * populated into the supplied buffer.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ */
+ int32_t (*GetBlock)(uint64_t addr, ARM_STORAGE_BLOCK *block);
+} const ARM_DRIVER_STORAGE;
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif /* __DRIVER_STORAGE_H */
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/ticker_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/ticker_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,207 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_API_H
+#define MBED_TICKER_API_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "device.h"
+
+/**
+ * Legacy format representing a timestamp in us.
+ * Given it is modeled as a 32 bit integer, this type can represent timestamp
+ * up to 4294 seconds (71 minutes).
+ * Prefer using us_timestamp_t which store timestamp as 64 bits integer.
+ */
+typedef uint32_t timestamp_t;
+
+/**
+ * A us timestamp stored in a 64 bit integer.
+ * Can store timestamp up to 584810 years.
+ */
+typedef uint64_t us_timestamp_t;
+
+/** Ticker's event structure
+ */
+typedef struct ticker_event_s {
+ us_timestamp_t timestamp; /**< Event's timestamp */
+ uint32_t id; /**< TimerEvent object */
+ struct ticker_event_s *next; /**< Next event in the queue */
+} ticker_event_t;
+
+typedef void (*ticker_event_handler)(uint32_t id);
+
+/** Information about the ticker implementation
+ */
+typedef struct {
+ uint32_t frequency; /**< Frequency in Hz this ticker runs at */
+ uint32_t bits; /**< Number of bits this ticker supports */
+} ticker_info_t;
+
+
+/** Ticker's interface structure - required API for a ticker
+ */
+typedef struct {
+ void (*init)(void); /**< Init function */
+ uint32_t (*read)(void); /**< Read function */
+ void (*disable_interrupt)(void); /**< Disable interrupt function */
+ void (*clear_interrupt)(void); /**< Clear interrupt function */
+ void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
+ void (*fire_interrupt)(void); /**< Fire interrupt right-away */
+ const ticker_info_t *(*get_info)(void); /**< Return info about this ticker's implementation */
+} ticker_interface_t;
+
+/** Ticker's event queue structure
+ */
+typedef struct {
+ ticker_event_handler event_handler; /**< Event handler */
+ ticker_event_t *head; /**< A pointer to head */
+ uint32_t frequency; /**< Frequency of the timer in Hz */
+ uint32_t bitmask; /**< Mask to be applied to time values read */
+ uint32_t max_delta; /**< Largest delta in ticks that can be used when scheduling */
+ uint64_t max_delta_us; /**< Largest delta in us that can be used when scheduling */
+ uint32_t tick_last_read; /**< Last tick read */
+ uint64_t tick_remainder; /**< Ticks that have not been added to base_time */
+ us_timestamp_t present_time; /**< Store the timestamp used for present time */
+ bool initialized; /**< Indicate if the instance is initialized */
+ bool dispatching; /**< The function ticker_irq_handler is dispatching */
+ uint8_t frequency_shifts; /**< If frequency is a value of 2^n, this is n, otherwise 0 */
+} ticker_event_queue_t;
+
+/** Ticker's data structure
+ */
+typedef struct {
+ const ticker_interface_t *interface; /**< Ticker's interface */
+ ticker_event_queue_t *queue; /**< Ticker's event queue */
+} ticker_data_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_ticker Ticker HAL functions
+ * @{
+ */
+
+/** Initialize a ticker and set the event handler
+ *
+ * @param ticker The ticker object.
+ * @param handler A handler to be set
+ */
+void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler);
+
+/** IRQ handler that goes through the events to trigger overdue events.
+ *
+ * @param ticker The ticker object.
+ */
+void ticker_irq_handler(const ticker_data_t *const ticker);
+
+/** Remove an event from the queue
+ *
+ * @param ticker The ticker object.
+ * @param obj The event object to be removed from the queue
+ */
+void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj);
+
+/** Insert an event to the queue
+ *
+ * The event will be executed in timestamp - ticker_read().
+ *
+ * @warning This function does not consider timestamp in the past. If an event
+ * is inserted with a timestamp less than the current timestamp then the event
+ * will be executed in timestamp - ticker_read() us.
+ * The internal counter wrap very quickly it is hard to decide weither an
+ * event is in the past or in 1 hour.
+ *
+ * @note prefer the use of ticker_insert_event_us which allows registration of
+ * absolute timestamp.
+ *
+ * @param ticker The ticker object.
+ * @param obj The event object to be inserted to the queue
+ * @param timestamp The event's timestamp
+ * @param id The event object
+ */
+void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
+
+/** Insert an event to the queue
+ *
+ * The event will be executed in timestamp - ticker_read_us() us.
+ *
+ * @note If an event is inserted with a timestamp less than the current
+ * timestamp then the event will be scheduled immediately resulting in
+ * an instant call to event handler.
+ *
+ * @param ticker The ticker object.
+ * @param obj The event object to be inserted to the queue
+ * @param timestamp The event's timestamp
+ * @param id The event object
+ */
+void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id);
+
+/** Read the current (relative) ticker's timestamp
+ *
+ * @warning Return a relative timestamp because the counter wrap every 4294
+ * seconds.
+ *
+ * @param ticker The ticker object.
+ * @return The current timestamp
+ */
+timestamp_t ticker_read(const ticker_data_t *const ticker);
+
+/** Read the current (absolute) ticker's timestamp
+ *
+ * @warning Return an absolute timestamp counting from the initialization of the
+ * ticker.
+ *
+ * @param ticker The ticker object.
+ * @return The current timestamp
+ */
+us_timestamp_t ticker_read_us(const ticker_data_t *const ticker);
+
+/** Read the next event's timestamp
+ *
+ * @param ticker The ticker object.
+ * @param timestamp The timestamp object.
+ * @return 1 if timestamp is pending event, 0 if there's no event pending
+ */
+int ticker_get_next_timestamp(const ticker_data_t *const ticker, timestamp_t *timestamp);
+
+/* Private functions
+ *
+ * @cond PRIVATE
+ *
+ */
+
+int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick);
+
+/*
+ * @endcond PRIVATE
+ *
+ */
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/trng_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/trng_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,72 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRNG_API_H
+#define MBED_TRNG_API_H
+
+#include <stddef.h>
+#include "device.h"
+
+#if DEVICE_TRNG
+
+/** TRNG HAL structure. trng_s is declared in the target's HAL
+ */
+typedef struct trng_s trng_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_trng TRNG hal functions
+ * @{
+ */
+
+/** Initialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
+void trng_init(trng_t *obj);
+
+/** Deinitialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
+void trng_free(trng_t *obj);
+
+/** Get random data from TRNG peripheral
+ *
+ * @param obj The TRNG object
+ * @param output The pointer to an output array
+ * @param length The size of output data, to avoid buffer overwrite
+ * @param output_length The length of generated data
+ * @return 0 success, -1 fail
+ */
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/hal/us_ticker_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/hal/us_ticker_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,282 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_US_TICKER_API_H
+#define MBED_US_TICKER_API_H
+
+#include <stdint.h>
+#include "hal/ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_us_ticker Microsecond Ticker
+ * Low level interface to the microsecond ticker of a target
+ *
+ * # Defined behavior
+ * * Has a reported frequency between 250KHz and 8MHz - Verified by test ::us_ticker_info_test
+ * * Has a counter that is at least 16 bits wide - Verified by test ::us_ticker_info_test
+ * * All behavior defined by the @ref hal_ticker_shared "ticker specification"
+ *
+ * # Undefined behavior
+ * * See the @ref hal_ticker_shared "ticker specification"
+ *
+ * @see hal_us_ticker_tests
+ *
+ * @{
+ */
+
+/**
+ * \defgroup hal_us_ticker_tests Microsecond Ticker tests
+ * Tests to validate the proper implementation of the microsecond ticker
+ *
+ * To run the microsecond ticker hal tests use the command:
+ *
+ * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*,tests-mbed_hal-us_ticker*
+ *
+ * @see hal_ticker_tests
+ *
+ */
+
+/**
+ * \defgroup hal_ticker_shared Ticker Hal
+ * Low level interface to the ticker of a target
+ *
+ * # Defined behavior
+ * * The function ticker_init is safe to call repeatedly - Verified by test ::ticker_init_test
+ * * The function ticker_init allows the ticker to keep counting and disables the ticker interrupt - Verified by test ::ticker_init_test
+ * * Ticker frequency is non-zero and counter is at least 8 bits - Verified by ::ticker_info_test
+ * * The ticker rolls over at (1 << bits) and continues counting starting from 0 - Verified by ::ticker_overflow_test
+ * * The ticker counts at the specified frequency +- 10% - Verified by ::ticker_frequency_test
+ * * The ticker increments by 1 each tick - Verified by ::ticker_increment_test
+ * * The ticker interrupt fires only when the ticker times increments to or past the value set by ticker_set_interrupt.
+ * Verified by ::ticker_interrupt_test and ::ticker_past_test
+ * * It is safe to call ticker_set_interrupt repeatedly before the handler is called - Verified by ::ticker_repeat_reschedule_test
+ * * The function ticker_fire_interrupt causes ticker_irq_handler to be called immediately from interrupt context -
+ * Verified by ::ticker_fire_now_test
+ * * The ticker operations ticker_read, ticker_clear_interrupt, ticker_set_interrupt and ticker_fire_interrupt
+ * take less than 20us to complete - Verified by ::ticker_speed_test
+ *
+ * # Undefined behavior
+ * * Calling any function other than ticker_init before the initialization of the ticker
+ * * Whether ticker_irq_handler is called a second time if the time wraps and matches the value set by ticker_set_interrupt again
+ * * Calling ticker_set_interrupt with a value that has more than the supported number of bits
+ * * Calling any function other than us_ticker_init after calling us_ticker_free
+ *
+ * # Potential bugs
+ * * Drift due to reschedule - Verified by ::ticker_repeat_reschedule_test
+ * * Incorrect overflow handling of timers - Verified by ::ticker_overflow_test
+ * * Interrupting at a time of 0 - Verified by ::ticker_overflow_test
+ * * Interrupt triggered more than once - Verified by ::ticker_interrupt_test
+ *
+ * @ingroup hal_us_ticker
+ * @ingroup hal_lp_ticker
+ */
+
+/**
+ * \defgroup hal_ticker_tests Ticker Tests
+ * Tests to validate the proper implementation of a ticker
+ *
+ * To run the ticker hal tests use the command:
+ *
+ * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*
+ *
+ * @ingroup hal_us_ticker
+ * @ingroup hal_lp_ticker
+ */
+
+
+typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
+
+/** Set ticker IRQ handler
+ *
+ * @param ticker_irq_handler IRQ handler to be connected
+ *
+ * @return previous ticker IRQ handler
+ *
+ * @note by default IRQ handler is set to ::ticker_irq_handler
+ * @note this function is primarily for testing purposes and it's not required part of HAL implementation
+ *
+ */
+ticker_irq_handler_type set_us_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler);
+
+/** Get ticker's data
+ *
+ * @return The microsecond ticker data
+ */
+const ticker_data_t *get_us_ticker_data(void);
+
+
+/** The wrapper for ticker_irq_handler, to pass us ticker's data
+ *
+ */
+void us_ticker_irq_handler(void);
+
+/* HAL us ticker */
+
+/** Initialize the ticker
+ *
+ * Initialize or re-initialize the ticker. This resets all the
+ * clocking and prescaler registers, along with disabling
+ * the compare interrupt.
+ *
+ * @note Initialization properties tested by ::ticker_init_test
+ *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_init()
+ * {
+ * // Enable clock gate so processor can read TIMER registers
+ * POWER_CTRL |= POWER_CTRL_TIMER_Msk;
+ *
+ * // Disable the timer and ensure it is powered down
+ * TIMER_CTRL &= ~(TIMER_CTRL_ENABLE_Msk | TIMER_CTRL_COMPARE_ENABLE_Msk);
+ *
+ * // Configure divisors
+ * uint32_t prescale = SystemCoreClock / 1000000;
+ * TIMER_PRESCALE = prescale - 1;
+ * TIMER_CTRL |= TIMER_CTRL_ENABLE_Msk;
+ *
+ * // Install the interrupt handler
+ * NVIC_SetVector(TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+ * NVIC_EnableIRQ(TIMER_IRQn);
+ * }
+ * @endcode
+ */
+void us_ticker_init(void);
+
+/** Deinitialize the us ticker
+ *
+ * Powerdown the us ticker in preparation for sleep, powerdown, or reset.
+ *
+ * After this function is called, no other ticker functions should be called
+ * except us_ticker_init(), calling any function other than init is undefined.
+ *
+ * @note This function stops the ticker from counting.
+ */
+void us_ticker_free(void);
+
+/** Read the current counter
+ *
+ * Read the current counter value without performing frequency conversions.
+ * If no rollover has occurred, the seconds passed since us_ticker_init()
+ * was called can be found by dividing the ticks returned by this function
+ * by the frequency returned by ::us_ticker_get_info.
+ *
+ * @return The current timer's counter value in ticks
+ *
+ * Pseudo Code:
+ * @code
+ * uint32_t us_ticker_read()
+ * {
+ * return TIMER_COUNT;
+ * }
+ * @endcode
+ */
+uint32_t us_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in ticks to be set
+ *
+ * @note no special handling needs to be done for times in the past
+ * as the common timer code will detect this and call
+ * us_ticker_fire_interrupt() if this is the case
+ *
+ * @note calling this function with timestamp of more than the supported
+ * number of bits returned by ::us_ticker_get_info results in undefined
+ * behavior.
+ *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_set_interrupt(timestamp_t timestamp)
+ * {
+ * TIMER_COMPARE = timestamp;
+ * TIMER_CTRL |= TIMER_CTRL_COMPARE_ENABLE_Msk;
+ * }
+ * @endcode
+ */
+void us_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable us ticker interrupt
+ *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_disable_interrupt(void)
+ * {
+ * // Disable the compare interrupt
+ * TIMER_CTRL &= ~TIMER_CTRL_COMPARE_ENABLE_Msk;
+ * }
+ * @endcode
+ */
+void us_ticker_disable_interrupt(void);
+
+/** Clear us ticker interrupt
+ *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_clear_interrupt(void)
+ * {
+ * // Write to the ICR (interrupt clear register) of the TIMER
+ * TIMER_ICR = TIMER_ICR_COMPARE_Msk;
+ * }
+ * @endcode
+ */
+void us_ticker_clear_interrupt(void);
+
+/** Set pending interrupt that should be fired right away.
+ *
+ * The ticker should be initialized prior calling this function.
+ *
+ * Pseudo Code:
+ * @code
+ * void us_ticker_fire_interrupt(void)
+ * {
+ * NVIC_SetPendingIRQ(TIMER_IRQn);
+ * }
+ * @endcode
+ */
+void us_ticker_fire_interrupt(void);
+
+/** Get frequency and counter bits of this ticker.
+ *
+ * Pseudo Code:
+ * @code
+ * const ticker_info_t* us_ticker_get_info()
+ * {
+ * static const ticker_info_t info = {
+ * 1000000, // 1 MHz
+ * 32 // 32 bit counter
+ * };
+ * return &info;
+ * }
+ * @endcode
+ */
+const ticker_info_t *us_ticker_get_info(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/mbed.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/mbed.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,107 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_H +#define MBED_H + +#include "platform/mbed_version.h" + +#if MBED_CONF_RTOS_PRESENT +#include "rtos/rtos.h" +#endif + +#if MBED_CONF_NSAPI_PRESENT +#include "netsocket/nsapi.h" +#include "netsocket/nsapi_ppp.h" +#endif + +#if MBED_CONF_EVENTS_PRESENT +#include "events/mbed_events.h" +#endif + +#if MBED_CONF_FILESYSTEM_PRESENT +#include "filesystem/mbed_filesystem.h" +#endif + +#include "platform/mbed_toolchain.h" +#include "platform/platform.h" +#include "platform/mbed_application.h" + +// Useful C libraries +#include <math.h> +#include <time.h> + +// mbed Debug libraries +#include "platform/mbed_error.h" +#include "platform/mbed_interface.h" +#include "platform/mbed_assert.h" +#include "platform/mbed_debug.h" + +// mbed Peripheral components +#include "drivers/DigitalIn.h" +#include "drivers/DigitalOut.h" +#include "drivers/DigitalInOut.h" +#include "drivers/BusIn.h" +#include "drivers/BusOut.h" +#include "drivers/BusInOut.h" +#include "drivers/PortIn.h" +#include "drivers/PortInOut.h" +#include "drivers/PortOut.h" +#include "drivers/AnalogIn.h" +#include "drivers/AnalogOut.h" +#include "drivers/PwmOut.h" +#include "drivers/Serial.h" +#include "drivers/SPI.h" +#include "drivers/SPISlave.h" +#include "drivers/I2C.h" +#include "drivers/I2CSlave.h" +#include "drivers/Ethernet.h" +#include "drivers/CAN.h" +#include "drivers/RawSerial.h" +#include "drivers/UARTSerial.h" +#include "drivers/FlashIAP.h" +#include "drivers/MbedCRC.h" + +// mbed Internal components +#include "drivers/Timer.h" +#include "drivers/Ticker.h" +#include "drivers/Timeout.h" +#include "drivers/LowPowerTimeout.h" +#include "drivers/LowPowerTicker.h" +#include "drivers/LowPowerTimer.h" +#include "platform/LocalFileSystem.h" +#include "drivers/InterruptIn.h" +#include "platform/mbed_wait_api.h" +#include "hal/sleep_api.h" +#include "platform/mbed_power_mgmt.h" +#include "platform/mbed_rtc_time.h" +#include "platform/mbed_poll.h" +#include "platform/ATCmdParser.h" +#include "platform/FileSystemHandle.h" +#include "platform/FileHandle.h" +#include "platform/DirHandle.h" +#include "platform/CriticalSectionLock.h" +#include "platform/DeepSleepLock.h" +#include "platform/mbed_stats.h" + +// mbed Non-hardware components +#include "platform/Callback.h" +#include "platform/FunctionPointer.h" +#include "platform/ScopedLock.h" + +using namespace mbed; +using namespace std; + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/ATCmdParser.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/ATCmdParser.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,434 @@
+/* Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * @section DESCRIPTION
+ *
+ * Parser for the AT command syntax
+ *
+ */
+
+#include "ATCmdParser.h"
+#include "mbed_poll.h"
+#include "mbed_debug.h"
+
+#ifdef LF
+#undef LF
+#define LF 10
+#else
+#define LF 10
+#endif
+
+#ifdef CR
+#undef CR
+#define CR 13
+#else
+#define CR 13
+#endif
+
+// getc/putc handling with timeouts
+int ATCmdParser::putc(char c)
+{
+ pollfh fhs;
+ fhs.fh = _fh;
+ fhs.events = POLLOUT;
+
+ int count = poll(&fhs, 1, _timeout);
+ if (count > 0 && (fhs.revents & POLLOUT)) {
+ return _fh->write(&c, 1) == 1 ? 0 : -1;
+ } else {
+ return -1;
+ }
+}
+
+int ATCmdParser::getc()
+{
+ pollfh fhs;
+ fhs.fh = _fh;
+ fhs.events = POLLIN;
+
+ int count = poll(&fhs, 1, _timeout);
+ if (count > 0 && (fhs.revents & POLLIN)) {
+ unsigned char ch;
+ return _fh->read(&ch, 1) == 1 ? ch : -1;
+ } else {
+ return -1;
+ }
+}
+
+void ATCmdParser::flush()
+{
+ while (_fh->readable()) {
+ unsigned char ch;
+ _fh->read(&ch, 1);
+ }
+}
+
+
+// read/write handling with timeouts
+int ATCmdParser::write(const char *data, int size)
+{
+ int i = 0;
+ for (; i < size; i++) {
+ if (putc(data[i]) < 0) {
+ return -1;
+ }
+ }
+ return i;
+}
+
+int ATCmdParser::read(char *data, int size)
+{
+ int i = 0;
+ for (; i < size; i++) {
+ int c = getc();
+ if (c < 0) {
+ return -1;
+ }
+ data[i] = c;
+ }
+ return i;
+}
+
+
+// printf/scanf handling
+int ATCmdParser::vprintf(const char *format, va_list args)
+{
+
+ if (vsprintf(_buffer, format, args) < 0) {
+ return false;
+ }
+
+ int i = 0;
+ for (; _buffer[i]; i++) {
+ if (putc(_buffer[i]) < 0) {
+ return -1;
+ }
+ }
+ return i;
+}
+
+int ATCmdParser::vscanf(const char *format, va_list args)
+{
+ // Since format is const, we need to copy it into our buffer to
+ // add the line's null terminator and clobber value-matches with asterisks.
+ //
+ // We just use the beginning of the buffer to avoid unnecessary allocations.
+ int i = 0;
+ int offset = 0;
+
+ while (format[i]) {
+ if (format[i] == '%' && format[i + 1] != '%' && format[i + 1] != '*') {
+ _buffer[offset++] = '%';
+ _buffer[offset++] = '*';
+ i++;
+ } else {
+ _buffer[offset++] = format[i++];
+ }
+ }
+
+ // Scanf has very poor support for catching errors
+ // fortunately, we can abuse the %n specifier to determine
+ // if the entire string was matched.
+ _buffer[offset++] = '%';
+ _buffer[offset++] = 'n';
+ _buffer[offset++] = 0;
+
+ // To workaround scanf's lack of error reporting, we actually
+ // make two passes. One checks the validity with the modified
+ // format string that only stores the matched characters (%n).
+ // The other reads in the actual matched values.
+ //
+ // We keep trying the match until we succeed or some other error
+ // derails us.
+ int j = 0;
+
+ while (true) {
+ // Ran out of space
+ if (j + 1 >= _buffer_size - offset) {
+ return false;
+ }
+ // Receive next character
+ int c = getc();
+ if (c < 0) {
+ return -1;
+ }
+ _buffer[offset + j++] = c;
+ _buffer[offset + j] = 0;
+
+ // Check for match
+ int count = -1;
+ sscanf(_buffer + offset, _buffer, &count);
+
+ // We only succeed if all characters in the response are matched
+ if (count == j) {
+ // Store the found results
+ vsscanf(_buffer + offset, format, args);
+ return j;
+ }
+ }
+}
+
+
+// Command parsing with line handling
+bool ATCmdParser::vsend(const char *command, va_list args)
+{
+ // Create and send command
+ if (vsprintf(_buffer, command, args) < 0) {
+ return false;
+ }
+
+ for (int i = 0; _buffer[i]; i++) {
+ if (putc(_buffer[i]) < 0) {
+ return false;
+ }
+ }
+
+ // Finish with newline
+ for (size_t i = 0; _output_delimiter[i]; i++) {
+ if (putc(_output_delimiter[i]) < 0) {
+ return false;
+ }
+ }
+
+ debug_if(_dbg_on, "AT> %s\n", _buffer);
+ return true;
+}
+
+bool ATCmdParser::vrecv(const char *response, va_list args)
+{
+restart:
+ _aborted = false;
+ // Iterate through each line in the expected response
+ while (response[0]) {
+ // Since response is const, we need to copy it into our buffer to
+ // add the line's null terminator and clobber value-matches with asterisks.
+ //
+ // We just use the beginning of the buffer to avoid unnecessary allocations.
+ int i = 0;
+ int offset = 0;
+ bool whole_line_wanted = false;
+
+ while (response[i]) {
+ if (response[i] == '%' && response[i + 1] != '%' && response[i + 1] != '*') {
+ _buffer[offset++] = '%';
+ _buffer[offset++] = '*';
+ i++;
+ } else {
+ _buffer[offset++] = response[i++];
+ // Find linebreaks, taking care not to be fooled if they're in a %[^\n] conversion specification
+ if (response[i - 1] == '\n' && !(i >= 3 && response[i - 3] == '[' && response[i - 2] == '^')) {
+ whole_line_wanted = true;
+ break;
+ }
+ }
+ }
+
+ // Scanf has very poor support for catching errors
+ // fortunately, we can abuse the %n specifier to determine
+ // if the entire string was matched.
+ _buffer[offset++] = '%';
+ _buffer[offset++] = 'n';
+ _buffer[offset++] = 0;
+
+ debug_if(_dbg_on, "AT? %s\n", _buffer);
+ // To workaround scanf's lack of error reporting, we actually
+ // make two passes. One checks the validity with the modified
+ // format string that only stores the matched characters (%n).
+ // The other reads in the actual matched values.
+ //
+ // We keep trying the match until we succeed or some other error
+ // derails us.
+ int j = 0;
+
+ while (true) {
+ // Receive next character
+ int c = getc();
+ if (c < 0) {
+ debug_if(_dbg_on, "AT(Timeout)\n");
+ return false;
+ }
+ // Simplify newlines (borrowed from retarget.cpp)
+ if ((c == CR && _in_prev != LF) ||
+ (c == LF && _in_prev != CR)) {
+ _in_prev = c;
+ c = '\n';
+ } else if ((c == CR && _in_prev == LF) ||
+ (c == LF && _in_prev == CR)) {
+ _in_prev = c;
+ // onto next character
+ continue;
+ } else {
+ _in_prev = c;
+ }
+ _buffer[offset + j++] = c;
+ _buffer[offset + j] = 0;
+
+ // Check for oob data
+ for (struct oob *oob = _oobs; oob; oob = oob->next) {
+ if ((unsigned)j == oob->len && memcmp(
+ oob->prefix, _buffer + offset, oob->len) == 0) {
+ debug_if(_dbg_on, "AT! %s\n", oob->prefix);
+ oob->cb();
+
+ if (_aborted) {
+ debug_if(_dbg_on, "AT(Aborted)\n");
+ return false;
+ }
+ // oob may have corrupted non-reentrant buffer,
+ // so we need to set it up again
+ goto restart;
+ }
+ }
+
+ // Check for match
+ int count = -1;
+ if (whole_line_wanted && c != '\n') {
+ // Don't attempt scanning until we get delimiter if they included it in format
+ // This allows recv("Foo: %s\n") to work, and not match with just the first character of a string
+ // (scanf does not itself match whitespace in its format string, so \n is not significant to it)
+ } else {
+ sscanf(_buffer + offset, _buffer, &count);
+ }
+
+ // We only succeed if all characters in the response are matched
+ if (count == j) {
+ debug_if(_dbg_on, "AT= %s\n", _buffer + offset);
+ // Reuse the front end of the buffer
+ memcpy(_buffer, response, i);
+ _buffer[i] = 0;
+
+ // Store the found results
+ vsscanf(_buffer + offset, _buffer, args);
+
+ // Jump to next line and continue parsing
+ response += i;
+ break;
+ }
+
+ // Clear the buffer when we hit a newline or ran out of space
+ // running out of space usually means we ran into binary data
+ if (c == '\n' || j + 1 >= _buffer_size - offset) {
+ debug_if(_dbg_on, "AT< %s", _buffer + offset);
+ j = 0;
+ }
+ }
+ }
+
+ return true;
+}
+
+// Mapping to vararg functions
+int ATCmdParser::printf(const char *format, ...)
+{
+ va_list args;
+ va_start(args, format);
+ int res = vprintf(format, args);
+ va_end(args);
+ return res;
+}
+
+int ATCmdParser::scanf(const char *format, ...)
+{
+ va_list args;
+ va_start(args, format);
+ int res = vscanf(format, args);
+ va_end(args);
+ return res;
+}
+
+bool ATCmdParser::send(const char *command, ...)
+{
+ va_list args;
+ va_start(args, command);
+ bool res = vsend(command, args);
+ va_end(args);
+ return res;
+}
+
+bool ATCmdParser::recv(const char *response, ...)
+{
+ va_list args;
+ va_start(args, response);
+ bool res = vrecv(response, args);
+ va_end(args);
+ return res;
+}
+
+// oob registration
+void ATCmdParser::oob(const char *prefix, Callback<void()> cb)
+{
+ struct oob *oob = new struct oob;
+ oob->len = strlen(prefix);
+ oob->prefix = prefix;
+ oob->cb = cb;
+ oob->next = _oobs;
+ _oobs = oob;
+}
+
+void ATCmdParser::abort()
+{
+ _aborted = true;
+}
+
+bool ATCmdParser::process_oob()
+{
+ if (!_fh->readable()) {
+ return false;
+ }
+
+ int i = 0;
+ while (true) {
+ // Receive next character
+ int c = getc();
+ if (c < 0) {
+ return false;
+ }
+ // Simplify newlines (borrowed from retarget.cpp)
+ if ((c == CR && _in_prev != LF) ||
+ (c == LF && _in_prev != CR)) {
+ _in_prev = c;
+ c = '\n';
+ } else if ((c == CR && _in_prev == LF) ||
+ (c == LF && _in_prev == CR)) {
+ _in_prev = c;
+ // onto next character
+ continue;
+ } else {
+ _in_prev = c;
+ }
+ _buffer[i++] = c;
+ _buffer[i] = 0;
+
+ // Check for oob data
+ struct oob *oob = _oobs;
+ while (oob) {
+ if (i == (int)oob->len && memcmp(
+ oob->prefix, _buffer, oob->len) == 0) {
+ debug_if(_dbg_on, "AT! %s\r\n", oob->prefix);
+ oob->cb();
+ return true;
+ }
+ oob = oob->next;
+ }
+
+ // Clear the buffer when we hit a newline or ran out of space
+ // running out of space usually means we ran into binary data
+ if (((i + 1) >= _buffer_size) || (c == '\n')) {
+ debug_if(_dbg_on, "AT< %s", _buffer);
+ i = 0;
+ }
+ }
+}
+
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/ATCmdParser.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/ATCmdParser.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,318 @@
+/* Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * @section DESCRIPTION
+ *
+ * Parser for the AT command syntax
+ *
+ */
+#ifndef MBED_ATCMDPARSER_H
+#define MBED_ATCMDPARSER_H
+
+#include "mbed.h"
+#include <cstdarg>
+#include "Callback.h"
+
+namespace mbed {
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_ATCmdParser ATCmdParser class
+ * @{
+ */
+
+/**
+ * Parser class for parsing AT commands
+ *
+ * Here are some examples:
+ * @code
+ * UARTSerial serial = UARTSerial(D1, D0);
+ * ATCmdParser at = ATCmdParser(&serial, "\r\n");
+ * int value;
+ * char buffer[100];
+ *
+ * at.send("AT") && at.recv("OK");
+ * at.send("AT+CWMODE=%d", 3) && at.recv("OK");
+ * at.send("AT+CWMODE?") && at.recv("+CWMODE:%d\r\nOK", &value);
+ * at.recv("+IPD,%d:", &value);
+ * at.read(buffer, value);
+ * at.recv("OK");
+ * @endcode
+ */
+
+class ATCmdParser : private NonCopyable<ATCmdParser> {
+private:
+ // File handle
+ // Not owned by ATCmdParser
+ FileHandle *_fh;
+
+ int _buffer_size;
+ char *_buffer;
+ int _timeout;
+
+ // Parsing information
+ const char *_output_delimiter;
+ int _output_delim_size;
+ char _in_prev;
+ bool _dbg_on;
+ bool _aborted;
+
+ struct oob {
+ unsigned len;
+ const char *prefix;
+ mbed::Callback<void()> cb;
+ oob *next;
+ };
+ oob *_oobs;
+
+public:
+
+ /**
+ * Constructor
+ *
+ * @param fh A FileHandle to a digital interface to use for AT commands
+ * @param output_delimiter end of command line termination
+ * @param buffer_size size of internal buffer for transaction
+ * @param timeout timeout of the connection
+ * @param debug turns on/off debug output for AT commands
+ */
+ ATCmdParser(FileHandle *fh, const char *output_delimiter = "\r",
+ int buffer_size = 256, int timeout = 8000, bool debug = false)
+ : _fh(fh), _buffer_size(buffer_size), _in_prev(0), _oobs(NULL)
+ {
+ _buffer = new char[buffer_size];
+ set_timeout(timeout);
+ set_delimiter(output_delimiter);
+ debug_on(debug);
+ }
+
+ /**
+ * Destructor
+ */
+ ~ATCmdParser()
+ {
+ while (_oobs) {
+ struct oob *oob = _oobs;
+ _oobs = oob->next;
+ delete oob;
+ }
+ delete[] _buffer;
+ }
+
+ /**
+ * Allows timeout to be changed between commands
+ *
+ * @param timeout timeout of the connection
+ */
+ void set_timeout(int timeout)
+ {
+ _timeout = timeout;
+ }
+
+ /**
+ * For backwards compatibility.
+ * @deprecated Do not use this function. This function has been replaced with set_timeout for consistency.
+ *
+ * Please use set_timeout(int) API only from now on.
+ * Allows timeout to be changed between commands
+ *
+ * @param timeout timeout of the connection
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with set_timeout for consistency")
+ void setTimeout(int timeout)
+ {
+ set_timeout(timeout);
+ }
+
+ /**
+ * Sets string of characters to use as line delimiters
+ *
+ * @param output_delimiter string of characters to use as line delimiters
+ */
+ void set_delimiter(const char *output_delimiter)
+ {
+ _output_delimiter = output_delimiter;
+ _output_delim_size = strlen(output_delimiter);
+ }
+
+ /**
+ * For backwards compatibility.
+ * @deprecated Do not use this function. This function has been replaced with set_delimiter for consistency.
+ *
+ * Please use set_delimiter(const char *) API only from now on.
+ * Sets string of characters to use as line delimiters
+ *
+ * @param output_delimiter string of characters to use as line delimiters
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with set_delimiter for consistency")
+ void setDelimiter(const char *output_delimiter)
+ {
+ set_delimiter(output_delimiter);
+ }
+
+ /**
+ * Allows traces from modem to be turned on or off
+ *
+ * @param on set as 1 to turn on traces and vice versa.
+ */
+ void debug_on(uint8_t on)
+ {
+ _dbg_on = (on) ? 1 : 0;
+ }
+
+ /**
+ * For backwards compatibility.
+ * @deprecated Do not use this function. This function has been replaced with debug_on for consistency.
+ *
+ * Allows traces from modem to be turned on or off
+ *
+ * @param on set as 1 to turn on traces and vice versa.
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with debug_on for consistency")
+ void debugOn(uint8_t on)
+ {
+ debug_on(on);
+ }
+
+ /**
+ * Sends an AT command
+ *
+ * Sends a formatted command using printf style formatting
+ * @see printf
+ *
+ * @param command printf-like format string of command to send which
+ * is appended with a newline
+ * @param ... all printf-like arguments to insert into command
+ * @return true only if command is successfully sent
+ */
+ bool send(const char *command, ...) MBED_PRINTF_METHOD(1, 2);
+
+ bool vsend(const char *command, va_list args);
+
+ /**
+ * Receive an AT response
+ *
+ * Receives a formatted response using scanf style formatting
+ * @see scanf
+ *
+ * Responses are parsed line at a time.
+ * Any received data that does not match the response is ignored until
+ * a timeout occurs.
+ *
+ * @param response scanf-like format string of response to expect
+ * @param ... all scanf-like arguments to extract from response
+ * @return true only if response is successfully matched
+ */
+ bool recv(const char *response, ...) MBED_SCANF_METHOD(1, 2);
+
+ bool vrecv(const char *response, va_list args);
+
+ /**
+ * Write a single byte to the underlying stream
+ *
+ * @param c The byte to write
+ * @return The byte that was written or -1 during a timeout
+ */
+ int putc(char c);
+
+ /**
+ * Get a single byte from the underlying stream
+ *
+ * @return The byte that was read or -1 during a timeout
+ */
+ int getc();
+
+ /**
+ * Write an array of bytes to the underlying stream
+ *
+ * @param data the array of bytes to write
+ * @param size number of bytes to write
+ * @return number of bytes written or -1 on failure
+ */
+ int write(const char *data, int size);
+
+ /**
+ * Read an array of bytes from the underlying stream
+ *
+ * @param data the destination for the read bytes
+ * @param size number of bytes to read
+ * @return number of bytes read or -1 on failure
+ */
+ int read(char *data, int size);
+
+ /**
+ * Direct printf to underlying stream
+ * @see printf
+ *
+ * @param format format string to pass to printf
+ * @param ... arguments to printf
+ * @return number of bytes written or -1 on failure
+ */
+ int printf(const char *format, ...) MBED_PRINTF_METHOD(1, 2);
+
+ int vprintf(const char *format, va_list args);
+
+ /**
+ * Direct scanf on underlying stream
+ * @see scanf
+ *
+ * @param format format string to pass to scanf
+ * @param ... arguments to scanf
+ * @return number of bytes read or -1 on failure
+ */
+ int scanf(const char *format, ...) MBED_SCANF_METHOD(1, 2);
+
+ int vscanf(const char *format, va_list args);
+
+ /**
+ * Attach a callback for out-of-band data
+ *
+ * @param prefix string on when to initiate callback
+ * @param func callback to call when string is read
+ * @note out-of-band data is only processed during a scanf call
+ */
+ void oob(const char *prefix, mbed::Callback<void()> func);
+
+ /**
+ * Flushes the underlying stream
+ */
+ void flush();
+
+ /**
+ * Abort current recv
+ *
+ * Can be called from oob handler to interrupt the current
+ * recv operation.
+ */
+ void abort();
+
+ /**
+ * Process out-of-band data
+ *
+ * Process out-of-band data in the receive buffer. This function
+ * returns immediately if there is no data to process.
+ *
+ * @return true if oob data processed, false otherwise
+ */
+ bool process_oob(void);
+};
+
+/**@}*/
+
+/**@}*/
+
+} //namespace mbed
+
+#endif //MBED_ATCMDPARSER_H
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/CThunk.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/CThunk.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,251 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_CThunk CThunk class
+ * @{
+ */
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ *
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ */
+
+#ifndef __CTHUNK_H__
+#define __CTHUNK_H__
+
+#define CTHUNK_ADDRESS 1
+#define CTHUNK_VARIABLES volatile uint32_t code[2]
+
+#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7) || defined(__CORTEX_A9) \
+ || defined(__CORTEX_M33))
+/**
+* CTHUNK disassembly for Cortex-M3/M4/M7/A9 (thumb2):
+* * adr r0, #4
+* * ldm r0, {r0, r1, r2, pc}
+*
+* This instruction loads the arguments for the static thunking function to r0-r2, and
+* branches to that function by loading its address into PC.
+*
+* This is safe for both regular calling and interrupt calling, since it only touches scratch registers
+* which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
+*/
+#define CTHUNK_ASSIGMENT do { \
+ m_thunk.code[0] = 0xE890A001; \
+ m_thunk.code[1] = 0x00008007; \
+ } while (0)
+
+#elif (defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0) || defined(__CORTEX_M23))
+/*
+* CTHUNK disassembly for Cortex M0/M0+ (thumb):
+* * adr r0, #4
+* * ldm r0, {r0, r1, r2, r3}
+* * bx r3
+*/
+#define CTHUNK_ASSIGMENT do { \
+ m_thunk.code[0] = 0xC80FA001; \
+ m_thunk.code[1] = 0x00004718; \
+ } while (0)
+
+#else
+#error "Target is not currently suported."
+#endif
+
+/* IRQ/Exception compatible thunk entry function */
+typedef void (*CThunkEntry)(void);
+
+/**
+ * Class for created a pointer with data bound to it
+ *
+ * @note Synchronization level: Not protected
+ */
+template<class T>
+class CThunk {
+public:
+ typedef void (T::*CCallbackSimple)(void);
+ typedef void (T::*CCallback)(void *context);
+
+ inline CThunk(T *instance)
+ {
+ init(instance, NULL, NULL);
+ }
+
+ inline CThunk(T *instance, CCallback callback)
+ {
+ init(instance, callback, NULL);
+ }
+
+ ~CThunk()
+ {
+
+ }
+
+ inline CThunk(T *instance, CCallbackSimple callback)
+ {
+ init(instance, (CCallback)callback, NULL);
+ }
+
+ inline CThunk(T &instance, CCallback callback)
+ {
+ init(instance, callback, NULL);
+ }
+
+ inline CThunk(T &instance, CCallbackSimple callback)
+ {
+ init(instance, (CCallback)callback, NULL);
+ }
+
+ inline CThunk(T &instance, CCallback callback, void *context)
+ {
+ init(instance, callback, context);
+ }
+
+ inline void callback(CCallback callback)
+ {
+ m_callback = callback;
+ }
+
+ inline void callback(CCallbackSimple callback)
+ {
+ m_callback = (CCallback)callback;
+ }
+
+ inline void context(void *context)
+ {
+ m_thunk.context = (uint32_t)context;
+ }
+
+ inline void context(uint32_t context)
+ {
+ m_thunk.context = context;
+ }
+
+ inline uint32_t entry(void)
+ {
+ return (((uint32_t)&m_thunk) | CTHUNK_ADDRESS);
+ }
+
+ /* get thunk entry point for connecting rhunk to an IRQ table */
+ inline operator CThunkEntry(void)
+ {
+ return (CThunkEntry)entry();
+ }
+
+ /* get thunk entry point for connecting rhunk to an IRQ table */
+ inline operator uint32_t(void)
+ {
+ return entry();
+ }
+
+ /* simple test function */
+ inline void call(void)
+ {
+ (((CThunkEntry)(entry()))());
+ }
+
+private:
+ T *m_instance;
+ volatile CCallback m_callback;
+
+// TODO: this needs proper fix, to refactor toolchain header file and all its use
+// PACKED there is not defined properly for IAR
+#if defined (__ICCARM__)
+ typedef __packed struct {
+ CTHUNK_VARIABLES;
+ volatile uint32_t instance;
+ volatile uint32_t context;
+ volatile uint32_t callback;
+ volatile uint32_t trampoline;
+ } CThunkTrampoline;
+#else
+ typedef struct {
+ CTHUNK_VARIABLES;
+ volatile uint32_t instance;
+ volatile uint32_t context;
+ volatile uint32_t callback;
+ volatile uint32_t trampoline;
+ } __attribute__((__packed__)) CThunkTrampoline;
+#endif
+
+ static void trampoline(T *instance, void *context, CCallback *callback)
+ {
+ if (instance && *callback) {
+ (static_cast<T *>(instance)->**callback)(context);
+ }
+ }
+
+ volatile CThunkTrampoline m_thunk;
+
+ inline void init(T *instance, CCallback callback, void *context)
+ {
+ /* remember callback - need to add this level of redirection
+ as pointer size for member functions differs between platforms */
+ m_callback = callback;
+
+ /* populate thunking trampoline */
+ CTHUNK_ASSIGMENT;
+ m_thunk.context = (uint32_t)context;
+ m_thunk.instance = (uint32_t)instance;
+ m_thunk.callback = (uint32_t)&m_callback;
+ m_thunk.trampoline = (uint32_t)&trampoline;
+
+#if defined(__CORTEX_A9)
+ /* Data cache clean */
+ /* Cache control */
+ {
+ uint32_t start_addr = (uint32_t)&m_thunk & 0xFFFFFFE0;
+ uint32_t end_addr = (uint32_t)&m_thunk + sizeof(m_thunk);
+ uint32_t addr;
+
+ /* Data cache clean and invalid */
+ for (addr = start_addr; addr < end_addr; addr += 0x20) {
+ L1C_CleanInvalidateDCacheMVA((void *)addr);
+ }
+ /* Instruction cache invalid */
+ L1C_InvalidateICacheAll();
+ MMU_InvalidateTLB();
+ L1C_InvalidateBTAC();
+ }
+#endif
+#if defined(__CORTEX_M7)
+ /* Data cache clean and invalid */
+ SCB_CleanInvalidateDCache();
+
+ /* Instruction cache invalid */
+ SCB_InvalidateICache();
+#endif
+ __ISB();
+ __DSB();
+ }
+};
+
+/**@}*/
+
+/**@}*/
+
+#endif/*__CTHUNK_H__*/
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/CallChain.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/CallChain.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,135 @@
+
+// Suppress deprecation warnings since this whole
+// class is deprecated already
+#include "mbed_toolchain.h"
+#undef MBED_DEPRECATED_SINCE
+#define MBED_DEPRECATED_SINCE(...)
+
+#include "platform/CallChain.h"
+#include "cmsis.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+class CallChainLink {
+public:
+ CallChainLink(): cb(), next(NULL)
+ {
+ // No work to do
+ }
+
+ CallChainLink(Callback<void()> &callback): cb(callback), next(NULL)
+ {
+ // No work to do
+ }
+ Callback<void()> cb;
+ CallChainLink *next;
+};
+
+CallChain::CallChain(int size) : _chain(NULL)
+{
+ // No work to do
+}
+
+CallChain::~CallChain()
+{
+ clear();
+}
+
+pFunctionPointer_t CallChain::add(Callback<void()> func)
+{
+ CallChainLink *new_link = new CallChainLink(func);
+ if (NULL == _chain) {
+ _chain = new_link;
+ return &new_link->cb;
+ }
+
+ CallChainLink *link = _chain;
+ while (true) {
+ if (NULL == link->next) {
+ link->next = new_link;
+ return &new_link->cb;
+ }
+ link = link->next;
+ }
+}
+
+pFunctionPointer_t CallChain::add_front(Callback<void()> func)
+{
+ CallChainLink *link = new CallChainLink(func);
+ link->next = _chain;
+ _chain = link;
+ return &link->cb;
+}
+
+int CallChain::size() const
+{
+ CallChainLink *link = _chain;
+ int elements = 0;
+ while (link != NULL) {
+ elements++;
+ link = link->next;
+ }
+ return elements;
+}
+
+pFunctionPointer_t CallChain::get(int idx) const
+{
+ CallChainLink *link = _chain;
+ for (int i = 0; i < idx; i++) {
+ if (NULL == link) {
+ break;
+ }
+ link = link->next;
+ }
+ return &link->cb;
+}
+
+int CallChain::find(pFunctionPointer_t f) const
+{
+ CallChainLink *link = _chain;
+ int i = 0;
+ while (link != NULL) {
+ if (f == &link->cb) {
+ return i;
+ }
+ i++;
+ link = link->next;
+ }
+ return -1;
+}
+
+void CallChain::clear()
+{
+ CallChainLink *link = _chain;
+ _chain = NULL;
+ while (link != NULL) {
+ CallChainLink *temp = link->next;
+ delete link;
+ link = temp;
+ }
+}
+
+bool CallChain::remove(pFunctionPointer_t f)
+{
+ CallChainLink *link = _chain;
+ while (link != NULL) {
+ if (f == &link->cb) {
+ delete link;
+ return true;
+ }
+ link = link->next;
+ }
+ return false;
+}
+
+void CallChain::call()
+{
+ CallChainLink *link = _chain;
+ while (link != NULL) {
+ link->cb.call();
+ link = link->next;
+ }
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/CallChain.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/CallChain.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,264 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/NonCopyable.h"
+#include <string.h>
+
+namespace mbed {
+
+
+typedef Callback<void()> *pFunctionPointer_t;
+class CallChainLink;
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_CallChain CallChain class
+ * @{
+ */
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * @deprecated Do not use this class. This class is not part of the public API of mbed-os and is being removed in the future.
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ * printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ * printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ * void f(void) {
+ * printf("A::f (class member).\n");
+ * }
+ * };
+ *
+ * int main() {
+ * Test test;
+ *
+ * chain.add(second);
+ * chain.add_front(first);
+ * chain.add(&test, &Test::f);
+ * chain.call();
+ * }
+ * @endcode
+ */
+class CallChain : private NonCopyable<CallChain> {
+public:
+ /** Create an empty chain
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @param size (optional) Initial size of the chain
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ CallChain(int size = 4);
+
+ /** Create an empty chain
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ virtual ~CallChain();
+
+ /** Add a function at the end of the chain
+ *
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @param func A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ pFunctionPointer_t add(Callback<void()> func);
+
+ /** Add a function at the end of the chain
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'obj' and 'method'
+ *
+ * @deprecated
+ * The add function does not support cv-qualifiers. Replaced by
+ * add(callback(obj, method)).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The add function does not support cv-qualifiers. Replaced by "
+ "add(callback(obj, method)).")
+ pFunctionPointer_t add(T *obj, M method)
+ {
+ return add(callback(obj, method));
+ }
+
+ /** Add a function at the beginning of the chain
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ *
+ * @param func A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ pFunctionPointer_t add_front(Callback<void()> func);
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ *
+ * @deprecated
+ * The add_front function does not support cv-qualifiers. Replaced by
+ * add_front(callback(obj, method)).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The add_front function does not support cv-qualifiers. Replaced by "
+ "add_front(callback(obj, method)).")
+ pFunctionPointer_t add_front(T *obj, M method)
+ {
+ return add_front(callback(obj, method));
+ }
+
+ /** Get the number of functions in the chain
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ int size() const;
+
+ /** Get a function object from the chain
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @param i function object index
+ *
+ * @returns
+ * The function object at position 'i' in the chain
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ pFunctionPointer_t get(int i) const;
+
+ /** Look for a function object in the call chain
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @param f the function object to search
+ *
+ * @returns
+ * The index of the function object if found, -1 otherwise.
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ int find(pFunctionPointer_t f) const;
+
+ /** Clear the call chain (remove all functions in the chain).
+ * @deprecated Do not use this function. This class is not part of the public API of mbed-os and is being removed in the future.
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ void clear();
+
+ /** Remove a function object from the chain
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ * @arg f the function object to remove
+ *
+ * @returns
+ * true if the function object was found and removed, false otherwise.
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ bool remove(pFunctionPointer_t f);
+
+ /** Call all the functions in the chain in sequence
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ void call();
+
+ /**
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ void operator()(void)
+ {
+ call();
+ }
+
+ /**
+ * @deprecated
+ * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+ *
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
+ "public API of mbed-os and is being removed in the future.")
+ pFunctionPointer_t operator [](int i) const
+ {
+ return get(i);
+ }
+
+private:
+ CallChainLink *_chain;
+};
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/Callback.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/Callback.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,4938 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLBACK_H
+#define MBED_CALLBACK_H
+
+#include <string.h>
+#include <stdint.h>
+#include <new>
+#include "platform/mbed_assert.h"
+#include "platform/mbed_toolchain.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_Callback Callback class
+ * @{
+ */
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ */
+template <typename F>
+class Callback;
+
+// Internal sfinae declarations
+//
+// These are used to eliminate overloads based on type attributes
+// 1. Does a function object have a call operator
+// 2. Does a function object fit in the available storage
+//
+// These eliminations are handled cleanly by the compiler and avoid
+// massive and misleading error messages when confronted with an
+// invalid type (or worse, runtime failures)
+namespace detail {
+struct nil {};
+
+template <bool B, typename R = nil>
+struct enable_if {
+ typedef R type;
+};
+
+template <typename R>
+struct enable_if<false, R> {};
+
+template <typename M, M>
+struct is_type {
+ static const bool value = true;
+};
+}
+
+#define MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M) \
+ typename detail::enable_if< \
+ detail::is_type<M, &F::operator()>::value && \
+ sizeof(F) <= sizeof(uintptr_t) \
+ >::type = detail::nil()
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ */
+template <typename R>
+class Callback<R()> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R(*func)() = 0)
+ {
+ if (!func) {
+ memset(this, 0, sizeof(Callback));
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R()> &func)
+ {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R(T::*method)())
+ {
+ generate(method_context<T, R(T::*)()>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R(T::*method)() const)
+ {
+ generate(method_context<const T, R(T::*)() const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R(T::*method)() volatile)
+ {
+ generate(method_context<volatile T, R(T::*)() volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R(T::*method)() const volatile)
+ {
+ generate(method_context<const volatile T, R(T::*)() const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(T *), U *arg)
+ {
+ generate(function_context<R(*)(T *), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const T *), const U *arg)
+ {
+ generate(function_context<R(*)(const T *), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(volatile T *), volatile U *arg)
+ {
+ generate(function_context<R(*)(volatile T *), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const volatile T *), const volatile U *arg)
+ {
+ generate(function_context<R(*)(const volatile T *), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)()))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() const))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() const volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R(*func)(T *))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R(*func)(const T *))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R(*func)(volatile T *))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R(*func)(const volatile T *))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback()
+ {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)())
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R()> &func)
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R(T::*method)())
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R(T::*method)() const)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R(T::*method)() volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R(T::*method)() const volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(T *), U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const T *), const U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(volatile T *), volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const volatile T *), const volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)()))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() const))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() const volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R(*func)(T *))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R(*func)(const T *))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R(*func)(volatile T *))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R(*func)(const volatile T *))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that)
+ {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call() const
+ {
+ MBED_ASSERT(_ops);
+ return _ops->call(this);
+ }
+
+ /** Call the attached function
+ */
+ R operator()() const
+ {
+ return call();
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const
+ {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r)
+ {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r)
+ {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func)
+ {
+ return static_cast<Callback *>(func)->call();
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to guarantee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)();
+ void (*_boundfunc)(_class *);
+ void (_class::*_methodfunc)();
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R(*call)(const void *);
+ void (*move)(void *, const void *);
+ void (*dtor)(void *);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f)
+ {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ memset(this, 0, sizeof(Callback));
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p)
+ {
+ return (*(F *)p)();
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p)
+ {
+ new (d) F(*(F *)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p)
+ {
+ ((F *)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()() const
+ {
+ return (obj->*method)();
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()() const
+ {
+ return func(arg);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ */
+template <typename R, typename A0>
+class Callback<R(A0)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R(*func)(A0) = 0)
+ {
+ if (!func) {
+ memset(this, 0, sizeof(Callback));
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0)> &func)
+ {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R(T::*method)(A0))
+ {
+ generate(method_context<T, R(T::*)(A0)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R(T::*method)(A0) const)
+ {
+ generate(method_context<const T, R(T::*)(A0) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R(T::*method)(A0) volatile)
+ {
+ generate(method_context<volatile T, R(T::*)(A0) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R(T::*method)(A0) const volatile)
+ {
+ generate(method_context<const volatile T, R(T::*)(A0) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(T *, A0), U *arg)
+ {
+ generate(function_context<R(*)(T *, A0), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const T *, A0), const U *arg)
+ {
+ generate(function_context<R(*)(const T *, A0), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(volatile T *, A0), volatile U *arg)
+ {
+ generate(function_context<R(*)(volatile T *, A0), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const volatile T *, A0), const volatile U *arg)
+ {
+ generate(function_context<R(*)(const volatile T *, A0), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0)))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) const))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) const volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R(*func)(T *, A0))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R(*func)(const T *, A0))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R(*func)(volatile T *, A0))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R(*func)(const volatile T *, A0))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback()
+ {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(A0))
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0)> &func)
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R(T::*method)(A0))
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R(T::*method)(A0) const)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R(T::*method)(A0) volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R(T::*method)(A0) const volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(T *, A0), U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const T *, A0), const U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(volatile T *, A0), volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const volatile T *, A0), const volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0)))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) const))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) const volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R(*func)(T *, A0))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R(*func)(const T *, A0))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R(*func)(volatile T *, A0))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R(*func)(const volatile T *, A0))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that)
+ {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0) const
+ {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0) const
+ {
+ return call(a0);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const
+ {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r)
+ {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r)
+ {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0)
+ {
+ return static_cast<Callback *>(func)->call(a0);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to guarantee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0);
+ void (*_boundfunc)(_class *, A0);
+ void (_class::*_methodfunc)(A0);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R(*call)(const void *, A0);
+ void (*move)(void *, const void *);
+ void (*dtor)(void *);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f)
+ {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ memset(this, 0, sizeof(Callback));
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0)
+ {
+ return (*(F *)p)(a0);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p)
+ {
+ new (d) F(*(F *)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p)
+ {
+ ((F *)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0) const
+ {
+ return (obj->*method)(a0);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0) const
+ {
+ return func(arg, a0);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ */
+template <typename R, typename A0, typename A1>
+class Callback<R(A0, A1)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R(*func)(A0, A1) = 0)
+ {
+ if (!func) {
+ memset(this, 0, sizeof(Callback));
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0, A1)> &func)
+ {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R(T::*method)(A0, A1))
+ {
+ generate(method_context<T, R(T::*)(A0, A1)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R(T::*method)(A0, A1) const)
+ {
+ generate(method_context<const T, R(T::*)(A0, A1) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R(T::*method)(A0, A1) volatile)
+ {
+ generate(method_context<volatile T, R(T::*)(A0, A1) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R(T::*method)(A0, A1) const volatile)
+ {
+ generate(method_context<const volatile T, R(T::*)(A0, A1) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(T *, A0, A1), U *arg)
+ {
+ generate(function_context<R(*)(T *, A0, A1), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const T *, A0, A1), const U *arg)
+ {
+ generate(function_context<R(*)(const T *, A0, A1), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(volatile T *, A0, A1), volatile U *arg)
+ {
+ generate(function_context<R(*)(volatile T *, A0, A1), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const volatile T *, A0, A1), const volatile U *arg)
+ {
+ generate(function_context<R(*)(const volatile T *, A0, A1), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1)))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) const))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) const volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R(*func)(T *, A0, A1))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R(*func)(const T *, A0, A1))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R(*func)(volatile T *, A0, A1))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback()
+ {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(A0, A1))
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0, A1)> &func)
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R(T::*method)(A0, A1))
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R(T::*method)(A0, A1) const)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R(T::*method)(A0, A1) volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R(T::*method)(A0, A1) const volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(T *, A0, A1), U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const T *, A0, A1), const U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(volatile T *, A0, A1), volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const volatile T *, A0, A1), const volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1)))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) const))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) const volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R(*func)(T *, A0, A1))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R(*func)(const T *, A0, A1))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R(*func)(volatile T *, A0, A1))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R(*func)(const volatile T *, A0, A1))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that)
+ {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0, A1 a1) const
+ {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0, a1);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0, A1 a1) const
+ {
+ return call(a0, a1);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const
+ {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r)
+ {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r)
+ {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @param a1 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0, A1 a1)
+ {
+ return static_cast<Callback *>(func)->call(a0, a1);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to guarantee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0, A1);
+ void (*_boundfunc)(_class *, A0, A1);
+ void (_class::*_methodfunc)(A0, A1);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R(*call)(const void *, A0, A1);
+ void (*move)(void *, const void *);
+ void (*dtor)(void *);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f)
+ {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ memset(this, 0, sizeof(Callback));
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0, A1 a1)
+ {
+ return (*(F *)p)(a0, a1);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p)
+ {
+ new (d) F(*(F *)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p)
+ {
+ ((F *)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0, A1 a1) const
+ {
+ return (obj->*method)(a0, a1);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0, A1 a1) const
+ {
+ return func(arg, a0, a1);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ */
+template <typename R, typename A0, typename A1, typename A2>
+class Callback<R(A0, A1, A2)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R(*func)(A0, A1, A2) = 0)
+ {
+ if (!func) {
+ memset(this, 0, sizeof(Callback));
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0, A1, A2)> &func)
+ {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R(T::*method)(A0, A1, A2))
+ {
+ generate(method_context<T, R(T::*)(A0, A1, A2)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R(T::*method)(A0, A1, A2) const)
+ {
+ generate(method_context<const T, R(T::*)(A0, A1, A2) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R(T::*method)(A0, A1, A2) volatile)
+ {
+ generate(method_context<volatile T, R(T::*)(A0, A1, A2) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R(T::*method)(A0, A1, A2) const volatile)
+ {
+ generate(method_context<const volatile T, R(T::*)(A0, A1, A2) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(T *, A0, A1, A2), U *arg)
+ {
+ generate(function_context<R(*)(T *, A0, A1, A2), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const T *, A0, A1, A2), const U *arg)
+ {
+ generate(function_context<R(*)(const T *, A0, A1, A2), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(volatile T *, A0, A1, A2), volatile U *arg)
+ {
+ generate(function_context<R(*)(volatile T *, A0, A1, A2), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const volatile T *, A0, A1, A2), const volatile U *arg)
+ {
+ generate(function_context<R(*)(const volatile T *, A0, A1, A2), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2)))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) const))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) const volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R(*func)(T *, A0, A1, A2))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R(*func)(const T *, A0, A1, A2))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback()
+ {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(A0, A1, A2))
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0, A1, A2)> &func)
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R(T::*method)(A0, A1, A2))
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R(T::*method)(A0, A1, A2) const)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R(T::*method)(A0, A1, A2) volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R(T::*method)(A0, A1, A2) const volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(T *, A0, A1, A2), U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const T *, A0, A1, A2), const U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(volatile T *, A0, A1, A2), volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const volatile T *, A0, A1, A2), const volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2)))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) const))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) const volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R(*func)(T *, A0, A1, A2))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R(*func)(const T *, A0, A1, A2))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R(*func)(volatile T *, A0, A1, A2))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that)
+ {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0, A1 a1, A2 a2) const
+ {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0, a1, a2);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0, A1 a1, A2 a2) const
+ {
+ return call(a0, a1, a2);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const
+ {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r)
+ {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r)
+ {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @param a1 An argument to be called with function func
+ * @param a2 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0, A1 a1, A2 a2)
+ {
+ return static_cast<Callback *>(func)->call(a0, a1, a2);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to guarantee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0, A1, A2);
+ void (*_boundfunc)(_class *, A0, A1, A2);
+ void (_class::*_methodfunc)(A0, A1, A2);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R(*call)(const void *, A0, A1, A2);
+ void (*move)(void *, const void *);
+ void (*dtor)(void *);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f)
+ {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ memset(this, 0, sizeof(Callback));
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0, A1 a1, A2 a2)
+ {
+ return (*(F *)p)(a0, a1, a2);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p)
+ {
+ new (d) F(*(F *)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p)
+ {
+ ((F *)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2) const
+ {
+ return (obj->*method)(a0, a1, a2);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2) const
+ {
+ return func(arg, a0, a1, a2);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+class Callback<R(A0, A1, A2, A3)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R(*func)(A0, A1, A2, A3) = 0)
+ {
+ if (!func) {
+ memset(this, 0, sizeof(Callback));
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0, A1, A2, A3)> &func)
+ {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R(T::*method)(A0, A1, A2, A3))
+ {
+ generate(method_context<T, R(T::*)(A0, A1, A2, A3)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R(T::*method)(A0, A1, A2, A3) const)
+ {
+ generate(method_context<const T, R(T::*)(A0, A1, A2, A3) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3) volatile)
+ {
+ generate(method_context<volatile T, R(T::*)(A0, A1, A2, A3) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3) const volatile)
+ {
+ generate(method_context<const volatile T, R(T::*)(A0, A1, A2, A3) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(T *, A0, A1, A2, A3), U *arg)
+ {
+ generate(function_context<R(*)(T *, A0, A1, A2, A3), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const T *, A0, A1, A2, A3), const U *arg)
+ {
+ generate(function_context<R(*)(const T *, A0, A1, A2, A3), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(volatile T *, A0, A1, A2, A3), volatile U *arg)
+ {
+ generate(function_context<R(*)(volatile T *, A0, A1, A2, A3), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const volatile T *, A0, A1, A2, A3), const volatile U *arg)
+ {
+ generate(function_context<R(*)(const volatile T *, A0, A1, A2, A3), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3)))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) const))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) const volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R(*func)(T *, A0, A1, A2, A3))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R(*func)(const T *, A0, A1, A2, A3))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback()
+ {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(A0, A1, A2, A3))
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0, A1, A2, A3)> &func)
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R(T::*method)(A0, A1, A2, A3))
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R(T::*method)(A0, A1, A2, A3) const)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R(T::*method)(A0, A1, A2, A3) volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R(T::*method)(A0, A1, A2, A3) const volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(T *, A0, A1, A2, A3), U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const T *, A0, A1, A2, A3), const U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(volatile T *, A0, A1, A2, A3), volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const volatile T *, A0, A1, A2, A3), const volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3)))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) const))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) const volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R(*func)(T *, A0, A1, A2, A3))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R(*func)(const T *, A0, A1, A2, A3))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that)
+ {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0, A1 a1, A2 a2, A3 a3) const
+ {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0, a1, a2, a3);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const
+ {
+ return call(a0, a1, a2, a3);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const
+ {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r)
+ {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r)
+ {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @param a1 An argument to be called with function func
+ * @param a2 An argument to be called with function func
+ * @param a3 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3)
+ {
+ return static_cast<Callback *>(func)->call(a0, a1, a2, a3);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to guarantee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0, A1, A2, A3);
+ void (*_boundfunc)(_class *, A0, A1, A2, A3);
+ void (_class::*_methodfunc)(A0, A1, A2, A3);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R(*call)(const void *, A0, A1, A2, A3);
+ void (*move)(void *, const void *);
+ void (*dtor)(void *);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f)
+ {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ memset(this, 0, sizeof(Callback));
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0, A1 a1, A2 a2, A3 a3)
+ {
+ return (*(F *)p)(a0, a1, a2, a3);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p)
+ {
+ new (d) F(*(F *)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p)
+ {
+ ((F *)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const
+ {
+ return (obj->*method)(a0, a1, a2, a3);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const
+ {
+ return func(arg, a0, a1, a2, a3);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+class Callback<R(A0, A1, A2, A3, A4)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R(*func)(A0, A1, A2, A3, A4) = 0)
+ {
+ if (!func) {
+ memset(this, 0, sizeof(Callback));
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0, A1, A2, A3, A4)> &func)
+ {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R(T::*method)(A0, A1, A2, A3, A4))
+ {
+ generate(method_context<T, R(T::*)(A0, A1, A2, A3, A4)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R(T::*method)(A0, A1, A2, A3, A4) const)
+ {
+ generate(method_context<const T, R(T::*)(A0, A1, A2, A3, A4) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) volatile)
+ {
+ generate(method_context<volatile T, R(T::*)(A0, A1, A2, A3, A4) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) const volatile)
+ {
+ generate(method_context<const volatile T, R(T::*)(A0, A1, A2, A3, A4) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(T *, A0, A1, A2, A3, A4), U *arg)
+ {
+ generate(function_context<R(*)(T *, A0, A1, A2, A3, A4), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const T *, A0, A1, A2, A3, A4), const U *arg)
+ {
+ generate(function_context<R(*)(const T *, A0, A1, A2, A3, A4), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(volatile T *, A0, A1, A2, A3, A4), volatile U *arg)
+ {
+ generate(function_context<R(*)(volatile T *, A0, A1, A2, A3, A4), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R(*func)(const volatile T *, A0, A1, A2, A3, A4), const volatile U *arg)
+ {
+ generate(function_context<R(*)(const volatile T *, A0, A1, A2, A3, A4), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4)))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) const))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) const volatile))
+ {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R(*func)(T *, A0, A1, A2, A3, A4))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R(*func)(const T *, A0, A1, A2, A3, A4))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3, A4))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3, A4))
+ {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback()
+ {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(A0, A1, A2, A3, A4))
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0, A1, A2, A3, A4)> &func)
+ {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R(T::*method)(A0, A1, A2, A3, A4))
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R(T::*method)(A0, A1, A2, A3, A4) const)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) const volatile)
+ {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(T *, A0, A1, A2, A3, A4), U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const T *, A0, A1, A2, A3, A4), const U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(volatile T *, A0, A1, A2, A3, A4), volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R(*func)(const volatile T *, A0, A1, A2, A3, A4), const volatile U *arg)
+ {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4)))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) const))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) const volatile))
+ {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R(*func)(T *, A0, A1, A2, A3, A4))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R(*func)(const T *, A0, A1, A2, A3, A4))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3, A4))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3, A4))
+ {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that)
+ {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const
+ {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0, a1, a2, a3, a4);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const
+ {
+ return call(a0, a1, a2, a3, a4);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const
+ {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r)
+ {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r)
+ {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @param a1 An argument to be called with function func
+ * @param a2 An argument to be called with function func
+ * @param a3 An argument to be called with function func
+ * @param a4 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4)
+ {
+ return static_cast<Callback *>(func)->call(a0, a1, a2, a3, a4);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to guarantee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0, A1, A2, A3, A4);
+ void (*_boundfunc)(_class *, A0, A1, A2, A3, A4);
+ void (_class::*_methodfunc)(A0, A1, A2, A3, A4);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R(*call)(const void *, A0, A1, A2, A3, A4);
+ void (*move)(void *, const void *);
+ void (*dtor)(void *);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f)
+ {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ memset(this, 0, sizeof(Callback));
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4)
+ {
+ return (*(F *)p)(a0, a1, a2, a3, a4);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p)
+ {
+ new (d) F(*(F *)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p)
+ {
+ ((F *)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const
+ {
+ return (obj->*method)(a0, a1, a2, a3, a4);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const
+ {
+ return func(arg, a0, a1, a2, a3, a4);
+ }
+ };
+};
+
+// Internally used event type
+typedef Callback<void(int)> event_callback_t;
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R>
+Callback<R()> callback(R(*func)() = 0)
+{
+ return Callback<R()>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R>
+Callback<R()> callback(const Callback<R()> &func)
+{
+ return Callback<R()>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(U *obj, R(T::*method)())
+{
+ return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(const U *obj, R(T::*method)() const)
+{
+ return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(volatile U *obj, R(T::*method)() volatile)
+{
+ return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(const volatile U *obj, R(T::*method)() const volatile)
+{
+ return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R(*func)(T *), U *arg)
+{
+ return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R(*func)(const T *), const U *arg)
+{
+ return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R(*func)(volatile T *), volatile U *arg)
+{
+ return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R(*func)(const volatile T *), const volatile U *arg)
+{
+ return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(U *obj, R(*func)(T *))
+{
+ return Callback<R()>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(const U *obj, R(*func)(const T *))
+{
+ return Callback<R()>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(volatile U *obj, R(*func)(volatile T *))
+{
+ return Callback<R()>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(const volatile U *obj, R(*func)(const volatile T *))
+{
+ return Callback<R()>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0>
+Callback<R(A0)> callback(R(*func)(A0) = 0)
+{
+ return Callback<R(A0)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0>
+Callback<R(A0)> callback(const Callback<R(A0)> &func)
+{
+ return Callback<R(A0)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(U *obj, R(T::*method)(A0))
+{
+ return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(const U *obj, R(T::*method)(A0) const)
+{
+ return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(volatile U *obj, R(T::*method)(A0) volatile)
+{
+ return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(const volatile U *obj, R(T::*method)(A0) const volatile)
+{
+ return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R(*func)(T *, A0), U *arg)
+{
+ return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R(*func)(const T *, A0), const U *arg)
+{
+ return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R(*func)(volatile T *, A0), volatile U *arg)
+{
+ return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R(*func)(const volatile T *, A0), const volatile U *arg)
+{
+ return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(U *obj, R(*func)(T *, A0))
+{
+ return Callback<R(A0)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(const U *obj, R(*func)(const T *, A0))
+{
+ return Callback<R(A0)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(volatile U *obj, R(*func)(volatile T *, A0))
+{
+ return Callback<R(A0)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(const volatile U *obj, R(*func)(const volatile T *, A0))
+{
+ return Callback<R(A0)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R(*func)(A0, A1) = 0)
+{
+ return Callback<R(A0, A1)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(const Callback<R(A0, A1)> &func)
+{
+ return Callback<R(A0, A1)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(U *obj, R(T::*method)(A0, A1))
+{
+ return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(const U *obj, R(T::*method)(A0, A1) const)
+{
+ return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(volatile U *obj, R(T::*method)(A0, A1) volatile)
+{
+ return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(const volatile U *obj, R(T::*method)(A0, A1) const volatile)
+{
+ return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R(*func)(T *, A0, A1), U *arg)
+{
+ return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R(*func)(const T *, A0, A1), const U *arg)
+{
+ return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R(*func)(volatile T *, A0, A1), volatile U *arg)
+{
+ return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R(*func)(const volatile T *, A0, A1), const volatile U *arg)
+{
+ return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(U *obj, R(*func)(T *, A0, A1))
+{
+ return Callback<R(A0, A1)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(const U *obj, R(*func)(const T *, A0, A1))
+{
+ return Callback<R(A0, A1)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(volatile U *obj, R(*func)(volatile T *, A0, A1))
+{
+ return Callback<R(A0, A1)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1))
+{
+ return Callback<R(A0, A1)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R(*func)(A0, A1, A2) = 0)
+{
+ return Callback<R(A0, A1, A2)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(const Callback<R(A0, A1, A2)> &func)
+{
+ return Callback<R(A0, A1, A2)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(U *obj, R(T::*method)(A0, A1, A2))
+{
+ return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(const U *obj, R(T::*method)(A0, A1, A2) const)
+{
+ return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(volatile U *obj, R(T::*method)(A0, A1, A2) volatile)
+{
+ return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(const volatile U *obj, R(T::*method)(A0, A1, A2) const volatile)
+{
+ return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R(*func)(T *, A0, A1, A2), U *arg)
+{
+ return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R(*func)(const T *, A0, A1, A2), const U *arg)
+{
+ return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R(*func)(volatile T *, A0, A1, A2), volatile U *arg)
+{
+ return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R(*func)(const volatile T *, A0, A1, A2), const volatile U *arg)
+{
+ return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(U *obj, R(*func)(T *, A0, A1, A2))
+{
+ return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(const U *obj, R(*func)(const T *, A0, A1, A2))
+{
+ return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2))
+{
+ return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2))
+{
+ return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R(*func)(A0, A1, A2, A3) = 0)
+{
+ return Callback<R(A0, A1, A2, A3)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(const Callback<R(A0, A1, A2, A3)> &func)
+{
+ return Callback<R(A0, A1, A2, A3)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(U *obj, R(T::*method)(A0, A1, A2, A3))
+{
+ return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(const U *obj, R(T::*method)(A0, A1, A2, A3) const)
+{
+ return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3) volatile)
+{
+ return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3) const volatile)
+{
+ return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R(*func)(T *, A0, A1, A2, A3), U *arg)
+{
+ return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R(*func)(const T *, A0, A1, A2, A3), const U *arg)
+{
+ return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R(*func)(volatile T *, A0, A1, A2, A3), volatile U *arg)
+{
+ return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R(*func)(const volatile T *, A0, A1, A2, A3), const volatile U *arg)
+{
+ return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(U *obj, R(*func)(T *, A0, A1, A2, A3))
+{
+ return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(const U *obj, R(*func)(const T *, A0, A1, A2, A3))
+{
+ return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3))
+{
+ return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3))
+{
+ return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(A0, A1, A2, A3, A4) = 0)
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(const Callback<R(A0, A1, A2, A3, A4)> &func)
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(U *obj, R(T::*method)(A0, A1, A2, A3, A4))
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(const U *obj, R(T::*method)(A0, A1, A2, A3, A4) const)
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) volatile)
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) const volatile)
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(T *, A0, A1, A2, A3, A4), U *arg)
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(const T *, A0, A1, A2, A3, A4), const U *arg)
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(volatile T *, A0, A1, A2, A3, A4), volatile U *arg)
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(const volatile T *, A0, A1, A2, A3, A4), const volatile U *arg)
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(U *obj, R(*func)(T *, A0, A1, A2, A3, A4))
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(const U *obj, R(*func)(const T *, A0, A1, A2, A3, A4))
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3, A4))
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3, A4))
+{
+ return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/CircularBuffer.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/CircularBuffer.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,208 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CIRCULARBUFFER_H
+#define MBED_CIRCULARBUFFER_H
+
+#include "platform/mbed_critical.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+namespace internal {
+/* Detect if CounterType of the Circular buffer is of unsigned type. */
+template<typename T>
+struct is_unsigned {
+ static const bool value = false;
+};
+template<>
+struct is_unsigned<unsigned char> {
+ static const bool value = true;
+};
+template<>
+struct is_unsigned<unsigned short> {
+ static const bool value = true;
+};
+template<>
+struct is_unsigned<unsigned int> {
+ static const bool value = true;
+};
+template<>
+struct is_unsigned<unsigned long> {
+ static const bool value = true;
+};
+template<>
+struct is_unsigned<unsigned long long> {
+ static const bool value = true;
+};
+};
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_CircularBuffer CircularBuffer functions
+ * @{
+ */
+
+/** Templated Circular buffer class
+ *
+ * @note Synchronization level: Interrupt safe
+ * @note CounterType must be unsigned and consistent with BufferSize
+ */
+template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
+class CircularBuffer {
+public:
+ CircularBuffer() : _head(0), _tail(0), _full(false)
+ {
+ MBED_STATIC_ASSERT(
+ internal::is_unsigned<CounterType>::value,
+ "CounterType must be unsigned"
+ );
+
+ MBED_STATIC_ASSERT(
+ (sizeof(CounterType) >= sizeof(uint32_t)) ||
+ (BufferSize < (((uint64_t) 1) << (sizeof(CounterType) * 8))),
+ "Invalid BufferSize for the CounterType"
+ );
+ }
+
+ ~CircularBuffer()
+ {
+ }
+
+ /** Push the transaction to the buffer. This overwrites the buffer if it's
+ * full
+ *
+ * @param data Data to be pushed to the buffer
+ */
+ void push(const T &data)
+ {
+ core_util_critical_section_enter();
+ if (full()) {
+ _tail++;
+ _tail %= BufferSize;
+ }
+ _pool[_head++] = data;
+ _head %= BufferSize;
+ if (_head == _tail) {
+ _full = true;
+ }
+ core_util_critical_section_exit();
+ }
+
+ /** Pop the transaction from the buffer
+ *
+ * @param data Data to be popped from the buffer
+ * @return True if the buffer is not empty and data contains a transaction, false otherwise
+ */
+ bool pop(T &data)
+ {
+ bool data_popped = false;
+ core_util_critical_section_enter();
+ if (!empty()) {
+ data = _pool[_tail++];
+ _tail %= BufferSize;
+ _full = false;
+ data_popped = true;
+ }
+ core_util_critical_section_exit();
+ return data_popped;
+ }
+
+ /** Check if the buffer is empty
+ *
+ * @return True if the buffer is empty, false if not
+ */
+ bool empty() const
+ {
+ core_util_critical_section_enter();
+ bool is_empty = (_head == _tail) && !_full;
+ core_util_critical_section_exit();
+ return is_empty;
+ }
+
+ /** Check if the buffer is full
+ *
+ * @return True if the buffer is full, false if not
+ */
+ bool full() const
+ {
+ core_util_critical_section_enter();
+ bool full = _full;
+ core_util_critical_section_exit();
+ return full;
+ }
+
+ /** Reset the buffer
+ *
+ */
+ void reset()
+ {
+ core_util_critical_section_enter();
+ _head = 0;
+ _tail = 0;
+ _full = false;
+ core_util_critical_section_exit();
+ }
+
+ /** Get the number of elements currently stored in the circular_buffer */
+ CounterType size() const
+ {
+ core_util_critical_section_enter();
+ CounterType elements;
+ if (!_full) {
+ if (_head < _tail) {
+ elements = BufferSize + _head - _tail;
+ } else {
+ elements = _head - _tail;
+ }
+ } else {
+ elements = BufferSize;
+ }
+ core_util_critical_section_exit();
+ return elements;
+ }
+
+ /** Peek into circular buffer without popping
+ *
+ * @param data Data to be peeked from the buffer
+ * @return True if the buffer is not empty and data contains a transaction, false otherwise
+ */
+ bool peek(T &data) const
+ {
+ bool data_updated = false;
+ core_util_critical_section_enter();
+ if (!empty()) {
+ data = _pool[_tail];
+ data_updated = true;
+ }
+ core_util_critical_section_exit();
+ return data_updated;
+ }
+
+private:
+ T _pool[BufferSize];
+ volatile CounterType _head;
+ volatile CounterType _tail;
+ volatile bool _full;
+};
+
+/**@}*/
+
+/**@}*/
+
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/CriticalSectionLock.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/CriticalSectionLock.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,115 @@
+/*
+ * PackageLicenseDeclared: Apache-2.0
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CRITICALSECTIONLOCK_H
+#define MBED_CRITICALSECTIONLOCK_H
+
+#include "platform/mbed_critical.h"
+#include "platform/mbed_toolchain.h"
+
+namespace mbed {
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_CriticalSectionLock CriticalSectionLock functions
+ * @{
+ */
+
+/** RAII object for disabling, then restoring, interrupt state
+ * Usage:
+ * @code
+ *
+ * // RAII style usage
+ * unsigned int atomic_counter_increment(unsigned int &counter) {
+ * CriticalSectionLock lock;
+ * // Code in this block will run with interrupts disabled
+ * // Interrupts will be restored to their previous state automatically
+ * // at the end of function scope
+ * return ++counter;
+ * }
+ *
+ * // free locking usage
+ * unsigned int atomic_counter_decrement(unsigned int &counter) {
+ * CriticalSectionLock::enable();
+ * // Code in this block will run with interrupts disabled
+ * counter--;
+ * CriticalSectionLock::disable(); // need explicitly to disable critical section lock
+ * // interrupts will be restored to their previous state here
+ * return counter;
+ * }
+ *
+ * @endcode
+ */
+class CriticalSectionLock {
+public:
+ CriticalSectionLock()
+ {
+ core_util_critical_section_enter();
+ }
+
+ ~CriticalSectionLock()
+ {
+ core_util_critical_section_exit();
+ }
+
+ /** Mark the start of a critical section
+ * @deprecated This function is inconsistent with RAII and is being removed in the future. Replaced by static function CriticalSectionLock::enable.
+ *
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.8",
+ "This function is inconsistent with RAII and is being removed in the future."
+ "Replaced by static function CriticalSectionLock::enable.")
+ void lock()
+ {
+ core_util_critical_section_enter();
+ }
+
+ /** Mark the end of a critical section
+ * @deprecated This function is inconsistent with RAII and is being removed in the future. Replaced by static function CriticalSectionLock::enable.
+ *
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.8",
+ "This function is inconsistent with RAII and is being removed in the future."
+ "Replaced by static function CriticalSectionLock::disable.")
+ void unlock()
+ {
+ core_util_critical_section_exit();
+ }
+
+ /** Mark the start of a critical section
+ */
+ static void enable()
+ {
+ core_util_critical_section_enter();
+ }
+
+ /** Mark the end of a critical section
+ */
+ static void disable()
+ {
+ core_util_critical_section_exit();
+ }
+};
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/DeepSleepLock.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/DeepSleepLock.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEEPSLEEPLOCK_H
+#define MBED_DEEPSLEEPLOCK_H
+
+#include <limits.h>
+#include "platform/mbed_power_mgmt.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_DeepSleepLock DeepSleepLock functions
+ * @{
+ */
+
+/** RAII object for disabling, then restoring the deep sleep mode
+ * Usage:
+ * @code
+ *
+ * void f() {
+ * // some code here
+ * {
+ * DeepSleepLock lock;
+ * // Code in this block will run with the deep sleep mode locked
+ * }
+ * // deep sleep mode will be restored to their previous state
+ * }
+ * @endcode
+ */
+class DeepSleepLock {
+private:
+ uint16_t _lock_count;
+
+public:
+ DeepSleepLock(): _lock_count(1)
+ {
+ sleep_manager_lock_deep_sleep();
+ }
+
+ ~DeepSleepLock()
+ {
+ if (_lock_count) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ }
+
+ /** Mark the start of a locked deep sleep section
+ */
+ void lock()
+ {
+ uint16_t count = core_util_atomic_incr_u16(&_lock_count, 1);
+ if (1 == count) {
+ sleep_manager_lock_deep_sleep();
+ }
+ if (0 == count) {
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OVERFLOW), "DeepSleepLock overflow (> USHRT_MAX)", count);
+ }
+ }
+
+ /** Mark the end of a locked deep sleep section
+ */
+ void unlock()
+ {
+ uint16_t count = core_util_atomic_decr_u16(&_lock_count, 1);
+ if (count == 0) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ if (count == USHRT_MAX) {
+ core_util_critical_section_exit();
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_UNDERFLOW), "DeepSleepLock underflow (< 0)", count);
+ }
+ }
+};
+
+/**@}*/
+
+/**@}*/
+
+
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/DirHandle.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/DirHandle.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,171 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIRHANDLE_H
+#define MBED_DIRHANDLE_H
+
+#include <stdint.h>
+#include "platform/platform.h"
+#include "platform/FileHandle.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_DirHandle DirHandle functions
+ * @{
+ */
+
+
+/** Represents a directory stream. Objects of this type are returned
+ * by an opendir function. The core functions are read and seek,
+ * but only a subset needs to be provided.
+ *
+ * If a FileSystemLike class defines the opendir method, then the
+ * directories of an object of that type can be accessed by
+ * DIR *d = opendir("/example/directory") (or opendir("/example")
+ * to open the root of the filesystem), and then using readdir(d) etc.
+ *
+ * The root directory is considered to contain all FileHandle and
+ * FileSystem objects, so the DIR* returned by opendir("/") will
+ * reflect this.
+ *
+ * @note to create a directory, @see Dir
+ * @note Synchronization level: Set by subclass
+ */
+class DirHandle : private NonCopyable<DirHandle> {
+public:
+ virtual ~DirHandle() {}
+
+ /** Read the next directory entry
+ *
+ * @param ent The directory entry to fill out
+ * @return 1 on reading a filename, 0 at end of directory, negative error on failure
+ */
+ virtual ssize_t read(struct dirent *ent) = 0;
+
+ /** Close a directory
+ *
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int close() = 0;
+
+ /** Set the current position of the directory
+ *
+ * @param offset Offset of the location to seek to,
+ * must be a value returned from tell
+ */
+ virtual void seek(off_t offset) = 0;
+
+ /** Get the current position of the directory
+ *
+ * @return Position of the directory that can be passed to rewind
+ */
+ virtual off_t tell() = 0;
+
+ /** Rewind the current position to the beginning of the directory
+ */
+ virtual void rewind() = 0;
+
+ /** Get the sizeof the directory
+ *
+ * @return Number of files in the directory
+ */
+ virtual size_t size()
+ {
+ off_t off = tell();
+ size_t size = 0;
+ struct dirent *ent = new struct dirent;
+
+ rewind();
+ while (read(ent) > 0) {
+ size += 1;
+ }
+ seek(off);
+
+ delete ent;
+ return size;
+ }
+
+ /** Closes the directory.
+ *
+ * @returns
+ * 0 on success,
+ * -1 on error.
+ * @deprecated Replaced by `int DirHandle::close()'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::close")
+ virtual int closedir()
+ {
+ return close();
+ };
+
+ /** Return the directory entry at the current position, and
+ * advances the position to the next entry.
+ *
+ * @returns
+ * A pointer to a dirent structure representing the
+ * directory entry at the current position, or NULL on reaching
+ * end of directory or error.
+ * @deprecated Replaced by `ssize_t DirHandle::read(struct dirent *ent)
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::read")
+ virtual struct dirent *readdir()
+ {
+ static struct dirent ent;
+ return (read(&ent) > 0) ? &ent : NULL;
+ }
+
+ /** Resets the position to the beginning of the directory.
+ * @deprecated Replaced by `void DirHandle::rewind()'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::rewind")
+ virtual void rewinddir()
+ {
+ rewind();
+ }
+
+ /** Returns the current position of the DirHandle.
+ *
+ * @returns
+ * the current position,
+ * -1 on error.
+ * @deprecated Replaced by `off_t DirHandle::tell()'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::tell")
+ virtual off_t telldir()
+ {
+ return tell();
+ }
+
+ /** Sets the position of the DirHandle.
+ *
+ * @param location The location to seek to. Must be a value returned by telldir.
+ * @deprecated Replaced by `void DirHandle::seek(off_t offset)'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::seek")
+ virtual void seekdir(off_t location)
+ {
+ seek(location);
+ }
+};
+
+/**@}*/
+
+/**@}*/
+} // namespace mbed
+
+#endif /* MBED_DIRHANDLE_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FileBase.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FileBase.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/FileBase.h"
+#include "platform/FileLike.h"
+#include "platform/FileHandle.h"
+
+namespace mbed {
+
+FileBase *FileBase::_head = NULL;
+SingletonPtr<PlatformMutex> FileBase::_mutex;
+
+FileBase::FileBase(const char *name, PathType t) : _next(NULL),
+ _name(name),
+ _path_type(t)
+{
+ _mutex->lock();
+ if (name != NULL) {
+ // put this object at head of the list
+ _next = _head;
+ _head = this;
+ } else {
+ _next = NULL;
+ }
+ _mutex->unlock();
+}
+
+FileBase::~FileBase()
+{
+ _mutex->lock();
+ if (_name != NULL) {
+ // remove this object from the list
+ if (_head == this) { // first in the list, so just drop me
+ _head = _next;
+ } else { // find the object before me, then drop me
+ FileBase *p = _head;
+ while (p->_next != this) {
+ p = p->_next;
+ }
+ p->_next = _next;
+ }
+ }
+ _mutex->unlock();
+
+ if (getPathType() == FilePathType) {
+ extern void remove_filehandle(FileHandle * file);
+ remove_filehandle(static_cast<FileHandle *>(static_cast<FileLike *>(this)));
+ }
+}
+
+FileBase *FileBase::lookup(const char *name, unsigned int len)
+{
+ _mutex->lock();
+ FileBase *p = _head;
+ while (p != NULL) {
+ /* Check that p->_name matches name and is the correct length */
+ if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
+ _mutex->unlock();
+ return p;
+ }
+ p = p->_next;
+ }
+ _mutex->unlock();
+ return NULL;
+}
+
+FileBase *FileBase::get(int n)
+{
+ _mutex->lock();
+ FileBase *p = _head;
+ int m = 0;
+ while (p != NULL) {
+ if (m == n) {
+ _mutex->unlock();
+ return p;
+ }
+
+ m++;
+ p = p->_next;
+ }
+ _mutex->unlock();
+ return NULL;
+}
+
+const char *FileBase::getName(void)
+{
+ // Constant read so no lock needed
+ return _name;
+}
+
+PathType FileBase::getPathType(void)
+{
+ // Constant read so no lock needed
+ return _path_type;
+}
+
+} // namespace mbed
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FileBase.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FileBase.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEBASE_H
+#define MBED_FILEBASE_H
+
+typedef int FILEHANDLE;
+
+#include <cstdio>
+#include <cstring>
+
+#include "platform/platform.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+
+typedef enum {
+ FilePathType,
+ FileSystemPathType
+} PathType;
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_FileBase FileBase class
+ * @{
+ */
+/** Class FileBase
+ *
+ */
+
+class FileBase : private NonCopyable<FileBase> {
+public:
+ FileBase(const char *name, PathType t);
+ virtual ~FileBase();
+
+ const char *getName(void);
+ PathType getPathType(void);
+
+ static FileBase *lookup(const char *name, unsigned int len);
+
+ static FileBase *get(int n);
+
+ /* disallow copy constructor and assignment operators */
+private:
+ static FileBase *_head;
+ static SingletonPtr<PlatformMutex> _mutex;
+
+ FileBase *_next;
+ const char *const _name;
+ const PathType _path_type;
+};
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FileHandle.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FileHandle.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,36 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileHandle.h"
+#include "platform/mbed_retarget.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+off_t FileHandle::size()
+{
+ /* remember our current position */
+ off_t off = seek(0, SEEK_CUR);
+ if (off < 0) {
+ return off;
+ }
+ /* seek to the end to get the file length */
+ off_t size = seek(0, SEEK_END);
+ /* return to our old position */
+ seek(off, SEEK_SET);
+ return size;
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FileHandle.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FileHandle.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,275 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEHANDLE_H
+#define MBED_FILEHANDLE_H
+
+typedef int FILEHANDLE;
+
+#include <cstdio>
+#include "Callback.h"
+#include "platform/mbed_poll.h"
+#include "platform/platform.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_FileHandle FileHandle functions
+ * @{
+ */
+
+
+/** Class FileHandle
+ *
+ * An abstract interface that represents operations on a file-like
+ * object. The core functions are read, write, and seek, but only
+ * a subset of these operations can be provided.
+ *
+ * @note to create a file, @see File
+ * @note Synchronization level: Set by subclass
+ */
+class FileHandle : private NonCopyable<FileHandle> {
+public:
+ virtual ~FileHandle() {}
+
+ /** Read the contents of a file into a buffer
+ *
+ * Devices acting as FileHandles should follow POSIX semantics:
+ *
+ * * if no data is available, and non-blocking set return -EAGAIN
+ * * if no data is available, and blocking set, wait until some data is available
+ * * If any data is available, call returns immediately
+ *
+ * @param buffer The buffer to read in to
+ * @param size The number of bytes to read
+ * @return The number of bytes read, 0 at end of file, negative error on failure
+ */
+ virtual ssize_t read(void *buffer, size_t size) = 0;
+
+ /** Write the contents of a buffer to a file
+ *
+ * Devices acting as FileHandles should follow POSIX semantics:
+ *
+ * * if blocking, block until all data is written
+ * * if no data can be written, and non-blocking set, return -EAGAIN
+ * * if some data can be written, and non-blocking set, write partial
+ *
+ * @param buffer The buffer to write from
+ * @param size The number of bytes to write
+ * @return The number of bytes written, negative error on failure
+ */
+ virtual ssize_t write(const void *buffer, size_t size) = 0;
+
+ /** Move the file position to a given offset from from a given location
+ *
+ * @param offset The offset from whence to move to
+ * @param whence The start of where to seek
+ * SEEK_SET to start from beginning of file,
+ * SEEK_CUR to start from current position in file,
+ * SEEK_END to start from end of file
+ * @return The new offset of the file, negative error code on failure
+ */
+ virtual off_t seek(off_t offset, int whence = SEEK_SET) = 0;
+
+ /** Close a file
+ *
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int close() = 0;
+
+ /** Flush any buffers associated with the file
+ *
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int sync()
+ {
+ return 0;
+ }
+
+ /** Check if the file in an interactive terminal device
+ *
+ * @return True if the file is a terminal
+ * @return False if the file is not a terminal
+ * @return Negative error code on failure
+ */
+ virtual int isatty()
+ {
+ return false;
+ }
+
+ /** Get the file position of the file
+ *
+ * @note This is equivalent to seek(0, SEEK_CUR)
+ *
+ * @return The current offset in the file, negative error code on failure
+ */
+ virtual off_t tell()
+ {
+ return seek(0, SEEK_CUR);
+ }
+
+ /** Rewind the file position to the beginning of the file
+ *
+ * @note This is equivalent to seek(0, SEEK_SET)
+ */
+ virtual void rewind()
+ {
+ seek(0, SEEK_SET);
+ }
+
+ /** Get the size of the file
+ *
+ * @return Size of the file in bytes
+ */
+ virtual off_t size();
+
+ /** Move the file position to a given offset from a given location.
+ *
+ * @param offset The offset from whence to move to
+ * @param whence SEEK_SET for the start of the file, SEEK_CUR for the
+ * current file position, or SEEK_END for the end of the file.
+ *
+ * @returns
+ * new file position on success,
+ * -1 on failure or unsupported
+ * @deprecated Replaced by `off_t FileHandle::seek(off_t offset, int whence = SEEK_SET)'
+ *
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by FileHandle::seek")
+ virtual off_t lseek(off_t offset, int whence)
+ {
+ return seek(offset, whence);
+ }
+
+ /** Flush any buffers associated with the FileHandle, ensuring it
+ * is up to date on disk
+ *
+ * @returns
+ * 0 on success or un-needed,
+ * -1 on error
+ * @deprecated Replaced by `int FileHandle::sync()'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by FileHandle::sync")
+ virtual int fsync()
+ {
+ return sync();
+ }
+
+ /** Find the length of the file
+ *
+ * @returns
+ * Length of the file
+ * @deprecated Replaced by `off_t FileHandle::size()'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by FileHandle::size")
+ virtual off_t flen()
+ {
+ return size();
+ }
+
+ /** Set blocking or non-blocking mode of the file operation like read/write.
+ * Definition depends upon the subclass implementing FileHandle.
+ * The default is blocking.
+ *
+ * @param blocking true for blocking mode, false for non-blocking mode.
+ *
+ * @return 0 on success
+ * @return Negative error code on failure
+ */
+ virtual int set_blocking(bool blocking)
+ {
+ return blocking ? 0 : -ENOTTY;
+ }
+
+ /** Check current blocking or non-blocking mode for file operations.
+ *
+ * @return true for blocking mode, false for non-blocking mode.
+ */
+ virtual bool is_blocking() const
+ {
+ return true;
+ }
+
+ /** Check for poll event flags
+ * The input parameter can be used or ignored - the could always return all events,
+ * or could check just the events listed in events.
+ * Call is non-blocking - returns instantaneous state of events.
+ * Whenever an event occurs, the derived class should call the sigio() callback).
+ *
+ * @param events bitmask of poll events we're interested in - POLLIN/POLLOUT etc.
+ *
+ * @returns bitmask of poll events that have occurred.
+ */
+ virtual short poll(short events) const
+ {
+ // Possible default for real files
+ return POLLIN | POLLOUT;
+ }
+
+ /** Definition depends upon the subclass implementing FileHandle.
+ * For example, if the FileHandle is of type Stream, writable() could return
+ * true when there is ample buffer space available for write() calls.
+ *
+ * @returns true if the FileHandle is writable.
+ */
+ bool writable() const
+ {
+ return poll(POLLOUT) & POLLOUT;
+ }
+
+ /** Definition depends upon the subclass implementing FileHandle.
+ * For example, if the FileHandle is of type Stream, readable() could return
+ * true when there is something available to read.
+ *
+ * @returns true when there is something available to read.
+ */
+ bool readable() const
+ {
+ return poll(POLLIN) & POLLIN;
+ }
+
+ /** Register a callback on state change of the file.
+ *
+ * The specified callback will be called on state changes such as when
+ * the file can be written to or read from.
+ *
+ * The callback may be called in an interrupt context and should not
+ * perform expensive operations.
+ *
+ * Note! This is not intended as an attach-like asynchronous api, but rather
+ * as a building block for constructing such functionality.
+ *
+ * The exact timing of when the registered function
+ * is called is not guaranteed and susceptible to change. It should be used
+ * as a cue to make read/write/poll calls to find the current state.
+ *
+ * @param func Function to call on state change
+ */
+ virtual void sigio(Callback<void()> func)
+ {
+ //Default for real files. Do nothing for real files.
+ }
+};
+
+/**@}*/
+
+/**@}*/
+
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FileLike.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FileLike.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILELIKE_H
+#define MBED_FILELIKE_H
+
+#include "platform/mbed_toolchain.h"
+#include "platform/FileBase.h"
+#include "platform/FileHandle.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_FileLike FileLike class
+ * @{
+ */
+/** Class FileLike
+ *
+ * A file-like object is one that can be opened with fopen by
+ * fopen("/name", mode).
+ *
+ * @note Synchronization level: Set by subclass
+ */
+class FileLike : public FileHandle, public FileBase, private NonCopyable<FileLike> {
+public:
+ /** Constructor FileLike
+ *
+ * @param name The name to use to open the file.
+ */
+ FileLike(const char *name = NULL) : FileBase(name, FilePathType) {}
+ virtual ~FileLike() {}
+};
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FilePath.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FilePath.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/FilePath.h"
+
+namespace mbed {
+
+FilePath::FilePath(const char *file_path) : file_name(NULL), fb(NULL)
+{
+ // skip slashes
+ file_path += strspn(file_path, "/");
+
+ const char *file_system = file_path;
+ file_name = file_system;
+ int len = 0;
+ while (true) {
+ char c = *file_name;
+ if (c == '/') { // end of object name
+ file_name++; // point to one char after the '/'
+ break;
+ }
+ if (c == 0) { // end of object name, with no filename
+ break;
+ }
+ len++;
+ file_name++;
+ }
+
+ MBED_ASSERT(len != 0);
+ fb = FileBase::lookup(file_system, len);
+}
+
+const char *FilePath::fileName(void)
+{
+ return file_name;
+}
+
+bool FilePath::isFileSystem(void)
+{
+ if (NULL == fb) {
+ return false;
+ }
+ return (fb->getPathType() == FileSystemPathType);
+}
+
+FileSystemLike *FilePath::fileSystem(void)
+{
+ if (isFileSystem()) {
+ return static_cast<FileSystemLike *>(fb);
+ }
+ return NULL;
+}
+
+bool FilePath::isFile(void)
+{
+ if (NULL == fb) {
+ return false;
+ }
+ return (fb->getPathType() == FilePathType);
+}
+
+FileLike *FilePath::file(void)
+{
+ if (isFile()) {
+ return (FileLike *)fb;
+ }
+ return NULL;
+}
+
+bool FilePath::exists(void)
+{
+ return fb != NULL;
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FilePath.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FilePath.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEPATH_H
+#define MBED_FILEPATH_H
+
+#include "platform/platform.h"
+
+#include "platform/FileSystemLike.h"
+#include "platform/FileLike.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_FilePath FilePath class
+ * @{
+ */
+
+class FileSystem;
+/** Class FilePath
+ *
+ */
+
+class FilePath {
+public:
+ /** Constructor FilePath
+ *
+ * @param file_path The path of file.
+ */
+ FilePath(const char *file_path);
+
+ const char *fileName(void);
+
+ bool isFileSystem(void);
+ FileSystemLike *fileSystem(void);
+
+ bool isFile(void);
+ FileLike *file(void);
+ bool exists(void);
+
+private:
+ const char *file_name;
+ FileBase *fb;
+};
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FileSystemHandle.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FileSystemHandle.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "FileSystemHandle.h"
+#include <errno.h>
+
+int FileSystemHandle::open(DirHandle **dir, const char *path)
+{
+ return -ENOSYS;
+}
+
+int FileSystemHandle::remove(const char *path)
+{
+ return -ENOSYS;
+}
+
+int FileSystemHandle::rename(const char *path, const char *newpath)
+{
+ return -ENOSYS;
+}
+
+int FileSystemHandle::stat(const char *path, struct stat *st)
+{
+ return -ENOSYS;
+}
+
+int FileSystemHandle::mkdir(const char *path, mode_t mode)
+{
+ return -ENOSYS;
+}
+
+int FileSystemHandle::statvfs(const char *path, struct statvfs *buf)
+{
+ return -ENOSYS;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FileSystemHandle.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FileSystemHandle.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMHANDLE_H
+#define MBED_FILESYSTEMHANDLE_H
+
+#include "platform/platform.h"
+
+#include "platform/FileBase.h"
+#include "platform/FileHandle.h"
+#include "platform/DirHandle.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_FileSystemHandle FileSystemHandle functions
+ * @{
+ */
+
+
+/** A filesystem-like object is one that can be used to open file-like
+ * objects though it by fopen("/name/filename", mode)
+ *
+ * Implementations must define at least open (the default definitions
+ * of the rest of the functions just return error values).
+ *
+ * @note Synchronization level: Set by subclass
+ */
+class FileSystemHandle : private NonCopyable<FileSystemHandle> {
+public:
+ /** FileSystemHandle lifetime
+ */
+ virtual ~FileSystemHandle() {}
+
+ /** Open a file on the filesystem
+ *
+ * @param file Destination for the handle to a newly created file
+ * @param filename The name of the file to open
+ * @param flags The flags to open the file in, one of O_RDONLY, O_WRONLY, O_RDWR,
+ * bitwise or'd with one of O_CREAT, O_TRUNC, O_APPEND
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int open(FileHandle **file, const char *filename, int flags) = 0;
+
+ /** Open a directory on the filesystem
+ *
+ * @param dir Destination for the handle to the directory
+ * @param path Name of the directory to open
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int open(DirHandle **dir, const char *path);
+
+ /** Remove a file from the filesystem.
+ *
+ * @param path The name of the file to remove.
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int remove(const char *path);
+
+ /** Rename a file in the filesystem.
+ *
+ * @param path The name of the file to rename.
+ * @param newpath The name to rename it to
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int rename(const char *path, const char *newpath);
+
+ /** Store information about the file in a stat structure
+ *
+ * @param path The name of the file to find information about
+ * @param st The stat buffer to write to
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int stat(const char *path, struct stat *st);
+
+ /** Create a directory in the filesystem.
+ *
+ * @param path The name of the directory to create.
+ * @param mode The permissions with which to create the directory
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int mkdir(const char *path, mode_t mode);
+
+ /** Store information about the mounted filesystem in a statvfs structure
+ *
+ * @param path The name of the file to find information about
+ * @param buf The stat buffer to write to
+ * @return 0 on success, negative error code on failure
+ */
+ virtual int statvfs(const char *path, struct statvfs *buf);
+};
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FileSystemLike.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FileSystemLike.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,92 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMLIKE_H
+#define MBED_FILESYSTEMLIKE_H
+
+#include "platform/platform.h"
+
+#include "platform/FileSystemHandle.h"
+#include "platform/FileHandle.h"
+#include "platform/DirHandle.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_FileSystemLike FileSystemLike functions
+ * @{
+ */
+
+
+/** A filesystem-like object is one that can be used to open file-like
+ * objects though it by fopen("/name/filename", mode)
+ *
+ * Implementations must define at least open (the default definitions
+ * of the rest of the functions just return error values).
+ *
+ * @note Synchronization level: Set by subclass
+ */
+class FileSystemLike : public FileSystemHandle, public FileBase, private NonCopyable<FileSystemLike> {
+public:
+ /** FileSystemLike lifetime
+ */
+ FileSystemLike(const char *name = NULL) : FileBase(name, FileSystemPathType) {}
+ virtual ~FileSystemLike() {}
+
+ // Inherited functions with name conflicts
+ using FileSystemHandle::open;
+
+ /** Open a file on the filesystem
+ *
+ * @param path The name of the file to open
+ * @param flags The flags to open the file in, one of O_RDONLY, O_WRONLY, O_RDWR,
+ * bitwise or'd with one of O_CREAT, O_TRUNC, O_APPEND
+ * @return A file handle on success, NULL on failure
+ * @deprecated Replaced by `int open(FileHandle **, ...)` for propagating error codes
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.5",
+ "Replaced by `int open(FileHandle **, ...)` for propagating error codes")
+ FileHandle *open(const char *path, int flags)
+ {
+ FileHandle *file;
+ int err = open(&file, path, flags);
+ return err ? NULL : file;
+ }
+
+ /** Open a directory on the filesystem
+ *
+ * @param path Name of the directory to open
+ * @return A directory handle on success, NULL on failure
+ * @deprecated Replaced by `int open(DirHandle **, ...)` for propagating error codes
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.5",
+ "Replaced by `int open(DirHandle **, ...)` for propagating error codes")
+ DirHandle *opendir(const char *path)
+ {
+ DirHandle *dir;
+ int err = open(&dir, path);
+ return err ? NULL : dir;
+ }
+};
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/FunctionPointer.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/FunctionPointer.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FUNCTIONPOINTER_H
+#define MBED_FUNCTIONPOINTER_H
+
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+#include <string.h>
+#include <stdint.h>
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_FunctionPointer FunctionPointer class
+ * @{
+ */
+
+// Declarations for backwards compatibility
+// To be foward compatible, code should adopt the Callback class
+template <typename R, typename A1>
+class FunctionPointerArg1 : public Callback<R(A1)> {
+public:
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
+ FunctionPointerArg1(R(*function)(A1) = 0)
+ : Callback<R(A1)>(function) {}
+
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
+ FunctionPointerArg1(T *object, R(T::*member)(A1))
+ : Callback<R(A1)>(object, member) {}
+
+ R(*get_function())(A1)
+ {
+ return *reinterpret_cast<R(* *)(A1)>(this);
+ }
+
+ R call(A1 a1) const
+ {
+ if (!Callback<R(A1)>::operator bool()) {
+ return (R)0;
+ }
+
+ return Callback<R(A1)>::call(a1);
+ }
+
+ R operator()(A1 a1) const
+ {
+ return Callback<R(A1)>::call(a1);
+ }
+};
+
+template <typename R>
+class FunctionPointerArg1<R, void> : public Callback<R()> {
+public:
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "FunctionPointer has been replaced by Callback<void()>")
+ FunctionPointerArg1(R(*function)() = 0)
+ : Callback<R()>(function) {}
+
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "FunctionPointer has been replaced by Callback<void()>")
+ FunctionPointerArg1(T *object, R(T::*member)())
+ : Callback<R()>(object, member) {}
+
+ R(*get_function())()
+ {
+ return *reinterpret_cast<R(* *)()>(this);
+ }
+
+ R call() const
+ {
+ if (!Callback<R()>::operator bool()) {
+ return (R)0;
+ }
+
+ return Callback<R()>::call();
+ }
+
+ R operator()() const
+ {
+ return Callback<R()>::call();
+ }
+};
+
+typedef FunctionPointerArg1<void, void> FunctionPointer;
+
+/**@}*/
+
+/**@}*/
+
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/LocalFileSystem.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/LocalFileSystem.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,302 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/LocalFileSystem.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "platform/mbed_semihost_api.h"
+#include <string.h>
+#include <stdio.h>
+#include <errno.h>
+
+namespace mbed {
+
+/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
+typedef struct {
+ unsigned char hr; /* Hours [0..23] */
+ unsigned char min; /* Minutes [0..59] */
+ unsigned char sec; /* Seconds [0..59] */
+ unsigned char day; /* Day [1..31] */
+ unsigned char mon; /* Month [1..12] */
+ unsigned short year; /* Year [1980..2107] */
+} FTIME;
+
+typedef struct { /* File Search info record */
+ char name[32]; /* File name */
+ long size; /* File size in bytes */
+ int fileID; /* System File Identification */
+ FTIME create_time; /* Date & time file was created */
+ FTIME write_time; /* Date & time of last write */
+} XFINFO;
+
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+
+static int xffind(const char *pattern, XFINFO *info)
+{
+ unsigned param[4];
+
+ param[0] = (unsigned long)pattern;
+ param[1] = (unsigned long)strlen(pattern);
+ param[2] = (unsigned long)info;
+ param[3] = (unsigned long)sizeof(XFINFO);
+
+ return __semihost(USR_XFFIND, param);
+}
+
+#define OPEN_R 0
+#define OPEN_B 1
+#define OPEN_PLUS 2
+#define OPEN_W 4
+#define OPEN_A 8
+#define OPEN_INVALID -1
+
+int posix_to_semihost_open_flags(int flags)
+{
+ /* POSIX flags -> semihosting open mode */
+ int openmode;
+ if (flags & O_RDWR) {
+ /* a plus mode */
+ openmode = OPEN_PLUS;
+ if (flags & O_APPEND) {
+ openmode |= OPEN_A;
+ } else if (flags & O_TRUNC) {
+ openmode |= OPEN_W;
+ } else {
+ openmode |= OPEN_R;
+ }
+ } else if (flags & O_WRONLY) {
+ /* write or append */
+ if (flags & O_APPEND) {
+ openmode = OPEN_A;
+ } else {
+ openmode = OPEN_W;
+ }
+ } else if (flags == O_RDONLY) {
+ /* read mode */
+ openmode = OPEN_R;
+ } else {
+ /* invalid flags */
+ openmode = OPEN_INVALID;
+ }
+
+ return openmode;
+}
+
+FILEHANDLE local_file_open(const char *name, int flags)
+{
+ int openmode = posix_to_semihost_open_flags(flags);
+ if (openmode == OPEN_INVALID) {
+ return (FILEHANDLE)NULL;
+ }
+
+ FILEHANDLE fh = semihost_open(name, openmode);
+ if (fh == -1) {
+ return (FILEHANDLE)NULL;
+ }
+
+ return fh;
+}
+
+LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0)
+{
+ // No lock needed in constructor
+}
+
+int LocalFileHandle::close()
+{
+ int retval = semihost_close(_fh);
+ delete this;
+ return retval;
+}
+
+ssize_t LocalFileHandle::write(const void *buffer, size_t length)
+{
+ lock();
+ ssize_t n = semihost_write(_fh, (const unsigned char *)buffer, length, 0); // number of characters not written
+ n = length - n; // number of characters written
+ pos += n;
+ unlock();
+ return n;
+}
+
+ssize_t LocalFileHandle::read(void *buffer, size_t length)
+{
+ lock();
+ ssize_t n = semihost_read(_fh, (unsigned char *)buffer, length, 0); // number of characters not read
+ n = length - n; // number of characters read
+ pos += n;
+ unlock();
+ return n;
+}
+
+int LocalFileHandle::isatty()
+{
+ lock();
+ int ret = semihost_istty(_fh);
+ unlock();
+ return ret;
+}
+
+off_t LocalFileHandle::seek(off_t position, int whence)
+{
+ lock();
+ if (whence == SEEK_CUR) {
+ position += pos;
+ } else if (whence == SEEK_END) {
+ position += semihost_flen(_fh);
+ } /* otherwise SEEK_SET, so position is fine */
+
+ /* Always seems to return -1, so just ignore for now. */
+ semihost_seek(_fh, position);
+ pos = position;
+ unlock();
+ return position;
+}
+
+int LocalFileHandle::sync()
+{
+ lock();
+ int ret = semihost_ensure(_fh);
+ unlock();
+ return ret;
+}
+
+off_t LocalFileHandle::size()
+{
+ lock();
+ off_t off = semihost_flen(_fh);
+ unlock();
+ return off;
+}
+
+void LocalFileHandle::lock()
+{
+ _mutex.lock();
+}
+
+void LocalFileHandle::unlock()
+{
+ _mutex.unlock();
+}
+
+class LocalDirHandle : public DirHandle {
+
+public:
+ XFINFO info;
+
+ LocalDirHandle() : info()
+ {
+ }
+
+ virtual int close()
+ {
+ // No lock can be used in destructor
+ delete this;
+ return 0;
+ }
+
+ virtual int read(struct dirent *ent)
+ {
+ lock();
+ if (xffind("*", &info) != 0) {
+ unlock();
+ return 0;
+ }
+ memcpy(ent->d_name, info.name, sizeof(info.name));
+ unlock();
+ return 1;
+ }
+
+ virtual void rewind()
+ {
+ lock();
+ info.fileID = 0;
+ unlock();
+ }
+
+ virtual off_t tell()
+ {
+ lock();
+ int fileId = info.fileID;
+ unlock();
+ return fileId;
+ }
+
+ virtual void seek(off_t offset)
+ {
+ lock();
+ info.fileID = offset;
+ unlock();
+ }
+
+protected:
+ PlatformMutex _mutex;
+
+ virtual void lock()
+ {
+ _mutex.lock();
+ }
+
+ virtual void unlock()
+ {
+ _mutex.unlock();
+ }
+};
+
+int LocalFileSystem::open(FileHandle **file, const char *name, int flags)
+{
+ // No global state modified so function is thread safe
+
+ /* reject filenames with / in them */
+ for (const char *tmp = name; *tmp; tmp++) {
+ if (*tmp == '/') {
+ return -EINVAL;
+ }
+ }
+
+ int openmode = posix_to_semihost_open_flags(flags);
+ if (openmode == OPEN_INVALID) {
+ return -EINVAL;
+ }
+
+ FILEHANDLE fh = semihost_open(name, openmode);
+ if (fh == -1) {
+ return -EIO;
+ }
+
+ *file = new LocalFileHandle(fh);
+ return 0;
+}
+
+int LocalFileSystem::remove(const char *filename)
+{
+ // No global state modified so function is thread safe
+
+ return semihost_remove(filename);
+}
+
+int LocalFileSystem::open(DirHandle **dir, const char *name)
+{
+ // No global state modified so function is thread safe
+
+ *dir = new LocalDirHandle();
+ return 0;
+}
+
+} // namespace mbed
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/LocalFileSystem.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/LocalFileSystem.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,128 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOCALFILESYSTEM_H
+#define MBED_LOCALFILESYSTEM_H
+
+#include "platform/platform.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "platform/FileSystemLike.h"
+#include "platform/PlatformMutex.h"
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_LocalFileSystem LocalFileSystem functions
+ * @{
+ */
+
+FILEHANDLE local_file_open(const char *name, int flags);
+
+/**
+ * @class LocalFileHandle
+ * @ingroup platform
+ */
+class LocalFileHandle : public FileHandle, private NonCopyable<LocalFileHandle> {
+
+public:
+ LocalFileHandle(FILEHANDLE fh);
+
+ virtual int close();
+
+ virtual ssize_t write(const void *buffer, size_t length);
+
+ virtual ssize_t read(void *buffer, size_t length);
+
+ virtual int isatty();
+
+ virtual off_t seek(off_t position, int whence);
+
+ virtual int sync();
+
+ virtual off_t size();
+
+protected:
+ virtual void lock();
+ virtual void unlock();
+ FILEHANDLE _fh;
+ int pos;
+ PlatformMutex _mutex;
+};
+
+/** A filesystem for accessing the local mbed Microcontroller USB disk drive
+ *
+ * This allows programs to read and write files on the same disk drive that is used to program the
+ * mbed Microcontroller. Once created, the standard C file access functions are used to open,
+ * read and write files.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * LocalFileSystem local("local"); // Create the local filesystem under the name "local"
+ *
+ * int main() {
+ * FILE *fp = fopen("/local/out.txt", "w"); // Open "out.txt" on the local file system for writing
+ * fprintf(fp, "Hello World!");
+ * fclose(fp);
+ * remove("/local/out.txt"); // Removes the file "out.txt" from the local file system
+ *
+ * DIR *d = opendir("/local"); // Opens the root directory of the local file system
+ * struct dirent *p;
+ * while((p = readdir(d)) != NULL) { // Print the names of the files in the local file system
+ * printf("%s\n", p->d_name); // to stdout.
+ * }
+ * closedir(d);
+ * }
+ * @endcode
+ *
+ * @note
+ * If the microcontroller program makes an access to the local drive, it will be marked as "removed"
+ * on the Host computer. This means it is no longer accessible from the Host Computer.
+ *
+ * The drive will only re-appear when the microcontroller program exists. Note that if the program does
+ * not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
+ * @ingroup platform
+ */
+class LocalFileSystem : public FileSystemLike, private NonCopyable<LocalFileSystem> {
+ // No modifiable state
+
+public:
+ LocalFileSystem(const char *n) : FileSystemLike(n)
+ {
+
+ }
+
+ virtual int open(FileHandle **file, const char *path, int flags);
+ virtual int open(DirHandle **dir, const char *name);
+ virtual int remove(const char *filename);
+};
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/NonCopyable.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/NonCopyable.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,211 @@
+/* Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_NONCOPYABLE_H_
+#define MBED_NONCOPYABLE_H_
+
+#if (!defined(MBED_DEBUG) && (MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR == 0))
+#include "mbed_toolchain.h"
+#include "mbed_debug.h"
+#endif
+
+namespace mbed {
+
+/**
+ * Inheriting from this class autogeneration of copy construction and copy
+ * assignment operations.
+ *
+ * Classes which are not value type should inherit privately from this class
+ * to avoid generation of invalid copy constructor or copy assignment operator
+ * which can lead to unnoticeable programming errors.
+ *
+ * As an example consider the following signature:
+ *
+ * @code
+ * class Resource;
+ *
+ * class Foo {
+ * public:
+ * Foo() : _resource(new Resource()) { }
+ * ~Foo() { delete _resource; }
+ * private:
+ * Resource* _resource;
+ * }
+ *
+ * Foo get_foo();
+ *
+ * Foo foo = get_foo();
+ * @endcode
+ *
+ * There is a bug in this function, it returns a temporary value which will be
+ * byte copied into foo then destroyed. Unfortunately, internally the Foo class
+ * manage a pointer to a Resource object. This pointer will be released when the
+ * temporary is destroyed and foo will manage a pointer to an already released
+ * Resource.
+ *
+ * Two issues has to be fixed in the example above:
+ * - Function signature has to be changed to reflect the fact that Foo
+ * instances cannot be copied. In that case accessor should return a
+ * reference to give access to objects already existing and managed.
+ * Generator on the other hand should return a pointer to the created object.
+ *
+ * @code
+ * // return a reference to an already managed Foo instance
+ * Foo& get_foo();
+ * Foo& foo = get_foo();
+ *
+ * // create a new Foo instance
+ * Foo* make_foo();
+ * Foo* m = make_foo();
+ * @endcode
+ *
+ * - Copy constructor and copy assignment operator has to be made private
+ * in the Foo class. It prevents unwanted copy of Foo objects. This can be
+ * done by declaring copy constructor and copy assignment in the private
+ * section of the Foo class.
+ *
+ * @code
+ * class Foo {
+ * public:
+ * Foo() : _resource(new Resource()) { }
+ * ~Foo() { delete _resource; }
+ * private:
+ * // disallow copy operations
+ * Foo(const Foo&);
+ * Foo& operator=(const Foo&);
+ * // data members
+ * Resource* _resource;
+ * }
+ * @endcode
+ *
+ * Another solution is to inherit privately from the NonCopyable class.
+ * It reduces the boiler plate needed to avoid copy operations but more
+ * importantly it clarifies the programmer intent and the object semantic.
+ *
+ * class Foo : private NonCopyable<Foo> {
+ * public:
+ * Foo() : _resource(new Resource()) { }
+ * ~Foo() { delete _resource; }
+ * private:
+ * Resource* _resource;
+ * }
+ *
+ * @tparam T The type that should be made non copyable. It prevent cases where
+ * the empty base optimization cannot be applied and therefore ensure that the
+ * cost of this semantic sugar is null.
+ *
+ * As an example, the empty base optimization is prohibited if one of the empty
+ * base class is also a base type of the first non static data member:
+ *
+ * @code
+ * struct A { };
+ * struct B : A {
+ * int foo;
+ * };
+ * // thanks to empty base optimization, sizeof(B) == sizeof(int)
+ *
+ * struct C : A {
+ * B b;
+ * };
+ *
+ * // empty base optimization cannot be applied here because A from C and A from
+ * // B shall have a different address. In that case, with the alignment
+ * // sizeof(C) == 2* sizeof(int)
+ * @endcode
+ *
+ * The solution to that problem is to templatize the empty class to makes it
+ * unique to the type it is applied to:
+ *
+ * @code
+ * template<typename T>
+ * struct A<T> { };
+ * struct B : A<B> {
+ * int foo;
+ * };
+ * struct C : A<C> {
+ * B b;
+ * };
+ *
+ * // empty base optimization can be applied B and C does not refer to the same
+ * // kind of A. sizeof(C) == sizeof(B) == sizeof(int).
+ * @endcode
+ *
+ * @note Compile time errors are disabled if the develop or the release profile
+ * is used. To override this behavior and force compile time errors in all profile
+ * set the configuration parameter "platform.force-non-copyable-error" to true.
+ */
+template<typename T>
+class NonCopyable {
+protected:
+ /**
+ * Disallow construction of NonCopyable objects from outside of its hierarchy.
+ */
+ NonCopyable() { }
+ /**
+ * Disallow destruction of NonCopyable objects from outside of its hierarchy.
+ */
+ ~NonCopyable() { }
+
+#if (!defined(MBED_DEBUG) && (MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR == 0))
+ /**
+ * NonCopyable copy constructor.
+ *
+ * A compile time warning is issued when this function is used and a runtime
+ * warning is printed when the copy construction of the non copyable happens.
+ *
+ * If you see this warning, your code is probably doing something unspecified.
+ * Copy of non copyable resources can lead to resource leak and random error.
+ */
+ MBED_DEPRECATED("Invalid copy construction of a NonCopyable resource.")
+ NonCopyable(const NonCopyable &)
+ {
+ debug("Invalid copy construction of a NonCopyable resource: %s\r\n", MBED_PRETTY_FUNCTION);
+ }
+
+ /**
+ * NonCopyable copy assignment operator.
+ *
+ * A compile time warning is issued when this function is used and a runtime
+ * warning is printed when the copy construction of the non copyable happens.
+ *
+ * If you see this warning, your code is probably doing something unspecified.
+ * Copy of non copyable resources can lead to resource leak and random error.
+ */
+ MBED_DEPRECATED("Invalid copy assignment of a NonCopyable resource.")
+ NonCopyable &operator=(const NonCopyable &)
+ {
+ debug("Invalid copy assignment of a NonCopyable resource: %s\r\n", MBED_PRETTY_FUNCTION);
+ return *this;
+ }
+
+#else
+private:
+ /**
+ * Declare copy constructor as private, any attempt to copy construct
+ * a NonCopyable will fail at compile time.
+ */
+ NonCopyable(const NonCopyable &);
+
+ /**
+ * Declare copy assignment operator as private, any attempt to copy assign
+ * a NonCopyable will fail at compile time.
+ */
+ NonCopyable &operator=(const NonCopyable &);
+#endif
+};
+
+} // namespace mbed
+
+#endif /* MBED_NONCOPYABLE_H_ */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/PlatformMutex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/PlatformMutex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_PlatformMutex PlatformMutex class
+ * @{
+ */
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef PLATFORM_MUTEX_H
+#define PLATFORM_MUTEX_H
+
+#include "platform/NonCopyable.h"
+
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "rtos/Mutex.h"
+typedef rtos::Mutex PlatformMutex;
+#else
+/** A stub mutex for when an RTOS is not present
+*/
+class PlatformMutex : private mbed::NonCopyable<PlatformMutex> {
+public:
+ PlatformMutex()
+ {
+ // Stub
+
+ }
+ ~PlatformMutex()
+ {
+ // Stub
+ }
+
+ void lock()
+ {
+ // Do nothing
+ }
+
+ void unlock()
+ {
+ // Do nothing
+ }
+};
+
+#endif
+
+#endif
+
+/**@}*/
+
+/**@}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/ScopedLock.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/ScopedLock.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SCOPEDLOCK_H
+#define MBED_SCOPEDLOCK_H
+
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_ScopedLock ScopedLock functions
+ * @{
+ */
+
+/** RAII-style mechanism for owning a lock of Lockable object for the duration of a scoped block
+ *
+ * @tparam Lockable The type implementing BasicLockable concept
+ *
+ * @note For type Lockable to be BasicLockable, the following conditions have to be satisfied:
+ * - has public member function @a lock which blocks until a lock can be obtained for the current execution context
+ * - has public member function @a unlock which releases the lock
+ *
+ * Usage:
+ *
+ * Example with rtos::Mutex
+ *
+ * @code
+ * void foo(Mutex &m) {
+ * ScopedLock<Mutex> lock(m);
+ * // Mutex lock protects code in this block
+ * }
+ * @endcode
+ *
+ *
+ * More generic example
+ *
+ * @code
+ * template<typename Lockable>
+ * void foo(Lockable& lockable) {
+ * ScopedLock<Lockable> lock(lockable);
+ * // Code in this block runs under lock
+ * }
+ * @endcode
+ */
+template <typename Lockable>
+class ScopedLock : private NonCopyable<ScopedLock<Lockable> > {
+public:
+ /** Locks given locable object
+ *
+ * @param lockable reference to the instance of Lockable object
+ * @note lockable object should outlive the ScopedLock object
+ */
+ ScopedLock(Lockable &lockable): _lockable(lockable)
+ {
+ _lockable.lock();
+ }
+
+ ~ScopedLock()
+ {
+ _lockable.unlock();
+ }
+private:
+ Lockable &_lockable;
+};
+
+/**@}*/
+
+/**@}*/
+
+} // embed
+
+#endif // MBED_SCOPEDLOCK_H
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/SingletonPtr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/SingletonPtr.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,117 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_SingletonPtr SingletonPtr class
+ * @{
+ */
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef SINGLETONPTR_H
+#define SINGLETONPTR_H
+
+#include <stdint.h>
+#include <new>
+#include "platform/mbed_assert.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "cmsis_os2.h"
+#endif
+
+#ifdef MBED_CONF_RTOS_PRESENT
+extern osMutexId_t singleton_mutex_id;
+#endif
+
+/** Lock the singleton mutex
+ *
+ * This function is typically used to provide
+ * exclusive access when initializing a
+ * global object.
+ */
+inline static void singleton_lock(void)
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ osMutexAcquire(singleton_mutex_id, osWaitForever);
+#endif
+}
+
+/** Unlock the singleton mutex
+ *
+ * This function is typically used to provide
+ * exclusive access when initializing a
+ * global object.
+ */
+inline static void singleton_unlock(void)
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ osMutexRelease(singleton_mutex_id);
+#endif
+}
+
+/** Utility class for creating an using a singleton
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @note: This class must only be used in a static context -
+ * this class must never be allocated or created on the
+ * stack.
+ *
+ * @note: This class is lazily initialized on first use.
+ * This class is a POD type so if it is not used it will
+ * be garbage collected.
+ */
+template <class T>
+struct SingletonPtr {
+
+ /** Get a pointer to the underlying singleton
+ *
+ * @returns
+ * A pointer to the singleton
+ */
+ T *get()
+ {
+ if (NULL == _ptr) {
+ singleton_lock();
+ if (NULL == _ptr) {
+ _ptr = new (_data) T();
+ }
+ singleton_unlock();
+ }
+ // _ptr was not zero initialized or was
+ // corrupted if this assert is hit
+ MBED_ASSERT(_ptr == (T *)&_data);
+ return _ptr;
+ }
+
+ /** Get a pointer to the underlying singleton
+ *
+ * @returns
+ * A pointer to the singleton
+ */
+ T *operator->()
+ {
+ return get();
+ }
+
+ // This is zero initialized when in global scope
+ T *_ptr;
+ // Force data to be 4 byte aligned
+ uint32_t _data[(sizeof(T) + sizeof(uint32_t) - 1) / sizeof(uint32_t)];
+};
+
+#endif
+/**@}*/
+
+/**@}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/Stream.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/Stream.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,186 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/Stream.h"
+#include "platform/mbed_error.h"
+#include <errno.h>
+
+namespace mbed {
+
+Stream::Stream(const char *name) : FileLike(name), _file(NULL)
+{
+ // No lock needed in constructor
+ /* open ourselves */
+ _file = fdopen(this, "w+");
+ // fdopen() will make us buffered because Stream::isatty()
+ // wrongly returns zero which is not being changed for
+ // backward compatibility
+ if (_file) {
+ mbed_set_unbuffered_stream(_file);
+ } else {
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OPEN_FAILED), "Stream obj failure", _file);
+ }
+}
+
+Stream::~Stream()
+{
+ // No lock can be used in destructor
+ fclose(_file);
+}
+
+int Stream::putc(int c)
+{
+ lock();
+ fflush(_file);
+ int ret = std::fputc(c, _file);
+ unlock();
+ return ret;
+}
+int Stream::puts(const char *s)
+{
+ lock();
+ fflush(_file);
+ int ret = std::fputs(s, _file);
+ unlock();
+ return ret;
+}
+int Stream::getc()
+{
+ lock();
+ fflush(_file);
+ int ret = mbed_getc(_file);
+ unlock();
+ return ret;
+}
+char *Stream::gets(char *s, int size)
+{
+ lock();
+ fflush(_file);
+ char *ret = mbed_gets(s, size, _file);
+ unlock();
+ return ret;
+}
+
+int Stream::close()
+{
+ return 0;
+}
+
+ssize_t Stream::write(const void *buffer, size_t length)
+{
+ const char *ptr = (const char *)buffer;
+ const char *end = ptr + length;
+
+ lock();
+ while (ptr != end) {
+ if (_putc(*ptr++) == EOF) {
+ break;
+ }
+ }
+ unlock();
+
+ return ptr - (const char *)buffer;
+}
+
+ssize_t Stream::read(void *buffer, size_t length)
+{
+ char *ptr = (char *)buffer;
+ char *end = ptr + length;
+
+ lock();
+ while (ptr != end) {
+ int c = _getc();
+ if (c == EOF) {
+ break;
+ }
+ *ptr++ = c;
+ }
+ unlock();
+
+ return ptr - (const char *)buffer;
+}
+
+off_t Stream::seek(off_t offset, int whence)
+{
+ return 0;
+}
+
+off_t Stream::tell()
+{
+ return 0;
+}
+
+void Stream::rewind()
+{
+}
+
+int Stream::isatty()
+{
+ return 0;
+}
+
+int Stream::sync()
+{
+ return 0;
+}
+
+off_t Stream::size()
+{
+ return 0;
+}
+
+int Stream::printf(const char *format, ...)
+{
+ lock();
+ std::va_list arg;
+ va_start(arg, format);
+ fflush(_file);
+ int r = vfprintf(_file, format, arg);
+ va_end(arg);
+ unlock();
+ return r;
+}
+
+int Stream::scanf(const char *format, ...)
+{
+ lock();
+ std::va_list arg;
+ va_start(arg, format);
+ fflush(_file);
+ int r = vfscanf(_file, format, arg);
+ va_end(arg);
+ unlock();
+ return r;
+}
+
+int Stream::vprintf(const char *format, std::va_list args)
+{
+ lock();
+ fflush(_file);
+ int r = vfprintf(_file, format, args);
+ unlock();
+ return r;
+}
+
+int Stream::vscanf(const char *format, std::va_list args)
+{
+ lock();
+ fflush(_file);
+ int r = vfscanf(_file, format, args);
+ unlock();
+ return r;
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/Stream.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/Stream.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STREAM_H
+#define MBED_STREAM_H
+
+#include "platform/platform.h"
+#include "platform/FileLike.h"
+#include "platform/FileHandle.h"
+#include "platform/NonCopyable.h"
+#include <cstdio>
+#include <cstdarg>
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_Stream Stream class
+ * @{
+ */
+
+extern void mbed_set_unbuffered_stream(std::FILE *_file);
+extern int mbed_getc(std::FILE *_file);
+extern char *mbed_gets(char *s, int size, std::FILE *_file);
+
+/** File stream
+ *
+ * @note Synchronization level: Set by subclass
+ */
+class Stream : public FileLike, private NonCopyable<Stream> {
+
+public:
+ Stream(const char *name = NULL);
+ virtual ~Stream();
+
+ int putc(int c);
+ int puts(const char *s);
+ int getc();
+ char *gets(char *s, int size);
+ int printf(const char *format, ...);
+ int scanf(const char *format, ...);
+ int vprintf(const char *format, std::va_list args);
+ int vscanf(const char *format, std::va_list args);
+
+ operator std::FILE *()
+ {
+ return _file;
+ }
+
+protected:
+ virtual int close();
+ virtual ssize_t write(const void *buffer, size_t length);
+ virtual ssize_t read(void *buffer, size_t length);
+ virtual off_t seek(off_t offset, int whence);
+ virtual off_t tell();
+ virtual void rewind();
+ virtual int isatty();
+ virtual int sync();
+ virtual off_t size();
+
+ virtual int _putc(int c) = 0;
+ virtual int _getc() = 0;
+
+ std::FILE *_file;
+
+ /** Acquire exclusive access to this object.
+ */
+ virtual void lock()
+ {
+ // Stub
+ }
+
+ /** Release exclusive access to this object.
+ */
+ virtual void unlock()
+ {
+ // Stub
+ }
+};
+/**@}*/
+
+/**@}*/
+} // namespace mbed
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/Transaction.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/Transaction.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,88 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRANSACTION_H
+#define MBED_TRANSACTION_H
+
+#include "platform/platform.h"
+#include "platform/FunctionPointer.h"
+
+namespace mbed {
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_Transaction Transaction class
+ * @{
+ */
+
+/** Transaction structure
+ */
+typedef struct {
+ void *tx_buffer; /**< Tx buffer */
+ size_t tx_length; /**< Length of Tx buffer*/
+ void *rx_buffer; /**< Rx buffer */
+ size_t rx_length; /**< Length of Rx buffer */
+ uint32_t event; /**< Event for a transaction */
+ event_callback_t callback; /**< User's callback */
+ uint8_t width; /**< Buffer's word width (8, 16, 32, 64) */
+} transaction_t;
+
+/** Transaction class defines a transaction.
+ *
+ * @note Synchronization level: Not protected
+ */
+template<typename Class>
+class Transaction {
+public:
+ Transaction(Class *tpointer, const transaction_t &transaction) : _obj(tpointer), _data(transaction)
+ {
+ }
+
+ Transaction() : _obj(), _data()
+ {
+ }
+
+ ~Transaction()
+ {
+ }
+
+ /** Get object's instance for the transaction
+ *
+ * @return The object which was stored
+ */
+ Class *get_object()
+ {
+ return _obj;
+ }
+
+ /** Get the transaction
+ *
+ * @return The transaction which was stored
+ */
+ transaction_t *get_transaction()
+ {
+ return &_data;
+ }
+
+private:
+ Class *_obj;
+ transaction_t _data;
+};
+/**@}*/
+
+/**@}*/
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/astyle-branch.out --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/platform/astyle-branch.out Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,74 @@ +Formatted .\ATCmdParser.cpp +Formatted .\ATCmdParser.h +Formatted .\Callback.h +Formatted .\CallChain.cpp +Formatted .\CallChain.h +Formatted .\CircularBuffer.h +Unchanged .\critical.h +Formatted .\CriticalSectionLock.h +Formatted .\CThunk.h +Unchanged .\DeepSleepLock.h +Formatted .\DirHandle.h +Formatted .\FileBase.cpp +Formatted .\FileBase.h +Unchanged .\FileHandle.cpp +Formatted .\FileHandle.h +Unchanged .\FileLike.h +Formatted .\FilePath.cpp +Formatted .\FilePath.h +Unchanged .\FileSystemHandle.cpp +Formatted .\FileSystemHandle.h +Formatted .\FileSystemLike.h +Formatted .\FunctionPointer.h +Formatted .\LocalFileSystem.cpp +Formatted .\LocalFileSystem.h +Formatted .\mbed_alloc_wrappers.cpp +Formatted .\mbed_application.c +Unchanged .\mbed_application.h +Unchanged .\mbed_assert.c +Unchanged .\mbed_assert.h +Formatted .\mbed_board.c +Formatted .\mbed_critical.c +Formatted .\mbed_critical.h +Formatted .\mbed_debug.h +Formatted .\mbed_error.c +Formatted .\mbed_error.h +Formatted .\mbed_error_hist.c +Formatted .\mbed_error_hist.h +Formatted .\mbed_interface.c +Formatted .\mbed_interface.h +Formatted .\mbed_mem_trace.cpp +Formatted .\mbed_mem_trace.h +Formatted .\mbed_mktime.c +Formatted .\mbed_mktime.h +Unchanged .\mbed_poll.cpp +Unchanged .\mbed_poll.h +Formatted .\mbed_power_mgmt.h +Unchanged .\mbed_preprocessor.h +Formatted .\mbed_retarget.cpp +Formatted .\mbed_retarget.h +Formatted .\mbed_rtc_time.cpp +Unchanged .\mbed_rtc_time.h +Formatted .\mbed_sdk_boot.c +Formatted .\mbed_semihost_api.c +Formatted .\mbed_semihost_api.h +Unchanged .\mbed_sleep.h +Unchanged .\mbed_stats.c +Unchanged .\mbed_stats.h +Formatted .\mbed_toolchain.h +Formatted .\mbed_wait_api.h +Formatted .\mbed_wait_api_no_rtos.c +Formatted .\mbed_wait_api_rtos.cpp +Formatted .\NonCopyable.h +Unchanged .\platform.h +Formatted .\PlatformMutex.h +Unchanged .\rtc_time.h +Formatted .\ScopedLock.h +Unchanged .\semihost_api.h +Formatted .\SingletonPtr.h +Unchanged .\sleep.h +Formatted .\Stream.cpp +Formatted .\Stream.h +Unchanged .\toolchain.h +Formatted .\Transaction.h +Unchanged .\wait_api.h
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/critical.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/platform/critical.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_CRITICAL_H +#define MBED_OLD_CRITICAL_H + +#warning critical.h has been replaced by mbed_critical.h, please update to mbed_critical.h [since mbed-os-5.3] +#include "platform/mbed_critical.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_alloc_wrappers.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_alloc_wrappers.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,413 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/mbed_mem_trace.h"
+#include "platform/mbed_stats.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+/* There are two memory tracers in mbed OS:
+
+- the first can be used to detect the maximum heap usage at runtime. It is
+ activated by defining the MBED_HEAP_STATS_ENABLED macro.
+- the second can be used to trace each memory call by automatically invoking
+ a callback on each memory operation (see hal/api/mbed_mem_trace.h). It is
+ activated by defining the MBED_MEM_TRACING_ENABLED macro.
+
+Both tracers can be activated and deactivated in any combination. If both tracers
+are active, the second one (MBED_MEM_TRACING_ENABLED) will trace the first one's
+(MBED_HEAP_STATS_ENABLED) memory calls.*/
+
+/******************************************************************************/
+/* Implementation of the runtime max heap usage checker */
+/******************************************************************************/
+
+/* Size must be a multiple of 8 to keep alignment */
+typedef struct {
+ uint32_t size;
+ uint32_t pad;
+} alloc_info_t;
+
+#ifdef MBED_HEAP_STATS_ENABLED
+static SingletonPtr<PlatformMutex> malloc_stats_mutex;
+static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0};
+#endif
+
+void mbed_stats_heap_get(mbed_stats_heap_t *stats)
+{
+#ifdef MBED_HEAP_STATS_ENABLED
+ extern uint32_t mbed_heap_size;
+ heap_stats.reserved_size = mbed_heap_size;
+
+ malloc_stats_mutex->lock();
+ memcpy(stats, &heap_stats, sizeof(mbed_stats_heap_t));
+ malloc_stats_mutex->unlock();
+#else
+ memset(stats, 0, sizeof(mbed_stats_heap_t));
+#endif
+}
+
+/******************************************************************************/
+/* GCC memory allocation wrappers */
+/******************************************************************************/
+
+#if defined(TOOLCHAIN_GCC)
+
+#ifdef FEATURE_UVISOR
+#include "uvisor-lib/uvisor-lib.h"
+#endif/* FEATURE_UVISOR */
+
+extern "C" {
+ void *__real__malloc_r(struct _reent *r, size_t size);
+ void *__real__memalign_r(struct _reent *r, size_t alignment, size_t bytes);
+ void *__real__realloc_r(struct _reent *r, void *ptr, size_t size);
+ void __real__free_r(struct _reent *r, void *ptr);
+ void *__real__calloc_r(struct _reent *r, size_t nmemb, size_t size);
+ void *malloc_wrapper(struct _reent *r, size_t size, void *caller);
+ void free_wrapper(struct _reent *r, void *ptr, void *caller);
+}
+
+// TODO: memory tracing doesn't work with uVisor enabled.
+#if !defined(FEATURE_UVISOR)
+
+extern "C" void *__wrap__malloc_r(struct _reent *r, size_t size)
+{
+ return malloc_wrapper(r, size, MBED_CALLER_ADDR());
+}
+
+extern "C" void *malloc_wrapper(struct _reent *r, size_t size, void *caller)
+{
+ void *ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_lock();
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+ malloc_stats_mutex->lock();
+ alloc_info_t *alloc_info = (alloc_info_t *)__real__malloc_r(r, size + sizeof(alloc_info_t));
+ if (alloc_info != NULL) {
+ alloc_info->size = size;
+ ptr = (void *)(alloc_info + 1);
+ heap_stats.current_size += size;
+ heap_stats.total_size += size;
+ heap_stats.alloc_cnt += 1;
+ if (heap_stats.current_size > heap_stats.max_size) {
+ heap_stats.max_size = heap_stats.current_size;
+ }
+ } else {
+ heap_stats.alloc_fail_cnt += 1;
+ }
+ malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ ptr = __real__malloc_r(r, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_malloc(ptr, size, caller);
+ mbed_mem_trace_unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return ptr;
+}
+
+extern "C" void *__wrap__realloc_r(struct _reent *r, void *ptr, size_t size)
+{
+ void *new_ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_lock();
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+ // Implement realloc_r with malloc and free.
+ // The function realloc_r can't be used here directly since
+ // it can call into __wrap__malloc_r (returns ptr + 4) or
+ // resize memory directly (returns ptr + 0).
+
+ // Note - no lock needed since malloc and free are thread safe
+
+ // Get old size
+ uint32_t old_size = 0;
+ if (ptr != NULL) {
+ alloc_info_t *alloc_info = ((alloc_info_t *)ptr) - 1;
+ old_size = alloc_info->size;
+ }
+
+ // Allocate space
+ if (size != 0) {
+ new_ptr = malloc(size);
+ }
+
+ // If the new buffer has been allocated copy the data to it
+ // and free the old buffer
+ if (new_ptr != NULL) {
+ uint32_t copy_size = (old_size < size) ? old_size : size;
+ memcpy(new_ptr, (void *)ptr, copy_size);
+ free(ptr);
+ }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ new_ptr = __real__realloc_r(r, ptr, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+ mbed_mem_trace_unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return new_ptr;
+}
+
+extern "C" void __wrap__free_r(struct _reent *r, void *ptr)
+{
+ free_wrapper(r, ptr, MBED_CALLER_ADDR());
+}
+
+extern "C" void free_wrapper(struct _reent *r, void *ptr, void *caller)
+{
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_lock();
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+ malloc_stats_mutex->lock();
+ alloc_info_t *alloc_info = NULL;
+ if (ptr != NULL) {
+ alloc_info = ((alloc_info_t *)ptr) - 1;
+ heap_stats.current_size -= alloc_info->size;
+ heap_stats.alloc_cnt -= 1;
+ }
+ __real__free_r(r, (void *)alloc_info);
+ malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ __real__free_r(r, ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_free(ptr, caller);
+ mbed_mem_trace_unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+extern "C" void *__wrap__calloc_r(struct _reent *r, size_t nmemb, size_t size)
+{
+ void *ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_lock();
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+ // Note - no lock needed since malloc is thread safe
+
+ ptr = malloc(nmemb * size);
+ if (ptr != NULL) {
+ memset(ptr, 0, nmemb * size);
+ }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ ptr = __real__calloc_r(r, nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+ mbed_mem_trace_unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return ptr;
+}
+
+extern "C" void *__wrap__memalign_r(struct _reent *r, size_t alignment, size_t bytes)
+{
+ return __real__memalign_r(r, alignment, bytes);
+}
+
+#endif // if !defined(FEATURE_UVISOR)
+
+
+/******************************************************************************/
+/* ARMCC / IAR memory allocation wrappers */
+/******************************************************************************/
+
+#elif defined(TOOLCHAIN_ARM) || defined(__ICCARM__)
+
+#if defined(TOOLCHAIN_ARM)
+#define SUPER_MALLOC $Super$$malloc
+#define SUB_MALLOC $Sub$$malloc
+#define SUPER_REALLOC $Super$$realloc
+#define SUB_REALLOC $Sub$$realloc
+#define SUPER_CALLOC $Super$$calloc
+#define SUB_CALLOC $Sub$$calloc
+#define SUPER_FREE $Super$$free
+#define SUB_FREE $Sub$$free
+#elif defined(__ICCARM__)
+#define SUPER_MALLOC $Super$$__iar_dlmalloc
+#define SUB_MALLOC $Sub$$__iar_dlmalloc
+#define SUPER_REALLOC $Super$$__iar_dlrealloc
+#define SUB_REALLOC $Sub$$__iar_dlrealloc
+#define SUPER_CALLOC $Super$$__iar_dlcalloc
+#define SUB_CALLOC $Sub$$__iar_dlcalloc
+#define SUPER_FREE $Super$$__iar_dlfree
+#define SUB_FREE $Sub$$__iar_dlfree
+#endif
+
+/* Enable hooking of memory function only if tracing is also enabled */
+#if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+extern "C" {
+ void *SUPER_MALLOC(size_t size);
+ void *SUPER_REALLOC(void *ptr, size_t size);
+ void *SUPER_CALLOC(size_t nmemb, size_t size);
+ void SUPER_FREE(void *ptr);
+ void *malloc_wrapper(size_t size, void *caller);
+ void free_wrapper(void *ptr, void *caller);
+}
+
+
+extern "C" void *SUB_MALLOC(size_t size)
+{
+ return malloc_wrapper(size, MBED_CALLER_ADDR());
+}
+
+extern "C" void *malloc_wrapper(size_t size, void *caller)
+{
+ void *ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_lock();
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+ malloc_stats_mutex->lock();
+ alloc_info_t *alloc_info = (alloc_info_t *)SUPER_MALLOC(size + sizeof(alloc_info_t));
+ if (alloc_info != NULL) {
+ alloc_info->size = size;
+ ptr = (void *)(alloc_info + 1);
+ heap_stats.current_size += size;
+ heap_stats.total_size += size;
+ heap_stats.alloc_cnt += 1;
+ if (heap_stats.current_size > heap_stats.max_size) {
+ heap_stats.max_size = heap_stats.current_size;
+ }
+ } else {
+ heap_stats.alloc_fail_cnt += 1;
+ }
+ malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ ptr = SUPER_MALLOC(size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_malloc(ptr, size, caller);
+ mbed_mem_trace_unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return ptr;
+}
+
+
+extern "C" void *SUB_REALLOC(void *ptr, size_t size)
+{
+ void *new_ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_lock();
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+ // Note - no lock needed since malloc and free are thread safe
+
+ // Get old size
+ uint32_t old_size = 0;
+ if (ptr != NULL) {
+ alloc_info_t *alloc_info = ((alloc_info_t *)ptr) - 1;
+ old_size = alloc_info->size;
+ }
+
+ // Allocate space
+ if (size != 0) {
+ new_ptr = malloc(size);
+ }
+
+ // If the new buffer has been allocated copy the data to it
+ // and free the old buffer
+ if (new_ptr != NULL) {
+ uint32_t copy_size = (old_size < size) ? old_size : size;
+ memcpy(new_ptr, (void *)ptr, copy_size);
+ free(ptr);
+ }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ new_ptr = SUPER_REALLOC(ptr, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+ mbed_mem_trace_unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return new_ptr;
+}
+
+extern "C" void *SUB_CALLOC(size_t nmemb, size_t size)
+{
+ void *ptr = NULL;
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_lock();
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+ // Note - no lock needed since malloc is thread safe
+ ptr = malloc(nmemb * size);
+ if (ptr != NULL) {
+ memset(ptr, 0, nmemb * size);
+ }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ ptr = SUPER_CALLOC(nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+ mbed_mem_trace_unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return ptr;
+}
+
+extern "C" void SUB_FREE(void *ptr)
+{
+ free_wrapper(ptr, MBED_CALLER_ADDR());
+}
+
+extern "C" void free_wrapper(void *ptr, void *caller)
+{
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_lock();
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+ malloc_stats_mutex->lock();
+ alloc_info_t *alloc_info = NULL;
+ if (ptr != NULL) {
+ alloc_info = ((alloc_info_t *)ptr) - 1;
+ heap_stats.current_size -= alloc_info->size;
+ heap_stats.alloc_cnt -= 1;
+ }
+ SUPER_FREE((void *)alloc_info);
+ malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ SUPER_FREE(ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mbed_mem_trace_free(ptr, caller);
+ mbed_mem_trace_unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+#endif // #if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+/******************************************************************************/
+/* Allocation wrappers for other toolchains are not supported yet */
+/******************************************************************************/
+
+#else
+
+#ifdef MBED_MEM_TRACING_ENABLED
+#error Memory tracing is not supported with the current toolchain.
+#endif
+
+#ifdef MBED_HEAP_STATS_ENABLED
+#error Heap statistics are not supported with the current toolchain.
+#endif
+
+#endif // #if defined(TOOLCHAIN_GCC)
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_application.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_application.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,180 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "platform/mbed_application.h"
+
+#if MBED_APPLICATION_SUPPORT
+
+#if defined(__CORTEX_A9)
+
+static void powerdown_gic(void);
+
+void mbed_start_application(uintptr_t address)
+{
+ __disable_irq();
+ powerdown_gic();
+ __enable_irq();
+ ((void(*)())address)();
+}
+
+static void powerdown_gic()
+{
+ int i;
+ int j;
+
+ for (i = 0; i < 32; i++) {
+ GICDistributor->ICENABLER[i] = 0xFFFFFFFF;
+ GICDistributor->ICPENDR[i] = 0xFFFFFFFF;
+ if (i < 4) {
+ GICDistributor->CPENDSGIR[i] = 0xFFFFFFFF;
+ }
+ for (j = 0; j < 8; j++) {
+ GICDistributor->IPRIORITYR[i*8+j] = 0x00000000;
+ }
+ }
+}
+
+#else
+
+static void powerdown_nvic(void);
+static void powerdown_scb(uint32_t vtor);
+static void start_new_application(void *sp, void *pc);
+
+void mbed_start_application(uintptr_t address)
+{
+ void *sp;
+ void *pc;
+
+ // Interrupts are re-enabled in start_new_application
+ __disable_irq();
+
+ SysTick->CTRL = 0x00000000;
+ powerdown_nvic();
+ powerdown_scb(address);
+
+ sp = *((void **)address + 0);
+ pc = *((void **)address + 1);
+ start_new_application(sp, pc);
+}
+
+static void powerdown_nvic()
+{
+ int isr_groups_32;
+ int i;
+ int j;
+
+#if defined(__CORTEX_M23)
+ // M23 doesn't support ICTR and supports up to 240 external interrupts.
+ isr_groups_32 = 8;
+#else
+ isr_groups_32 = ((SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) >> SCnSCB_ICTR_INTLINESNUM_Pos) + 1;
+#endif
+ for (i = 0; i < isr_groups_32; i++) {
+ NVIC->ICER[i] = 0xFFFFFFFF;
+ NVIC->ICPR[i] = 0xFFFFFFFF;
+ for (j = 0; j < 8; j++) {
+#if defined(__CORTEX_M23)
+ NVIC->IPR[i * 8 + j] = 0x00000000;
+#else
+ NVIC->IP[i * 8 + j] = 0x00000000;
+#endif
+ }
+ }
+}
+
+static void powerdown_scb(uint32_t vtor)
+{
+ int i;
+
+ // SCB->CPUID - Read only CPU ID register
+ SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk;
+ SCB->VTOR = vtor;
+ SCB->AIRCR = 0x05FA | 0x0000;
+ SCB->SCR = 0x00000000;
+ // SCB->CCR - Implementation defined value
+#if defined(__CORTEX_M23)
+ for (i = 0; i < 2; i++) {
+ SCB->SHPR[i] = 0x00;
+ }
+#else
+ for (i = 0; i < 12; i++) {
+#if defined(__CORTEX_M7)
+ SCB->SHPR[i] = 0x00;
+#else
+ SCB->SHP[i] = 0x00;
+#endif
+ }
+#endif
+ SCB->SHCSR = 0x00000000;
+#if defined(__CORTEX_M23)
+#else
+ SCB->CFSR = 0xFFFFFFFF;
+ SCB->HFSR = SCB_HFSR_DEBUGEVT_Msk | SCB_HFSR_FORCED_Msk | SCB_HFSR_VECTTBL_Msk;
+ SCB->DFSR = SCB_DFSR_EXTERNAL_Msk | SCB_DFSR_VCATCH_Msk |
+ SCB_DFSR_DWTTRAP_Msk | SCB_DFSR_BKPT_Msk | SCB_DFSR_HALTED_Msk;
+#endif
+ // SCB->MMFAR - Implementation defined value
+ // SCB->BFAR - Implementation defined value
+ // SCB->AFSR - Implementation defined value
+ // SCB->PFR - Read only processor feature register
+ // SCB->DFR - Read only debug feature registers
+ // SCB->ADR - Read only auxiliary feature registers
+ // SCB->MMFR - Read only memory model feature registers
+ // SCB->ISAR - Read only instruction set attribute registers
+ // SCB->CPACR - Implementation defined value
+}
+
+#if defined (__CC_ARM)
+
+__asm static void start_new_application(void *sp, void *pc)
+{
+ MOV R2, #0
+ MSR CONTROL, R2 // Switch to main stack
+ MOV SP, R0
+ MSR PRIMASK, R2 // Enable interrupts
+ BX R1
+}
+
+#elif defined (__GNUC__) || defined (__ICCARM__)
+
+void start_new_application(void *sp, void *pc)
+{
+ __asm volatile(
+ "movw r2, #0 \n" // Fail to compile "mov r2, #0" with ARMC6. Replace with MOVW.
+ // We needn't "movt r2, #0" immediately following because MOVW
+ // will zero-extend the 16-bit immediate.
+ "msr control, r2 \n" // Switch to main stack
+ "mov sp, %0 \n"
+ "msr primask, r2 \n" // Enable interrupts
+ "bx %1 \n"
+ :
+ : "l"(sp), "l"(pc)
+ : "r2", "cc", "memory"
+ );
+}
+
+#else
+
+#error "Unsupported toolchain"
+
+#endif
+
+#endif
+
+#endif /* MBED_APPLICATION_SUPPORT */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_application.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_application.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_APPLICATION_H
+#define MBED_APPLICATION_H
+
+#include<stdint.h>
+
+#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7)\
+ || defined(__CORTEX_M23) || defined(__CORTEX_A9)
+#define MBED_APPLICATION_SUPPORT 1
+#else
+#define MBED_APPLICATION_SUPPORT 0
+#endif
+
+#if MBED_APPLICATION_SUPPORT
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Start the application at the given address. This function does
+ * not return. It is the applications responsibility for flushing to
+ * or powering down external components such as filesystems or
+ * socket connections before calling this function. For Cortex-M
+ * devices this function powers down generic system components such as
+ * the NVIC and set the vector table to that of the new image followed
+ * by jumping to the reset handler of the new image.
+ *
+ * @param address Starting address of next application to run
+ */
+void mbed_start_application(uintptr_t address);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_assert.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_assert.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,27 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/mbed_assert.h"
+#include "device.h"
+
+#include "platform/mbed_interface.h"
+#include "platform/mbed_critical.h"
+
+void mbed_assert_internal(const char *expr, const char *file, int line)
+{
+ core_util_critical_section_enter();
+ mbed_error_printf("mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
+ mbed_die();
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_assert.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_assert.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,133 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_Assert Assert macros
+ * @{
+ */
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ASSERT_H
+#define MBED_ASSERT_H
+
+#include "mbed_preprocessor.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
+ * This function is active only if NDEBUG is not defined prior to including this
+ * assert header file.
+ * In case of MBED_ASSERT failing condition, error() is called with the assertation message.
+ * @param expr Expresion to be checked.
+ * @param file File where assertation failed.
+ * @param line Failing assertation line number.
+ */
+void mbed_assert_internal(const char *expr, const char *file, int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** MBED_ASSERT
+ * Declare runtime assertions: results in runtime error if condition is false
+ *
+ * @note
+ * Use of MBED_ASSERT is limited to Debug and Develop builds.
+ *
+ * @code
+ *
+ * int Configure(serial_t *obj) {
+ * MBED_ASSERT(obj);
+ * }
+ * @endcode
+ */
+#ifdef NDEBUG
+#define MBED_ASSERT(expr) ((void)0)
+
+#else
+#define MBED_ASSERT(expr) \
+do { \
+ if (!(expr)) { \
+ mbed_assert_internal(#expr, __FILE__, __LINE__); \
+ } \
+} while (0)
+#endif
+
+
+/** MBED_STATIC_ASSERT
+ * Declare compile-time assertions, results in compile-time error if condition is false
+ *
+ * The assertion acts as a declaration that can be placed at file scope, in a
+ * code block (except after a label), or as a member of a C++ class/struct/union.
+ *
+ * @note
+ * Use of MBED_STATIC_ASSERT as a member of a struct/union is limited:
+ * - In C++, MBED_STATIC_ASSERT is valid in class/struct/union scope.
+ * - In C, MBED_STATIC_ASSERT is not valid in struct/union scope, and
+ * MBED_STRUCT_STATIC_ASSERT is provided as an alternative that is valid
+ * in C and C++ class/struct/union scope.
+ *
+ * @code
+ * MBED_STATIC_ASSERT(MBED_LIBRARY_VERSION >= 120,
+ * "The mbed library must be at least version 120");
+ *
+ * int main() {
+ * MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char),
+ * "An int must be larger than a char");
+ * }
+ * @endcode
+ */
+#if defined(__cplusplus) && (__cplusplus >= 201103L || __cpp_static_assert >= 200410L)
+#define MBED_STATIC_ASSERT(expr, msg) static_assert(expr, msg)
+#elif !defined(__cplusplus) && __STDC_VERSION__ >= 201112L
+#define MBED_STATIC_ASSERT(expr, msg) _Static_assert(expr, msg)
+#elif defined(__cplusplus) && defined(__GNUC__) && defined(__GXX_EXPERIMENTAL_CXX0X__) \
+ && (__GNUC__*100 + __GNUC_MINOR__) > 403L
+#define MBED_STATIC_ASSERT(expr, msg) __extension__ static_assert(expr, msg)
+#elif !defined(__cplusplus) && defined(__GNUC__) && !defined(__CC_ARM) \
+ && (__GNUC__*100 + __GNUC_MINOR__) > 406L
+#define MBED_STATIC_ASSERT(expr, msg) __extension__ _Static_assert(expr, msg)
+#elif defined(__ICCARM__)
+#define MBED_STATIC_ASSERT(expr, msg) static_assert(expr, msg)
+#else
+#define MBED_STATIC_ASSERT(expr, msg) \
+ enum {MBED_CONCAT(MBED_ASSERTION_AT_, __LINE__) = sizeof(char[(expr) ? 1 : -1])}
+#endif
+
+/** MBED_STRUCT_STATIC_ASSERT
+ * Declare compile-time assertions, results in compile-time error if condition is false
+ *
+ * Unlike MBED_STATIC_ASSERT, MBED_STRUCT_STATIC_ASSERT can and must be used
+ * as a member of a C/C++ class/struct/union.
+ *
+ * @code
+ * struct thing {
+ * MBED_STATIC_ASSERT(2 + 2 == 4,
+ * "Hopefully the universe is mathematically consistent");
+ * };
+ * @endcode
+ */
+#define MBED_STRUCT_STATIC_ASSERT(expr, msg) int : (expr) ? 0 : -1
+
+
+#endif
+
+/**@}*/
+
+/**@}*/
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_board.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_board.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "hal/gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_interface.h"
+#include "platform/mbed_critical.h"
+#include "hal/serial_api.h"
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#endif
+
+WEAK void mbed_die(void)
+{
+#if !defined (NRF51_H) && !defined(TARGET_EFM32)
+ core_util_critical_section_enter();
+#endif
+ gpio_t led_err;
+ gpio_init_out(&led_err, LED1);
+
+ while (1) {
+ for (int i = 0; i < 4; ++i) {
+ gpio_write(&led_err, 1);
+ wait_ms(150);
+ gpio_write(&led_err, 0);
+ wait_ms(150);
+ }
+
+ for (int i = 0; i < 4; ++i) {
+ gpio_write(&led_err, 1);
+ wait_ms(400);
+ gpio_write(&led_err, 0);
+ wait_ms(400);
+ }
+ }
+}
+
+void mbed_error_printf(const char *format, ...)
+{
+ va_list arg;
+ va_start(arg, format);
+ mbed_error_vfprintf(format, arg);
+ va_end(arg);
+}
+
+void mbed_error_vfprintf(const char *format, va_list arg)
+{
+#if DEVICE_SERIAL
+#define ERROR_BUF_SIZE (128)
+ core_util_critical_section_enter();
+ char buffer[ERROR_BUF_SIZE];
+ int size = vsnprintf(buffer, ERROR_BUF_SIZE, format, arg);
+ if (size > 0) {
+ if (!stdio_uart_inited) {
+ serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+ }
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+ char stdio_out_prev = '\0';
+ for (int i = 0; i < size; i++) {
+ if (buffer[i] == '\n' && stdio_out_prev != '\r') {
+ serial_putc(&stdio_uart, '\r');
+ }
+ serial_putc(&stdio_uart, buffer[i]);
+ stdio_out_prev = buffer[i];
+ }
+#else
+ for (int i = 0; i < size; i++) {
+ serial_putc(&stdio_uart, buffer[i]);
+ }
+#endif
+ }
+ core_util_critical_section_exit();
+#endif
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_critical.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_critical.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,350 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Declare __STDC_LIMIT_MACROS so stdint.h defines UINT32_MAX when using C++ */
+#define __STDC_LIMIT_MACROS
+#include "hal/critical_section_api.h"
+
+#include "cmsis.h"
+#include "platform/mbed_assert.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_toolchain.h"
+
+// if __EXCLUSIVE_ACCESS rtx macro not defined, we need to get this via own-set architecture macros
+#ifndef MBED_EXCLUSIVE_ACCESS
+#ifndef __EXCLUSIVE_ACCESS
+#if ((__ARM_ARCH_7M__ == 1U) || \
+ (__ARM_ARCH_7EM__ == 1U) || \
+ (__ARM_ARCH_8M_BASE__ == 1U) || \
+ (__ARM_ARCH_8M_MAIN__ == 1U)) || \
+ (__ARM_ARCH_7A__ == 1U)
+#define MBED_EXCLUSIVE_ACCESS 1U
+#elif (__ARM_ARCH_6M__ == 1U)
+#define MBED_EXCLUSIVE_ACCESS 0U
+#else
+#error "Unknown architecture for exclusive access"
+#endif
+#else
+#define MBED_EXCLUSIVE_ACCESS __EXCLUSIVE_ACCESS
+#endif
+#endif
+
+static volatile uint32_t critical_section_reentrancy_counter = 0;
+
+bool core_util_are_interrupts_enabled(void)
+{
+#if defined(__CORTEX_A9)
+ return ((__get_CPSR() & 0x80) == 0);
+#else
+ return ((__get_PRIMASK() & 0x1) == 0);
+#endif
+}
+
+bool core_util_is_isr_active(void)
+{
+#if defined(__CORTEX_A9)
+ switch (__get_CPSR() & 0x1FU) {
+ case CPSR_M_USR:
+ case CPSR_M_SYS:
+ return false;
+ case CPSR_M_SVC:
+ default:
+ return true;
+ }
+#else
+ return (__get_IPSR() != 0U);
+#endif
+}
+
+bool core_util_in_critical_section(void)
+{
+ return hal_in_critical_section();
+}
+
+void core_util_critical_section_enter(void)
+{
+// FIXME
+#ifdef FEATURE_UVISOR
+#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
+#else
+ // If the reentrancy counter overflows something has gone badly wrong.
+ MBED_ASSERT(critical_section_reentrancy_counter < UINT32_MAX);
+#endif /* FEATURE_UVISOR */
+
+ hal_critical_section_enter();
+
+ ++critical_section_reentrancy_counter;
+}
+
+void core_util_critical_section_exit(void)
+{
+// FIXME
+#ifdef FEATURE_UVISOR
+#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
+#endif /* FEATURE_UVISOR */
+
+ // If critical_section_enter has not previously been called, do nothing
+ if (critical_section_reentrancy_counter == 0) {
+ return;
+ }
+
+ --critical_section_reentrancy_counter;
+
+ if (critical_section_reentrancy_counter == 0) {
+ hal_critical_section_exit();
+ }
+}
+
+#if MBED_EXCLUSIVE_ACCESS
+
+/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
+#if defined (__CC_ARM)
+#pragma diag_suppress 3731
+#endif
+
+bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+{
+ do {
+ uint8_t currentValue = __LDREXB(ptr);
+ if (currentValue != *expectedCurrentValue) {
+ *expectedCurrentValue = currentValue;
+ __CLREX();
+ return false;
+ }
+ } while (__STREXB(desiredValue, ptr));
+ return true;
+}
+
+bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+{
+ do {
+ uint16_t currentValue = __LDREXH(ptr);
+ if (currentValue != *expectedCurrentValue) {
+ *expectedCurrentValue = currentValue;
+ __CLREX();
+ return false;
+ }
+ } while (__STREXH(desiredValue, ptr));
+ return true;
+}
+
+
+bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+{
+ do {
+ uint32_t currentValue = __LDREXW(ptr);
+ if (currentValue != *expectedCurrentValue) {
+ *expectedCurrentValue = currentValue;
+ __CLREX();
+ return false;
+ }
+ } while (__STREXW(desiredValue, ptr));
+ return true;
+}
+
+uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta)
+{
+ uint8_t newValue;
+ do {
+ newValue = __LDREXB(valuePtr) + delta;
+ } while (__STREXB(newValue, valuePtr));
+ return newValue;
+}
+
+uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta)
+{
+ uint16_t newValue;
+ do {
+ newValue = __LDREXH(valuePtr) + delta;
+ } while (__STREXH(newValue, valuePtr));
+ return newValue;
+}
+
+uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta)
+{
+ uint32_t newValue;
+ do {
+ newValue = __LDREXW(valuePtr) + delta;
+ } while (__STREXW(newValue, valuePtr));
+ return newValue;
+}
+
+
+uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta)
+{
+ uint8_t newValue;
+ do {
+ newValue = __LDREXB(valuePtr) - delta;
+ } while (__STREXB(newValue, valuePtr));
+ return newValue;
+}
+
+uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta)
+{
+ uint16_t newValue;
+ do {
+ newValue = __LDREXH(valuePtr) - delta;
+ } while (__STREXH(newValue, valuePtr));
+ return newValue;
+}
+
+uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta)
+{
+ uint32_t newValue;
+ do {
+ newValue = __LDREXW(valuePtr) - delta;
+ } while (__STREXW(newValue, valuePtr));
+ return newValue;
+}
+
+#else
+
+bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+{
+ bool success;
+ uint8_t currentValue;
+ core_util_critical_section_enter();
+ currentValue = *ptr;
+ if (currentValue == *expectedCurrentValue) {
+ *ptr = desiredValue;
+ success = true;
+ } else {
+ *expectedCurrentValue = currentValue;
+ success = false;
+ }
+ core_util_critical_section_exit();
+ return success;
+}
+
+bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+{
+ bool success;
+ uint16_t currentValue;
+ core_util_critical_section_enter();
+ currentValue = *ptr;
+ if (currentValue == *expectedCurrentValue) {
+ *ptr = desiredValue;
+ success = true;
+ } else {
+ *expectedCurrentValue = currentValue;
+ success = false;
+ }
+ core_util_critical_section_exit();
+ return success;
+}
+
+
+bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+{
+ bool success;
+ uint32_t currentValue;
+ core_util_critical_section_enter();
+ currentValue = *ptr;
+ if (currentValue == *expectedCurrentValue) {
+ *ptr = desiredValue;
+ success = true;
+ } else {
+ *expectedCurrentValue = currentValue;
+ success = false;
+ }
+ core_util_critical_section_exit();
+ return success;
+}
+
+
+uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta)
+{
+ uint8_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr + delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta)
+{
+ uint16_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr + delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta)
+{
+ uint32_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr + delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+
+uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta)
+{
+ uint8_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr - delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta)
+{
+ uint16_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr - delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta)
+{
+ uint32_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr - delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+#endif
+
+
+bool core_util_atomic_cas_ptr(void *volatile *ptr, void **expectedCurrentValue, void *desiredValue)
+{
+ return core_util_atomic_cas_u32(
+ (volatile uint32_t *)ptr,
+ (uint32_t *)expectedCurrentValue,
+ (uint32_t)desiredValue);
+}
+
+void *core_util_atomic_incr_ptr(void *volatile *valuePtr, ptrdiff_t delta)
+{
+ return (void *)core_util_atomic_incr_u32((volatile uint32_t *)valuePtr, (uint32_t)delta);
+}
+
+void *core_util_atomic_decr_ptr(void *volatile *valuePtr, ptrdiff_t delta)
+{
+ return (void *)core_util_atomic_decr_u32((volatile uint32_t *)valuePtr, (uint32_t)delta);
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_critical.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_critical.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,400 @@
+
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_UTIL_CRITICAL_H__
+#define __MBED_UTIL_CRITICAL_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_critical critical section function
+ * @{
+ */
+
+/** Determine the current interrupts enabled state
+ *
+ * This function can be called to determine whether or not interrupts are currently enabled.
+ * @note
+ * NOTE:
+ * This function works for both cortex-A and cortex-M, although the underlyng implementation
+ * differs.
+ * @return true if interrupts are enabled, false otherwise
+ */
+bool core_util_are_interrupts_enabled(void);
+
+/** Determine if this code is executing from an interrupt
+ *
+ * This function can be called to determine if the code is running on interrupt context.
+ * @note
+ * NOTE:
+ * This function works for both cortex-A and cortex-M, although the underlyng implementation
+ * differs.
+ * @return true if in an isr, false otherwise
+ */
+bool core_util_is_isr_active(void);
+
+/** Mark the start of a critical section
+ *
+ * This function should be called to mark the start of a critical section of code.
+ * @note
+ * NOTES:
+ * 1) The use of this style of critical section is targetted at C based implementations.
+ * 2) These critical sections can be nested.
+ * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
+ * section) will be preserved on exit from the section.
+ * 4) This implementation will currently only work on code running in privileged mode.
+ */
+void core_util_critical_section_enter(void);
+
+/** Mark the end of a critical section
+ *
+ * This function should be called to mark the end of a critical section of code.
+ * @note
+ * NOTES:
+ * 1) The use of this style of critical section is targetted at C based implementations.
+ * 2) These critical sections can be nested.
+ * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
+ * section) will be preserved on exit from the section.
+ * 4) This implementation will currently only work on code running in privileged mode.
+ */
+void core_util_critical_section_exit(void);
+
+/**
+ * Determine if we are currently in a critical section
+ *
+ * @return true if in a critical section, false otherwise.
+ */
+bool core_util_in_critical_section(void);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param ptr The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ * expected current value of the data being set atomically.
+ * The computed 'desiredValue' should be a function of this current value.
+ * @note: This is an in-out parameter. In the
+ * failure case of atomic_cas (where the
+ * destination isn't set), the pointee of expectedCurrentValue is
+ * updated with the current value.
+ * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return true if the memory location was atomically
+ * updated with the desired value (after verifying
+ * that it contained the expectedCurrentValue),
+ * false otherwise. In the failure case,
+ * exepctedCurrentValue is updated with the new
+ * value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ * if *p != *old {
+ * *old = *p
+ * return false
+ * }
+ * *p = new
+ * return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is instead updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ * done = false
+ * value = *p // This fetch operation need not be atomic.
+ * while not done {
+ * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ * }
+ * return value + a
+ * }
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
+ */
+bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param ptr The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ * expected current value of the data being set atomically.
+ * The computed 'desiredValue' should be a function of this current value.
+ * @note: This is an in-out parameter. In the
+ * failure case of atomic_cas (where the
+ * destination isn't set), the pointee of expectedCurrentValue is
+ * updated with the current value.
+ * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return true if the memory location was atomically
+ * updated with the desired value (after verifying
+ * that it contained the expectedCurrentValue),
+ * false otherwise. In the failure case,
+ * exepctedCurrentValue is updated with the new
+ * value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ * if *p != *old {
+ * *old = *p
+ * return false
+ * }
+ * *p = new
+ * return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is instead updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ * done = false
+ * value = *p // This fetch operation need not be atomic.
+ * while not done {
+ * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ * }
+ * return value + a
+ * }
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
+ */
+bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param ptr The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ * expected current value of the data being set atomically.
+ * The computed 'desiredValue' should be a function of this current value.
+ * @note: This is an in-out parameter. In the
+ * failure case of atomic_cas (where the
+ * destination isn't set), the pointee of expectedCurrentValue is
+ * updated with the current value.
+ * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return true if the memory location was atomically
+ * updated with the desired value (after verifying
+ * that it contained the expectedCurrentValue),
+ * false otherwise. In the failure case,
+ * exepctedCurrentValue is updated with the new
+ * value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ * if *p != *old {
+ * *old = *p
+ * return false
+ * }
+ * *p = new
+ * return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is instead updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ * done = false
+ * value = *p // This fetch operation need not be atomic.
+ * while not done {
+ * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ * }
+ * return value + a
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
+ * }
+ */
+bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param ptr The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ * expected current value of the data being set atomically.
+ * The computed 'desiredValue' should be a function of this current value.
+ * @note: This is an in-out parameter. In the
+ * failure case of atomic_cas (where the
+ * destination isn't set), the pointee of expectedCurrentValue is
+ * updated with the current value.
+ * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return true if the memory location was atomically
+ * updated with the desired value (after verifying
+ * that it contained the expectedCurrentValue),
+ * false otherwise. In the failure case,
+ * exepctedCurrentValue is updated with the new
+ * value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ * if *p != *old {
+ * *old = *p
+ * return false
+ * }
+ * *p = new
+ * return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is instead updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ * done = false
+ * value = *p // This fetch operation need not be atomic.
+ * while not done {
+ * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ * }
+ * return value + a
+ * }
+ *
+ * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
+ * always succeeds if the current value is expected, as per the pseudocode
+ * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
+ */
+bool core_util_atomic_cas_ptr(void *volatile *ptr, void **expectedCurrentValue, void *desiredValue);
+
+/**
+ * Atomic increment.
+ * @param valuePtr Target memory location being incremented.
+ * @param delta The amount being incremented.
+ * @return The new incremented value.
+ */
+uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta);
+
+/**
+ * Atomic increment.
+ * @param valuePtr Target memory location being incremented.
+ * @param delta The amount being incremented.
+ * @return The new incremented value.
+ */
+uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta);
+
+/**
+ * Atomic increment.
+ * @param valuePtr Target memory location being incremented.
+ * @param delta The amount being incremented.
+ * @return The new incremented value.
+ */
+uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta);
+
+/**
+ * Atomic increment.
+ * @param valuePtr Target memory location being incremented.
+ * @param delta The amount being incremented in bytes.
+ * @return The new incremented value.
+ *
+ * @note The type of the pointer argument is not taken into account
+ * and the pointer is incremented by bytes.
+ */
+void *core_util_atomic_incr_ptr(void *volatile *valuePtr, ptrdiff_t delta);
+
+/**
+ * Atomic decrement.
+ * @param valuePtr Target memory location being decremented.
+ * @param delta The amount being decremented.
+ * @return The new decremented value.
+ */
+uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta);
+
+/**
+ * Atomic decrement.
+ * @param valuePtr Target memory location being decremented.
+ * @param delta The amount being decremented.
+ * @return The new decremented value.
+ */
+uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta);
+
+/**
+ * Atomic decrement.
+ * @param valuePtr Target memory location being decremented.
+ * @param delta The amount being decremented.
+ * @return The new decremented value.
+ */
+uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta);
+
+/**
+ * Atomic decrement.
+ * @param valuePtr Target memory location being decremented.
+ * @param delta The amount being decremented in bytes.
+ * @return The new decremented value.
+ *
+ * @note The type of the pointer argument is not taken into account
+ * and the pointer is decremented by bytes
+ */
+void *core_util_atomic_decr_ptr(void *volatile *valuePtr, ptrdiff_t delta);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+/**@}*/
+
+/**@}*/
+
+#endif // __MBED_UTIL_CRITICAL_H__
+
+
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_debug.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_debug.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,81 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_debug Debug functions
+ * @{
+ */
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...)
+{
+#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+#endif
+}
+
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (== 0) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (!= 0)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...)
+{
+#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
+ if (condition) {
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+ }
+#endif
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**@}*/
+
+/**@}*/
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_error.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_error.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,469 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include "device.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_error_hist.h"
+#include "platform/mbed_interface.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "rtx_os.h"
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+//Helper macro to get the current SP
+#define GET_CURRENT_SP(sp) \
+ { \
+ /*If in Handler mode we are always using MSP*/ \
+ if ( __get_IPSR() != 0U ) { \
+ sp = __get_MSP(); \
+ } else { \
+ /*Look into CONTROL.SPSEL value*/ \
+ if ((__get_CONTROL() & 2U) == 0U) { \
+ sp = __get_MSP();/*Read MSP*/ \
+ } else { \
+ sp = __get_PSP();/*Read PSP*/ \
+ } \
+ } \
+ }
+
+#ifndef NDEBUG
+#define ERROR_REPORT(ctx, error_msg) print_error_report(ctx, error_msg)
+#else
+#define ERROR_REPORT(ctx, error_msg) ((void) 0)
+#endif
+
+static uint8_t error_in_progress = 0;
+static int error_count = 0;
+static mbed_error_ctx first_error_ctx = {0};
+static mbed_error_ctx last_error_ctx = {0};
+static mbed_error_hook_t error_hook = NULL;
+static void print_error_report(mbed_error_ctx *ctx, const char *);
+static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number, void *caller);
+
+//Helper function to halt the system
+static void mbed_halt_system(void)
+{
+ //If not in ISR context exit, otherwise spin on WFI
+ if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
+ for (;;) {
+ __WFI();
+ }
+ } else {
+ //exit eventually calls mbed_die
+ exit(1);
+ }
+}
+
+WEAK void error(const char *format, ...)
+{
+
+ // Prevent recursion if error is called again
+ if (error_in_progress) {
+ return;
+ }
+
+ //Call handle_error/print_error_report permanently setting error_in_progress flag
+ handle_error(MBED_ERROR_UNKNOWN, 0, NULL, 0, MBED_CALLER_ADDR());
+ ERROR_REPORT(&last_error_ctx, "Fatal Run-time error");
+ error_in_progress = 1;
+
+#ifndef NDEBUG
+ va_list arg;
+ va_start(arg, format);
+ mbed_error_vfprintf(format, arg);
+ va_end(arg);
+#endif
+ exit(1);
+}
+
+//Set an error status with the error handling system
+static mbed_error_status_t handle_error(mbed_error_status_t error_status, unsigned int error_value, const char *filename, int line_number, void *caller)
+{
+ mbed_error_ctx current_error_ctx;
+
+ //Error status should always be < 0
+ if (error_status >= 0) {
+ //This is a weird situation, someone called mbed_error with invalid error code.
+ //We will still handle the situation but change the error code to ERROR_INVALID_ARGUMENT, atleast the context will have info on who called it
+ error_status = MBED_ERROR_INVALID_ARGUMENT;
+ }
+
+ //Prevent corruption by holding out other callers
+ //and we also need this until we remove the "error" call completely
+ while (error_in_progress == 1);
+
+ //Use critsect here, as we don't want inadvertant modification of this global variable
+ core_util_critical_section_enter();
+ error_in_progress = 1;
+ core_util_critical_section_exit();
+
+ //Increment error count
+ error_count++;
+
+ //Clear the context capturing buffer
+ memset(¤t_error_ctx, sizeof(mbed_error_ctx), 0);
+ //Capture error information
+ current_error_ctx.error_status = error_status;
+ current_error_ctx.error_address = (uint32_t)caller;
+ current_error_ctx.error_value = error_value;
+#ifdef MBED_CONF_RTOS_PRESENT
+ //Capture thread info
+ osRtxThread_t *current_thread = osRtxInfo.thread.run.curr;
+ current_error_ctx.thread_id = (uint32_t)current_thread;
+ current_error_ctx.thread_entry_address = (uint32_t)current_thread->thread_addr;
+ current_error_ctx.thread_stack_size = current_thread->stack_size;
+ current_error_ctx.thread_stack_mem = (uint32_t)current_thread->stack_mem;
+#ifdef TARGET_CORTEX_M
+ GET_CURRENT_SP(current_error_ctx.thread_current_sp);
+#endif //TARGET_CORTEX_M
+
+#endif //MBED_CONF_RTOS_PRESENT
+
+#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+ //Capture filename/linenumber if provided
+ //Index for tracking error_filename
+ memset(¤t_error_ctx.error_filename, 0, MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN);
+ strncpy(current_error_ctx.error_filename, filename, MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN);
+ current_error_ctx.error_line_number = line_number;
+#endif
+
+ //Capture the fist system error and store it
+ if (error_count == 1) { //first error
+ memcpy(&first_error_ctx, ¤t_error_ctx, sizeof(mbed_error_ctx));
+ }
+
+ //copy this error to last error
+ memcpy(&last_error_ctx, ¤t_error_ctx, sizeof(mbed_error_ctx));
+
+#if MBED_CONF_PLATFORM_ERROR_HIST_ENABLED
+ //Log the error with error log
+ mbed_error_hist_put(¤t_error_ctx);
+#endif
+
+ //Call the error hook if available
+ if (error_hook != NULL) {
+ error_hook(&last_error_ctx);
+ }
+
+ error_in_progress = 0;
+
+ return MBED_SUCCESS;
+}
+
+//Return the first error
+mbed_error_status_t mbed_get_first_error(void)
+{
+ //return the first error recorded
+ return first_error_ctx.error_status;
+}
+
+//Return the last error
+mbed_error_status_t mbed_get_last_error(void)
+{
+ //return the last error recorded
+ return last_error_ctx.error_status;
+}
+
+//Gets the current error count
+int mbed_get_error_count(void)
+{
+ //return the current error count
+ return error_count;
+}
+
+//Sets a fatal error
+mbed_error_status_t mbed_warning(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number)
+{
+ return handle_error(error_status, error_value, filename, line_number, MBED_CALLER_ADDR());
+}
+
+//Sets a fatal error, this function is marked WEAK to be able to override this for some tests
+WEAK mbed_error_status_t mbed_error(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number)
+{
+ //set the error reported and then halt the system
+ if (MBED_SUCCESS != handle_error(error_status, error_value, filename, line_number, MBED_CALLER_ADDR())) {
+ return MBED_ERROR_FAILED_OPERATION;
+ }
+
+ //On fatal errors print the error context/report
+ ERROR_REPORT(&last_error_ctx, error_msg);
+ mbed_halt_system();
+
+ return MBED_ERROR_FAILED_OPERATION;
+}
+
+//Register an application defined callback with error handling
+mbed_error_status_t mbed_set_error_hook(mbed_error_hook_t error_hook_in)
+{
+ //register the new hook/callback
+ if (error_hook_in != NULL) {
+ error_hook = error_hook_in;
+ return MBED_SUCCESS;
+ }
+
+ return MBED_ERROR_INVALID_ARGUMENT;
+}
+
+//Retrieve the first error context from error log
+mbed_error_status_t mbed_get_first_error_info(mbed_error_ctx *error_info)
+{
+ memcpy(error_info, &first_error_ctx, sizeof(first_error_ctx));
+ return MBED_SUCCESS;
+}
+
+//Retrieve the last error context from error log
+mbed_error_status_t mbed_get_last_error_info(mbed_error_ctx *error_info)
+{
+ memcpy(error_info, &last_error_ctx, sizeof(mbed_error_ctx));
+ return MBED_SUCCESS;
+}
+
+//Makes an mbed_error_status_t value
+mbed_error_status_t mbed_make_error(mbed_error_type_t error_type, mbed_module_type_t entity, mbed_error_code_t error_code)
+{
+ switch (error_type) {
+ case MBED_ERROR_TYPE_POSIX:
+ if (error_code >= MBED_POSIX_ERROR_BASE && error_code <= MBED_SYSTEM_ERROR_BASE) {
+ return -error_code;
+ }
+ break;
+
+ case MBED_ERROR_TYPE_SYSTEM:
+ if (error_code >= MBED_SYSTEM_ERROR_BASE && error_code <= MBED_CUSTOM_ERROR_BASE) {
+ return MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, entity, error_code);
+ }
+ break;
+
+ case MBED_ERROR_TYPE_CUSTOM:
+ if (error_code >= MBED_CUSTOM_ERROR_BASE) {
+ return MAKE_MBED_ERROR(MBED_ERROR_TYPE_CUSTOM, entity, error_code);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ //If we are passed incorrect values return a generic system error
+ return MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, MBED_MODULE_UNKNOWN, MBED_ERROR_CODE_UNKNOWN);
+}
+
+/**
+ * Clears all the last error, error count and all entries in the error log.
+ * @return 0 or MBED_SUCCESS on success.
+ *
+ */
+mbed_error_status_t mbed_clear_all_errors(void)
+{
+ mbed_error_status_t status = MBED_SUCCESS;
+
+ //Make sure we dont multiple clients resetting
+ core_util_critical_section_enter();
+ //Clear the error and context capturing buffer
+ memset(&last_error_ctx, sizeof(mbed_error_ctx), 0);
+ //reset error count to 0
+ error_count = 0;
+#if MBED_CONF_PLATFORM_ERROR_HIST_ENABLED
+ status = mbed_error_hist_reset();
+#endif
+ core_util_critical_section_exit();
+
+ return status;
+}
+
+#if MBED_CONF_PLATFORM_ERROR_ALL_THREADS_INFO && defined(MBED_CONF_RTOS_PRESENT)
+/* Prints info of a thread(using osRtxThread_t struct)*/
+static void print_thread(osRtxThread_t *thread)
+{
+ mbed_error_printf("\nState: 0x%08X Entry: 0x%08X Stack Size: 0x%08X Mem: 0x%08X SP: 0x%08X", thread->state, thread->thread_addr, thread->stack_size, (uint32_t)thread->stack_mem, thread->sp);
+}
+
+/* Prints thread info from a list */
+static void print_threads_info(osRtxThread_t *threads)
+{
+ while (threads != NULL) {
+ print_thread(threads);
+ threads = threads->thread_next;
+ }
+}
+#endif
+
+#ifndef NDEBUG
+static void print_error_report(mbed_error_ctx *ctx, const char *error_msg)
+{
+ uint32_t error_code = MBED_GET_ERROR_CODE(ctx->error_status);
+ uint32_t error_module = MBED_GET_ERROR_MODULE(ctx->error_status);
+
+ mbed_error_printf("\n\n++ MbedOS Error Info ++\nError Status: 0x%X Code: %d Module: %d\nError Message: ", ctx->error_status, error_code, error_module);
+
+ switch (error_code) {
+ //These are errors reported by kernel handled from mbed_rtx_handlers
+ case MBED_ERROR_CODE_RTOS_EVENT:
+ mbed_error_printf("Kernel Error: 0x%X, ", ctx->error_value);
+ break;
+
+ case MBED_ERROR_CODE_RTOS_THREAD_EVENT:
+ mbed_error_printf("Thread: 0x%X, ", ctx->error_value);
+ break;
+
+ case MBED_ERROR_CODE_RTOS_MUTEX_EVENT:
+ mbed_error_printf("Mutex: 0x%X, ", ctx->error_value);
+ break;
+
+ case MBED_ERROR_CODE_RTOS_SEMAPHORE_EVENT:
+ mbed_error_printf("Semaphore: 0x%X, ", ctx->error_value);
+ break;
+
+ case MBED_ERROR_CODE_RTOS_MEMORY_POOL_EVENT:
+ mbed_error_printf("MemoryPool: 0x%X, ", ctx->error_value);
+ break;
+
+ case MBED_ERROR_CODE_RTOS_EVENT_FLAGS_EVENT:
+ mbed_error_printf("EventFlags: 0x%X, ", ctx->error_value);
+ break;
+
+ case MBED_ERROR_CODE_RTOS_TIMER_EVENT:
+ mbed_error_printf("Timer: 0x%X, ", ctx->error_value);
+ break;
+
+ case MBED_ERROR_CODE_RTOS_MESSAGE_QUEUE_EVENT:
+ mbed_error_printf("MessageQueue: 0x%X, ", ctx->error_value);
+ break;
+
+ default:
+ //Nothing to do here, just print the error info down
+ break;
+ }
+ mbed_error_printf(error_msg);
+ mbed_error_printf("\nLocation: 0x%X", ctx->error_address);
+
+#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED && !defined(NDEBUG)
+ if ((NULL != ctx->error_filename[0]) && (ctx->error_line_number != 0)) {
+ //for string, we must pass address of a ptr which has the address of the string
+ mbed_error_printf("\nFile:%s+%d", ctx->error_filename, ctx->error_line_number);
+ }
+#endif
+
+ mbed_error_printf("\nError Value: 0x%X", ctx->error_value);
+#ifdef TARGET_CORTEX_M
+ mbed_error_printf("\nCurrent Thread: Id: 0x%X Entry: 0x%X StackSize: 0x%X StackMem: 0x%X SP: 0x%X ",
+ ctx->thread_id, ctx->thread_entry_address, ctx->thread_stack_size, ctx->thread_stack_mem, ctx->thread_current_sp);
+#else
+ //For Cortex-A targets we dont have support to capture the current SP
+ mbed_error_printf("\nCurrent Thread: Id: 0x%X Entry: 0x%X StackSize: 0x%X StackMem: 0x%X ",
+ ctx->thread_id, ctx->thread_entry_address, ctx->thread_stack_size, ctx->thread_stack_mem);
+#endif //TARGET_CORTEX_M
+
+#if MBED_CONF_PLATFORM_ERROR_ALL_THREADS_INFO && defined(MBED_CONF_RTOS_PRESENT)
+ mbed_error_printf("\nNext:");
+ print_thread(osRtxInfo.thread.run.next);
+
+ mbed_error_printf("\nWait:");
+ osRtxThread_t *threads = (osRtxThread_t *)&osRtxInfo.thread.wait_list;
+ print_threads_info(threads);
+
+ mbed_error_printf("\nDelay:");
+ threads = (osRtxThread_t *)&osRtxInfo.thread.delay_list;
+ print_threads_info(threads);
+
+ mbed_error_printf("\nIdle:");
+ threads = (osRtxThread_t *)&osRtxInfo.thread.idle;
+ print_threads_info(threads);
+#endif
+
+ mbed_error_printf("\n-- MbedOS Error Info --\n");
+}
+#endif //ifndef NDEBUG
+
+#if MBED_CONF_PLATFORM_ERROR_HIST_ENABLED
+//Retrieve the error context from error log at the specified index
+mbed_error_status_t mbed_get_error_hist_info(int index, mbed_error_ctx *error_info)
+{
+ return mbed_error_hist_get(index, error_info);
+}
+
+//Retrieve the error log count
+int mbed_get_error_hist_count(void)
+{
+ return mbed_error_hist_get_count();
+}
+
+mbed_error_status_t mbed_save_error_hist(const char *path)
+{
+ mbed_error_status_t ret = MBED_SUCCESS;
+ mbed_error_ctx ctx = {0};
+ int log_count = mbed_error_hist_get_count();
+ FILE *error_log_file = NULL;
+
+ //Ensure path is valid
+ if (path == NULL) {
+ ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_INVALID_ARGUMENT);
+ goto exit;
+ }
+
+ //Open the file for saving the error log info
+ if ((error_log_file = fopen(path, "w")) == NULL) {
+ ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OPEN_FAILED);
+ goto exit;
+ }
+
+ //First store the first and last errors
+ if (fprintf(error_log_file, "\nFirst Error: Status:0x%x ThreadId:0x%x Address:0x%x Value:0x%x\n",
+ (unsigned int)first_error_ctx.error_status,
+ (unsigned int)first_error_ctx.thread_id,
+ (unsigned int)first_error_ctx.error_address,
+ (unsigned int)first_error_ctx.error_value) <= 0) {
+ ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_WRITE_FAILED);
+ goto exit;
+ }
+
+ if (fprintf(error_log_file, "\nLast Error: Status:0x%x ThreadId:0x%x Address:0x%x Value:0x%x\n",
+ (unsigned int)last_error_ctx.error_status,
+ (unsigned int)last_error_ctx.thread_id,
+ (unsigned int)last_error_ctx.error_address,
+ (unsigned int)last_error_ctx.error_value) <= 0) {
+ ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_WRITE_FAILED);
+ goto exit;
+ }
+
+ //Update with error log info
+ while (--log_count >= 0) {
+ mbed_error_hist_get(log_count, &ctx);
+ //first line of file will be error log count
+ if (fprintf(error_log_file, "\n%d: Status:0x%x ThreadId:0x%x Address:0x%x Value:0x%x\n",
+ log_count,
+ (unsigned int)ctx.error_status,
+ (unsigned int)ctx.thread_id,
+ (unsigned int)ctx.error_address,
+ (unsigned int)ctx.error_value) <= 0) {
+ ret = MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_WRITE_FAILED);
+ goto exit;
+ }
+ }
+
+exit:
+ fclose(error_log_file);
+
+ return ret;
+}
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_error.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_error.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1087 @@
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_error Error functions
+ * @{
+ */
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_H
+#define MBED_ERROR_H
+
+#include "platform/mbed_retarget.h"
+#include "platform/mbed_toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Define this macro to include filenames in error context. For release builds, do not include filename to save memory.
+ * MBED_PLATFORM_CONF_ERROR_FILENAME_CAPTURE_ENABLED
+ */
+
+/** Define this macro to enable error history
+ * MBED_PLATFORM_CONF_ERROR_HIST_ENABLED
+ */
+
+#ifndef MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN
+#define MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN 16
+#else //MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN
+#if MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN > 64
+//We have to limit this to 64 bytes since we use mbed_error_printf for error reporting
+//and mbed_error_vfprintf uses 128bytes internal buffer which may not be sufficient for anything
+//longer that 64 bytes with the current implementation.
+#error "Unsupported error filename buffer length detected, max supported length is 64 chars. Please change MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN or max-error-filename-len in configuration."
+#endif
+#endif
+
+#define MBED_ERROR_STATUS_CODE_MASK (0x0000FFFF)
+#define MBED_ERROR_STATUS_CODE_POS (0)
+#define MBED_ERROR_STATUS_CODE_FIELD_SIZE (16)
+
+#define MBED_ERROR_STATUS_MODULE_MASK (0x00FF0000)
+#define MBED_ERROR_STATUS_MODULE_POS (16)
+#define MBED_ERROR_STATUS_MODULE_FIELD_SIZE (8)
+
+#define MBED_ERROR_STATUS_TYPE_MASK (0x60000000)
+#define MBED_ERROR_STATUS_TYPE_POS (29)
+#define MBED_ERROR_STATUS_TYPE_FIELD_SIZE (2)
+
+/* mbed_error_status_t Status Encoding */
+//|31(1 bit) Always Negative|30-29(2 bits) |28-24 | 23-16(8 bits) | 15-0(16 bits) |
+//|-1 |TYPE |(unused/reserved) | MODULE TYPE | ERROR CODE |
+
+#define MAKE_MBED_ERROR(type, module, error_code) (mbed_error_status_t) \
+ ((0x80000000) | \
+ (MBED_ERROR_STATUS_CODE_MASK & (error_code << MBED_ERROR_STATUS_CODE_POS)) | \
+ (MBED_ERROR_STATUS_MODULE_MASK & (module << MBED_ERROR_STATUS_MODULE_POS)) | \
+ (MBED_ERROR_STATUS_TYPE_MASK & (type << MBED_ERROR_STATUS_TYPE_POS)))
+
+#define MBED_GET_ERROR_TYPE( error_status ) ((error_status & MBED_ERROR_STATUS_TYPE_MASK) >> MBED_ERROR_STATUS_TYPE_POS)
+#define MBED_GET_ERROR_MODULE( error_status ) ((error_status & MBED_ERROR_STATUS_MODULE_MASK) >> MBED_ERROR_STATUS_MODULE_POS)
+#define MBED_GET_ERROR_CODE( error_status ) (int)((MBED_GET_ERROR_TYPE( error_status ) == MBED_ERROR_TYPE_POSIX)?(-error_status):((error_status & MBED_ERROR_STATUS_CODE_MASK) >> MBED_ERROR_STATUS_CODE_POS))
+
+/** mbed_error_status_t description
+ *
+ * mbed_error_status_t type represents the error status values under MbedOS. mbed_error_status_t values are signed integers and always be negative.\n
+ * Internally its encoded as below with bit-fields representing error type, module and error code:\n\n
+ * mbed_error_status_t Status Encoding:\n
+ *
+ \verbatim
+ | 31 Always Negative | 30-29(2 bits) | 28-24 | 23-16(8 bits) | 15-0(16 bits) |
+ | -1 | TYPE | (unused/reserved) | MODULE TYPE | ERROR CODE |
+ \endverbatim
+ *
+ * The error status value range for each error type is as follows:\n
+ * Posix Error Status-es - 0xFFFFFFFF to 0xFFFFFF01(-1 -255) - This corresponds to Posix error codes represented as negative.\n
+ * System Error Status-es - 0x80XX0100 to 0x80XX0FFF - This corresponds to System error codes range(all values are negative). Bits 23-16 will be module type(marked with XX)\n
+ * Custom Error Status-es - 0xA0XX1000 to 0xA0XXFFFF - This corresponds to Custom error codes range(all values are negative). Bits 23-16 will be module type(marked with XX)\n\n
+ *
+ * The ERROR CODE(values encoded into ERROR CODE bit-field in mbed_error_status_t) value range for each error type is also seperated as below:\n
+ * Posix Error Codes - 1 to 255.\n
+ * System Error Codes - 256 to 4095.\n
+ * Custom Error Codes - 4096 to 65535.\n
+ *
+ * @note Posix error codes are always encoded as negative of their actual value. For example, EPERM is encoded as -EPERM.
+ * And, the MODULE TYPE for Posix error codes are always encoded as MBED_MODULE_UNKNOWN.\n
+ * This is to enable easy injection of Posix error codes into MbedOS error handling system without altering the actual Posix error values.\n
+ * Accordingly, Posix error codes are represented as -1 to -255 under MbedOS error status representation.
+ */
+typedef int mbed_error_status_t;
+
+/**
+ * Macro for defining a Posix error status. This macro is mainly used to define Posix error values in mbed_error_code_t enumeration.
+ * @param error_name Name of the error without the ERROR_ prefix
+ * @param error_code Error code value to be used, must be between 1 and 255(inclusive).
+ *
+ */
+#define MBED_DEFINE_POSIX_ERROR( error_name, error_code ) \
+ MBED_ERROR_CODE_##error_name = error_code, \
+ MBED_ERROR_##error_name = -(MBED_POSIX_ERROR_BASE + error_code)
+
+/**
+ * Macro for defining a System error status. This macro is used to define System error values in mbed_error_code_t enumeration.
+ * @param error_name Name of the error without the ERROR_ prefix
+ * @param error_code Error code value to be used, must be between 256 and 4096(inclusive).
+ *
+ */
+#define MBED_DEFINE_SYSTEM_ERROR( error_name, error_code ) \
+ MBED_ERROR_CODE_##error_name = MBED_SYSTEM_ERROR_BASE + error_code, \
+ MBED_ERROR_##error_name = MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, MBED_MODULE_UNKNOWN, MBED_ERROR_CODE_##error_name)
+
+/**
+ * Macro for defining a Custom error status. This macro is used to define custom error values in mbed_error_code_t enumeration.
+ * @param error_name Name of the error without the ERROR_ prefix
+ * @param error_code Error code value to be used, must be between 4097 and 65535(inclusive).
+ *
+ */
+#define MBED_DEFINE_CUSTOM_ERROR( error_name, error_code ) \
+ MBED_ERROR_CODE_##error_name = MBED_CUSTOM_ERROR_BASE + error_code, \
+ MBED_ERROR_##error_name = MAKE_MBED_ERROR(MBED_ERROR_TYPE_CUSTOM, MBED_MODULE_UNKNOWN, MBED_ERROR_CODE_##error_name)
+
+
+/**
+ * Macros for setting a system warning. These macros will log the error, Its a wrapper for calling mbed_warning API.
+ * There are 2 versions of this macro. MBED_WARNING takes status and message. MBED_WARNING1 takes an additional context specific argument
+ * @param error_status mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @param error_msg The error message to be printed out to STDIO/Serial.
+ * @param error_value Value associated with the error status. This would depend on error code/error scenario.
+ *
+ * @code
+ *
+ * MBED_WARNING( ERROR_INVALID_SIZE, "MyDriver: Invalid size in read" )
+ * MBED_WARNING1( ERROR_INVALID_SIZE, "MyDriver: Invalid size in read", size_val )
+ *
+ * @endcode
+ * @note The macro calls mbed_warning API with filename and line number info without caller explicitly passing them.
+ * Since this macro is a wrapper for mbed_warning API callers should process the return value from this macro which is the return value from calling mbed_error API.
+ *
+ */
+#ifdef NDEBUG
+#define MBED_WARNING1( error_status, error_msg, error_value ) mbed_warning( error_status, (const char *)NULL, (uint32_t)error_value, NULL, 0 )
+#define MBED_WARNING( error_status, error_msg ) mbed_warning( error_status, (const char *)NULL, (uint32_t)0, NULL, 0 )
+#else //NDEBUG
+#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+#define MBED_WARNING1( error_status, error_msg, error_value ) mbed_warning( error_status, (const char *)error_msg, (uint32_t)error_value, (const char *)MBED_FILENAME, __LINE__ )
+#define MBED_WARNING( error_status, error_msg ) mbed_warning( error_status, (const char *)error_msg, (uint32_t)0 , (const char *)MBED_FILENAME, __LINE__ )
+#else //MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+#define MBED_WARNING1( error_status, error_msg, error_value ) mbed_warning( error_status, (const char *)error_msg, (uint32_t)error_value, NULL, 0 )
+#define MBED_WARNING( error_status, error_msg ) mbed_warning( error_status, (const char *)error_msg, (uint32_t)0, NULL, 0 )
+#endif
+#endif
+
+/**
+ * Macros for setting a fatal system error. These macros will log the error, prints the error report and halts the system. Its a wrapper for calling mbed_error API.
+ * There are 2 versions of this macro. MBED_ERROR takes status and message. MBED_ERROR1 takes an additional context specific argument
+ * @param error_status mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @param error_msg The error message to be printed out to STDIO/Serial.
+ * @param error_value Value associated with the error status. This would depend on error code/error scenario. Only available with MBED_ERROR1
+ * @return 0 or MBED_SUCCESS.
+ * MBED_ERROR_INVALID_ARGUMENT if called with invalid error status/codes
+ *
+ * @code
+ *
+ * MBED_ERROR( MBED_ERROR_MUTEX_LOCK_FAILED, "MyDriver: Can't lock driver Mutex" )
+ * MBED_ERROR1( MBED_ERROR_MUTEX_LOCK_FAILED, "MyDriver: Can't lock driver Mutex", &my_mutex )
+ *
+ * @endcode
+ * @note The macro calls mbed_error API with filename and line number info without caller explicitly passing them.
+ * Since this macro is a wrapper for mbed_error API callers should process the return value from this macro which is the return value from calling mbed_error API.
+ *
+ */
+#ifdef NDEBUG
+#define MBED_ERROR1( error_status, error_msg, error_value ) mbed_error( error_status, (const char *)NULL, (uint32_t)error_value, NULL, 0 )
+#define MBED_ERROR( error_status, error_msg ) mbed_error( error_status, (const char *)NULL, (uint32_t)0 , NULL, 0 )
+#else //NDEBUG
+#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+#define MBED_ERROR1( error_status, error_msg, error_value ) mbed_error( error_status, (const char *)error_msg, (uint32_t)error_value, (const char *)MBED_FILENAME, __LINE__ )
+#define MBED_ERROR( error_status, error_msg ) mbed_error( error_status, (const char *)error_msg, (uint32_t)0 , (const char *)MBED_FILENAME, __LINE__ )
+#else //MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
+#define MBED_ERROR1( error_status, error_msg, error_value ) mbed_error( error_status, (const char *)error_msg, (uint32_t)error_value, NULL, 0 )
+#define MBED_ERROR( error_status, error_msg ) mbed_error( error_status, (const char *)error_msg, (uint32_t)0 , NULL, 0 )
+#endif
+#endif
+
+//Error Type definition
+/** mbed_error_type_t definition
+ * @note
+ * This enumeration defines the Error types supported. The value of these enum values will be encoded into mbed_error_status_t TYPE field.\n
+ * See mbed_error_status_t description for more info.\n
+ * MBED_ERROR_TYPE_SYSTEM - Used to indicate that the error status is of System defined Error type.\n
+ * MBED_ERROR_TYPE_CUSTOM - Used to indicate that the error status is of Custom defined Error type.\n
+ * MBED_ERROR_TYPE_POSIX - Used to indicate that the error status is of Posix error type.\n
+ *
+ */
+typedef enum _mbed_error_type_t {
+ MBED_ERROR_TYPE_SYSTEM = 0,
+ MBED_ERROR_TYPE_CUSTOM = 1,
+ //2 is reserved
+ //Use 3 for POSIX because we are mapping -1 to -255 to POSIX error codes
+ //and thus we must use 3 to match the type bits in error status representation which are from 0xFFFFFFFF to 0xFFFFFF00
+ MBED_ERROR_TYPE_POSIX = 3
+} mbed_error_type_t;
+
+//Module type/id definitions
+/** mbed_module_type_t definition
+ * @note
+ * This enumeration defines the module types. The value of these enum values will be encoded into mbed_error_status_t MODULE field.\n\n
+ * See mbed_error_status_t description for more info.\n
+ * MBED_MODULE_UNKNOWN - This module type can be used if caller of the mbed_error/mbed_warning doesn't know who is the actual originator of the error.\n
+ * Other module values can be used to provide more info on who/where the error originated from.\n\n
+ * For example, if I2C driver is the component originating the error you can use MBED_MODULE_DRIVER_I2C to provide more info.\n
+ * Its used in call to MBED_MAKE_ERROR/MBED_MAKE_SYSTEM_ERROR/MBED_MAKE_CUSTOM_ERROR macros.\n
+ *
+ * @code
+ * Example: mbed_error_status_t i2c_driver_error = MBED_MAKE_ERROR( MBED_MODULE_DRIVER_I2C, MBED_ERROR_CONFIG_UNSUPPORTED );
+ * @endcode
+ *
+ * @note
+ * \n Below are the module code mappings:\n
+ \verbatim
+ MBED_MODULE_APPLICATION 0 Application
+ MBED_MODULE_PLATFORM 1 Platform
+ MODULE_KERNEL 2 RTX Kernel
+ MBED_MODULE_NETWORK_STACK 3 Network stack
+ MBED_MODULE_HAL 4 HAL - Hardware Abstraction Layer
+ MBED_MODULE_NETWORK_STACKMODULE_MEMORY_SUBSYSTEM 5 Memory Subsystem
+ MBED_MODULE_FILESYSTEM 6 Filesystem
+ MBED_MODULE_BLOCK_DEVICE 7 Block device
+ MBED_MODULE_DRIVER 8 Driver
+ MBED_MODULE_DRIVER_SERIAL 9 Serial Driver
+ MBED_MODULE_DRIVER_RTC 10 RTC Driver
+ MBED_MODULE_DRIVER_I2C 11 I2C Driver
+ MODULE_DRIVER_SPI 12 SPI Driver
+ MODULE_DRIVER_GPIO 13 GPIO Driver
+ MODULE_DRIVER_ANALOG 14 Analog Driver
+ MODULE_DRIVER_DIGITAL 15 DigitalIO Driver
+ MODULE_DRIVER_CAN 16 CAN Driver
+ MODULE_DRIVER_ETHERNET 17 Ethernet Driver
+ MODULE_DRIVER_CRC 18 CRC Module
+ MODULE_DRIVER_PWM 19 PWM Driver
+ MODULE_DRIVER_QSPI 20 QSPI Driver
+ MODULE_DRIVER_USB 21 USB Driver
+ MODULE_TARGET_SDK 22 SDK
+
+ MBED_MODULE_UNKNOWN 255 Unknown module
+ \endverbatim
+ *
+ */
+typedef enum _mbed_module_type {
+ MBED_MODULE_APPLICATION = 0,
+ MBED_MODULE_PLATFORM,
+ MBED_MODULE_KERNEL,
+ MBED_MODULE_NETWORK_STACK,
+ MBED_MODULE_HAL,
+ MBED_MODULE_NETWORK_STACKMODULE_MEMORY_SUBSYSTEM,
+ MBED_MODULE_FILESYSTEM,
+ MBED_MODULE_BLOCK_DEVICE,
+ MBED_MODULE_DRIVER,
+ MBED_MODULE_DRIVER_SERIAL,
+ MBED_MODULE_DRIVER_RTC,
+ MBED_MODULE_DRIVER_I2C,
+ MBED_MODULE_DRIVER_SPI,
+ MBED_MODULE_DRIVER_GPIO,
+ MBED_MODULE_DRIVER_ANALOG,
+ MBED_MODULE_DRIVER_DIGITAL,
+ MBED_MODULE_DRIVER_CAN,
+ MBED_MODULE_DRIVER_ETHERNET,
+ MBED_MODULE_DRIVER_CRC,
+ MBED_MODULE_DRIVER_PWM,
+ MBED_MODULE_DRIVER_QSPI,
+ MBED_MODULE_DRIVER_USB,
+ MBED_MODULE_TARGET_SDK,
+ /* Add More entities here as required */
+
+ MBED_MODULE_UNKNOWN = 255,
+ MBED_MODULE_MAX = MBED_MODULE_UNKNOWN
+} mbed_module_type_t;
+
+//Use MBED_SUCCESS(=0) or any postive number for successful returns
+#define MBED_SUCCESS 0
+
+#define MBED_POSIX_ERROR_BASE 0
+#define MBED_SYSTEM_ERROR_BASE 256
+#define MBED_CUSTOM_ERROR_BASE 4096
+
+//Error Code definitions
+/** mbed_error_code_t definition
+ *
+ * mbed_error_code_t enumeration defines the Error codes and Error status values for MBED_MODULE_UNKNOWN.\n
+ * It defines all of Posix Error Codes/Statuses and Mbed System Error Codes/Statuses.\n\n
+ *
+ * @note
+ * Posix Error codes are defined using the macro MBED_DEFINE_POSIX_ERROR\n
+ * For example MBED_DEFINE_POSIX_ERROR( EPERM, EPERM ). This effectively defines the following values:\n
+ * ERROR_CODE_EPERM = EPERM\n
+ * ERROR_EPERM = -EPERM\n
+ *
+ * Posix Error codes are defined using the macro MBED_DEFINE_POSIX_ERROR\n
+ * For example MBED_DEFINE_POSIX_ERROR( EPERM, EPERM ). This macro defines the following values:\n
+ * ERROR_CODE_EPERM = MBED_POSIX_ERROR_BASE+EPERM\n
+ * ERROR_EPERM = -(MBED_POSIX_ERROR_BASE+EPERM)\n
+ * Its effectively equivalent to:\n
+ * ERROR_CODE_EPERM = 1\n
+ * ERROR_EPERM = -1\n
+ * All Posix error codes currently supported by MbedOS(defined in mbed_retarget.h) are defined using the MBED_DEFINE_POSIX_ERROR macro.\n\n
+ * Below are the Posic error codes and the description:\n
+ * \verbatim
+ EPERM 1 Operation not permitted
+ ENOENT 2 No such file or directory
+ ESRCH 3 No such process
+ EINTR 4 Interrupted system call
+ EIO 5 I/O error
+ ENXIO 6 No such device or address
+ E2BIG 7 Argument list too long
+ ENOEXEC 8 Exec format error
+ EBADF 9 Bad file number
+ ECHILD 10 No child processes
+ EAGAIN 11 Try again
+ ENOMEM 12 Out of memory
+ EACCES 13 Permission denied
+ EFAULT 14 Bad address
+ ENOTBLK 15 Block device required
+ EBUSY 16 Device or resource busy
+ EEXIST 17 File exists
+ EXDEV 18 Cross-device link
+ ENODEV 19 No such device
+ ENOTDIR 20 Not a directory
+ EISDIR 21 Is a directory
+ EINVAL 22 Invalid argument
+ ENFILE 23 File table overflow
+ EMFILE 24 Too many open files
+ ENOTTY 25 Not a typewriter
+ ETXTBSY 26 Text file busy
+ EFBIG 27 File too large
+ ENOSPC 28 No space left on device
+ ESPIPE 29 Illegal seek
+ EROFS 30 Read-only file system
+ EMLINK 31 Too many links
+ EPIPE 32 Broken pipe
+ EDOM 33 Math argument out of domain of func
+ ERANGE 34 Math result not representable
+ EDEADLK 35 Resource deadlock would occur
+ ENAMETOOLONG 36 File name too long
+ ENOLCK 37 No record locks available
+ ENOSYS 38 Function not implemented
+ ENOTEMPTY 39 Directory not empty
+ ELOOP 40 Too many symbolic links encountered
+ EWOULDBLOCK EAGAIN Operation would block
+ ENOMSG 42 No message of desired type
+ EIDRM 43 Identifier removed
+ ECHRNG 44 Channel number out of range
+ EL2NSYNC 45 Level 2 not synchronized
+ EL3HLT 46 Level 3 halted
+ EL3RST 47 Level 3 reset
+ ELNRNG 48 Link number out of range
+ EUNATCH 49 Protocol driver not attached
+ ENOCSI 50 No CSI structure available
+ EL2HLT 51 Level 2 halted
+ EBADE 52 Invalid exchange
+ EBADR 53 Invalid request descriptor
+ EXFULL 54 Exchange full
+ ENOANO 55 No anode
+ EBADRQC 56 Invalid request code
+ EBADSLT 57 Invalid slot
+ EDEADLOCK EDEADLK Resource deadlock would occur
+ EBFONT 59 Bad font file format
+ ENOSTR 60 Device not a stream
+ ENODATA 61 No data available
+ ETIME 62 Timer expired
+ ENOSR 63 Out of streams resources
+ ENONET 64 Machine is not on the network
+ ENOPKG 65 Package not installed
+ EREMOTE 66 Object is remote
+ ENOLINK 67 Link has been severed
+ EADV 68 Advertise error
+ ESRMNT 69 Srmount error
+ ECOMM 70 Communication error on send
+ EPROTO 71 Protocol error
+ EMULTIHOP 72 Multihop attempted
+ EDOTDOT 73 RFS specific error
+ EBADMSG 74 Not a data message
+ EOVERFLOW 75 Value too large for defined data type
+ ENOTUNIQ 76 Name not unique on network
+ EBADFD 77 File descriptor in bad state
+ EREMCHG 78 Remote address changed
+ ELIBACC 79 Can not access a needed shared library
+ ELIBBAD 80 Accessing a corrupted shared library
+ ELIBSCN 81 .lib section in a.out corrupted
+ ELIBMAX 82 Attempting to link in too many shared libraries
+ ELIBEXEC 83 Cannot exec a shared library directly
+ EILSEQ 84 Illegal byte sequence
+ ERESTART 85 Interrupted system call should be restarted
+ ESTRPIPE 86 Streams pipe error
+ EUSERS 87 Too many users
+ ENOTSOCK 88 Socket operation on non-socket
+ EDESTADDRREQ 89 Destination address required
+ EMSGSIZE 90 Message too long
+ EPROTOTYPE 91 Protocol wrong type for socket
+ ENOPROTOOPT 92 Protocol not available
+ EPROTONOSUPPORT 93 Protocol not supported
+ ESOCKTNOSUPPORT 94 Socket type not supported
+ EOPNOTSUPP 95 Operation not supported on transport endpoint
+ EPFNOSUPPORT 96 Protocol family not supported
+ EAFNOSUPPORT 97 Address family not supported by protocol
+ EADDRINUSE 98 Address already in use
+ EADDRNOTAVAIL 99 Cannot assign requested address
+ ENETDOWN 100 Network is down
+ ENETUNREACH 101 Network is unreachable
+ ENETRESET 102 Network dropped connection because of reset
+ ECONNABORTED 103 Software caused connection abort
+ ECONNRESET 104 Connection reset by peer
+ ENOBUFS 105 No buffer space available
+ EISCONN 106 Transport endpoint is already connected
+ ENOTCONN 107 Transport endpoint is not connected
+ ESHUTDOWN 108 Cannot send after transport endpoint shutdown
+ ETOOMANYREFS 109 Too many references: cannot splice
+ ETIMEDOUT 110 Connection timed out
+ ECONNREFUSED 111 Connection refused
+ EHOSTDOWN 112 Host is down
+ EHOSTUNREACH 113 No route to host
+ EALREADY 114 Operation already in progress
+ EINPROGRESS 115 Operation now in progress
+ ESTALE 116 Stale NFS file handle
+ EUCLEAN 117 Structure needs cleaning
+ ENOTNAM 118 Not a XENIX named type file
+ ENAVAIL 119 No XENIX semaphores available
+ EISNAM 120 Is a named type file
+ EREMOTEIO 121 Remote I/O error
+ EDQUOT 122 Quota exceeded
+ ENOMEDIUM 123 No medium found
+ EMEDIUMTYPE 124 Wrong medium type
+ ECANCELED 125 Operation Canceled
+ ENOKEY 126 Required key not available
+ EKEYEXPIRED 127 Key has expired
+ EKEYREVOKED 128 Key has been revoked
+ EKEYREJECTED 129 Key was rejected by service
+ EOWNERDEAD 130 Owner died
+ ENOTRECOVERABLE 131 State not recoverable
+ \endverbatim
+ *
+ * @note
+ * MbedOS System Error codes are defined using the macro MBED_DEFINE_SYSTEM_ERROR\n
+ * For example MBED_DEFINE_SYSTEM_ERROR( INVALID_ARGUMENT ,1 ) macro defines the following values:\n
+ * ERROR_CODE_INVALID_ARGUMENT = MBED_SYSTEM_ERROR_BASE+1\n
+ * ERROR_INVALID_ARGUMENT = MAKE_MBED_ERROR(ERROR_TYPE_SYSTEM, MBED_MODULE_UNKNOWN, ERROR_CODE_INVALID_ARGUMENT)\n
+ * Its effectively equivalent to:\n
+ * ERROR_CODE_INVALID_ARGUMENT = 1\n
+ * ERROR_INVALID_ARGUMENT = 0x80FF0001\n (Note that MODULE field is set to MBED_MODULE_UNKNOWN)
+ * New System Error codes should be defined using MBED_DEFINE_SYSTEM_ERROR macro and must have an unique error code value\n
+ * passed as the second argument in the MBED_DEFINE_SYSTEM_ERROR macro.\n\n
+ * Below are the Mbed System error codes and the description:
+ * \verbatim
+ UNKNOWN 256 Unknown error
+ INVALID_ARGUMENT 257 Invalid Argument
+ INVALID_DATA 258 Invalid data
+ INVALID_FORMAT 259 Invalid format
+ INVALID_INDEX 260 Invalid Index
+ INVALID_SIZE 261 Inavlid Size
+ INVALID_OPERATION 262 Invalid Operation
+ NOT_FOUND 263 Not Found
+ ACCESS_DENIED 264 Access Denied
+ NOT_SUPPORTED 265 Not supported
+ BUFFER_FULL 266 Buffer Full
+ MEDIA_FULL 267 Media/Disk Full
+ ALREADY_IN_USE 268 Already in use
+ TIMEOUT 269 Timeout error
+ NOT_READY 270 Not Ready
+ FAILED_OPERATION 271 Requested Operation failed
+ OPERATION_PROHIBITED 272 Operation prohibited
+ OPERATION_ABORTED 273 Operation failed
+ WRITE_PROTECTED 274 Attempt to write to write-protected resource
+ NO_RESPONSE 275 No response
+ SEMAPHORE_LOCK_FAILED 276 Sempahore lock failed
+ MUTEX_LOCK_FAILED 277 Mutex lock failed
+ SEMAPHORE_UNLOCK_FAILED 278 Sempahore unlock failed
+ MUTEX_UNLOCK_FAILED 279 Mutex unlock failed
+ CRC_ERROR 280 CRC error or mismatch
+ OPEN_FAILED 281 Open failed
+ CLOSE_FAILED 282 Close failed
+ READ_FAILED 283 Read failed
+ WRITE_FAILED 284 Write failed
+ INITIALIZATION_FAILED 285 Initialization failed
+ BOOT_FAILURE 286 Boot failure
+ OUT_OF_MEMORY 287 Out of memory
+ OUT_OF_RESOURCES 288 Out of resources
+ ALLOC_FAILED 289 Alloc failed
+ FREE_FAILED 290 Free failed
+ OVERFLOW 291 Overflow error
+ UNDERFLOW 292 Underflow error
+ STACK_OVERFLOW 293 Stack overflow error
+ ISR_QUEUE_OVERFLOW 294 ISR queue overflow
+ TIMER_QUEUE_OVERFLOW 295 Timer Queue overflow
+ CLIB_SPACE_UNAVAILABLE 296 Standard library error - Space unavailable
+ CLIB_EXCEPTION 297 Standard library error - Exception
+ CLIB_MUTEX_INIT_FAILURE 298 Standard library error - Mutex Init failure
+ CREATE_FAILED 299 Create failed
+ DELETE_FAILED 300 Delete failed
+ THREAD_CREATE_FAILED 301 Thread Create failed
+ THREAD_DELETE_FAILED 302 Thread Delete failed
+ PROHIBITED_IN_ISR_CONTEXT 303 Operation Prohibited in ISR context
+ PINMAP_INVALID 304 Pinmap Invalid
+ RTOS_EVENT 305 Unknown Rtos Error
+ RTOS_THREAD_EVENT 306 Rtos Thread Error
+ RTOS_MUTEX_EVENT 307 Rtos Mutex Error
+ RTOS_SEMAPHORE_EVENT 308 Rtos Semaphore Error
+ RTOS_MEMORY_POOL_EVENT 309 Rtos Memory Pool Error
+ RTOS_TIMER_EVENT 310 Rtos Timer Error
+ RTOS_EVENT_FLAGS_EVENT 311 Rtos Event flags Error
+ RTOS_MESSAGE_QUEUE_EVENT 312 Rtos Message queue Error
+ DEVICE_BUSY 313 Device Busy
+ CONFIG_UNSUPPORTED 314 Configuration not supported
+ CONFIG_MISMATCH 315 Configuration mismatch
+ ALREADY_INITIALIZED 316 Already initialzied
+ HARDFAULT_EXCEPTION 317 HardFault exception
+ MEMMANAGE_EXCEPTION 318 MemManage exception
+ BUSFAULT_EXCEPTION 319 BusFault exception
+ USAGEFAULT_EXCEPTION 320 UsageFault exception
+ \endverbatim
+ *
+ * @note
+ * Custom Error codes can be defined using the macro DEFINE_CUSTOM_ERROR\n
+ * This is mainly meant to capture non-generic error codes specific to a device.
+ * For example DEFINE_CUSTOM_ERROR( MY_CUSTOM_ERROR ,1 ) macro defines the following values:\n
+ * ERROR_CODE_MY_CUSTOM_ERROR = MBED_CUSTOM_ERROR_BASE+1\n
+ * ERROR_MY_CUSTOM_ERROR = MAKE_MBED_ERROR(ERROR_TYPE_CUSTOM, MBED_MODULE_UNKNOWN, ERROR_CODE_MY_CUSTOM_ERROR)\n
+ * Its effectively equivalent to:\n
+ * ERROR_CODE_MY_CUSTOM_ERROR = 4097\n
+ * ERROR_MY_CUSTOM_ERROR = 0xA0FF1001\n (Note that MODULE field is set to MBED_MODULE_UNKNOWN) \n\n
+ *
+ * @note
+ * **Using error codes:** \n
+ * Posix error codes may be used in modules/functions currently using Posix error codes and switching them to Mbed-OS error codes
+ * may cause interoperability issues. For example, some of the filesystem, network stack implementations may need to use
+ * Posix error codes in order to keep them compatible with other modules interfacing with them, and may continue to use Posix error codes.
+ *
+ * In all other cases, like for any native development of Mbed-OS modules Mbed-OS error codes should be used.
+ * This makes it easy to use Mbed-OS error reporting/logging infrastructure and makes debugging error scenarios
+ * much more efficient.
+ *
+ * @note
+ * **Searching for error codes in mbed-os source tree:** \n
+ * If you get an error report as below which you want to search for in mbed-os source tree, first take note of "Error Code" number. \n
+ * For example, the below error report has an error code of \b 259. Find the error name associated with the error code and in this case its \b INVALID_FORMAT. \n
+ * Use that error name(\b INVALID_FORMAT) to search the source tree for code locations setting that specific error code. \n
+ * If the Error module reported is not 255(which indicates unknown module), you can also use that to narrow down to the specific component reporting the error.
+ * See mbed_module_type_t enum above for module mapping. \n
+ *
+ * \verbatim
+ ++ MbedOS Error Info ++
+ Error Status: 0x80040103
+ Error Code: 259
+ Error Module: 04
+ Error Message: HAL Module error
+ Error Location: 0x000067C7
+ Error Value: 0x00005566
+ Current Thread: Id: 0x200024A8 EntryFn: 0x0000FB0D StackSize: 0x00001000 StackMem: 0x200014A8 SP: 0x2002FFD8
+ -- MbedOS Error Info --
+ \endverbatim
+ */
+
+typedef enum _mbed_error_code {
+ //Below are POSIX ERROR CODE definitions, which starts at MBED_POSIX_ERROR_BASE(=0)
+ //POSIX ERROR CODE definitions starts at offset 0(MBED_POSIX_ERROR_BASE) to align them with actual Posix Error Code
+ //defintions in mbed_retarget.h
+ // Error Name Error Code
+ MBED_DEFINE_POSIX_ERROR(EPERM, EPERM), /* 1 Operation not permitted */
+ MBED_DEFINE_POSIX_ERROR(ENOENT, ENOENT), /* 2 No such file or directory */
+ MBED_DEFINE_POSIX_ERROR(ESRCH, ESRCH), /* 3 No such process */
+ MBED_DEFINE_POSIX_ERROR(EINTR, EINTR), /* 4 Interrupted system call */
+ MBED_DEFINE_POSIX_ERROR(EIO, EIO), /* 5 I/O error */
+ MBED_DEFINE_POSIX_ERROR(ENXIO, ENXIO), /* 6 No such device or address */
+ MBED_DEFINE_POSIX_ERROR(E2BIG, E2BIG), /* 7 Argument list too long */
+ MBED_DEFINE_POSIX_ERROR(ENOEXEC, ENOEXEC), /* 8 Exec format error */
+ MBED_DEFINE_POSIX_ERROR(EBADF, EBADF), /* 9 Bad file number */
+ MBED_DEFINE_POSIX_ERROR(ECHILD, ECHILD), /* 10 No child processes */
+ MBED_DEFINE_POSIX_ERROR(EAGAIN, EAGAIN), /* 11 Try again */
+ MBED_DEFINE_POSIX_ERROR(ENOMEM, ENOMEM), /* 12 Out of memory */
+ MBED_DEFINE_POSIX_ERROR(EACCES, EACCES), /* 13 Permission denied */
+ MBED_DEFINE_POSIX_ERROR(EFAULT, EFAULT), /* 14 Bad address */
+ MBED_DEFINE_POSIX_ERROR(ENOTBLK, ENOTBLK), /* 15 Block device required */
+ MBED_DEFINE_POSIX_ERROR(EBUSY, EBUSY), /* 16 Device or resource busy */
+ MBED_DEFINE_POSIX_ERROR(EEXIST, EEXIST), /* 17 File exists */
+ MBED_DEFINE_POSIX_ERROR(EXDEV, EXDEV), /* 18 Cross-device link */
+ MBED_DEFINE_POSIX_ERROR(ENODEV, ENODEV), /* 19 No such device */
+ MBED_DEFINE_POSIX_ERROR(ENOTDIR, ENOTDIR), /* 20 Not a directory */
+ MBED_DEFINE_POSIX_ERROR(EISDIR, EISDIR), /* 21 Is a directory */
+ MBED_DEFINE_POSIX_ERROR(EINVAL, EINVAL), /* 22 Invalid argument */
+ MBED_DEFINE_POSIX_ERROR(ENFILE, ENFILE), /* 23 File table overflow */
+ MBED_DEFINE_POSIX_ERROR(EMFILE, EMFILE), /* 24 Too many open files */
+ MBED_DEFINE_POSIX_ERROR(ENOTTY, ENOTTY), /* 25 Not a typewriter */
+ MBED_DEFINE_POSIX_ERROR(ETXTBSY, ETXTBSY), /* 26 Text file busy */
+ MBED_DEFINE_POSIX_ERROR(EFBIG, EFBIG), /* 27 File too large */
+ MBED_DEFINE_POSIX_ERROR(ENOSPC, ENOSPC), /* 28 No space left on device */
+ MBED_DEFINE_POSIX_ERROR(ESPIPE, ESPIPE), /* 29 Illegal seek */
+ MBED_DEFINE_POSIX_ERROR(EROFS, EROFS), /* 30 Read-only file system */
+ MBED_DEFINE_POSIX_ERROR(EMLINK, EMLINK), /* 31 Too many links */
+ MBED_DEFINE_POSIX_ERROR(EPIPE, EPIPE), /* 32 Broken pipe */
+ MBED_DEFINE_POSIX_ERROR(EDOM, EDOM), /* 33 Math argument out of domain of func */
+ MBED_DEFINE_POSIX_ERROR(ERANGE, ERANGE), /* 34 Math result not representable */
+ MBED_DEFINE_POSIX_ERROR(EDEADLK, EDEADLK), /* 35 Resource deadlock would occur */
+ MBED_DEFINE_POSIX_ERROR(ENAMETOOLONG, ENAMETOOLONG), /* 36 File name too long */
+ MBED_DEFINE_POSIX_ERROR(ENOLCK, ENOLCK), /* 37 No record locks available */
+ MBED_DEFINE_POSIX_ERROR(ENOSYS, ENOSYS), /* 38 Function not implemented */
+ MBED_DEFINE_POSIX_ERROR(ENOTEMPTY, ENOTEMPTY), /* 39 Directory not empty */
+ MBED_DEFINE_POSIX_ERROR(ELOOP, ELOOP), /* 40 Too many symbolic links encountered */
+ MBED_DEFINE_POSIX_ERROR(EWOULDBLOCK, EAGAIN), /* EAGAIN Operation would block */
+ MBED_DEFINE_POSIX_ERROR(ENOMSG, ENOMSG), /* 42 No message of desired type */
+ MBED_DEFINE_POSIX_ERROR(EIDRM, EIDRM), /* 43 Identifier removed */
+ MBED_DEFINE_POSIX_ERROR(ECHRNG, ECHRNG), /* 44 Channel number out of range */
+ MBED_DEFINE_POSIX_ERROR(EL2NSYNC, EL2NSYNC), /* 45 Level 2 not synchronized */
+ MBED_DEFINE_POSIX_ERROR(EL3HLT, EL3HLT), /* 46 Level 3 halted */
+ MBED_DEFINE_POSIX_ERROR(EL3RST, EL3RST), /* 47 Level 3 reset */
+ MBED_DEFINE_POSIX_ERROR(ELNRNG, ELNRNG), /* 48 Link number out of range */
+ MBED_DEFINE_POSIX_ERROR(EUNATCH, EUNATCH), /* 49 Protocol driver not attached */
+ MBED_DEFINE_POSIX_ERROR(ENOCSI, ENOCSI), /* 50 No CSI structure available */
+ MBED_DEFINE_POSIX_ERROR(EL2HLT, EL2HLT), /* 51 Level 2 halted */
+ MBED_DEFINE_POSIX_ERROR(EBADE, EBADE), /* 52 Invalid exchange */
+ MBED_DEFINE_POSIX_ERROR(EBADR, EBADR), /* 53 Invalid request descriptor */
+ MBED_DEFINE_POSIX_ERROR(EXFULL, EXFULL), /* 54 Exchange full */
+ MBED_DEFINE_POSIX_ERROR(ENOANO, ENOANO), /* 55 No anode */
+ MBED_DEFINE_POSIX_ERROR(EBADRQC, EBADRQC), /* 56 Invalid request code */
+ MBED_DEFINE_POSIX_ERROR(EBADSLT, EBADSLT), /* 57 Invalid slot */
+ MBED_DEFINE_POSIX_ERROR(EDEADLOCK, EDEADLK), /* EDEADLK Resource deadlock would occur */
+ MBED_DEFINE_POSIX_ERROR(EBFONT, EBFONT), /* 59 Bad font file format */
+ MBED_DEFINE_POSIX_ERROR(ENOSTR, ENOSTR), /* 60 Device not a stream */
+ MBED_DEFINE_POSIX_ERROR(ENODATA, ENODATA), /* 61 No data available */
+ MBED_DEFINE_POSIX_ERROR(ETIME, ETIME), /* 62 Timer expired */
+ MBED_DEFINE_POSIX_ERROR(ENOSR, ENOSR), /* 63 Out of streams resources */
+ MBED_DEFINE_POSIX_ERROR(ENONET, ENONET), /* 64 Machine is not on the network */
+ MBED_DEFINE_POSIX_ERROR(ENOPKG, ENOPKG), /* 65 Package not installed */
+ MBED_DEFINE_POSIX_ERROR(EREMOTE, EREMOTE), /* 66 Object is remote */
+ MBED_DEFINE_POSIX_ERROR(ENOLINK, ENOLINK), /* 67 Link has been severed */
+ MBED_DEFINE_POSIX_ERROR(EADV, EADV), /* 68 Advertise error */
+ MBED_DEFINE_POSIX_ERROR(ESRMNT, ESRMNT), /* 69 Srmount error */
+ MBED_DEFINE_POSIX_ERROR(ECOMM, ECOMM), /* 70 Communication error on send */
+ MBED_DEFINE_POSIX_ERROR(EPROTO, EPROTO), /* 71 Protocol error */
+ MBED_DEFINE_POSIX_ERROR(EMULTIHOP, EMULTIHOP), /* 72 Multihop attempted */
+ MBED_DEFINE_POSIX_ERROR(EDOTDOT, EDOTDOT), /* 73 RFS specific error */
+ MBED_DEFINE_POSIX_ERROR(EBADMSG, EBADMSG), /* 74 Not a data message */
+ MBED_DEFINE_POSIX_ERROR(EOVERFLOW, EOVERFLOW), /* 75 Value too large for defined data type */
+ MBED_DEFINE_POSIX_ERROR(ENOTUNIQ, ENOTUNIQ), /* 76 Name not unique on network */
+ MBED_DEFINE_POSIX_ERROR(EBADFD, EBADFD), /* 77 File descriptor in bad state */
+ MBED_DEFINE_POSIX_ERROR(EREMCHG, EREMCHG), /* 78 Remote address changed */
+ MBED_DEFINE_POSIX_ERROR(ELIBACC, ELIBACC), /* 79 Can not access a needed shared library */
+ MBED_DEFINE_POSIX_ERROR(ELIBBAD, ELIBBAD), /* 80 Accessing a corrupted shared library */
+ MBED_DEFINE_POSIX_ERROR(ELIBSCN, ELIBSCN), /* 81 .lib section in a.out corrupted */
+ MBED_DEFINE_POSIX_ERROR(ELIBMAX, ELIBMAX), /* 82 Attempting to link in too many shared libraries */
+ MBED_DEFINE_POSIX_ERROR(ELIBEXEC, ELIBEXEC), /* 83 Cannot exec a shared library directly */
+ MBED_DEFINE_POSIX_ERROR(EILSEQ, EILSEQ), /* 84 Illegal byte sequence */
+ MBED_DEFINE_POSIX_ERROR(ERESTART, ERESTART), /* 85 Interrupted system call should be restarted */
+ MBED_DEFINE_POSIX_ERROR(ESTRPIPE, ESTRPIPE), /* 86 Streams pipe error */
+ MBED_DEFINE_POSIX_ERROR(EUSERS, EUSERS), /* 87 Too many users */
+ MBED_DEFINE_POSIX_ERROR(ENOTSOCK, ENOTSOCK), /* 88 Socket operation on non-socket */
+ MBED_DEFINE_POSIX_ERROR(EDESTADDRREQ, EDESTADDRREQ), /* 89 Destination address required */
+ MBED_DEFINE_POSIX_ERROR(EMSGSIZE, EMSGSIZE), /* 90 Message too long */
+ MBED_DEFINE_POSIX_ERROR(EPROTOTYPE, EPROTOTYPE), /* 91 Protocol wrong type for socket */
+ MBED_DEFINE_POSIX_ERROR(ENOPROTOOPT, ENOPROTOOPT), /* 92 Protocol not available */
+ MBED_DEFINE_POSIX_ERROR(EPROTONOSUPPORT, EPROTONOSUPPORT), /* 93 Protocol not supported */
+ MBED_DEFINE_POSIX_ERROR(ESOCKTNOSUPPORT, ESOCKTNOSUPPORT), /* 94 Socket type not supported */
+ MBED_DEFINE_POSIX_ERROR(EOPNOTSUPP, EOPNOTSUPP), /* 95 Operation not supported on transport endpoint */
+ MBED_DEFINE_POSIX_ERROR(EPFNOSUPPORT, EPFNOSUPPORT), /* 96 Protocol family not supported */
+ MBED_DEFINE_POSIX_ERROR(EAFNOSUPPORT, EAFNOSUPPORT), /* 97 Address family not supported by protocol */
+ MBED_DEFINE_POSIX_ERROR(EADDRINUSE, EADDRINUSE), /* 98 Address already in use */
+ MBED_DEFINE_POSIX_ERROR(EADDRNOTAVAIL, EADDRNOTAVAIL), /* 99 Cannot assign requested address */
+ MBED_DEFINE_POSIX_ERROR(ENETDOWN, ENETDOWN), /* 100 Network is down */
+ MBED_DEFINE_POSIX_ERROR(ENETUNREACH, ENETUNREACH), /* 101 Network is unreachable */
+ MBED_DEFINE_POSIX_ERROR(ENETRESET, ENETRESET), /* 102 Network dropped connection because of reset */
+ MBED_DEFINE_POSIX_ERROR(ECONNABORTED, ECONNABORTED), /* 103 Software caused connection abort */
+ MBED_DEFINE_POSIX_ERROR(ECONNRESET, ECONNRESET), /* 104 Connection reset by peer */
+ MBED_DEFINE_POSIX_ERROR(ENOBUFS, ENOBUFS), /* 105 No buffer space available */
+ MBED_DEFINE_POSIX_ERROR(EISCONN, EISCONN), /* 106 Transport endpoint is already connected */
+ MBED_DEFINE_POSIX_ERROR(ENOTCONN, ENOTCONN), /* 107 Transport endpoint is not connected */
+ MBED_DEFINE_POSIX_ERROR(ESHUTDOWN, ESHUTDOWN), /* 108 Cannot send after transport endpoint shutdown */
+ MBED_DEFINE_POSIX_ERROR(ETOOMANYREFS, ETOOMANYREFS), /* 109 Too many references: cannot splice */
+ MBED_DEFINE_POSIX_ERROR(ETIMEDOUT, ETIMEDOUT), /* 110 Connection timed out */
+ MBED_DEFINE_POSIX_ERROR(ECONNREFUSED, ECONNREFUSED), /* 111 Connection refused */
+ MBED_DEFINE_POSIX_ERROR(EHOSTDOWN, EHOSTDOWN), /* 112 Host is down */
+ MBED_DEFINE_POSIX_ERROR(EHOSTUNREACH, EHOSTUNREACH), /* 113 No route to host */
+ MBED_DEFINE_POSIX_ERROR(EALREADY, EALREADY), /* 114 Operation already in progress */
+ MBED_DEFINE_POSIX_ERROR(EINPROGRESS, EINPROGRESS), /* 115 Operation now in progress */
+ MBED_DEFINE_POSIX_ERROR(ESTALE, ESTALE), /* 116 Stale NFS file handle */
+ MBED_DEFINE_POSIX_ERROR(EUCLEAN, EUCLEAN), /* 117 Structure needs cleaning */
+ MBED_DEFINE_POSIX_ERROR(ENOTNAM, ENOTNAM), /* 118 Not a XENIX named type file */
+ MBED_DEFINE_POSIX_ERROR(ENAVAIL, ENAVAIL), /* 119 No XENIX semaphores available */
+ MBED_DEFINE_POSIX_ERROR(EISNAM, EISNAM), /* 120 Is a named type file */
+ MBED_DEFINE_POSIX_ERROR(EREMOTEIO, EREMOTEIO), /* 121 Remote I/O error */
+ MBED_DEFINE_POSIX_ERROR(EDQUOT, EDQUOT), /* 122 Quota exceeded */
+ MBED_DEFINE_POSIX_ERROR(ENOMEDIUM, ENOMEDIUM), /* 123 No medium found */
+ MBED_DEFINE_POSIX_ERROR(EMEDIUMTYPE, EMEDIUMTYPE), /* 124 Wrong medium type */
+ MBED_DEFINE_POSIX_ERROR(ECANCELED, ECANCELED), /* 125 Operation Canceled */
+ MBED_DEFINE_POSIX_ERROR(ENOKEY, ENOKEY), /* 126 Required key not available */
+ MBED_DEFINE_POSIX_ERROR(EKEYEXPIRED, EKEYEXPIRED), /* 127 Key has expired */
+ MBED_DEFINE_POSIX_ERROR(EKEYREVOKED, EKEYREVOKED), /* 128 Key has been revoked */
+ MBED_DEFINE_POSIX_ERROR(EKEYREJECTED, EKEYREJECTED), /* 129 Key was rejected by service */
+ MBED_DEFINE_POSIX_ERROR(EOWNERDEAD, EOWNERDEAD), /* 130 Owner died */
+ MBED_DEFINE_POSIX_ERROR(ENOTRECOVERABLE, ENOTRECOVERABLE), /* 131 State not recoverable */
+
+ //Below are MBED SYSTEM ERROR CODE definitions
+ //MBED SYSTEM ERROR CODE definitions starts at offset MBED_SYSTEM_ERROR_BASE, see above.
+ // Error Name Error Offset Error Code
+ MBED_DEFINE_SYSTEM_ERROR(UNKNOWN, 0), /* 256 Unknown error */
+ MBED_DEFINE_SYSTEM_ERROR(INVALID_ARGUMENT, 1), /* 257 Invalid Argument */
+ MBED_DEFINE_SYSTEM_ERROR(INVALID_DATA_DETECTED, 2), /* 258 Invalid data detected */
+ MBED_DEFINE_SYSTEM_ERROR(INVALID_FORMAT, 3), /* 259 Invalid format */
+ MBED_DEFINE_SYSTEM_ERROR(INVALID_INDEX, 4), /* 260 Invalid Index */
+ MBED_DEFINE_SYSTEM_ERROR(INVALID_SIZE, 5), /* 261 Inavlid Size */
+ MBED_DEFINE_SYSTEM_ERROR(INVALID_OPERATION, 6), /* 262 Invalid Operation */
+ MBED_DEFINE_SYSTEM_ERROR(ITEM_NOT_FOUND, 7), /* 263 Item Not Found */
+ MBED_DEFINE_SYSTEM_ERROR(ACCESS_DENIED, 8), /* 264 Access Denied */
+ MBED_DEFINE_SYSTEM_ERROR(UNSUPPORTED, 9), /* 265 Unsupported */
+ MBED_DEFINE_SYSTEM_ERROR(BUFFER_FULL, 10), /* 266 Buffer Full */
+ MBED_DEFINE_SYSTEM_ERROR(MEDIA_FULL, 11), /* 267 Media/Disk Full */
+ MBED_DEFINE_SYSTEM_ERROR(ALREADY_IN_USE, 12), /* 268 Already in use */
+ MBED_DEFINE_SYSTEM_ERROR(TIME_OUT, 13), /* 269 Timeout error */
+ MBED_DEFINE_SYSTEM_ERROR(NOT_READY, 14), /* 270 Not Ready */
+ MBED_DEFINE_SYSTEM_ERROR(FAILED_OPERATION, 15), /* 271 Requested Operation failed */
+ MBED_DEFINE_SYSTEM_ERROR(OPERATION_PROHIBITED, 16), /* 272 Operation prohibited */
+ MBED_DEFINE_SYSTEM_ERROR(OPERATION_ABORTED, 17), /* 273 Operation failed */
+ MBED_DEFINE_SYSTEM_ERROR(WRITE_PROTECTED, 18), /* 274 Attempt to write to write-protected resource */
+ MBED_DEFINE_SYSTEM_ERROR(NO_RESPONSE, 19), /* 275 No response */
+ MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_LOCK_FAILED, 20), /* 276 Sempahore lock failed */
+ MBED_DEFINE_SYSTEM_ERROR(MUTEX_LOCK_FAILED, 21), /* 277 Mutex lock failed */
+ MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_UNLOCK_FAILED, 22), /* 278 Sempahore unlock failed */
+ MBED_DEFINE_SYSTEM_ERROR(MUTEX_UNLOCK_FAILED, 23), /* 279 Mutex unlock failed */
+ MBED_DEFINE_SYSTEM_ERROR(CRC_ERROR, 24), /* 280 CRC error or mismatch */
+ MBED_DEFINE_SYSTEM_ERROR(OPEN_FAILED, 25), /* 281 Open failed */
+ MBED_DEFINE_SYSTEM_ERROR(CLOSE_FAILED, 26), /* 282 Close failed */
+ MBED_DEFINE_SYSTEM_ERROR(READ_FAILED, 27), /* 283 Read failed */
+ MBED_DEFINE_SYSTEM_ERROR(WRITE_FAILED, 28), /* 284 Write failed */
+ MBED_DEFINE_SYSTEM_ERROR(INITIALIZATION_FAILED, 29), /* 285 Initialization failed */
+ MBED_DEFINE_SYSTEM_ERROR(BOOT_FAILURE, 30), /* 286 Boot failure */
+ MBED_DEFINE_SYSTEM_ERROR(OUT_OF_MEMORY, 31), /* 287 Out of memory */
+ MBED_DEFINE_SYSTEM_ERROR(OUT_OF_RESOURCES, 32), /* 288 Out of resources */
+ MBED_DEFINE_SYSTEM_ERROR(ALLOC_FAILED, 33), /* 289 Alloc failed */
+ MBED_DEFINE_SYSTEM_ERROR(FREE_FAILED, 34), /* 290 Free failed */
+ MBED_DEFINE_SYSTEM_ERROR(OVERFLOW, 35), /* 291 Overflow error */
+ MBED_DEFINE_SYSTEM_ERROR(UNDERFLOW, 36), /* 292 Underflow error */
+ MBED_DEFINE_SYSTEM_ERROR(STACK_OVERFLOW, 37), /* 293 Stack overflow error */
+ MBED_DEFINE_SYSTEM_ERROR(ISR_QUEUE_OVERFLOW, 38), /* 294 ISR queue overflow */
+ MBED_DEFINE_SYSTEM_ERROR(TIMER_QUEUE_OVERFLOW, 39), /* 295 Timer Queue overflow */
+ MBED_DEFINE_SYSTEM_ERROR(CLIB_SPACE_UNAVAILABLE, 40), /* 296 Standard library error - Space unavailable */
+ MBED_DEFINE_SYSTEM_ERROR(CLIB_EXCEPTION, 41), /* 297 Standard library error - Exception */
+ MBED_DEFINE_SYSTEM_ERROR(CLIB_MUTEX_INIT_FAILURE, 42), /* 298 Standard library error - Mutex Init failure */
+ MBED_DEFINE_SYSTEM_ERROR(CREATE_FAILED, 43), /* 299 Create failed */
+ MBED_DEFINE_SYSTEM_ERROR(DELETE_FAILED, 44), /* 300 Delete failed */
+ MBED_DEFINE_SYSTEM_ERROR(THREAD_CREATE_FAILED, 45), /* 301 Thread Create failed */
+ MBED_DEFINE_SYSTEM_ERROR(THREAD_DELETE_FAILED, 46), /* 302 Thread Delete failed */
+ MBED_DEFINE_SYSTEM_ERROR(PROHIBITED_IN_ISR_CONTEXT, 47), /* 303 Operation Prohibited in ISR context */
+ MBED_DEFINE_SYSTEM_ERROR(PINMAP_INVALID, 48), /* 304 Pinmap Invalid */
+ MBED_DEFINE_SYSTEM_ERROR(RTOS_EVENT, 49), /* 305 Unknown Rtos Error */
+ MBED_DEFINE_SYSTEM_ERROR(RTOS_THREAD_EVENT, 50), /* 306 Rtos Thread Error */
+ MBED_DEFINE_SYSTEM_ERROR(RTOS_MUTEX_EVENT, 51), /* 307 Rtos Mutex Error */
+ MBED_DEFINE_SYSTEM_ERROR(RTOS_SEMAPHORE_EVENT, 52), /* 308 Rtos Semaphore Error */
+ MBED_DEFINE_SYSTEM_ERROR(RTOS_MEMORY_POOL_EVENT, 53), /* 309 Rtos Memory Pool Error */
+ MBED_DEFINE_SYSTEM_ERROR(RTOS_TIMER_EVENT, 54), /* 310 Rtos Timer Error */
+ MBED_DEFINE_SYSTEM_ERROR(RTOS_EVENT_FLAGS_EVENT, 55), /* 311 Rtos Event flags Error */
+ MBED_DEFINE_SYSTEM_ERROR(RTOS_MESSAGE_QUEUE_EVENT, 56), /* 312 Rtos Message queue Error */
+ MBED_DEFINE_SYSTEM_ERROR(DEVICE_BUSY, 57), /* 313 Device Busy */
+ MBED_DEFINE_SYSTEM_ERROR(CONFIG_UNSUPPORTED, 58), /* 314 Configuration not supported */
+ MBED_DEFINE_SYSTEM_ERROR(CONFIG_MISMATCH, 59), /* 315 Configuration mismatch */
+ MBED_DEFINE_SYSTEM_ERROR(ALREADY_INITIALIZED, 60), /* 316 Already initialzied */
+ MBED_DEFINE_SYSTEM_ERROR(HARDFAULT_EXCEPTION, 61), /* 317 HardFault exception */
+ MBED_DEFINE_SYSTEM_ERROR(MEMMANAGE_EXCEPTION, 62), /* 318 MemManage exception */
+ MBED_DEFINE_SYSTEM_ERROR(BUSFAULT_EXCEPTION, 63), /* 319 BusFault exception */
+ MBED_DEFINE_SYSTEM_ERROR(USAGEFAULT_EXCEPTION, 64), /* 320 UsageFault exception*/
+
+ //Everytime you add a new system error code, you must update
+ //Error documentation under Handbook to capture the info on
+ //the new error status/codes
+
+ //MBED CUSTOM ERROR CODE definitions starts at offset MBED_CUSTOM_ERROR_BASE, see above.
+ /* Add More/Custom Error Codes here, See example below */
+ //DEFINE_CUSTOM_ERROR( MY_CUSTOM_ERROR , 1 ),
+
+} mbed_error_code_t;
+
+/** mbed_error_ctx struct
+ *
+ * This struct captures the context information at the time of error.\n
+ * It primarily contains information about the thread where the error originated,\n
+ * filename/line number of the source file where the error occurred, a context specific error value(error_value)\n
+ * and the address where the error originated.\n
+ *
+ * @note
+ * Below are the members of mbed_error_ctx struct\n
+ * error_status mbed_error_status_t value for this error\n
+ * error_function_address Address where the error occurred\n
+ * thread_id ID of the thread which generated the error\n
+ * thread_entry_address Entry function of the thread which generated the error\n
+ * thread_stack_size Stack Size of the thread which generated the error\n
+ * thread_stack_mem Stack Top of the thread which generated the error\n
+ * thread_current_sp Current Stack Pointer of the thread which generated the error\n
+ * error_value A context/error specific value associated with this error\n
+ * error_filename Filename where the error originated\n
+ * error_line_number Line number in error_filename where the error originated\n
+ */
+typedef struct _mbed_error_ctx {
+ mbed_error_status_t error_status;
+ uint32_t error_address;
+ uint32_t error_value;
+ uint32_t thread_id;
+ uint32_t thread_entry_address;
+ uint32_t thread_stack_size;
+ uint32_t thread_stack_mem;
+ uint32_t thread_current_sp;
+#ifdef MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN
+ char error_filename[MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN];
+ uint32_t error_line_number;
+#endif
+} mbed_error_ctx;
+
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @param format C string that contains data stream to be printed.
+ * Code snippets below show valid format.
+ *
+ * @code
+ * #error "That shouldn't have happened!"
+ * @endcode
+ *
+ * If the compiler evaluates this line, it will report the error and stop the compile.
+ *
+ * For example, you could use this to check some user-defined compile-time variables:
+ *
+ * @code
+ * #define NUM_PORTS 7
+ * #if (NUM_PORTS > 4)
+ * #error "NUM_PORTS must be less than 4"
+ * #endif
+ * @endcode
+ *
+ * Reporting Run-Time Errors:
+ * To generate a fatal run-time error, you can use the mbed error() function.
+ *
+ * @code
+ * error("That shouldn't have happened!");
+ * @endcode
+ *
+ * If the mbed running the program executes this function, it will print the
+ * message via the USB serial port, and then die with the blue lights of death!
+ *
+ * The message can use printf-style formatting, so you can report variables in the
+ * message too. For example, you could use this to check a run-time condition:
+ *
+ * @code
+ * if(x >= 5) {
+ * error("expected x to be less than 5, but got %d", x);
+ * }
+ * @endcode
+ *
+ *
+ */
+
+void error(const char *format, ...);
+
+/**
+ * Call this Macro to generate a mbed_error_status_t value for a System error
+ * @param module Module generating the error code. If its unknown, pass MBED_MODULE_UNKNOWN. See mbed_module_type_t for module types.
+ * @param error_code The mbed_error_code_t code to be used in generating the mbed_error_status_t. See mbed_error_code_t for error codes.
+ *
+ * @code
+ *
+ * mbed_error_status_t driver_error = MBED_MAKE_SYSTEM_ERROR( MODULE_DRIVER_USB, MBED_ERROR_CODE_INITIALIZATION_FAILED )
+ *
+ * @endcode
+ * @note This macro generate mbed_error_status_t-es with error type set to MBED_ERROR_TYPE_SYSTEM
+ *
+ */
+#define MBED_MAKE_SYSTEM_ERROR(module, error_code) MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, module, error_code)
+
+/**
+ * Call this Macro to generate a mbed_error_status_t value for a Custom error
+ * @param module Module generating the error code. If its unknown, pass MBED_MODULE_UNKNOWN. See mbed_module_type_t for module types.
+ * @param error_code The mbed_error_code_t code to be used in generating the mbed_error_status_t. See mbed_error_code_t for error codes.
+ *
+ * @code
+ *
+ * mbed_error_status_t custom_error = MBED_MAKE_CUSTOM_ERROR( MBED_MODULE_APPLICATION, 0xDEAD//16-bit custom error code )
+ *
+ * @endcode
+ * @note This macro generate mbed_error_status_t-es with error type set to MBED_ERROR_TYPE_CUSTOM
+ *
+ */
+#define MBED_MAKE_CUSTOM_ERROR(module, error_code) MAKE_MBED_ERROR(MBED_ERROR_TYPE_CUSTOM, module, error_code)
+
+/**
+ * Call this Macro to generate a mbed_error_status_t value for a System error
+ * @param module Module generating the error code. If its unknown, pass MBED_MODULE_UNKNOWN. See mbed_module_type_t for module types.
+ * @param error_code The mbed_error_code_t code to be used in generating the mbed_error_status_t. See mbed_error_code_t for error codes.
+ *
+ * @code
+ *
+ * mbed_error_status_t new_error = MBED_MAKE_ERROR( MODULE_DRIVER_USB, MBED_ERROR_INITIALIZATION_FAILED )
+ *
+ * @endcode
+ * @note This macro generate mbed_error_status_t-es with error type set to MBED_ERROR_TYPE_SYSTEM
+ *
+ */
+#define MBED_MAKE_ERROR(module, error_code) MBED_MAKE_SYSTEM_ERROR(module, error_code)
+
+/**
+ * Callback/Error hook function prototype. Applications needing a callback when an error is reported can use mbed_set_error_hook function
+ * to register a callback/error hook function using the following prototype. When an error happens in the system error handling
+ * implementation will invoke this callback with the mbed_error_status_t reported and the error context at the time of error.
+ * @param error_status mbed_error_status_t status being reported.
+ * @param error_ctx Error context structure associated with this error.
+ * @return void
+ *
+ */
+typedef void (*mbed_error_hook_t)(const mbed_error_ctx *error_ctx);
+
+/**
+ * Call this function to set a system error/warning. This function will log the error status with the context info and return to caller.
+ *
+ * @param error_status mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @param error_msg The error message to be printed out to STDIO/Serial.
+ * @param error_value Value associated with the error status. This would depend on error code/error scenario.
+ * @param filename Name of the source file originating the error( Most callers can pass __FILE__ here ).
+ * @param line_number The line number of the source file originating the error( Most callers can pass __LINE__ here ) .
+ * @return 0 or MBED_SUCCESS.
+ * MBED_ERROR_INVALID_ARGUMENT if called with invalid error status/codes
+ *
+ * @code
+ *
+ * mbed_error( ERROR_OUT_OF_MEMORY, "Out of memory error", 0, __FILE__, __LINE__ )
+ *
+ * @endcode
+ *
+ * @note See MBED_WARNING/MBED_ERROR macros which provides a wrapper on this API
+ */
+mbed_error_status_t mbed_warning(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number);
+
+/**
+ * Returns the first system error reported.
+ * @return mbed_error_status_t code logged for the first error or MBED_SUCCESS if no errors are logged.
+ *
+ */
+mbed_error_status_t mbed_get_first_error(void);
+
+/**
+ * Returns the most recent system error reported.
+ * @return mbed_error_status_t code logged for the last error or MBED_SUCCESS if no errors are logged.
+ *
+ */
+mbed_error_status_t mbed_get_last_error(void);
+
+/**
+ * Returns the number of system errors reported after boot.
+ * @return int Number of errors reported.
+ *
+ */
+int mbed_get_error_count(void);
+
+/**
+ * Call this function to set a fatal system error and halt the system. This function will log the fatal error with the context info and prints the error report and halts the system.
+ *
+ * @param error_status mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @param error_msg The error message to be printed out to STDIO/Serial.
+ * @param error_value Value associated with the error status. This would depend on error code/error scenario.
+ * @param filename Name of the source file originating the error( Most callers can pass __FILE__ here ).
+ * @param line_number The line number of the source file originating the error( Most callers can pass __LINE__ here ) .
+ * @return 0 or MBED_SUCCESS.
+ * MBED_ERROR_INVALID_ARGUMENT if called with invalid error status/codes
+ *
+ * @code
+ *
+ * mbed_error( MBED_ERROR_PROHIBITED_OPERATION, "Prohibited operation tried", 0, __FILE__, __LINE__ )
+ *
+ * @endcode
+ *
+ * @note See MBED_WARNING/MBED_ERROR macros which provides a wrapper on this API
+ */
+mbed_error_status_t mbed_error(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number);
+
+/**
+ * Registers an application defined error callback with the error handling system.
+ * This function will be called with error context info whenever system handles a mbed_error/mbed_warning call
+ * NOTE: This function should be implemented for re-entrancy as multiple threads may invoke mbed_error which may cause error hook to be called.
+ * @param custom_error_hook mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
+ * @return 0 or MBED_SUCCESS on success.
+ * MBED_ERROR_INVALID_ARGUMENT in case of NULL for custom_error_hook
+ *
+ * @code
+ *
+ * mbed_error_status_t my_custom_error_hook(mbed_error_status_t error_status, const mbed_error_ctx *error_ctx) {
+ * //Do something with the error_status or error_ctx
+ * }
+ *
+ * mbed_set_error_hook( my_custom_error_hook )
+ *
+ * @endcode
+ * @note The erro hook function implementation should be re-entrant.
+ *
+ */
+mbed_error_status_t mbed_set_error_hook(mbed_error_hook_t custom_error_hook);
+
+/**
+ * Reads the first error context information captured.
+ * @param error_info This is the mbed_error_context info captured as part of the first mbed_error call. The caller should pass a pointer to mbed_error_context struct allocated by the caller.
+ * @return 0 or MBED_SUCCESS on success.
+ * MBED_ERROR_INVALID_ARGUMENT in case of invalid index
+ *
+ */
+mbed_error_status_t mbed_get_first_error_info(mbed_error_ctx *error_info);
+
+/**
+ * Reads the last error context information captured.
+ * @param error_info This is the mbed_error_context info captured as part of the last mbed_error call. The caller should pass a pointer to mbed_error_context struct allocated by the caller.
+ * @return 0 or MBED_ERROR_SUCCESS on success.
+ * MBED_ERROR_INVALID_ARGUMENT in case of invalid index
+ *
+ */
+mbed_error_status_t mbed_get_last_error_info(mbed_error_ctx *error_info);
+
+/**
+ * Clears the last error, first error, error count and all entries in the error history.
+ * @return 0 or MBED_SUCCESS on success.
+ *
+ */
+mbed_error_status_t mbed_clear_all_errors(void);
+
+/**
+ * Generates a mbed_error_status_t value based on passed in values for type, module and error code.
+ * @param error_type Error type based on mbed_error_type_t enum.
+ * @param module Module type based on mbed_module_type_t enum.
+ * @param error_code Error codes defined by mbed_error_code_t enum
+ * @return 0 or MBED_ERROR_SUCCESS on success.
+ *
+ */
+mbed_error_status_t mbed_make_error(mbed_error_type_t error_type, mbed_module_type_t module, mbed_error_code_t error_code);
+
+/**
+ * Returns the current number of entries in the error history, if there has been more than max number of errors logged the number returned will be max depth of error history.
+ * @return Current number of entries in the error history.
+ *
+ */
+int mbed_get_error_hist_count(void);
+
+/**
+ * Reads the error context information for a specific error from error history, specified by the index.
+ *
+ * @param index index of the error context entry in the history to be retrieved.\n
+ * The number of entries in the error history is configured during build and the max index depends on max depth of error history.\n
+ * index = 0 points to the oldest entry in the history, and index = (max history depth - 1) points to the latest entry in the error history.\n
+ * @param error_info This is the mbed_error_context info captured as part of the error history. The caller should pass a pointer to mbed_error_context struct allocated by the caller.
+ * @return 0 or MBED_SUCCESS on success.
+ * MBED_ERROR_INVALID_ARGUMENT in case of invalid index
+ *
+ */
+mbed_error_status_t mbed_get_error_hist_info(int index, mbed_error_ctx *error_info);
+
+/**
+ * Saves the error history information to a file
+ *
+ * @param path path to the file in the filesystem
+ * @return 0 or MBED_ERROR_SUCCESS on success.
+ * MBED_ERROR_WRITE_FAILED if writing to file failed
+ * MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ * @note Filesystem support is required in order for this function to work.
+ *
+ */
+mbed_error_status_t mbed_save_error_hist(const char *path);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+/** @}*/
+
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_error_hist.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_error_hist.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_interface.h"
+
+#if MBED_CONF_PLATFORM_ERROR_HIST_ENABLED
+#include "platform/mbed_error_hist.h"
+
+static mbed_error_ctx mbed_error_ctx_log[MBED_CONF_PLATFORM_ERROR_HIST_SIZE] = {0};
+static int error_log_count = -1;
+
+mbed_error_status_t mbed_error_hist_put(mbed_error_ctx *error_ctx)
+{
+ //Return error if error_ctx is NULL
+ if (NULL == error_ctx) {
+ return MBED_ERROR_INVALID_ARGUMENT;
+ }
+
+ core_util_critical_section_enter();
+ error_log_count++;
+ memcpy(&mbed_error_ctx_log[error_log_count % MBED_CONF_PLATFORM_ERROR_HIST_SIZE], error_ctx, sizeof(mbed_error_ctx));
+ core_util_critical_section_exit();
+
+ return MBED_SUCCESS;
+}
+
+mbed_error_status_t mbed_error_hist_get(int index, mbed_error_ctx *error_ctx)
+{
+ //Return error if index is more than max log size
+ if (index >= MBED_CONF_PLATFORM_ERROR_HIST_SIZE) {
+ return MBED_ERROR_INVALID_ARGUMENT;
+ }
+
+ core_util_critical_section_enter();
+ //calculate the index where we want to pick the ctx
+ if (error_log_count >= MBED_CONF_PLATFORM_ERROR_HIST_SIZE) {
+ index = (error_log_count + index + 1) % MBED_CONF_PLATFORM_ERROR_HIST_SIZE;
+ }
+ core_util_critical_section_exit();
+ memcpy(error_ctx, &mbed_error_ctx_log[index % MBED_CONF_PLATFORM_ERROR_HIST_SIZE], sizeof(mbed_error_ctx));
+
+ return MBED_SUCCESS;
+}
+
+mbed_error_ctx *mbed_error_hist_get_entry(void)
+{
+ core_util_critical_section_enter();
+ error_log_count++;
+ mbed_error_ctx *ctx = &mbed_error_ctx_log[error_log_count % MBED_CONF_PLATFORM_ERROR_HIST_SIZE];
+ core_util_critical_section_exit();
+
+ return ctx;
+}
+
+mbed_error_status_t mbed_error_hist_get_last_error(mbed_error_ctx *error_ctx)
+{
+ if (-1 == error_log_count) {
+ return MBED_ERROR_ITEM_NOT_FOUND;
+ }
+ core_util_critical_section_enter();
+ memcpy(error_ctx, &mbed_error_ctx_log[error_log_count % MBED_CONF_PLATFORM_ERROR_HIST_SIZE], sizeof(mbed_error_ctx));
+ core_util_critical_section_exit();
+
+ return MBED_SUCCESS;
+}
+
+int mbed_error_hist_get_count()
+{
+ return (error_log_count >= MBED_CONF_PLATFORM_ERROR_HIST_SIZE ? MBED_CONF_PLATFORM_ERROR_HIST_SIZE : error_log_count + 1);
+}
+
+mbed_error_status_t mbed_error_hist_reset()
+{
+ core_util_critical_section_enter();
+ error_log_count = -1;
+ core_util_critical_section_exit();
+
+ return MBED_SUCCESS;
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_error_hist.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_error_hist.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_HIST_H
+#define MBED_ERROR_HIST_H
+
+#ifndef MBED_CONF_PLATFORM_ERROR_HIST_SIZE
+#define MBED_CONF_PLATFORM_ERROR_HIST_SIZE 4
+#else
+#if MBED_CONF_PLATFORM_ERROR_HIST_SIZE == 0
+#define MBED_CONF_PLATFORM_ERROR_HIST_SIZE 1
+#endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Puts/Adds an error entry into the error history list
+ *
+ * @param error_ctx pointer to the mbed_error_ctx struct with the error context
+ * @return 0 or MBED_SUCCESS on success.
+ * MBED_ERROR_WRITE_FAILED if writing to file failed
+ * MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ *
+ */
+mbed_error_status_t mbed_error_hist_put(mbed_error_ctx *error_ctx);
+
+/*
+ * Reads the error entry from the error list with the specified index
+ *
+ * @param index Index of the error context to be retrieved. It starts from 0 and 0 is the oldest.
+ * @param error_ctx pointer to the mbed_error_ctx struct where the error context will be filled, this should be allocated by the caller
+ * @return 0 or MBED_SUCCESS on success.
+ * MBED_ERROR_WRITE_FAILED if writing to file failed
+ * MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ *
+ */
+mbed_error_status_t mbed_error_hist_get(int index, mbed_error_ctx *error_ctx);
+
+/*
+ * Gets a reference to the next error entry in the error log where in the error ctx can be filled in.
+ * Its like reserving the next error entry to fill in the error info
+ *
+ * @return Returns the pointer to the next error ctx entry
+ *
+ *
+ */
+mbed_error_ctx *mbed_error_hist_get_entry(void);
+
+/*
+ * Reads the last(latest) error entry from the error history
+ *
+ * @param error_ctx pointer to the mbed_error_ctx struct where the error context will be filled, this should be allocated by the caller
+ * @return 0 or MBED_SUCCESS on success.
+ * MBED_ERROR_WRITE_FAILED if writing to file failed
+ * MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ *
+ */
+mbed_error_status_t mbed_error_hist_get_last_error(mbed_error_ctx *error_ctx);
+
+/*
+ * Returns the number of error entries in the error history list
+ *
+ * @return Number of entries in the history list
+ *
+ *
+ */
+int mbed_error_hist_get_count(void);
+
+/*
+ * Resets the error log by resetting the number of errors to 0 and clears all previous errors in the history list
+ *
+ * @return 0 or MBED_SUCCESS on success.
+ * MBED_ERROR_WRITE_FAILED if writing to file failed
+ * MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ *
+ */
+mbed_error_status_t mbed_error_hist_reset(void);
+
+/*
+ * Saves the error log information to a file
+ *
+ * @param path path to the file in the filesystem
+ * @return 0 or MBED_SUCCESS on success.
+ * MBED_ERROR_WRITE_FAILED if writing to file failed
+ * MBED_ERROR_INVALID_ARGUMENT if path is not valid
+ *
+ * @note Filesystem support is required in order for this function to work.
+ *
+ */
+mbed_error_status_t mbed_save_error_hist(const char *path);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_interface.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_interface.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "platform/mbed_interface.h"
+
+#include "hal/gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "platform/mbed_semihost_api.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_toolchain.h"
+
+#if DEVICE_SEMIHOST
+
+// return true if a debugger is attached, indicating mbed interface is connected
+int mbed_interface_connected(void)
+{
+ return semihost_connected();
+}
+
+int mbed_interface_reset(void)
+{
+ if (mbed_interface_connected()) {
+ semihost_reset();
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+WEAK int mbed_interface_uid(char *uid)
+{
+ if (mbed_interface_connected()) {
+ return semihost_uid(uid); // Returns 0 if successful, -1 on failure
+ } else {
+ uid[0] = 0;
+ return -1;
+ }
+}
+
+int mbed_interface_disconnect(void)
+{
+ int res;
+ if (mbed_interface_connected()) {
+ if ((res = semihost_disabledebug()) != 0) {
+ return res;
+ }
+ while (mbed_interface_connected());
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+int mbed_interface_powerdown(void)
+{
+ int res;
+ if (mbed_interface_connected()) {
+ if ((res = semihost_powerdown()) != 0) {
+ return res;
+ }
+ while (mbed_interface_connected());
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+MBED_DEPRECATED_SINCE("mbed-os-5.9", "This function shouldn't be used in new code."
+ "For system reset funcionality use system_reset()")
+void mbed_reset(void)
+{
+ mbed_interface_reset();
+}
+
+WEAK int mbed_uid(char *uid)
+{
+ return mbed_interface_uid(uid);
+}
+#endif
+
+WEAK void mbed_mac_address(char *mac)
+{
+#if DEVICE_SEMIHOST
+ char uid[DEVICE_ID_LENGTH + 1];
+ int i;
+
+ // if we have a UID, extract the MAC
+ if (mbed_interface_uid(uid) == 0) {
+ char *p = uid;
+#if defined(DEVICE_MAC_OFFSET)
+ p += DEVICE_MAC_OFFSET;
+#endif
+ for (i = 0; i < 6; i++) {
+ int byte;
+ sscanf(p, "%2x", &byte);
+ mac[i] = byte;
+ p += 2;
+ }
+ mac[0] &= ~0x01; // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b)
+ } else { // else return a default MAC
+#endif
+ mac[0] = 0x00;
+ mac[1] = 0x02;
+ mac[2] = 0xF7;
+ mac[3] = 0xF0;
+ mac[4] = 0x00;
+ mac[5] = 0x00;
+#if DEVICE_SEMIHOST
+ }
+#endif
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_interface.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_interface.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,158 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_interface Network interface and other utility functions
+ * @{
+ */
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERFACE_H
+#define MBED_INTERFACE_H
+
+#include <stdarg.h>
+
+#include "device.h"
+
+/* Mbed interface mac address
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
+ * otherwise MAC_ADD_x are used.
+ */
+#define MBED_MAC_ADDR_INTERFACE 0x00
+#define MBED_MAC_ADDR_0 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_1 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_2 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_3 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_4 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_5 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+/**
+ * \defgroup platform_interface interface functions
+ * @{
+ */
+
+/** Functions to control the mbed interface
+ *
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
+ * system. These functions provide means to control the interface suing semihost
+ * calls it supports.
+ */
+
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
+ *
+ * @returns
+ * 1 if interface is connected,
+ * 0 otherwise
+ */
+int mbed_interface_connected(void);
+
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise (e.g. interface not present)
+ */
+int mbed_interface_reset(void);
+
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
+ * The interface will still support the USB serial aspect
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_disconnect(void);
+
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
+ * connected, also power down the interface. If the USB cable is connected, the interface
+ * will remain powered up and visible to the host
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_powerdown(void);
+
+/** This returns a string containing the 32-character UID of the mbed interface
+ * This is a weak function that can be overwritten if required
+ *
+ * @param uid A 33-byte array to write the null terminated 32-byte string
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_uid(char *uid);
+
+#endif
+
+/** This returns a unique 6-byte MAC address, based on the interface UID
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
+ *
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
+ * provide a MAC address.
+ *
+ * @param mac A 6-byte array to write the MAC address
+ */
+void mbed_mac_address(char *mac);
+
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
+ */
+void mbed_die(void);
+
+/** Print out an error message. This is typically called when
+ * handling a crash.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * @param format C string that contains data stream to be printed.
+ * Code snippets below show valid format.
+ *
+ * @code
+ * mbed_error_printf("Failed: %s, file: %s, line %d \n", expr, file, line);
+ * @endcode
+ *
+ */
+void mbed_error_printf(const char *format, ...);
+
+/** Print out an error message. Similar to mbed_error_printf
+ * but uses a va_list.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * @param format C string that contains data stream to be printed.
+ * @param arg Variable arguments list
+ *
+ */
+void mbed_error_vfprintf(const char *format, va_list arg);
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_lib.json
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_lib.json Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,77 @@
+{
+ "name": "platform",
+ "config": {
+ "stdio-convert-newlines": {
+ "help": "Enable conversion to standard newlines on stdin/stdout/stderr",
+ "value": false
+ },
+
+ "stdio-convert-tty-newlines": {
+ "help": "Enable conversion to standard newlines on any tty FILE stream",
+ "value": false
+ },
+
+ "stdio-buffered-serial": {
+ "help": "Use UARTSerial driver to obtain buffered serial I/O on stdin/stdout/stderr. If false, unbuffered serial_getc and serial_putc are used directly.",
+ "value": false
+ },
+
+ "stdio-baud-rate": {
+ "help": "Baud rate for stdio",
+ "value": 9600
+ },
+
+ "stdio-flush-at-exit": {
+ "help": "Enable or disable the flush of standard I/O's at exit.",
+ "value": true
+ },
+
+ "default-serial-baud-rate": {
+ "help": "Default baud rate for a Serial or RawSerial instance (if not specified in the constructor)",
+ "value": 9600
+ },
+
+ "force-non-copyable-error": {
+ "help": "Force compile time error when a NonCopyable object is copied",
+ "value": false
+ },
+
+ "poll-use-lowpower-timer": {
+ "help": "Enable use of low power timer class for poll(). May cause missing events.",
+ "value": false
+ },
+
+ "error-hist-enabled": {
+ "help": "Enable for error history tracking.",
+ "value": false
+ },
+
+ "error-hist-size": {
+ "help": "Set the number of most recent errors the system keeps in its history, needs error-hist-enabled set to true for this to work.",
+ "value": 4
+ },
+
+ "error-filename-capture-enabled": {
+ "help": "Enables capture of filename and line number as part of error context capture, this works only for debug and develop builds. On release builds, filename capture is always disabled",
+ "value": false
+ },
+
+ "error-all-threads-info": {
+ "help": "Reports all the threads in the system as part of error report.",
+ "value": false
+ },
+
+ "max-error-filename-len": {
+ "help": "Sets the maximum length of buffer used for capturing the filename in error context. This needs error-filename-capture-enabled feature.",
+ "value": 16
+ }
+ },
+ "target_overrides": {
+ "EFM32": {
+ "stdio-baud-rate": 115200
+ },
+ "EFR32": {
+ "stdio-baud-rate": 115200
+ }
+ }
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_mem_trace.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_mem_trace.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include "platform/mbed_mem_trace.h"
+#include "platform/mbed_critical.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+/******************************************************************************
+ * Internal variables, functions and helpers
+ *****************************************************************************/
+
+/* The callback function that will be called after a traced memory operations finishes. */
+static mbed_mem_trace_cb_t mem_trace_cb;
+/* 'trace_lock_count' guards "trace inside trace" situations (for example, the implementation
+ * of realloc() might call malloc() internally, and since malloc() is also traced, this could
+ * result in two calls to the callback function instead of one. */
+static uint8_t trace_lock_count;
+static SingletonPtr<PlatformMutex> mem_trace_mutex;
+
+#define TRACE_FIRST_LOCK() (trace_lock_count < 2)
+
+
+/******************************************************************************
+ * Public interface
+ *****************************************************************************/
+
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb)
+{
+ mem_trace_cb = cb;
+}
+
+void mbed_mem_trace_lock()
+{
+ mem_trace_mutex->lock();
+ trace_lock_count++;
+}
+
+void mbed_mem_trace_unlock()
+{
+ trace_lock_count--;
+ mem_trace_mutex->unlock();
+}
+
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller)
+{
+ if (mem_trace_cb) {
+ if (TRACE_FIRST_LOCK()) {
+ mem_trace_cb(MBED_MEM_TRACE_MALLOC, res, caller, size);
+ }
+ }
+ return res;
+}
+
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller)
+{
+ if (mem_trace_cb) {
+ if (TRACE_FIRST_LOCK()) {
+ mem_trace_cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size);
+ }
+ }
+ return res;
+}
+
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller)
+{
+ if (mem_trace_cb) {
+ if (TRACE_FIRST_LOCK()) {
+ mem_trace_cb(MBED_MEM_TRACE_CALLOC, res, caller, num, size);
+ }
+ }
+ return res;
+}
+
+void mbed_mem_trace_free(void *ptr, void *caller)
+{
+ if (mem_trace_cb) {
+ if (TRACE_FIRST_LOCK()) {
+ mem_trace_cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr);
+ }
+ }
+}
+
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...)
+{
+ va_list va;
+ size_t temp_s1, temp_s2;
+ void *temp_ptr;
+
+ va_start(va, caller);
+ switch (op) {
+ case MBED_MEM_TRACE_MALLOC:
+ temp_s1 = va_arg(va, size_t);
+ printf(MBED_MEM_DEFAULT_TRACER_PREFIX "m:%p;%p-%u\n", res, caller, temp_s1);
+ break;
+
+ case MBED_MEM_TRACE_REALLOC:
+ temp_ptr = va_arg(va, void *);
+ temp_s1 = va_arg(va, size_t);
+ printf(MBED_MEM_DEFAULT_TRACER_PREFIX "r:%p;%p-%p;%u\n", res, caller, temp_ptr, temp_s1);
+ break;
+
+ case MBED_MEM_TRACE_CALLOC:
+ temp_s1 = va_arg(va, size_t);
+ temp_s2 = va_arg(va, size_t);
+ printf(MBED_MEM_DEFAULT_TRACER_PREFIX "c:%p;%p-%u;%u\n", res, caller, temp_s1, temp_s2);
+ break;
+
+ case MBED_MEM_TRACE_FREE:
+ temp_ptr = va_arg(va, void *);
+ printf(MBED_MEM_DEFAULT_TRACER_PREFIX "f:%p;%p-%p\n", res, caller, temp_ptr);
+ break;
+
+ default:
+ printf("?\n");
+ }
+ va_end(va);
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_mem_trace.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_mem_trace.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,162 @@
+
+/** \addtogroup platform */
+/** @{*/
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_MEM_TRACE_H__
+#define __MBED_MEM_TRACE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/* Operation types for tracer */
+enum {
+ MBED_MEM_TRACE_MALLOC,
+ MBED_MEM_TRACE_REALLOC,
+ MBED_MEM_TRACE_CALLOC,
+ MBED_MEM_TRACE_FREE
+};
+
+/**
+ * \defgroup platform_mem_trace mem_trace functions
+ * @{
+ */
+
+/* Prefix for the output of the default tracer */
+#define MBED_MEM_DEFAULT_TRACER_PREFIX "#"
+
+/**
+ * Type of the callback used by the memory tracer. This callback is called when a memory
+ * allocation operation (malloc, realloc, calloc, free) is called and tracing is enabled
+ * for that memory allocation function.
+ *
+ * @param op the ID of the operation (MBED_MEM_TRACE_MALLOC, MBED_MEM_TRACE_REALLOC,
+ * MBED_MEM_TRACE_CALLOC or MBED_MEM_TRACE_FREE).
+ * @param res the result that the memory operation returned (NULL for 'free').
+ * @param caller the caller of the memory operation. Note that the value of 'caller' might be
+ * unreliable.
+ *
+ * The rest of the parameters passed 'mbed_mem_trace_cb_t' are the same as the memory operations
+ * that triggered its call (see 'man malloc' for details):
+ *
+ * - for malloc: cb(MBED_MEM_TRACE_MALLOC, res, caller, size).
+ * - for realloc: cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size).
+ * - for calloc: cb(MBED_MEM_TRACE_CALLOC, res, caller, nmemb, size).
+ * - for free: cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr).
+ */
+typedef void (*mbed_mem_trace_cb_t)(uint8_t op, void *res, void *caller, ...);
+
+/**
+ * Set the callback used by the memory tracer (use NULL for disable tracing).
+ *
+ * @param cb the callback to call on each memory operation.
+ */
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb);
+
+/**
+ * Trace lock.
+ * @note Locking prevent recursive tracing of malloc/free inside relloc/calloc
+ */
+void mbed_mem_trace_lock();
+
+/**
+ * Trace unlock.
+ */
+void mbed_mem_trace_unlock();
+
+/**
+ * Trace a call to 'malloc'.
+ * @param res the result of running 'malloc'.
+ * @param size the 'size' argument given to 'malloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller);
+
+/**
+ * Trace a call to 'realloc'.
+ * @param res the result of running 'realloc'.
+ * @param ptr the 'ptr' argument given to 'realloc'.
+ * @param size the 'size' argument given to 'realloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller);
+
+/**
+ * Trace a call to 'calloc'.
+ * @param res the result of running 'calloc'.
+ * @param num the 'nmemb' argument given to 'calloc'.
+ * @param size the 'size' argument given to 'calloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller);
+
+/**
+ * Trace a call to 'free'.
+ * @param ptr the 'ptr' argument given to 'free'.
+ * @param caller the caller of the memory operation.
+ */
+void mbed_mem_trace_free(void *ptr, void *caller);
+
+/**
+ * Default memory trace callback. DO NOT CALL DIRECTLY. It is meant to be used
+ * as the second argument of 'mbed_mem_trace_setup'.
+ *
+ * The default callback outputs trace data using 'printf', in a format that's
+ * easily parsable by an external tool. For each memory operation, the callback
+ * outputs a line that begins with "#<op>:<0xresult>;<0xcaller>-":
+ *
+ * @param op identifies the memory operation ('m' for 'malloc', 'r' for 'realloc',
+ * 'c' for 'calloc' and 'f' for 'free').
+ * @param res (base 16) is the result of the memor operation. This is always NULL
+ * for 'free', since 'free' doesn't return anything.
+ * @param caller (base 16) is the caller of the memory operation. Note that the value
+ * of 'caller' might be unreliable.
+ *
+ * The rest of the output depends on the operation being traced:
+ *
+ * - for 'malloc': 'size', where 'size' is the original argument to 'malloc'.
+ * - for 'realloc': '0xptr;size', where 'ptr' (base 16) and 'size' are the original arguments to 'realloc'.
+ * - for 'calloc': 'nmemb;size', where 'nmemb' and 'size' are the original arguments to 'calloc'.
+ * - for 'free': '0xptr', where 'ptr' (base 16) is the original argument to 'free'.
+ *
+ * Examples:
+ *
+ * - "#m:0x20003240;0x600d-50" encodes a 'malloc' that returned 0x20003240, was called
+ * by the instruction at 0x600D with a the 'size' argument equal to 50.
+ * - "#f:0x0;0x602f-0x20003240" encodes a 'free' that was called by the instruction at
+ * 0x602f with the 'ptr' argument equal to 0x20003240.
+ */
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...);
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif// #ifndef __MBED_MEM_TRACE_H__
+
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_mktime.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_mktime.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,193 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_mktime.h"
+
+/* Time constants. */
+#define SECONDS_BY_MINUTES 60
+#define MINUTES_BY_HOUR 60
+#define SECONDS_BY_HOUR (SECONDS_BY_MINUTES * MINUTES_BY_HOUR)
+#define HOURS_BY_DAY 24
+#define SECONDS_BY_DAY (SECONDS_BY_HOUR * HOURS_BY_DAY)
+#define LAST_VALID_YEAR 206
+
+/* Macros which will be used to determine if we are within valid range. */
+#define EDGE_TIMESTAMP_FULL_LEAP_YEAR_SUPPORT 3220095 // 7th of February 1970 at 06:28:15
+#define EDGE_TIMESTAMP_4_YEAR_LEAP_YEAR_SUPPORT 3133695 // 6th of February 1970 at 06:28:15
+
+/*
+ * 2 dimensional array containing the number of seconds elapsed before a given
+ * month.
+ * The second index map to the month while the first map to the type of year:
+ * - 0: non leap year
+ * - 1: leap year
+ */
+static const uint32_t seconds_before_month[2][12] = {
+ {
+ 0,
+ 31 * SECONDS_BY_DAY,
+ (31 + 28) *SECONDS_BY_DAY,
+ (31 + 28 + 31) *SECONDS_BY_DAY,
+ (31 + 28 + 31 + 30) *SECONDS_BY_DAY,
+ (31 + 28 + 31 + 30 + 31) *SECONDS_BY_DAY,
+ (31 + 28 + 31 + 30 + 31 + 30) *SECONDS_BY_DAY,
+ (31 + 28 + 31 + 30 + 31 + 30 + 31) *SECONDS_BY_DAY,
+ (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31) *SECONDS_BY_DAY,
+ (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30) *SECONDS_BY_DAY,
+ (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31) *SECONDS_BY_DAY,
+ (31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30) *SECONDS_BY_DAY,
+ },
+ {
+ 0,
+ 31 * SECONDS_BY_DAY,
+ (31 + 29) *SECONDS_BY_DAY,
+ (31 + 29 + 31) *SECONDS_BY_DAY,
+ (31 + 29 + 31 + 30) *SECONDS_BY_DAY,
+ (31 + 29 + 31 + 30 + 31) *SECONDS_BY_DAY,
+ (31 + 29 + 31 + 30 + 31 + 30) *SECONDS_BY_DAY,
+ (31 + 29 + 31 + 30 + 31 + 30 + 31) *SECONDS_BY_DAY,
+ (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31) *SECONDS_BY_DAY,
+ (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31 + 30) *SECONDS_BY_DAY,
+ (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31) *SECONDS_BY_DAY,
+ (31 + 29 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30) *SECONDS_BY_DAY,
+ }
+};
+
+bool _rtc_is_leap_year(int year, rtc_leap_year_support_t leap_year_support)
+{
+ /*
+ * since in practice, the value manipulated by this algorithm lie in the
+ * range: [70 : 206] the algorithm can be reduced to: year % 4 with exception for 200 (year 2100 is not leap year).
+ * The algorithm valid over the full range of value is:
+
+ year = 1900 + year;
+ if (year % 4) {
+ return false;
+ } else if (year % 100) {
+ return true;
+ } else if (year % 400) {
+ return false;
+ }
+ return true;
+
+ */
+ if (leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT && year == 200) {
+ return false; // 2100 is not a leap year
+ }
+
+ return (year) % 4 ? false : true;
+}
+
+bool _rtc_maketime(const struct tm *time, time_t *seconds, rtc_leap_year_support_t leap_year_support)
+{
+ if (seconds == NULL || time == NULL) {
+ return false;
+ }
+
+ /* Partial check for the upper bound of the range - check years only. Full check will be performed after the
+ * elapsed time since the beginning of the year is calculated.
+ */
+ if ((time->tm_year < 70) || (time->tm_year > LAST_VALID_YEAR)) {
+ return false;
+ }
+
+ uint32_t result = time->tm_sec;
+ result += time->tm_min * SECONDS_BY_MINUTES;
+ result += time->tm_hour * SECONDS_BY_HOUR;
+ result += (time->tm_mday - 1) * SECONDS_BY_DAY;
+ result += seconds_before_month[_rtc_is_leap_year(time->tm_year, leap_year_support)][time->tm_mon];
+
+ /* Check if we are within valid range. */
+ if (time->tm_year == LAST_VALID_YEAR) {
+ if ((leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT && result > EDGE_TIMESTAMP_FULL_LEAP_YEAR_SUPPORT) ||
+ (leap_year_support == RTC_4_YEAR_LEAP_YEAR_SUPPORT && result > EDGE_TIMESTAMP_4_YEAR_LEAP_YEAR_SUPPORT)) {
+ return false;
+ }
+ }
+
+ if (time->tm_year > 70) {
+ /* Valid in the range [70:206]. */
+ uint32_t count_of_leap_days = ((time->tm_year - 1) / 4) - (70 / 4);
+ if (leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT) {
+ if (time->tm_year > 200) {
+ count_of_leap_days--; // 2100 is not a leap year
+ }
+ }
+
+ result += (((time->tm_year - 70) * 365) + count_of_leap_days) * SECONDS_BY_DAY;
+ }
+
+ *seconds = result;
+
+ return true;
+}
+
+bool _rtc_localtime(time_t timestamp, struct tm *time_info, rtc_leap_year_support_t leap_year_support)
+{
+ if (time_info == NULL) {
+ return false;
+ }
+
+ uint32_t seconds = (uint32_t)timestamp;
+
+ time_info->tm_sec = seconds % 60;
+ seconds = seconds / 60; // timestamp in minutes
+ time_info->tm_min = seconds % 60;
+ seconds = seconds / 60; // timestamp in hours
+ time_info->tm_hour = seconds % 24;
+ seconds = seconds / 24; // timestamp in days;
+
+ /* Compute the weekday.
+ * The 1st of January 1970 was a Thursday which is equal to 4 in the weekday representation ranging from [0:6].
+ */
+ time_info->tm_wday = (seconds + 4) % 7;
+
+ /* Years start at 70. */
+ time_info->tm_year = 70;
+ while (true) {
+ if (_rtc_is_leap_year(time_info->tm_year, leap_year_support) && seconds >= 366) {
+ ++time_info->tm_year;
+ seconds -= 366;
+ } else if (!_rtc_is_leap_year(time_info->tm_year, leap_year_support) && seconds >= 365) {
+ ++time_info->tm_year;
+ seconds -= 365;
+ } else {
+ /* The remaining days are less than a years. */
+ break;
+ }
+ }
+
+ time_info->tm_yday = seconds;
+
+ /* Convert days into seconds and find the current month. */
+ seconds *= SECONDS_BY_DAY;
+ time_info->tm_mon = 11;
+ bool leap = _rtc_is_leap_year(time_info->tm_year, leap_year_support);
+ for (uint32_t i = 0; i < 12; ++i) {
+ if ((uint32_t) seconds < seconds_before_month[leap][i]) {
+ time_info->tm_mon = i - 1;
+ break;
+ }
+ }
+
+ /* Remove month from timestamp and compute the number of days.
+ * Note: unlike other fields, days are not 0 indexed.
+ */
+ seconds -= seconds_before_month[leap][time_info->tm_mon];
+ time_info->tm_mday = (seconds / SECONDS_BY_DAY) + 1;
+
+ return true;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_mktime.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_mktime.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,131 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_MKTIME_H
+#define MBED_MKTIME_H
+
+#include <time.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup platform_mktime mktime functions
+ * @{
+ */
+
+/* Time range across the whole 32-bit range should be supported which means that years in range 1970 - 2106 can be
+ * encoded. We have two types of RTC devices:
+ * a) RTCs which handles all leap years in the mentioned year range correctly. Leap year is determined by checking if
+ * the year counter value is divisible by 400, 100, and 4. No problem here.
+ * b) RTCs which handles leap years correctly up to 2100. The RTC does a simple bit comparison to see if the two
+ * lowest order bits of the year counter are zero. In this case 2100 year will be considered
+ * incorrectly as a leap year, so the last valid point in time will be 28.02.2100 23:59:59 and next day will be
+ * 29.02.2100 (invalid). So after 28.02.2100 the day counter will be off by a day.
+ */
+typedef enum {
+ RTC_FULL_LEAP_YEAR_SUPPORT,
+ RTC_4_YEAR_LEAP_YEAR_SUPPORT
+} rtc_leap_year_support_t;
+
+/** Compute if a year is a leap year or not.
+ *
+ * @param year The year to test it shall be in the range [70:206]. Year 0 is
+ * translated into year 1900 CE.
+ * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
+ * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
+ *
+ * @return true if the year in input is a leap year and false otherwise.
+ *
+ * @note For use by the HAL only
+ * @note Year 2100 is treated differently for devices with full leap year support and devices with
+ * partial leap year support. Devices with partial leap year support treats 2100 as a leap year.
+ */
+bool _rtc_is_leap_year(int year, rtc_leap_year_support_t leap_year_support);
+
+/* Convert a calendar time into time since UNIX epoch as a time_t.
+ *
+ * This function is a thread safe (partial) replacement for mktime. It is
+ * tailored around RTC peripherals needs and is not by any mean a complete
+ * replacement of mktime.
+ *
+ * @param time The calendar time to convert into a time_t since epoch.
+ * The fields from tm used for the computation are:
+ * - tm_sec
+ * - tm_min
+ * - tm_hour
+ * - tm_mday
+ * - tm_mon
+ * - tm_year
+ * Other fields are ignored and won't be renormalized by a call to this function.
+ * A valid calendar time is comprised between:
+ * the 1st of January 1970 at 00:00:00 to the 7th of February 2106 at 06:28:15.
+ * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
+ * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
+ * @param seconds holder for the result - calendar time as seconds since UNIX epoch.
+ *
+ * @return true on success, false if conversion error occurred.
+ *
+ * @note Leap seconds are not supported.
+ * @note Values in output range from 0 to UINT_MAX.
+ * @note Full and partial leap years support.
+ * @note For use by the HAL only
+ */
+bool _rtc_maketime(const struct tm *time, time_t *seconds, rtc_leap_year_support_t leap_year_support);
+
+/* Convert a given time in seconds since epoch into calendar time.
+ *
+ * This function is a thread safe (partial) replacement for localtime. It is
+ * tailored around RTC peripherals specification and is not by any means a
+ * complete of localtime.
+ *
+ * @param timestamp The time (in seconds) to convert into calendar time. Valid
+ * input are in the range [0 : UINT32_MAX].
+ * @param calendar_time Pointer to the object which will contain the result of
+ * the conversion. The tm fields filled by this function are:
+ * - tm_sec
+ * - tm_min
+ * - tm_hour
+ * - tm_mday
+ * - tm_mon
+ * - tm_year
+ * - tm_wday
+ * - tm_yday
+ * The object remains untouched if the time in input is invalid.
+ * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
+ * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
+ * @return true if the conversion was successful, false otherwise.
+ *
+ * @note For use by the HAL only.
+ * @note Full and partial leap years support.
+ */
+bool _rtc_localtime(time_t timestamp, struct tm *time_info, rtc_leap_year_support_t leap_year_support);
+
+/** @}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBED_MKTIME_H */
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_poll.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_poll.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,92 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_poll.h"
+#include "FileHandle.h"
+#if MBED_CONF_RTOS_PRESENT
+#include "rtos/Kernel.h"
+#include "rtos/Thread.h"
+using namespace rtos;
+#else
+#include "Timer.h"
+#include "LowPowerTimer.h"
+#endif
+
+namespace mbed {
+
+// timeout -1 forever, or milliseconds
+int poll(pollfh fhs[], unsigned nfhs, int timeout)
+{
+ /**
+ * TODO Proper wake-up mechanism.
+ * In order to correctly detect availability of read/write a FileHandle, we needed
+ * a select or poll mechanisms. We opted for poll as POSIX defines in
+ * http://pubs.opengroup.org/onlinepubs/009695399/functions/poll.html Currently,
+ * mbed::poll() just spins and scans filehandles looking for any events we are
+ * interested in. In future, his spinning behaviour will be replaced with
+ * condition variables.
+ */
+#if MBED_CONF_RTOS_PRESENT
+ uint64_t start_time = 0;
+ if (timeout > 0) {
+ start_time = Kernel::get_ms_count();
+ }
+#define TIME_ELAPSED() int64_t(Kernel::get_ms_count() - start_time)
+#else
+#if MBED_CONF_PLATFORM_POLL_USE_LOWPOWER_TIMER
+ LowPowerTimer timer;
+#else
+ Timer timer;
+#endif
+ if (timeout > 0) {
+ timer.start();
+ }
+#define TIME_ELAPSED() timer.read_ms()
+#endif // MBED_CONF_RTOS_PRESENT
+
+ int count = 0;
+ for (;;) {
+ /* Scan the file handles */
+ for (unsigned n = 0; n < nfhs; n++) {
+ FileHandle *fh = fhs[n].fh;
+ short mask = fhs[n].events | POLLERR | POLLHUP | POLLNVAL;
+ if (fh) {
+ fhs[n].revents = fh->poll(mask) & mask;
+ } else {
+ fhs[n].revents = POLLNVAL;
+ }
+ if (fhs[n].revents) {
+ count++;
+ }
+ }
+
+ if (count) {
+ break;
+ }
+
+ /* Nothing selected - this is where timeout handling would be needed */
+ if (timeout == 0 || (timeout > 0 && TIME_ELAPSED() > timeout)) {
+ break;
+ }
+#ifdef MBED_CONF_RTOS_PRESENT
+ // TODO - proper blocking
+ // wait for condition variable, wait queue whatever here
+ rtos::Thread::wait(1);
+#endif
+ }
+ return count;
+}
+
+} // namespace mbed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_poll.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_poll.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,60 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_POLL_H
+#define MBED_POLL_H
+
+#define POLLIN 0x0001 ///< Data may be read without blocking
+#define POLLOUT 0x0010 ///< Data may be written without blocking
+#define POLLERR 0x1000 ///< An error has occurred on the device or stream
+#define POLLHUP 0x2000 ///< The device has been disconnected
+#define POLLNVAL 0x4000 ///< The specified file handle value is invalid
+
+namespace mbed {
+
+class FileHandle;
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_poll poll functions
+ * @{
+ */
+
+struct pollfh {
+ FileHandle *fh;
+ short events;
+ short revents;
+};
+
+/** A mechanism to multiplex input/output over a set of file handles(file descriptors).
+ * For every file handle provided, poll() examines it for any events registered for that particular
+ * file handle.
+ *
+ * @param fhs an array of PollFh struct carrying a FileHandle and bitmasks of events
+ * @param nfhs number of file handles
+ * @param timeout timer value to timeout or -1 for loop forever
+ *
+ * @return number of file handles selected (for which revents is non-zero). 0 if timed out with nothing selected. -1 for error.
+ */
+int poll(pollfh fhs[], unsigned nfhs, int timeout);
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif //MBED_POLL_H
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_power_mgmt.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_power_mgmt.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,245 @@
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_power_mgmt Power management functions
+ * @{
+ */
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_POWER_MGMT_H
+#define MBED_POWER_MGMT_H
+
+#include "sleep_api.h"
+#include "mbed_toolchain.h"
+#include "hal/ticker_api.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Sleep manager API
+ * The sleep manager provides API to automatically select sleep mode.
+ *
+ * There are two sleep modes:
+ * - sleep
+ * - deepsleep
+ *
+ * Use locking/unlocking deepsleep for drivers that depend on features that
+ * are not allowed (=disabled) during the deepsleep. For instance, high frequency
+ * clocks.
+ *
+ * Example:
+ * @code
+ *
+ * void driver::handler()
+ * {
+ * if (_sensor.get_event()) {
+ * // any event - we are finished, unlock the deepsleep
+ * sleep_manager_unlock_deep_sleep();
+ * _callback();
+ * }
+ * }
+ *
+ * int driver::measure(event_t event, callback_t& callback)
+ * {
+ * _callback = callback;
+ * sleep_manager_lock_deep_sleep();
+ * // start async transaction, we are waiting for an event
+ * return _sensor.start(event, callback);
+ * }
+ * @endcode
+ */
+#ifdef MBED_SLEEP_TRACING_ENABLED
+
+void sleep_tracker_lock(const char *const filename, int line);
+void sleep_tracker_unlock(const char *const filename, int line);
+
+#define sleep_manager_lock_deep_sleep() \
+ do \
+ { \
+ sleep_manager_lock_deep_sleep_internal(); \
+ sleep_tracker_lock(MBED_FILENAME, __LINE__); \
+ } while (0);
+
+#define sleep_manager_unlock_deep_sleep() \
+ do \
+ { \
+ sleep_manager_unlock_deep_sleep_internal(); \
+ sleep_tracker_unlock(MBED_FILENAME, __LINE__); \
+ } while (0);
+
+#else
+
+#define sleep_manager_lock_deep_sleep() \
+ sleep_manager_lock_deep_sleep_internal()
+
+#define sleep_manager_unlock_deep_sleep() \
+ sleep_manager_unlock_deep_sleep_internal()
+
+#endif // MBED_SLEEP_TRACING_ENABLED
+
+/** Lock the deep sleep mode
+ *
+ * This locks the automatic deep mode selection.
+ * sleep_manager_sleep_auto() will ignore deepsleep mode if
+ * this function is invoked at least once (the internal counter is non-zero)
+ *
+ * Use this locking mechanism for interrupt driven API that are
+ * running in the background and deepsleep could affect their functionality
+ *
+ * The lock is a counter, can be locked up to USHRT_MAX
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_lock_deep_sleep_internal(void);
+
+/** Unlock the deep sleep mode
+ *
+ * Use unlocking in pair with sleep_manager_lock_deep_sleep().
+ *
+ * The lock is a counter, should be equally unlocked as locked
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_unlock_deep_sleep_internal(void);
+
+/** Get the status of deep sleep allowance for a target
+ *
+ * @return true if a target can go to deepsleep, false otherwise
+ */
+bool sleep_manager_can_deep_sleep(void);
+
+/** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based
+ * on the deepsleep locking counter
+ *
+ * This function is IRQ and thread safe
+ *
+ * @note
+ * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger
+ * to be active for debug modes.
+ *
+ */
+void sleep_manager_sleep_auto(void);
+
+/** Send the microcontroller to sleep
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined).
+ * @note This function will be a noop while uVisor is in use.
+ * @note This function will be a noop if the following conditions are met:
+ * - The RTOS is present
+ * - The processor turn off the Systick clock during sleep
+ * - The target does not implement tickless mode
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+static inline void sleep(void)
+{
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+#if DEVICE_SLEEP
+#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS)
+ sleep_manager_sleep_auto();
+#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */
+#endif /* DEVICE_SLEEP */
+#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
+}
+
+/** Send the microcontroller to deep sleep
+ *
+ * @deprecated
+ * Do not use this function. Applications should use sleep() API which puts the system in deepsleep mode if supported.
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined)
+ * @note This function will be a noop while uVisor is in use.
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep. This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+
+MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()")
+static inline void deepsleep(void)
+{
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+#if DEVICE_SLEEP
+ sleep_manager_sleep_auto();
+#endif /* DEVICE_SLEEP */
+#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
+}
+
+/** Resets the processor and most of the sub-system
+ *
+ * @note Does not affect the debug sub-system
+ */
+static inline void system_reset(void)
+{
+ NVIC_SystemReset();
+}
+
+/** Provides the time spent in sleep mode since boot.
+ *
+ * @return Time spent in sleep
+ * @note Works only if platform supports LP ticker.
+ */
+us_timestamp_t mbed_time_sleep(void);
+
+/** Provides the time spent in deep sleep mode since boot.
+ *
+ * @return Time spent in deep sleep
+ * @note Works only if platform supports LP ticker.
+ */
+us_timestamp_t mbed_time_deepsleep(void);
+
+/** Provides the time spent in idle mode since boot.
+ *
+ * @return Idle thread time.
+ * @note Works only if platform supports LP ticker.
+ */
+us_timestamp_t mbed_time_idle(void);
+
+/** Provides the time since the system is up i.e. boot.
+ *
+ * @return System uptime.
+ * @note Works only if platform supports LP ticker.
+ */
+us_timestamp_t mbed_uptime(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_preprocessor.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_preprocessor.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,86 @@
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_preprocessor preprocessor macros
+ * @{
+ */
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PREPROCESSOR_H
+#define MBED_PREPROCESSOR_H
+
+
+/** MBED_CONCAT
+ * Concatenate tokens together
+ *
+ * @note
+ * Expands tokens before concatenation
+ *
+ * @code
+ * // Creates a unique label based on the line number
+ * int MBED_CONCAT(UNIQUE_LABEL_, __LINE__) = 1;
+ * @endcode
+ */
+#define MBED_CONCAT(a, b) MBED_CONCAT_(a, b)
+#define MBED_CONCAT_(a, b) a##b
+
+/** MBED_STRINGIFY
+ * Converts tokens into strings
+ *
+ * @note
+ * Expands tokens before stringification
+ *
+ * @code
+ * // Creates a string based on the parameters
+ * const char *c = MBED_STRINGIFY(This is a ridiculous way to create a string)
+ * @endcode
+ */
+#define MBED_STRINGIFY(a) MBED_STRINGIFY_(a)
+#define MBED_STRINGIFY_(a) #a
+
+/** MBED_STRLEN
+ * Reports string token length
+ *
+ * @note
+ * Expands tokens before calculating length
+ *
+ * @code
+ * // Get string length
+ * const int len = MBED_STRLEN("Get the length")
+ * @endcode
+ */
+#define MBED_STRLEN(a) MBED_STRLEN_(a)
+#define MBED_STRLEN_(a) (sizeof(a) - 1)
+
+/** MBED_COUNT_VA_ARGS(...)
+ * Reports number of tokens passed
+ *
+ * @note
+ * Token limit is 16
+ *
+ * @code
+ * // Get number of arguments
+ * const int count = MBED_COUNT_VA_ARGS("Address 0x%x, Data[0] = %d Data[1] = %d", 0x20001234, 10, 20)
+ * @endcode
+ */
+#define MBED_COUNT_VA_ARGS(...) GET_NTH_ARG_(__VA_ARGS__, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
+#define GET_NTH_ARG_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, N, ...) N
+
+#endif
+
+/** @}*/
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_retarget.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_retarget.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1641 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <time.h>
+#include "platform/platform.h"
+#include "platform/FilePath.h"
+#include "hal/serial_api.h"
+#include "hal/us_ticker_api.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_semihost_api.h"
+#include "platform/mbed_interface.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_stats.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_poll.h"
+#include "platform/PlatformMutex.h"
+#include "drivers/UARTSerial.h"
+#include "us_ticker_api.h"
+#include "lp_ticker_api.h"
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#ifndef SSIZE_MAX
+#define SSIZE_MAX INT_MAX
+#endif
+#include <stdio.h>
+#include <errno.h>
+#include "platform/mbed_retarget.h"
+
+static SingletonPtr<PlatformMutex> _mutex;
+
+#if defined(__ARMCC_VERSION)
+# if __ARMCC_VERSION >= 6010050
+# include <arm_compat.h>
+# endif
+# include <rt_sys.h>
+# include <rt_misc.h>
+# include <stdint.h>
+# define PREFIX(x) _sys##x
+# define OPEN_MAX _SYS_OPEN
+# ifdef __MICROLIB
+# pragma import(__use_full_stdio)
+# endif
+
+#elif defined(__ICCARM__)
+# include <yfuns.h>
+# define PREFIX(x) _##x
+# define OPEN_MAX 16
+
+# define STDIN_FILENO 0
+# define STDOUT_FILENO 1
+# define STDERR_FILENO 2
+
+#else
+# include <sys/syslimits.h>
+# define PREFIX(x) x
+#endif
+
+#define FILE_HANDLE_RESERVED ((FileHandle*)0xFFFFFFFF)
+
+/**
+ * Macros for setting console flow control.
+ */
+#define CONSOLE_FLOWCONTROL_RTS 1
+#define CONSOLE_FLOWCONTROL_CTS 2
+#define CONSOLE_FLOWCONTROL_RTSCTS 3
+#define mbed_console_concat_(x) CONSOLE_FLOWCONTROL_##x
+#define mbed_console_concat(x) mbed_console_concat_(x)
+#define CONSOLE_FLOWCONTROL mbed_console_concat(MBED_CONF_TARGET_CONSOLE_UART_FLOW_CONTROL)
+
+using namespace mbed;
+
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+// Before version 5.03, we were using a patched version of microlib with proper names
+extern const char __stdin_name[] = ":tt";
+extern const char __stdout_name[] = ":tt";
+extern const char __stderr_name[] = ":tt";
+
+#else
+extern const char __stdin_name[] = "/stdin";
+extern const char __stdout_name[] = "/stdout";
+extern const char __stderr_name[] = "/stderr";
+#endif
+
+unsigned char *mbed_heap_start = 0;
+uint32_t mbed_heap_size = 0;
+
+/* newlib has the filehandle field in the FILE struct as a short, so
+ * we can't just return a Filehandle* from _open and instead have to
+ * put it in a filehandles array and return the index into that array
+ */
+static FileHandle *filehandles[OPEN_MAX] = { FILE_HANDLE_RESERVED, FILE_HANDLE_RESERVED, FILE_HANDLE_RESERVED };
+static char stdio_in_prev[OPEN_MAX];
+static char stdio_out_prev[OPEN_MAX];
+static SingletonPtr<PlatformMutex> filehandle_mutex;
+
+namespace mbed {
+void mbed_set_unbuffered_stream(std::FILE *_file);
+
+void remove_filehandle(FileHandle *file)
+{
+ filehandle_mutex->lock();
+ /* Remove all open filehandles for this */
+ for (unsigned int fh_i = 0; fh_i < sizeof(filehandles) / sizeof(*filehandles); fh_i++) {
+ if (filehandles[fh_i] == file) {
+ filehandles[fh_i] = NULL;
+ }
+ }
+ filehandle_mutex->unlock();
+}
+}
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+
+/* Private FileHandle to implement backwards-compatible functionality of
+ * direct HAL serial access for default stdin/stdout/stderr.
+ * This is not a particularly well-behaved FileHandle for a stream, which
+ * is why it's not public. People should be using UARTSerial.
+ */
+class DirectSerial : public FileHandle {
+public:
+ DirectSerial(PinName tx, PinName rx, int baud);
+ virtual ssize_t write(const void *buffer, size_t size);
+ virtual ssize_t read(void *buffer, size_t size);
+ virtual off_t seek(off_t offset, int whence = SEEK_SET)
+ {
+ return -ESPIPE;
+ }
+ virtual off_t size()
+ {
+ return -EINVAL;
+ }
+ virtual int isatty()
+ {
+ return true;
+ }
+ virtual int close()
+ {
+ return 0;
+ }
+ virtual short poll(short events) const;
+};
+
+DirectSerial::DirectSerial(PinName tx, PinName rx, int baud)
+{
+ if (stdio_uart_inited) {
+ return;
+ }
+ serial_init(&stdio_uart, tx, rx);
+ serial_baud(&stdio_uart, baud);
+#if CONSOLE_FLOWCONTROL == CONSOLE_FLOWCONTROL_RTS
+ serial_set_flow_control(&stdio_uart, FlowControlRTS, STDIO_UART_RTS, NC);
+#elif CONSOLE_FLOWCONTROL == CONSOLE_FLOWCONTROL_CTS
+ serial_set_flow_control(&stdio_uart, FlowControlCTS, NC, STDIO_UART_CTS);
+#elif CONSOLE_FLOWCONTROL == CONSOLE_FLOWCONTROL_RTSCTS
+ serial_set_flow_control(&stdio_uart, FlowControlRTSCTS, STDIO_UART_RTS, STDIO_UART_CTS);
+#endif
+}
+
+ssize_t DirectSerial::write(const void *buffer, size_t size)
+{
+ const unsigned char *buf = static_cast<const unsigned char *>(buffer);
+ for (size_t i = 0; i < size; i++) {
+ serial_putc(&stdio_uart, buf[i]);
+ }
+ return size;
+}
+
+ssize_t DirectSerial::read(void *buffer, size_t size)
+{
+ unsigned char *buf = static_cast<unsigned char *>(buffer);
+ if (size == 0) {
+ return 0;
+ }
+ buf[0] = serial_getc(&stdio_uart);
+ return 1;
+}
+
+short DirectSerial::poll(short events) const
+{
+ short revents = 0;
+ if ((events & POLLIN) && serial_readable(&stdio_uart)) {
+ revents |= POLLIN;
+ }
+ if ((events & POLLOUT) && serial_writable(&stdio_uart)) {
+ revents |= POLLOUT;
+ }
+ return revents;
+}
+#endif
+
+class Sink : public FileHandle {
+public:
+ virtual ssize_t write(const void *buffer, size_t size);
+ virtual ssize_t read(void *buffer, size_t size);
+ virtual off_t seek(off_t offset, int whence = SEEK_SET)
+ {
+ return ESPIPE;
+ }
+ virtual off_t size()
+ {
+ return -EINVAL;
+ }
+ virtual int isatty()
+ {
+ return true;
+ }
+ virtual int close()
+ {
+ return 0;
+ }
+};
+
+ssize_t Sink::write(const void *buffer, size_t size)
+{
+ // Just swallow the data - this is historical non-DEVICE_SERIAL behaviour
+ return size;
+}
+
+ssize_t Sink::read(void *buffer, size_t size)
+{
+ // Produce 1 zero byte - historical behaviour returned 1 without touching
+ // the buffer
+ unsigned char *buf = static_cast<unsigned char *>(buffer);
+ buf[0] = 0;
+ return 1;
+}
+
+
+MBED_WEAK FileHandle *mbed::mbed_target_override_console(int fd)
+{
+ return NULL;
+}
+
+MBED_WEAK FileHandle *mbed::mbed_override_console(int fd)
+{
+ return NULL;
+}
+
+static FileHandle *default_console()
+{
+#if DEVICE_SERIAL
+# if MBED_CONF_PLATFORM_STDIO_BUFFERED_SERIAL
+ static UARTSerial console(STDIO_UART_TX, STDIO_UART_RX, MBED_CONF_PLATFORM_STDIO_BAUD_RATE);
+# if CONSOLE_FLOWCONTROL == CONSOLE_FLOWCONTROL_RTS
+ console.set_flow_control(SerialBase::RTS, STDIO_UART_RTS, NC);
+# elif CONSOLE_FLOWCONTROL == CONSOLE_FLOWCONTROL_CTS
+ console.set_flow_control(SerialBase::CTS, NC, STDIO_UART_CTS);
+# elif CONSOLE_FLOWCONTROL == CONSOLE_FLOWCONTROL_RTSCTS
+ console.set_flow_control(SerialBase::RTSCTS, STDIO_UART_RTS, STDIO_UART_CTS);
+# endif
+# else
+ static DirectSerial console(STDIO_UART_TX, STDIO_UART_RX, MBED_CONF_PLATFORM_STDIO_BAUD_RATE);
+# endif
+#else // DEVICE_SERIAL
+ static Sink console;
+#endif
+ return &console;
+}
+
+/* Locate the default console for stdout, stdin, stderr */
+static FileHandle *get_console(int fd)
+{
+ FileHandle *fh = mbed_override_console(fd);
+ if (fh) {
+ return fh;
+ }
+ fh = mbed_target_override_console(fd);
+ if (fh) {
+ return fh;
+ }
+ return default_console();
+}
+
+/* Deal with the fact C library may not _open descriptors 0, 1, 2 - auto bind */
+static FileHandle *get_fhc(int fd)
+{
+ if (fd >= OPEN_MAX) {
+ return NULL;
+ }
+ FileHandle *fh = filehandles[fd];
+ if (fh == FILE_HANDLE_RESERVED && fd < 3) {
+ filehandles[fd] = fh = get_console(fd);
+ }
+ return fh;
+}
+
+/**
+ * Sets errno when file opening fails.
+ * Wipes out the filehandle too.
+ *
+ * @param error is a negative error code returned from an mbed function and
+ * will be negated to store a positive error code in errno
+ */
+static int handle_open_errors(int error, unsigned filehandle_idx)
+{
+ errno = -error;
+ // Free file handle
+ filehandles[filehandle_idx] = NULL;
+ return -1;
+}
+
+static inline int openflags_to_posix(int openflags)
+{
+ int posix = openflags;
+#ifdef __ARMCC_VERSION
+ if (openflags & OPEN_PLUS) {
+ posix = O_RDWR;
+ } else if (openflags & OPEN_W) {
+ posix = O_WRONLY;
+ } else if (openflags & OPEN_A) {
+ posix = O_WRONLY | O_APPEND;
+ } else {
+ posix = O_RDONLY;
+ }
+ /* a, w, a+, w+ all create if file does not already exist */
+ if (openflags & (OPEN_A | OPEN_W)) {
+ posix |= O_CREAT;
+ }
+ /* w and w+ truncate */
+ if (openflags & OPEN_W) {
+ posix |= O_TRUNC;
+ }
+#elif defined(__ICCARM__)
+ switch (openflags & _LLIO_RDWRMASK) {
+ case _LLIO_RDONLY:
+ posix = O_RDONLY;
+ break;
+ case _LLIO_WRONLY:
+ posix = O_WRONLY;
+ break;
+ case _LLIO_RDWR :
+ posix = O_RDWR ;
+ break;
+ }
+ if (openflags & _LLIO_CREAT) {
+ posix |= O_CREAT;
+ }
+ if (openflags & _LLIO_APPEND) {
+ posix |= O_APPEND;
+ }
+ if (openflags & _LLIO_TRUNC) {
+ posix |= O_TRUNC;
+ }
+#elif defined(TOOLCHAIN_GCC)
+ posix &= ~O_BINARY;
+#endif
+ return posix;
+}
+
+static int reserve_filehandle()
+{
+ // find the first empty slot in filehandles, after the slots reserved for stdin/stdout/stderr
+ filehandle_mutex->lock();
+ int fh_i;
+ for (fh_i = 3; fh_i < OPEN_MAX; fh_i++) {
+ /* Take a next free filehandle slot available. */
+ if (filehandles[fh_i] == NULL) {
+ break;
+ }
+ }
+ if (fh_i >= OPEN_MAX) {
+ /* Too many file handles have been opened */
+ errno = EMFILE;
+ filehandle_mutex->unlock();
+ return -1;
+ }
+ filehandles[fh_i] = FILE_HANDLE_RESERVED;
+ filehandle_mutex->unlock();
+
+ return fh_i;
+}
+
+int mbed::bind_to_fd(FileHandle *fh)
+{
+ int fildes = reserve_filehandle();
+ if (fildes < 0) {
+ return fildes;
+ }
+
+ filehandles[fildes] = fh;
+ stdio_in_prev[fildes] = 0;
+ stdio_out_prev[fildes] = 0;
+
+ return fildes;
+}
+
+static int unbind_from_fd(int fd, FileHandle *fh)
+{
+ if (filehandles[fd] == fh) {
+ filehandles[fd] = NULL;
+ return 0;
+ } else {
+ errno = EBADF;
+ return -1;
+ }
+}
+
+#ifndef __IAR_SYSTEMS_ICC__
+/* IAR provides fdopen itself */
+extern "C" std::FILE *fdopen(int fildes, const char *mode)
+{
+ // This is to avoid scanf and the bloat it brings.
+ char buf[1 + sizeof fildes]; /* @(integer) */
+ MBED_STATIC_ASSERT(sizeof buf == 5, "Integers should be 4 bytes.");
+ buf[0] = '@';
+ memcpy(buf + 1, &fildes, sizeof fildes);
+
+ std::FILE *stream = std::fopen(buf, mode);
+ /* newlib-nano doesn't appear to ever call _isatty itself, so
+ * happily fully buffers an interactive stream. Deal with that here.
+ */
+ if (stream && isatty(fildes)) {
+ mbed_set_unbuffered_stream(stream);
+ }
+ return stream;
+}
+#endif
+
+namespace mbed {
+std::FILE *fdopen(FileHandle *fh, const char *mode)
+{
+ // First reserve the integer file descriptor
+ int fd = bind_to_fd(fh);
+ if (!fd) {
+ return NULL;
+ }
+ // Then bind that to the C stream. If successful, C library
+ // takes ownership and responsibility to close.
+ std::FILE *stream = ::fdopen(fd, mode);
+ if (!stream) {
+ unbind_from_fd(fd, fh);
+ }
+ return stream;
+}
+}
+
+/* @brief standard c library fopen() retargeting function.
+ *
+ * This function is invoked by the standard c library retargeting to handle fopen()
+ *
+ * @return
+ * On success, a valid FILEHANDLE is returned.
+ * On failure, -1 is returned and errno is set to an appropriate value e.g.
+ * ENOENT file not found (default errno setting)
+ * EMFILE the maximum number of open files was exceeded.
+ *
+ * */
+extern "C" FILEHANDLE PREFIX(_open)(const char *name, int openflags)
+{
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+#if !defined(MBED_CONF_RTOS_PRESENT)
+ // valid only for mbed 2
+ // for ulib, this is invoked after RAM init, prior c++
+ // used as hook, as post stack/heap is not active there
+ extern void mbed_copy_nvic(void);
+ extern void mbed_sdk_init(void);
+
+ static int mbed_sdk_inited = 0;
+ if (!mbed_sdk_inited) {
+ mbed_copy_nvic();
+ mbed_sdk_init();
+ mbed_sdk_inited = 1;
+ }
+#endif
+ // Before version 5.03, we were using a patched version of microlib with proper names
+ // This is the workaround that the microlib author suggested us
+ static int n = 0;
+ if (std::strcmp(name, ":tt") == 0 && n < 3) {
+ return n++;
+ }
+#else
+ /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
+ */
+ if (std::strcmp(name, __stdin_name) == 0) {
+ get_fhc(STDIN_FILENO);
+ return STDIN_FILENO;
+ } else if (std::strcmp(name, __stdout_name) == 0) {
+ get_fhc(STDOUT_FILENO);
+ return STDOUT_FILENO;
+ } else if (std::strcmp(name, __stderr_name) == 0) {
+ get_fhc(STDERR_FILENO);
+ return STDERR_FILENO;
+ }
+#endif
+#ifndef __IAR_SYSTEMS_ICC__
+ /* FILENAME: "@(integer)" gives an already-allocated descriptor */
+ if (name[0] == '@') {
+ int fd;
+ memcpy(&fd, name + 1, sizeof fd);
+ return fd;
+ }
+#endif
+ return open(name, openflags_to_posix(openflags));
+}
+
+extern "C" int open(const char *name, int oflag, ...)
+{
+ int fildes = reserve_filehandle();
+ if (fildes < 0) {
+ return fildes;
+ }
+
+ FileHandle *res = NULL;
+ FilePath path(name);
+
+ if (!path.exists()) {
+ /* The first part of the filename (between first 2 '/') is not a
+ * registered mount point in the namespace.
+ */
+ return handle_open_errors(-ENODEV, fildes);
+ }
+
+ if (path.isFile()) {
+ res = path.file();
+ } else {
+ FileSystemHandle *fs = path.fileSystem();
+ if (fs == NULL) {
+ return handle_open_errors(-ENODEV, fildes);
+ }
+ int err = fs->open(&res, path.fileName(), oflag);
+ if (err) {
+ return handle_open_errors(err, fildes);
+ }
+ }
+
+ filehandles[fildes] = res;
+ stdio_in_prev[fildes] = 0;
+ stdio_out_prev[fildes] = 0;
+
+ return fildes;
+}
+
+extern "C" int PREFIX(_close)(FILEHANDLE fh)
+{
+ return close(fh);
+}
+
+extern "C" int close(int fildes)
+{
+ FileHandle *fhc = get_fhc(fildes);
+ filehandles[fildes] = NULL;
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ int err = fhc->close();
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+static bool convert_crlf(int fd)
+{
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_TTY_NEWLINES
+ return isatty(fd);
+#elif MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+ return fd < 3 && isatty(fd);
+#else
+ return false;
+#endif
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t __write(int fh, const unsigned char *buffer, size_t length)
+{
+#else
+extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode)
+{
+#endif
+
+#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED && defined(MBED_CONF_RTOS_PRESENT)
+ if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PROHIBITED_IN_ISR_CONTEXT), "Error - writing to a file in an ISR or critical section\r\n", fh);
+ }
+#endif
+
+ if (length > SSIZE_MAX) {
+ errno = EINVAL;
+ return -1;
+ }
+
+ ssize_t slength = length;
+ ssize_t written = 0;
+
+ if (convert_crlf(fh)) {
+ // local prev is previous in buffer during seek
+ // stdio_out_prev[fh] is last thing actually written
+ char prev = stdio_out_prev[fh];
+ // Seek for '\n' without preceding '\r'; if found flush
+ // preceding and insert '\r'. Continue until end of input.
+ for (ssize_t cur = 0; cur < slength; cur++) {
+ if (buffer[cur] == '\n' && prev != '\r') {
+ ssize_t r;
+ // flush stuff preceding the \n
+ if (cur > written) {
+ r = write(fh, buffer + written, cur - written);
+ if (r < 0) {
+ return -1;
+ }
+ written += r;
+ if (written < cur) {
+ // For some reason, didn't write all - give up now
+ goto finish;
+ }
+ stdio_out_prev[fh] = prev;
+ }
+ // insert a \r now, leaving the \n still to be written
+ r = write(fh, "\r", 1);
+ if (r < 0) {
+ return -1;
+ }
+ if (r < 1) {
+ goto finish;
+ }
+ stdio_out_prev[fh] = '\r';
+ }
+ prev = buffer[cur];
+ }
+ }
+
+ // Flush remaining from conversion, or the whole thing if no conversion
+ if (written < slength) {
+ ssize_t r = write(fh, buffer + written, slength - written);
+ if (r < 0) {
+ return -1;
+ }
+ written += r;
+ if (written > 0) {
+ stdio_out_prev[fh] = buffer[written - 1];
+ }
+ }
+
+finish:
+#ifdef __ARMCC_VERSION
+ if (written >= 0) {
+ return slength - written;
+ } else {
+ return written;
+ }
+#else
+ return written;
+#endif
+}
+
+extern "C" ssize_t write(int fildes, const void *buf, size_t length)
+{
+
+ FileHandle *fhc = get_fhc(fildes);
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ ssize_t ret = fhc->write(buf, length);
+ if (ret < 0) {
+ errno = -ret;
+ return -1;
+ } else {
+ return ret;
+ }
+}
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+extern "C" void PREFIX(_exit)(int return_code)
+{
+ while (1) {}
+}
+
+extern "C" void _ttywrch(int ch)
+{
+ char c = ch;
+ write(STDOUT_FILENO, &c, 1);
+}
+#endif
+
+#if defined(__ICCARM__)
+extern "C" size_t __read(int fh, unsigned char *buffer, size_t length)
+{
+#else
+extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode)
+{
+#endif
+
+#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED && defined(MBED_CONF_RTOS_PRESENT)
+ if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PROHIBITED_IN_ISR_CONTEXT), "Error - reading from a file in an ISR or critical section\r\n", fh);
+ }
+#endif
+
+ if (length > SSIZE_MAX) {
+ errno = EINVAL;
+ return -1;
+ }
+
+ ssize_t bytes_read = 0;
+
+ if (convert_crlf(fh)) {
+ while (true) {
+ char c;
+ ssize_t r = read(fh, &c, 1);
+ if (r < 0) {
+ return -1;
+ }
+ if (r == 0) {
+ return bytes_read;
+ }
+ if ((c == '\r' && stdio_in_prev[fh] != '\n') ||
+ (c == '\n' && stdio_in_prev[fh] != '\r')) {
+ stdio_in_prev[fh] = c;
+ *buffer = '\n';
+ break;
+ } else if ((c == '\r' && stdio_in_prev[fh] == '\n') ||
+ (c == '\n' && stdio_in_prev[fh] == '\r')) {
+ stdio_in_prev[fh] = c;
+ continue;
+ } else {
+ stdio_in_prev[fh] = c;
+ *buffer = c;
+ break;
+ }
+ }
+ bytes_read = 1;
+ } else {
+ bytes_read = read(fh, buffer, length);
+ }
+
+#ifdef __ARMCC_VERSION
+ if (bytes_read < 0) {
+ return -1;
+ } else if (bytes_read == 0) {
+ return 0x80000000 | length; // weird EOF indication
+ } else {
+ return (ssize_t)length - bytes_read;
+ }
+#else
+ return bytes_read;
+#endif
+}
+
+extern "C" ssize_t read(int fildes, void *buf, size_t length)
+{
+
+ FileHandle *fhc = get_fhc(fildes);
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ ssize_t ret = fhc->read(buf, length);
+ if (ret < 0) {
+ errno = -ret;
+ return -1;
+ } else {
+ return ret;
+ }
+}
+
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_istty)(FILEHANDLE fh)
+#else
+extern "C" int _isatty(FILEHANDLE fh)
+#endif
+{
+ return isatty(fh);
+}
+
+extern "C" int isatty(int fildes)
+{
+ FileHandle *fhc = get_fhc(fildes);
+ if (fhc == NULL) {
+ errno = EBADF;
+ return 0;
+ }
+
+ int tty = fhc->isatty();
+ if (tty < 0) {
+ errno = -tty;
+ return 0;
+ } else {
+ return tty;
+ }
+}
+
+extern "C"
+#if defined(__ARMCC_VERSION)
+int _sys_seek(FILEHANDLE fh, long offset)
+#elif defined(__ICCARM__)
+long __lseek(int fh, long offset, int whence)
+#else
+int _lseek(FILEHANDLE fh, int offset, int whence)
+#endif
+{
+#if defined(__ARMCC_VERSION)
+ int whence = SEEK_SET;
+#endif
+
+ off_t off = lseek(fh, offset, whence);
+ // Assuming INT_MAX = LONG_MAX, so we don't care about prototype difference
+ if (off > INT_MAX) {
+ errno = EOVERFLOW;
+ return -1;
+ }
+ return off;
+}
+
+extern "C" off_t lseek(int fildes, off_t offset, int whence)
+{
+ FileHandle *fhc = get_fhc(fildes);
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ off_t off = fhc->seek(offset, whence);
+ if (off < 0) {
+ errno = -off;
+ return -1;
+ }
+ return off;
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_ensure)(FILEHANDLE fh)
+{
+ return fsync(fh);
+}
+#endif
+
+extern "C" int fsync(int fildes)
+{
+ FileHandle *fhc = get_fhc(fildes);
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ int err = fhc->sync();
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" long PREFIX(_flen)(FILEHANDLE fh)
+{
+ FileHandle *fhc = get_fhc(fh);
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ off_t size = fhc->size();
+ if (size < 0) {
+ errno = -size;
+ return -1;
+ }
+ if (size > LONG_MAX) {
+ errno = EOVERFLOW;
+ return -1;
+ }
+ return size;
+}
+
+extern "C" char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern "C" MBED_WEAK __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+extern "C" __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
+ return _mbed_user_setup_stackheap(R0, R1, R2, R3);
+}
+
+#endif
+
+
+#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
+extern "C" int _fstat(int fh, struct stat *st)
+{
+ return fstat(fh, st);
+}
+#endif
+
+extern "C" int fstat(int fildes, struct stat *st)
+{
+ FileHandle *fhc = get_fhc(fildes);
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ st->st_mode = fhc->isatty() ? S_IFCHR : S_IFREG;
+ st->st_size = fhc->size();
+ return 0;
+}
+
+extern "C" int fcntl(int fildes, int cmd, ...)
+{
+ FileHandle *fhc = get_fhc(fildes);
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ switch (cmd) {
+ case F_GETFL: {
+ int flags = 0;
+ if (fhc->is_blocking()) {
+ flags |= O_NONBLOCK;
+ }
+ return flags;
+ }
+ case F_SETFL: {
+ va_list ap;
+ va_start(ap, cmd);
+ int flags = va_arg(ap, int);
+ va_end(ap);
+ int ret = fhc->set_blocking(flags & O_NONBLOCK);
+ if (ret < 0) {
+ errno = -ret;
+ return -1;
+ }
+ return 0;
+ }
+
+ default: {
+ errno = EINVAL;
+ return -1;
+ }
+ }
+}
+
+extern "C" int poll(struct pollfd fds[], nfds_t nfds, int timeout)
+{
+ if (nfds > OPEN_MAX) {
+ errno = EINVAL;
+ return -1;
+ }
+
+ struct mbed::pollfh fhs[OPEN_MAX];
+ for (nfds_t n = 0; n < nfds; n++) {
+ // Underlying FileHandle poll returns POLLNVAL if given NULL, so
+ // we don't need to take special action.
+ fhs[n].fh = get_fhc(fds[n].fd);
+ fhs[n].events = fds[n].events;
+ }
+ int ret = poll(fhs, nfds, timeout);
+ for (nfds_t n = 0; n < nfds; n++) {
+ fds[n].revents = fhs[n].revents;
+ }
+ return ret;
+}
+
+namespace std {
+extern "C" int remove(const char *path)
+{
+ FilePath fp(path);
+ FileSystemHandle *fs = fp.fileSystem();
+ if (fs == NULL) {
+ errno = ENODEV;
+ return -1;
+ }
+
+ int err = fs->remove(fp.fileName());
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" int rename(const char *oldname, const char *newname)
+{
+ FilePath fpOld(oldname);
+ FilePath fpNew(newname);
+ FileSystemHandle *fsOld = fpOld.fileSystem();
+ FileSystemHandle *fsNew = fpNew.fileSystem();
+
+ if (fsOld == NULL) {
+ errno = ENODEV;
+ return -1;
+ }
+
+ /* rename only if both files are on the same FS */
+ if (fsOld != fsNew) {
+ errno = EXDEV;
+ return -1;
+ }
+
+ int err = fsOld->rename(fpOld.fileName(), fpNew.fileName());
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" char *tmpnam(char *s)
+{
+ errno = EBADF;
+ return NULL;
+}
+
+extern "C" FILE *tmpfile()
+{
+ errno = EBADF;
+ return NULL;
+}
+} // namespace std
+
+#ifdef __ARMCC_VERSION
+extern "C" char *_sys_command_string(char *cmd, int len)
+{
+ return NULL;
+}
+#endif
+
+extern "C" DIR *opendir(const char *path)
+{
+ FilePath fp(path);
+ FileSystemHandle *fs = fp.fileSystem();
+ if (fs == NULL) {
+ errno = ENODEV;
+ return NULL;
+ }
+
+ DirHandle *dir;
+ int err = fs->open(&dir, fp.fileName());
+ if (err < 0) {
+ errno = -err;
+ return NULL;
+ }
+
+ return dir;
+}
+
+extern "C" struct dirent *readdir(DIR *dir)
+{
+ static struct dirent ent;
+ int err = dir->read(&ent);
+ if (err < 1) {
+ if (err < 0) {
+ errno = -err;
+ }
+ return NULL;
+ }
+
+ return &ent;
+}
+
+extern "C" int closedir(DIR *dir)
+{
+ int err = dir->close();
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" void rewinddir(DIR *dir)
+{
+ dir->rewind();
+}
+
+extern "C" off_t telldir(DIR *dir)
+{
+ return dir->tell();
+}
+
+extern "C" void seekdir(DIR *dir, off_t off)
+{
+ dir->seek(off);
+}
+
+extern "C" int mkdir(const char *path, mode_t mode)
+{
+ FilePath fp(path);
+ FileSystemHandle *fs = fp.fileSystem();
+ if (fs == NULL) {
+ errno = ENODEV;
+ return -1;
+ }
+
+ int err = fs->mkdir(fp.fileName(), mode);
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" int stat(const char *path, struct stat *st)
+{
+ FilePath fp(path);
+ FileSystemHandle *fs = fp.fileSystem();
+ if (fs == NULL) {
+ errno = ENODEV;
+ return -1;
+ }
+
+ int err = fs->stat(fp.fileName(), st);
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" int statvfs(const char *path, struct statvfs *buf)
+{
+ FilePath fp(path);
+ FileSystemHandle *fs = fp.fileSystem();
+ if (fs == NULL) {
+ errno = ENODEV;
+ return -1;
+ }
+
+ int err = fs->statvfs(fp.fileName(), buf);
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+#if defined(TOOLCHAIN_GCC)
+/* prevents the exception handling name demangling code getting pulled in */
+#include "mbed_error.h"
+namespace __gnu_cxx {
+void __verbose_terminate_handler()
+{
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_CLIB_EXCEPTION), "Exception", 0);
+}
+}
+extern "C" WEAK void __cxa_pure_virtual(void);
+extern "C" WEAK void __cxa_pure_virtual(void)
+{
+ exit(1);
+}
+
+#endif
+
+// Provide implementation of _sbrk (low-level dynamic memory allocation
+// routine) for GCC_ARM which compares new heap pointer with MSP instead of
+// SP. This make it compatible with RTX RTOS thread stacks.
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
+
+#if defined(TARGET_CORTEX_A)
+extern "C" uint32_t __HeapLimit;
+#endif
+
+// Turn off the errno macro and use actual global variable instead.
+#undef errno
+extern "C" int errno;
+
+// Dynamic memory allocation related syscall.
+#if defined(TWO_RAM_REGIONS)
+
+// Overwrite _sbrk() to support two region model (heap and stack are two distinct regions).
+// __wrap__sbrk() is implemented in:
+// TARGET_STM32L4 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4/l4_retarget.c
+extern "C" void *__wrap__sbrk(int incr);
+extern "C" caddr_t _sbrk(int incr)
+{
+ return (caddr_t) __wrap__sbrk(incr);
+}
+#else
+// Linker defined symbol used by _sbrk to indicate where heap should start.
+extern "C" uint32_t __end__;
+// Weak attribute allows user to override, e.g. to use external RAM for dynamic memory.
+extern "C" WEAK caddr_t _sbrk(int incr)
+{
+ static unsigned char *heap = (unsigned char *)&__end__;
+ unsigned char *prev_heap = heap;
+ unsigned char *new_heap = heap + incr;
+
+#if defined(TARGET_CORTEX_A)
+ if (new_heap >= (unsigned char *)&__HeapLimit) { /* __HeapLimit is end of heap section */
+#else
+ if (new_heap >= (unsigned char *)__get_MSP()) {
+#endif
+ errno = ENOMEM;
+ return (caddr_t) -1;
+ }
+
+ // Additional heap checking if set
+ if (mbed_heap_size && (new_heap >= mbed_heap_start + mbed_heap_size)) {
+ errno = ENOMEM;
+ return (caddr_t) -1;
+ }
+
+ heap = new_heap;
+ return (caddr_t) prev_heap;
+}
+#endif
+#endif
+
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
+extern "C" void _exit(int return_code)
+{
+#else
+namespace std {
+extern "C" void exit(int return_code)
+{
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+#if MBED_CONF_PLATFORM_STDIO_FLUSH_AT_EXIT
+ fflush(stdout);
+ fflush(stderr);
+#endif
+#endif
+
+#if DEVICE_SEMIHOST
+ if (mbed_interface_connected()) {
+ semihost_exit();
+ }
+#endif
+ if (return_code) {
+ mbed_die();
+ }
+
+ while (1);
+}
+
+#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CR)
+} //namespace std
+#endif
+
+#if defined(TOOLCHAIN_ARM) || defined(TOOLCHAIN_GCC)
+
+// This series of function disable the registration of global destructors
+// in a dynamic table which will be called when the application exit.
+// In mbed, program never exit properly, it dies.
+// More informations about this topic for ARMCC here:
+// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/6449.html
+extern "C" {
+ int __aeabi_atexit(void *object, void (*dtor)(void * /*this*/), void *handle)
+ {
+ return 1;
+ }
+
+ int __cxa_atexit(void (*dtor)(void * /*this*/), void *object, void *handle)
+ {
+ return 1;
+ }
+
+ void __cxa_finalize(void *handle)
+ {
+ }
+
+} // end of extern "C"
+
+#endif
+
+
+#if defined(TOOLCHAIN_GCC)
+
+/*
+ * Depending on how newlib is configured, it is often not enough to define
+ * __aeabi_atexit, __cxa_atexit and __cxa_finalize in order to override the
+ * behavior regarding the registration of handlers with atexit.
+ *
+ * To overcome this limitation, exit and atexit are overriden here.
+ */
+extern "C" {
+
+ /**
+ * @brief Retarget of exit for GCC.
+ * @details Unlike the standard version, this function doesn't call any function
+ * registered with atexit before calling _exit.
+ */
+ void __wrap_exit(int return_code)
+ {
+ _exit(return_code);
+ }
+
+ /**
+ * @brief Retarget atexit from GCC.
+ * @details This function will always fail and never register any handler to be
+ * called at exit.
+ */
+ int __wrap_atexit(void (*func)())
+ {
+ return 1;
+ }
+
+}
+
+#endif
+
+
+
+namespace mbed {
+
+void mbed_set_unbuffered_stream(std::FILE *_file)
+{
+#if defined (__ICCARM__)
+ char buf[2];
+ std::setvbuf(_file, buf, _IONBF, NULL);
+#else
+ setbuf(_file, NULL);
+#endif
+}
+
+int mbed_getc(std::FILE *_file)
+{
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ < 8000000)
+ /*This is only valid for unbuffered streams*/
+ int res = std::fgetc(_file);
+ if (res >= 0) {
+ _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+ _file->_Rend = _file->_Wend;
+ _file->_Next = _file->_Wend;
+ }
+ return res;
+#else
+ return std::fgetc(_file);
+#endif
+}
+
+char *mbed_gets(char *s, int size, std::FILE *_file)
+{
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ < 8000000)
+ /*This is only valid for unbuffered streams*/
+ char *str = fgets(s, size, _file);
+ if (str != NULL) {
+ _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+ _file->_Rend = _file->_Wend;
+ _file->_Next = _file->_Wend;
+ }
+ return str;
+#else
+ return std::fgets(s, size, _file);
+#endif
+}
+
+} // namespace mbed
+
+#if defined (__ICCARM__)
+// Stub out locks when an rtos is not present
+extern "C" WEAK void __iar_system_Mtxinit(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxdst(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxunlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxinit(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxdst(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxunlock(__iar_Rmtx *mutex) {}
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ >= 8000000)
+#pragma section="__iar_tls$$DATA"
+extern "C" WEAK void *__aeabi_read_tp(void)
+{
+ // Thread Local storage is not supported, using main thread memory for errno
+ return __section_begin("__iar_tls$$DATA");
+}
+#endif
+#elif defined(__CC_ARM)
+// Do nothing
+#elif defined (__GNUC__)
+struct _reent;
+// Stub out locks when an rtos is not present
+extern "C" WEAK void __rtos_malloc_lock(struct _reent *_r) {}
+extern "C" WEAK void __rtos_malloc_unlock(struct _reent *_r) {}
+extern "C" WEAK void __rtos_env_lock(struct _reent *_r) {}
+extern "C" WEAK void __rtos_env_unlock(struct _reent *_r) {}
+
+extern "C" void __malloc_lock(struct _reent *_r)
+{
+ __rtos_malloc_lock(_r);
+}
+
+extern "C" void __malloc_unlock(struct _reent *_r)
+{
+ __rtos_malloc_unlock(_r);
+}
+
+extern "C" void __env_lock(struct _reent *_r)
+{
+ __rtos_env_lock(_r);
+}
+
+extern "C" void __env_unlock(struct _reent *_r)
+{
+ __rtos_env_unlock(_r);
+}
+
+#endif
+
+#if defined (__GNUC__) || defined(__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+
+#define CXA_GUARD_INIT_DONE (1 << 0)
+#define CXA_GUARD_INIT_IN_PROGRESS (1 << 1)
+#define CXA_GUARD_MASK (CXA_GUARD_INIT_DONE | CXA_GUARD_INIT_IN_PROGRESS)
+
+extern "C" int __cxa_guard_acquire(int *guard_object_p)
+{
+ uint8_t *guard_object = (uint8_t *)guard_object_p;
+ if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) {
+ return 0;
+ }
+ singleton_lock();
+ if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) {
+ singleton_unlock();
+ return 0;
+ }
+ MBED_ASSERT(0 == (*guard_object & CXA_GUARD_MASK));
+ *guard_object = *guard_object | CXA_GUARD_INIT_IN_PROGRESS;
+ return 1;
+}
+
+extern "C" void __cxa_guard_release(int *guard_object_p)
+{
+ uint8_t *guard_object = (uint8_t *)guard_object_p;
+ MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK));
+ *guard_object = (*guard_object & ~CXA_GUARD_MASK) | CXA_GUARD_INIT_DONE;
+ singleton_unlock();
+}
+
+extern "C" void __cxa_guard_abort(int *guard_object_p)
+{
+ uint8_t *guard_object = (uint8_t *)guard_object_p;
+ MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK));
+ *guard_object = *guard_object & ~CXA_GUARD_INIT_IN_PROGRESS;
+ singleton_unlock();
+}
+
+#endif
+
+#if defined(MBED_MEM_TRACING_ENABLED) && (defined(__CC_ARM) || defined(__ICCARM__) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)))
+
+// If the memory tracing is enabled, the wrappers in mbed_alloc_wrappers.cpp
+// provide the implementation for these. Note: this needs to use the wrappers
+// instead of malloc()/free() as the caller address would point to wrappers,
+// not the caller of "new" or "delete".
+extern "C" void *malloc_wrapper(size_t size, const void *caller);
+extern "C" void free_wrapper(void *ptr, const void *caller);
+
+void *operator new (std::size_t count)
+{
+ void *buffer = malloc_wrapper(count, MBED_CALLER_ADDR());
+ if (NULL == buffer) {
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OUT_OF_MEMORY), "Operator new out of memory\r\n", count);
+ }
+ return buffer;
+}
+
+void *operator new[](std::size_t count)
+{
+ void *buffer = malloc_wrapper(count, MBED_CALLER_ADDR());
+ if (NULL == buffer) {
+ error("Operator new[] out of memory\r\n");
+ }
+ return buffer;
+}
+
+void *operator new (std::size_t count, const std::nothrow_t &tag)
+{
+ return malloc_wrapper(count, MBED_CALLER_ADDR());
+}
+
+void *operator new[](std::size_t count, const std::nothrow_t &tag)
+{
+ return malloc_wrapper(count, MBED_CALLER_ADDR());
+}
+
+void operator delete (void *ptr)
+{
+ free_wrapper(ptr, MBED_CALLER_ADDR());
+}
+void operator delete[](void *ptr)
+{
+ free_wrapper(ptr, MBED_CALLER_ADDR());
+}
+
+#elif defined(MBED_MEM_TRACING_ENABLED) && defined(__GNUC__)
+
+#include <reent.h>
+
+extern "C" void *malloc_wrapper(struct _reent *r, size_t size, void *caller);
+extern "C" void free_wrapper(struct _reent *r, void *ptr, void *caller);
+
+void *operator new (std::size_t count)
+{
+ void *buffer = malloc_wrapper(_REENT, count, MBED_CALLER_ADDR());
+ if (NULL == buffer) {
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OUT_OF_MEMORY), "Operator new out of memory\r\n", count);
+ }
+ return buffer;
+}
+
+void *operator new[](std::size_t count)
+{
+ void *buffer = malloc_wrapper(_REENT, count, MBED_CALLER_ADDR());
+ if (NULL == buffer) {
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OUT_OF_MEMORY), "Operator new out of memory\r\n", count);
+ }
+ return buffer;
+}
+
+void *operator new (std::size_t count, const std::nothrow_t &tag)
+{
+ return malloc_wrapper(_REENT, count, MBED_CALLER_ADDR());
+}
+
+void *operator new[](std::size_t count, const std::nothrow_t &tag)
+{
+ return malloc_wrapper(_REENT, count, MBED_CALLER_ADDR());
+}
+
+void operator delete (void *ptr)
+{
+ free_wrapper(_REENT, ptr, MBED_CALLER_ADDR());
+}
+
+void operator delete[](void *ptr)
+{
+ free_wrapper(_REENT, ptr, MBED_CALLER_ADDR());
+}
+
+#else
+
+void *operator new (std::size_t count)
+{
+ void *buffer = malloc(count);
+ if (NULL == buffer) {
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OUT_OF_MEMORY), "Operator new out of memory\r\n", count);
+ }
+ return buffer;
+}
+
+void *operator new[](std::size_t count)
+{
+ void *buffer = malloc(count);
+ if (NULL == buffer) {
+ MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OUT_OF_MEMORY), "Operator new[] out of memory\r\n", count);
+ }
+ return buffer;
+}
+
+void *operator new (std::size_t count, const std::nothrow_t &tag)
+{
+ return malloc(count);
+}
+
+void *operator new[](std::size_t count, const std::nothrow_t &tag)
+{
+ return malloc(count);
+}
+
+void operator delete (void *ptr)
+{
+ free(ptr);
+}
+void operator delete[](void *ptr)
+{
+ free(ptr);
+}
+
+#endif
+
+/* @brief standard c library clock() function.
+ *
+ * This function returns the number of clock ticks elapsed since the start of the program.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @return
+ * the number of clock ticks elapsed since the start of the program.
+ *
+ * */
+extern "C" clock_t clock()
+{
+ _mutex->lock();
+ clock_t t = ticker_read(get_us_ticker_data());
+ t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+ _mutex->unlock();
+ return t;
+}
+
+// temporary - Default to 1MHz at 32 bits if target does not have us_ticker_get_info
+MBED_WEAK const ticker_info_t *us_ticker_get_info()
+{
+ static const ticker_info_t info = {
+ 1000000,
+ 32
+ };
+ return &info;
+}
+
+// temporary - Default to 1MHz at 32 bits if target does not have lp_ticker_get_info
+MBED_WEAK const ticker_info_t *lp_ticker_get_info()
+{
+ static const ticker_info_t info = {
+ 1000000,
+ 32
+ };
+ return &info;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_retarget.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_retarget.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,582 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef RETARGET_H
+#define RETARGET_H
+
+#if __cplusplus
+#include <cstdio>
+#else
+#include <stdio.h>
+#endif //__cplusplus
+#include <stdint.h>
+#include <stddef.h>
+
+/* Include logic for errno so we can get errno defined but not bring in error_t,
+ * including errno here prevents an include later, which would redefine our
+ * error codes
+ */
+#ifndef __error_t_defined
+#define __error_t_defined 1
+#include <errno.h>
+#undef __error_t_defined
+#else
+#include <errno.h>
+#endif
+
+/* We can get the following standard types from sys/types for gcc, but we
+ * need to define the types ourselves for the other compilers that normally
+ * target embedded systems */
+typedef signed int ssize_t; ///< Signed size type, usually encodes negative errors
+typedef signed long off_t; ///< Offset in a data stream
+typedef unsigned int nfds_t; ///< Number of file descriptors
+typedef unsigned long long fsblkcnt_t; ///< Count of file system blocks
+#if defined(__ARMCC_VERSION) || !defined(__GNUC__)
+typedef unsigned int mode_t; ///< Mode for opening files
+typedef unsigned int dev_t; ///< Device ID type
+typedef unsigned long ino_t; ///< File serial number
+typedef unsigned int nlink_t; ///< Number of links to a file
+typedef unsigned int uid_t; ///< User ID
+typedef unsigned int gid_t; ///< Group ID
+#endif
+
+/* Flags for open() and fcntl(GETFL/SETFL)
+ * At present, fcntl only supports reading and writing O_NONBLOCK
+ */
+#define O_RDONLY 0 ///< Open for reading
+#define O_WRONLY 1 ///< Open for writing
+#define O_RDWR 2 ///< Open for reading and writing
+#define O_NONBLOCK 0x0004 ///< Non-blocking mode
+#define O_APPEND 0x0008 ///< Set file offset to end of file prior to each write
+#define O_CREAT 0x0200 ///< Create file if it does not exist
+#define O_TRUNC 0x0400 ///< Truncate file to zero length
+#define O_EXCL 0x0800 ///< Fail if file exists
+#define O_BINARY 0x8000 ///< Open file in binary mode
+
+#define O_ACCMODE (O_RDONLY|O_WRONLY|O_RDWR)
+
+#define NAME_MAX 255 ///< Maximum size of a name in a file path
+
+#define STDIN_FILENO 0
+#define STDOUT_FILENO 1
+#define STDERR_FILENO 2
+
+#include <time.h>
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_retarget Retarget functions
+ * @{
+ */
+
+/* DIR declarations must also be here */
+#if __cplusplus
+namespace mbed {
+
+class FileHandle;
+class DirHandle;
+
+/** Targets may implement this to change stdin, stdout, stderr.
+ *
+ * If the application hasn't provided mbed_override_console, this is called
+ * to give the target a chance to specify a FileHandle for the console.
+ *
+ * If this is not provided or returns NULL, the console will be:
+ * - UARTSerial if configuration option "platform.stdio-buffered-serial" is
+ * true and the target has DEVICE_SERIAL;
+ * - Raw HAL serial via serial_getc and serial_putc if
+ * "platform.stdio-buffered-serial" is false and the target has DEVICE_SERIAL;
+ * - stdout/stderr will be a sink and stdin will input a stream of 0s if the
+ * target does not have DEVICE_SERIAL.
+ *
+ * @param fd file descriptor - STDIN_FILENO, STDOUT_FILENO or STDERR_FILENO
+ * @return pointer to FileHandle to override normal stream otherwise NULL
+ */
+FileHandle *mbed_target_override_console(int fd);
+
+/** Applications may implement this to change stdin, stdout, stderr.
+ *
+ * This hook gives the application a chance to specify a custom FileHandle
+ * for the console.
+ *
+ * If this is not provided or returns NULL, the console will be specified
+ * by mbed_target_override_console, else will default to serial - see
+ * mbed_target_override_console for more details.
+ *
+ * Example:
+ * @code
+ * FileHandle* mbed::mbed_override_console(int) {
+ * static UARTSerial my_serial(D0, D1);
+ * return &my_serial;
+ * }
+ * @endcode
+
+ * @param fd file descriptor - STDIN_FILENO, STDOUT_FILENO or STDERR_FILENO
+ * @return pointer to FileHandle to override normal stream otherwise NULL
+ */
+FileHandle *mbed_override_console(int fd);
+
+}
+
+typedef mbed::DirHandle DIR;
+#else
+typedef struct Dir DIR;
+#endif
+
+/* The intent of this section is to unify the errno error values to match
+ * the POSIX definitions for the GCC_ARM, ARMCC and IAR compilers. This is
+ * necessary because the ARMCC/IAR errno.h, or sys/stat.h are missing some
+ * symbol definitions used by the POSIX filesystem API to return errno codes.
+ * Note also that ARMCC errno.h defines some symbol values differently from
+ * the GCC_ARM/IAR/standard POSIX definitions. The definitions guard against
+ * this and future changes by changing the symbol definition as shown below.
+ */
+#undef EPERM
+#define EPERM 1 /* Operation not permitted */
+#undef ENOENT
+#define ENOENT 2 /* No such file or directory */
+#undef ESRCH
+#define ESRCH 3 /* No such process */
+#undef EINTR
+#define EINTR 4 /* Interrupted system call */
+#undef EIO
+#define EIO 5 /* I/O error */
+#undef ENXIO
+#define ENXIO 6 /* No such device or address */
+#undef E2BIG
+#define E2BIG 7 /* Argument list too long */
+#undef ENOEXEC
+#define ENOEXEC 8 /* Exec format error */
+#undef EBADF
+#define EBADF 9 /* Bad file number */
+#undef ECHILD
+#define ECHILD 10 /* No child processes */
+#undef EAGAIN
+#define EAGAIN 11 /* Try again */
+#undef ENOMEM
+#define ENOMEM 12 /* Out of memory */
+#undef EACCES
+#define EACCES 13 /* Permission denied */
+#undef EFAULT
+#define EFAULT 14 /* Bad address */
+#undef ENOTBLK
+#define ENOTBLK 15 /* Block device required */
+#undef EBUSY
+#define EBUSY 16 /* Device or resource busy */
+#undef EEXIST
+#define EEXIST 17 /* File exists */
+#undef EXDEV
+#define EXDEV 18 /* Cross-device link */
+#undef ENODEV
+#define ENODEV 19 /* No such device */
+#undef ENOTDIR
+#define ENOTDIR 20 /* Not a directory */
+#undef EISDIR
+#define EISDIR 21 /* Is a directory */
+#undef EINVAL
+#define EINVAL 22 /* Invalid argument */
+#undef ENFILE
+#define ENFILE 23 /* File table overflow */
+#undef EMFILE
+#define EMFILE 24 /* Too many open files */
+#undef ENOTTY
+#define ENOTTY 25 /* Not a typewriter */
+#undef ETXTBSY
+#define ETXTBSY 26 /* Text file busy */
+#undef EFBIG
+#define EFBIG 27 /* File too large */
+#undef ENOSPC
+#define ENOSPC 28 /* No space left on device */
+#undef ESPIPE
+#define ESPIPE 29 /* Illegal seek */
+#undef EROFS
+#define EROFS 30 /* Read-only file system */
+#undef EMLINK
+#define EMLINK 31 /* Too many links */
+#undef EPIPE
+#define EPIPE 32 /* Broken pipe */
+#undef EDOM
+#define EDOM 33 /* Math argument out of domain of func */
+#undef ERANGE
+#define ERANGE 34 /* Math result not representable */
+#undef EDEADLK
+#define EDEADLK 35 /* Resource deadlock would occur */
+#undef ENAMETOOLONG
+#define ENAMETOOLONG 36 /* File name too long */
+#undef ENOLCK
+#define ENOLCK 37 /* No record locks available */
+#undef ENOSYS
+#define ENOSYS 38 /* Function not implemented */
+#undef ENOTEMPTY
+#define ENOTEMPTY 39 /* Directory not empty */
+#undef ELOOP
+#define ELOOP 40 /* Too many symbolic links encountered */
+#undef EWOULDBLOCK
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#undef ENOMSG
+#define ENOMSG 42 /* No message of desired type */
+#undef EIDRM
+#define EIDRM 43 /* Identifier removed */
+#undef ECHRNG
+#define ECHRNG 44 /* Channel number out of range */
+#undef EL2NSYNC
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#undef EL3HLT
+#define EL3HLT 46 /* Level 3 halted */
+#undef EL3RST
+#define EL3RST 47 /* Level 3 reset */
+#undef ELNRNG
+#define ELNRNG 48 /* Link number out of range */
+#undef EUNATCH
+#define EUNATCH 49 /* Protocol driver not attached */
+#undef ENOCSI
+#define ENOCSI 50 /* No CSI structure available */
+#undef EL2HLT
+#define EL2HLT 51 /* Level 2 halted */
+#undef EBADE
+#define EBADE 52 /* Invalid exchange */
+#undef EBADR
+#define EBADR 53 /* Invalid request descriptor */
+#undef EXFULL
+#define EXFULL 54 /* Exchange full */
+#undef ENOANO
+#define ENOANO 55 /* No anode */
+#undef EBADRQC
+#define EBADRQC 56 /* Invalid request code */
+#undef EBADSLT
+#define EBADSLT 57 /* Invalid slot */
+#undef EDEADLOCK
+#define EDEADLOCK EDEADLK /* Resource deadlock would occur */
+#undef EBFONT
+#define EBFONT 59 /* Bad font file format */
+#undef ENOSTR
+#define ENOSTR 60 /* Device not a stream */
+#undef ENODATA
+#define ENODATA 61 /* No data available */
+#undef ETIME
+#define ETIME 62 /* Timer expired */
+#undef ENOSR
+#define ENOSR 63 /* Out of streams resources */
+#undef ENONET
+#define ENONET 64 /* Machine is not on the network */
+#undef ENOPKG
+#define ENOPKG 65 /* Package not installed */
+#undef EREMOTE
+#define EREMOTE 66 /* Object is remote */
+#undef ENOLINK
+#define ENOLINK 67 /* Link has been severed */
+#undef EADV
+#define EADV 68 /* Advertise error */
+#undef ESRMNT
+#define ESRMNT 69 /* Srmount error */
+#undef ECOMM
+#define ECOMM 70 /* Communication error on send */
+#undef EPROTO
+#define EPROTO 71 /* Protocol error */
+#undef EMULTIHOP
+#define EMULTIHOP 72 /* Multihop attempted */
+#undef EDOTDOT
+#define EDOTDOT 73 /* RFS specific error */
+#undef EBADMSG
+#define EBADMSG 74 /* Not a data message */
+#undef EOVERFLOW
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#undef ENOTUNIQ
+#define ENOTUNIQ 76 /* Name not unique on network */
+#undef EBADFD
+#define EBADFD 77 /* File descriptor in bad state */
+#undef EREMCHG
+#define EREMCHG 78 /* Remote address changed */
+#undef ELIBACC
+#define ELIBACC 79 /* Can not access a needed shared library */
+#undef ELIBBAD
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#undef ELIBSCN
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#undef ELIBMAX
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#undef ELIBEXEC
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#undef EILSEQ
+#define EILSEQ 84 /* Illegal byte sequence */
+#undef ERESTART
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#undef ESTRPIPE
+#define ESTRPIPE 86 /* Streams pipe error */
+#undef EUSERS
+#define EUSERS 87 /* Too many users */
+#undef ENOTSOCK
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#undef EDESTADDRREQ
+#define EDESTADDRREQ 89 /* Destination address required */
+#undef EMSGSIZE
+#define EMSGSIZE 90 /* Message too long */
+#undef EPROTOTYPE
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#undef ENOPROTOOPT
+#define ENOPROTOOPT 92 /* Protocol not available */
+#undef EPROTONOSUPPORT
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#undef ESOCKTNOSUPPORT
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#undef EOPNOTSUPP
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#undef EPFNOSUPPORT
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#undef EAFNOSUPPORT
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#undef EADDRINUSE
+#define EADDRINUSE 98 /* Address already in use */
+#undef EADDRNOTAVAIL
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#undef ENETDOWN
+#define ENETDOWN 100 /* Network is down */
+#undef ENETUNREACH
+#define ENETUNREACH 101 /* Network is unreachable */
+#undef ENETRESET
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#undef ECONNABORTED
+#define ECONNABORTED 103 /* Software caused connection abort */
+#undef ECONNRESET
+#define ECONNRESET 104 /* Connection reset by peer */
+#undef ENOBUFS
+#define ENOBUFS 105 /* No buffer space available */
+#undef EISCONN
+#define EISCONN 106 /* Transport endpoint is already connected */
+#undef ENOTCONN
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#undef ESHUTDOWN
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#undef ETOOMANYREFS
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#undef ETIMEDOUT
+#define ETIMEDOUT 110 /* Connection timed out */
+#undef ECONNREFUSED
+#define ECONNREFUSED 111 /* Connection refused */
+#undef EHOSTDOWN
+#define EHOSTDOWN 112 /* Host is down */
+#undef EHOSTUNREACH
+#define EHOSTUNREACH 113 /* No route to host */
+#undef EALREADY
+#define EALREADY 114 /* Operation already in progress */
+#undef EINPROGRESS
+#define EINPROGRESS 115 /* Operation now in progress */
+#undef ESTALE
+#define ESTALE 116 /* Stale NFS file handle */
+#undef EUCLEAN
+#define EUCLEAN 117 /* Structure needs cleaning */
+#undef ENOTNAM
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#undef ENAVAIL
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#undef EISNAM
+#define EISNAM 120 /* Is a named type file */
+#undef EREMOTEIO
+#define EREMOTEIO 121 /* Remote I/O error */
+#undef EDQUOT
+#define EDQUOT 122 /* Quota exceeded */
+#undef ENOMEDIUM
+#define ENOMEDIUM 123 /* No medium found */
+#undef EMEDIUMTYPE
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+#undef ECANCELED
+#define ECANCELED 125 /* Operation Canceled */
+#undef ENOKEY
+#define ENOKEY 126 /* Required key not available */
+#undef EKEYEXPIRED
+#define EKEYEXPIRED 127 /* Key has expired */
+#undef EKEYREVOKED
+#define EKEYREVOKED 128 /* Key has been revoked */
+#undef EKEYREJECTED
+#define EKEYREJECTED 129 /* Key was rejected by service */
+#undef EOWNERDEAD
+#define EOWNERDEAD 130 /* Owner died */
+#undef ENOTRECOVERABLE
+#define ENOTRECOVERABLE 131 /* State not recoverable */
+
+/* Missing stat.h defines.
+ * The following are sys/stat.h definitions not currently present in the ARMCC
+ * errno.h. Note, ARMCC errno.h defines some symbol values differing from
+ * GCC_ARM/IAR/standard POSIX definitions. Guard against this and future
+ * changes by changing the symbol definition for filesystem use.
+ */
+#define _IFMT 0170000 //< type of file
+#define _IFSOCK 0140000 //< socket
+#define _IFLNK 0120000 //< symbolic link
+#define _IFREG 0100000 //< regular
+#define _IFBLK 0060000 //< block special
+#define _IFDIR 0040000 //< directory
+#define _IFCHR 0020000 //< character special
+#define _IFIFO 0010000 //< fifo special
+
+#define S_IFMT _IFMT //< type of file
+#define S_IFSOCK _IFSOCK //< socket
+#define S_IFLNK _IFLNK //< symbolic link
+#define S_IFREG _IFREG //< regular
+#define S_IFBLK _IFBLK //< block special
+#define S_IFDIR _IFDIR //< directory
+#define S_IFCHR _IFCHR //< character special
+#define S_IFIFO _IFIFO //< fifo special
+
+#define S_IRWXU (S_IRUSR | S_IWUSR | S_IXUSR)
+#define S_IRUSR 0000400 ///< read permission, owner
+#define S_IWUSR 0000200 ///< write permission, owner
+#define S_IXUSR 0000100 ///< execute/search permission, owner
+#define S_IRWXG (S_IRGRP | S_IWGRP | S_IXGRP)
+#define S_IRGRP 0000040 ///< read permission, group
+#define S_IWGRP 0000020 ///< write permission, group
+#define S_IXGRP 0000010 ///< execute/search permission, group
+#define S_IRWXO (S_IROTH | S_IWOTH | S_IXOTH)
+#define S_IROTH 0000004 ///< read permission, other
+#define S_IWOTH 0000002 ///< write permission, other
+#define S_IXOTH 0000001 ///< execute/search permission, other
+
+/* Refer to sys/stat standard
+ * Note: Not all fields may be supported by the underlying filesystem
+ */
+struct stat {
+ dev_t st_dev; ///< Device ID containing file
+ ino_t st_ino; ///< File serial number
+ mode_t st_mode; ///< Mode of file
+ nlink_t st_nlink; ///< Number of links to file
+
+ uid_t st_uid; ///< User ID
+ gid_t st_gid; ///< Group ID
+
+ off_t st_size; ///< Size of file in bytes
+
+ time_t st_atime; ///< Time of last access
+ time_t st_mtime; ///< Time of last data modification
+ time_t st_ctime; ///< Time of last status change
+};
+
+struct statvfs {
+ unsigned long f_bsize; ///< Filesystem block size
+ unsigned long f_frsize; ///< Fragment size (block size)
+
+ fsblkcnt_t f_blocks; ///< Number of blocks
+ fsblkcnt_t f_bfree; ///< Number of free blocks
+ fsblkcnt_t f_bavail; ///< Number of free blocks for unprivileged users
+
+ unsigned long f_fsid; ///< Filesystem ID
+
+ unsigned long f_namemax; ///< Maximum filename length
+};
+
+/* The following are dirent.h definitions are declared here to guarantee
+ * consistency where structure may be different with different toolchains
+ */
+struct dirent {
+ char d_name[NAME_MAX + 1]; ///< Name of file
+ uint8_t d_type; ///< Type of file
+};
+
+enum {
+ DT_UNKNOWN, ///< The file type could not be determined.
+ DT_FIFO, ///< This is a named pipe (FIFO).
+ DT_CHR, ///< This is a character device.
+ DT_DIR, ///< This is a directory.
+ DT_BLK, ///< This is a block device.
+ DT_REG, ///< This is a regular file.
+ DT_LNK, ///< This is a symbolic link.
+ DT_SOCK, ///< This is a UNIX domain socket.
+};
+
+/* fcntl.h defines */
+#define F_GETFL 3
+#define F_SETFL 4
+
+struct pollfd {
+ int fd;
+ short events;
+ short revents;
+};
+
+/* POSIX-compatible I/O functions */
+#if __cplusplus
+extern "C" {
+#endif
+ int open(const char *path, int oflag, ...);
+#ifndef __IAR_SYSTEMS_ICC__ /* IAR provides fdopen itself */
+#if __cplusplus
+ std::FILE *fdopen(int fildes, const char *mode);
+#else
+ FILE *fdopen(int fildes, const char *mode);
+#endif
+#endif
+ ssize_t write(int fildes, const void *buf, size_t nbyte);
+ ssize_t read(int fildes, void *buf, size_t nbyte);
+ off_t lseek(int fildes, off_t offset, int whence);
+ int isatty(int fildes);
+ int fsync(int fildes);
+ int fstat(int fildes, struct stat *st);
+ int fcntl(int fildes, int cmd, ...);
+ int poll(struct pollfd fds[], nfds_t nfds, int timeout);
+ int close(int fildes);
+ int stat(const char *path, struct stat *st);
+ int statvfs(const char *path, struct statvfs *buf);
+ DIR *opendir(const char *);
+ struct dirent *readdir(DIR *);
+ int closedir(DIR *);
+ void rewinddir(DIR *);
+ long telldir(DIR *);
+ void seekdir(DIR *, long);
+ int mkdir(const char *name, mode_t n);
+#if __cplusplus
+}; // extern "C"
+
+namespace mbed {
+
+/** This call is an analogue to POSIX fdopen().
+ *
+ * It associates a C stream to an already-opened FileHandle, to allow you to
+ * use C printf/scanf/fwrite etc. The provided FileHandle must remain open -
+ * it will be closed by the C library when fclose(FILE) is called.
+ *
+ * The net effect is fdopen(bind_to_fd(fh), mode), with error handling.
+ *
+ * @param fh a pointer to an opened FileHandle
+ * @param mode operation upon the file descriptor, e.g., "w+"
+ *
+ * @returns a pointer to FILE
+ */
+std::FILE *fdopen(mbed::FileHandle *fh, const char *mode);
+
+/** Bind an mbed FileHandle to a POSIX file descriptor
+ *
+ * This is similar to fdopen, but only operating at the POSIX layer - it
+ * associates a POSIX integer file descriptor with a FileHandle, to allow you
+ * to use POSIX read/write calls etc. The provided FileHandle must remain open -
+ * it will be closed when close(int) is called.
+ *
+ * @param fh a pointer to an opened FileHandle
+ *
+ * @return an integer file descriptor, or negative if no descriptors available
+ */
+int bind_to_fd(mbed::FileHandle *fh);
+
+} // namespace mbed
+
+#endif // __cplusplus
+
+/**@}*/
+
+/**@}*/
+
+#endif /* RETARGET_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_rtc_time.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_rtc_time.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,129 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/rtc_api.h"
+
+#include "platform/mbed_critical.h"
+#include "platform/mbed_rtc_time.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+static SingletonPtr<PlatformMutex> _mutex;
+
+#if DEVICE_RTC
+
+static void (*_rtc_init)(void) = rtc_init;
+static int (*_rtc_isenabled)(void) = rtc_isenabled;
+static time_t (*_rtc_read)(void) = rtc_read;
+static void (*_rtc_write)(time_t t) = rtc_write;
+
+#elif DEVICE_LPTICKER
+
+#include "drivers/LowPowerTimer.h"
+
+static SingletonPtr<mbed::LowPowerTimer> _rtc_lp_timer;
+static uint64_t _rtc_lp_base;
+static bool _rtc_enabled;
+
+static void _rtc_lpticker_init(void)
+{
+ _rtc_lp_timer->start();
+ _rtc_enabled = true;
+}
+
+static int _rtc_lpticker_isenabled(void)
+{
+ return (_rtc_enabled == true);
+}
+
+static time_t _rtc_lpticker_read(void)
+{
+ return (uint64_t)_rtc_lp_timer->read() + _rtc_lp_base;
+}
+
+static void _rtc_lpticker_write(time_t t)
+{
+ _rtc_lp_base = t;
+}
+
+static void (*_rtc_init)(void) = _rtc_lpticker_init;
+static int (*_rtc_isenabled)(void) = _rtc_lpticker_isenabled;
+static time_t (*_rtc_read)(void) = _rtc_lpticker_read;
+static void (*_rtc_write)(time_t t) = _rtc_lpticker_write;
+
+#else /* DEVICE_LPTICKER */
+
+static void (*_rtc_init)(void) = NULL;
+static int (*_rtc_isenabled)(void) = NULL;
+static time_t (*_rtc_read)(void) = NULL;
+static void (*_rtc_write)(time_t t) = NULL;
+#endif /* DEVICE_LPTICKER */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined (__ICCARM__)
+time_t __time32(time_t *timer)
+#else
+time_t time(time_t *timer)
+#endif
+
+{
+ _mutex->lock();
+ if (_rtc_isenabled != NULL) {
+ if (!(_rtc_isenabled())) {
+ set_time(0);
+ }
+ }
+
+ time_t t = (time_t) -1;
+ if (_rtc_read != NULL) {
+ t = _rtc_read();
+ }
+
+ if (timer != NULL) {
+ *timer = t;
+ }
+ _mutex->unlock();
+ return t;
+}
+
+void set_time(time_t t)
+{
+ _mutex->lock();
+ if (_rtc_init != NULL) {
+ _rtc_init();
+ }
+ if (_rtc_write != NULL) {
+ _rtc_write(t);
+ }
+ _mutex->unlock();
+}
+
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void))
+{
+ _mutex->lock();
+ _rtc_read = read_rtc;
+ _rtc_write = write_rtc;
+ _rtc_init = init_rtc;
+ _rtc_isenabled = isenabled_rtc;
+ _mutex->unlock();
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_rtc_time.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_rtc_time.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,97 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_rtc_time rtc_time functions
+ * @{
+ */
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Implementation of the C time.h functions
+ *
+ * Provides mechanisms to set and read the current time, based
+ * on the microcontroller Real-Time Clock (RTC), plus some
+ * standard C manipulation and formating functions.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ * set_time(1256729737); // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ *
+ * while(1) {
+ * time_t seconds = time(NULL);
+ *
+ * printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ *
+ * printf("Time as a basic string = %s", ctime(&seconds));
+ *
+ * char buffer[32];
+ * strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
+ * printf("Time as a custom formatted string = %s", buffer);
+ *
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+
+/** Set the current time
+ *
+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * to the time represented by the number of seconds since January 1, 1970
+ * (the UNIX timestamp).
+ *
+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ * set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
+ * }
+ * @endcode
+ */
+void set_time(time_t t);
+
+/** Attach an external RTC to be used for the C time functions
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @param read_rtc pointer to function which returns current UNIX timestamp
+ * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
+ * @param init_rtc pointer to funtion which initializes RTC, can be NULL
+ * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
+ */
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_sdk_boot.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_sdk_boot.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_toolchain.h"
+#include <stdlib.h>
+#include <stdint.h>
+#include "cmsis.h"
+
+/* This startup is for mbed 2 baremetal. There is no config for RTOS for mbed 2,
+ * therefore we protect this file with MBED_CONF_RTOS_PRESENT
+ * Note: The new consolidated started for mbed OS is in rtos/mbed_boot code file.
+ */
+#if !defined(MBED_CONF_RTOS_PRESENT)
+
+/* mbed_main is a function that is called before main()
+ * mbed_sdk_init() is also a function that is called before main(), but unlike
+ * mbed_main(), it is not meant for user code, but for the SDK itself to perform
+ * initializations before main() is called.
+ */
+MBED_WEAK void mbed_main(void)
+{
+
+}
+
+/* This function can be implemented by the target to perform higher level target initialization
+ */
+MBED_WEAK void mbed_sdk_init(void)
+{
+
+}
+
+MBED_WEAK void software_init_hook_rtos()
+{
+ // Nothing by default
+}
+
+void mbed_copy_nvic(void)
+{
+ /* If vector address in RAM is defined, copy and switch to dynamic vectors. Exceptions for M0 which doesn't have
+ VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is
+ responsible for correctly handling the vectors.
+ */
+#if !defined(__CORTEX_M0) && !defined(__CORTEX_A9)
+#ifdef NVIC_RAM_VECTOR_ADDRESS
+ uint32_t *old_vectors = (uint32_t *)SCB->VTOR;
+ uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+ for (int i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+#endif /* NVIC_RAM_VECTOR_ADDRESS */
+#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A9) */
+}
+
+/* Toolchain specific main code */
+
+#if defined (__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 5010060))
+
+int $Super$$main(void);
+
+int $Sub$$main(void)
+{
+ mbed_main();
+ return $Super$$main();
+}
+
+void _platform_post_stackheap_init(void)
+{
+ mbed_copy_nvic();
+ mbed_sdk_init();
+}
+
+#elif defined (__GNUC__)
+
+extern int __real_main(void);
+
+void software_init_hook(void)
+{
+ mbed_copy_nvic();
+ mbed_sdk_init();
+ software_init_hook_rtos();
+}
+
+
+int __wrap_main(void)
+{
+ mbed_main();
+ return __real_main();
+}
+
+#elif defined (__ICCARM__)
+
+int __low_level_init(void)
+{
+ mbed_copy_nvic();
+ return 1;
+}
+
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_semihost_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_semihost_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,183 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "platform/mbed_semihost_api.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#if DEVICE_SEMIHOST
+
+// ARM Semihosting Commands
+#define SYS_OPEN (0x1)
+#define SYS_CLOSE (0x2)
+#define SYS_WRITE (0x5)
+#define SYS_READ (0x6)
+#define SYS_ISTTY (0x9)
+#define SYS_SEEK (0xa)
+#define SYS_ENSURE (0xb)
+#define SYS_FLEN (0xc)
+#define SYS_REMOVE (0xe)
+#define SYS_RENAME (0xf)
+#define SYS_EXIT (0x18)
+
+// mbed Semihosting Commands
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+#define USR_UID (RESERVED_FOR_USER_APPLICATIONS + 1)
+#define USR_RESET (RESERVED_FOR_USER_APPLICATIONS + 2)
+#define USR_VBUS (RESERVED_FOR_USER_APPLICATIONS + 3)
+#define USR_POWERDOWN (RESERVED_FOR_USER_APPLICATIONS + 4)
+#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char *name, int openmode)
+{
+ uint32_t args[3];
+ args[0] = (uint32_t)name;
+ args[1] = (uint32_t)openmode;
+ args[2] = (uint32_t)strlen(name);
+ return __semihost(SYS_OPEN, args);
+}
+
+int semihost_close(FILEHANDLE fh)
+{
+ return __semihost(SYS_CLOSE, &fh);
+}
+
+int semihost_write(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode)
+{
+ if (length == 0) {
+ return 0;
+ }
+
+ uint32_t args[3];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)buffer;
+ args[2] = (uint32_t)length;
+ return __semihost(SYS_WRITE, args);
+}
+
+int semihost_read(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode)
+{
+ uint32_t args[3];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)buffer;
+ args[2] = (uint32_t)length;
+ return __semihost(SYS_READ, args);
+}
+
+int semihost_istty(FILEHANDLE fh)
+{
+ return __semihost(SYS_ISTTY, &fh);
+}
+
+int semihost_seek(FILEHANDLE fh, long position)
+{
+ uint32_t args[2];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)position;
+ return __semihost(SYS_SEEK, args);
+}
+
+int semihost_ensure(FILEHANDLE fh)
+{
+ return __semihost(SYS_ENSURE, &fh);
+}
+
+long semihost_flen(FILEHANDLE fh)
+{
+ return __semihost(SYS_FLEN, &fh);
+}
+
+int semihost_remove(const char *name)
+{
+ uint32_t args[2];
+ args[0] = (uint32_t)name;
+ args[1] = (uint32_t)strlen(name);
+ return __semihost(SYS_REMOVE, args);
+}
+
+int semihost_rename(const char *old_name, const char *new_name)
+{
+ uint32_t args[4];
+ args[0] = (uint32_t)old_name;
+ args[1] = (uint32_t)strlen(old_name);
+ args[0] = (uint32_t)new_name;
+ args[1] = (uint32_t)strlen(new_name);
+ return __semihost(SYS_RENAME, args);
+}
+#endif
+
+int semihost_exit(void)
+{
+ uint32_t args[4];
+ return __semihost(SYS_EXIT, args);
+}
+
+int semihost_uid(char *uid)
+{
+ uint32_t args[2];
+ args[0] = (uint32_t)uid;
+ args[1] = DEVICE_ID_LENGTH + 1;
+ return __semihost(USR_UID, &args);
+}
+
+int semihost_reset(void)
+{
+ // Does not normally return, however if used with older firmware versions
+ // that do not support this call it will return -1.
+ return __semihost(USR_RESET, NULL);
+}
+
+int semihost_vbus(void)
+{
+ return __semihost(USR_VBUS, NULL);
+}
+
+int semihost_powerdown(void)
+{
+ return __semihost(USR_POWERDOWN, NULL);
+}
+
+#if DEVICE_DEBUG_AWARENESS
+
+int semihost_connected(void)
+{
+ return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
+}
+
+#else
+// These processors cannot know if the interface is connect, assume so:
+static int is_debugger_attached = 1;
+
+int semihost_connected(void)
+{
+ return is_debugger_attached;
+}
+#endif
+
+int semihost_disabledebug(void)
+{
+ uint32_t args[1];
+#if !(DEVICE_DEBUG_AWARENESS)
+ is_debugger_attached = 0;
+#endif
+ return __semihost(USR_DISABLEDEBUG, &args);
+}
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_semihost_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_semihost_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,98 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SEMIHOST_H
+#define MBED_SEMIHOST_H
+
+#include "device.h"
+#include "platform/mbed_toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+#if !defined(__CC_ARM) && !defined(__ARMCC_VERSION)
+
+#if defined(__ICCARM__)
+static inline int __semihost(int reason, const void *arg)
+{
+ return __semihosting(reason, (void *)arg);
+}
+#else
+
+#ifdef __thumb__
+# define AngelSWI 0xAB
+# define AngelSWIInsn "bkpt"
+# define AngelSWIAsm bkpt
+#else
+# define AngelSWI 0x123456
+# define AngelSWIInsn "swi"
+# define AngelSWIAsm swi
+#endif
+
+static inline int __semihost(int reason, const void *arg)
+{
+ int value;
+
+ asm volatile(
+ "mov r0, %1" "\n\t"
+ "mov r1, %2" "\n\t"
+ AngelSWIInsn " %a3" "\n\t"
+ "mov %0, r0"
+ : "=r"(value) /* output operands */
+ : "r"(reason), "r"(arg), "i"(AngelSWI) /* input operands */
+ : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* list of clobbered registers */
+ );
+
+ return value;
+}
+#endif
+#endif
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char *name, int openmode);
+int semihost_close(FILEHANDLE fh);
+int semihost_read(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode);
+int semihost_write(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode);
+int semihost_ensure(FILEHANDLE fh);
+long semihost_flen(FILEHANDLE fh);
+int semihost_seek(FILEHANDLE fh, long position);
+int semihost_istty(FILEHANDLE fh);
+
+int semihost_remove(const char *name);
+int semihost_rename(const char *old_name, const char *new_name);
+#endif
+
+int semihost_uid(char *uid);
+int semihost_reset(void);
+int semihost_vbus(void);
+int semihost_powerdown(void);
+int semihost_exit(void);
+
+int semihost_connected(void);
+int semihost_disabledebug(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_sleep.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/platform/mbed_sleep.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_MBED_SLEEP_H +#define MBED_MBED_SLEEP_H + +#warning mbed_sleep.h has been replaced by mbed_power_mgmt.h, please update to mbed_power_mgmt.h [since mbed-os-5.8] +#include "platform/mbed_power_mgmt.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_stats.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_stats.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,144 @@
+#include "mbed_assert.h"
+#include "mbed_stats.h"
+#include "mbed_power_mgmt.h"
+#include "mbed_version.h"
+#include <string.h>
+#include <stdlib.h>
+
+#include "device.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "cmsis_os2.h"
+#include "rtos_idle.h"
+#elif defined(MBED_STACK_STATS_ENABLED) || defined(MBED_THREAD_STATS_ENABLED) || defined(MBED_CPU_STATS_ENABLED)
+#warning Statistics are currently not supported without the rtos.
+#endif
+
+#if defined(MBED_CPU_STATS_ENABLED) && (!defined(DEVICE_LPTICKER) || !defined(DEVICE_SLEEP))
+#warning CPU statistics are not supported without low power timer support.
+#endif
+
+void mbed_stats_cpu_get(mbed_stats_cpu_t *stats)
+{
+ MBED_ASSERT(stats != NULL);
+ memset(stats, 0, sizeof(mbed_stats_cpu_t));
+#if defined(MBED_CPU_STATS_ENABLED) && defined(DEVICE_LPTICKER) && defined(DEVICE_SLEEP)
+ stats->uptime = mbed_uptime();
+ stats->idle_time = mbed_time_idle();
+ stats->sleep_time = mbed_time_sleep();
+ stats->deep_sleep_time = mbed_time_deepsleep();
+#endif
+}
+
+// note: mbed_stats_heap_get defined in mbed_alloc_wrappers.cpp
+void mbed_stats_stack_get(mbed_stats_stack_t *stats)
+{
+ MBED_ASSERT(stats != NULL);
+ memset(stats, 0, sizeof(mbed_stats_stack_t));
+
+#if defined(MBED_STACK_STATS_ENABLED) && defined(MBED_CONF_RTOS_PRESENT)
+ uint32_t thread_n = osThreadGetCount();
+ unsigned i;
+ osThreadId_t *threads;
+
+ threads = malloc(sizeof(osThreadId_t) * thread_n);
+ MBED_ASSERT(threads != NULL);
+
+ osKernelLock();
+ thread_n = osThreadEnumerate(threads, thread_n);
+
+ for (i = 0; i < thread_n; i++) {
+ uint32_t stack_size = osThreadGetStackSize(threads[i]);
+ stats->max_size += stack_size - osThreadGetStackSpace(threads[i]);
+ stats->reserved_size += stack_size;
+ stats->stack_cnt++;
+ }
+ osKernelUnlock();
+
+ free(threads);
+#endif
+}
+
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count)
+{
+ MBED_ASSERT(stats != NULL);
+ memset(stats, 0, count * sizeof(mbed_stats_stack_t));
+
+ size_t i = 0;
+
+#if defined(MBED_STACK_STATS_ENABLED) && defined(MBED_CONF_RTOS_PRESENT)
+ osThreadId_t *threads;
+
+ threads = malloc(sizeof(osThreadId_t) * count);
+ MBED_ASSERT(threads != NULL);
+
+ osKernelLock();
+ count = osThreadEnumerate(threads, count);
+
+ for (i = 0; i < count; i++) {
+ uint32_t stack_size = osThreadGetStackSize(threads[i]);
+ stats[i].max_size = stack_size - osThreadGetStackSpace(threads[i]);
+ stats[i].reserved_size = stack_size;
+ stats[i].thread_id = (uint32_t)threads[i];
+ stats[i].stack_cnt = 1;
+ }
+ osKernelUnlock();
+
+ free(threads);
+#endif
+
+ return i;
+}
+
+size_t mbed_stats_thread_get_each(mbed_stats_thread_t *stats, size_t count)
+{
+ MBED_ASSERT(stats != NULL);
+ memset(stats, 0, count * sizeof(mbed_stats_thread_t));
+ size_t i = 0;
+
+#if defined(MBED_THREAD_STATS_ENABLED) && defined(MBED_CONF_RTOS_PRESENT)
+ osThreadId_t *threads;
+
+ threads = malloc(sizeof(osThreadId_t) * count);
+ MBED_ASSERT(threads != NULL);
+
+ osKernelLock();
+ count = osThreadEnumerate(threads, count);
+
+ for (i = 0; i < count; i++) {
+ stats[i].id = (uint32_t)threads[i];
+ stats[i].state = (uint32_t)osThreadGetState(threads[i]);
+ stats[i].priority = (uint32_t)osThreadGetPriority(threads[i]);
+ stats[i].stack_size = osThreadGetStackSize(threads[i]);
+ stats[i].stack_space = osThreadGetStackSpace(threads[i]);
+ stats[i].name = osThreadGetName(threads[i]);
+ }
+ osKernelUnlock();
+ free(threads);
+#endif
+ return i;
+}
+
+void mbed_stats_sys_get(mbed_stats_sys_t *stats)
+{
+ MBED_ASSERT(stats != NULL);
+ memset(stats, 0, sizeof(mbed_stats_sys_t));
+
+#if defined(MBED_SYS_STATS_ENABLED)
+ stats->os_version = MBED_VERSION;
+#if defined(__CORTEX_M)
+ stats->cpu_id = SCB->CPUID;
+#endif
+#if defined(__IAR_SYSTEMS_ICC__)
+ stats->compiler_id = IAR;
+ stats->compiler_version = __VER__;
+#elif defined(__CC_ARM)
+ stats->compiler_id = ARM;
+ stats->compiler_version = __ARMCC_VERSION;
+#elif defined(__GNUC__)
+ stats->compiler_id = GCC_ARM;
+ stats->compiler_version = (__GNUC__ * 10000 + __GNUC_MINOR__ * 100);
+#endif
+
+#endif
+ return;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_stats.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_stats.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,161 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_stats stats functions
+ * @{
+ */
+/* mbed Microcontroller Library
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STATS_H
+#define MBED_STATS_H
+#include <stdint.h>
+#include <stddef.h>
+#include "hal/ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef MBED_ALL_STATS_ENABLED
+#define MBED_SYS_STATS_ENABLED 1
+#define MBED_STACK_STATS_ENABLED 1
+#define MBED_CPU_STATS_ENABLED 1
+#define MBED_HEAP_STATS_ENABLED 1
+#define MBED_THREAD_STATS_ENABLED 1
+#endif
+
+/**
+ * struct mbed_stats_heap_t definition
+ */
+typedef struct {
+ uint32_t current_size; /**< Bytes allocated currently. */
+ uint32_t max_size; /**< Max bytes allocated at a given time. */
+ uint32_t total_size; /**< Cumulative sum of bytes ever allocated. */
+ uint32_t reserved_size; /**< Current number of bytes allocated for the heap. */
+ uint32_t alloc_cnt; /**< Current number of allocations. */
+ uint32_t alloc_fail_cnt; /**< Number of failed allocations. */
+} mbed_stats_heap_t;
+
+/**
+ * Fill the passed in heap stat structure with heap stats.
+ *
+ * @param stats A pointer to the mbed_stats_heap_t structure to fill
+ */
+void mbed_stats_heap_get(mbed_stats_heap_t *stats);
+
+/**
+ * struct mbed_stats_stack_t definition
+ */
+typedef struct {
+ uint32_t thread_id; /**< Identifier for thread that owns the stack or 0 if multiple threads. */
+ uint32_t max_size; /**< Maximum number of bytes used on the stack. */
+ uint32_t reserved_size; /**< Current number of bytes allocated for the stack. */
+ uint32_t stack_cnt; /**< Number of stacks stats accumulated in the structure. */
+} mbed_stats_stack_t;
+
+/**
+ * Fill the passed in structure with stack stats accumulated for all threads. The thread_id will be 0
+ * and stack_cnt will represent number of threads.
+ *
+ * @param stats A pointer to the mbed_stats_stack_t structure to fill
+ */
+void mbed_stats_stack_get(mbed_stats_stack_t *stats);
+
+/**
+ * Fill the passed array of stat structures with the stack stats for each available thread.
+ *
+ * @param stats A pointer to an array of mbed_stats_stack_t structures to fill
+ * @param count The number of mbed_stats_stack_t structures in the provided array
+ * @return The number of mbed_stats_stack_t structures that have been filled,
+ * this is equal to the number of stacks on the system.
+ */
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count);
+
+/**
+ * struct mbed_stats_cpu_t definition
+ */
+typedef struct {
+ us_timestamp_t uptime; /**< Time since system is up and running */
+ us_timestamp_t idle_time; /**< Time spent in idle thread since system is up and running */
+ us_timestamp_t sleep_time; /**< Time spent in sleep since system is up and running */
+ us_timestamp_t deep_sleep_time; /**< Time spent in deep sleep since system is up and running */
+} mbed_stats_cpu_t;
+
+/**
+ * Fill the passed in CPU stat structure with CPU statistics.
+ *
+ * @param stats A pointer to the mbed_stats_cpu_t structure to fill
+ */
+void mbed_stats_cpu_get(mbed_stats_cpu_t *stats);
+
+/**
+ * struct mbed_stats_thread_t definition
+ */
+typedef struct {
+ uint32_t id; /**< Thread Object Identifier */
+ uint32_t state; /**< Thread Object State */
+ uint32_t priority; /**< Thread Priority */
+ uint32_t stack_size; /**< Thread Stack Size */
+ uint32_t stack_space; /**< Thread remaining stack size */
+ const char *name; /**< Thread Object name */
+} mbed_stats_thread_t;
+
+/**
+ * Fill the passed array of stat structures with the thread stats for each available thread.
+ *
+ * @param stats A pointer to an array of mbed_stats_thread_t structures to fill
+ * @param count The number of mbed_stats_thread_t structures in the provided array
+ * @return The number of mbed_stats_thread_t structures that have been filled,
+ * this is equal to the number of threads on the system.
+ */
+size_t mbed_stats_thread_get_each(mbed_stats_thread_t *stats, size_t count);
+
+/**
+ * enum mbed_compiler_id_t definition
+ */
+typedef enum {
+ ARM = 1, /**< ARM */
+ GCC_ARM, /**< GNU ARM */
+ IAR /**< IAR */
+} mbed_compiler_id_t;
+
+/**
+ * struct mbed_stats_sys_t definition
+ */
+typedef struct {
+ uint32_t os_version; /**< Mbed OS Version (Release only) */
+ uint32_t cpu_id; /**< CPUID Register data (Cortex-M only supported) */
+ mbed_compiler_id_t compiler_id; /**< Compiler ID \ref mbed_compiler_id_t */
+ uint32_t compiler_version; /**< Compiler version */
+} mbed_stats_sys_t;
+
+/**
+ * Fill the passed in sys stat structure with system stats.
+ *
+ * @param stats A pointer to the mbed_stats_sys_t structure to fill
+ */
+void mbed_stats_sys_get(mbed_stats_sys_t *stats);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_toolchain.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_toolchain.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,439 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_toolchain Toolchain functions
+ * @{
+ */
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TOOLCHAIN_H
+#define MBED_TOOLCHAIN_H
+
+#include "mbed_preprocessor.h"
+
+
+// Warning for unsupported compilers
+#if !defined(__GNUC__) /* GCC */ \
+ && !defined(__CC_ARM) /* ARMCC */ \
+ && !defined(__clang__) /* LLVM/Clang */ \
+ && !defined(__ICCARM__) /* IAR */
+#warning "This compiler is not yet supported."
+#endif
+
+
+// Attributes
+
+/** MBED_PACKED
+ * Pack a structure, preventing any padding from being added between fields.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_PACKED(struct) foo {
+ * char x;
+ * int y;
+ * };
+ * @endcode
+ */
+#ifndef MBED_PACKED
+#if defined(__ICCARM__)
+#define MBED_PACKED(struct) __packed struct
+#else
+#define MBED_PACKED(struct) struct __attribute__((packed))
+#endif
+#endif
+
+/** MBED_ALIGN(N)
+ * Declare a variable to be aligned on an N-byte boundary.
+ *
+ * @note
+ * IAR does not support alignment greater than word size on the stack
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_ALIGN(16) char a;
+ * @endcode
+ */
+#ifndef MBED_ALIGN
+#if defined(__ICCARM__)
+#define MBED_ALIGN(N) _Pragma(MBED_STRINGIFY(data_alignment=N))
+#else
+#define MBED_ALIGN(N) __attribute__((aligned(N)))
+#endif
+#endif
+
+/** MBED_UNUSED
+ * Declare a function argument to be unused, suppressing compiler warnings
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * void foo(MBED_UNUSED int arg) {
+ *
+ * }
+ * @endcode
+ */
+#ifndef MBED_UNUSED
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_UNUSED __attribute__((__unused__))
+#else
+#define MBED_UNUSED
+#endif
+#endif
+
+/** MBED_USED
+ * Inform the compiler that a static variable is to be retained in the object file, even if it is unreferenced.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_USED int foo;
+ *
+ * @endcode
+ */
+#ifndef MBED_USED
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_USED __attribute__((used))
+#elif defined(__ICCARM__)
+#define MBED_USED __root
+#else
+#define MBED_USED
+#endif
+#endif
+
+/** MBED_WEAK
+ * Mark a function as being weak.
+ *
+ * @note
+ * Functions should only be marked as weak in the source file. The header file
+ * should contain a regular function declaration to insure the function is emitted.
+ * A function marked weak will not be emitted if an alternative non-weak
+ * implementation is defined.
+ *
+ * @note
+ * Weak functions are not friendly to making code re-usable, as they can only
+ * be overridden once (and if they are multiply overridden the linker will emit
+ * no warning). You should not normally use weak symbols as part of the API to
+ * re-usable modules.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_WEAK void foo() {
+ * // a weak implementation of foo that can be overriden by a definition
+ * // without __weak
+ * }
+ * @endcode
+ */
+#ifndef MBED_WEAK
+#if defined(__ICCARM__)
+#define MBED_WEAK __weak
+#else
+#define MBED_WEAK __attribute__((weak))
+#endif
+#endif
+
+/** MBED_PURE
+ * Hint to the compiler that a function depends only on parameters
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_PURE int foo(int arg){
+ * // no access to global variables
+ * }
+ * @endcode
+ */
+#ifndef MBED_PURE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_PURE __attribute__((const))
+#else
+#define MBED_PURE
+#endif
+#endif
+
+/** MBED_NOINLINE
+ * Declare a function that must not be inlined.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_NOINLINE void foo() {
+ *
+ * }
+ * @endcode
+ */
+#ifndef MBED_NOINLINE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_NOINLINE __attribute__((noinline))
+#elif defined(__ICCARM__)
+#define MBED_NOINLINE _Pragma("inline=never")
+#else
+#define MBED_NOINLINE
+#endif
+#endif
+
+/** MBED_FORCEINLINE
+ * Declare a function that must always be inlined. Failure to inline
+ * such a function will result in an error.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_FORCEINLINE void foo() {
+ *
+ * }
+ * @endcode
+ */
+#ifndef MBED_FORCEINLINE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_FORCEINLINE static inline __attribute__((always_inline))
+#elif defined(__ICCARM__)
+#define MBED_FORCEINLINE _Pragma("inline=forced") static
+#else
+#define MBED_FORCEINLINE static inline
+#endif
+#endif
+
+/** MBED_NORETURN
+ * Declare a function that will never return.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_NORETURN void foo() {
+ * // must never return
+ * while (1) {}
+ * }
+ * @endcode
+ */
+#ifndef MBED_NORETURN
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_NORETURN __attribute__((noreturn))
+#elif defined(__ICCARM__)
+#define MBED_NORETURN __noreturn
+#else
+#define MBED_NORETURN
+#endif
+#endif
+
+/** MBED_UNREACHABLE
+ * An unreachable statement. If the statement is reached,
+ * behaviour is undefined. Useful in situations where the compiler
+ * cannot deduce the unreachability of code.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * void foo(int arg) {
+ * switch (arg) {
+ * case 1: return 1;
+ * case 2: return 2;
+ * ...
+ * }
+ * MBED_UNREACHABLE;
+ * }
+ * @endcode
+ */
+#ifndef MBED_UNREACHABLE
+#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
+#define MBED_UNREACHABLE __builtin_unreachable()
+#else
+#define MBED_UNREACHABLE while (1)
+#endif
+#endif
+
+/** MBED_DEPRECATED("message string")
+ * Mark a function declaration as deprecated, if it used then a warning will be
+ * issued by the compiler possibly including the provided message. Note that not
+ * all compilers are able to display the message.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_DEPRECATED("don't foo any more, bar instead")
+ * void foo(int arg);
+ * @endcode
+ */
+#ifndef MBED_DEPRECATED
+#if defined(__CC_ARM)
+#define MBED_DEPRECATED(M) __attribute__((deprecated))
+#elif defined(__GNUC__) || defined(__clang__)
+#define MBED_DEPRECATED(M) __attribute__((deprecated(M)))
+#else
+#define MBED_DEPRECATED(M)
+#endif
+#endif
+
+/** MBED_DEPRECATED_SINCE("version", "message string")
+ * Mark a function declaration as deprecated, noting that the declaration was
+ * deprecated on the specified version. If the function is used then a warning
+ * will be issued by the compiler possibly including the provided message.
+ * Note that not all compilers are able to display this message.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_DEPRECATED_SINCE("mbed-os-5.1", "don't foo any more, bar instead")
+ * void foo(int arg);
+ * @endcode
+ */
+#define MBED_DEPRECATED_SINCE(D, M) MBED_DEPRECATED(M " [since " D "]")
+
+/** MBED_CALLER_ADDR()
+ * Returns the caller of the current function.
+ *
+ * @note
+ * This macro is only implemented for GCC and ARMCC.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * printf("This function was called from %p", MBED_CALLER_ADDR());
+ * @endcode
+ *
+ * @return Address of the calling function
+ */
+#ifndef MBED_CALLER_ADDR
+#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_extract_return_addr(__builtin_return_address(0))
+#elif defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_return_address(0)
+#else
+#define MBED_CALLER_ADDR() (NULL)
+#endif
+#endif
+
+#ifndef MBED_SECTION
+#if (defined(__GNUC__) || defined(__clang__)) || defined(__CC_ARM)
+#define MBED_SECTION(name) __attribute__ ((section (name)))
+#elif defined(__ICCARM__)
+#define MBED_SECTION(name) _Pragma(MBED_STRINGIFY(location=name))
+#else
+#error "Missing MBED_SECTION directive"
+#endif
+#endif
+
+/**
+ * Macro expanding to a string literal of the enclosing function name.
+ *
+ * The string returned takes into account language specificity and yield human
+ * readable content.
+ *
+ * As an example, if the macro is used within a C++ function then the string
+ * literal containing the function name will contain the complete signature of
+ * the function - including template parameters - and namespace qualifications.
+ */
+#ifndef MBED_PRETTY_FUNCTION
+#define MBED_PRETTY_FUNCTION __PRETTY_FUNCTION__
+#endif
+
+#ifndef MBED_PRINTF
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_PRINTF(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx, first_param_idx)))
+#else
+#define MBED_PRINTF(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_PRINTF_METHOD
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_PRINTF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx+1, first_param_idx+1)))
+#else
+#define MBED_PRINTF_METHOD(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_SCANF
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_SCANF(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx, first_param_idx)))
+#else
+#define MBED_SCANF(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_SCANF_METHOD
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_SCANF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx+1, first_param_idx+1)))
+#else
+#define MBED_SCANF_METHOD(format_idx, first_param_idx)
+#endif
+#endif
+
+// Macro containing the filename part of the value of __FILE__. Defined as
+// string literal.
+#ifndef MBED_FILENAME
+#if defined(__CC_ARM)
+#define MBED_FILENAME __MODULE__
+#elif defined(__GNUC__)
+#define MBED_FILENAME (__builtin_strrchr(__FILE__, '/') ? __builtin_strrchr(__FILE__, '/') + 1 : __builtin_strrchr(__FILE__, '\\') ? __builtin_strrchr(__FILE__, '\\') + 1 : __FILE__)
+#elif defined(__ICCARM__)
+#define MBED_FILENAME (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : strrchr(__FILE__, '\\') ? strrchr(__FILE__, '\\') + 1 : __FILE__)
+#else
+#define MBED_FILENAME __FILE__
+#endif
+#endif // #ifndef MBED_FILENAME
+
+// FILEHANDLE declaration
+#if defined(TOOLCHAIN_ARM)
+#include <rt_sys.h>
+#endif
+
+#ifndef FILEHANDLE
+typedef int FILEHANDLE;
+#endif
+
+// Backwards compatibility
+#ifndef WEAK
+#define WEAK MBED_WEAK
+#endif
+
+#ifndef PACKED
+#define PACKED MBED_PACKED()
+#endif
+
+#ifndef EXTERN
+#define EXTERN extern
+#endif
+
+/** MBED_NONSECURE_ENTRY
+ * Declare a function that can be called from non-secure world or secure world
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_NONSECURE_ENTRY void foo() {
+ *
+ * }
+ * @endcode
+ */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L)
+#if defined (__ICCARM__)
+#define MBED_NONSECURE_ENTRY __cmse_nonsecure_entry
+#else
+#define MBED_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))
+#endif
+#else
+#define MBED_NONSECURE_ENTRY
+#endif
+
+#endif
+
+/** @}*/
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_version.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_version.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,55 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_version Version macros
+ * @{
+ */
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_VERSION_H
+#define MBED_VERSION_H
+
+#define MBED_LIBRARY_VERSION 163
+
+/** MBED_MAJOR_VERSION
+ * Mbed 2 major version
+ */
+#define MBED_MAJOR_VERSION 2
+
+/** MBED_MINOR_VERSION
+ * Mbed 2 minor version
+ */
+#define MBED_MINOR_VERSION 0
+
+/** MBED_PATCH_VERSION
+ * Mbed 2 patch version
+ */
+#define MBED_PATCH_VERSION 163
+
+#define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch))
+
+#define MBED_VERSION MBED_ENCODE_VERSION(MBED_MAJOR_VERSION, MBED_MINOR_VERSION, MBED_PATCH_VERSION)
+
+#define MBED_VERSION_CHECK(major, minor, patch) do { \
+ MBED_STATIC_ASSERT((MBED_VERSION >= MBED_ENCODE_VERSION((major),(minor),(patch))), "Incompatible mbed-os version detected!!"); \
+ } while(0)
+
+#endif
+
+/** @}*/
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_wait_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_wait_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,92 @@
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_wait_api wait_api functions
+ * @{
+ */
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_WAIT_API_H
+#define MBED_WAIT_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generic wait functions.
+ *
+ * These provide simple NOP type wait capabilities.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * DigitalOut heartbeat(LED1);
+ *
+ * int main() {
+ * while (1) {
+ * heartbeat = 1;
+ * wait(0.5);
+ * heartbeat = 0;
+ * wait(0.5);
+ * }
+ * }
+ * @endcode
+ */
+
+/** Waits for a number of seconds, with microsecond resolution (within
+ * the accuracy of single precision floating point).
+ *
+ * @param s number of seconds to wait
+ *
+ * @note
+ * If the RTOS is present, this function always spins to get the exact number of microseconds,
+ * which potentially affects power (such as preventing deep sleep) and multithread performance.
+ * You can avoid it by using Thread::wait().
+ */
+void wait(float s);
+
+/** Waits a number of milliseconds.
+ *
+ * @param ms the whole number of milliseconds to wait
+ *
+ * @note
+ * If the RTOS is present, this function always spins to get the exact number of microseconds,
+ * which potentially affects power (such as preventing deep sleep) and multithread performance.
+ * You can avoid it by using Thread::wait().
+ */
+void wait_ms(int ms);
+
+/** Waits a number of microseconds.
+ *
+ * @param us the whole number of microseconds to wait
+ *
+ * @note
+ * If the RTOS is present, this function always spins to get the exact number of microseconds,
+ * which potentially affects power (such as preventing deep sleep) and multithread performance.
+ */
+void wait_us(int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_wait_api_no_rtos.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_wait_api_no_rtos.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// This implementation of the wait functions will be compiled only
+// if the RTOS is not present.
+#ifndef MBED_CONF_RTOS_PRESENT
+
+#include "platform/mbed_wait_api.h"
+#include "hal/us_ticker_api.h"
+
+void wait(float s)
+{
+ wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms)
+{
+ wait_us(ms * 1000);
+}
+
+void wait_us(int us)
+{
+ const ticker_data_t *const ticker = get_us_ticker_data();
+ uint32_t start = ticker_read(ticker);
+ while ((ticker_read(ticker) - start) < (uint32_t)us);
+}
+
+#endif // #ifndef MBED_CONF_RTOS_PRESENT
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/mbed_wait_api_rtos.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/mbed_wait_api_rtos.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// This implementation of the wait functions will be compiled only
+// if the RTOS is present.
+#ifdef MBED_CONF_RTOS_PRESENT
+
+#include "platform/mbed_wait_api.h"
+#include "hal/us_ticker_api.h"
+#include "rtos/rtos.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_power_mgmt.h"
+
+void wait(float s)
+{
+ wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms)
+{
+ wait_us(ms * 1000);
+}
+
+void wait_us(int us)
+{
+ const ticker_data_t *const ticker = get_us_ticker_data();
+
+ uint32_t start = ticker_read(ticker);
+ if ((us >= 1000) && core_util_are_interrupts_enabled()) {
+ // Use the RTOS to wait for millisecond delays if possible
+ sleep_manager_lock_deep_sleep();
+ Thread::wait((uint32_t)us / 1000);
+ sleep_manager_unlock_deep_sleep();
+ }
+ // Use busy waiting for sub-millisecond delays, or for the whole
+ // interval if interrupts are not enabled
+ while ((ticker_read(ticker) - start) < (uint32_t)us);
+}
+
+#endif // #if MBED_CONF_RTOS_PRESENT
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/platform.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/platform.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,35 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PLATFORM_H
+#define MBED_PLATFORM_H
+
+#include <cstddef>
+#include <cstdlib>
+#include <cstdio>
+#include <cstring>
+
+#include "platform/mbed_retarget.h"
+#include "platform/mbed_toolchain.h"
+#include "device.h"
+#include "PinNames.h"
+#include "PeripheralNames.h"
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/rtc_time.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/platform/rtc_time.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_RTC_TIME_H +#define MBED_OLD_RTC_TIME_H + +#warning rtc_time.h has been replaced by mbed_rtc_time.h, please update to mbed_rtc_time.h [since mbed-os-5.3] +#include "platform/mbed_rtc_time.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/semihost_api.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/platform/semihost_api.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_SEMIHOST_API_H +#define MBED_OLD_SEMIHOST_API_H + +#warning semihost_api.h has been replaced by mbed_semihost_api.h, please update to mbed_semihost_api.h [since mbed-os-5.3] +#include "platform/mbed_semihost_api.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/sleep.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/platform/sleep.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_SLEEP_H +#define MBED_OLD_SLEEP_H + +#warning sleep.h has been replaced by mbed_power_mgmt.h, please update to mbed_power_mgmt.h [since mbed-os-5.8] +#include "platform/mbed_power_mgmt.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/toolchain.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/platform/toolchain.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,28 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OLD_TOOLCHAIN_H
+#define MBED_OLD_TOOLCHAIN_H
+
+#warning toolchain.h has been replaced by mbed_toolchain.h, please update to mbed_toolchain.h [since mbed-os-5.3]
+#include "platform/mbed_toolchain.h"
+
+#endif
+
+/** @}*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/platform/wait_api.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/platform/wait_api.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_WAIT_API_H +#define MBED_OLD_WAIT_API_H + +#warning wait_api.h has been replaced by mbed_wait_api.h, please update to mbed_wait_api.h [since mbed-os-5.3] +#include "platform/mbed_wait_api.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/PeripheralPins.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/PeripheralPins.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,83 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +//*** ADC *** +#ifdef DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +extern const PinMap PinMap_ADC_Internal[]; +#endif + +//*** DAC *** +#ifdef DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +//*** I2C *** +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +//*** PWM *** +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM[]; +#endif + +//*** SERIAL *** +#ifdef DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +#ifdef DEVICE_SERIAL_FC +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif +#endif + +//*** SPI *** +#ifdef DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +//*** CAN *** +#ifdef DEVICE_CAN +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; +#endif + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/PinNamesTypes.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/PinNamesTypes.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMESTYPES_H
+#define MBED_PINNAMESTYPES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* STM PIN data as used in pin_function is coded on 32 bits as below
+ * [2:0] Function (like in MODER reg) : Input / Output / Alt / Analog
+ * [3] Output Push-Pull / Open Drain (as in OTYPER reg)
+ * [5:4] as in PUPDR reg: No Pull, Pull-up, Pull-Donc
+ * [7:6] Reserved for speed config (as in OSPEEDR), but not used yet
+ * [11:8] Alternate Num (as in AFRL/AFRG reg)
+ * [16:12] Channel (Analog/Timer specific)
+ * [17] Inverted (Analog/Timer specific)
+ * [18] Analog ADC control - Only valid for specific families
+ * [32:19] Reserved
+ */
+
+#define STM_PIN_FUNCTION_MASK 0x07
+#define STM_PIN_FUNCTION_SHIFT 0
+#define STM_PIN_FUNCTION_BITS (STM_PIN_FUNCTION_MASK << STM_PIN_FUNCTION_SHIFT)
+
+#define STM_PIN_OD_MASK 0x01
+#define STM_PIN_OD_SHIFT 3
+#define STM_PIN_OD_BITS (STM_PIN_OD_MASK << STM_PIN_OD_SHIFT)
+
+#define STM_PIN_PUPD_MASK 0x03
+#define STM_PIN_PUPD_SHIFT 4
+#define STM_PIN_PUPD_BITS (STM_PIN_PUPD_MASK << STM_PIN_PUPD_SHIFT)
+
+#define STM_PIN_SPEED_MASK 0x03
+#define STM_PIN_SPEED_SHIFT 6
+#define STM_PIN_SPEED_BITS (STM_PIN_SPEED_MASK << STM_PIN_SPEED_SHIFT)
+
+#define STM_PIN_AFNUM_MASK 0x0F
+#define STM_PIN_AFNUM_SHIFT 8
+#define STM_PIN_AFNUM_BITS (STM_PIN_AFNUM_MASK << STM_PIN_AFNUM_SHIFT)
+
+#define STM_PIN_CHAN_MASK 0x1F
+#define STM_PIN_CHAN_SHIFT 12
+#define STM_PIN_CHANNEL_BIT (STM_PIN_CHAN_MASK << STM_PIN_CHAN_SHIFT)
+
+#define STM_PIN_INV_MASK 0x01
+#define STM_PIN_INV_SHIFT 17
+#define STM_PIN_INV_BIT (STM_PIN_INV_MASK << STM_PIN_INV_SHIFT)
+
+#define STM_PIN_AN_CTRL_MASK 0x01
+#define STM_PIN_AN_CTRL_SHIFT 18
+#define STM_PIN_ANALOG_CONTROL_BIT (STM_PIN_AN_CTRL_MASK << STM_PIN_AN_CTRL_SHIFT)
+
+#define STM_PIN_FUNCTION(X) (((X) >> STM_PIN_FUNCTION_SHIFT) & STM_PIN_FUNCTION_MASK)
+#define STM_PIN_OD(X) (((X) >> STM_PIN_OD_SHIFT) & STM_PIN_OD_MASK)
+#define STM_PIN_PUPD(X) (((X) >> STM_PIN_PUPD_SHIFT) & STM_PIN_PUPD_MASK)
+#define STM_PIN_SPEED(X) (((X) >> STM_PIN_SPEED_SHIFT) & STM_PIN_SPEED_MASK)
+#define STM_PIN_AFNUM(X) (((X) >> STM_PIN_AFNUM_SHIFT) & STM_PIN_AFNUM_MASK)
+#define STM_PIN_CHANNEL(X) (((X) >> STM_PIN_CHAN_SHIFT) & STM_PIN_CHAN_MASK)
+#define STM_PIN_INVERTED(X) (((X) >> STM_PIN_INV_SHIFT) & STM_PIN_INV_MASK)
+#define STM_PIN_ANALOG_CONTROL(X) (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK)
+
+#define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM) ((int)(FUNC_OD) |\
+ ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
+ ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT))
+
+#define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \
+ ((int)(FUNC_OD) |\
+ ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
+ ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
+ ((CHAN & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\
+ ((INV & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT))
+
+/*
+ * MACROS to support the legacy definition of PIN formats
+ * The STM_MODE_ defines contain the function and the Push-pull/OpenDrain
+ * configuration (legacy inheritance).
+ */
+#define STM_PIN_DATA(FUNC_OD, PUPD, AFNUM) \
+ STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM)
+#define STM_PIN_DATA_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED) \
+ STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED)
+
+typedef enum {
+ STM_PIN_INPUT = 0,
+ STM_PIN_OUTPUT = 1,
+ STM_PIN_ALTERNATE = 2,
+ STM_PIN_ANALOG = 3,
+} StmPinFunction;
+
+#define STM_MODE_INPUT (STM_PIN_INPUT)
+#define STM_MODE_OUTPUT_PP (STM_PIN_OUTPUT)
+#define STM_MODE_OUTPUT_OD (STM_PIN_OUTPUT | STM_PIN_OD_BITS)
+#define STM_MODE_AF_PP (STM_PIN_ALTERNATE)
+#define STM_MODE_AF_OD (STM_PIN_ALTERNATE | STM_PIN_OD_BITS)
+#define STM_MODE_ANALOG (STM_PIN_ANALOG)
+#define STM_MODE_ANALOG_ADC_CONTROL (STM_PIN_ANALOG | STM_PIN_ANALOG_CONTROL_BIT)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+/* Defines to be used by application */
+typedef enum {
+ PIN_INPUT = 0,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrainPullUp = 3,
+ OpenDrainNoPull = 4,
+ OpenDrainPullDown = 5,
+ PushPullNoPull = PullNone,
+ PushPullPullUp = PullUp,
+ PushPullPullDown = PullDown,
+ OpenDrain = OpenDrainPullUp,
+ PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/PortNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/PortNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortE = 4,
+ PortF = 5,
+ PortG = 6,
+ PortH = 7,
+ PortI = 8,
+ PortJ = 9,
+ PortK = 10
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,212 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK
+// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,247 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ // Not connected
+ NC = -1,
+
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Module pins
+ // Defined based on the external pin (40-pin connector) alternate function mapping (Page 15 of MTQ-H5-B01 device guide)
+ // Device guide used: S000628,Version1.4
+ P_1 = PB_6,
+ P_2 = PA_14,
+ P_3 = PA_15,
+ P_4 = PB_4,
+ P_5 = NC,
+ P_6 = NC,
+ P_7 = NC,
+ P_8 = NC,
+ P_9 = PA_2,
+ P_10 = PA_7,
+ P_11 = PB_1,
+ P_12 = PA_1,
+ P_13 = NC,
+ P_14 = PB_5,
+ P_15 = PA_5,
+ P_16 = PB_8,
+ P_17 = PB_15,
+ P_18 = PC_2,
+ P_19 = PB_0,
+ P_20 = PC_0,
+ P_21 = PC_1,
+ P_22 = PC_4,
+ P_23 = PB_13,
+ P_24 = PC_9,
+ P_25 = PB_9,
+ P_26 = PA_6,
+ P_27 = PC_8,
+ P_28 = NC,
+ P_29 = PA_0,
+ P_30 = PA_9,
+ P_31 = PA_8,
+ P_32 = PA_3,
+ P_33 = NC,
+ P_34 = NC,
+ P_35 = NC,
+ P_36 = NC,
+ P_37 = NC,
+ P_38 = PB_3,
+ P_39 = PA_13,
+ P_40 = PB_7,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#elif MBED_CONF_TARGET_USB_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_TX,
+#else
+ STDIO_UART_TX = PB_6,
+#endif
+
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#elif MBED_CONF_TARGET_USB_RX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_RX,
+#else
+ STDIO_UART_RX = PB_7,
+#endif
+
+ //DAPLink
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ SWDIO = PA_13,
+ SWCLK = PA_14,
+
+ I2C1_SCL = PB_8,
+ I2C1_SDA = PB_9,
+ I2C3_SCL = PA_8,
+ I2C3_SDA = PC_9,
+
+ I2C_SCL = I2C1_SCL,
+ I2C_SDA = I2C1_SDA,
+
+ SPI1_MOSI = PB_5,
+ SPI1_MISO = PA_6,
+ SPI1_SCK = PA_5,
+ SPI2_MOSI = PB_15,
+ SPI2_MISO = PC_2,
+ SPI2_SCK = PB_13,
+
+ SPI_MOSI = SPI1_MOSI,
+ SPI_MISO = SPI1_MISO,
+ SPI_SCK = SPI1_SCK,
+ SPI_CS1 = PA_3, //LCD CS
+ SPI_CS2 = PA_15, //SD Card CS
+
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_3,
+ SERIAL_RTS = PA_0,
+ SERIAL_CTS = PA_1,
+ SERIAL_DCD = PA_7,
+ SERIAL_DSR = PA_9,
+ SERIAL_DTR = PA_8,
+ SERIAL_RI = PB_1,
+
+ WAKEUP = PA_0,
+
+ // Generic signals namings
+ LED1 = PA_7,
+ LED2 = PC_4,
+ LED3 = PB_13, //MTB mapped to LINK_STATUS pin on module.
+ SW1 = PB_4,
+ GPIO1 = PC_8,
+ GPIO3 = PB_1,
+ AIN0 = PB_0,
+ AIN1 = PC_0,
+ AIN2 = PC_1,
+
+ //Standardized button names
+ BUTTON1 = SW1,
+
+ RADIO_TX = PC_7,
+ RADIO_RX = PC_6,
+ RADIO_RTS = PB_10,
+ RADIO_CTS = PB_12,
+ RADIO_DCD = NC,
+ RADIO_DSR = NC,
+ RADIO_DTR = NC,
+ RADIO_RI = NC,
+ MDMPWRON = PC_13, // 3G_ONOFF DragonFly Design Guide, Page No. 16
+ MDMTXD = RADIO_TX, // Transmit Data
+ MDMRXD = RADIO_RX, // Receive Data
+ MDMRTS = RADIO_RTS, // Request to Send
+ MDMCTS = RADIO_CTS, // Clear to Send
+ MDMDCD = RADIO_DCD, // Data Carrier Detect
+ MDMDSR = RADIO_DSR, // Data Set Ready
+ MDMDTR = RADIO_DTR, // Data Terminal Ready
+ MDMRI = RADIO_RI, // Ring Indicator
+
+} PinName;
+
+#define ACTIVE_HIGH_POLARITY 1
+#define ACTIVE_LOW_POLARITY 0
+
+#define MDM_PIN_POLARITY ACTIVE_HIGH_POLARITY
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,371 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,47 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+; FIRST 64 KB FLASH FOR BOOTLOADER
+; REST 448 KB FLASH FOR APPLICATION
+LR_IROM1 0x08010000 0x70000 { ; load region size_region
+
+ ER_IROM1 0x08010000 0x70000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,344 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/stm32f411re.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/stm32f411re.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,47 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+; FIRST 64 KB FLASH FOR BOOTLOADER
+; REST 448 KB FLASH FOR APPLICATION
+LR_IROM1 0x08010000 0x70000 { ; load region size_region
+
+ ER_IROM1 0x08010000 0x70000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,153 @@
+/* Linker script for STM32F411 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* First 64kB of flash reserved for bootloader */
+ /* Other 448kB for application */
+ FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K
+/* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */
+ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,297 @@ +/* File: startup_STM32F40x.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 09 July 2012 + * + * Copyright (c) 2011, 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WWDG_IRQHandler /* Window WatchDog */ + .long PVD_IRQHandler /* PVD through EXTI Line detection */ + .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .long FLASH_IRQHandler /* FLASH */ + .long RCC_IRQHandler /* RCC */ + .long EXTI0_IRQHandler /* EXTI Line0 */ + .long EXTI1_IRQHandler /* EXTI Line1 */ + .long EXTI2_IRQHandler /* EXTI Line2 */ + .long EXTI3_IRQHandler /* EXTI Line3 */ + .long EXTI4_IRQHandler /* EXTI Line4 */ + .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long EXTI9_5_IRQHandler /* External Line[9:5]s */ + .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .long TIM2_IRQHandler /* TIM2 */ + .long TIM3_IRQHandler /* TIM3 */ + .long TIM4_IRQHandler /* TIM4 */ + .long I2C1_EV_IRQHandler /* I2C1 Event */ + .long I2C1_ER_IRQHandler /* I2C1 Error */ + .long I2C2_EV_IRQHandler /* I2C2 Event */ + .long I2C2_ER_IRQHandler /* I2C2 Error */ + .long SPI1_IRQHandler /* SPI1 */ + .long SPI2_IRQHandler /* SPI2 */ + .long USART1_IRQHandler /* USART1 */ + .long USART2_IRQHandler /* USART2 */ + .long 0 /* Reserved */ + .long EXTI15_10_IRQHandler /* External Line[15:10]s */ + .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .long 0 /* Reserved */ + .long SDIO_IRQHandler /* SDIO */ + .long TIM5_IRQHandler /* TIM5 */ + .long SPI3_IRQHandler /* SPI3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long OTG_FS_IRQHandler /* USB OTG FS */ + .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .long USART6_IRQHandler /* USART6 */ + .long I2C3_EV_IRQHandler /* I2C3 event */ + .long I2C3_ER_IRQHandler /* I2C3 error */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long FPU_IRQHandler /* FPU */ + .long SPI4_IRQHandler /* SPI4 */ + .long SPI5_IRQHandler /* SPI5 */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler WWDG_IRQHandler + def_irq_default_handler PVD_IRQHandler + def_irq_default_handler TAMP_STAMP_IRQHandler + def_irq_default_handler RTC_WKUP_IRQHandler + def_irq_default_handler FLASH_IRQHandler + def_irq_default_handler RCC_IRQHandler + def_irq_default_handler EXTI0_IRQHandler + def_irq_default_handler EXTI1_IRQHandler + def_irq_default_handler EXTI2_IRQHandler + def_irq_default_handler EXTI3_IRQHandler + def_irq_default_handler EXTI4_IRQHandler + def_irq_default_handler DMA1_Stream0_IRQHandler + def_irq_default_handler DMA1_Stream1_IRQHandler + def_irq_default_handler DMA1_Stream2_IRQHandler + def_irq_default_handler DMA1_Stream3_IRQHandler + def_irq_default_handler DMA1_Stream4_IRQHandler + def_irq_default_handler DMA1_Stream5_IRQHandler + def_irq_default_handler DMA1_Stream6_IRQHandler + def_irq_default_handler ADC_IRQHandler + def_irq_default_handler EXTI9_5_IRQHandler + def_irq_default_handler TIM1_BRK_TIM9_IRQHandler + def_irq_default_handler TIM1_UP_TIM10_IRQHandler + def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler + def_irq_default_handler TIM1_CC_IRQHandler + def_irq_default_handler TIM2_IRQHandler + def_irq_default_handler TIM3_IRQHandler + def_irq_default_handler TIM4_IRQHandler + def_irq_default_handler I2C1_EV_IRQHandler + def_irq_default_handler I2C1_ER_IRQHandler + def_irq_default_handler I2C2_EV_IRQHandler + def_irq_default_handler I2C2_ER_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler SPI2_IRQHandler + def_irq_default_handler USART1_IRQHandler + def_irq_default_handler USART2_IRQHandler + def_irq_default_handler EXTI15_10_IRQHandler + def_irq_default_handler RTC_Alarm_IRQHandler + def_irq_default_handler OTG_FS_WKUP_IRQHandler + def_irq_default_handler DMA1_Stream7_IRQHandler + def_irq_default_handler SDIO_IRQHandler + def_irq_default_handler TIM5_IRQHandler + def_irq_default_handler SPI3_IRQHandler + def_irq_default_handler DMA2_Stream0_IRQHandler + def_irq_default_handler DMA2_Stream1_IRQHandler + def_irq_default_handler DMA2_Stream2_IRQHandler + def_irq_default_handler DMA2_Stream3_IRQHandler + def_irq_default_handler DMA2_Stream4_IRQHandler + def_irq_default_handler OTG_FS_IRQHandler + def_irq_default_handler DMA2_Stream5_IRQHandler + def_irq_default_handler DMA2_Stream6_IRQHandler + def_irq_default_handler DMA2_Stream7_IRQHandler + def_irq_default_handler USART6_IRQHandler + def_irq_default_handler I2C3_EV_IRQHandler + def_irq_default_handler I2C3_ER_IRQHandler + def_irq_default_handler FPU_IRQHandler + def_irq_default_handler SPI4_IRQHandler + def_irq_default_handler SPI5_IRQHandler + def_irq_default_handler DEF_IRQHandler + + .end
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,521 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/stm32f411xe.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/stm32f411xe.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,32 @@
+/* [ROM = 512kb = 0x80000] */
+define symbol __intvec_start__ = 0x08010000;
+define symbol __region_ROM_start__ = 0x08010000;
+define symbol __region_ROM_end__ = 0x0807FFFF;
+
+/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000198;
+define symbol __region_RAM_end__ = 0x2001FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/* Stack: 4kB - 408B for vector table */
+/* Heap: 64kB */
+define symbol __size_cstack__ = 0xe68;
+define symbol __size_heap__ = 0x10000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F411RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197 +// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM +#define NVIC_NUM_VECTORS 102 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,8683 @@
+/**
+ ******************************************************************************
+ * @file stm32f411xe.h
+ * @author MCD Application Team
+ * @version V2.6.1
+ * @date 14-February-2017
+ * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f411xe
+ * @{
+ */
+
+#ifndef __STM32F411xE_H
+#define __STM32F411xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC1_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC1_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_FMSSR_Pos (20U)
+#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
+#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR_Pos (21U)
+#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
+#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+#define RCC_BDCR_LSEMOD_Pos (3U)
+#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
+#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
+#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
+#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
+#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
+#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
+#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
+#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
+#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x20003010U
+
+#define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F411xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ #define STM32F411xE /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,238 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 16 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100 | 100
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 100 | 100
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 50 | 50
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 100 | 100
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | NO | NO
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_debug.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#ifndef VECT_TAB_OFFSET
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif
+
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0) {
+ while(1) {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
+ RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if MBED_CONF_NSAPI_PRESENT
+
+#include "cellular/onboard_modem_api.h"
+#include "gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "PinNames.h"
+
+#if MODEM_ON_BOARD
+
+static void press_power_button(int time_ms)
+{
+ gpio_t gpio;
+
+ gpio_init_out_ex(&gpio, MDMPWRON, 1);
+ gpio_write(&gpio, 0);
+ wait_ms(time_ms);
+ gpio_write(&gpio, 1);
+}
+
+void onboard_modem_init()
+{
+ //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed
+}
+
+void onboard_modem_deinit()
+{
+ //does nothing at the moment, TODO: MultiTech to add hardware de-initialization stuff if needed
+}
+void onboard_modem_power_up()
+{
+ /* keep the power line low for 200 milisecond */
+ press_power_button(200);
+ /* give modem a little time to respond */
+ wait_ms(100);
+}
+
+void onboard_modem_power_down()
+{
+ gpio_t gpio;
+
+ gpio_init_out_ex(&gpio, MDMPWRON, 0);
+ /* keep the power line low for more than 10 seconds.
+ * If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes
+ * place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10
+ * seconds only */
+ wait_ms(10 * 1000);
+}
+#endif //MODEM_ON_BOARD
+#endif //MBED_CONF_NSAPI_PRESENT
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+#define STDIO_UART_TX PB_6
+#define STDIO_UART_RX PB_7
+#define STDIO_UART UART_1
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,212 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK
+// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,205 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ // Not connected
+ NC = -1,
+
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PC_2,
+ A1 = PC_0,
+ A2 = PC_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_9,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PB_15,
+ D3 = PA_0,
+ D4 = PA_7,
+ D5 = PA_9,
+ D6 = PA_1,
+ D7 = PA_8,
+ D8 = PB_1,
+ D9 = PB_13,
+ D10 = PC_8,
+ D11 = PB_5,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // Generic signals namings
+ LED1 = D3,
+ LED2 = D3,
+ LED3 = D3,
+ LED4 = D3,
+ SERIAL_TX = D1,
+ SERIAL_RX = D0,
+ SERIAL_RTS = D3,
+ SERIAL_CTS = D6,
+ SERIAL_DCD = D4,
+ SERIAL_DSR = D5,
+ SERIAL_DTR = D7,
+ SERIAL_RI = D8,
+ USBTX = PB_6,
+ USBRX = PB_7,
+ RADIO_TX = PC_7,
+ RADIO_RX = PC_6,
+ RADIO_RTS = PB_10,
+ RADIO_CTS = PB_12,
+ RADIO_DCD = NC,
+ RADIO_DSR = NC,
+ RADIO_DTR = NC,
+ RADIO_RI = NC,
+ MDMPWRON = PC_13, // 3G_ONOFF DragonFly Design Guide, Page No. 16
+ MDMTXD = RADIO_TX, // Transmit Data
+ MDMRXD = RADIO_RX, // Receive Data
+ MDMRTS = RADIO_RTS, // Request to Send
+ MDMCTS = RADIO_CTS, // Clear to Send
+ MDMDCD = RADIO_DCD, // Data Carrier Detect
+ MDMDSR = RADIO_DSR, // Data Set Ready
+ MDMDTR = RADIO_DTR, // Data Terminal Ready
+ MDMRI = RADIO_RI, // Ring Indicator
+
+ WAKEUP = D3,
+
+ // I2C1 and I2C3 are available on Arduino pins
+ I2C1_SCL = D15,
+ I2C1_SDA = D14,
+ I2C3_SCL = D7,
+ I2C3_SDA = A5,
+
+ // legacy definitions
+ I2C_SCL = I2C1_SCL,
+ I2C_SDA = I2C1_SDA,
+
+ // SPI1 and SPI2 are available on Arduino pins
+ SPI1_MOSI = D11,
+ SPI1_MISO = D12,
+ SPI1_SCK = D13,
+ SPI2_MOSI = D2,
+ SPI2_MISO = A0,
+ SPI2_SCK = D9,
+
+ // SPI3 connects to flash part
+ SPI3_MOSI = PC_12,
+ SPI3_MISO = PC_11,
+ SPI3_SCK = PC_10,
+
+ // legacy definitions
+ SPI_MOSI = SPI3_MOSI,
+ SPI_MISO = SPI3_MISO,
+ SPI_SCK = SPI3_SCK,
+ SPI_CS1 = PA_4,
+ SPI_CS2 = PB_14
+
+} PinName;
+
+#define ACTIVE_HIGH_POLARITY 1
+#define ACTIVE_LOW_POLARITY 0
+
+#define MDM_PIN_POLARITY ACTIVE_HIGH_POLARITY
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,371 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,47 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+; FIRST 64 KB FLASH FOR BOOTLOADER
+; REST 448 KB FLASH FOR APPLICATION
+LR_IROM1 0x08010000 0x70000 { ; load region size_region
+
+ ER_IROM1 0x08010000 0x70000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,344 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_STD/stm32f411re.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_STD/stm32f411re.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,47 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+; FIRST 64 KB FLASH FOR BOOTLOADER
+; REST 448 KB FLASH FOR APPLICATION
+LR_IROM1 0x08010000 0x70000 { ; load region size_region
+
+ ER_IROM1 0x08010000 0x70000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,153 @@
+/* Linker script for STM32F411 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* First 64kB of flash reserved for bootloader */
+ /* Other 448kB for application */
+ FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K
+/* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */
+ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,297 @@ +/* File: startup_STM32F40x.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 09 July 2012 + * + * Copyright (c) 2011, 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WWDG_IRQHandler /* Window WatchDog */ + .long PVD_IRQHandler /* PVD through EXTI Line detection */ + .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .long FLASH_IRQHandler /* FLASH */ + .long RCC_IRQHandler /* RCC */ + .long EXTI0_IRQHandler /* EXTI Line0 */ + .long EXTI1_IRQHandler /* EXTI Line1 */ + .long EXTI2_IRQHandler /* EXTI Line2 */ + .long EXTI3_IRQHandler /* EXTI Line3 */ + .long EXTI4_IRQHandler /* EXTI Line4 */ + .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long EXTI9_5_IRQHandler /* External Line[9:5]s */ + .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .long TIM2_IRQHandler /* TIM2 */ + .long TIM3_IRQHandler /* TIM3 */ + .long TIM4_IRQHandler /* TIM4 */ + .long I2C1_EV_IRQHandler /* I2C1 Event */ + .long I2C1_ER_IRQHandler /* I2C1 Error */ + .long I2C2_EV_IRQHandler /* I2C2 Event */ + .long I2C2_ER_IRQHandler /* I2C2 Error */ + .long SPI1_IRQHandler /* SPI1 */ + .long SPI2_IRQHandler /* SPI2 */ + .long USART1_IRQHandler /* USART1 */ + .long USART2_IRQHandler /* USART2 */ + .long 0 /* Reserved */ + .long EXTI15_10_IRQHandler /* External Line[15:10]s */ + .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .long 0 /* Reserved */ + .long SDIO_IRQHandler /* SDIO */ + .long TIM5_IRQHandler /* TIM5 */ + .long SPI3_IRQHandler /* SPI3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long OTG_FS_IRQHandler /* USB OTG FS */ + .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .long USART6_IRQHandler /* USART6 */ + .long I2C3_EV_IRQHandler /* I2C3 event */ + .long I2C3_ER_IRQHandler /* I2C3 error */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long FPU_IRQHandler /* FPU */ + .long SPI4_IRQHandler /* SPI4 */ + .long SPI5_IRQHandler /* SPI5 */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler WWDG_IRQHandler + def_irq_default_handler PVD_IRQHandler + def_irq_default_handler TAMP_STAMP_IRQHandler + def_irq_default_handler RTC_WKUP_IRQHandler + def_irq_default_handler FLASH_IRQHandler + def_irq_default_handler RCC_IRQHandler + def_irq_default_handler EXTI0_IRQHandler + def_irq_default_handler EXTI1_IRQHandler + def_irq_default_handler EXTI2_IRQHandler + def_irq_default_handler EXTI3_IRQHandler + def_irq_default_handler EXTI4_IRQHandler + def_irq_default_handler DMA1_Stream0_IRQHandler + def_irq_default_handler DMA1_Stream1_IRQHandler + def_irq_default_handler DMA1_Stream2_IRQHandler + def_irq_default_handler DMA1_Stream3_IRQHandler + def_irq_default_handler DMA1_Stream4_IRQHandler + def_irq_default_handler DMA1_Stream5_IRQHandler + def_irq_default_handler DMA1_Stream6_IRQHandler + def_irq_default_handler ADC_IRQHandler + def_irq_default_handler EXTI9_5_IRQHandler + def_irq_default_handler TIM1_BRK_TIM9_IRQHandler + def_irq_default_handler TIM1_UP_TIM10_IRQHandler + def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler + def_irq_default_handler TIM1_CC_IRQHandler + def_irq_default_handler TIM2_IRQHandler + def_irq_default_handler TIM3_IRQHandler + def_irq_default_handler TIM4_IRQHandler + def_irq_default_handler I2C1_EV_IRQHandler + def_irq_default_handler I2C1_ER_IRQHandler + def_irq_default_handler I2C2_EV_IRQHandler + def_irq_default_handler I2C2_ER_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler SPI2_IRQHandler + def_irq_default_handler USART1_IRQHandler + def_irq_default_handler USART2_IRQHandler + def_irq_default_handler EXTI15_10_IRQHandler + def_irq_default_handler RTC_Alarm_IRQHandler + def_irq_default_handler OTG_FS_WKUP_IRQHandler + def_irq_default_handler DMA1_Stream7_IRQHandler + def_irq_default_handler SDIO_IRQHandler + def_irq_default_handler TIM5_IRQHandler + def_irq_default_handler SPI3_IRQHandler + def_irq_default_handler DMA2_Stream0_IRQHandler + def_irq_default_handler DMA2_Stream1_IRQHandler + def_irq_default_handler DMA2_Stream2_IRQHandler + def_irq_default_handler DMA2_Stream3_IRQHandler + def_irq_default_handler DMA2_Stream4_IRQHandler + def_irq_default_handler OTG_FS_IRQHandler + def_irq_default_handler DMA2_Stream5_IRQHandler + def_irq_default_handler DMA2_Stream6_IRQHandler + def_irq_default_handler DMA2_Stream7_IRQHandler + def_irq_default_handler USART6_IRQHandler + def_irq_default_handler I2C3_EV_IRQHandler + def_irq_default_handler I2C3_ER_IRQHandler + def_irq_default_handler FPU_IRQHandler + def_irq_default_handler SPI4_IRQHandler + def_irq_default_handler SPI5_IRQHandler + def_irq_default_handler DEF_IRQHandler + + .end
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,521 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,32 @@
+/* [ROM = 512kb = 0x80000] */
+define symbol __intvec_start__ = 0x08010000;
+define symbol __region_ROM_start__ = 0x08010000;
+define symbol __region_ROM_end__ = 0x0807FFFF;
+
+/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000198;
+define symbol __region_RAM_end__ = 0x2001FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/* Stack: 4kB - 408B for vector table */
+/* Heap: 64kB */
+define symbol __size_cstack__ = 0xe68;
+define symbol __size_heap__ = 0x10000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F411RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197 +// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM +#define NVIC_NUM_VECTORS 102 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/stm32f411xe.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/stm32f411xe.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,8683 @@
+/**
+ ******************************************************************************
+ * @file stm32f411xe.h
+ * @author MCD Application Team
+ * @version V2.6.1
+ * @date 14-February-2017
+ * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f411xe
+ * @{
+ */
+
+#ifndef __STM32F411xE_H
+#define __STM32F411xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC1_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC1_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_FMSSR_Pos (20U)
+#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
+#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR_Pos (21U)
+#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
+#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+#define RCC_BDCR_LSEMOD_Pos (3U)
+#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
+#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
+#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
+#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
+#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
+#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
+#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
+#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
+#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x20003010U
+
+#define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F411xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ #define STM32F411xE /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,238 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 16 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100 | 100
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 100 | 100
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 50 | 50
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 100 | 100
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | NO | NO
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_debug.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#ifndef VECT_TAB_OFFSET
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif
+
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0) {
+ while(1) {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
+ RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/onboard_modem_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/onboard_modem_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if MBED_CONF_NSAPI_PRESENT
+
+#include "cellular/onboard_modem_api.h"
+#include "gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "PinNames.h"
+
+#if MODEM_ON_BOARD
+
+static void press_power_button(int time_ms)
+{
+ gpio_t gpio;
+
+ gpio_init_out_ex(&gpio, MDMPWRON, 1);
+ gpio_write(&gpio, 0);
+ wait_ms(time_ms);
+ gpio_write(&gpio, 1);
+}
+
+void onboard_modem_init()
+{
+ //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed
+}
+
+void onboard_modem_deinit()
+{
+ //does nothing at the moment, TODO: MultiTech to add hardware de-initialization stuff if needed
+}
+void onboard_modem_power_up()
+{
+ /* keep the power line low for 200 milisecond */
+ press_power_button(200);
+ /* give modem a little time to respond */
+ wait_ms(100);
+}
+
+void onboard_modem_power_down()
+{
+ gpio_t gpio;
+
+ gpio_init_out_ex(&gpio, MDMPWRON, 0);
+ /* keep the power line low for more than 10 seconds.
+ * If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes
+ * place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10
+ * seconds only */
+ wait_ms(10 * 1000);
+}
+#endif //MODEM_ON_BOARD
+#endif //MBED_CONF_NSAPI_PRESENT
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0,
+ DAC_1
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+} UARTName;
+
+#define STDIO_UART_TX PA_2
+#define STDIO_UART_RX PA_3
+#define STDIO_UART UART_2
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,222 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2
+ {NC, NC, 0}
+};
+
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM1_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,150 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Generic signals namings
+ LED1 = PA_9,
+ LED2 = PA_9,
+ LED3 = PA_9,
+ LED4 = PA_9,
+ SERIAL_TX = PA_9,
+ SERIAL_RX = PA_10,
+ I2C_SCL = PA_8,
+ I2C_SDA = PC_9,
+ SPI_MOSI = PC_12,
+ SPI_MISO = PC_11,
+ SPI_SCK = PC_10,
+ SPI_CS = PC_13,
+ PWM0 = PA_8,
+ PWM1 = PC_9,
+
+ //USB pins
+ USB_OTG_HS_ULPI_D0 = PA_3,
+ USB_OTG_HS_SOF = PA_4,
+ USB_OTG_HS_ULPI_CK = PA_5,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_HS_ULPI_D1 = PB_0,
+ USB_OTG_HS_ULPI_D2 = PB_1,
+ USB_OTG_HS_ULPI_D7 = PB_5,
+ USB_OTG_HS_ULPI_D3 = PB_10,
+ USB_OTG_HS_ULPI_D4 = PB_11,
+ USB_OTG_HS_ID = PB_12,
+ USB_OTG_HS_ULPI_D5 = PB_12,
+ USB_OTG_HS_ULPI_D6 = PB_13,
+ USB_OTG_HS_VBUS = PB_13,
+ USB_OTG_HS_DM = PB_14,
+ USB_OTG_HS_DP = PB_15,
+ USB_OTG_HS_ULPI_STP = PC_0,
+ USB_OTG_HS_ULPI_DIR = PC_2,
+ USB_OTG_HS_ULPI_NXT = PC_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f405xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f405xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,411 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f405xx.s +;* Author : MCD Application Team +;* Description : STM32F405xx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_MICRO/stm32f405xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_MICRO/stm32f405xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F405RG: 1024KB FLASH + 128KB SRAM
+LR_IROM1 0x08000000 0x100000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x100000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x188) (0x20000-0x188) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_STD/startup_stm32f405xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_STD/startup_stm32f405xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,385 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f405xx.s +;* Author : MCD Application Team +;* Description : STM32F405xx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_STD/stm32f405xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_STD/stm32f405xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F405RG: 1024KB FLASH + 128KB SRAM
+LR_IROM1 0x08000000 0x100000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x100000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x188) (0x20000-0x188) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_GCC_ARM/STM32F405.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_GCC_ARM/STM32F405.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,151 @@
+/* Linker script for STM32F405 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 128K - 0x188
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_GCC_ARM/startup_STM32F40x.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_GCC_ARM/startup_STM32F40x.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,316 @@ +/* File: startup_STM32F40x.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 09 July 2012 + * + * Copyright (c) 2011, 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WWDG_IRQHandler /* Window WatchDog */ + .long PVD_IRQHandler /* PVD through EXTI Line detection */ + .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .long FLASH_IRQHandler /* FLASH */ + .long RCC_IRQHandler /* RCC */ + .long EXTI0_IRQHandler /* EXTI Line0 */ + .long EXTI1_IRQHandler /* EXTI Line1 */ + .long EXTI2_IRQHandler /* EXTI Line2 */ + .long EXTI3_IRQHandler /* EXTI Line3 */ + .long EXTI4_IRQHandler /* EXTI Line4 */ + .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .long CAN1_TX_IRQHandler /* CAN1 TX */ + .long CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .long CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .long CAN1_SCE_IRQHandler /* CAN1 SCE */ + .long EXTI9_5_IRQHandler /* External Line[9:5]s */ + .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .long TIM2_IRQHandler /* TIM2 */ + .long TIM3_IRQHandler /* TIM3 */ + .long TIM4_IRQHandler /* TIM4 */ + .long I2C1_EV_IRQHandler /* I2C1 Event */ + .long I2C1_ER_IRQHandler /* I2C1 Error */ + .long I2C2_EV_IRQHandler /* I2C2 Event */ + .long I2C2_ER_IRQHandler /* I2C2 Error */ + .long SPI1_IRQHandler /* SPI1 */ + .long SPI2_IRQHandler /* SPI2 */ + .long USART1_IRQHandler /* USART1 */ + .long USART2_IRQHandler /* USART2 */ + .long USART3_IRQHandler /* USART3 */ + .long EXTI15_10_IRQHandler /* External Line[15:10]s */ + .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .long FSMC_IRQHandler /* FSMC */ + .long SDIO_IRQHandler /* SDIO */ + .long TIM5_IRQHandler /* TIM5 */ + .long SPI3_IRQHandler /* SPI3 */ + .long UART4_IRQHandler /* UART4 */ + .long UART5_IRQHandler /* UART5 */ + .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .long TIM7_IRQHandler /* TIM7 */ + .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long CAN2_TX_IRQHandler /* CAN2 TX */ + .long CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .long CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .long CAN2_SCE_IRQHandler /* CAN2 SCE */ + .long OTG_FS_IRQHandler /* USB OTG FS */ + .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .long USART6_IRQHandler /* USART6 */ + .long I2C3_EV_IRQHandler /* I2C3 event */ + .long I2C3_ER_IRQHandler /* I2C3 error */ + .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .long OTG_HS_IRQHandler /* USB OTG HS */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long HASH_RNG_IRQHandler /* Hash and Rng */ + .long FPU_IRQHandler /* FPU */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler WWDG_IRQHandler + def_irq_default_handler PVD_IRQHandler + def_irq_default_handler TAMP_STAMP_IRQHandler + def_irq_default_handler RTC_WKUP_IRQHandler + def_irq_default_handler FLASH_IRQHandler + def_irq_default_handler RCC_IRQHandler + def_irq_default_handler EXTI0_IRQHandler + def_irq_default_handler EXTI1_IRQHandler + def_irq_default_handler EXTI2_IRQHandler + def_irq_default_handler EXTI3_IRQHandler + def_irq_default_handler EXTI4_IRQHandler + def_irq_default_handler DMA1_Stream0_IRQHandler + def_irq_default_handler DMA1_Stream1_IRQHandler + def_irq_default_handler DMA1_Stream2_IRQHandler + def_irq_default_handler DMA1_Stream3_IRQHandler + def_irq_default_handler DMA1_Stream4_IRQHandler + def_irq_default_handler DMA1_Stream5_IRQHandler + def_irq_default_handler DMA1_Stream6_IRQHandler + def_irq_default_handler ADC_IRQHandler + def_irq_default_handler CAN1_TX_IRQHandler + def_irq_default_handler CAN1_RX0_IRQHandler + def_irq_default_handler CAN1_RX1_IRQHandler + def_irq_default_handler CAN1_SCE_IRQHandler + def_irq_default_handler EXTI9_5_IRQHandler + def_irq_default_handler TIM1_BRK_TIM9_IRQHandler + def_irq_default_handler TIM1_UP_TIM10_IRQHandler + def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler + def_irq_default_handler TIM1_CC_IRQHandler + def_irq_default_handler TIM2_IRQHandler + def_irq_default_handler TIM3_IRQHandler + def_irq_default_handler TIM4_IRQHandler + def_irq_default_handler I2C1_EV_IRQHandler + def_irq_default_handler I2C1_ER_IRQHandler + def_irq_default_handler I2C2_EV_IRQHandler + def_irq_default_handler I2C2_ER_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler SPI2_IRQHandler + def_irq_default_handler USART1_IRQHandler + def_irq_default_handler USART2_IRQHandler + def_irq_default_handler USART3_IRQHandler + def_irq_default_handler EXTI15_10_IRQHandler + def_irq_default_handler RTC_Alarm_IRQHandler + def_irq_default_handler OTG_FS_WKUP_IRQHandler + def_irq_default_handler TIM8_BRK_TIM12_IRQHandler + def_irq_default_handler TIM8_UP_TIM13_IRQHandler + def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler + def_irq_default_handler TIM8_CC_IRQHandler + def_irq_default_handler DMA1_Stream7_IRQHandler + def_irq_default_handler FSMC_IRQHandler + def_irq_default_handler SDIO_IRQHandler + def_irq_default_handler TIM5_IRQHandler + def_irq_default_handler SPI3_IRQHandler + def_irq_default_handler UART4_IRQHandler + def_irq_default_handler UART5_IRQHandler + def_irq_default_handler TIM6_DAC_IRQHandler + def_irq_default_handler TIM7_IRQHandler + def_irq_default_handler DMA2_Stream0_IRQHandler + def_irq_default_handler DMA2_Stream1_IRQHandler + def_irq_default_handler DMA2_Stream2_IRQHandler + def_irq_default_handler DMA2_Stream3_IRQHandler + def_irq_default_handler DMA2_Stream4_IRQHandler + def_irq_default_handler CAN2_TX_IRQHandler + def_irq_default_handler CAN2_RX0_IRQHandler + def_irq_default_handler CAN2_RX1_IRQHandler + def_irq_default_handler CAN2_SCE_IRQHandler + def_irq_default_handler OTG_FS_IRQHandler + def_irq_default_handler DMA2_Stream5_IRQHandler + def_irq_default_handler DMA2_Stream6_IRQHandler + def_irq_default_handler DMA2_Stream7_IRQHandler + def_irq_default_handler USART6_IRQHandler + def_irq_default_handler I2C3_EV_IRQHandler + def_irq_default_handler I2C3_ER_IRQHandler + def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler + def_irq_default_handler OTG_HS_EP1_IN_IRQHandler + def_irq_default_handler OTG_HS_WKUP_IRQHandler + def_irq_default_handler OTG_HS_IRQHandler + def_irq_default_handler HASH_RNG_IRQHandler + def_irq_default_handler FPU_IRQHandler + def_irq_default_handler DEF_IRQHandler + + .end
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_IAR/startup_stm32f405xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_IAR/startup_stm32f405xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,621 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f405xx.s +;* Author : MCD Application Team +;* Description : STM32F405xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and RNG + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_IAR/stm32f405xx.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_IAR/stm32f405xx.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,38 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+/* [RAM] Vector table dynamic copy: 98 vectors * 4 bytes = 392 bytes (0x188) */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000187; /* to be aligned on 8 bytes */
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000188;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x4000;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F405RG +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to ... +// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM +#define NVIC_NUM_VECTORS 98 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/stm32f405xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/stm32f405xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,14306 @@
+/**
+ ******************************************************************************
+ * @file stm32f405xx.h
+ * @author MCD Application Team
+ * @version V2.6.1
+ * @date 14-February-2017
+ * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f405xx
+ * @{
+ */
+
+#ifndef __STM32F405xx_H
+#define __STM32F405xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81 /*!< FPU global interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC123_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC123_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2_Pos (8U)
+#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos (9U)
+#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos (10U)
+#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos (11U)
+#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos (12U)
+#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos (13U)
+#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3_Pos (16U)
+#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos (17U)
+#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos (18U)
+#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos (19U)
+#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos (20U)
+#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos (21U)
+#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos (14U)
+#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos (15U)
+#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos (16U)
+#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos (17U)
+#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos (18U)
+#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos (19U)
+#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos (20U)
+#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos (21U)
+#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos (22U)
+#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos (23U)
+#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos (24U)
+#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos (25U)
+#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos (26U)
+#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos (27U)
+#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN_Pos (0U)
+#define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN_Pos (1U)
+#define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP_Pos (2U)
+#define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR1_MWID_Pos (4U)
+#define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR1_FACCEN_Pos (6U)
+#define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN_Pos (8U)
+#define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL_Pos (9U)
+#define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD_Pos (10U)
+#define FSMC_BCR1_WRAPMOD_Msk (0x1U << FSMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG_Pos (11U)
+#define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN_Pos (12U)
+#define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN_Pos (13U)
+#define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD_Pos (14U)
+#define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE_Pos (16U)
+#define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR1_CBURSTRW_Pos (19U)
+#define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN_Pos (0U)
+#define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN_Pos (1U)
+#define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP_Pos (2U)
+#define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR2_MWID_Pos (4U)
+#define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR2_FACCEN_Pos (6U)
+#define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN_Pos (8U)
+#define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL_Pos (9U)
+#define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD_Pos (10U)
+#define FSMC_BCR2_WRAPMOD_Msk (0x1U << FSMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG_Pos (11U)
+#define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN_Pos (12U)
+#define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN_Pos (13U)
+#define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD_Pos (14U)
+#define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR2_CPSIZE_Pos (16U)
+#define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR2_CBURSTRW_Pos (19U)
+#define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN_Pos (0U)
+#define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN_Pos (1U)
+#define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP_Pos (2U)
+#define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR3_MWID_Pos (4U)
+#define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR3_FACCEN_Pos (6U)
+#define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN_Pos (8U)
+#define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL_Pos (9U)
+#define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WRAPMOD_Pos (10U)
+#define FSMC_BCR3_WRAPMOD_Msk (0x1U << FSMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG_Pos (11U)
+#define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN_Pos (12U)
+#define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN_Pos (13U)
+#define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD_Pos (14U)
+#define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR3_CPSIZE_Pos (16U)
+#define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR3_CBURSTRW_Pos (19U)
+#define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN_Pos (0U)
+#define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN_Pos (1U)
+#define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP_Pos (2U)
+#define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR4_MWID_Pos (4U)
+#define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR4_FACCEN_Pos (6U)
+#define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN_Pos (8U)
+#define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL_Pos (9U)
+#define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD_Pos (10U)
+#define FSMC_BCR4_WRAPMOD_Msk (0x1U << FSMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG_Pos (11U)
+#define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN_Pos (12U)
+#define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN_Pos (13U)
+#define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD_Pos (14U)
+#define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR4_CPSIZE_Pos (16U)
+#define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR4_CBURSTRW_Pos (19U)
+#define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET_Pos (0U)
+#define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR1_ADDHLD_Pos (4U)
+#define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR1_DATAST_Pos (8U)
+#define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR1_BUSTURN_Pos (16U)
+#define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR1_CLKDIV_Pos (20U)
+#define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR1_DATLAT_Pos (24U)
+#define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR1_ACCMOD_Pos (28U)
+#define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET_Pos (0U)
+#define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR2_ADDHLD_Pos (4U)
+#define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR2_DATAST_Pos (8U)
+#define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR2_BUSTURN_Pos (16U)
+#define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR2_CLKDIV_Pos (20U)
+#define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR2_DATLAT_Pos (24U)
+#define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR2_ACCMOD_Pos (28U)
+#define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET_Pos (0U)
+#define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR3_ADDHLD_Pos (4U)
+#define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR3_DATAST_Pos (8U)
+#define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR3_BUSTURN_Pos (16U)
+#define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR3_CLKDIV_Pos (20U)
+#define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR3_DATLAT_Pos (24U)
+#define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR3_ACCMOD_Pos (28U)
+#define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET_Pos (0U)
+#define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR4_ADDHLD_Pos (4U)
+#define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR4_DATAST_Pos (8U)
+#define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR4_BUSTURN_Pos (16U)
+#define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR4_CLKDIV_Pos (20U)
+#define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR4_DATLAT_Pos (24U)
+#define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR4_ACCMOD_Pos (28U)
+#define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET_Pos (0U)
+#define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR1_ADDHLD_Pos (4U)
+#define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR1_DATAST_Pos (8U)
+#define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR1_BUSTURN_Pos (16U)
+#define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR1_ACCMOD_Pos (28U)
+#define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET_Pos (0U)
+#define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR2_ADDHLD_Pos (4U)
+#define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR2_DATAST_Pos (8U)
+#define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR2_BUSTURN_Pos (16U)
+#define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR2_ACCMOD_Pos (28U)
+#define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET_Pos (0U)
+#define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR3_ADDHLD_Pos (4U)
+#define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR3_DATAST_Pos (8U)
+#define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR3_BUSTURN_Pos (16U)
+#define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR3_ACCMOD_Pos (28U)
+#define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET_Pos (0U)
+#define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR4_ADDHLD_Pos (4U)
+#define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR4_DATAST_Pos (8U)
+#define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN_Pos (16U)
+#define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR4_ACCMOD_Pos (28U)
+#define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN_Pos (1U)
+#define FSMC_PCR2_PWAITEN_Msk (0x1U << FSMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FSMC_PCR2_PBKEN_Pos (2U)
+#define FSMC_PCR2_PBKEN_Msk (0x1U << FSMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP_Pos (3U)
+#define FSMC_PCR2_PTYP_Msk (0x1U << FSMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk /*!<Memory type */
+
+#define FSMC_PCR2_PWID_Pos (4U)
+#define FSMC_PCR2_PWID_Msk (0x3U << FSMC_PCR2_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 (0x1U << FSMC_PCR2_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCR2_PWID_1 (0x2U << FSMC_PCR2_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCR2_ECCEN_Pos (6U)
+#define FSMC_PCR2_ECCEN_Msk (0x1U << FSMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR_Pos (9U)
+#define FSMC_PCR2_TCLR_Msk (0xFU << FSMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 (0x1U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCR2_TCLR_1 (0x2U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCR2_TCLR_2 (0x4U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCR2_TCLR_3 (0x8U << FSMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCR2_TAR_Pos (13U)
+#define FSMC_PCR2_TAR_Msk (0xFU << FSMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 (0x1U << FSMC_PCR2_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCR2_TAR_1 (0x2U << FSMC_PCR2_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCR2_TAR_2 (0x4U << FSMC_PCR2_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCR2_TAR_3 (0x8U << FSMC_PCR2_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCR2_ECCPS_Pos (17U)
+#define FSMC_PCR2_ECCPS_Msk (0x7U << FSMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 (0x1U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCR2_ECCPS_1 (0x2U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCR2_ECCPS_2 (0x4U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN_Pos (1U)
+#define FSMC_PCR3_PWAITEN_Msk (0x1U << FSMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FSMC_PCR3_PBKEN_Pos (2U)
+#define FSMC_PCR3_PBKEN_Msk (0x1U << FSMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP_Pos (3U)
+#define FSMC_PCR3_PTYP_Msk (0x1U << FSMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk /*!<Memory type */
+
+#define FSMC_PCR3_PWID_Pos (4U)
+#define FSMC_PCR3_PWID_Msk (0x3U << FSMC_PCR3_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 (0x1U << FSMC_PCR3_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCR3_PWID_1 (0x2U << FSMC_PCR3_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCR3_ECCEN_Pos (6U)
+#define FSMC_PCR3_ECCEN_Msk (0x1U << FSMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR_Pos (9U)
+#define FSMC_PCR3_TCLR_Msk (0xFU << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 (0x1U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCR3_TCLR_1 (0x2U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCR3_TCLR_2 (0x4U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCR3_TCLR_3 (0x8U << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCR3_TAR_Pos (13U)
+#define FSMC_PCR3_TAR_Msk (0xFU << FSMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 (0x1U << FSMC_PCR3_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCR3_TAR_1 (0x2U << FSMC_PCR3_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCR3_TAR_2 (0x4U << FSMC_PCR3_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCR3_TAR_3 (0x8U << FSMC_PCR3_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCR3_ECCPS_Pos (17U)
+#define FSMC_PCR3_ECCPS_Msk (0x7U << FSMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 (0x1U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCR3_ECCPS_1 (0x2U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCR3_ECCPS_2 (0x4U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN_Pos (1U)
+#define FSMC_PCR4_PWAITEN_Msk (0x1U << FSMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FSMC_PCR4_PBKEN_Pos (2U)
+#define FSMC_PCR4_PBKEN_Msk (0x1U << FSMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP_Pos (3U)
+#define FSMC_PCR4_PTYP_Msk (0x1U << FSMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk /*!<Memory type */
+
+#define FSMC_PCR4_PWID_Pos (4U)
+#define FSMC_PCR4_PWID_Msk (0x3U << FSMC_PCR4_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 (0x1U << FSMC_PCR4_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCR4_PWID_1 (0x2U << FSMC_PCR4_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCR4_ECCEN_Pos (6U)
+#define FSMC_PCR4_ECCEN_Msk (0x1U << FSMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR_Pos (9U)
+#define FSMC_PCR4_TCLR_Msk (0xFU << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 (0x1U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCR4_TCLR_1 (0x2U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCR4_TCLR_2 (0x4U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCR4_TCLR_3 (0x8U << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCR4_TAR_Pos (13U)
+#define FSMC_PCR4_TAR_Msk (0xFU << FSMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 (0x1U << FSMC_PCR4_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCR4_TAR_1 (0x2U << FSMC_PCR4_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCR4_TAR_2 (0x4U << FSMC_PCR4_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCR4_TAR_3 (0x8U << FSMC_PCR4_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCR4_ECCPS_Pos (17U)
+#define FSMC_PCR4_ECCPS_Msk (0x7U << FSMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 (0x1U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCR4_ECCPS_1 (0x2U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCR4_ECCPS_2 (0x4U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS_Pos (0U)
+#define FSMC_SR2_IRS_Msk (0x1U << FSMC_SR2_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SR2_IRS FSMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FSMC_SR2_ILS_Pos (1U)
+#define FSMC_SR2_ILS_Msk (0x1U << FSMC_SR2_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SR2_ILS FSMC_SR2_ILS_Msk /*!<Interrupt Level status */
+#define FSMC_SR2_IFS_Pos (2U)
+#define FSMC_SR2_IFS_Msk (0x1U << FSMC_SR2_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SR2_IFS FSMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FSMC_SR2_IREN_Pos (3U)
+#define FSMC_SR2_IREN_Msk (0x1U << FSMC_SR2_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SR2_IREN FSMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN_Pos (4U)
+#define FSMC_SR2_ILEN_Msk (0x1U << FSMC_SR2_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN_Pos (5U)
+#define FSMC_SR2_IFEN_Msk (0x1U << FSMC_SR2_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT_Pos (6U)
+#define FSMC_SR2_FEMPT_Msk (0x1U << FSMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS_Pos (0U)
+#define FSMC_SR3_IRS_Msk (0x1U << FSMC_SR3_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SR3_IRS FSMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FSMC_SR3_ILS_Pos (1U)
+#define FSMC_SR3_ILS_Msk (0x1U << FSMC_SR3_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SR3_ILS FSMC_SR3_ILS_Msk /*!<Interrupt Level status */
+#define FSMC_SR3_IFS_Pos (2U)
+#define FSMC_SR3_IFS_Msk (0x1U << FSMC_SR3_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SR3_IFS FSMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FSMC_SR3_IREN_Pos (3U)
+#define FSMC_SR3_IREN_Msk (0x1U << FSMC_SR3_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SR3_IREN FSMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN_Pos (4U)
+#define FSMC_SR3_ILEN_Msk (0x1U << FSMC_SR3_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN_Pos (5U)
+#define FSMC_SR3_IFEN_Msk (0x1U << FSMC_SR3_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT_Pos (6U)
+#define FSMC_SR3_FEMPT_Msk (0x1U << FSMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS_Pos (0U)
+#define FSMC_SR4_IRS_Msk (0x1U << FSMC_SR4_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SR4_IRS FSMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FSMC_SR4_ILS_Pos (1U)
+#define FSMC_SR4_ILS_Msk (0x1U << FSMC_SR4_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SR4_ILS FSMC_SR4_ILS_Msk /*!<Interrupt Level status */
+#define FSMC_SR4_IFS_Pos (2U)
+#define FSMC_SR4_IFS_Msk (0x1U << FSMC_SR4_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SR4_IFS FSMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FSMC_SR4_IREN_Pos (3U)
+#define FSMC_SR4_IREN_Msk (0x1U << FSMC_SR4_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SR4_IREN FSMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN_Pos (4U)
+#define FSMC_SR4_ILEN_Msk (0x1U << FSMC_SR4_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN_Pos (5U)
+#define FSMC_SR4_IFEN_Msk (0x1U << FSMC_SR4_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT_Pos (6U)
+#define FSMC_SR4_FEMPT_Msk (0x1U << FSMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk /*!<FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2_Pos (0U)
+#define FSMC_PMEM2_MEMSET2_Msk (0xFFU << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
+#define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 (0x01U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
+#define FSMC_PMEM2_MEMSET2_1 (0x02U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
+#define FSMC_PMEM2_MEMSET2_2 (0x04U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
+#define FSMC_PMEM2_MEMSET2_3 (0x08U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
+#define FSMC_PMEM2_MEMSET2_4 (0x10U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
+#define FSMC_PMEM2_MEMSET2_5 (0x20U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
+#define FSMC_PMEM2_MEMSET2_6 (0x40U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
+#define FSMC_PMEM2_MEMSET2_7 (0x80U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEM2_MEMWAIT2_Pos (8U)
+#define FSMC_PMEM2_MEMWAIT2_Msk (0xFFU << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 (0x01U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
+#define FSMC_PMEM2_MEMWAIT2_1 (0x02U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
+#define FSMC_PMEM2_MEMWAIT2_2 (0x04U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
+#define FSMC_PMEM2_MEMWAIT2_3 (0x08U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
+#define FSMC_PMEM2_MEMWAIT2_4 (0x10U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
+#define FSMC_PMEM2_MEMWAIT2_5 (0x20U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
+#define FSMC_PMEM2_MEMWAIT2_6 (0x40U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
+#define FSMC_PMEM2_MEMWAIT2_7 (0x80U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
+
+#define FSMC_PMEM2_MEMHOLD2_Pos (16U)
+#define FSMC_PMEM2_MEMHOLD2_Msk (0xFFU << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 (0x01U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
+#define FSMC_PMEM2_MEMHOLD2_1 (0x02U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
+#define FSMC_PMEM2_MEMHOLD2_2 (0x04U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
+#define FSMC_PMEM2_MEMHOLD2_3 (0x08U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
+#define FSMC_PMEM2_MEMHOLD2_4 (0x10U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
+#define FSMC_PMEM2_MEMHOLD2_5 (0x20U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
+#define FSMC_PMEM2_MEMHOLD2_6 (0x40U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
+#define FSMC_PMEM2_MEMHOLD2_7 (0x80U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEM2_MEMHIZ2_Pos (24U)
+#define FSMC_PMEM2_MEMHIZ2_Msk (0xFFU << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 (0x01U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
+#define FSMC_PMEM2_MEMHIZ2_1 (0x02U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
+#define FSMC_PMEM2_MEMHIZ2_2 (0x04U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
+#define FSMC_PMEM2_MEMHIZ2_3 (0x08U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
+#define FSMC_PMEM2_MEMHIZ2_4 (0x10U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
+#define FSMC_PMEM2_MEMHIZ2_5 (0x20U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
+#define FSMC_PMEM2_MEMHIZ2_6 (0x40U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
+#define FSMC_PMEM2_MEMHIZ2_7 (0x80U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3_Pos (0U)
+#define FSMC_PMEM3_MEMSET3_Msk (0xFFU << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
+#define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 (0x01U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
+#define FSMC_PMEM3_MEMSET3_1 (0x02U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
+#define FSMC_PMEM3_MEMSET3_2 (0x04U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
+#define FSMC_PMEM3_MEMSET3_3 (0x08U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
+#define FSMC_PMEM3_MEMSET3_4 (0x10U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
+#define FSMC_PMEM3_MEMSET3_5 (0x20U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
+#define FSMC_PMEM3_MEMSET3_6 (0x40U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
+#define FSMC_PMEM3_MEMSET3_7 (0x80U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEM3_MEMWAIT3_Pos (8U)
+#define FSMC_PMEM3_MEMWAIT3_Msk (0xFFU << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 (0x01U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
+#define FSMC_PMEM3_MEMWAIT3_1 (0x02U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
+#define FSMC_PMEM3_MEMWAIT3_2 (0x04U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
+#define FSMC_PMEM3_MEMWAIT3_3 (0x08U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
+#define FSMC_PMEM3_MEMWAIT3_4 (0x10U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
+#define FSMC_PMEM3_MEMWAIT3_5 (0x20U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
+#define FSMC_PMEM3_MEMWAIT3_6 (0x40U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
+#define FSMC_PMEM3_MEMWAIT3_7 (0x80U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
+
+#define FSMC_PMEM3_MEMHOLD3_Pos (16U)
+#define FSMC_PMEM3_MEMHOLD3_Msk (0xFFU << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 (0x01U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
+#define FSMC_PMEM3_MEMHOLD3_1 (0x02U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
+#define FSMC_PMEM3_MEMHOLD3_2 (0x04U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
+#define FSMC_PMEM3_MEMHOLD3_3 (0x08U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
+#define FSMC_PMEM3_MEMHOLD3_4 (0x10U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
+#define FSMC_PMEM3_MEMHOLD3_5 (0x20U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
+#define FSMC_PMEM3_MEMHOLD3_6 (0x40U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
+#define FSMC_PMEM3_MEMHOLD3_7 (0x80U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEM3_MEMHIZ3_Pos (24U)
+#define FSMC_PMEM3_MEMHIZ3_Msk (0xFFU << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 (0x01U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
+#define FSMC_PMEM3_MEMHIZ3_1 (0x02U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
+#define FSMC_PMEM3_MEMHIZ3_2 (0x04U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
+#define FSMC_PMEM3_MEMHIZ3_3 (0x08U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
+#define FSMC_PMEM3_MEMHIZ3_4 (0x10U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
+#define FSMC_PMEM3_MEMHIZ3_5 (0x20U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
+#define FSMC_PMEM3_MEMHIZ3_6 (0x40U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
+#define FSMC_PMEM3_MEMHIZ3_7 (0x80U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4_Pos (0U)
+#define FSMC_PMEM4_MEMSET4_Msk (0xFFU << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 (0x01U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PMEM4_MEMSET4_1 (0x02U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PMEM4_MEMSET4_2 (0x04U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PMEM4_MEMSET4_3 (0x08U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PMEM4_MEMSET4_4 (0x10U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PMEM4_MEMSET4_5 (0x20U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PMEM4_MEMSET4_6 (0x40U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PMEM4_MEMSET4_7 (0x80U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEM4_MEMWAIT4_Pos (8U)
+#define FSMC_PMEM4_MEMWAIT4_Msk (0xFFU << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 (0x01U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PMEM4_MEMWAIT4_1 (0x02U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PMEM4_MEMWAIT4_2 (0x04U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PMEM4_MEMWAIT4_3 (0x08U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PMEM4_MEMWAIT4_4 (0x10U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PMEM4_MEMWAIT4_5 (0x20U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PMEM4_MEMWAIT4_6 (0x40U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PMEM4_MEMWAIT4_7 (0x80U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PMEM4_MEMHOLD4_Pos (16U)
+#define FSMC_PMEM4_MEMHOLD4_Msk (0xFFU << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 (0x01U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PMEM4_MEMHOLD4_1 (0x02U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PMEM4_MEMHOLD4_2 (0x04U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PMEM4_MEMHOLD4_3 (0x08U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PMEM4_MEMHOLD4_4 (0x10U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PMEM4_MEMHOLD4_5 (0x20U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PMEM4_MEMHOLD4_6 (0x40U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PMEM4_MEMHOLD4_7 (0x80U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEM4_MEMHIZ4_Pos (24U)
+#define FSMC_PMEM4_MEMHIZ4_Msk (0xFFU << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 (0x01U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PMEM4_MEMHIZ4_1 (0x02U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PMEM4_MEMHIZ4_2 (0x04U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PMEM4_MEMHIZ4_3 (0x08U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PMEM4_MEMHIZ4_4 (0x10U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PMEM4_MEMHIZ4_5 (0x20U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PMEM4_MEMHIZ4_6 (0x40U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PMEM4_MEMHIZ4_7 (0x80U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2_Pos (0U)
+#define FSMC_PATT2_ATTSET2_Msk (0xFFU << FSMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
+#define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 (0x01U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
+#define FSMC_PATT2_ATTSET2_1 (0x02U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
+#define FSMC_PATT2_ATTSET2_2 (0x04U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
+#define FSMC_PATT2_ATTSET2_3 (0x08U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
+#define FSMC_PATT2_ATTSET2_4 (0x10U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
+#define FSMC_PATT2_ATTSET2_5 (0x20U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
+#define FSMC_PATT2_ATTSET2_6 (0x40U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
+#define FSMC_PATT2_ATTSET2_7 (0x80U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATT2_ATTWAIT2_Pos (8U)
+#define FSMC_PATT2_ATTWAIT2_Msk (0xFFU << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 (0x01U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
+#define FSMC_PATT2_ATTWAIT2_1 (0x02U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
+#define FSMC_PATT2_ATTWAIT2_2 (0x04U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
+#define FSMC_PATT2_ATTWAIT2_3 (0x08U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
+#define FSMC_PATT2_ATTWAIT2_4 (0x10U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
+#define FSMC_PATT2_ATTWAIT2_5 (0x20U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
+#define FSMC_PATT2_ATTWAIT2_6 (0x40U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
+#define FSMC_PATT2_ATTWAIT2_7 (0x80U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATT2_ATTHOLD2_Pos (16U)
+#define FSMC_PATT2_ATTHOLD2_Msk (0xFFU << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 (0x01U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
+#define FSMC_PATT2_ATTHOLD2_1 (0x02U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
+#define FSMC_PATT2_ATTHOLD2_2 (0x04U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
+#define FSMC_PATT2_ATTHOLD2_3 (0x08U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
+#define FSMC_PATT2_ATTHOLD2_4 (0x10U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
+#define FSMC_PATT2_ATTHOLD2_5 (0x20U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
+#define FSMC_PATT2_ATTHOLD2_6 (0x40U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
+#define FSMC_PATT2_ATTHOLD2_7 (0x80U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATT2_ATTHIZ2_Pos (24U)
+#define FSMC_PATT2_ATTHIZ2_Msk (0xFFU << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
+#define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 (0x01U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
+#define FSMC_PATT2_ATTHIZ2_1 (0x02U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
+#define FSMC_PATT2_ATTHIZ2_2 (0x04U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
+#define FSMC_PATT2_ATTHIZ2_3 (0x08U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
+#define FSMC_PATT2_ATTHIZ2_4 (0x10U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
+#define FSMC_PATT2_ATTHIZ2_5 (0x20U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
+#define FSMC_PATT2_ATTHIZ2_6 (0x40U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
+#define FSMC_PATT2_ATTHIZ2_7 (0x80U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3_Pos (0U)
+#define FSMC_PATT3_ATTSET3_Msk (0xFFU << FSMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
+#define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 (0x01U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
+#define FSMC_PATT3_ATTSET3_1 (0x02U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
+#define FSMC_PATT3_ATTSET3_2 (0x04U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
+#define FSMC_PATT3_ATTSET3_3 (0x08U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
+#define FSMC_PATT3_ATTSET3_4 (0x10U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
+#define FSMC_PATT3_ATTSET3_5 (0x20U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
+#define FSMC_PATT3_ATTSET3_6 (0x40U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
+#define FSMC_PATT3_ATTSET3_7 (0x80U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATT3_ATTWAIT3_Pos (8U)
+#define FSMC_PATT3_ATTWAIT3_Msk (0xFFU << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 (0x01U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
+#define FSMC_PATT3_ATTWAIT3_1 (0x02U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
+#define FSMC_PATT3_ATTWAIT3_2 (0x04U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
+#define FSMC_PATT3_ATTWAIT3_3 (0x08U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
+#define FSMC_PATT3_ATTWAIT3_4 (0x10U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
+#define FSMC_PATT3_ATTWAIT3_5 (0x20U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
+#define FSMC_PATT3_ATTWAIT3_6 (0x40U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
+#define FSMC_PATT3_ATTWAIT3_7 (0x80U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATT3_ATTHOLD3_Pos (16U)
+#define FSMC_PATT3_ATTHOLD3_Msk (0xFFU << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 (0x01U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
+#define FSMC_PATT3_ATTHOLD3_1 (0x02U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
+#define FSMC_PATT3_ATTHOLD3_2 (0x04U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
+#define FSMC_PATT3_ATTHOLD3_3 (0x08U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
+#define FSMC_PATT3_ATTHOLD3_4 (0x10U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
+#define FSMC_PATT3_ATTHOLD3_5 (0x20U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
+#define FSMC_PATT3_ATTHOLD3_6 (0x40U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
+#define FSMC_PATT3_ATTHOLD3_7 (0x80U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATT3_ATTHIZ3_Pos (24U)
+#define FSMC_PATT3_ATTHIZ3_Msk (0xFFU << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
+#define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 (0x01U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
+#define FSMC_PATT3_ATTHIZ3_1 (0x02U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
+#define FSMC_PATT3_ATTHIZ3_2 (0x04U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
+#define FSMC_PATT3_ATTHIZ3_3 (0x08U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
+#define FSMC_PATT3_ATTHIZ3_4 (0x10U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
+#define FSMC_PATT3_ATTHIZ3_5 (0x20U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
+#define FSMC_PATT3_ATTHIZ3_6 (0x40U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
+#define FSMC_PATT3_ATTHIZ3_7 (0x80U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4_Pos (0U)
+#define FSMC_PATT4_ATTSET4_Msk (0xFFU << FSMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 (0x01U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PATT4_ATTSET4_1 (0x02U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PATT4_ATTSET4_2 (0x04U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PATT4_ATTSET4_3 (0x08U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PATT4_ATTSET4_4 (0x10U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PATT4_ATTSET4_5 (0x20U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PATT4_ATTSET4_6 (0x40U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PATT4_ATTSET4_7 (0x80U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATT4_ATTWAIT4_Pos (8U)
+#define FSMC_PATT4_ATTWAIT4_Msk (0xFFU << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 (0x01U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PATT4_ATTWAIT4_1 (0x02U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PATT4_ATTWAIT4_2 (0x04U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PATT4_ATTWAIT4_3 (0x08U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PATT4_ATTWAIT4_4 (0x10U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PATT4_ATTWAIT4_5 (0x20U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PATT4_ATTWAIT4_6 (0x40U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PATT4_ATTWAIT4_7 (0x80U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATT4_ATTHOLD4_Pos (16U)
+#define FSMC_PATT4_ATTHOLD4_Msk (0xFFU << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 (0x01U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PATT4_ATTHOLD4_1 (0x02U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PATT4_ATTHOLD4_2 (0x04U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PATT4_ATTHOLD4_3 (0x08U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PATT4_ATTHOLD4_4 (0x10U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PATT4_ATTHOLD4_5 (0x20U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PATT4_ATTHOLD4_6 (0x40U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PATT4_ATTHOLD4_7 (0x80U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATT4_ATTHIZ4_Pos (24U)
+#define FSMC_PATT4_ATTHIZ4_Msk (0xFFU << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 (0x01U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PATT4_ATTHIZ4_1 (0x02U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PATT4_ATTHIZ4_2 (0x04U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PATT4_ATTHIZ4_3 (0x08U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PATT4_ATTHIZ4_4 (0x10U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PATT4_ATTHIZ4_5 (0x20U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PATT4_ATTHIZ4_6 (0x40U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PATT4_ATTHIZ4_7 (0x80U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4_Pos (0U)
+#define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PIO4_IOWAIT4_Pos (8U)
+#define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PIO4_IOHOLD4_Pos (16U)
+#define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PIO4_IOHIZ4_Pos (24U)
+#define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2_Pos (0U)
+#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!<ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3_Pos (0U)
+#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x1U << PWR_CR_VOS_Pos) /*!< 0x00004000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS bit (Regulator voltage scaling output selection) */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
+#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
+#define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
+#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
+#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_RNGEN_Pos (6U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FSMCEN_Pos (0U)
+#define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (1U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_ADC2EN_Pos (9U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
+#define RCC_APB2ENR_ADC3EN_Pos (10U)
+#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
+#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
+#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
+#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
+#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
+
+#define RCC_MAX_FREQUENCY 168000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 144000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FMC_IRQn FSMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FMC_IRQHandler FSMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F405xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ #define STM32F405xx /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+#include "stm32f4xx.h"
+
+
+/**
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 26;
+ RCC_OscInitStruct.PLL.PLLN = 192;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_9
+#define STDIO_UART_RX PA_10
+#define STDIO_UART UART_1
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,235 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Generic signals namings
+ XBEE_DOUT = PA_2,
+ XBEE_DIN = PA_3,
+ XBEE_AD0 = PB_1,
+ XBEE_AD1 = PB_0,
+ XBEE_AD2 = PA_5,
+ XBEE_AD3 = PA_4,
+ XBEE_AD4 = PA_7,
+ XBEE_AD5 = PC_1,
+ XBEE_AD6 = PA_1,
+ XBEE_DIO0 = PB_1,
+ XBEE_DIO1 = PB_0,
+ XBEE_DIO2 = PA_5,
+ XBEE_DIO3 = PA_4,
+ XBEE_DIO4 = PA_7,
+ XBEE_DIO5 = PC_1,
+ XBEE_DIO6 = PA_1,
+ XBEE_DIO7 = PA_0,
+ XBEE_DO8 = PA_6,
+ XBEE_DI8 = PA_11,
+ XBEE_PWM0 = PA_8,
+ XBEE_PWM1 = PC_9,
+ XBEE_CTS = PA_0,
+ XBEE_RTS = PA_1,
+ XBEE_DTR = PA_11,
+ XBEE_RSSI = PA_8,
+ XBEE_SLEEPRQ = PA_11,
+ XBEE_ON_SLEEP = PC_13,
+ XBEE_ASSOCIATE = PC_1,
+ XBEE_USB_RES = PA_12,
+
+ // needed for mbed to build tests
+ LED1 = PA_0,
+ LED2 = PA_0,
+ LED3 = PA_0,
+ LED4 = PA_0,
+
+ // XBEE_DOUT/DIN, RS232 port on UDK board
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_3,
+
+ // DB_TX/RX, USB port on UDK board
+ DB_TX = PA_9,
+ DB_RX = PA_10,
+ USBTX = PA_9,
+ USBRX = PA_10,
+
+ // Multiplexed with XBEE pins
+ I2C_SCL = PA_8,
+ I2C_SDA = PC_9,
+ SPI1_MOSI = PA_7,
+ SPI1_MISO = PA_6,
+ SPI1_SCK = PA_5,
+ SPI1_CS = PA_4,
+
+ // SPI flash
+ SPI3_MOSI = PC_12,
+ SPI3_MISO = PC_11,
+ SPI3_SCK = PC_10,
+ SPI3_CS = PC_6,
+ FLASH_HOLD = PC_7,
+ FLASH_WP = PC_8,
+
+ // LoRa
+ LORA_RESET = PC_0,
+ LORA_RXCTL = PC_2,
+ LORA_TXCTL = PC_3,
+ LORA_DIO0 = PB_5,
+ LORA_DIO1 = PB_6,
+ LORA_DIO2 = PB_7,
+ LORA_DIO3 = PB_8,
+ LORA_DIO4 = PB_9,
+ LORA_DIO5 = PB_10,
+ // LoRa/SPI2
+ LORA_NSS = PB_12,
+ LORA_SCK = PB_13,
+ LORA_MISO = PB_14,
+ LORA_MOSI = PB_15,
+
+ // UART pins
+ UART_TX = PA_2,
+ UART_RX = PA_3,
+ UART_CTS = PA_0,
+ UART_RTS = PA_1,
+
+ // SPI pins
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_NSS = PA_4,
+
+ // UDK2 pins
+ A0 = PB_1,
+ A1 = PB_0,
+ A2 = PC_1,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PC_13,
+ D3 = PA_0,
+ D6 = PA_1,
+ D7 = PA_11,
+ D10 = PA_4,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PC_9,
+ D15 = PA_8,
+
+ // mDot GPIO pins
+ GPIO0 = PB_1,
+ GPIO1 = PB_0,
+ GPIO2 = PA_5,
+ GPIO3 = PA_4,
+ GPIO4 = PA_1,
+ GPIO5 = PA_0,
+ GPIO6 = PA_7,
+ GPIO7 = PA_6,
+ ASSOCIATE = PC_1,
+ ON_SLEEP = PC_13,
+ SLEEPRQ = PA_11,
+ RSSI = PA_8,
+ JTAG_SWCLK = PA_14,
+ JTAG_SWIO = PA_13,
+ JTAG_NRST = PB_4,
+ JTAG_SWO = PB_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,371 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,47 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+; FIRST 64 KB FLASH FOR BOOTLOADER
+; REST 448 KB FLASH FOR APPLICATION
+LR_IROM1 0x08010000 0x70000 { ; load region size_region
+
+ ER_IROM1 0x08010000 0x70000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,344 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_STD/stm32f411re.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_STD/stm32f411re.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,47 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+; FIRST 64 KB FLASH FOR BOOTLOADER
+; REST 448 KB FLASH FOR APPLICATION
+LR_IROM1 0x08010000 0x70000 { ; load region size_region
+
+ ER_IROM1 0x08010000 0x70000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_GCC_ARM/STM32F411XE.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_GCC_ARM/STM32F411XE.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,155 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* First 64kB of flash reserved for bootloader */
+ /* Other 448kB for application */
+ FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K
+ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,457 @@ +/** + ****************************************************************************** + * @file startup_stm32f411xe.s + * @author MCD Application Team + * @brief STM32F411xExx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,521 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,31 @@
+/* [ROM = 512kb = 0x80000] */
+define symbol __intvec_start__ = 0x08010000;
+define symbol __region_ROM_start__ = 0x08010000;
+define symbol __region_ROM_end__ = 0x0807FFFF;
+
+/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000198;
+define symbol __region_RAM_end__ = 0x2001FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x4000;
+define symbol __size_heap__ = 0x8000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F411RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197 +// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM +#define NVIC_NUM_VECTORS 102 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f411xe.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f411xe.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,8683 @@
+/**
+ ******************************************************************************
+ * @file stm32f411xe.h
+ * @author MCD Application Team
+ * @version V2.6.1
+ * @date 14-February-2017
+ * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f411xe
+ * @{
+ */
+
+#ifndef __STM32F411xE_H
+#define __STM32F411xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC1_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC1_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_FMSSR_Pos (20U)
+#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
+#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR_Pos (21U)
+#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
+#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+#define RCC_BDCR_LSEMOD_Pos (3U)
+#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
+#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
+#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
+#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
+#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
+#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
+#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
+#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
+#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x20003010U
+
+#define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F411xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ #define STM32F411xE /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,240 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 16 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 96 | 96
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 96 | 96
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 96 | 96
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | NO
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_debug.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#ifndef VECT_TAB_OFFSET
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif
+
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#if !defined (USE_PLL_HSE_EXTC)
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#endif
+#if !defined (USE_PLL_HSE_XTAL)
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+#endif
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0) {
+ while(1) {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; // VCO input clock = 1 MHz
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4) --> Not stable for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,247 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 // Connected to B1 [Blue PushButton]
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to I2S3_WS [CS43L22_LRCK]
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to SPI1_SCK [L3GD20_SC/SPC]
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to SPI1_MISO [L3GD20_AS0/SDO]
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to SPI1_MISO [L3GD20_SDA/SDI/SDO]
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to OTG_FS_PowerSwitchOn
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Connected to PDM_OUT [MP45DT02_DOUT]
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, // Connected to SWO
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to Audio_SDA [CS43L22_SDA]
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to Audio_SCL [CS43L22_SCL]
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to CLK_IN [MP45DT02_CLK]
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to B1 [Blue PushButton]
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to B1 [Blue PushButton]
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to SPI1_SCK [L3GD20_SC/SPC]
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to SPI1_MISO [L3GD20_AS0/SDO]
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to SPI1_MISO [L3GD20_SDA/SDI/SDO]
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SPI1_MISO [L3GD20_SDA/SDI/SDO]
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to VBUS_FS
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to OTG_FS_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to OTG_FS_DM
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to Audio_SCL [CS43L22_SCL]
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to Audio_SDA [CS43L22_SDA]
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to Audio_SDA [CS43L22_SDA]
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to CLK_IN [MP45DT02_CLK]
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to I2S3_MCK [CS43L22_MCLK]
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to LD4 [Green Led]
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD3 [Orange Led]
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to LD5 [Red Led]
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to LD6 [Blue Led]
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to GPXTI5
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to VBUS_FS
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to OTG_FS_DM
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to Audio_SCL [CS43L22_SCL]
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to OTG_FS_OverCurrent
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_ID
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to OTG_FS_DP
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to I2S3_MCK [CS43L22_MCLK]
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_DP
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to Audio_RST [CS43L22_RESET]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B1 [Blue PushButton]
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_DM
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_MISO [L3GD20_SDA/SDI/SDO]
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PDM_OUT [MP45DT02_DOUT]
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_SD [CS43L22_SDIN]
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_MISO [L3GD20_AS0/SDO]
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to GPXTI5
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_SCK [L3GD20_SC/SPC]
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CLK_IN [MP45DT02_CLK]
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_SCK [CS43L22_SCLK]
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to GPIO_Input
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to I2S3_WS [CS43L22_LRCK]
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_WS [CS43L22_LRCK]
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to Audio_SDA [CS43L22_SDA]
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to I2S2_WS
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to GPXTI4
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,221 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_2,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_3,
+#endif
+
+ // Generic signals namings
+ LED1 = PD_12,
+ LED2 = PD_13,
+ LED3 = PD_14,
+ LED4 = PD_15,
+ LED_RED = LED1,
+ USER_BUTTON = PA_0,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED3 = PE_6,
+ SYS_WKUP = PA_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,231 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 16 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 84 | 84
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 84 | 84
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 42 | 42
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 84 | 84
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | NO
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0) {
+ while (1) {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ /*
+ if (bypass == 0)
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+ else
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+ */
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/TOOLCHAIN_GCC_ARM/STM32F401XC.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/TOOLCHAIN_GCC_ARM/STM32F401XC.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+ RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 64k - 0x194
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/TOOLCHAIN_GCC_ARM/startup_stm32f401xc.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/TOOLCHAIN_GCC_ARM/startup_stm32f401xc.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,453 @@ +/** + ****************************************************************************** + * @file startup_stm32f401xc.s + * @author MCD Application Team + * @brief STM32F401xCxx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F401RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ... +// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM +#define NVIC_NUM_VECTORS 101 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f401xc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f401xc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,8599 @@
+/**
+ ******************************************************************************
+ * @file stm32f401xc.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F401xC Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f401xc
+ * @{
+ */
+
+#ifndef __STM32F401xC_H
+#define __STM32F401xC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0803FFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC1_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC1_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+
+/****************** TIM Instances : supporting commutation event generation ***/
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
+
+#define RCC_MAX_FREQUENCY 84000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE3 60000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 192U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F401xC_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ #define STM32F401xC /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,228 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: some pins are connected to the default STDIO_UART_TX and STDIO_UART_RX pins.
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to STDIO_UART_TX
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX
+#endif
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to LD2 [Green Led]
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, // Connected to SWO
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to STDIO_UART_TX
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to STDIO_UART_TX
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to STDIO_UART_RX
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // Connected to STDIO_UART_RX
+#endif
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to LD2 [Green Led]
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD2 [Green Led]
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,207 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E, // Connected to RCC_OSC32_IN
+ PC_15 = 0x2F, // Connected to RCC_OSC32_OUT
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70, // Connected to RCC_OSC_IN
+ PH_1 = 0x71, // Connected to RCC_OSC_OUT
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_0,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = PC_7,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_2,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_3,
+#endif
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ LED_RED = LED1,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_WKUP = PA_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,239 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 84
+ * AHBCLK (MHz) | 84
+ * APB1CLK (MHz) | 42
+ * APB2CLK (MHz) | 84
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/*
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ /*
+ if (bypass == 0)
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+ else
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+ */
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,255 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: some pins are connected to the default STDIO_UART_TX and STDIO_UART_RX pins.
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // TIM5 used by the us_ticker
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // TIM5 used by the us_ticker
+ {PA_2_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // TIM5 used by the us_ticker
+ {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // TIM5 used by the us_ticker
+ {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+#endif
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX (default)
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX (default)
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,198 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PH_0 = 0x70, // Connected to RCC_OSC_IN
+ PH_1 = 0x71, // Connected to RCC_OSC_OUT
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_9,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_10,
+#endif
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ LED_RED = LED1,
+ USER_BUTTON = PE_7,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ //USB pins
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,239 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 25 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 25 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 84
+ * AHBCLK (MHz) | 84
+ * APB1CLK (MHz) | 42
+ * APB2CLK (MHz) | 84
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (Not connected on board)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (Y1 on board)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/*
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 25 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 25 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ /*
+ if (bypass == 0)
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+ else
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+ */
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,366 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f401xe.s +;* Author : MCD Application Team +;* Description : STM32F401xe devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20018000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler + + B . + + ENDP + + ALIGN + END
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_MICRO/stm32f401xe.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_MICRO/stm32f401xe.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F401RE: 512KB FLASH + 96KB SRAM
+LR_IROM1 0x08000000 0x80000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x194) (0x18000-0x194) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_STD/startup_stm32f401xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_STD/startup_stm32f401xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,340 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f401xe.s +;* Author : MCD Application Team +;* Description : STM32F401xe devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + + +__initial_sp EQU 0x20018000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler + + B . + + ENDP + + ALIGN + END
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_STD/stm32f401xe.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_STD/stm32f401xe.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F401RE: 512KB FLASH + 96KB SRAM
+LR_IROM1 0x08000000 0x80000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x194) (0x18000-0x194) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_GCC_ARM/STM32F401XE.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_GCC_ARM/STM32F401XE.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 96k - 0x194
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f401xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f401xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,453 @@ +/** + ****************************************************************************** + * @file startup_stm32f401xe.s + * @author MCD Application Team + * @brief STM32F401xExx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_IAR/startup_stm32f401xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_IAR/startup_stm32f401xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,515 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f401xe.s +;* Author : MCD Application Team +;* Description : STM32F401xExx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_IAR/stm32f401xe.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_IAR/stm32f401xe.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000197; /* to be aligned on 8 bytes */
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000198;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x3000;
+define symbol __ICFEDIT_size_heap__ = 0x6000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F401RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ... +// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM +#define NVIC_NUM_VECTORS 101 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x80000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f401xe.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f401xe.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,8599 @@
+/**
+ ******************************************************************************
+ * @file stm32f401xe.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F401xE Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f401xe
+ * @{
+ */
+
+#ifndef __STM32F401xE_H
+#define __STM32F401xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(96 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(96 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC1_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC1_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+
+/****************** TIM Instances : supporting commutation event generation ***/
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
+
+#define RCC_MAX_FREQUENCY 84000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE3 60000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 192U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F401xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ #define STM32F401xE /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,124 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0,
+ DAC_1
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,208 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {NC, NC, 0}
+};
+
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2
+ {NC, NC, 0}
+};
+
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,263 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+ PH_2 = 0x72,
+ PH_3 = 0x73,
+ PH_4 = 0x74,
+ PH_5 = 0x75,
+ PH_6 = 0x76,
+ PH_7 = 0x77,
+ PH_8 = 0x78,
+ PH_9 = 0x79,
+ PH_10 = 0x7A,
+ PH_11 = 0x7B,
+ PH_12 = 0x7C,
+ PH_13 = 0x7D,
+ PH_14 = 0x7E,
+ PH_15 = 0x7F,
+
+ PI_0 = 0x80,
+ PI_1 = 0x81,
+ PI_2 = 0x82,
+ PI_3 = 0x83,
+ PI_4 = 0x84,
+ PI_5 = 0x85,
+ PI_6 = 0x86,
+ PI_7 = 0x87,
+ PI_8 = 0x88,
+ PI_9 = 0x89,
+ PI_10 = 0x8A,
+ PI_11 = 0x8B,
+ PI_12 = 0x8C,
+ PI_13 = 0x8D,
+ PI_14 = 0x8E,
+ PI_15 = 0x8F,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_3,
+ A2 = PA_4,
+ A3 = PA_5,
+ A4 = PA_6,
+ A5 = PB_0,
+ A6 = PB_1,
+ A7 = PC_0,
+ D0 = PD_3,
+ D1 = PD_6,
+ D2 = PD_11,
+ D3 = PD_12,
+ D4 = PD_13,
+ D5 = PA_8,
+ D6 = PB_6,
+ D7 = PB_7,
+ D8 = PB_15,
+ D9 = PB_14,
+ D10 = PA_15,
+ D11 = PB_5,
+ D12 = PB_4,
+ D13 = PB_3,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PC_6,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PC_7,
+#endif
+
+ // Generic signals namings
+ LED1 = PB_3,
+ LED2 = PD_8,
+ LED3 = PD_9,
+ LED4 = PD_10,
+ USBTX = STDIO_UART_TX, /* USART6 */
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8, /* I2C1 */
+ I2C_SDA = PB_9,
+ SPI_MOSI = PC_3,
+ SPI_MISO = PC_2,
+ SPI_SCK = PB_10,
+ SPI_CS = PE_3,
+ SD_MOSI = PC_3,
+ SD_MISO = PC_2,
+ SD_SCK = PB_10,
+ SD_CS = PE_2,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,232 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 16 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 168 | 168
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 168 | 168
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 42 | 42
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 84 | 84
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | NO
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0) {
+ while (1) {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz (SPI1 clock...)
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ /*
+ if (bypass == 0)
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+ else
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+ */
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,95 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0,
+ DAC_1
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,317 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 // Connected to B1 [Blue PushButton]
+ {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 // Connected to B1 [Blue PushButton]
+ {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 // Connected to B1 [Blue PushButton]
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
+ {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
+ {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
+ {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to I2S3_WS [CS43L22_LRCK]
+ {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // Connected to I2S3_WS [CS43L22_LRCK]
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to SPI1_SCK [LIS302DL_SCL/SPC]
+ {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // Connected to SPI1_SCK [LIS302DL_SCL/SPC]
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to SPI1_MISO [LIS302DL_SDO]
+ {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // Connected to SPI1_MISO [LIS302DL_SDO]
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]
+ {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to OTG_FS_PowerSwitchOn
+ {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to OTG_FS_PowerSwitchOn
+ {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 // Connected to OTG_FS_PowerSwitchOn
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
+ {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+ {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Connected to PDM_OUT [MP45DT02_DOUT]
+ {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 // Connected to PDM_OUT [MP45DT02_DOUT]
+ {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 // Connected to PDM_OUT [MP45DT02_DOUT]
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 // Connected to I2S3_WS [CS43L22_LRCK]
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 // Connected to SPI1_SCK [LIS302DL_SCL/SPC]
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to Audio_SDA [CS43L22_SDA]
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to Audio_SCL [CS43L22_SCL]
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to CLK_IN [MP45DT02_CLK]
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to B1 [Blue PushButton]
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to B1 [Blue PushButton]
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to SPI1_SCK [LIS302DL_SCL/SPC]
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to SPI1_SCK [LIS302DL_SCL/SPC]
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to SPI1_MISO [LIS302DL_SDO]
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to SPI1_MISO [LIS302DL_SDO]
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to VBUS_FS
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to OTG_FS_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to OTG_FS_DM
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to Audio_SCL [CS43L22_SCL]
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to Audio_SDA [CS43L22_SDA]
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to Audio_SDA [CS43L22_SDA]
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to CLK_IN [MP45DT02_CLK]
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to I2S3_MCK [CS43L22_MCLK]
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to I2S3_MCK [CS43L22_MCLK]
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to LD4 [Green Led]
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD3 [Orange Led]
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to LD5 [Red Led]
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to LD6 [Blue Led]
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to B1 [Blue PushButton]
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to VBUS_FS
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to Audio_SCL [CS43L22_SCL]
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to CLK_IN [MP45DT02_CLK]
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to I2S3_SCK [CS43L22_SCLK]
+ {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to I2S3_SCK [CS43L22_SCLK]
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to I2S3_SD [CS43L22_SDIN]
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to OTG_FS_OverCurrent
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_ID
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to I2S3_MCK [CS43L22_MCLK]
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_DP
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to Audio_RST [CS43L22_RESET]
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD4 [Green Led]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B1 [Blue PushButton]
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_DM
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PDM_OUT [MP45DT02_DOUT]
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_SD [CS43L22_SDIN]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_MISO [LIS302DL_SDO]
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_SCK [LIS302DL_SCL/SPC]
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CLK_IN [MP45DT02_CLK]
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_SCK [CS43L22_SCLK]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to I2S3_WS [CS43L22_LRCK]
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_WS [CS43L22_LRCK]
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to Audio_SDA [CS43L22_SDA]
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to OTG_FS_DM
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to OTG_FS_DP
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to Audio_SCL [CS43L22_SCL]
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to Audio_SDA [CS43L22_SDA]
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,364 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_0_ALT0 = PA_0 | ALT0,
+ PA_0_ALT1 = PA_0 | ALT1,
+ PA_1 = 0x01,
+ PA_1_ALT0 = PA_1 | ALT0,
+ PA_1_ALT1 = PA_1 | ALT1,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_2_ALT1 = PA_2 | ALT1,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_3_ALT1 = PA_3 | ALT1,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_4_ALT1 = PB_4 | ALT1,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_5_ALT1 = PB_5 | ALT1,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_8_ALT1 = PB_8 | ALT1,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_9_ALT1 = PB_9 | ALT1,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_0_ALT0 = PC_0 | ALT0,
+ PC_0_ALT1 = PC_0 | ALT1,
+ PC_1 = 0x21,
+ PC_1_ALT0 = PC_1 | ALT0,
+ PC_1_ALT1 = PC_1 | ALT1,
+ PC_2 = 0x22,
+ PC_2_ALT0 = PC_2 | ALT0,
+ PC_2_ALT1 = PC_2 | ALT1,
+ PC_3 = 0x23,
+ PC_3_ALT0 = PC_3 | ALT0,
+ PC_3_ALT1 = PC_3 | ALT1,
+ PC_4 = 0x24,
+ PC_4_ALT0 = PC_4 | ALT0,
+ PC_5 = 0x25,
+ PC_5_ALT0 = PC_5 | ALT0,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_10_ALT0 = PC_10 | ALT0,
+ PC_11 = 0x2B,
+ PC_11_ALT0 = PC_11 | ALT0,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+ PH_2 = 0x72,
+ PH_3 = 0x73,
+ PH_4 = 0x74,
+ PH_5 = 0x75,
+ PH_6 = 0x76,
+ PH_7 = 0x77,
+ PH_8 = 0x78,
+ PH_9 = 0x79,
+ PH_10 = 0x7A,
+ PH_11 = 0x7B,
+ PH_12 = 0x7C,
+ PH_13 = 0x7D,
+ PH_14 = 0x7E,
+ PH_15 = 0x7F,
+
+ PI_0 = 0x80,
+ PI_1 = 0x81,
+ PI_2 = 0x82,
+ PI_3 = 0x83,
+ PI_4 = 0x84,
+ PI_5 = 0x85,
+ PI_6 = 0x86,
+ PI_7 = 0x87,
+ PI_8 = 0x88,
+ PI_9 = 0x89,
+ PI_10 = 0x8A,
+ PI_11 = 0x8B,
+ PI_12 = 0x8C,
+ PI_13 = 0x8D,
+ PI_14 = 0x8E,
+ PI_15 = 0x8F,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_2,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_3,
+#endif
+
+ // Generic signals namings
+ LED1 = PD_13, // LD3 as LD1 is not a user LED
+ LED2 = PD_12, // LD4 as LD2 is not a user LED
+ LED3 = PD_13, // orange
+ LED4 = PD_12, // green
+ LED5 = PD_14, // red
+ LED6 = PD_15, // blue
+ LED_RED = LED5,
+ USER_BUTTON = PA_0,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX, /* USART2 */
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX, /* USART2 */
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8, /* I2C1 */
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_HS_DM = PB_14,
+ USB_OTG_HS_DP = PB_15,
+ USB_OTG_HS_ID = PB_12,
+ USB_OTG_HS_SOF = PA_4,
+ USB_OTG_HS_ULPI_CK = PA_5,
+ USB_OTG_HS_ULPI_D0 = PA_3,
+ USB_OTG_HS_ULPI_D1 = PB_0,
+ USB_OTG_HS_ULPI_D2 = PB_1,
+ USB_OTG_HS_ULPI_D3 = PB_10,
+ USB_OTG_HS_ULPI_D4 = PB_11,
+ USB_OTG_HS_ULPI_D5 = PB_12,
+ USB_OTG_HS_ULPI_D6 = PB_13,
+ USB_OTG_HS_ULPI_D7 = PB_5,
+ USB_OTG_HS_ULPI_DIR = PC_2,
+ USB_OTG_HS_ULPI_NXT = PC_3,
+ USB_OTG_HS_ULPI_STP = PC_0,
+ USB_OTG_HS_VBUS = PB_13,
+
+ /**** ETHERNET pins ****/
+ ETH_COL = PA_3,
+ ETH_CRS = PA_0,
+ ETH_CRS_DV = PA_7,
+ ETH_MDC = PC_1,
+ ETH_MDIO = PA_2,
+ ETH_PPS_OUT = PB_5,
+ ETH_REF_CLK = PA_1,
+ ETH_RXD0 = PC_4,
+ ETH_RXD1 = PC_5,
+ ETH_RXD2 = PB_0,
+ ETH_RXD3 = PB_1,
+ ETH_RX_CLK = PA_1,
+ ETH_RX_DV = PA_7,
+ ETH_RX_ER = PB_10,
+ ETH_TXD0 = PB_12,
+ ETH_TXD1 = PB_13,
+ ETH_TXD2 = PC_2,
+ ETH_TXD3 = PE_2,
+ ETH_TXD3_ALT0 = PB_8,
+ ETH_TX_CLK = PC_3,
+ ETH_TX_EN = PB_11,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED3 = PE_6,
+ SYS_WKUP = PA_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,238 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 168
+ * AHBCLK (MHz) | 168
+ * APB1CLK (MHz) | 42
+ * APB2CLK (MHz) | 84
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz (SPI1 clock...)
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ /*
+ if (bypass == 0)
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+ else
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+ */
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,18 @@
+; *****************************************
+; *** Scatter-Loading Description File ***
+; *****************************************
+
+LR_IROM1 0x08000000 0x00100000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000188 0x0001FE78 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x10000000 0x00010000 { ; CCM
+ .ANY (CCMRAM)
+ }
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/startup_STM32F407xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/startup_STM32F407xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,415 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f407xx.s +;* Author : MCD Application Team +;* Description : STM32F407xx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + + ALIGN + END
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,18 @@
+; *****************************************
+; *** Scatter-Loading Description File ***
+; *****************************************
+
+LR_IROM1 0x08000000 0x00100000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000188 0x0001FE78 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x10000000 0x00010000 { ; CCM
+ .ANY (CCMRAM)
+ }
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/startup_STM32F407xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/startup_STM32F407xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,389 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f407xx.s +;* Author : MCD Application Team +;* Description : STM32F407xx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + + + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + + ALIGN + END
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,154 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 128k - 0x188
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f407xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f407xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,526 @@ +/** + ****************************************************************************** + * @file startup_stm32f407xx.s + * @author MCD Application Team + * @brief STM32F407xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/startup_stm32f407xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/startup_stm32f407xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,636 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f407xx.s +;* Author : MCD Application Team +;* Description : STM32F407xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and RNG + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,32 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000187;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000188;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x7000;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F407VG +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to ... +// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM + +#define NVIC_NUM_VECTORS 98 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,15555 @@
+/**
+ ******************************************************************************
+ * @file stm32f407xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f407xx
+ * @{
+ */
+
+#ifndef __STM32F407xx_H
+#define __STM32F407xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81 /*!< FPU global interrupt */
+} IRQn_Type;
+/* Legacy define */
+#define HASH_RNG_IRQn RNG_IRQn
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1;
+ __IO uint32_t MACDBGR;
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC123_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC123_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2_Pos (8U)
+#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos (9U)
+#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos (10U)
+#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos (11U)
+#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos (12U)
+#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos (13U)
+#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3_Pos (16U)
+#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos (17U)
+#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos (18U)
+#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos (19U)
+#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos (20U)
+#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos (21U)
+#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos (14U)
+#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos (15U)
+#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos (16U)
+#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos (17U)
+#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos (18U)
+#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos (19U)
+#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos (20U)
+#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos (21U)
+#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos (22U)
+#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos (23U)
+#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos (24U)
+#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos (25U)
+#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos (26U)
+#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos (27U)
+#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE_Pos (0U)
+#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos (1U)
+#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
+#define DCMI_CR_CM DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos (2U)
+#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos (3U)
+#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos (4U)
+#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos (5U)
+#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos (6U)
+#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos (7U)
+#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_CRE_Pos (12U)
+#define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
+#define DCMI_CR_CRE DCMI_CR_CRE_Msk
+#define DCMI_CR_ENABLE_Pos (14U)
+#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC_Pos (0U)
+#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos (1U)
+#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos (2U)
+#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS_Pos (0U)
+#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos (1U)
+#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos (2U)
+#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos (4U)
+#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE_Pos (0U)
+#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos (1U)
+#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos (2U)
+#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos (3U)
+#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos (4U)
+#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS_Pos (0U)
+#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos (1U)
+#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos (2U)
+#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos (4U)
+#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC_Pos (0U)
+#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos (1U)
+#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos (2U)
+#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos (4U)
+#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC_Pos (0U)
+#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos (8U)
+#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos (16U)
+#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos (24U)
+#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU_Pos (0U)
+#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos (8U)
+#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos (16U)
+#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos (24U)
+#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos (16U)
+#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos (16U)
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
+
+/******************** Bits definition for DCMI_DR register *********************/
+#define DCMI_DR_BYTE0_Pos (0U)
+#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos (8U)
+#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos (16U)
+#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos (24U)
+#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN_Pos (0U)
+#define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN_Pos (1U)
+#define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP_Pos (2U)
+#define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR1_MWID_Pos (4U)
+#define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR1_FACCEN_Pos (6U)
+#define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN_Pos (8U)
+#define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL_Pos (9U)
+#define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD_Pos (10U)
+#define FSMC_BCR1_WRAPMOD_Msk (0x1U << FSMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG_Pos (11U)
+#define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN_Pos (12U)
+#define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN_Pos (13U)
+#define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD_Pos (14U)
+#define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE_Pos (16U)
+#define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR1_CBURSTRW_Pos (19U)
+#define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN_Pos (0U)
+#define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN_Pos (1U)
+#define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP_Pos (2U)
+#define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR2_MWID_Pos (4U)
+#define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR2_FACCEN_Pos (6U)
+#define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN_Pos (8U)
+#define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL_Pos (9U)
+#define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD_Pos (10U)
+#define FSMC_BCR2_WRAPMOD_Msk (0x1U << FSMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG_Pos (11U)
+#define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN_Pos (12U)
+#define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN_Pos (13U)
+#define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD_Pos (14U)
+#define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR2_CPSIZE_Pos (16U)
+#define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR2_CBURSTRW_Pos (19U)
+#define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN_Pos (0U)
+#define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN_Pos (1U)
+#define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP_Pos (2U)
+#define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR3_MWID_Pos (4U)
+#define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR3_FACCEN_Pos (6U)
+#define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN_Pos (8U)
+#define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL_Pos (9U)
+#define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WRAPMOD_Pos (10U)
+#define FSMC_BCR3_WRAPMOD_Msk (0x1U << FSMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG_Pos (11U)
+#define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN_Pos (12U)
+#define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN_Pos (13U)
+#define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD_Pos (14U)
+#define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR3_CPSIZE_Pos (16U)
+#define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR3_CBURSTRW_Pos (19U)
+#define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN_Pos (0U)
+#define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN_Pos (1U)
+#define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP_Pos (2U)
+#define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR4_MWID_Pos (4U)
+#define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR4_FACCEN_Pos (6U)
+#define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN_Pos (8U)
+#define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL_Pos (9U)
+#define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD_Pos (10U)
+#define FSMC_BCR4_WRAPMOD_Msk (0x1U << FSMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG_Pos (11U)
+#define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN_Pos (12U)
+#define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN_Pos (13U)
+#define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD_Pos (14U)
+#define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR4_CPSIZE_Pos (16U)
+#define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR4_CBURSTRW_Pos (19U)
+#define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET_Pos (0U)
+#define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR1_ADDHLD_Pos (4U)
+#define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR1_DATAST_Pos (8U)
+#define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR1_BUSTURN_Pos (16U)
+#define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR1_CLKDIV_Pos (20U)
+#define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR1_DATLAT_Pos (24U)
+#define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR1_ACCMOD_Pos (28U)
+#define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET_Pos (0U)
+#define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR2_ADDHLD_Pos (4U)
+#define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR2_DATAST_Pos (8U)
+#define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR2_BUSTURN_Pos (16U)
+#define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR2_CLKDIV_Pos (20U)
+#define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR2_DATLAT_Pos (24U)
+#define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR2_ACCMOD_Pos (28U)
+#define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET_Pos (0U)
+#define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR3_ADDHLD_Pos (4U)
+#define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR3_DATAST_Pos (8U)
+#define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR3_BUSTURN_Pos (16U)
+#define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR3_CLKDIV_Pos (20U)
+#define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR3_DATLAT_Pos (24U)
+#define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR3_ACCMOD_Pos (28U)
+#define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET_Pos (0U)
+#define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR4_ADDHLD_Pos (4U)
+#define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR4_DATAST_Pos (8U)
+#define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR4_BUSTURN_Pos (16U)
+#define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR4_CLKDIV_Pos (20U)
+#define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR4_DATLAT_Pos (24U)
+#define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR4_ACCMOD_Pos (28U)
+#define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET_Pos (0U)
+#define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR1_ADDHLD_Pos (4U)
+#define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR1_DATAST_Pos (8U)
+#define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR1_BUSTURN_Pos (16U)
+#define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR1_ACCMOD_Pos (28U)
+#define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET_Pos (0U)
+#define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR2_ADDHLD_Pos (4U)
+#define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR2_DATAST_Pos (8U)
+#define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR2_BUSTURN_Pos (16U)
+#define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR2_ACCMOD_Pos (28U)
+#define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET_Pos (0U)
+#define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR3_ADDHLD_Pos (4U)
+#define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR3_DATAST_Pos (8U)
+#define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR3_BUSTURN_Pos (16U)
+#define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR3_ACCMOD_Pos (28U)
+#define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET_Pos (0U)
+#define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR4_ADDHLD_Pos (4U)
+#define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR4_DATAST_Pos (8U)
+#define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN_Pos (16U)
+#define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR4_ACCMOD_Pos (28U)
+#define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN_Pos (1U)
+#define FSMC_PCR2_PWAITEN_Msk (0x1U << FSMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FSMC_PCR2_PBKEN_Pos (2U)
+#define FSMC_PCR2_PBKEN_Msk (0x1U << FSMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP_Pos (3U)
+#define FSMC_PCR2_PTYP_Msk (0x1U << FSMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk /*!<Memory type */
+
+#define FSMC_PCR2_PWID_Pos (4U)
+#define FSMC_PCR2_PWID_Msk (0x3U << FSMC_PCR2_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 (0x1U << FSMC_PCR2_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCR2_PWID_1 (0x2U << FSMC_PCR2_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCR2_ECCEN_Pos (6U)
+#define FSMC_PCR2_ECCEN_Msk (0x1U << FSMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR_Pos (9U)
+#define FSMC_PCR2_TCLR_Msk (0xFU << FSMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 (0x1U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCR2_TCLR_1 (0x2U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCR2_TCLR_2 (0x4U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCR2_TCLR_3 (0x8U << FSMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCR2_TAR_Pos (13U)
+#define FSMC_PCR2_TAR_Msk (0xFU << FSMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 (0x1U << FSMC_PCR2_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCR2_TAR_1 (0x2U << FSMC_PCR2_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCR2_TAR_2 (0x4U << FSMC_PCR2_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCR2_TAR_3 (0x8U << FSMC_PCR2_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCR2_ECCPS_Pos (17U)
+#define FSMC_PCR2_ECCPS_Msk (0x7U << FSMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 (0x1U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCR2_ECCPS_1 (0x2U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCR2_ECCPS_2 (0x4U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN_Pos (1U)
+#define FSMC_PCR3_PWAITEN_Msk (0x1U << FSMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FSMC_PCR3_PBKEN_Pos (2U)
+#define FSMC_PCR3_PBKEN_Msk (0x1U << FSMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP_Pos (3U)
+#define FSMC_PCR3_PTYP_Msk (0x1U << FSMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk /*!<Memory type */
+
+#define FSMC_PCR3_PWID_Pos (4U)
+#define FSMC_PCR3_PWID_Msk (0x3U << FSMC_PCR3_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 (0x1U << FSMC_PCR3_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCR3_PWID_1 (0x2U << FSMC_PCR3_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCR3_ECCEN_Pos (6U)
+#define FSMC_PCR3_ECCEN_Msk (0x1U << FSMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR_Pos (9U)
+#define FSMC_PCR3_TCLR_Msk (0xFU << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 (0x1U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCR3_TCLR_1 (0x2U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCR3_TCLR_2 (0x4U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCR3_TCLR_3 (0x8U << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCR3_TAR_Pos (13U)
+#define FSMC_PCR3_TAR_Msk (0xFU << FSMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 (0x1U << FSMC_PCR3_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCR3_TAR_1 (0x2U << FSMC_PCR3_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCR3_TAR_2 (0x4U << FSMC_PCR3_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCR3_TAR_3 (0x8U << FSMC_PCR3_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCR3_ECCPS_Pos (17U)
+#define FSMC_PCR3_ECCPS_Msk (0x7U << FSMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 (0x1U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCR3_ECCPS_1 (0x2U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCR3_ECCPS_2 (0x4U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN_Pos (1U)
+#define FSMC_PCR4_PWAITEN_Msk (0x1U << FSMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FSMC_PCR4_PBKEN_Pos (2U)
+#define FSMC_PCR4_PBKEN_Msk (0x1U << FSMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP_Pos (3U)
+#define FSMC_PCR4_PTYP_Msk (0x1U << FSMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk /*!<Memory type */
+
+#define FSMC_PCR4_PWID_Pos (4U)
+#define FSMC_PCR4_PWID_Msk (0x3U << FSMC_PCR4_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 (0x1U << FSMC_PCR4_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCR4_PWID_1 (0x2U << FSMC_PCR4_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCR4_ECCEN_Pos (6U)
+#define FSMC_PCR4_ECCEN_Msk (0x1U << FSMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR_Pos (9U)
+#define FSMC_PCR4_TCLR_Msk (0xFU << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 (0x1U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCR4_TCLR_1 (0x2U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCR4_TCLR_2 (0x4U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCR4_TCLR_3 (0x8U << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCR4_TAR_Pos (13U)
+#define FSMC_PCR4_TAR_Msk (0xFU << FSMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 (0x1U << FSMC_PCR4_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCR4_TAR_1 (0x2U << FSMC_PCR4_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCR4_TAR_2 (0x4U << FSMC_PCR4_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCR4_TAR_3 (0x8U << FSMC_PCR4_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCR4_ECCPS_Pos (17U)
+#define FSMC_PCR4_ECCPS_Msk (0x7U << FSMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 (0x1U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCR4_ECCPS_1 (0x2U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCR4_ECCPS_2 (0x4U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS_Pos (0U)
+#define FSMC_SR2_IRS_Msk (0x1U << FSMC_SR2_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SR2_IRS FSMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FSMC_SR2_ILS_Pos (1U)
+#define FSMC_SR2_ILS_Msk (0x1U << FSMC_SR2_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SR2_ILS FSMC_SR2_ILS_Msk /*!<Interrupt Level status */
+#define FSMC_SR2_IFS_Pos (2U)
+#define FSMC_SR2_IFS_Msk (0x1U << FSMC_SR2_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SR2_IFS FSMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FSMC_SR2_IREN_Pos (3U)
+#define FSMC_SR2_IREN_Msk (0x1U << FSMC_SR2_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SR2_IREN FSMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN_Pos (4U)
+#define FSMC_SR2_ILEN_Msk (0x1U << FSMC_SR2_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN_Pos (5U)
+#define FSMC_SR2_IFEN_Msk (0x1U << FSMC_SR2_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT_Pos (6U)
+#define FSMC_SR2_FEMPT_Msk (0x1U << FSMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS_Pos (0U)
+#define FSMC_SR3_IRS_Msk (0x1U << FSMC_SR3_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SR3_IRS FSMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FSMC_SR3_ILS_Pos (1U)
+#define FSMC_SR3_ILS_Msk (0x1U << FSMC_SR3_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SR3_ILS FSMC_SR3_ILS_Msk /*!<Interrupt Level status */
+#define FSMC_SR3_IFS_Pos (2U)
+#define FSMC_SR3_IFS_Msk (0x1U << FSMC_SR3_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SR3_IFS FSMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FSMC_SR3_IREN_Pos (3U)
+#define FSMC_SR3_IREN_Msk (0x1U << FSMC_SR3_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SR3_IREN FSMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN_Pos (4U)
+#define FSMC_SR3_ILEN_Msk (0x1U << FSMC_SR3_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN_Pos (5U)
+#define FSMC_SR3_IFEN_Msk (0x1U << FSMC_SR3_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT_Pos (6U)
+#define FSMC_SR3_FEMPT_Msk (0x1U << FSMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS_Pos (0U)
+#define FSMC_SR4_IRS_Msk (0x1U << FSMC_SR4_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SR4_IRS FSMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FSMC_SR4_ILS_Pos (1U)
+#define FSMC_SR4_ILS_Msk (0x1U << FSMC_SR4_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SR4_ILS FSMC_SR4_ILS_Msk /*!<Interrupt Level status */
+#define FSMC_SR4_IFS_Pos (2U)
+#define FSMC_SR4_IFS_Msk (0x1U << FSMC_SR4_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SR4_IFS FSMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FSMC_SR4_IREN_Pos (3U)
+#define FSMC_SR4_IREN_Msk (0x1U << FSMC_SR4_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SR4_IREN FSMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN_Pos (4U)
+#define FSMC_SR4_ILEN_Msk (0x1U << FSMC_SR4_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN_Pos (5U)
+#define FSMC_SR4_IFEN_Msk (0x1U << FSMC_SR4_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT_Pos (6U)
+#define FSMC_SR4_FEMPT_Msk (0x1U << FSMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk /*!<FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2_Pos (0U)
+#define FSMC_PMEM2_MEMSET2_Msk (0xFFU << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
+#define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 (0x01U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
+#define FSMC_PMEM2_MEMSET2_1 (0x02U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
+#define FSMC_PMEM2_MEMSET2_2 (0x04U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
+#define FSMC_PMEM2_MEMSET2_3 (0x08U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
+#define FSMC_PMEM2_MEMSET2_4 (0x10U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
+#define FSMC_PMEM2_MEMSET2_5 (0x20U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
+#define FSMC_PMEM2_MEMSET2_6 (0x40U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
+#define FSMC_PMEM2_MEMSET2_7 (0x80U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEM2_MEMWAIT2_Pos (8U)
+#define FSMC_PMEM2_MEMWAIT2_Msk (0xFFU << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 (0x01U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
+#define FSMC_PMEM2_MEMWAIT2_1 (0x02U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
+#define FSMC_PMEM2_MEMWAIT2_2 (0x04U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
+#define FSMC_PMEM2_MEMWAIT2_3 (0x08U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
+#define FSMC_PMEM2_MEMWAIT2_4 (0x10U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
+#define FSMC_PMEM2_MEMWAIT2_5 (0x20U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
+#define FSMC_PMEM2_MEMWAIT2_6 (0x40U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
+#define FSMC_PMEM2_MEMWAIT2_7 (0x80U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
+
+#define FSMC_PMEM2_MEMHOLD2_Pos (16U)
+#define FSMC_PMEM2_MEMHOLD2_Msk (0xFFU << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 (0x01U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
+#define FSMC_PMEM2_MEMHOLD2_1 (0x02U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
+#define FSMC_PMEM2_MEMHOLD2_2 (0x04U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
+#define FSMC_PMEM2_MEMHOLD2_3 (0x08U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
+#define FSMC_PMEM2_MEMHOLD2_4 (0x10U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
+#define FSMC_PMEM2_MEMHOLD2_5 (0x20U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
+#define FSMC_PMEM2_MEMHOLD2_6 (0x40U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
+#define FSMC_PMEM2_MEMHOLD2_7 (0x80U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEM2_MEMHIZ2_Pos (24U)
+#define FSMC_PMEM2_MEMHIZ2_Msk (0xFFU << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 (0x01U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
+#define FSMC_PMEM2_MEMHIZ2_1 (0x02U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
+#define FSMC_PMEM2_MEMHIZ2_2 (0x04U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
+#define FSMC_PMEM2_MEMHIZ2_3 (0x08U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
+#define FSMC_PMEM2_MEMHIZ2_4 (0x10U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
+#define FSMC_PMEM2_MEMHIZ2_5 (0x20U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
+#define FSMC_PMEM2_MEMHIZ2_6 (0x40U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
+#define FSMC_PMEM2_MEMHIZ2_7 (0x80U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3_Pos (0U)
+#define FSMC_PMEM3_MEMSET3_Msk (0xFFU << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
+#define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 (0x01U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
+#define FSMC_PMEM3_MEMSET3_1 (0x02U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
+#define FSMC_PMEM3_MEMSET3_2 (0x04U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
+#define FSMC_PMEM3_MEMSET3_3 (0x08U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
+#define FSMC_PMEM3_MEMSET3_4 (0x10U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
+#define FSMC_PMEM3_MEMSET3_5 (0x20U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
+#define FSMC_PMEM3_MEMSET3_6 (0x40U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
+#define FSMC_PMEM3_MEMSET3_7 (0x80U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEM3_MEMWAIT3_Pos (8U)
+#define FSMC_PMEM3_MEMWAIT3_Msk (0xFFU << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 (0x01U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
+#define FSMC_PMEM3_MEMWAIT3_1 (0x02U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
+#define FSMC_PMEM3_MEMWAIT3_2 (0x04U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
+#define FSMC_PMEM3_MEMWAIT3_3 (0x08U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
+#define FSMC_PMEM3_MEMWAIT3_4 (0x10U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
+#define FSMC_PMEM3_MEMWAIT3_5 (0x20U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
+#define FSMC_PMEM3_MEMWAIT3_6 (0x40U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
+#define FSMC_PMEM3_MEMWAIT3_7 (0x80U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
+
+#define FSMC_PMEM3_MEMHOLD3_Pos (16U)
+#define FSMC_PMEM3_MEMHOLD3_Msk (0xFFU << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 (0x01U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
+#define FSMC_PMEM3_MEMHOLD3_1 (0x02U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
+#define FSMC_PMEM3_MEMHOLD3_2 (0x04U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
+#define FSMC_PMEM3_MEMHOLD3_3 (0x08U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
+#define FSMC_PMEM3_MEMHOLD3_4 (0x10U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
+#define FSMC_PMEM3_MEMHOLD3_5 (0x20U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
+#define FSMC_PMEM3_MEMHOLD3_6 (0x40U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
+#define FSMC_PMEM3_MEMHOLD3_7 (0x80U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEM3_MEMHIZ3_Pos (24U)
+#define FSMC_PMEM3_MEMHIZ3_Msk (0xFFU << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 (0x01U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
+#define FSMC_PMEM3_MEMHIZ3_1 (0x02U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
+#define FSMC_PMEM3_MEMHIZ3_2 (0x04U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
+#define FSMC_PMEM3_MEMHIZ3_3 (0x08U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
+#define FSMC_PMEM3_MEMHIZ3_4 (0x10U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
+#define FSMC_PMEM3_MEMHIZ3_5 (0x20U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
+#define FSMC_PMEM3_MEMHIZ3_6 (0x40U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
+#define FSMC_PMEM3_MEMHIZ3_7 (0x80U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4_Pos (0U)
+#define FSMC_PMEM4_MEMSET4_Msk (0xFFU << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 (0x01U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PMEM4_MEMSET4_1 (0x02U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PMEM4_MEMSET4_2 (0x04U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PMEM4_MEMSET4_3 (0x08U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PMEM4_MEMSET4_4 (0x10U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PMEM4_MEMSET4_5 (0x20U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PMEM4_MEMSET4_6 (0x40U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PMEM4_MEMSET4_7 (0x80U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEM4_MEMWAIT4_Pos (8U)
+#define FSMC_PMEM4_MEMWAIT4_Msk (0xFFU << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 (0x01U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PMEM4_MEMWAIT4_1 (0x02U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PMEM4_MEMWAIT4_2 (0x04U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PMEM4_MEMWAIT4_3 (0x08U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PMEM4_MEMWAIT4_4 (0x10U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PMEM4_MEMWAIT4_5 (0x20U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PMEM4_MEMWAIT4_6 (0x40U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PMEM4_MEMWAIT4_7 (0x80U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PMEM4_MEMHOLD4_Pos (16U)
+#define FSMC_PMEM4_MEMHOLD4_Msk (0xFFU << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 (0x01U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PMEM4_MEMHOLD4_1 (0x02U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PMEM4_MEMHOLD4_2 (0x04U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PMEM4_MEMHOLD4_3 (0x08U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PMEM4_MEMHOLD4_4 (0x10U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PMEM4_MEMHOLD4_5 (0x20U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PMEM4_MEMHOLD4_6 (0x40U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PMEM4_MEMHOLD4_7 (0x80U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEM4_MEMHIZ4_Pos (24U)
+#define FSMC_PMEM4_MEMHIZ4_Msk (0xFFU << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 (0x01U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PMEM4_MEMHIZ4_1 (0x02U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PMEM4_MEMHIZ4_2 (0x04U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PMEM4_MEMHIZ4_3 (0x08U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PMEM4_MEMHIZ4_4 (0x10U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PMEM4_MEMHIZ4_5 (0x20U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PMEM4_MEMHIZ4_6 (0x40U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PMEM4_MEMHIZ4_7 (0x80U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2_Pos (0U)
+#define FSMC_PATT2_ATTSET2_Msk (0xFFU << FSMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
+#define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 (0x01U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
+#define FSMC_PATT2_ATTSET2_1 (0x02U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
+#define FSMC_PATT2_ATTSET2_2 (0x04U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
+#define FSMC_PATT2_ATTSET2_3 (0x08U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
+#define FSMC_PATT2_ATTSET2_4 (0x10U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
+#define FSMC_PATT2_ATTSET2_5 (0x20U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
+#define FSMC_PATT2_ATTSET2_6 (0x40U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
+#define FSMC_PATT2_ATTSET2_7 (0x80U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATT2_ATTWAIT2_Pos (8U)
+#define FSMC_PATT2_ATTWAIT2_Msk (0xFFU << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 (0x01U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
+#define FSMC_PATT2_ATTWAIT2_1 (0x02U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
+#define FSMC_PATT2_ATTWAIT2_2 (0x04U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
+#define FSMC_PATT2_ATTWAIT2_3 (0x08U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
+#define FSMC_PATT2_ATTWAIT2_4 (0x10U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
+#define FSMC_PATT2_ATTWAIT2_5 (0x20U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
+#define FSMC_PATT2_ATTWAIT2_6 (0x40U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
+#define FSMC_PATT2_ATTWAIT2_7 (0x80U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATT2_ATTHOLD2_Pos (16U)
+#define FSMC_PATT2_ATTHOLD2_Msk (0xFFU << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 (0x01U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
+#define FSMC_PATT2_ATTHOLD2_1 (0x02U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
+#define FSMC_PATT2_ATTHOLD2_2 (0x04U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
+#define FSMC_PATT2_ATTHOLD2_3 (0x08U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
+#define FSMC_PATT2_ATTHOLD2_4 (0x10U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
+#define FSMC_PATT2_ATTHOLD2_5 (0x20U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
+#define FSMC_PATT2_ATTHOLD2_6 (0x40U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
+#define FSMC_PATT2_ATTHOLD2_7 (0x80U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATT2_ATTHIZ2_Pos (24U)
+#define FSMC_PATT2_ATTHIZ2_Msk (0xFFU << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
+#define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 (0x01U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
+#define FSMC_PATT2_ATTHIZ2_1 (0x02U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
+#define FSMC_PATT2_ATTHIZ2_2 (0x04U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
+#define FSMC_PATT2_ATTHIZ2_3 (0x08U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
+#define FSMC_PATT2_ATTHIZ2_4 (0x10U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
+#define FSMC_PATT2_ATTHIZ2_5 (0x20U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
+#define FSMC_PATT2_ATTHIZ2_6 (0x40U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
+#define FSMC_PATT2_ATTHIZ2_7 (0x80U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3_Pos (0U)
+#define FSMC_PATT3_ATTSET3_Msk (0xFFU << FSMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
+#define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 (0x01U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
+#define FSMC_PATT3_ATTSET3_1 (0x02U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
+#define FSMC_PATT3_ATTSET3_2 (0x04U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
+#define FSMC_PATT3_ATTSET3_3 (0x08U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
+#define FSMC_PATT3_ATTSET3_4 (0x10U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
+#define FSMC_PATT3_ATTSET3_5 (0x20U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
+#define FSMC_PATT3_ATTSET3_6 (0x40U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
+#define FSMC_PATT3_ATTSET3_7 (0x80U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATT3_ATTWAIT3_Pos (8U)
+#define FSMC_PATT3_ATTWAIT3_Msk (0xFFU << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 (0x01U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
+#define FSMC_PATT3_ATTWAIT3_1 (0x02U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
+#define FSMC_PATT3_ATTWAIT3_2 (0x04U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
+#define FSMC_PATT3_ATTWAIT3_3 (0x08U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
+#define FSMC_PATT3_ATTWAIT3_4 (0x10U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
+#define FSMC_PATT3_ATTWAIT3_5 (0x20U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
+#define FSMC_PATT3_ATTWAIT3_6 (0x40U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
+#define FSMC_PATT3_ATTWAIT3_7 (0x80U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATT3_ATTHOLD3_Pos (16U)
+#define FSMC_PATT3_ATTHOLD3_Msk (0xFFU << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 (0x01U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
+#define FSMC_PATT3_ATTHOLD3_1 (0x02U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
+#define FSMC_PATT3_ATTHOLD3_2 (0x04U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
+#define FSMC_PATT3_ATTHOLD3_3 (0x08U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
+#define FSMC_PATT3_ATTHOLD3_4 (0x10U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
+#define FSMC_PATT3_ATTHOLD3_5 (0x20U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
+#define FSMC_PATT3_ATTHOLD3_6 (0x40U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
+#define FSMC_PATT3_ATTHOLD3_7 (0x80U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATT3_ATTHIZ3_Pos (24U)
+#define FSMC_PATT3_ATTHIZ3_Msk (0xFFU << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
+#define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 (0x01U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
+#define FSMC_PATT3_ATTHIZ3_1 (0x02U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
+#define FSMC_PATT3_ATTHIZ3_2 (0x04U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
+#define FSMC_PATT3_ATTHIZ3_3 (0x08U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
+#define FSMC_PATT3_ATTHIZ3_4 (0x10U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
+#define FSMC_PATT3_ATTHIZ3_5 (0x20U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
+#define FSMC_PATT3_ATTHIZ3_6 (0x40U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
+#define FSMC_PATT3_ATTHIZ3_7 (0x80U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4_Pos (0U)
+#define FSMC_PATT4_ATTSET4_Msk (0xFFU << FSMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 (0x01U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PATT4_ATTSET4_1 (0x02U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PATT4_ATTSET4_2 (0x04U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PATT4_ATTSET4_3 (0x08U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PATT4_ATTSET4_4 (0x10U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PATT4_ATTSET4_5 (0x20U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PATT4_ATTSET4_6 (0x40U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PATT4_ATTSET4_7 (0x80U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATT4_ATTWAIT4_Pos (8U)
+#define FSMC_PATT4_ATTWAIT4_Msk (0xFFU << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 (0x01U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PATT4_ATTWAIT4_1 (0x02U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PATT4_ATTWAIT4_2 (0x04U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PATT4_ATTWAIT4_3 (0x08U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PATT4_ATTWAIT4_4 (0x10U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PATT4_ATTWAIT4_5 (0x20U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PATT4_ATTWAIT4_6 (0x40U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PATT4_ATTWAIT4_7 (0x80U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATT4_ATTHOLD4_Pos (16U)
+#define FSMC_PATT4_ATTHOLD4_Msk (0xFFU << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 (0x01U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PATT4_ATTHOLD4_1 (0x02U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PATT4_ATTHOLD4_2 (0x04U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PATT4_ATTHOLD4_3 (0x08U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PATT4_ATTHOLD4_4 (0x10U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PATT4_ATTHOLD4_5 (0x20U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PATT4_ATTHOLD4_6 (0x40U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PATT4_ATTHOLD4_7 (0x80U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATT4_ATTHIZ4_Pos (24U)
+#define FSMC_PATT4_ATTHIZ4_Msk (0xFFU << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 (0x01U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PATT4_ATTHIZ4_1 (0x02U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PATT4_ATTHIZ4_2 (0x04U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PATT4_ATTHIZ4_3 (0x08U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PATT4_ATTHIZ4_4 (0x10U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PATT4_ATTHIZ4_5 (0x20U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PATT4_ATTHIZ4_6 (0x40U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PATT4_ATTHIZ4_7 (0x80U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4_Pos (0U)
+#define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PIO4_IOWAIT4_Pos (8U)
+#define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PIO4_IOHOLD4_Pos (16U)
+#define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PIO4_IOHIZ4_Pos (24U)
+#define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2_Pos (0U)
+#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!<ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3_Pos (0U)
+#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x1U << PWR_CR_VOS_Pos) /*!< 0x00004000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS bit (Regulator voltage scaling output selection) */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
+#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
+#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
+#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
+#define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
+#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
+#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
+#define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
+#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
+#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
+#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
+#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
+#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
+#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
+#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_DCMIEN_Pos (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos (6U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FSMCEN_Pos (0U)
+#define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (1U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_ADC2EN_Pos (9U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
+#define RCC_APB2ENR_ADC3EN_Pos (10U)
+#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
+#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
+#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
+#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
+#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
+#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD_Pos (23U)
+#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
+#define ETH_MACCR_JD_Pos (22U)
+#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
+#define ETH_MACCR_IFG_Pos (17U)
+#define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
+#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD_Pos (16U)
+#define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES_Pos (14U)
+#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
+#define ETH_MACCR_ROD_Pos (13U)
+#define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
+#define ETH_MACCR_LM_Pos (12U)
+#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
+#define ETH_MACCR_DM_Pos (11U)
+#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
+#define ETH_MACCR_IPCO_Pos (10U)
+#define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
+#define ETH_MACCR_RD_Pos (9U)
+#define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
+#define ETH_MACCR_APCS_Pos (7U)
+#define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
+#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL_Pos (5U)
+#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC_Pos (4U)
+#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
+#define ETH_MACCR_TE_Pos (3U)
+#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
+#define ETH_MACCR_RE_Pos (2U)
+#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA_Pos (31U)
+#define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
+#define ETH_MACFFR_HPF_Pos (10U)
+#define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
+#define ETH_MACFFR_SAF_Pos (9U)
+#define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
+#define ETH_MACFFR_SAIF_Pos (8U)
+#define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
+#define ETH_MACFFR_PCF_Pos (6U)
+#define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
+#define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
+#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
+#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
+#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD_Pos (5U)
+#define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
+#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
+#define ETH_MACFFR_PAM_Pos (4U)
+#define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
+#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF_Pos (3U)
+#define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
+#define ETH_MACFFR_HM_Pos (2U)
+#define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
+#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
+#define ETH_MACFFR_HU_Pos (1U)
+#define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
+#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
+#define ETH_MACFFR_PM_Pos (0U)
+#define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
+#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos (0U)
+#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos (0U)
+#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA_Pos (11U)
+#define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
+#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
+#define ETH_MACMIIAR_MR_Pos (6U)
+#define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
+#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR_Pos (2U)
+#define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
+#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
+#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIAR_CR_Div62_Pos (2U)
+#define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
+#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define ETH_MACMIIAR_CR_Div16_Pos (3U)
+#define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
+#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ETH_MACMIIAR_CR_Div26_Pos (2U)
+#define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
+#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_CR_Div102_Pos (4U)
+#define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
+#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW_Pos (1U)
+#define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
+#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
+#define ETH_MACMIIAR_MB_Pos (0U)
+#define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD_Pos (0U)
+#define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT_Pos (16U)
+#define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
+#define ETH_MACFCR_ZQPD_Pos (7U)
+#define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
+#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT_Pos (4U)
+#define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+#define ETH_MACFCR_PLT_Minus28_Pos (4U)
+#define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
+#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACFCR_PLT_Minus144_Pos (5U)
+#define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
+#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256_Pos (4U)
+#define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD_Pos (3U)
+#define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
+#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE_Pos (2U)
+#define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
+#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
+#define ETH_MACFCR_TFCE_Pos (1U)
+#define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
+#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA_Pos (0U)
+#define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
+#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC_Pos (16U)
+#define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
+#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI_Pos (0U)
+#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D_Pos (0U)
+#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
+#define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
+#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU_Pos (9U)
+#define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
+#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
+#define ETH_MACPMTCSR_WFR_Pos (6U)
+#define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
+#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR_Pos (5U)
+#define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
+#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE_Pos (2U)
+#define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
+#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE_Pos (1U)
+#define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
+#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD_Pos (0U)
+#define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
+#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
+
+/* Bit definition for Ethernet MAC debug Register */
+#define ETH_MACDBGR_TFF_Pos (25U)
+#define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
+#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
+#define ETH_MACDBGR_TFNE_Pos (24U)
+#define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
+#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
+#define ETH_MACDBGR_TFWA_Pos (22U)
+#define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
+#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
+#define ETH_MACDBGR_TFRS_Pos (20U)
+#define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
+#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
+#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
+#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
+#define ETH_MACDBGR_TFRS_READ_Pos (20U)
+#define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
+#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
+#define ETH_MACDBGR_MTP_Pos (19U)
+#define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
+#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
+#define ETH_MACDBGR_MTFCS_Pos (17U)
+#define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
+#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
+#define ETH_MACDBGR_MMTEA_Pos (16U)
+#define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
+#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
+#define ETH_MACDBGR_RFFL_Pos (8U)
+#define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
+#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
+#define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
+#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
+#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
+#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
+#define ETH_MACDBGR_RFRCS_Pos (5U)
+#define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
+#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
+#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
+#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
+#define ETH_MACDBGR_RFWRA_Pos (4U)
+#define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
+#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
+#define ETH_MACDBGR_MSFRWCS_Pos (1U)
+#define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
+#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
+#define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
+#define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
+#define ETH_MACDBGR_MMRPEA_Pos (0U)
+#define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
+#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS_Pos (9U)
+#define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
+#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS_Pos (6U)
+#define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
+#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
+#define ETH_MACSR_MMMCRS_Pos (5U)
+#define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
+#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
+#define ETH_MACSR_MMCS_Pos (4U)
+#define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
+#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
+#define ETH_MACSR_PMTS_Pos (3U)
+#define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
+#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM_Pos (9U)
+#define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
+#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM_Pos (3U)
+#define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
+#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H_Pos (0U)
+#define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L_Pos (0U)
+#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE_Pos (31U)
+#define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
+#define ETH_MACA1HR_SA_Pos (30U)
+#define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
+#define ETH_MACA1HR_MBC_Pos (24U)
+#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H_Pos (0U)
+#define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L_Pos (0U)
+#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE_Pos (31U)
+#define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
+#define ETH_MACA2HR_SA_Pos (30U)
+#define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
+#define ETH_MACA2HR_MBC_Pos (24U)
+#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H_Pos (0U)
+#define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L_Pos (0U)
+#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE_Pos (31U)
+#define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
+#define ETH_MACA3HR_SA_Pos (30U)
+#define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
+#define ETH_MACA3HR_MBC_Pos (24U)
+#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H_Pos (0U)
+#define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L_Pos (0U)
+#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP_Pos (5U)
+#define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP_Pos (4U)
+#define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
+#define ETH_MMCCR_MCF_Pos (3U)
+#define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR_Pos (2U)
+#define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
+#define ETH_MMCCR_CSR_Pos (1U)
+#define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
+#define ETH_MMCCR_CR_Pos (0U)
+#define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS_Pos (17U)
+#define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES_Pos (6U)
+#define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES_Pos (5U)
+#define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS_Pos (21U)
+#define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS_Pos (15U)
+#define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS_Pos (14U)
+#define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM_Pos (17U)
+#define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM_Pos (6U)
+#define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM_Pos (5U)
+#define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM_Pos (21U)
+#define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
+#define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM_Pos (14U)
+#define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
+#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC_Pos (0U)
+#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC_Pos (0U)
+#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC_Pos (0U)
+#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
+#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT_Pos (16U)
+#define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
+#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME_Pos (15U)
+#define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME_Pos (14U)
+#define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
+#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
+#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
+#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
+#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
+#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
+#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
+#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
+#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
+#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR_Pos (9U)
+#define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
+#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE_Pos (8U)
+#define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
+#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU_Pos (5U)
+#define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
+#define ETH_PTPTSCR_TSITE_Pos (4U)
+#define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU_Pos (3U)
+#define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
+#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI_Pos (2U)
+#define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
+#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU_Pos (1U)
+#define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
+#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE_Pos (0U)
+#define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
+#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI_Pos (0U)
+#define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
+#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS_Pos (0U)
+#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS_Pos (31U)
+#define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS_Pos (0U)
+#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS_Pos (0U)
+#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
+#define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS_Pos (0U)
+#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA_Pos (0U)
+#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH_Pos (0U)
+#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL_Pos (0U)
+#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR_Pos (5U)
+#define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO_Pos (4U)
+#define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB_Pos (25U)
+#define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
+#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
+#define ETH_DMABMR_FPM_Pos (24U)
+#define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
+#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
+#define ETH_DMABMR_USP_Pos (23U)
+#define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
+#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
+#define ETH_DMABMR_RDP_Pos (17U)
+#define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
+#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
+#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB_Pos (16U)
+#define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
+#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
+#define ETH_DMABMR_RTPR_Pos (14U)
+#define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
+#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL_Pos (8U)
+#define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
+#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
+#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE_Pos (7U)
+#define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
+#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL_Pos (2U)
+#define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
+#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
+#define ETH_DMABMR_DA_Pos (1U)
+#define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
+#define ETH_DMABMR_SR_Pos (0U)
+#define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD_Pos (0U)
+#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD_Pos (0U)
+#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL_Pos (0U)
+#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL_Pos (0U)
+#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS_Pos (29U)
+#define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
+#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS_Pos (28U)
+#define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
+#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
+#define ETH_DMASR_MMCS_Pos (27U)
+#define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
+#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
+#define ETH_DMASR_EBS_Pos (23U)
+#define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
+#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+#define ETH_DMASR_EBS_DescAccess_Pos (25U)
+#define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
+#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
+#define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
+#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
+#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
+#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS_Pos (20U)
+#define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
+#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMASR_TPS_Fetching_Pos (20U)
+#define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
+#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
+#define ETH_DMASR_TPS_Waiting_Pos (21U)
+#define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
+#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
+#define ETH_DMASR_TPS_Reading_Pos (20U)
+#define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
+#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
+#define ETH_DMASR_TPS_Suspended_Pos (21U)
+#define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
+#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
+#define ETH_DMASR_TPS_Closing_Pos (20U)
+#define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS_Pos (17U)
+#define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
+#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Fetching_Pos (17U)
+#define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
+#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
+#define ETH_DMASR_RPS_Waiting_Pos (17U)
+#define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
+#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
+#define ETH_DMASR_RPS_Suspended_Pos (19U)
+#define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
+#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
+#define ETH_DMASR_RPS_Closing_Pos (17U)
+#define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
+#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
+#define ETH_DMASR_RPS_Queuing_Pos (17U)
+#define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS_Pos (16U)
+#define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
+#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
+#define ETH_DMASR_AIS_Pos (15U)
+#define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
+#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS_Pos (14U)
+#define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
+#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
+#define ETH_DMASR_FBES_Pos (13U)
+#define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
+#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
+#define ETH_DMASR_ETS_Pos (10U)
+#define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
+#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
+#define ETH_DMASR_RWTS_Pos (9U)
+#define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
+#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS_Pos (8U)
+#define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
+#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
+#define ETH_DMASR_RBUS_Pos (7U)
+#define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
+#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
+#define ETH_DMASR_RS_Pos (6U)
+#define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
+#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
+#define ETH_DMASR_TUS_Pos (5U)
+#define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
+#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
+#define ETH_DMASR_ROS_Pos (4U)
+#define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
+#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
+#define ETH_DMASR_TJTS_Pos (3U)
+#define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
+#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS_Pos (2U)
+#define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
+#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS_Pos (1U)
+#define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
+#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
+#define ETH_DMASR_TS_Pos (0U)
+#define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
+#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD_Pos (26U)
+#define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
+#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF_Pos (25U)
+#define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
+#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
+#define ETH_DMAOMR_DFRF_Pos (24U)
+#define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
+#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF_Pos (21U)
+#define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
+#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
+#define ETH_DMAOMR_FTF_Pos (20U)
+#define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
+#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC_Pos (14U)
+#define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
+#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
+#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST_Pos (13U)
+#define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
+#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF_Pos (7U)
+#define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
+#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
+#define ETH_DMAOMR_FUGF_Pos (6U)
+#define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
+#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC_Pos (3U)
+#define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
+#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
+#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF_Pos (2U)
+#define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
+#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
+#define ETH_DMAOMR_SR_Pos (1U)
+#define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
+#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE_Pos (16U)
+#define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
+#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE_Pos (15U)
+#define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
+#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE_Pos (14U)
+#define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE_Pos (13U)
+#define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
+#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE_Pos (10U)
+#define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE_Pos (9U)
+#define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
+#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE_Pos (8U)
+#define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
+#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE_Pos (7U)
+#define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
+#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE_Pos (6U)
+#define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE_Pos (5U)
+#define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
+#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE_Pos (4U)
+#define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
+#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE_Pos (3U)
+#define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
+#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE_Pos (2U)
+#define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
+#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE_Pos (1U)
+#define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
+#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE_Pos (0U)
+#define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC_Pos (28U)
+#define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
+#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA_Pos (17U)
+#define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
+#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC_Pos (16U)
+#define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
+#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC_Pos (0U)
+#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
+#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP_Pos (0U)
+#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP_Pos (0U)
+#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP_Pos (0U)
+#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP_Pos (0U)
+#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
+
+#define RCC_MAX_FREQUENCY 168000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 144000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FMC_IRQn FSMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FMC_IRQHandler FSMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F407xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ #define STM32F407xx /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,218 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to STDIO_UART_TX
+// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to LD2 [Green Led]
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 // Connected to LD2 [Green Led]
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, // Connected to SWO
+ {PB_3_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to SWO
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9_ALT0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_9, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_10_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)},
+ {PB_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to STDIO_UART_TX
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to STDIO_UART_TX
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to STDIO_UART_RX
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // Connected to STDIO_UART_RX
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+// {PB_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+// {PB_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PC_4, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PC_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+// {PC_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+// {PC_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PC_12, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SWO
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD2 [Green Led]
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,201 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_9_ALT1 = PB_9 | ALT1,
+ PB_10 = 0x1A,
+ PB_10_ALT0 = PB_10 | ALT0,
+ PB_11 = 0x1B,
+ PB_11_ALT0 = PB_11 | ALT0,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_0,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = PC_7,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_2,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_3,
+#endif
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ LED_RED = LED1,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PB_15,
+ SPI_MISO = PB_14,
+ SPI_SCK = PB_13,
+ SPI_CS = PB_12,
+ PWM_OUT = PA_7,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PC_6,
+ SYS_TRACED0 = PC_10,
+ SYS_TRACED1 = PC_11,
+ SYS_TRACED2 = PC_12,
+ SYS_TRACED3 = PB_11,
+ SYS_WKUP1 = PA_0,
+ SYS_WKUP2 = PC_0,
+ SYS_WKUP3 = PC_1,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,239 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100
+ * AHBCLK (MHz) | 100
+ * APB1CLK (MHz) | 100
+ * APB2CLK (MHz) | 100
+ * USB capable | NO
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+* @brief Configures the System clock source, PLL Multiplier and Divider factors,
+* AHB/APBx prescalers and Flash settings
+* @note This function should be called only once the RCC clock configuration
+* is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 4;
+ RCC_OscInitStruct.PLL.PLLN = 100;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+ RCC_OscInitStruct.PLL.PLLN = 100;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f410rx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f410rx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,374 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f410rx.s +;* Author : MCD Application Team +;* Description : STM32F410Rx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20008000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LP TIM1 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DMA1_Stream7_IRQHandler +TIM5_IRQHandler +TIM6_DAC_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI5_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler +LPTIM1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_MICRO/stm32f410xb.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_MICRO/stm32f410xb.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F410RB: 128 KB FLASH (0x20000) + 32 KB SRAM (0x8000)
+LR_IROM1 0x08000000 0x20000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C8) (0x8000-0x1C8) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_STD/startup_stm32f410rx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_STD/startup_stm32f410rx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,348 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f410rx.s +;* Author : MCD Application Team +;* Description : STM32F410Rx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + + +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LP TIM1 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DMA1_Stream7_IRQHandler +TIM5_IRQHandler +TIM6_DAC_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI5_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler +LPTIM1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_STD/stm32f410xb.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_STD/stm32f410xb.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F410RB: 128 KB FLASH (0x20000) + 32 KB SRAM (0x8000)
+LR_IROM1 0x08000000 0x20000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C8) (0x8000-0x1C8) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/STM32F410xB.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/STM32F410xB.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x200001C8, LENGTH = 32k - 0x1C8
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410rx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410rx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,452 @@ +/** + ****************************************************************************** + * @file startup_stm32f410rx.s + * @author MCD Application Team + * @brief STM32F410Rx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM5_IRQHandler /* TIM5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + .word LPTIM1_IRQHandler /* LP TIM1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410rx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410rx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,508 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f410rx.s +;* Author : MCD Application Team +;* Description : STM32F410Rx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LP TIM1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK FMPI2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_EV_IRQHandler + B FMPI2C1_EV_IRQHandler + + PUBWEAK FMPI2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_ER_IRQHandler + B FMPI2C1_ER_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/stm32f410xx.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/stm32f410xx.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,31 @@
+/* [ROM = 128kb = 0x20000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0801FFFF;
+
+/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x200001C7; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x200001C8;
+define symbol __region_RAM_end__ = 0x20007FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x1000;
+define symbol __size_heap__ = 0x2000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F411RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 98 vectors = 392 bytes from 0x40 to 0x1C8 +// Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM +#define NVIC_NUM_VECTORS 114 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,52 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x20000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f410rx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f410rx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,7362 @@
+/**
+ ******************************************************************************
+ * @file stm32f410rx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F410Rx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f410rx
+ * @{
+ */
+
+#ifndef __STM32F410Rx_H
+#define __STM32F410Rx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x24 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(32 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x0801FFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+
+/*!< APB1 peripherals */
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC1_COMMON_BASE
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+#define RNG_BASE (PERIPH_BASE + 0x80000U)
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23_Pos (23U)
+#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM23 EXTI_IMR_MR23
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23_Pos (23U)
+#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+#define EXTI_EMR_EM23 EXTI_EMR_MR23
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23_Pos (23U)
+#define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
+#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23_Pos (23U)
+#define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
+#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23_Pos (23U)
+#define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
+#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23_Pos (23U)
+#define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
+#define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE_Pos (0U)
+#define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE_Pos (1U)
+#define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE_Pos (2U)
+#define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE_Pos (3U)
+#define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE_Pos (4U)
+#define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE_Pos (5U)
+#define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE_Pos (6U)
+#define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE_Pos (7U)
+#define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN_Pos (8U)
+#define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
+#define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF_Pos (12U)
+#define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN_Pos (14U)
+#define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN_Pos (15U)
+#define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC_Pos (16U)
+#define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH_Pos (17U)
+#define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN_Pos (19U)
+#define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN_Pos (20U)
+#define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN_Pos (21U)
+#define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN_Pos (22U)
+#define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN_Pos (23U)
+#define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD_Pos (0U)
+#define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN_Pos (10U)
+#define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10_Pos (11U)
+#define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R_Pos (12U)
+#define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START_Pos (13U)
+#define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
+#define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
+#define FMPI2C_CR2_STOP_Pos (14U)
+#define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK_Pos (15U)
+#define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES_Pos (16U)
+#define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD_Pos (24U)
+#define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND_Pos (25U)
+#define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE_Pos (26U)
+#define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1_Pos (0U)
+#define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE_Pos (10U)
+#define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN_Pos (15U)
+#define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2_Pos (1U)
+#define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK_Pos (8U)
+#define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN_Pos (15U)
+#define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL_Pos (0U)
+#define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH_Pos (8U)
+#define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL_Pos (16U)
+#define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
+#define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC_Pos (28U)
+#define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
+#define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE_Pos (0U)
+#define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS_Pos (1U)
+#define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE_Pos (2U)
+#define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR_Pos (3U)
+#define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF_Pos (4U)
+#define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF_Pos (5U)
+#define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define FMPI2C_ISR_TC_Pos (6U)
+#define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR_Pos (7U)
+#define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR_Pos (8U)
+#define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
+#define FMPI2C_ISR_ARLO_Pos (9U)
+#define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR_Pos (10U)
+#define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR_Pos (11U)
+#define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT_Pos (12U)
+#define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT_Pos (13U)
+#define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY_Pos (15U)
+#define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
+#define FMPI2C_ISR_DIR_Pos (16U)
+#define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE_Pos (17U)
+#define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF_Pos (3U)
+#define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF_Pos (4U)
+#define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF_Pos (5U)
+#define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF_Pos (8U)
+#define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF_Pos (9U)
+#define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF_Pos (10U)
+#define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF_Pos (11U)
+#define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF_Pos (12U)
+#define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF_Pos (13U)
+#define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC_Pos (0U)
+#define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA_Pos (0U)
+#define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA_Pos (0U)
+#define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_FMSSR_Pos (20U)
+#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
+#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR_Pos (21U)
+#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
+#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP3_Pos (6U)
+#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+#define PWR_CSR_EWUP2_Pos (7U)
+#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
+
+#define RCC_PLLCFGR_PLLR_Pos (28U)
+#define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
+#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+/*!< MCO1EN configuration */
+#define RCC_CFGR_MCO1EN_Pos (8U)
+#define RCC_CFGR_MCO1EN_Msk (0x1U << RCC_CFGR_MCO1EN_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_MCO1EN RCC_CFGR_MCO1EN_Msk /*!< MCO1EN bit */
+
+/*!< MCO2EN configuration */
+#define RCC_CFGR_MCO2EN_Pos (9U)
+#define RCC_CFGR_MCO2EN_Msk (0x1U << RCC_CFGR_MCO2EN_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_MCO2EN RCC_CFGR_MCO2EN_Msk /*!< MCO2EN bit */
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_RNGRST_Pos (31U)
+#define RCC_AHB1RSTR_RNGRST_Msk (0x1U << RCC_AHB1RSTR_RNGRST_Pos) /*!< 0x80000000 */
+#define RCC_AHB1RSTR_RNGRST RCC_AHB1RSTR_RNGRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
+#define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_RNGEN_Pos (31U)
+#define RCC_AHB1ENR_RNGEN_Msk (0x1U << RCC_AHB1ENR_RNGEN_Pos) /*!< 0x80000000 */
+#define RCC_AHB1ENR_RNGEN RCC_AHB1ENR_RNGEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
+#define RCC_APB1ENR_RTCAPBEN_Pos (10U)
+#define RCC_APB1ENR_RTCAPBEN_Msk (0x1U << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
+#define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_EXTITEN_Pos (15U)
+#define RCC_APB2ENR_EXTITEN_Msk (0x1U << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
+#define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_RNGLPEN_Pos (31U)
+#define RCC_AHB1LPENR_RNGLPEN_Msk (0x1U << RCC_AHB1LPENR_RNGLPEN_Pos) /*!< 0x80000000 */
+#define RCC_AHB1LPENR_RNGLPEN RCC_AHB1LPENR_RNGLPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
+#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
+#define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
+#define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1U << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
+#define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
+#define RCC_APB2LPENR_EXTITLPEN_Msk (0x1U << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+#define RCC_BDCR_LSEMOD_Pos (3U)
+#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+#define RCC_DCKCFGR_I2SSRC_Pos (25U)
+#define RCC_DCKCFGR_I2SSRC_Msk (0x3U << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x06000000 */
+#define RCC_DCKCFGR_I2SSRC RCC_DCKCFGR_I2SSRC_Msk
+#define RCC_DCKCFGR_I2SSRC_0 (0x1U << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x02000000 */
+#define RCC_DCKCFGR_I2SSRC_1 (0x2U << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x04000000 */
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
+#define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
+#define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
+#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
+#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
+#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
+#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
+#define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
+#define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/****************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
+#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */
+#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
+#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register *******************/
+#define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
+#define LPTIM_OR_LPT_IN1_RMP_Msk (0x3U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000003 */
+#define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
+#define LPTIM_OR_LPT_IN1_RMP_0 (0x1U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000001 */
+#define LPTIM_OR_LPT_IN1_RMP_1 (0x2U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000002 */
+
+/* Legacy Defines */
+#define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
+#define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
+#define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+
+/******************************* LPTIM Instances ******************************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5)
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x7F003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
+
+#define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F410Rx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ #define STM32F410Rx /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE, ELMO_RF_SPI2 = SPI_1,
+ SPI_2 = (int)SPI2_BASE, ELMO_SPI1 = SPI_2,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,212 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+// {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK
+// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,176 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ // Arduino connector namings
+ A0 = PC_0,
+ A1 = PC_1,
+ A2 = PC_2,
+ A3 = PC_3,
+ A4 = NC,
+ A5 = NC,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_1,
+ D3 = PA_0,
+ D4 = NC,
+ D5 = NC,
+ D6 = NC,
+ D7 = NC,
+ D8 = NC,
+ D9 = NC,
+ D10 = PB_12,
+ D11 = PB_15,
+ D12 = PB_14,
+ D13 = PB_13,
+ D14 = PC_9,
+ D15 = PA_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_9,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_10,
+#endif
+
+ // Generic signals namings
+ LED1 = PB_0,
+ LED2 = PB_1,
+ LED3 = PB_0,
+ LED4 = PB_1,
+ USER_BUTTON = PB_7,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ RF_SPI_MOSI = PA_7,
+ RF_SPI_MISO = PA_6,
+ RF_SPI_SCK = PA_5,
+ RF_SPI_CS = PA_4,
+ RF_RESET = PC_4,
+ RF_DIO0 = PC_10,
+ RF_DIO1 = PC_11,
+ RF_DIO2 = PC_12,
+ RF_DIO3 = PD_2,
+ RF_DIO4 = PB_5,
+ RF_DIO5 = PB_6,
+ RF_RXTX_SW = PC_13
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 16 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 96 | 96
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 96 | 96
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 96 | 96
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+* @brief Configures the System clock source, PLL Multiplier and Divider factors,
+* AHB/APBx prescalers and Flash settings
+* @note This function should be called only once the RCC clock configuration
+* is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0) {
+ while (1) {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
+ //RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
+ //RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+
+ RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 2 MHz (8 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (2 MHz * 192)
+
+
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,235 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to STDIO_UART_TX
+// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to LD2 [Green Led]
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, // Connected to SWO
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9_ALT0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to STDIO_UART_TX
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to STDIO_UART_TX
+// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to STDIO_UART_RX
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // Connected to STDIO_UART_RX
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to LD2 [Green Led]
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SWO
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD2 [Green Led]
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,216 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_1_ALT0 = PA_1 | ALT0,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_4_ALT1 = PB_4 | ALT1,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_5_ALT1 = PB_5 | ALT1,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_8_ALT1 = PB_8 | ALT1,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_9_ALT1 = PB_9 | ALT1,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_12_ALT0 = PB_12 | ALT0,
+ PB_13 = 0x1D,
+ PB_13_ALT0 = PB_13 | ALT0,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_0,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = PC_7,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_2,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_3,
+#endif
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ LED_RED = LED1,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_WKUP = PA_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,230 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | CLOCK_SOURCE_USB=1
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
+ * | 3- USE_PLL_HSI (internal 16 MHz) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100 | 96
+ * AHBCLK (MHz) | 100 | 96
+ * APB1CLK (MHz) | 50 | 48
+ * APB2CLK (MHz) | 100 | 96
+ * USB capable | NO | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+}
+
+
+/**
+* @brief Configures the System clock source, PLL Multiplier and Divider factors,
+* AHB/APBx prescalers and Flash settings
+* @note This function should be called only once the RCC clock configuration
+* is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+#else /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
+#endif /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100/96 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100/96 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50/48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100/96 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+#else /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
+#endif /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+#define STDIO_UART_TX PB_6
+#define STDIO_UART_RX PB_7
+#define STDIO_UART UART_1
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,224 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // SERIAL_TX
+// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // SERIAL_RX
+// {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // SPI_CS
+// {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // SPI_CLK
+// {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // SPI_MISO
+// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // SPI_MOSI
+// {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // SPI_CLK
+// {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // SPI_CS
+// {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Push SW 3
+// {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Push SW 4
+// {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Slide SW 1
+// {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Slide SW 2
+// {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // LED-4
+// {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Display LED
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+// {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+// {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // SERIAL_TX
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // SERIAL_TX
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // SERIAL_TX
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // SERIAL_RX
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // SERIAL_RX
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // SERIAL_RX
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+// {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO
+// {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO
+// {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO
+// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+// {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1
+// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO
+// {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+// {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+// {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+// {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
+// {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // WAKE_OUT
+// {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // GPS_EN
+// {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // GPS module SPI
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
+// {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // MPU9250 SPI MOSI
+// {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // MPU9250 SPI MISO
+// {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // GROVE SDA
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+// {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+// {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+// {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+// {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+// {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+// {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+// {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+// {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK
+// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,208 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // External IO connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ VBAT_AD_IN = A0,
+ VBAT_AD_EN = A1,
+ I2C_SCL = PB_10,
+ I2C_SDA = PB_3,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PA_4,
+
+ EXT_PIN_3 = PA_7,
+ EXT_PIN_4 = PA_6,
+ EXT_PIN_5 = PA_5,
+ EXT_PIN_6 = PA_4,
+ EXT_PIN_7 = PA_3,
+ EXT_PIN_8 = PA_2,
+ EXT_PIN_9 = PB_10,
+ EXT_PIN_10 = PB_3,
+ EXT_PIN_13 = PA_0,
+ EXT_PIN_14 = PA_1,
+
+ EXT_I2C_SCL = I2C_SCL,
+ EXT_I2C_SDA = I2C_SDA,
+ EXT_SPI_MOSI = SPI_MOSI,
+ EXT_SPI_MISO = SPI_MISO,
+ EXT_SPI_SCK = SPI_SCK,
+ EXT_SPI_CS = SPI_CS,
+ EXT_SERIAL_TX = PA_2,
+ EXT_SERIAL_RX = PA_3,
+
+ SCM_I2C_SCL = PA_8,
+ SCM_I2C_SDA = PC_9,
+ SCM_SPI_MOSI = PB_15,
+ SCM_SPI_MISO = PB_14,
+ SCM_SPI_SCK = PB_13,
+ SCM_SPI_CS = PB_12,
+ SCM_WAKE_IN = PC_8,
+ SCM_WAKE_OUT = PA_9,
+
+ GPS_INT = PB_5,
+ GPS_1PPS = PB_4,
+ GPS_WAKEUP = PD_2,
+ GPS_EN = PA_11,
+ GPS_SERIAL_TX = PC_6,
+ GPS_SERIAL_RX = PC_7,
+ GPS_SPI_MOSI = PC_12,
+ GPS_SPI_MISO = PC_11,
+ GPS_SPI_SCK = PC_10,
+ GPS_SPI_CS = PA_15,
+
+ LCD_LED = PC_5,
+ LCD_I2C_SCL = PB_8,
+ LCD_I2C_SDA = PB_9,
+ BME280_I2C_SCL = PB_8,
+ BME280_I2C_SDA = PB_9,
+
+ MPU9250_SPI_MOSI = PA_10,
+ MPU9250_SPI_MISO = PA_12,
+ MPU9250_SPI_SCK = PB_0,
+ MPU9250_SPI_CS = PB_1,
+
+ // Generic signals namings
+ LED1 = PC_13,
+ LED2 = PC_15,
+ LED3 = PH_1,
+ LED4 = PC_4,
+ LED_RED = LED1,
+
+ // Standardized button names
+ SW1 = PC_14,
+ SW2 = PH_0,
+ SW3 = PC_0,
+ SW4 = PC_1,
+ SW5 = PC_2,
+ SW6 = PC_3,
+
+ USER_BUTTON = SW1,
+ BUTTON1 = SW1,
+ BUTTON2 = SW2,
+ BUTTON3 = SW3,
+ BUTTON4 = SW4,
+ SLIDE_SW1 = SW5,
+ SLIDE_SW2 = SW6,
+
+ // Serial port pins
+ SERIAL_TX = PB_6,
+ SERIAL_RX = PB_7,
+ USBTX = PB_6,
+ USBRX = PB_7,
+
+ // USB pins
+ // USB_OTG_FS_SOF = PA_8,
+ // USB_OTG_FS_VBUS = PA_9,
+ // USB_OTG_FS_ID = PA_10,
+ // USB_OTG_FS_DM = PA_11,
+ // USB_OTG_FS_DP = PA_12,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | CLOCK_SOURCE_USB=1
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
+ * | 3- USE_PLL_HSI (internal 16 MHz) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100 | 96
+ * AHBCLK (MHz) | 100 | 96
+ * APB1CLK (MHz) | 50 | 48
+ * APB2CLK (MHz) | 100 | 96
+ * USB capable | NO | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+* @brief Configures the System clock source, PLL Multiplier and Divider factors,
+* AHB/APBx prescalers and Flash settings
+* @note This function should be called only once the RCC clock configuration
+* is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+#else /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
+#endif /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100/96 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100/96 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50/48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100/96 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+#else /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
+#endif /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,371 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+LR_IROM1 0x08000000 0x80000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,344 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_STD/stm32f411re.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_STD/stm32f411re.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,54 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x80000
+#endif
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_GCC_ARM/STM32F411XE.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_GCC_ARM/STM32F411XE.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,161 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 512K
+#endif
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,457 @@ +/** + ****************************************************************************** + * @file startup_stm32f411xe.s + * @author MCD Application Team + * @brief STM32F411xExx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,521 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Description : STM32F411xExx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_IAR/stm32f411xe.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_IAR/stm32f411xe.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,34 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x80000; }
+
+/* [ROM = 512kb = 0x80000] */
+define symbol __intvec_start__ = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
+
+/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000198;
+define symbol __region_RAM_end__ = 0x2001FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x4000;
+define symbol __size_heap__ = 0x8000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F411RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197 +// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM +#define NVIC_NUM_VECTORS 102 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x80000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f411xe.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f411xe.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,8638 @@
+/**
+ ******************************************************************************
+ * @file stm32f411xe.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f411xe
+ * @{
+ */
+
+#ifndef __STM32F411xE_H
+#define __STM32F411xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC1_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC1_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_FMSSR_Pos (20U)
+#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
+#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR_Pos (21U)
+#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
+#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+#define RCC_BDCR_LSEMOD_Pos (3U)
+#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
+#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
+#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
+#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
+#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
+#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
+#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
+#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
+#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x20003010U
+
+#define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F411xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ #define STM32F411xE /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,326 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - A0
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - LED1
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - A1
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - A3
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - A2
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - A4
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - A5
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+// {PB_3, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+// {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+// {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+// {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_10, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+// {PB_15, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PC_6, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PD_12, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PD_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+// {PF_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+// {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+// {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+
+// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+// {PE_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_14, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+// {PE_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_13, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+// {PE_2, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+// {PE_4, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,284 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ //Module pins.
+ P_1 = NC,
+ P_2 = PB_2,
+ P_3 = NC,
+ P_4 = PB_15,
+ P_5 = PB_12,
+ P_6 = PB_13,
+ P_7 = PB_14,
+ P_8 = PC_6,
+ P_9 = PA_15,
+ P_10 = NC,
+ P_11 = NC,
+ P_12 = PC_7,
+ P_13 = NC,
+ P_14 = PC_0,
+ P_15 = NC,
+ P_16 = PC_13,
+ P_17 = PB_8,
+ P_18 = PB_9,
+ P_19 = PB_10,
+ P_20 = NC,
+ P_21 = NC,
+ P_22 = NC,
+ P_23 = NC,
+ P_24 = NC,
+ P_25 = PA_14,
+ P_26 = PA_13,
+ P_27 = PB_3,
+ P_28 = NC,
+ P_29 = PB_7,
+ P_30 = PB_6,
+ P_31 = PB_4,
+ P_32 = NC,
+ P_33 = PA_10,
+ P_34 = PA_5,
+ P_35 = PA_11,
+ P_36 = PA_12,
+ P_37 = PB_0,
+ P_38 = PA_4,
+ P_39 = NC,
+ P_40 = NC,
+ P_41 = NC,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+
+ // Generic signals namings
+ LED1 = PB_2,
+ LED2 = PB_10,
+ LED3 = NC,
+ LED_RED = LED1,
+ LED_BLUE = LED2,
+ USER_BUTTON = PC_13,
+
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+
+ SERIAL_TX = P_8,
+ SERIAL_RX = P_12,
+
+ I2C_SCL = P_17,
+ I2C_SDA = P_18,
+
+ SPI_MOSI = P_4,
+ SPI_MISO = P_7,
+ SPI_SCK = P_6,
+ SPI_CS = P_5,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#elif MBED_CONF_TARGET_USB_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_TX,
+#else
+ STDIO_UART_TX = PB_6,
+#endif
+
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#elif MBED_CONF_TARGET_USB_RX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_RX,
+#else
+ STDIO_UART_RX = PB_7,
+#endif
+ //DAPLink
+ USBRX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ SWDIO = P_26,
+ SWCLK = P_25,
+ NTRST = P_13,
+
+ //MTB Aliases
+ //Left side (top view)
+ TGT_SWDIO = SWDIO,
+ TGT_SWCLK = SWCLK,
+ TGT_RESET = NTRST,
+ PB6 = P_30,
+ PB7 = P_29,
+ PC6 = SERIAL_TX,
+ PC7 = SERIAL_RX,
+ PB9 = I2C_SDA,
+ PB8 = I2C_SCL,
+ PB15 = SPI_MOSI,
+ PB14 = SPI_MISO,
+ PB13 = SPI_SCK,
+ PC13 = SPI_CS,
+ PC0 = P_14,
+ PA4 = P_38,
+ PA5 = P_34,
+ PB0 = P_37,
+
+ //Right side (top view)
+ GND = NC,
+ PA11 = P_35,
+ PA12 = P_36,
+ PB4 = P_31, //CS for LCD
+ PB3 = P_27, //RESET for LCD
+ PA15 = P_9, //A0 for LCD
+ PA10 = P_33,
+ PB12 = P_5,
+ PB10 = LED2,
+ PB2 = LED1,
+
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,273 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100
+ * AHBCLK (MHz) | 100
+ * APB1CLK (MHz) | 50
+ * APB2CLK (MHz) | 100
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "nvic_addr.h"
+#include "mbed_error.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ uint8_t ret_HSIclk_status = SetSysClock_PLL_HSI();
+ if (ret_HSIclk_status == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+ PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+ PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,349 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - LED1
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, // Connected to SWO
+ {PB_3_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to SWO
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue]
+ {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9_ALT0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to LD3 [Red]
+ {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to USB_SOF [TP1]
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_10_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)},
+ {PB_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PD_12, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PD_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_SOF [TP1]
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD2 [Blue]
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LD3 [Red]
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to USB_DM
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to USB_DP
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SWO
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue]
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red]
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to USB_ID
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_6_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_14_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Connected to USB_DM
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to USB_DP
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red]
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_5_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_13_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_2_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_4_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_11_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,318 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_2_ALT1 = PA_2 | ALT1,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_3_ALT1 = PA_3 | ALT1,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_4_ALT1 = PB_4 | ALT1,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_5_ALT1 = PB_5 | ALT1,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_8_ALT1 = PB_8 | ALT1,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_9_ALT1 = PB_9 | ALT1,
+ PB_10 = 0x1A,
+ PB_10_ALT0 = PB_10 | ALT0,
+ PB_11 = 0x1B,
+ PB_11_ALT0 = PB_11 | ALT0,
+ PB_12 = 0x1C,
+ PB_12_ALT0 = PB_12 | ALT0,
+ PB_13 = 0x1D,
+ PB_13_ALT0 = PB_13 | ALT0,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_2_ALT0 = PE_2 | ALT0,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_4_ALT0 = PE_4 | ALT0,
+ PE_5 = 0x45,
+ PE_5_ALT0 = PE_5 | ALT0,
+ PE_6 = 0x46,
+ PE_6_ALT0 = PE_6 | ALT0,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_11_ALT0 = PE_11 | ALT0,
+ PE_12 = 0x4C,
+ PE_12_ALT0 = PE_12 | ALT0,
+ PE_13 = 0x4D,
+ PE_13_ALT0 = PE_13 | ALT0,
+ PE_14 = 0x4E,
+ PE_14_ALT0 = PE_14 | ALT0,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_3,
+ A1 = PC_0,
+ A2 = PC_3,
+ A3 = PC_1,
+ A4 = PC_4,
+ A5 = PC_5,
+ D0 = PG_9,
+ D1 = PG_14,
+ D2 = PF_15,
+ D3 = PE_13,
+ D4 = PF_14,
+ D5 = PE_11,
+ D6 = PE_9,
+ D7 = PF_13,
+ D8 = PF_12,
+ D9 = PD_15,
+ D10 = PD_14,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PD_8,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PD_9,
+#endif
+
+ // Generic signals namings
+ LED1 = PB_0,
+ LED2 = PB_7,
+ LED3 = PB_14,
+ LED4 = LED1,
+ LED_RED = LED1,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ PWM_OUT = D9,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED0_ALT0 = PF_6,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED1_ALT0 = PF_7,
+ SYS_TRACED1_ALT1 = PD_3,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED2_ALT0 = PG_13,
+ SYS_TRACED3 = PE_6,
+ SYS_TRACED3_ALT0 = PG_14,
+ SYS_WKUP1 = PA_0,
+ SYS_WKUP2 = PC_0,
+ SYS_WKUP3 = PC_1,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,272 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100
+ * AHBCLK (MHz) | 100
+ * APB1CLK (MHz) | 50
+ * APB2CLK (MHz) | 100
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "nvic_addr.h"
+#include "mbed_error.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+ PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+ PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,326 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - A0
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - LED1
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - A1
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - A3
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - A2
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - A4
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - A5
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+// {PB_3, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+// {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+// {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+// {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_10, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+// {PB_15, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PC_6, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PD_12, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+// {PD_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+// {PF_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+// {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+// {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+
+// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+// {PE_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_14, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+// {PE_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_13, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+// {PE_2, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+// {PE_4, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,327 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ //Module pins.
+ P_1 = PB_12,
+ P_2 = PA_4,
+ P_3 = PB_10,
+ P_4 = PC_12,
+ P_5 = PC_15,
+ P_6 = PB_1,
+ P_7 = PB_0,
+ P_8 = PA_5,
+ P_9 = PC_13,
+ P_10 = PB_6,
+ P_11 = PB_7,
+ P_12 = NC,
+ P_13 = NC,
+ P_14 = NC,
+ P_15 = NC,
+ P_16 = NC,
+ P_17 = NC,
+ P_18 = NC,
+ P_19 = NC,
+ P_20 = NC,
+ P_21 = NC,
+ P_22 = PB_9,
+ P_23 = PC_3,
+ P_24 = PB_13,
+ P_25 = PC_2,
+ P_26 = NC,
+ P_27 = PC_0,
+ P_28 = NC,
+ P_29 = NC,
+ P_30 = NC,
+ P_31 = PA_7,
+ P_32 = PC_4,
+ P_33 = PC_11,
+ P_34 = PC_5,
+ P_35 = PB_2,
+ P_36 = PA_6,
+ P_37 = NC,
+ P_38 = PA_10,
+ P_39 = PA_9,
+ P_40 = PA_14,
+ P_41 = PB_3,
+ P_42 = PB_4,
+ P_43 = PA_15,
+ P_44 = PA_13,
+ P_45 = NC,
+ P_46 = NC,
+ P_47 = NC,
+ P_48 = NC,
+ P_49 = NC,
+ P_50 = NC,
+ P_51 = PA_12,
+ P_52 = PA_11,
+ P_53 = PB_14,
+ P_54 = NC,
+ P_55 = NC,
+ P_56 = NC,
+ P_57 = NC,
+ P_58 = NC,
+ P_59 = NC,
+ P_60 = NC,
+ P_61 = NC,
+ P_62 = NC,
+ P_63 = NC,
+ P_64 = NC,
+ P_65 = NC,
+ P_66 = NC,
+ P_67 = NC,
+ P_68 = NC,
+ P_69 = PC_14,
+ P_70 = NC,
+ P_71 = NC,
+ P_72 = NC,
+ P_73 = NC,
+ P_74 = NC,
+ P_75 = NC,
+ P_76 = NC,
+ P_77 = NC,
+ P_78 = NC,
+ P_79 = NC,
+ P_80 = NC,
+ P_81 = NC,
+ P_82 = NC,
+ P_83 = NC,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+
+ // Generic signals namings
+#ifdef MBED_CONF_TARGET_LED1
+ LED1 = MBED_CONF_TARGET_LED1,
+#else
+ LED1 = PA_7,
+#endif
+#ifdef MBED_CONF_TARGET_LED2
+ LED2 = MBED_CONF_TARGET_LED2,
+#else
+ LED2 = PC_4,
+#endif
+#ifdef MBED_CONF_TARGET_LED3
+ LED3 = MBED_CONF_TARGET_LED3,
+#else
+ LED3 = PC_11,
+#endif
+ LED_RED = LED1,
+ LED_BLUE = LED2,
+ LED_GREEN = LED3,
+ USER_BUTTON = PB_14,
+
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+
+ I2C_SCL = P_10,
+ I2C_SDA = P_11,
+
+ SPI_MOSI = P_23,
+ SPI_MISO = P_25,
+ SPI_SCK = P_24,
+ SPI_CS = P_22,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#elif MBED_CONF_TARGET_USB_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_TX,
+#else
+ STDIO_UART_TX = PA_9,
+#endif
+
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#elif MBED_CONF_TARGET_USB_RX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_RX,
+#else
+ STDIO_UART_RX = PA_10,
+#endif
+ //DAPLink
+ USBRX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+
+ //MTB Aliases
+ //Left side (top view)
+ PB7 = I2C_SDA,
+ PB6 = I2C_SCL,
+ PC3 = SPI_MOSI,
+ PC2 = SPI_MISO,
+ PB13 = SPI_SCK,
+ PB14 = USER_BUTTON,
+ GP1 = PC_15,
+
+//AIN0
+//AIN1
+//AIN2
+
+ //Right side (top view)
+ GP3 = PB_2,
+ GP2 = PC_5,
+ GP4 = PC_12,
+ GP5 = PB_10, //A0 for LCD
+ GP6 = PA_4, //RESET for LCD
+ GP7 = PB_12, //CS for LCD
+ GP8 = PC_0,
+
+//TX2 = WL_GPIO1
+//RX2 = WL_GPIO2
+
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,273 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100
+ * AHBCLK (MHz) | 100
+ * APB1CLK (MHz) | 50
+ * APB2CLK (MHz) | 100
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "nvic_addr.h"
+#include "mbed_error.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ uint8_t ret_HSIclk_status = SetSysClock_PLL_HSI();
+ if (ret_HSIclk_status == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+ PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+ PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f412zx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f412zx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,425 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f412zx.s +;* Author : MCD Application Team +;* Description : STM32F412Zx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20040000 ; Top of RAM 256K + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +QUADSPI_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/stm32f412xg.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/stm32f412xg.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,54 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2017, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
+; STM32F412ZG: 1024 KB FLASH (0x100000) + 256 KB SRAM (0x40000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C4) (0x40000-0x1C4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/startup_stm32f412zx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/startup_stm32f412zx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,398 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f412zx.s +;* Author : MCD Application Team +;* Description : STM32F412Zx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20040000 ; Top of RAM 256K + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +QUADSPI_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/stm32f412xg.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/stm32f412xg.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,54 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2017, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
+; STM32F412ZG: 1024 KB FLASH (0x100000) + 256 KB SRAM (0x40000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C4) (0x40000-0x1C4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/STM32F412xG.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/STM32F412xG.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,160 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 1024K
+#endif
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = 0x200001C4, LENGTH = 256K - 0x1C4
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412zx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412zx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,529 @@ +/** + ****************************************************************************** + * @file startup_stm32f412zx.s + * @author MCD Application Team + * @brief STM32F412Zx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QUADSPI_IRQHandler /* QuadSPI */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/startup_stm32f412zx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/startup_stm32f412zx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,637 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f412zx.s +;* Author : MCD Application Team +;* Description : STM32F412Zx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter0 + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter1 + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK FMPI2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_EV_IRQHandler + B FMPI2C1_EV_IRQHandler + + PUBWEAK FMPI2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_ER_IRQHandler + B FMPI2C1_ER_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,33 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+
+/* [ROM = 1024kb = 0x100000] */
+define symbol __intvec_start__ = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE;
+
+/* [RAM = 256kb = 0x40000] Vector table dynamic copy: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x200001C7; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x200001C8;
+define symbol __region_RAM_end__ = 0x2003FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x8000;
+define symbol __size_heap__ = 0x10000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F412ZG +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 97 vectors = 388 bytes from 0x40 to 0x1C3 +// Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM +#define NVIC_NUM_VECTORS 113 +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM + + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Flash size */ +#define FLASH_SIZE (uint32_t) 0x100000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f412zx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f412zx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,14491 @@
+/**
+ ******************************************************************************
+ * @file stm32f412zx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F412Zx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f412zx
+ * @{
+ */
+
+#ifndef __STM32F412Zx_H
+#define __STM32F412Zx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x24 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC1_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC1_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos (14U)
+#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos (15U)
+#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos (16U)
+#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos (17U)
+#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos (18U)
+#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos (19U)
+#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos (20U)
+#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos (21U)
+#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos (22U)
+#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos (23U)
+#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos (24U)
+#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos (25U)
+#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos (26U)
+#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos (27U)
+#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define QSPI1_V2_1L /*!< QSPI Virtual Version */
+
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos (0U)
+#define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos (0U)
+#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos (29U)
+#define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos (24U)
+#define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos (18U)
+#define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
+#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
+#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos (0U)
+#define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
+
+/***************** Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk (0xFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x000F0000 */
+#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos (8U)
+#define DFSDM_FLTCR2_EXCH_Msk (0xFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x00000F00 */
+#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos (24U)
+#define DFSDM_FLTISR_SCDF_Msk (0xFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0x0F000000 */
+#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos (16U)
+#define DFSDM_FLTISR_CKABF_Msk (0xFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x000F0000 */
+#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos (14U)
+#define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos (13U)
+#define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos (4U)
+#define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos (3U)
+#define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos (2U)
+#define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos (1U)
+#define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos (0U)
+#define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
+#define DFSDM_FLTICR_CLRSCSDF_Msk (0xFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0x0F000000 */
+#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk (0xFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x000F0000 */
+#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk (0xFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos (29U)
+#define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos (16U)
+#define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos (0U)
+#define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk (0xFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x00000F00 */
+#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk (0xFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x00000F00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN_Pos (0U)
+#define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN_Pos (1U)
+#define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP_Pos (2U)
+#define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR1_MWID_Pos (4U)
+#define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR1_FACCEN_Pos (6U)
+#define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN_Pos (8U)
+#define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL_Pos (9U)
+#define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WAITCFG_Pos (11U)
+#define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN_Pos (12U)
+#define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN_Pos (13U)
+#define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD_Pos (14U)
+#define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE_Pos (16U)
+#define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR1_CBURSTRW_Pos (19U)
+#define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+#define FSMC_BCR1_CCLKEN_Pos (20U)
+#define FSMC_BCR1_CCLKEN_Msk (0x1U << FSMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FSMC_BCR1_CCLKEN FSMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FSMC_BCR1_WFDIS_Pos (21U)
+#define FSMC_BCR1_WFDIS_Msk (0x1U << FSMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
+#define FSMC_BCR1_WFDIS FSMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN_Pos (0U)
+#define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN_Pos (1U)
+#define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP_Pos (2U)
+#define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR2_MWID_Pos (4U)
+#define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR2_FACCEN_Pos (6U)
+#define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN_Pos (8U)
+#define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL_Pos (9U)
+#define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WAITCFG_Pos (11U)
+#define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN_Pos (12U)
+#define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN_Pos (13U)
+#define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD_Pos (14U)
+#define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR2_CPSIZE_Pos (16U)
+#define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR2_CBURSTRW_Pos (19U)
+#define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN_Pos (0U)
+#define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN_Pos (1U)
+#define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP_Pos (2U)
+#define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR3_MWID_Pos (4U)
+#define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR3_FACCEN_Pos (6U)
+#define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN_Pos (8U)
+#define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL_Pos (9U)
+#define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WAITCFG_Pos (11U)
+#define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN_Pos (12U)
+#define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN_Pos (13U)
+#define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD_Pos (14U)
+#define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR3_CPSIZE_Pos (16U)
+#define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR3_CBURSTRW_Pos (19U)
+#define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN_Pos (0U)
+#define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN_Pos (1U)
+#define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP_Pos (2U)
+#define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR4_MWID_Pos (4U)
+#define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR4_FACCEN_Pos (6U)
+#define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN_Pos (8U)
+#define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL_Pos (9U)
+#define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WAITCFG_Pos (11U)
+#define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN_Pos (12U)
+#define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN_Pos (13U)
+#define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD_Pos (14U)
+#define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR4_CPSIZE_Pos (16U)
+#define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR4_CBURSTRW_Pos (19U)
+#define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET_Pos (0U)
+#define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR1_ADDHLD_Pos (4U)
+#define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR1_DATAST_Pos (8U)
+#define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR1_BUSTURN_Pos (16U)
+#define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR1_CLKDIV_Pos (20U)
+#define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR1_DATLAT_Pos (24U)
+#define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR1_ACCMOD_Pos (28U)
+#define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET_Pos (0U)
+#define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR2_ADDHLD_Pos (4U)
+#define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR2_DATAST_Pos (8U)
+#define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR2_BUSTURN_Pos (16U)
+#define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR2_CLKDIV_Pos (20U)
+#define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR2_DATLAT_Pos (24U)
+#define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR2_ACCMOD_Pos (28U)
+#define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET_Pos (0U)
+#define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR3_ADDHLD_Pos (4U)
+#define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR3_DATAST_Pos (8U)
+#define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR3_BUSTURN_Pos (16U)
+#define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR3_CLKDIV_Pos (20U)
+#define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR3_DATLAT_Pos (24U)
+#define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR3_ACCMOD_Pos (28U)
+#define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET_Pos (0U)
+#define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR4_ADDHLD_Pos (4U)
+#define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR4_DATAST_Pos (8U)
+#define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR4_BUSTURN_Pos (16U)
+#define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR4_CLKDIV_Pos (20U)
+#define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR4_DATLAT_Pos (24U)
+#define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR4_ACCMOD_Pos (28U)
+#define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET_Pos (0U)
+#define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR1_ADDHLD_Pos (4U)
+#define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR1_DATAST_Pos (8U)
+#define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR1_BUSTURN_Pos (16U)
+#define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR1_ACCMOD_Pos (28U)
+#define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET_Pos (0U)
+#define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR2_ADDHLD_Pos (4U)
+#define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR2_DATAST_Pos (8U)
+#define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR2_BUSTURN_Pos (16U)
+#define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR2_ACCMOD_Pos (28U)
+#define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET_Pos (0U)
+#define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR3_ADDHLD_Pos (4U)
+#define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR3_DATAST_Pos (8U)
+#define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR3_BUSTURN_Pos (16U)
+#define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR3_ACCMOD_Pos (28U)
+#define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET_Pos (0U)
+#define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR4_ADDHLD_Pos (4U)
+#define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR4_DATAST_Pos (8U)
+#define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN_Pos (16U)
+#define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR4_ACCMOD_Pos (28U)
+#define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE_Pos (0U)
+#define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE_Pos (1U)
+#define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE_Pos (2U)
+#define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE_Pos (3U)
+#define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE_Pos (4U)
+#define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE_Pos (5U)
+#define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE_Pos (6U)
+#define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE_Pos (7U)
+#define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN_Pos (8U)
+#define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
+#define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF_Pos (12U)
+#define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN_Pos (14U)
+#define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN_Pos (15U)
+#define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC_Pos (16U)
+#define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH_Pos (17U)
+#define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN_Pos (19U)
+#define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN_Pos (20U)
+#define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN_Pos (21U)
+#define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN_Pos (22U)
+#define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN_Pos (23U)
+#define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD_Pos (0U)
+#define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN_Pos (10U)
+#define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10_Pos (11U)
+#define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R_Pos (12U)
+#define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START_Pos (13U)
+#define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
+#define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
+#define FMPI2C_CR2_STOP_Pos (14U)
+#define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK_Pos (15U)
+#define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES_Pos (16U)
+#define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD_Pos (24U)
+#define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND_Pos (25U)
+#define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE_Pos (26U)
+#define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1_Pos (0U)
+#define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE_Pos (10U)
+#define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN_Pos (15U)
+#define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2_Pos (1U)
+#define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK_Pos (8U)
+#define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN_Pos (15U)
+#define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL_Pos (0U)
+#define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH_Pos (8U)
+#define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL_Pos (16U)
+#define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
+#define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC_Pos (28U)
+#define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
+#define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE_Pos (0U)
+#define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS_Pos (1U)
+#define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE_Pos (2U)
+#define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR_Pos (3U)
+#define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF_Pos (4U)
+#define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF_Pos (5U)
+#define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define FMPI2C_ISR_TC_Pos (6U)
+#define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR_Pos (7U)
+#define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR_Pos (8U)
+#define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
+#define FMPI2C_ISR_ARLO_Pos (9U)
+#define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR_Pos (10U)
+#define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR_Pos (11U)
+#define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT_Pos (12U)
+#define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT_Pos (13U)
+#define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY_Pos (15U)
+#define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
+#define FMPI2C_ISR_DIR_Pos (16U)
+#define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE_Pos (17U)
+#define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF_Pos (3U)
+#define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF_Pos (4U)
+#define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF_Pos (5U)
+#define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF_Pos (8U)
+#define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF_Pos (9U)
+#define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF_Pos (10U)
+#define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF_Pos (11U)
+#define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF_Pos (12U)
+#define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF_Pos (13U)
+#define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC_Pos (0U)
+#define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA_Pos (0U)
+#define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA_Pos (0U)
+#define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_FMSSR_Pos (20U)
+#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
+#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR_Pos (21U)
+#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
+#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP3_Pos (6U)
+#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+#define PWR_CSR_EWUP2_Pos (7U)
+#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define QSPI1_V2_1L /*!< QSPI Virtual Version */
+
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN_Pos (0U)
+#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos (1U)
+#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos (2U)
+#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos (3U)
+#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos (4U)
+#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos (6U)
+#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
+#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos (7U)
+#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos (8U)
+#define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
+#define QUADSPI_CR_TEIE_Pos (16U)
+#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos (17U)
+#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos (18U)
+#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos (19U)
+#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos (20U)
+#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos (22U)
+#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos (23U)
+#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos (24U)
+#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE_Pos (0U)
+#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos (8U)
+#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos (16U)
+#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF_Pos (0U)
+#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos (1U)
+#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos (2U)
+#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos (3U)
+#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos (4U)
+#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos (5U)
+#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos (8U)
+#define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF_Pos (0U)
+#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos (1U)
+#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos (3U)
+#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos (4U)
+#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL_Pos (0U)
+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos (8U)
+#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos (10U)
+#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos (12U)
+#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos (14U)
+#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos (16U)
+#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos (18U)
+#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos (24U)
+#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos (26U)
+#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos (28U)
+#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos (30U)
+#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM_Pos (31U)
+#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS_Pos (0U)
+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA_Pos (0U)
+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK_Pos (0U)
+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH_Pos (0U)
+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL_Pos (0U)
+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
+
+#define RCC_PLLCFGR_PLLR_Pos (28U)
+#define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
+#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
+#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
+#define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_RNGEN_Pos (6U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FSMCEN_Pos (0U)
+#define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos (1U)
+#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
+#define RCC_APB1ENR_RTCAPBEN_Pos (10U)
+#define RCC_APB1ENR_RTCAPBEN_Msk (0x1U << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
+#define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (1U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_EXTITEN_Pos (15U)
+#define RCC_APB2ENR_EXTITEN_Msk (0x1U << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
+#define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
+#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
+#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
+#define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
+#define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1U << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
+#define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
+#define RCC_APB2LPENR_EXTITLPEN_Msk (0x1U << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos (24U)
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+#define RCC_BDCR_LSEMOD_Pos (3U)
+#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
+#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
+#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
+#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
+#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
+#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
+#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
+#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
+#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SSRC_Pos (22U)
+#define RCC_PLLI2SCFGR_PLLI2SSRC_Msk (0x1U << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC_Msk
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+
+#define RCC_DCKCFGR_CKDFSDM1ASEL_Pos (15U)
+#define RCC_DCKCFGR_CKDFSDM1ASEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */
+#define RCC_DCKCFGR_CKDFSDM1ASEL RCC_DCKCFGR_CKDFSDM1ASEL_Msk
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+#define RCC_DCKCFGR_I2S1SRC_Pos (25U)
+#define RCC_DCKCFGR_I2S1SRC_Msk (0x3U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x06000000 */
+#define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
+#define RCC_DCKCFGR_I2S1SRC_0 (0x1U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x02000000 */
+#define RCC_DCKCFGR_I2S1SRC_1 (0x2U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x04000000 */
+
+#define RCC_DCKCFGR_I2S2SRC_Pos (27U)
+#define RCC_DCKCFGR_I2S2SRC_Msk (0x3U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x18000000 */
+#define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
+#define RCC_DCKCFGR_I2S2SRC_0 (0x1U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x08000000 */
+#define RCC_DCKCFGR_I2S2SRC_1 (0x2U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x10000000 */
+#define RCC_DCKCFGR_CKDFSDM1SEL_Pos (31U)
+#define RCC_DCKCFGR_CKDFSDM1SEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */
+#define RCC_DCKCFGR_CKDFSDM1SEL RCC_DCKCFGR_CKDFSDM1SEL_Msk
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
+#define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
+#define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
+#define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
+#define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
+#define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
+#define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
+#define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1U << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
+#define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
+#define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
+#define RCC_CKGATENR_SPARE_CKEN_Msk (0x1U << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
+#define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
+#define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
+#define RCC_CKGATENR_SRAM_CKEN_Msk (0x1U << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
+#define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
+#define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
+#define RCC_CKGATENR_FLITF_CKEN_Msk (0x1U << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
+#define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
+#define RCC_CKGATENR_RCC_CKEN_Pos (6U)
+#define RCC_CKGATENR_RCC_CKEN_Msk (0x1U << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
+#define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
+#define RCC_CKGATENR_RCC_EVTCTL_Pos (7U)
+#define RCC_CKGATENR_RCC_EVTCTL_Msk (0x1U << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */
+#define RCC_CKGATENR_RCC_EVTCTL RCC_CKGATENR_RCC_EVTCTL_Msk
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
+#define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
+#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
+#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
+#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
+#define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
+#define RCC_DCKCFGR2_SDIOSEL_Msk (0x1U << RCC_DCKCFGR2_SDIOSEL_Pos) /*!< 0x10000000 */
+#define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+#define I2S_APB1_APB2_FEATURE /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+/****************** Bit definition for SYSCFG_CFGR register ****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
+#define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
+#define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
+#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDETM_Pos (23U)
+#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_DCDET_Pos (0U)
+#define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos (1U)
+#define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos (2U)
+#define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos (19U)
+#define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos (20U)
+#define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL_Pos (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
+
+#define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FMC_IRQn FSMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FMC_IRQHandler FSMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F412Zx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ #define STM32F412Zx /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE,
+ UART_9 = (int)UART9_BASE,
+ UART_10 = (int)UART10_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE,
+ CAN_3 = (int)CAN3_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,401 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 // Connected to B_USER
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to ARD_A1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to ARD_A2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to CODEC_MCK [WM8994ECS_MCLK1]
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to ARD_D8
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to ARD_A3
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to SD_CMD
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to DFSDM2_DATIN1
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to ARD_D6
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // Connected to ARD_A4
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to ARD_A0
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to CTP_INT
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Connected to CODEC_ext_SD [WM8994ECS_ADC_DAT1]
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Connected to CODEC_SD [WM8994ECS_DACDAT1]
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to ARD_A5
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to LED2_GREEN
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 // Connected to ARD_D8
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 // Connected to ARD_A3
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, // Connected to STLINK_JTDO_SWCLK
+ {PB_3_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to STLINK_JTDO_SWCLK
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Connected to ARD_D12 // Connected to WIFI module
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to DFSDM2_DATIN7
+ {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Connected to ARD_D9
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to CODEC_WS [WM8994ECS_LRCLK1]
+ {PB_9_ALT0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, // Connected to CODEC_WS [WM8994ECS_LRCLK1]
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ARD_D14
+ {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to LCD_TE
+ {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to I2CFMP_SDA [WM8994ECS_SDA]
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to SD_D1
+ {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
+ {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to LCD_PSRAM_D1
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to PSRAM_A0 [IS66WV51216EBLL_A0]
+ {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to PSRAM_A9 [IS66WV51216EBLL_A9]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to DFSDM1_CKOUT
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to ARD_D4
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to ARD_D9
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ARD_D15
+ {PB_10_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)}, // Connected to ARD_D15
+ {PB_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to WIFI_WKUP
+ {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to I2CFMP1_SCL [WM8994ECS_CLK]
+ {PD_12, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to PSRAM_A17 [IS66WV51216EBLL_A17]
+ {PD_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to LCD_PSRAM_D0
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to PSRAM_A1 [IS66WV51216EBLL_A1]
+ {PF_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to PSRAM_A8 [IS66WV51216EBLL_A8]
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to B_USER
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to B_USER
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ARD_A1
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ARD_A1
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ARD_A2
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ARD_A2
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to ARD_A2
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to CODEC_MCK [WM8994ECS_MCLK1]
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to CODEC_MCK [WM8994ECS_MCLK1]
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // Connected to CODEC_MCK [WM8994ECS_MCLK1]
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ARD_A3
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ARD_A3
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to SD_CMD
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to SD_CMD
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to DFSDM2_DATIN1
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to DFSDM2_DATIN1
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to DFSDM2_DATIN1
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to DFSDM2_DATIN1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to DFSDM1_CKOUT
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_OTG_FS_VBUS
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_OTG_FS_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_OTG_FS_DM
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ARD_D10
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to ARD_D6
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to ARD_D6
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to ARD_D6
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to ARD_A4
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to ARD_A4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to ARD_A4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to STLINK_JTDO_SWCLK
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to ARD_D12 // Connected to WIFI module
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ARD_D11 // Connected to WIFI module
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to ARD_D4
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to DFSDM2_DATIN7
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to ARD_D9
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 // Connected to ARD_D9
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to CODEC_WS [WM8994ECS_LRCLK1]
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to CODEC_WS [WM8994ECS_LRCLK1]
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ARD_D15
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ARD_D14
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to LCD_CTP_RST
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LCD_TE
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LCD_TE
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LCD_TE
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to WIFI_WKUP
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to WIFI_WKUP
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 // Connected to WIFI_WKUP
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to I2CFMP1_SCL [WM8994ECS_CLK]
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to I2CFMP1_SCL [WM8994ECS_CLK]
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to I2CFMP_SDA [WM8994ECS_SDA]
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to I2CFMP_SDA [WM8994ECS_SDA]
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to SD_D0
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to SD_D0
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to SD_D1
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to SD_D1
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to PSRAM_A17 [IS66WV51216EBLL_A17]
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to LCD_PSRAM_D0
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to LCD_PSRAM_D1
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // Connected to ARD_D5
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to LCD_PSRAM_D5
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to LCD_PSRAM_D6
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LCD_PSRAM_D7
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to LCD_PSRAM_D8
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to LCD_PSRAM_D9
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to LCD_PSRAM_D10
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to LCD_PSRAM_D11
+// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to PSRAM_A3 [IS66WV51216EBLL_A3]
+// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to PSRAM_A4 [IS66WV51216EBLL_A4]
+// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to PSRAM_A5 [IS66WV51216EBLL_A5]
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 // Connected to ARD_D0
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to ARD_D1
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0]
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1]
+// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to ARD_D3
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to B_USER
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_A2
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_VBUS
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to USB_OTG_FS_DM
+ {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, // Connected to USB_OTG_FS_DP
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to ARD_D10
+ {PA_15_ALT0, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to ARD_D10
+ {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to ARD_D12 // Connected to WIFI module
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to ARD_D4
+ {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, // Connected to ARD_D4
+ {PB_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, // Connected to CODEC_WS [WM8994ECS_LRCLK1]
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_D15
+ {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, // Connected to LCD_CTP_RST
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to I2CFMP1_SCL [WM8994ECS_CLK]
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SD_D2
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SD_CLK
+ {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, // Connected to LCD_PSRAM_D3
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to LCD_PSRAM_NWE
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LCD_PSRAM_D13
+ {PD_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LCd_PSRAM_D15
+ {PD_15, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, // Connected to LCD_PSRAM_D1
+ {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to PSRAM_NBL1 [IS66WV51216EBLL_UB]
+ {PE_3, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, // Connected to LED1_RED
+ {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to LCD_PSRAM_D5
+ {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to ARD_D1
+ {PF_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1]
+ {PG_1, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, // Connected to PSRAM_A11 [IS66WV51216EBLL_A11]
+ {PG_12, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, // Connected to WIFI_DRDY
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to STDIO_UART_TX
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ARD_A1
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to CODEC_MCK [WM8994ECS_MCLK1]
+ {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to DFSDM1_CKOUT
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_ID
+ {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, // Connected to USB_OTG_FS_DM
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to USB_OTG_FS_DP
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STLINK_JTDO_SWCLK
+ {PB_3_ALT0, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to STLINK_JTDO_SWCLK
+ {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, // Connected to ARD_D11 // Connected to WIFI module
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to DFSDM2_DATIN7
+ {PB_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, // Connected to ARD_D9
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_D14
+ {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, // Connected to ARD_D13 // Connected to WIFI module // Connected to LD5
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED2_GREEN
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to I2CFMP_SDA [WM8994ECS_SDA]
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SD_D3
+ {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to SD_D3
+ {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, // Connected to LCD_PSRAM_D2
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to DFSDM2_CKOUT
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to DFSDM1_DATIN1
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LCD_PSRAM_D14
+ {PD_14, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, // Connected to LCD_PSRAM_D0
+ {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to PSRAM_NBL0 [IS66WV51216EBLL_LB]
+ {PE_2, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+ {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to LCD_PSRAM_D4
+ {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to ARD_D0
+ {PF_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0]
+ {PG_0, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, // Connected to PSRAM_A10 [IS66WV51216EBLL_A10]
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to STDIO_UART_RX
+ {PG_11, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, // Connected to WIFI_SPI_CSN
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_A1
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DP
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LCD_TE
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to LCD_PSRAM_NOE
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A17 [IS66WV51216EBLL_A17]
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to USB_OTG_FS_PWR_EN [STMPS2141STR_EN]
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to WIFI_DRDY
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B_USER
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DM
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, // Connected to LCD_CTP_RST
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to CODEC_CK [WM8994ECS_BCLK1]
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A16 [IS66WV51216EBLL_A16]
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to ARD_D2
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to CODEC_INT [WM8994ECS_GPIO1]
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to ARD_A1
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to DFSDM2_DATIN1
+ {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_OTG_FS_ID
+ {PA_10_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to USB_OTG_FS_ID
+ {PB_5_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D11 // Connected to WIFI module
+ {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to ARD_D11 // Connected to WIFI module
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to ARD_D9
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to WIFI_WKUP
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CODEC_SD [WM8994ECS_DACDAT1]
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SD_CLK
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, // Connected to DFSDM1_DATIN1
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to ARD_D5
+ {PE_6_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to ARD_D5
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to LCD_PSRAM_D11
+ {PE_14_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to LCD_PSRAM_D11
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SD_CMD
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Connected to USB_OTG_FS_DM
+ {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_OTG_FS_DP
+ {PA_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to USB_OTG_FS_DP
+ {PB_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D12 // Connected to WIFI module
+ {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to ARD_D12 // Connected to WIFI module
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LCD_TE
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CODEC_ext_SD [WM8994ECS_ADC_DAT1]
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SD_D3
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+ {PE_5_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to LCD_PSRAM_D10
+ {PE_13_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to LCD_PSRAM_D10
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_A3
+ {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_OTG_FS_VBUS
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to ARD_D6
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to STLINK_JTDO_SWCLK
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to STLINK_JTDO_SWCLK
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ARD_D15
+ {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Connected to ARD_D13 // Connected to WIFI module // Connected to LD5
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LCD_CTP_RST
+ {PB_13_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Connected to LCD_CTP_RST
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to I2CFMP_SDA [WM8994ECS_SDA]
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SD_D2
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CODEC_CK [WM8994ECS_BCLK1]
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+ {PE_2_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to LCD_PSRAM_D9
+ {PE_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to LCD_PSRAM_D9
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D8
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to ARD_D8
+ {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_OTG_FS_DM
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D10
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to ARD_D10
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to ARD_A4
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CODEC_WS [WM8994ECS_LRCLK1]
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ARD_D13 // Connected to WIFI module // Connected to LD5
+ {PB_12_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Connected to ARD_D13 // Connected to WIFI module // Connected to LD5
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to MEMS_LED
+ {PE_4_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to MEMS_LED
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to LCD_PSRAM_D8
+ {PE_11_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to LCD_PSRAM_D8
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_8, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, // Connected to DFSDM1_CKOUT
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_OTG_FS_DM
+ {PB_3, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, // Connected to STLINK_JTDO_SWCLK
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to ARD_D11 // Connected to WIFI module
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, // Connected to ARD_D9
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to ARD_D13 // Connected to WIFI module // Connected to LD5
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to LCD_PSRAM_D2
+ {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to PSRAM_A10 [IS66WV51216EBLL_A10]
+ {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to WIFI_SPI_CSN
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_OTG_FS_DP
+ {PA_15, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, // Connected to ARD_D10
+ {PB_4, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, // Connected to ARD_D12 // Connected to WIFI module
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to ARD_D4
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, // Connected to CODEC_WS [WM8994ECS_LRCLK1]
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to LCD_CTP_RST
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to LCD_PSRAM_D3
+ {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to PSRAM_A11 [IS66WV51216EBLL_A11]
+ {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to WIFI_DRDY
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,314 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_10_ALT0 = PA_10 | ALT0,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_12_ALT0 = PA_12 | ALT0,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_6 = 0x16,
+ PB_6_ALT0 = PB_6 | ALT0,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_10_ALT0 = PB_10 | ALT0,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_12_ALT0 = PB_12 | ALT0,
+ PB_13 = 0x1D,
+ PB_13_ALT0 = PB_13 | ALT0,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_11_ALT0 = PC_11 | ALT0,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_2_ALT0 = PE_2 | ALT0,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_4_ALT0 = PE_4 | ALT0,
+ PE_5 = 0x45,
+ PE_5_ALT0 = PE_5 | ALT0,
+ PE_6 = 0x46,
+ PE_6_ALT0 = PE_6 | ALT0,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_11_ALT0 = PE_11 | ALT0,
+ PE_12 = 0x4C,
+ PE_12_ALT0 = PE_12 | ALT0,
+ PE_13 = 0x4D,
+ PE_13_ALT0 = PE_13 | ALT0,
+ PE_14 = 0x4E,
+ PE_14_ALT0 = PE_14 | ALT0,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PC_0,
+ A1 = PA_1,
+ A2 = PA_2,
+ A3 = PA_5,
+ A4 = PB_1,
+ A5 = PC_4,
+ D0 = PF_6,
+ D1 = PF_7,
+ D2 = PG_13,
+ D3 = PF_10,
+ D4 = PB_6,
+ D5 = PE_6,
+ D6 = PB_0,
+ D7 = PC_13,
+ D8 = PA_4,
+ D9 = PB_8,
+ D10 = PA_15,
+ D11 = PB_5,
+ D12 = PB_4,
+ D13 = PB_12,
+ D14 = PB_11,
+ D15 = PB_10,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PG_14,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PG_9,
+#endif
+
+ // Generic signals namings
+ LED1 = PC_5, // Green = LD3 on the board
+ LED2 = PE_3, // Red = LD4 on the board
+ LED3 = PB_12, // Green = LD5 on the board, connected to Arduino D13
+ LED4 = LED1,
+ LED_RED = LED2,
+ USER_BUTTON = PA_0,
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ PWM_OUT = D9,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED0_ALT0 = PF_6,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED1_ALT0 = PF_7,
+ SYS_TRACED1_ALT1 = PD_3,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED2_ALT0 = PG_13,
+ SYS_TRACED3 = PE_6,
+ SYS_TRACED3_ALT0 = PG_14,
+ SYS_WKUP1 = PA_0,
+ SYS_WKUP2 = PC_0,
+ SYS_WKUP3 = PC_1,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,273 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100
+ * AHBCLK (MHz) | 100
+ * APB1CLK (MHz) | 50
+ * APB2CLK (MHz) | 100
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+ PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLI2S output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+ PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE,
+ UART_9 = (int)UART9_BASE,
+ UART_10 = (int)UART10_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE,
+ CAN_3 = (int)CAN3_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,401 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to LD1
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, // Connected to SWO
+ {PB_3_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to SWO
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue]
+ {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9_ALT0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to LD3 [Red]
+ {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to USB_SOF [TP1]
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_10_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)},
+ {PB_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PD_12, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PD_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_SOF [TP1]
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD1
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LD1
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD1
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD2 [Blue]
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LD3 [Red]
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to USB_DM
+ {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, // Connected to USB_DP
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_15_ALT0, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+ {PB_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX
+ {PD_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_15, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)},
+ {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PE_3, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)},
+ {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PG_1, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)},
+ {PG_12, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)},
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to USB_SOF [TP1]
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID
+ {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, // Connected to USB_DM
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to USB_DP
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SWO
+ {PB_3_ALT0, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to SWO
+ {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue]
+ {PB_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)},
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX
+ {PD_14, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)},
+ {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PE_2, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)},
+ {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PG_0, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)},
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_11, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red]
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_ID
+ {PA_10_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to USB_ID
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_6_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_14_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Connected to USB_DM
+ {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_DP
+ {PA_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to USB_DP
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red]
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_5_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_13_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_VBUS
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to LD1
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_2_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_DM
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_4_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_11_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_8, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, // Connected to USB_SOF [TP1]
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM
+ {PB_3, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, // Connected to SWO
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP
+ {PA_15, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
+ {PB_4, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)},
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)},
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,317 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_2_ALT1 = PA_2 | ALT1,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_3_ALT1 = PA_3 | ALT1,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_10_ALT0 = PA_10 | ALT0,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_12_ALT0 = PA_12 | ALT0,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PA_4 | ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_6 = 0x16,
+ PB_6_ALT0 = PB_6 | ALT0,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_10_ALT0 = PB_10 | ALT0,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_12_ALT0 = PB_12 | ALT0,
+ PB_13 = 0x1D,
+ PB_13_ALT0 = PB_13 | ALT0,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_11_ALT0 = PC_11 | ALT0,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_2_ALT0 = PE_2 | ALT0,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_4_ALT0 = PE_4 | ALT0,
+ PE_5 = 0x45,
+ PE_5_ALT0 = PE_5 | ALT0,
+ PE_6 = 0x46,
+ PE_6_ALT0 = PE_6 | ALT0,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_11_ALT0 = PE_11 | ALT0,
+ PE_12 = 0x4C,
+ PE_12_ALT0 = PE_12 | ALT0,
+ PE_13 = 0x4D,
+ PE_13_ALT0 = PE_13 | ALT0,
+ PE_14 = 0x4E,
+ PE_14_ALT0 = PE_14 | ALT0,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_3,
+ A1 = PC_0,
+ A2 = PC_3,
+ A3 = PC_1,
+ A4 = PC_4,
+ A5 = PC_5,
+ D0 = PG_9,
+ D1 = PG_14,
+ D2 = PF_15,
+ D3 = PE_13,
+ D4 = PF_14,
+ D5 = PE_11,
+ D6 = PE_9,
+ D7 = PF_13,
+ D8 = PF_12,
+ D9 = PD_15,
+ D10 = PD_14,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PD_8,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PD_9,
+#endif
+
+ // Generic signals namings
+ LED1 = PB_0, // Green
+ LED2 = PB_7, // Blue
+ LED3 = PB_14, // Red
+ LED4 = LED1,
+ LED_RED = LED3,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ PWM_OUT = D9,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED0_ALT0 = PF_6,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED1_ALT0 = PF_7,
+ SYS_TRACED1_ALT1 = PD_3,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED2_ALT0 = PG_13,
+ SYS_TRACED3 = PE_6,
+ SYS_TRACED3_ALT0 = PG_14,
+ SYS_WKUP1 = PA_0,
+ SYS_WKUP2 = PC_0,
+ SYS_WKUP3 = PC_1,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100
+ * AHBCLK (MHz) | 100
+ * APB1CLK (MHz) | 50
+ * APB2CLK (MHz) | 100
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLI2S output as USB clock source */
+ PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
+ PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+ PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/startup_stm32f413xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/startup_stm32f413xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,464 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f413xx.s +;* Author : MCD Application Team +;* Description : STM32F413xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20050000 ; Top of RAM 320K + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6, DAC1 and DAC2 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD UART9_IRQHandler ; UART9 + DCD UART10_IRQHandler ; UART10 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD DFSDM2_FLT0_IRQHandler ; DFSDM2 Filter0 + DCD DFSDM2_FLT1_IRQHandler ; DFSDM2 Filter1 + DCD DFSDM2_FLT2_IRQHandler ; DFSDM2 Filter2 + DCD DFSDM2_FLT3_IRQHandler ; DFSDM2 Filter3 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT CAN3_TX_IRQHandler [WEAK] + EXPORT CAN3_RX0_IRQHandler [WEAK] + EXPORT CAN3_RX1_IRQHandler [WEAK] + EXPORT CAN3_SCE_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT UART10_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT DFSDM2_FLT0_IRQHandler [WEAK] + EXPORT DFSDM2_FLT1_IRQHandler [WEAK] + EXPORT DFSDM2_FLT2_IRQHandler [WEAK] + EXPORT DFSDM2_FLT3_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +CAN3_TX_IRQHandler +CAN3_RX0_IRQHandler +CAN3_RX1_IRQHandler +CAN3_SCE_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SAI1_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +QUADSPI_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler +LPTIM1_IRQHandler +DFSDM2_FLT0_IRQHandler +DFSDM2_FLT1_IRQHandler +DFSDM2_FLT2_IRQHandler +DFSDM2_FLT3_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/stm32f413xh.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/stm32f413xh.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2017, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F413ZH: 1536 KB FLASH (0x150000) + 320 KB SRAM (0x50000)
+LR_IROM1 0x08000000 0x150000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x150000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 118 vectors = 472 bytes (0x1D8) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1D8) (0x50000-0x1D8) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_STD/startup_stm32f413xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_STD/startup_stm32f413xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,437 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f413xx.s +;* Author : MCD Application Team +;* Description : STM32F413xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20050000 ; Top of RAM 320K + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6, DAC1 and DAC2 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD UART9_IRQHandler ; UART9 + DCD UART10_IRQHandler ; UART10 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD DFSDM2_FLT0_IRQHandler ; DFSDM2 Filter0 + DCD DFSDM2_FLT1_IRQHandler ; DFSDM2 Filter1 + DCD DFSDM2_FLT2_IRQHandler ; DFSDM2 Filter2 + DCD DFSDM2_FLT3_IRQHandler ; DFSDM2 Filter3 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT CAN3_TX_IRQHandler [WEAK] + EXPORT CAN3_RX0_IRQHandler [WEAK] + EXPORT CAN3_RX1_IRQHandler [WEAK] + EXPORT CAN3_SCE_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT UART10_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT DFSDM2_FLT0_IRQHandler [WEAK] + EXPORT DFSDM2_FLT1_IRQHandler [WEAK] + EXPORT DFSDM2_FLT2_IRQHandler [WEAK] + EXPORT DFSDM2_FLT3_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +CAN3_TX_IRQHandler +CAN3_RX0_IRQHandler +CAN3_RX1_IRQHandler +CAN3_SCE_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SAI1_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +QUADSPI_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler +LPTIM1_IRQHandler +DFSDM2_FLT0_IRQHandler +DFSDM2_FLT1_IRQHandler +DFSDM2_FLT2_IRQHandler +DFSDM2_FLT3_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_STD/stm32f413xh.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_STD/stm32f413xh.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2017, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F413ZH: 1536 KB FLASH (0x150000) + 320 KB SRAM (0x50000)
+LR_IROM1 0x08000000 0x150000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x150000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 118 vectors = 472 bytes (0x1D8) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1D8) (0x50000-0x1D8) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/STM32F413xH.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/STM32F413xH.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1536K
+ RAM (rwx) : ORIGIN = 0x200001D8, LENGTH = 320K - 0x1D8
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/startup_stm32f413xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/startup_stm32f413xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,585 @@ +/** + ****************************************************************************** + * @file startup_stm32f413xx.s + * @author MCD Application Team + * @brief STM32F413xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6, DAC1 and DAC2 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word CAN3_TX_IRQHandler /* CAN3 TX */ + .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ + .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ + .word CAN3_SCE_IRQHandler /* CAN3 SCE */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word SAI1_IRQHandler /* SAI1 */ + .word UART9_IRQHandler /* UART9 */ + .word UART10_IRQHandler /* UART10 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QUADSPI_IRQHandler /* QuadSPI */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word DFSDM2_FLT0_IRQHandler /* DFSDM2 Filter0 */ + .word DFSDM2_FLT1_IRQHandler /* DFSDM2 Filter1 */ + .word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */ + .word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak CAN3_TX_IRQHandler + .thumb_set CAN3_TX_IRQHandler,Default_Handler + + .weak CAN3_RX0_IRQHandler + .thumb_set CAN3_RX0_IRQHandler,Default_Handler + + .weak CAN3_RX1_IRQHandler + .thumb_set CAN3_RX1_IRQHandler,Default_Handler + + .weak CAN3_SCE_IRQHandler + .thumb_set CAN3_SCE_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak UART10_IRQHandler + .thumb_set UART10_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak DFSDM2_FLT0_IRQHandler + .thumb_set DFSDM2_FLT0_IRQHandler,Default_Handler + + .weak DFSDM2_FLT1_IRQHandler + .thumb_set DFSDM2_FLT1_IRQHandler,Default_Handler + + .weak DFSDM2_FLT2_IRQHandler + .thumb_set DFSDM2_FLT2_IRQHandler,Default_Handler + + .weak DFSDM2_FLT3_IRQHandler + .thumb_set DFSDM2_FLT3_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/startup_stm32f413xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/startup_stm32f413xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,727 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f413xx.s +;* Author : MCD Application Team +;* Description : STM32F413xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6, DAC1 and DAC2 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter0 + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter1 + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD UART9_IRQHandler ; UART9 + DCD UART10_IRQHandler ; UART10 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD DFSDM2_FLT0_IRQHandler ; DFSDM2 Filter0 + DCD DFSDM2_FLT1_IRQHandler ; DFSDM2 Filter1 + DCD DFSDM2_FLT2_IRQHandler ; DFSDM2 Filter2 + DCD DFSDM2_FLT3_IRQHandler ; DFSDM2 Filter3 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK CAN3_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN3_TX_IRQHandler + B CAN3_TX_IRQHandler + + PUBWEAK CAN3_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN3_RX0_IRQHandler + B CAN3_RX0_IRQHandler + + PUBWEAK CAN3_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN3_RX1_IRQHandler + B CAN3_RX1_IRQHandler + + PUBWEAK CAN3_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN3_SCE_IRQHandler + B CAN3_SCE_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK UART10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART10_IRQHandler + B UART10_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK FMPI2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_EV_IRQHandler + B FMPI2C1_EV_IRQHandler + + PUBWEAK FMPI2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_ER_IRQHandler + B FMPI2C1_ER_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK DFSDM2_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM2_FLT0_IRQHandler + B DFSDM2_FLT0_IRQHandler + + PUBWEAK DFSDM2_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM2_FLT1_IRQHandler + B DFSDM2_FLT1_IRQHandler + + PUBWEAK DFSDM2_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM2_FLT2_IRQHandler + B DFSDM2_FLT2_IRQHandler + + PUBWEAK DFSDM2_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM2_FLT3_IRQHandler + B DFSDM2_FLT3_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/stm32f413xx.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/stm32f413xx.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,30 @@
+/* [ROM = 1536kb = 0x180000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0817FFFF;
+
+/* [RAM = 320kb = 0x50000] Vector table dynamic copy: 118 vectors = 472 bytes (0x1D8) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x200001D7;
+define symbol __region_RAM_start__ = 0x200001D8; /* Aligned on 8 bytes */
+define symbol __region_RAM_end__ = 0x2004FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x8000;
+define symbol __size_heap__ = 0x10000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
\ No newline at end of file
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F412ZG +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 102 vectors = 408 bytes from 0x40 to 0x1D7 +// Total: 118 vectors = 472 bytes (0x1D8) to be reserved in RAM +#define NVIC_NUM_VECTORS 118 +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM + + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x180000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_12 ((uint32_t)0x08100000) /* Base @ of Sector 12, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_13 ((uint32_t)0x08120000) /* Base @ of Sector 13, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_14 ((uint32_t)0x08140000) /* Base @ of Sector 14, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_15 ((uint32_t)0x08160000) /* Base @ of Sector 15, 128 Kbytes */ + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/stm32f413xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/stm32f413xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,15092 @@
+/**
+ ******************************************************************************
+ * @file stm32f413xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F413xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f413xx
+ * @{
+ */
+
+#ifndef __STM32F413xx_H
+#define __STM32F413xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ CAN3_TX_IRQn = 74, /*!< CAN3 TX Interrupt */
+ CAN3_RX0_IRQn = 75, /*!< CAN3 RX0 Interrupt */
+ CAN3_RX1_IRQn = 76, /*!< CAN3 RX1 Interrupt */
+ CAN3_SCE_IRQn = 77, /*!< CAN3 SCE Interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ UART9_IRQn = 88, /*!< UART9 global Interrupt */
+ UART10_IRQn = 89, /*!< UART10 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97, /*!< LP TIM1 interrupt */
+ DFSDM2_FLT0_IRQn = 98, /*!< DFSDM2 Filter 0 global Interrupt */
+ DFSDM2_FLT1_IRQn = 99, /*!< DFSDM2 Filter 1 global Interrupt */
+ DFSDM2_FLT2_IRQn = 100, /*!< DFSDM2 Filter 2 global Interrupt */
+ DFSDM2_FLT3_IRQn = 101 /*!< DFSDM2 Filter 3 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+ __IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset: 0x30 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7; /*!< Reserved, 0x84 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH (up to 1.5 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */
+#define SRAM2_BASE 0x20040000U /*!< SRAM2(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22800000U /*!< SRAM2(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x0817FFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define UART9_BASE (APB2PERIPH_BASE + 0x1800U)
+#define UART10_BASE (APB2PERIPH_BASE + 0x1C00U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC1_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400U)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
+#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00U)
+#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20U)
+#define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40U)
+#define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60U)
+#define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80U)
+#define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0U)
+#define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0U)
+#define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0U)
+#define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100U)
+#define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180U)
+#define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200U)
+#define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define UART9 ((USART_TypeDef *) UART9_BASE)
+#define UART10 ((USART_TypeDef *) UART10_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC1_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
+#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
+#define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
+#define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
+#define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
+#define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
+#define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
+#define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
+#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
+#define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
+#define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
+#define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos (14U)
+#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos (15U)
+#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos (16U)
+#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos (17U)
+#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos (18U)
+#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos (19U)
+#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos (20U)
+#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos (21U)
+#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos (22U)
+#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos (23U)
+#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos (24U)
+#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos (25U)
+#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos (26U)
+#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos (27U)
+#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos (0U)
+#define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos (0U)
+#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos (29U)
+#define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos (24U)
+#define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos (18U)
+#define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
+#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
+#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos (0U)
+#define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
+
+/***************** Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos (8U)
+#define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos (24U)
+#define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos (16U)
+#define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos (14U)
+#define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos (13U)
+#define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos (4U)
+#define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos (3U)
+#define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos (2U)
+#define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos (1U)
+#define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos (0U)
+#define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
+#define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
+
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos (29U)
+#define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos (16U)
+#define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos (0U)
+#define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0xFU << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_CHSEL_3 0x10000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23_Pos (23U)
+#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM23 EXTI_IMR_MR23
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23_Pos (23U)
+#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+#define EXTI_EMR_EM23 EXTI_EMR_MR23
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23_Pos (23U)
+#define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
+#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23_Pos (23U)
+#define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
+#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23_Pos (23U)
+#define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
+#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23_Pos (23U)
+#define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
+#define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0x7FFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x7FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_nWRP_12 0x10000000U
+#define FLASH_OPTCR_nWRP_13 0x20000000U
+#define FLASH_OPTCR_nWRP_14 0x40000000U
+#define FLASH_OPTCR_nWRP_15 0x40000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN_Pos (0U)
+#define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN_Pos (1U)
+#define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP_Pos (2U)
+#define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR1_MWID_Pos (4U)
+#define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR1_FACCEN_Pos (6U)
+#define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN_Pos (8U)
+#define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL_Pos (9U)
+#define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WAITCFG_Pos (11U)
+#define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN_Pos (12U)
+#define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN_Pos (13U)
+#define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD_Pos (14U)
+#define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE_Pos (16U)
+#define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR1_CBURSTRW_Pos (19U)
+#define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+#define FSMC_BCR1_CCLKEN_Pos (20U)
+#define FSMC_BCR1_CCLKEN_Msk (0x1U << FSMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FSMC_BCR1_CCLKEN FSMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FSMC_BCR1_WFDIS_Pos (21U)
+#define FSMC_BCR1_WFDIS_Msk (0x1U << FSMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
+#define FSMC_BCR1_WFDIS FSMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN_Pos (0U)
+#define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN_Pos (1U)
+#define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP_Pos (2U)
+#define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR2_MWID_Pos (4U)
+#define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR2_FACCEN_Pos (6U)
+#define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN_Pos (8U)
+#define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL_Pos (9U)
+#define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WAITCFG_Pos (11U)
+#define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN_Pos (12U)
+#define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN_Pos (13U)
+#define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD_Pos (14U)
+#define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR2_CPSIZE_Pos (16U)
+#define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR2_CBURSTRW_Pos (19U)
+#define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN_Pos (0U)
+#define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN_Pos (1U)
+#define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP_Pos (2U)
+#define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR3_MWID_Pos (4U)
+#define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR3_FACCEN_Pos (6U)
+#define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN_Pos (8U)
+#define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL_Pos (9U)
+#define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WAITCFG_Pos (11U)
+#define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN_Pos (12U)
+#define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN_Pos (13U)
+#define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD_Pos (14U)
+#define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR3_CPSIZE_Pos (16U)
+#define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR3_CBURSTRW_Pos (19U)
+#define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN_Pos (0U)
+#define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN_Pos (1U)
+#define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP_Pos (2U)
+#define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCR4_MWID_Pos (4U)
+#define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCR4_FACCEN_Pos (6U)
+#define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN_Pos (8U)
+#define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL_Pos (9U)
+#define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WAITCFG_Pos (11U)
+#define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN_Pos (12U)
+#define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN_Pos (13U)
+#define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD_Pos (14U)
+#define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FSMC_BCR4_CPSIZE_Pos (16U)
+#define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
+#define FSMC_BCR4_CBURSTRW_Pos (19U)
+#define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET_Pos (0U)
+#define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR1_ADDHLD_Pos (4U)
+#define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR1_DATAST_Pos (8U)
+#define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR1_BUSTURN_Pos (16U)
+#define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR1_CLKDIV_Pos (20U)
+#define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR1_DATLAT_Pos (24U)
+#define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR1_ACCMOD_Pos (28U)
+#define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET_Pos (0U)
+#define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR2_ADDHLD_Pos (4U)
+#define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR2_DATAST_Pos (8U)
+#define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR2_BUSTURN_Pos (16U)
+#define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR2_CLKDIV_Pos (20U)
+#define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR2_DATLAT_Pos (24U)
+#define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR2_ACCMOD_Pos (28U)
+#define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET_Pos (0U)
+#define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR3_ADDHLD_Pos (4U)
+#define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR3_DATAST_Pos (8U)
+#define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR3_BUSTURN_Pos (16U)
+#define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR3_CLKDIV_Pos (20U)
+#define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR3_DATLAT_Pos (24U)
+#define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR3_ACCMOD_Pos (28U)
+#define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET_Pos (0U)
+#define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTR4_ADDHLD_Pos (4U)
+#define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTR4_DATAST_Pos (8U)
+#define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTR4_BUSTURN_Pos (16U)
+#define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTR4_CLKDIV_Pos (20U)
+#define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTR4_DATLAT_Pos (24U)
+#define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTR4_ACCMOD_Pos (28U)
+#define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET_Pos (0U)
+#define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR1_ADDHLD_Pos (4U)
+#define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR1_DATAST_Pos (8U)
+#define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR1_BUSTURN_Pos (16U)
+#define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR1_ACCMOD_Pos (28U)
+#define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET_Pos (0U)
+#define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR2_ADDHLD_Pos (4U)
+#define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR2_DATAST_Pos (8U)
+#define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR2_BUSTURN_Pos (16U)
+#define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR2_ACCMOD_Pos (28U)
+#define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET_Pos (0U)
+#define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR3_ADDHLD_Pos (4U)
+#define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR3_DATAST_Pos (8U)
+#define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTR3_BUSTURN_Pos (16U)
+#define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR3_ACCMOD_Pos (28U)
+#define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET_Pos (0U)
+#define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTR4_ADDHLD_Pos (4U)
+#define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTR4_DATAST_Pos (8U)
+#define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN_Pos (16U)
+#define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTR4_ACCMOD_Pos (28U)
+#define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
+#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
+
+#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
+#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
+
+#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
+#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
+
+#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
+#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
+
+#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
+#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
+
+#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
+#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
+
+#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
+#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
+
+#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
+#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
+
+#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
+#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
+
+#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
+#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
+
+#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
+#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
+
+#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
+#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
+
+#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
+#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
+
+#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
+#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
+
+#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
+#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
+
+#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
+#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0_Pos (0U)
+#define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
+#define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPDR_PUPDR1_Pos (2U)
+#define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
+#define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
+
+#define GPIO_PUPDR_PUPDR2_Pos (4U)
+#define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
+#define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
+
+#define GPIO_PUPDR_PUPDR3_Pos (6U)
+#define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
+#define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
+
+#define GPIO_PUPDR_PUPDR4_Pos (8U)
+#define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
+#define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
+
+#define GPIO_PUPDR_PUPDR5_Pos (10U)
+#define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
+#define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
+
+#define GPIO_PUPDR_PUPDR6_Pos (12U)
+#define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
+#define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
+
+#define GPIO_PUPDR_PUPDR7_Pos (14U)
+#define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
+#define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
+
+#define GPIO_PUPDR_PUPDR8_Pos (16U)
+#define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
+#define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
+
+#define GPIO_PUPDR_PUPDR9_Pos (18U)
+#define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
+#define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
+
+#define GPIO_PUPDR_PUPDR10_Pos (20U)
+#define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
+#define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
+
+#define GPIO_PUPDR_PUPDR11_Pos (22U)
+#define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
+#define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
+
+#define GPIO_PUPDR_PUPDR12_Pos (24U)
+#define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
+#define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
+
+#define GPIO_PUPDR_PUPDR13_Pos (26U)
+#define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
+#define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
+
+#define GPIO_PUPDR_PUPDR14_Pos (28U)
+#define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
+#define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
+
+#define GPIO_PUPDR_PUPDR15_Pos (30U)
+#define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
+#define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE_Pos (0U)
+#define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE_Pos (1U)
+#define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE_Pos (2U)
+#define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE_Pos (3U)
+#define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE_Pos (4U)
+#define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE_Pos (5U)
+#define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE_Pos (6U)
+#define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE_Pos (7U)
+#define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN_Pos (8U)
+#define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
+#define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF_Pos (12U)
+#define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN_Pos (14U)
+#define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN_Pos (15U)
+#define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC_Pos (16U)
+#define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH_Pos (17U)
+#define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN_Pos (19U)
+#define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN_Pos (20U)
+#define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN_Pos (21U)
+#define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN_Pos (22U)
+#define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN_Pos (23U)
+#define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD_Pos (0U)
+#define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN_Pos (10U)
+#define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10_Pos (11U)
+#define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R_Pos (12U)
+#define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START_Pos (13U)
+#define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
+#define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
+#define FMPI2C_CR2_STOP_Pos (14U)
+#define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK_Pos (15U)
+#define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES_Pos (16U)
+#define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD_Pos (24U)
+#define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND_Pos (25U)
+#define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE_Pos (26U)
+#define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1_Pos (0U)
+#define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE_Pos (10U)
+#define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN_Pos (15U)
+#define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2_Pos (1U)
+#define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK_Pos (8U)
+#define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN_Pos (15U)
+#define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL_Pos (0U)
+#define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH_Pos (8U)
+#define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL_Pos (16U)
+#define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
+#define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC_Pos (28U)
+#define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
+#define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE_Pos (0U)
+#define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS_Pos (1U)
+#define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE_Pos (2U)
+#define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR_Pos (3U)
+#define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF_Pos (4U)
+#define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF_Pos (5U)
+#define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define FMPI2C_ISR_TC_Pos (6U)
+#define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR_Pos (7U)
+#define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR_Pos (8U)
+#define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
+#define FMPI2C_ISR_ARLO_Pos (9U)
+#define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR_Pos (10U)
+#define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR_Pos (11U)
+#define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT_Pos (12U)
+#define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT_Pos (13U)
+#define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY_Pos (15U)
+#define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
+#define FMPI2C_ISR_DIR_Pos (16U)
+#define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE_Pos (17U)
+#define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF_Pos (3U)
+#define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF_Pos (4U)
+#define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF_Pos (5U)
+#define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF_Pos (8U)
+#define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF_Pos (9U)
+#define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF_Pos (10U)
+#define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF_Pos (11U)
+#define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF_Pos (12U)
+#define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF_Pos (13U)
+#define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC_Pos (0U)
+#define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA_Pos (0U)
+#define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA_Pos (0U)
+#define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_FMSSR_Pos (20U)
+#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
+#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR_Pos (21U)
+#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
+#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP3_Pos (6U)
+#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+#define PWR_CSR_EWUP2_Pos (7U)
+#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN_Pos (0U)
+#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos (1U)
+#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos (2U)
+#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos (3U)
+#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos (4U)
+#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos (6U)
+#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
+#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos (7U)
+#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos (8U)
+#define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
+#define QUADSPI_CR_TEIE_Pos (16U)
+#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos (17U)
+#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos (18U)
+#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos (19U)
+#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos (20U)
+#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos (22U)
+#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos (23U)
+#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos (24U)
+#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE_Pos (0U)
+#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos (8U)
+#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos (16U)
+#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF_Pos (0U)
+#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos (1U)
+#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos (2U)
+#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos (3U)
+#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos (4U)
+#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos (5U)
+#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos (8U)
+#define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF_Pos (0U)
+#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos (1U)
+#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos (3U)
+#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos (4U)
+#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL_Pos (0U)
+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos (8U)
+#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos (10U)
+#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos (12U)
+#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos (14U)
+#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos (16U)
+#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos (18U)
+#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos (24U)
+#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos (26U)
+#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos (28U)
+#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos (30U)
+#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM_Pos (31U)
+#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS_Pos (0U)
+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA_Pos (0U)
+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK_Pos (0U)
+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH_Pos (0U)
+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL_Pos (0U)
+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
+
+#define RCC_PLLCFGR_PLLR_Pos (28U)
+#define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
+#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
+#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
+#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
+#define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
+#define RCC_APB1RSTR_CAN3RST_Pos (27U)
+#define RCC_APB1RSTR_CAN3RST_Msk (0x1U << RCC_APB1RSTR_CAN3RST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
+#define RCC_APB1RSTR_UART7RST_Pos (30U)
+#define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
+#define RCC_APB1RSTR_UART8RST_Pos (31U)
+#define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_UART9RST_Pos (6U)
+#define RCC_APB2RSTR_UART9RST_Msk (0x1U << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
+#define RCC_APB2RSTR_UART10RST_Pos (7U)
+#define RCC_APB2RSTR_UART10RST_Msk (0x1U << RCC_APB2RSTR_UART10RST_Pos) /*!< 0x00000080 */
+#define RCC_APB2RSTR_UART10RST RCC_APB2RSTR_UART10RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
+#define RCC_APB2RSTR_DFSDM2RST_Pos (25U)
+#define RCC_APB2RSTR_DFSDM2RST_Msk (0x1U << RCC_APB2RSTR_DFSDM2RST_Pos) /*!< 0x02000000 */
+#define RCC_APB2RSTR_DFSDM2RST RCC_APB2RSTR_DFSDM2RST_Msk
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_RNGEN_Pos (6U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FSMCEN_Pos (0U)
+#define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos (1U)
+#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
+#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
+#define RCC_APB1ENR_RTCAPBEN_Pos (10U)
+#define RCC_APB1ENR_RTCAPBEN_Msk (0x1U << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
+#define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
+#define RCC_APB1ENR_CAN3EN_Pos (27U)
+#define RCC_APB1ENR_CAN3EN_Msk (0x1U << RCC_APB1ENR_CAN3EN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
+#define RCC_APB1ENR_UART7EN_Pos (30U)
+#define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
+#define RCC_APB1ENR_UART8EN_Pos (31U)
+#define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (1U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_UART9EN_Pos (6U)
+#define RCC_APB2ENR_UART9EN_Msk (0x1U << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
+#define RCC_APB2ENR_UART10EN_Pos (7U)
+#define RCC_APB2ENR_UART10EN_Msk (0x1U << RCC_APB2ENR_UART10EN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_UART10EN RCC_APB2ENR_UART10EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_EXTITEN_Pos (15U)
+#define RCC_APB2ENR_EXTITEN_Msk (0x1U << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
+#define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos (22U)
+#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
+#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
+#define RCC_APB2ENR_DFSDM2EN_Pos (25U)
+#define RCC_APB2ENR_DFSDM2EN_Msk (0x1U << RCC_APB2ENR_DFSDM2EN_Pos) /*!< 0x02000000 */
+#define RCC_APB2ENR_DFSDM2EN RCC_APB2ENR_DFSDM2EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
+#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
+#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
+#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
+#define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
+#define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1U << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
+#define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
+#define RCC_APB1LPENR_CAN3LPEN_Pos (27U)
+#define RCC_APB1LPENR_CAN3LPEN_Msk (0x1U << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
+#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
+#define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
+#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
+#define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_UART9LPEN_Pos (6U)
+#define RCC_APB2LPENR_UART9LPEN_Msk (0x1U << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
+#define RCC_APB2LPENR_UART10LPEN_Pos (7U)
+#define RCC_APB2LPENR_UART10LPEN_Msk (0x1U << RCC_APB2LPENR_UART10LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2LPENR_UART10LPEN RCC_APB2LPENR_UART10LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
+#define RCC_APB2LPENR_EXTITLPEN_Msk (0x1U << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos (24U)
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
+#define RCC_APB2LPENR_DFSDM2LPEN_Pos (25U)
+#define RCC_APB2LPENR_DFSDM2LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM2LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB2LPENR_DFSDM2LPEN RCC_APB2LPENR_DFSDM2LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+#define RCC_BDCR_LSEMOD_Pos (3U)
+#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
+#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
+#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
+#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
+#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
+#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
+#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
+#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
+#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SSRC_Pos (22U)
+#define RCC_PLLI2SCFGR_PLLI2SSRC_Msk (0x1U << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC_Msk
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVR_Pos (0U)
+#define RCC_DCKCFGR_PLLI2SDIVR_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x0000001F */
+#define RCC_DCKCFGR_PLLI2SDIVR RCC_DCKCFGR_PLLI2SDIVR_Msk
+#define RCC_DCKCFGR_PLLI2SDIVR_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000001 */
+#define RCC_DCKCFGR_PLLI2SDIVR_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000002 */
+#define RCC_DCKCFGR_PLLI2SDIVR_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000004 */
+#define RCC_DCKCFGR_PLLI2SDIVR_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000008 */
+#define RCC_DCKCFGR_PLLI2SDIVR_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000010 */
+
+#define RCC_DCKCFGR_PLLDIVR_Pos (8U)
+#define RCC_DCKCFGR_PLLDIVR_Msk (0x1FU << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001F00 */
+#define RCC_DCKCFGR_PLLDIVR RCC_DCKCFGR_PLLDIVR_Msk
+#define RCC_DCKCFGR_PLLDIVR_0 (0x01U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000100 */
+#define RCC_DCKCFGR_PLLDIVR_1 (0x02U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000200 */
+#define RCC_DCKCFGR_PLLDIVR_2 (0x04U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000400 */
+#define RCC_DCKCFGR_PLLDIVR_3 (0x08U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000800 */
+#define RCC_DCKCFGR_PLLDIVR_4 (0x10U << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001000 */
+
+#define RCC_DCKCFGR_CKDFSDM2ASEL_Pos (14U)
+#define RCC_DCKCFGR_CKDFSDM2ASEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM2ASEL_Pos) /*!< 0x00004000 */
+#define RCC_DCKCFGR_CKDFSDM2ASEL RCC_DCKCFGR_CKDFSDM2ASEL_Msk
+#define RCC_DCKCFGR_CKDFSDM1ASEL_Pos (15U)
+#define RCC_DCKCFGR_CKDFSDM1ASEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */
+#define RCC_DCKCFGR_CKDFSDM1ASEL RCC_DCKCFGR_CKDFSDM1ASEL_Msk
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_SAI1A_PLLSOURCE_SUPPORT /*!< SAI1 block A PLL Main source clock support */
+#define RCC_SAI1B_PLLSOURCE_SUPPORT /*!< SAI1 block B PLL Main source clock support */
+
+#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
+#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
+#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
+#define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
+#define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
+#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
+#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
+#define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+#define RCC_DCKCFGR_I2S1SRC_Pos (25U)
+#define RCC_DCKCFGR_I2S1SRC_Msk (0x3U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x06000000 */
+#define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
+#define RCC_DCKCFGR_I2S1SRC_0 (0x1U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x02000000 */
+#define RCC_DCKCFGR_I2S1SRC_1 (0x2U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x04000000 */
+
+#define RCC_DCKCFGR_I2S2SRC_Pos (27U)
+#define RCC_DCKCFGR_I2S2SRC_Msk (0x3U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x18000000 */
+#define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
+#define RCC_DCKCFGR_I2S2SRC_0 (0x1U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x08000000 */
+#define RCC_DCKCFGR_I2S2SRC_1 (0x2U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x10000000 */
+#define RCC_DCKCFGR_CKDFSDM1SEL_Pos (31U)
+#define RCC_DCKCFGR_CKDFSDM1SEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */
+#define RCC_DCKCFGR_CKDFSDM1SEL RCC_DCKCFGR_CKDFSDM1SEL_Msk
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
+#define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
+#define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
+#define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
+#define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
+#define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
+#define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
+#define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1U << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
+#define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
+#define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
+#define RCC_CKGATENR_SPARE_CKEN_Msk (0x1U << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
+#define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
+#define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
+#define RCC_CKGATENR_SRAM_CKEN_Msk (0x1U << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
+#define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
+#define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
+#define RCC_CKGATENR_FLITF_CKEN_Msk (0x1U << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
+#define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
+#define RCC_CKGATENR_RCC_CKEN_Pos (6U)
+#define RCC_CKGATENR_RCC_CKEN_Msk (0x1U << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
+#define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
+#define RCC_CKGATENR_RCC_EVTCTL_Pos (7U)
+#define RCC_CKGATENR_RCC_EVTCTL_Msk (0x1U << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */
+#define RCC_CKGATENR_RCC_EVTCTL RCC_CKGATENR_RCC_EVTCTL_Msk
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
+#define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
+#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
+#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
+#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
+#define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
+#define RCC_DCKCFGR2_SDIOSEL_Msk (0x1U << RCC_DCKCFGR2_SDIOSEL_Pos) /*!< 0x10000000 */
+#define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
+#define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
+#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
+#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
+#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
+#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_Pos (0U)
+#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos (4U)
+#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE_Pos (0U)
+#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos (2U)
+#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos (5U)
+#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
+#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
+#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos (8U)
+#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR_Pos (9U)
+#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN_Pos (10U)
+#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos (12U)
+#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV_Pos (13U)
+#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
+#define SAI_xCR1_SAIEN_Pos (16U)
+#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN_Pos (17U)
+#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
+#define SAI_xCR1_NODIV_Pos (19U)
+#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV_Pos (20U)
+#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH_Pos (0U)
+#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos (3U)
+#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS_Pos (4U)
+#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos (5U)
+#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL_Pos (6U)
+#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT_Pos (7U)
+#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos (13U)
+#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
+
+#define SAI_xCR2_COMP_Pos (14U)
+#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL_Pos (0U)
+#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos (8U)
+#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos (16U)
+#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos (17U)
+#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF_Pos (18U)
+#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF_Pos (0U)
+#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos (8U)
+#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos (16U)
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE_Pos (0U)
+#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE_Pos (1U)
+#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE_Pos (2U)
+#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE_Pos (3U)
+#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE_Pos (4U)
+#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE_Pos (5U)
+#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE_Pos (6U)
+#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR_Pos (0U)
+#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET_Pos (1U)
+#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
+#define SAI_xSR_WCKCFG_Pos (2U)
+#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ_Pos (3U)
+#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
+#define SAI_xSR_CNRDY_Pos (4U)
+#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
+#define SAI_xSR_AFSDET_Pos (5U)
+#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET_Pos (6U)
+#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL_Pos (16U)
+#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR_Pos (0U)
+#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ_Pos (3U)
+#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY_Pos (4U)
+#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET_Pos (5U)
+#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET_Pos (6U)
+#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA_Pos (0U)
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+#define I2S_APB1_APB2_FEATURE /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
+#define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
+#define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/****************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
+#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */
+#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
+#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */
+/****************** Bit definition for SYSCFG_MCHDLYCR register *****************/
+#define SYSCFG_MCHDLYCR_BSCKSEL_Pos (0U)
+#define SYSCFG_MCHDLYCR_BSCKSEL_Msk (0x1U << SYSCFG_MCHDLYCR_BSCKSEL_Pos) /*!< 0x00000001 */
+#define SYSCFG_MCHDLYCR_BSCKSEL SYSCFG_MCHDLYCR_BSCKSEL_Msk /*!<Bitstream clock source selection */
+#define SYSCFG_MCHDLYCR_MCHDLY1EN_Pos (1U)
+#define SYSCFG_MCHDLYCR_MCHDLY1EN_Msk (0x1U << SYSCFG_MCHDLYCR_MCHDLY1EN_Pos) /*!< 0x00000002 */
+#define SYSCFG_MCHDLYCR_MCHDLY1EN SYSCFG_MCHDLYCR_MCHDLY1EN_Msk /*!<MCHDLY clock enable for DFSDM1 */
+#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos (2U)
+#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos) /*!< 0x00000004 */
+#define SYSCFG_MCHDLYCR_DFSDM1D0SEL SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk /*!<Source selection for DatIn0 for DFSDM1 */
+#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos (3U)
+#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos) /*!< 0x00000008 */
+#define SYSCFG_MCHDLYCR_DFSDM1D2SEL SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk /*!<Source selection for DatIn2 for DFSDM1 */
+#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos (4U)
+#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos) /*!< 0x00000010 */
+#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC2 */
+#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos (5U)
+#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos) /*!< 0x00000020 */
+#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC1 */
+#define SYSCFG_MCHDLYCR_DFSDM1CFG_Pos (6U)
+#define SYSCFG_MCHDLYCR_DFSDM1CFG_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CFG_Pos) /*!< 0x00000040 */
+#define SYSCFG_MCHDLYCR_DFSDM1CFG SYSCFG_MCHDLYCR_DFSDM1CFG_Msk /*!<Source selection for DFSDM1 */
+#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos (7U)
+#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos) /*!< 0x00000080 */
+#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk /*!<Source selection for 1_CKOUT */
+#define SYSCFG_MCHDLYCR_MCHDLY2EN_Pos (8U)
+#define SYSCFG_MCHDLYCR_MCHDLY2EN_Msk (0x1U << SYSCFG_MCHDLYCR_MCHDLY2EN_Pos) /*!< 0x00000100 */
+#define SYSCFG_MCHDLYCR_MCHDLY2EN SYSCFG_MCHDLYCR_MCHDLY2EN_Msk /*!<MCHDLY clock enable for DFSDM2 */
+#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos (9U)
+#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos) /*!< 0x00000200 */
+#define SYSCFG_MCHDLYCR_DFSDM2D0SEL SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk /*!<Source selection for DatIn0 for DFSDM2 */
+#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos (10U)
+#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos) /*!< 0x00000400 */
+#define SYSCFG_MCHDLYCR_DFSDM2D2SEL SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk /*!<Source selection for DatIn2 for DFSDM2 */
+#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos (11U)
+#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos) /*!< 0x00000800 */
+#define SYSCFG_MCHDLYCR_DFSDM2D4SEL SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk /*!<Source selection for DatIn4 for DFSDM2 */
+#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos (12U)
+#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos) /*!< 0x00001000 */
+#define SYSCFG_MCHDLYCR_DFSDM2D6SEL SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk /*!<Source selection for DatIn6 for DFSDM2 */
+#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos (13U)
+#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos) /*!< 0x00002000 */
+#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC4 */
+#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos (14U)
+#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos) /*!< 0x00004000 */
+#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC3 */
+#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos (15U)
+#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos) /*!< 0x00008000 */
+#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk /*!Distribution of the bitstreamclock gated by TIM3 OC2 */
+#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos (16U)
+#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos) /*!< 0x00010000 */
+#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC1 */
+#define SYSCFG_MCHDLYCR_DFSDM2CFG_Pos (17U)
+#define SYSCFG_MCHDLYCR_DFSDM2CFG_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CFG_Pos) /*!< 0x00020000 */
+#define SYSCFG_MCHDLYCR_DFSDM2CFG SYSCFG_MCHDLYCR_DFSDM2CFG_Msk /*!<Source selection for DFSDM2 */
+#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos (18U)
+#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk (0x1U << SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos) /*!< 0x00040000 */
+#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk /*!<Source selection for 2_CKOUT */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register *******************/
+#define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
+#define LPTIM_OR_LPT_IN1_RMP_Msk (0x3U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000003 */
+#define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
+#define LPTIM_OR_LPT_IN1_RMP_0 (0x1U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000001 */
+#define LPTIM_OR_LPT_IN1_RMP_1 (0x2U << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000002 */
+#define LPTIM_OR_TIM1_ITR2_RMP_Pos (2U)
+#define LPTIM_OR_TIM1_ITR2_RMP_Msk (0x1U << LPTIM_OR_TIM1_ITR2_RMP_Pos) /*!< 0x00000004 */
+#define LPTIM_OR_TIM1_ITR2_RMP LPTIM_OR_TIM1_ITR2_RMP_Msk /*!< Bit 2 */
+#define LPTIM_OR_TIM5_ITR1_RMP_Pos (3U)
+#define LPTIM_OR_TIM5_ITR1_RMP_Msk (0x1U << LPTIM_OR_TIM5_ITR1_RMP_Pos) /*!< 0x00000008 */
+#define LPTIM_OR_TIM5_ITR1_RMP LPTIM_OR_TIM5_ITR1_RMP_Msk /*!< Bit 3 */
+#define LPTIM_OR_TIM9_ITR1_RMP_Pos (4U)
+#define LPTIM_OR_TIM9_ITR1_RMP_Msk (0x1U << LPTIM_OR_TIM9_ITR1_RMP_Pos) /*!< 0x00000010 */
+#define LPTIM_OR_TIM9_ITR1_RMP LPTIM_OR_TIM9_ITR1_RMP_Msk /*!< Bit 4 */
+
+/* Legacy Defines */
+#define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
+#define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
+#define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos (9U)
+#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (27U)
+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x08000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
+#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDETM_Pos (23U)
+#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_DCDET_Pos (0U)
+#define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos (1U)
+#define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos (2U)
+#define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos (19U)
+#define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos (20U)
+#define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL_Pos (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2) || \
+ ((INSTANCE) == CAN3))
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1) || \
+ ((INSTANCE) == DFSDM2_Filter0) || \
+ ((INSTANCE) == DFSDM2_Filter1) || \
+ ((INSTANCE) == DFSDM2_Filter2) || \
+ ((INSTANCE) == DFSDM2_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3) || \
+ ((INSTANCE) == DFSDM2_Channel0) || \
+ ((INSTANCE) == DFSDM2_Channel1) || \
+ ((INSTANCE) == DFSDM2_Channel2) || \
+ ((INSTANCE) == DFSDM2_Channel3) || \
+ ((INSTANCE) == DFSDM2_Channel4) || \
+ ((INSTANCE) == DFSDM2_Channel5) || \
+ ((INSTANCE) == DFSDM2_Channel6) || \
+ ((INSTANCE) == DFSDM2_Channel7))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+/******************************* LPTIM Instances ******************************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8) || \
+ ((INSTANCE) == UART9) || \
+ ((INSTANCE) == UART10))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8) || \
+ ((INSTANCE) == UART9) || \
+ ((INSTANCE) == UART10))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
+
+#define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F413xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ #define STM32F413xx /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE,
+ SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,362 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 // Connected to B1 [Blue PushButton]
+ {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 // Connected to B1 [Blue PushButton]
+ {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 // Connected to B1 [Blue PushButton]
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to MEMS_INT1 [L3GD20_INT1]
+ {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to MEMS_INT1 [L3GD20_INT1]
+ {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to MEMS_INT1 [L3GD20_INT1]
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to MEMS_INT2 [L3GD20_INT2]
+ {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to MEMS_INT2 [L3GD20_INT2]
+ {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to MEMS_INT2 [L3GD20_INT2]
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to B5
+ {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // Connected to B5
+ {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // Connected to B5
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to VSYNC
+ {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // Connected to VSYNC
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to G2
+ {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // Connected to G2
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to ACP_RST
+ {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to ACP_RST
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to R3
+ {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to R3
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // Connected to R6
+ {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 // Connected to R6
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to SDNWE
+ {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to SDNWE
+ {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 // Connected to SDNWE
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to NCS_MEMS_SPI [L3GD20_CS_I2C/SPI]
+ {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to NCS_MEMS_SPI [L3GD20_CS_I2C/SPI]
+ {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 // Connected to NCS_MEMS_SPI [L3GD20_CS_I2C/SPI]
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Connected to CSX [LCD-RGB_CSX]
+ {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // Connected to CSX [LCD-RGB_CSX]
+ {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 // Connected to CSX [LCD-RGB_CSX]
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
+ {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to OTG_FS_PSO [OTG_FS_PowerSwitchOn]
+ {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to OTG_FS_PSO [OTG_FS_PowerSwitchOn]
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to OTG_FS_OC [OTG_FS_OverCurrent]
+ {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to OTG_FS_OC [OTG_FS_OverCurrent]
+ {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 // Connected to A3
+ {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 // Connected to A4
+ {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 // Connected to A5
+ {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
+ {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 // Connected to SPI5_SCK [L3GD20_SCL/SPC]
+ {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 // Connected to SPI5_MISO [L3GD20_SDO]
+ {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 // Connected to SPI5_MOSI [L3GD20_SDA/SDI/SDO]
+ {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 // Connected to ENABLE [LCD-RGB_ENABLE]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 // Connected to VSYNC
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to B7
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to G5
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to I2C3_SDA [ACP/RF_SDA]
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to A0
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to I2C3_SCL [ACP/RF_SCL]
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to SDNE1 [SDRAM_CS]
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to B6
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to G4
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to A1
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to B1 [Blue PushButton]
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to B1 [Blue PushButton]
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to MEMS_INT1 [L3GD20_INT1]
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to MEMS_INT1 [L3GD20_INT1]
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to MEMS_INT2 [L3GD20_INT2]
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to MEMS_INT2 [L3GD20_INT2]
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to MEMS_INT2 [L3GD20_INT2]
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to B5
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to B5
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // Connected to B5
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to G2
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to G2
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ACP_RST
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ACP_RST
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ACP_RST
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to ACP_RST
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to I2C3_SCL [ACP/RF_SCL]
+// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to STDIO_UART_TX
+// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to STDIO_UART_RX
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to R4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to TP_INT1 [Touch Panel]
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to R3
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to R3
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to R3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to R6
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to R6
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to R6
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SDCKE1
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to SDNE1 [SDRAM_CS]
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to B6
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 // Connected to B6
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to B7
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to B7
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to G4
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to G5
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to VBUS_FS
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to OTG_FS_DM
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to OTG_FS_DM
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to OTG_FS_DM
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to OTG_FS_DP
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to OTG_FS_DP
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 // Connected to OTG_FS_DP
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to HSYNC
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to HSYNC
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to G6
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to G6
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to I2C3_SDA [ACP/RF_SDA]
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to I2C3_SDA [ACP/RF_SDA]
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to RDX [LDC-RGB_RDX]
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to WRX_DCX [LCD-RGB_WRX_DCX]
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to D0
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to D1
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to D5
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to D6
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to D7
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to D8
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to D9
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to D10
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to D11
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to SPI5_SCK [L3GD20_SCL/SPC]
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to SPI5_MISO [L3GD20_SDO]
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to SPI5_MOSI [L3GD20_SDA/SDI/SDO]
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to B1 [Blue PushButton]
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to MEMS_INT2 [L3GD20_INT2]
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SDNE1 [SDRAM_CS]
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to G4
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to HSYNC
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to R2
+ {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to R2
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D13
+ {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to NBL1 [SDRAM_UDQM]
+ {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to D5
+ {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to SPI5_SCK [L3GD20_SCL/SPC]
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to LD4 [Red Led]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to MEMS_INT1 [L3GD20_INT1]
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B5
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to G5
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to G6
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B2
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D14
+ {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to NBL0 [SDRAM_LDQM]
+ {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to D4
+ {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to MEMS_INT1 [L3GD20_INT1]
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to R5
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to OTG_FS_DM
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to RDX [LDC-RGB_RDX]
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to SDCLK
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to B4
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B1 [Blue PushButton]
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to R4
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to VBUS_FS
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to G7
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to TE [LCD-RGB_TE]
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to LD3 [Green Led]
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to SDNCAS
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ACP_RST
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SDCKE1
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDCKE1
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OTG_FS_DP
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to B2
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D11
+ {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to SPI5_MOSI [L3GD20_SDA/SDI/SDO]
+ {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to SDNRAS
+ {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to LD4 [Red Led]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to G2
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OTG_FS_DM
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CSX [LCD-RGB_CSX]
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D10
+ {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to SPI5_MISO [L3GD20_SDO]
+ {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to B4
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to G4
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to VBUS_FS
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to R2
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to G7
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D9
+ {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to SPI5_SCK [L3GD20_SCL/SPC]
+ {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to LD3 [Green Led]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to VSYNC
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to VSYNC
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to TP_INT1 [Touch Panel]
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to TP_INT1 [Touch Panel]
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to B7
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OTG_FS_ID
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D8
+ {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to SDCLK
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to R4
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to SDCKE1
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to B6
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to OTG_FS_ID
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D2
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to R5
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to SDNE1 [SDRAM_CS]
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to B7
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to VBUS_FS
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D3
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,329 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_0_ALT0 = PA_0 | ALT0,
+ PA_0_ALT1 = PA_0 | ALT1,
+ PA_1 = 0x01,
+ PA_1_ALT0 = PA_1 | ALT0,
+ PA_1_ALT1 = PA_1 | ALT1,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_2_ALT1 = PA_2 | ALT1,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_3_ALT1 = PA_3 | ALT1,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_5_ALT1 = PA_5 | ALT1,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_0_ALT0 = PC_0 | ALT0,
+ PC_0_ALT1 = PC_0 | ALT1,
+ PC_1 = 0x21,
+ PC_1_ALT0 = PC_1 | ALT0,
+ PC_1_ALT1 = PC_1 | ALT1,
+ PC_2 = 0x22,
+ PC_2_ALT0 = PC_2 | ALT0,
+ PC_2_ALT1 = PC_2 | ALT1,
+ PC_3 = 0x23,
+ PC_3_ALT0 = PC_3 | ALT0,
+ PC_3_ALT1 = PC_3 | ALT1,
+ PC_4 = 0x24,
+ PC_4_ALT0 = PC_4 | ALT0,
+ PC_5 = 0x25,
+ PC_5_ALT0 = PC_5 | ALT0,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_10_ALT0 = PC_10 | ALT0,
+ PC_11 = 0x2B,
+ PC_11_ALT0 = PC_11 | ALT0,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_9,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_10,
+#endif
+
+ // Generic signals namings
+ LED1 = PG_13, // Corresponds to LD3 on MB1075B
+ LED2 = PG_14, // Corresponds to LD4 on MB1075B
+ LED3 = PG_13,
+ LED4 = PG_14,
+ LED_RED = LED2,
+ USER_BUTTON = PA_0,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_HS_DM = PB_14,
+ USB_OTG_HS_DP = PB_15,
+ USB_OTG_HS_ID = PB_12,
+ USB_OTG_HS_SOF = PA_4,
+ USB_OTG_HS_ULPI_CK = PA_5,
+ USB_OTG_HS_ULPI_D0 = PA_3,
+ USB_OTG_HS_ULPI_D1 = PB_0,
+ USB_OTG_HS_ULPI_D2 = PB_1,
+ USB_OTG_HS_ULPI_D3 = PB_10,
+ USB_OTG_HS_ULPI_D4 = PB_11,
+ USB_OTG_HS_ULPI_D5 = PB_12,
+ USB_OTG_HS_ULPI_D6 = PB_13,
+ USB_OTG_HS_ULPI_D7 = PB_5,
+ USB_OTG_HS_ULPI_DIR = PC_2,
+ USB_OTG_HS_ULPI_NXT = PC_3,
+ USB_OTG_HS_ULPI_STP = PC_0,
+ USB_OTG_HS_VBUS = PB_13,
+
+ /**** ETHERNET pins ****/
+ ETH_COL = PA_3,
+ ETH_CRS = PA_0,
+ ETH_CRS_DV = PA_7,
+ ETH_MDC = PC_1,
+ ETH_MDIO = PA_2,
+ ETH_PPS_OUT = PG_8,
+ ETH_PPS_OUT_ALT0 = PB_5,
+ ETH_REF_CLK = PA_1,
+ ETH_RXD0 = PC_4,
+ ETH_RXD1 = PC_5,
+ ETH_RXD2 = PB_0,
+ ETH_RXD3 = PB_1,
+ ETH_RX_CLK = PA_1,
+ ETH_RX_DV = PA_7,
+ ETH_RX_ER = PB_10,
+ ETH_TXD0 = PB_12,
+ ETH_TXD0_ALT0 = PG_13,
+ ETH_TXD1 = PB_13,
+ ETH_TXD1_ALT0 = PG_14,
+ ETH_TXD2 = PC_2,
+ ETH_TXD3 = PE_2,
+ ETH_TXD3_ALT0 = PB_8,
+ ETH_TX_CLK = PC_3,
+ ETH_TX_EN = PB_11,
+ ETH_TX_EN_ALT0 = PG_11,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED3 = PE_6,
+ SYS_WKUP = PA_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,229 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | CLOCK_SOURCE_USB=1
+ * | 3- USE_PLL_HSI (internal 16 MHz clock) |
+ *-----------------------------------------------------------------------------------
+ * SYSCLK(MHz) | 180 | 168
+ * AHBCLK (MHz) | 180 | 168
+ * APB1CLK (MHz) | 45 | 42
+ * APB2CLK (MHz) | 90 | 84
+ * USB capable (48 MHz) | NO | YES (HSI calibration needed)
+ *-----------------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+
+#include "mbed_error.h"
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 336;
+#else
+ RCC_OscInitStruct.PLL.PLLN = 360;
+#endif
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
+ RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+ return 1;
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 168;
+#else
+ RCC_OscInitStruct.PLL.PLLN = 180;
+#endif
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
+ RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+ return 1;
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE,
+ SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,362 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0
+ {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
+ {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to LD1
+ {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to LD1
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
+ {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC]
+ {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC]
+ {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC]
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+ {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
+ {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to RMII_RXD0 [LAN8742A-CZ-TR_RXD0]
+ {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to RMII_RXD0 [LAN8742A-CZ-TR_RXD0]
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to RMII_RXD1 [LAN8742A-CZ-TR_RXD1]
+ {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to RMII_RXD1 [LAN8742A-CZ-TR_RXD1]
+ {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9
+ {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14
+ {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15
+ {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
+ {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5
+ {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
+ {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
+ {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue]
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to USB_SOF [TP1]
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_SOF [TP1]
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD1
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LD1
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD1
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD2 [Blue]
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LD3 [Red]
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX
+ {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue]
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX
+ {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red]
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to RMII_TXD0 [LAN8742A-CZ-TR_TXD0]
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red]
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to RMII_TXD0 [LAN8742A-CZ-TR_TXD0]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,356 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_0_ALT0 = PA_0 | ALT0,
+ PA_0_ALT1 = PA_0 | ALT1,
+ PA_1 = 0x01,
+ PA_1_ALT0 = PA_1 | ALT0,
+ PA_1_ALT1 = PA_1 | ALT1,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_2_ALT1 = PA_2 | ALT1,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_3_ALT1 = PA_3 | ALT1,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_5_ALT1 = PA_5 | ALT1,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_0_ALT0 = PC_0 | ALT0,
+ PC_0_ALT1 = PC_0 | ALT1,
+ PC_1 = 0x21,
+ PC_1_ALT0 = PC_1 | ALT0,
+ PC_1_ALT1 = PC_1 | ALT1,
+ PC_2 = 0x22,
+ PC_2_ALT0 = PC_2 | ALT0,
+ PC_2_ALT1 = PC_2 | ALT1,
+ PC_3 = 0x23,
+ PC_3_ALT0 = PC_3 | ALT0,
+ PC_3_ALT1 = PC_3 | ALT1,
+ PC_4 = 0x24,
+ PC_4_ALT0 = PC_4 | ALT0,
+ PC_5 = 0x25,
+ PC_5_ALT0 = PC_5 | ALT0,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_10_ALT0 = PC_10 | ALT0,
+ PC_11 = 0x2B,
+ PC_11_ALT0 = PC_11 | ALT0,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_3,
+ A1 = PC_0,
+ A2 = PC_3,
+ A3 = PF_3,
+ A4 = PF_5,
+ A5 = PF_10,
+ D0 = PG_9,
+ D1 = PG_14,
+ D2 = PF_15,
+ D3 = PE_13,
+ D4 = PF_14,
+ D5 = PE_11,
+ D6 = PE_9,
+ D7 = PF_13,
+ D8 = PF_12,
+ D9 = PD_15,
+ D10 = PD_14,
+ D11 = STM32_D11_SPI_ETHERNET_PIN, /* config in targets.json file */
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PD_8,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PD_9,
+#endif
+
+ // Generic signals namings
+ LED1 = PB_0, // LD1 = GREEN
+ LED2 = PB_7, // Blue
+ LED3 = PB_14, // Red
+ LED4 = PB_0,
+ LED_RED = LED3,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX, // Virtual Com Port
+ SERIAL_RX = STDIO_UART_RX, // Virtual Com Port
+ USBTX = STDIO_UART_TX, // Virtual Com Port
+ USBRX = STDIO_UART_RX, // Virtual Com Port
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ PWM_OUT = D9,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_HS_DM = PB_14,
+ USB_OTG_HS_DP = PB_15,
+ USB_OTG_HS_ID = PB_12,
+ USB_OTG_HS_SOF = PA_4,
+ USB_OTG_HS_ULPI_CK = PA_5,
+ USB_OTG_HS_ULPI_D0 = PA_3,
+ USB_OTG_HS_ULPI_D1 = PB_0,
+ USB_OTG_HS_ULPI_D2 = PB_1,
+ USB_OTG_HS_ULPI_D3 = PB_10,
+ USB_OTG_HS_ULPI_D4 = PB_11,
+ USB_OTG_HS_ULPI_D5 = PB_12,
+ USB_OTG_HS_ULPI_D6 = PB_13,
+ USB_OTG_HS_ULPI_D7 = PB_5,
+ USB_OTG_HS_ULPI_DIR = PC_2,
+ USB_OTG_HS_ULPI_NXT = PC_3,
+ USB_OTG_HS_ULPI_STP = PC_0,
+ USB_OTG_HS_VBUS = PB_13,
+
+ /**** ETHERNET pins ****/
+ ETH_COL = PA_3,
+ ETH_CRS = PA_0,
+ ETH_CRS_DV = PA_7,
+ ETH_MDC = PC_1,
+ ETH_MDIO = PA_2,
+ ETH_PPS_OUT = PG_8,
+ ETH_PPS_OUT_ALT0 = PB_5,
+ ETH_REF_CLK = PA_1,
+ ETH_RXD0 = PC_4,
+ ETH_RXD1 = PC_5,
+ ETH_RXD2 = PB_0,
+ ETH_RXD3 = PB_1,
+ ETH_RX_CLK = PA_1,
+ ETH_RX_DV = PA_7,
+ ETH_RX_ER = PB_10,
+ ETH_TXD0 = PB_12,
+ ETH_TXD0_ALT0 = PG_13,
+ ETH_TXD1 = PB_13,
+ ETH_TXD1_ALT0 = PG_14,
+ ETH_TXD2 = PC_2,
+ ETH_TXD3 = PE_2,
+ ETH_TXD3_ALT0 = PB_8,
+ ETH_TX_CLK = PC_3,
+ ETH_TX_EN = PB_11,
+ ETH_TX_EN_ALT0 = PG_11,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED3 = PE_6,
+ SYS_WKUP = PA_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,229 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | CLOCK_SOURCE_USB=1
+ * | 3- USE_PLL_HSI (internal 16 MHz clock) |
+ *-----------------------------------------------------------------------------------
+ * SYSCLK(MHz) | 180 | 168
+ * AHBCLK (MHz) | 180 | 168
+ * APB1CLK (MHz) | 45 | 42
+ * APB2CLK (MHz) | 90 | 84
+ * USB capable (48 MHz) | NO | YES (HSI calibration needed)
+ *-----------------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+
+#include "mbed_error.h"
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 336;
+#else
+ RCC_OscInitStruct.PLL.PLLN = 360;
+#endif
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
+ RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+ return 1;
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 168;
+#else
+ RCC_OscInitStruct.PLL.PLLN = 180;
+#endif
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
+ RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+ return 1;
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,447 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f429xx.s +;* Author : MCD Application Team +;* Description : STM32F429x devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInitPre + IMPORT HAL_InitPre + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInitPre + BLX R0 + LDR R0, =HAL_InitPre + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/stm32f429xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/stm32f429xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,54 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+; 2 MB FLASH (0x200000) + 256 KB SRAM (0x40000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1AC) (0x20000-0x1AC) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,420 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f429xx.s +;* Author : MCD Application Team +;* Description : STM32F429x devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20030000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInitPre + IMPORT HAL_InitPre + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInitPre + BLX R0 + LDR R0, =HAL_InitPre + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,54 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+; 2 MB FLASH (0x200000) + 192 KB SRAM (0x30000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/STM32F429xI.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/STM32F429xI.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,291 @@
+M_VECTOR_RAM_SIZE = 0x400;
+
+/* With the RTOS in use, this does not affect the main stack size. The size of
+ * the stack where main runs is determined via the RTOS. */
+STACK_SIZE = 0x400;
+
+/* This is the guaranteed minimum available heap size for an application. When
+ * uVisor is enabled, this is also the maximum available heap size. The
+ * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
+ * heap and the page heap in uVisor applications. */
+HEAP_SIZE = 0x6000;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 2048k
+#endif
+
+/* Specify the memory areas */
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x400
+ FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192k
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.isr_vector))
+ . = ALIGN(4);
+ } > VECTORS
+
+ /* Note: The uVisor expects this section at a fixed location, as specified
+ * by the porting process configuration parameter:
+ * FLASH_OFFSET. */
+ __UVISOR_FLASH_OFFSET = 0x400;
+ __UVISOR_FLASH_START = ORIGIN(VECTORS) + __UVISOR_FLASH_OFFSET;
+ .text __UVISOR_FLASH_START :
+ {
+ /* uVisor code and data */
+ . = ALIGN(4);
+ __uvisor_main_start = .;
+ *(.uvisor.main)
+ __uvisor_main_end = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .interrupts_ram :
+ {
+ . = ALIGN(4);
+ __VECTOR_RAM__ = .;
+ __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+ *(.m_interrupts_ram) /* This is a user defined section */
+ . += M_VECTOR_RAM_SIZE;
+ . = ALIGN(4);
+ __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+ } > RAM
+
+ /* uVisor own memory and private box memories
+ /* Note: The uVisor expects this section at a fixed location, as specified
+ by the porting process configuration parameter: SRAM_OFFSET. */
+ __UVISOR_SRAM_OFFSET = 0x0;
+ __UVISOR_SRAM_START = ORIGIN(CCM) + __UVISOR_SRAM_OFFSET;
+ .uvisor.bss __UVISOR_SRAM_START (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uvisor_bss_start = .;
+
+ /* Protected uVisor own BSS section */
+ . = ALIGN(32);
+ __uvisor_bss_main_start = .;
+ KEEP(*(.keep.uvisor.bss.main))
+ . = ALIGN(32);
+ __uvisor_bss_main_end = .;
+
+ /* Protected uVisor boxes' static memories */
+ . = ALIGN(32);
+ __uvisor_bss_boxes_start = .;
+ KEEP(*(.keep.uvisor.bss.boxes))
+ . = ALIGN(32);
+ __uvisor_bss_boxes_end = .;
+
+ . = ALIGN(32);
+ __uvisor_bss_end = .;
+ } > CCM
+
+ /* Heap space for the page allocator
+ /* If uVisor shares the SRAM with the OS/app, ensure that this section is
+ * the first one after the uVisor BSS section. Otherwise, ensure it is the
+ * first one after the VTOR relocation section. */
+ .page_heap (NOLOAD) :
+ {
+ . = ALIGN(32);
+ __uvisor_page_start = .;
+ KEEP(*(.keep.uvisor.page_heap))
+ . = ALIGN((1 << LOG2CEIL(LENGTH(RAM))) / 8);
+ __uvisor_page_end = .;
+ } > RAM
+
+ .data :
+ {
+ PROVIDE( __etext = LOADADDR(.data) );
+
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM AT > FLASH
+
+ /* uVisor configuration section
+ * This section must be located after all other flash regions. */
+ .uvisor.secure :
+ {
+ . = ALIGN(32);
+ __uvisor_secure_start = .;
+
+ /* uVisor secure boxes configuration tables */
+ . = ALIGN(32);
+ __uvisor_cfgtbl_start = .;
+ KEEP(*(.keep.uvisor.cfgtbl))
+ . = ALIGN(32);
+ __uvisor_cfgtbl_end = .;
+
+ /* Pointers to the uVisor secure boxes configuration tables */
+ /* Note: Do not add any further alignment here, as uVisor will need to
+ * have access to the exact list of pointers. */
+ __uvisor_cfgtbl_ptr_start = .;
+ KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
+ KEEP(*(.keep.uvisor.cfgtbl_ptr))
+ __uvisor_cfgtbl_ptr_end = .;
+
+ /* Pointers to all boxes register gateways. These are grouped here to
+ allow discoverability and firmware verification. */
+ __uvisor_register_gateway_ptr_start = .;
+ KEEP(*(.keep.uvisor.register_gateway_ptr))
+ __uvisor_register_gateway_ptr_end = .;
+
+ . = ALIGN(32);
+ __uvisor_secure_end = .;
+ } > FLASH
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (NOLOAD):
+ {
+ __uvisor_heap_start = .;
+ __end__ = .;
+ end = __end__;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __uvisor_heap_end = .;
+ } > RAM
+
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __stack = __StackTop;
+ __StackLimit = __StackTop - STACK_SIZE;
+
+ ASSERT(__StackLimit >= __HeapLimit, "Region RAM overflowed with stack and heap")
+
+ /* Provide physical memory boundaries for uVisor. */
+ __uvisor_flash_start = ORIGIN(VECTORS);
+ __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
+ __uvisor_sram_start = ORIGIN(CCM);
+ __uvisor_sram_end = ORIGIN(CCM) + LENGTH(CCM);
+ __uvisor_public_sram_start = ORIGIN(RAM);
+ __uvisor_public_sram_end = ORIGIN(RAM) + LENGTH(RAM);
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,570 @@ +/** + ****************************************************************************** + * @file startup_stm32f429xx.s + * @author MCD Application Team + * @brief STM32F429xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =__stack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInitPre + bl HAL_InitPre +#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED) + ldr r0, =uvisor_init + blx r0 +#endif /* defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED) */ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word __stack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC_IRQHandler */ + .word LTDC_ER_IRQHandler /* LTDC_ER_IRQHandler */ + .word DMA2D_IRQHandler /* DMA2D */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,697 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f429xx.s +;* Author : MCD Application Team +;* Description : STM32F429xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInitPre + EXTERN HAL_InitPre + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInitPre + BLX R0 + LDR R0, =HAL_InitPre + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; }
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x200001AF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200001B0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
+/*-Sizes-*/
+/*Heap 64K and stack 4K */
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x10000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F429ZI +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB +// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM +#define NVIC_NUM_VECTORS 107 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x200000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +/* Base address of the Flash sectors Bank 2 */ +#define ADDR_FLASH_SECTOR_12 ((uint32_t)0x08100000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_13 ((uint32_t)0x08104000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_14 ((uint32_t)0x08108000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_15 ((uint32_t)0x0810C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_16 ((uint32_t)0x08110000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_17 ((uint32_t)0x08120000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_18 ((uint32_t)0x08140000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_19 ((uint32_t)0x08160000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_20 ((uint32_t)0x08180000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_21 ((uint32_t)0x081A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_22 ((uint32_t)0x081C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_23 ((uint32_t)0x081E0000) /* Base @ of Sector 11, 128 Kbytes */ + + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,17133 @@
+/**
+ ******************************************************************************
+ * @file stm32f429xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f429xx
+ * @{
+ */
+
+#ifndef __STM32F429xx_H
+#define __STM32F429xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1;
+ __IO uint32_t MACDBGR;
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
+} LTDC_Layer_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC123_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC123_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2_Pos (8U)
+#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos (9U)
+#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos (10U)
+#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos (11U)
+#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos (12U)
+#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos (13U)
+#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3_Pos (16U)
+#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos (17U)
+#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos (18U)
+#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos (19U)
+#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos (20U)
+#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos (21U)
+#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos (14U)
+#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos (15U)
+#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos (16U)
+#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos (17U)
+#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos (18U)
+#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos (19U)
+#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos (20U)
+#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos (21U)
+#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos (22U)
+#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos (23U)
+#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos (24U)
+#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos (25U)
+#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos (26U)
+#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos (27U)
+#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE_Pos (0U)
+#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos (1U)
+#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
+#define DCMI_CR_CM DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos (2U)
+#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos (3U)
+#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos (4U)
+#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos (5U)
+#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos (6U)
+#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos (7U)
+#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_CRE_Pos (12U)
+#define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
+#define DCMI_CR_CRE DCMI_CR_CRE_Msk
+#define DCMI_CR_ENABLE_Pos (14U)
+#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC_Pos (0U)
+#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos (1U)
+#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos (2U)
+#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS_Pos (0U)
+#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos (1U)
+#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos (2U)
+#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos (4U)
+#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE_Pos (0U)
+#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos (1U)
+#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos (2U)
+#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos (3U)
+#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos (4U)
+#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS_Pos (0U)
+#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos (1U)
+#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos (2U)
+#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos (4U)
+#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC_Pos (0U)
+#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos (1U)
+#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos (2U)
+#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos (4U)
+#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC_Pos (0U)
+#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos (8U)
+#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos (16U)
+#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos (24U)
+#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU_Pos (0U)
+#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos (8U)
+#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos (16U)
+#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos (24U)
+#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos (16U)
+#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos (16U)
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
+
+/******************** Bits definition for DCMI_DR register *********************/
+#define DCMI_DR_BYTE0_Pos (0U)
+#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos (8U)
+#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos (16U)
+#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos (24U)
+#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START_Pos (0U)
+#define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
+#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos (1U)
+#define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
+#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos (2U)
+#define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
+#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
+#define DMA2D_CR_TEIE_Pos (8U)
+#define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
+#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos (9U)
+#define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
+#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos (10U)
+#define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
+#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos (11U)
+#define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos (12U)
+#define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos (13U)
+#define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
+#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos (16U)
+#define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
+#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF_Pos (0U)
+#define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos (1U)
+#define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos (2U)
+#define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos (3U)
+#define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos (4U)
+#define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos (5U)
+#define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos (0U)
+#define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos (1U)
+#define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos (2U)
+#define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos (3U)
+#define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos (4U)
+#define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos (5U)
+#define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA_Pos (0U)
+#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO_Pos (0U)
+#define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA_Pos (0U)
+#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO_Pos (0U)
+#define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM_Pos (0U)
+#define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos (4U)
+#define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos (5U)
+#define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos (8U)
+#define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos (16U)
+#define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos (0U)
+#define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos (8U)
+#define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos (16U)
+#define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM_Pos (0U)
+#define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM_Pos (4U)
+#define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos (5U)
+#define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos (8U)
+#define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos (16U)
+#define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos (0U)
+#define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos (8U)
+#define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos (16U)
+#define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA_Pos (0U)
+#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA_Pos (0U)
+#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM_Pos (0U)
+#define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA_Pos (0U)
+#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO_Pos (0U)
+#define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL_Pos (0U)
+#define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos (16U)
+#define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW_Pos (0U)
+#define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN_Pos (0U)
+#define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos (8U)
+#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_MER2_Pos (15U)
+#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_BFB2_Pos (4U)
+#define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
+#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M_Pos (30U)
+#define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
+#define FLASH_OPTCR_SPRMOD_Pos (31U)
+#define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN_Pos (0U)
+#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN_Pos (1U)
+#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP_Pos (2U)
+#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR1_MWID_Pos (4U)
+#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR1_FACCEN_Pos (6U)
+#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN_Pos (8U)
+#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL_Pos (9U)
+#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD_Pos (10U)
+#define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG_Pos (11U)
+#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR1_WREN_Pos (12U)
+#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR1_WAITEN_Pos (13U)
+#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD_Pos (14U)
+#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE_Pos (16U)
+#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR1_CBURSTRW_Pos (19U)
+#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN_Pos (0U)
+#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN_Pos (1U)
+#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP_Pos (2U)
+#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR2_MWID_Pos (4U)
+#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR2_FACCEN_Pos (6U)
+#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN_Pos (8U)
+#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL_Pos (9U)
+#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD_Pos (10U)
+#define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG_Pos (11U)
+#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR2_WREN_Pos (12U)
+#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR2_WAITEN_Pos (13U)
+#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD_Pos (14U)
+#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR2_CPSIZE_Pos (16U)
+#define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR2_CBURSTRW_Pos (19U)
+#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN_Pos (0U)
+#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN_Pos (1U)
+#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP_Pos (2U)
+#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR3_MWID_Pos (4U)
+#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR3_FACCEN_Pos (6U)
+#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN_Pos (8U)
+#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL_Pos (9U)
+#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD_Pos (10U)
+#define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG_Pos (11U)
+#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR3_WREN_Pos (12U)
+#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR3_WAITEN_Pos (13U)
+#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD_Pos (14U)
+#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR3_CPSIZE_Pos (16U)
+#define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR3_CBURSTRW_Pos (19U)
+#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN_Pos (0U)
+#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN_Pos (1U)
+#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP_Pos (2U)
+#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR4_MWID_Pos (4U)
+#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR4_FACCEN_Pos (6U)
+#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN_Pos (8U)
+#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL_Pos (9U)
+#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD_Pos (10U)
+#define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG_Pos (11U)
+#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR4_WREN_Pos (12U)
+#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR4_WAITEN_Pos (13U)
+#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD_Pos (14U)
+#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR4_CPSIZE_Pos (16U)
+#define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR4_CBURSTRW_Pos (19U)
+#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET_Pos (0U)
+#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR1_ADDHLD_Pos (4U)
+#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR1_DATAST_Pos (8U)
+#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR1_BUSTURN_Pos (16U)
+#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR1_CLKDIV_Pos (20U)
+#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR1_DATLAT_Pos (24U)
+#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR1_ACCMOD_Pos (28U)
+#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET_Pos (0U)
+#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR2_ADDHLD_Pos (4U)
+#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR2_DATAST_Pos (8U)
+#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR2_BUSTURN_Pos (16U)
+#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR2_CLKDIV_Pos (20U)
+#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR2_DATLAT_Pos (24U)
+#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR2_ACCMOD_Pos (28U)
+#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET_Pos (0U)
+#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR3_ADDHLD_Pos (4U)
+#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR3_DATAST_Pos (8U)
+#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR3_BUSTURN_Pos (16U)
+#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR3_CLKDIV_Pos (20U)
+#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR3_DATLAT_Pos (24U)
+#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR3_ACCMOD_Pos (28U)
+#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET_Pos (0U)
+#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR4_ADDHLD_Pos (4U)
+#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR4_DATAST_Pos (8U)
+#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR4_BUSTURN_Pos (16U)
+#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR4_CLKDIV_Pos (20U)
+#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR4_DATLAT_Pos (24U)
+#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR4_ACCMOD_Pos (28U)
+#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET_Pos (0U)
+#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR1_ADDHLD_Pos (4U)
+#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR1_DATAST_Pos (8U)
+#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR1_BUSTURN_Pos (16U)
+#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR1_ACCMOD_Pos (28U)
+#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET_Pos (0U)
+#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR2_ADDHLD_Pos (4U)
+#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR2_DATAST_Pos (8U)
+#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR2_BUSTURN_Pos (16U)
+#define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR2_ACCMOD_Pos (28U)
+#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET_Pos (0U)
+#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR3_ADDHLD_Pos (4U)
+#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR3_DATAST_Pos (8U)
+#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR3_BUSTURN_Pos (16U)
+#define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR3_ACCMOD_Pos (28U)
+#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET_Pos (0U)
+#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR4_ADDHLD_Pos (4U)
+#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR4_DATAST_Pos (8U)
+#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR4_BUSTURN_Pos (16U)
+#define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR4_ACCMOD_Pos (28U)
+#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+
+#define FMC_PCR2_PWAITEN_Pos (1U)
+#define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN_Pos (2U)
+#define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP_Pos (3U)
+#define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR2_PWID_Pos (4U)
+#define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR2_ECCEN_Pos (6U)
+#define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR_Pos (9U)
+#define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR2_TAR_Pos (13U)
+#define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR2_ECCPS_Pos (17U)
+#define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN_Pos (1U)
+#define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN_Pos (2U)
+#define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP_Pos (3U)
+#define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR3_PWID_Pos (4U)
+#define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR3_ECCEN_Pos (6U)
+#define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR_Pos (9U)
+#define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR3_TAR_Pos (13U)
+#define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR3_ECCPS_Pos (17U)
+#define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN_Pos (1U)
+#define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN_Pos (2U)
+#define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP_Pos (3U)
+#define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR4_PWID_Pos (4U)
+#define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR4_ECCEN_Pos (6U)
+#define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR_Pos (9U)
+#define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR4_TAR_Pos (13U)
+#define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR4_ECCPS_Pos (17U)
+#define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS_Pos (0U)
+#define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS_Pos (1U)
+#define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR2_IFS_Pos (2U)
+#define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN_Pos (3U)
+#define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN_Pos (4U)
+#define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN_Pos (5U)
+#define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT_Pos (6U)
+#define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS_Pos (0U)
+#define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS_Pos (1U)
+#define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR3_IFS_Pos (2U)
+#define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN_Pos (3U)
+#define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN_Pos (4U)
+#define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN_Pos (5U)
+#define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT_Pos (6U)
+#define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS_Pos (0U)
+#define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS_Pos (1U)
+#define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR4_IFS_Pos (2U)
+#define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN_Pos (3U)
+#define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN_Pos (4U)
+#define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN_Pos (5U)
+#define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT_Pos (6U)
+#define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2_Pos (0U)
+#define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
+#define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
+#define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
+#define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
+#define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
+#define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
+#define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
+#define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
+#define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM2_MEMWAIT2_Pos (8U)
+#define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM2_MEMHOLD2_Pos (16U)
+#define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM2_MEMHIZ2_Pos (24U)
+#define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3_Pos (0U)
+#define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
+#define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
+#define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
+#define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
+#define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
+#define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
+#define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
+#define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
+#define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM3_MEMWAIT3_Pos (8U)
+#define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
+#define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
+#define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
+#define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
+#define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
+#define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
+#define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
+#define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM3_MEMHOLD3_Pos (16U)
+#define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
+#define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
+#define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
+#define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
+#define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
+#define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
+#define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
+#define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM3_MEMHIZ3_Pos (24U)
+#define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
+#define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
+#define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
+#define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
+#define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
+#define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
+#define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
+#define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4_Pos (0U)
+#define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
+#define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
+#define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
+#define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
+#define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
+#define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
+#define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
+#define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
+#define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM4_MEMWAIT4_Pos (8U)
+#define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM4_MEMHOLD4_Pos (16U)
+#define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM4_MEMHIZ4_Pos (24U)
+#define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2_Pos (0U)
+#define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
+#define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
+#define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
+#define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
+#define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
+#define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
+#define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
+#define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
+#define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT2_ATTWAIT2_Pos (8U)
+#define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT2_ATTHOLD2_Pos (16U)
+#define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT2_ATTHIZ2_Pos (24U)
+#define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3_Pos (0U)
+#define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
+#define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
+#define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
+#define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
+#define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
+#define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
+#define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
+#define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
+#define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT3_ATTWAIT3_Pos (8U)
+#define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
+#define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
+#define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
+#define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
+#define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
+#define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
+#define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
+#define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT3_ATTHOLD3_Pos (16U)
+#define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
+#define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
+#define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
+#define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
+#define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
+#define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
+#define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
+#define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT3_ATTHIZ3_Pos (24U)
+#define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
+#define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
+#define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
+#define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
+#define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
+#define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
+#define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
+#define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
+#define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4_Pos (0U)
+#define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
+#define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
+#define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
+#define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
+#define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
+#define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
+#define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
+#define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
+#define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT4_ATTWAIT4_Pos (8U)
+#define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT4_ATTHOLD4_Pos (16U)
+#define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT4_ATTHIZ4_Pos (24U)
+#define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4_Pos (0U)
+#define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PIO4_IOWAIT4_Pos (8U)
+#define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PIO4_IOHOLD4_Pos (16U)
+#define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PIO4_IOHIZ4_Pos (24U)
+#define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2_Pos (0U)
+#define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3_Pos (0U)
+#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC_Pos (0U)
+#define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR1_NR_Pos (2U)
+#define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR1_MWID_Pos (4U)
+#define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR1_NB_Pos (6U)
+#define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS_Pos (7U)
+#define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR1_WP_Pos (9U)
+#define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK_Pos (10U)
+#define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR1_RBURST_Pos (12U)
+#define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE_Pos (13U)
+#define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC_Pos (0U)
+#define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR2_NR_Pos (2U)
+#define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR2_MWID_Pos (4U)
+#define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR2_NB_Pos (6U)
+#define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS_Pos (7U)
+#define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR2_WP_Pos (9U)
+#define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK_Pos (10U)
+#define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR2_RBURST_Pos (12U)
+#define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE_Pos (13U)
+#define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD_Pos (0U)
+#define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR1_TXSR_Pos (4U)
+#define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR1_TRAS_Pos (8U)
+#define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR1_TRC_Pos (12U)
+#define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR1_TWR_Pos (16U)
+#define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR1_TRP_Pos (20U)
+#define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR1_TRCD_Pos (24U)
+#define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD_Pos (0U)
+#define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR2_TXSR_Pos (4U)
+#define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR2_TRAS_Pos (8U)
+#define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR2_TRC_Pos (12U)
+#define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR2_TWR_Pos (16U)
+#define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR2_TRP_Pos (20U)
+#define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR2_TRCD_Pos (24U)
+#define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE_Pos (0U)
+#define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
+#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
+
+#define FMC_SDCMR_CTB2_Pos (3U)
+#define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos (4U)
+#define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos (5U)
+#define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos (9U)
+#define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE_Pos (0U)
+#define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
+#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos (1U)
+#define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos (14U)
+#define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE_Pos (0U)
+#define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
+#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos (1U)
+#define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
+#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos (3U)
+#define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
+#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
+#define FMC_SDSR_BUSY_Pos (5U)
+#define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
+#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH_Pos (0U)
+#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
+#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW_Pos (16U)
+#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP_Pos (0U)
+#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP_Pos (16U)
+#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH_Pos (0U)
+#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW_Pos (16U)
+#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH_Pos (0U)
+#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW_Pos (16U)
+#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN_Pos (0U)
+#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW_Pos (4U)
+#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
+#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
+#define LTDC_GCR_DGW_Pos (8U)
+#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
+#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
+#define LTDC_GCR_DRW_Pos (12U)
+#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
+#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
+#define LTDC_GCR_DEN_Pos (16U)
+#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
+#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
+#define LTDC_GCR_PCPOL_Pos (28U)
+#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL_Pos (29U)
+#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL_Pos (30U)
+#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL_Pos (31U)
+#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN LTDC_GCR_DEN
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR_Pos (0U)
+#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
+#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
+#define LTDC_SRCR_VBR_Pos (1U)
+#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
+#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos (0U)
+#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN_Pos (8U)
+#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos (16U)
+#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE_Pos (0U)
+#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
+#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE_Pos (1U)
+#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
+#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE_Pos (2U)
+#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
+#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE_Pos (3U)
+#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
+#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF_Pos (0U)
+#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
+#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos (1U)
+#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
+#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos (2U)
+#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos (3U)
+#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
+#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF_Pos (0U)
+#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
+#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos (1U)
+#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos (2U)
+#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos (3U)
+#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos (0U)
+#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS_Pos (0U)
+#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos (16U)
+#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES_Pos (0U)
+#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
+#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES_Pos (1U)
+#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
+#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS_Pos (2U)
+#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS_Pos (3U)
+#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN_Pos (0U)
+#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
+#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN_Pos (1U)
+#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN_Pos (4U)
+#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN_Pos (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos (16U)
+#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF_Pos (0U)
+#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos (0U)
+#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN_Pos (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos (16U)
+#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA_Pos (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2_Pos (0U)
+#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos (8U)
+#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP_Pos (16U)
+#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN_Pos (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
+#define LTDC_LxCLUTWR_RED_Pos (16U)
+#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN_Pos (16U)
+#define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
+#define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
+#define PWR_CR_ODSWEN_Pos (17U)
+#define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
+#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN_Pos (18U)
+#define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
+#define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
+#define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY_Pos (16U)
+#define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
+#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY_Pos (17U)
+#define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
+#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
+#define PWR_CSR_UDRDY_Pos (18U)
+#define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
+#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
+/* Legacy define */
+#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
+
+#define RCC_CR_PLLSAION_Pos (28U)
+#define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
+#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
+#define RCC_CR_PLLSAIRDY_Pos (29U)
+#define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
+#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_PLLSAIRDYF_Pos (6U)
+#define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
+#define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
+#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+#define RCC_CIR_PLLSAIRDYC_Pos (22U)
+#define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
+#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
+#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
+#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
+#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
+#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
+#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
+#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
+#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
+#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
+#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
+#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
+#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
+#define RCC_APB1RSTR_UART7RST_Pos (30U)
+#define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
+#define RCC_APB1RSTR_UART8RST_Pos (31U)
+#define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SPI6RST_Pos (21U)
+#define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_LTDCRST_Pos (26U)
+#define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
+#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
+#define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
+#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
+#define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
+#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
+#define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
+#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
+#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
+#define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
+#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
+#define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
+#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
+#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
+#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
+#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
+#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
+#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
+#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_DCMIEN_Pos (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos (6U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FMCEN_Pos (0U)
+#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
+#define RCC_APB1ENR_UART7EN_Pos (30U)
+#define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
+#define RCC_APB1ENR_UART8EN_Pos (31U)
+#define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (1U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_ADC2EN_Pos (9U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
+#define RCC_APB2ENR_ADC3EN_Pos (10U)
+#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SPI6EN_Pos (21U)
+#define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
+#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos (22U)
+#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_LTDCEN_Pos (26U)
+#define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
+#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
+#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
+#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
+#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
+#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
+#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
+#define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
+#define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
+#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
+
+#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
+#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
+#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
+#define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
+#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
+#define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
+#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
+#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
+#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
+#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
+#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
+#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
+
+
+#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
+#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
+#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
+
+#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
+#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
+#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
+#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
+#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
+#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
+#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
+
+#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
+#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
+#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
+#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
+#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
+#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
+#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
+
+#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
+#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
+#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
+#define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
+#define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
+#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
+#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
+#define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
+#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_Pos (0U)
+#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos (4U)
+#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE_Pos (0U)
+#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos (2U)
+#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos (5U)
+#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
+#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
+#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos (8U)
+#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR_Pos (9U)
+#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN_Pos (10U)
+#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos (12U)
+#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV_Pos (13U)
+#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
+#define SAI_xCR1_SAIEN_Pos (16U)
+#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN_Pos (17U)
+#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
+#define SAI_xCR1_NODIV_Pos (19U)
+#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV_Pos (20U)
+#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH_Pos (0U)
+#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos (3U)
+#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS_Pos (4U)
+#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos (5U)
+#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL_Pos (6U)
+#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT_Pos (7U)
+#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos (13U)
+#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
+
+#define SAI_xCR2_COMP_Pos (14U)
+#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL_Pos (0U)
+#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos (8U)
+#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos (16U)
+#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos (17U)
+#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF_Pos (18U)
+#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF_Pos (0U)
+#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos (8U)
+#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos (16U)
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE_Pos (0U)
+#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE_Pos (1U)
+#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE_Pos (2U)
+#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE_Pos (3U)
+#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE_Pos (4U)
+#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE_Pos (5U)
+#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE_Pos (6U)
+#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR_Pos (0U)
+#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET_Pos (1U)
+#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
+#define SAI_xSR_WCKCFG_Pos (2U)
+#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ_Pos (3U)
+#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
+#define SAI_xSR_CNRDY_Pos (4U)
+#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
+#define SAI_xSR_AFSDET_Pos (5U)
+#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET_Pos (6U)
+#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL_Pos (16U)
+#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR_Pos (0U)
+#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ_Pos (3U)
+#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY_Pos (4U)
+#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET_Pos (5U)
+#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET_Pos (6U)
+#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA_Pos (0U)
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
+#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
+#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
+#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
+#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
+/* Legacy Defines */
+#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2_Pos (16U)
+#define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
+#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2_Pos (17U)
+#define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
+#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2_Pos (18U)
+#define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
+#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
+#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD_Pos (23U)
+#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
+#define ETH_MACCR_JD_Pos (22U)
+#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
+#define ETH_MACCR_IFG_Pos (17U)
+#define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
+#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD_Pos (16U)
+#define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES_Pos (14U)
+#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
+#define ETH_MACCR_ROD_Pos (13U)
+#define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
+#define ETH_MACCR_LM_Pos (12U)
+#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
+#define ETH_MACCR_DM_Pos (11U)
+#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
+#define ETH_MACCR_IPCO_Pos (10U)
+#define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
+#define ETH_MACCR_RD_Pos (9U)
+#define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
+#define ETH_MACCR_APCS_Pos (7U)
+#define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
+#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL_Pos (5U)
+#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC_Pos (4U)
+#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
+#define ETH_MACCR_TE_Pos (3U)
+#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
+#define ETH_MACCR_RE_Pos (2U)
+#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA_Pos (31U)
+#define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
+#define ETH_MACFFR_HPF_Pos (10U)
+#define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
+#define ETH_MACFFR_SAF_Pos (9U)
+#define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
+#define ETH_MACFFR_SAIF_Pos (8U)
+#define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
+#define ETH_MACFFR_PCF_Pos (6U)
+#define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
+#define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
+#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
+#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
+#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD_Pos (5U)
+#define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
+#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
+#define ETH_MACFFR_PAM_Pos (4U)
+#define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
+#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF_Pos (3U)
+#define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
+#define ETH_MACFFR_HM_Pos (2U)
+#define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
+#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
+#define ETH_MACFFR_HU_Pos (1U)
+#define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
+#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
+#define ETH_MACFFR_PM_Pos (0U)
+#define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
+#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos (0U)
+#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos (0U)
+#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA_Pos (11U)
+#define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
+#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
+#define ETH_MACMIIAR_MR_Pos (6U)
+#define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
+#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR_Pos (2U)
+#define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
+#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
+#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIAR_CR_Div62_Pos (2U)
+#define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
+#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define ETH_MACMIIAR_CR_Div16_Pos (3U)
+#define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
+#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ETH_MACMIIAR_CR_Div26_Pos (2U)
+#define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
+#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_CR_Div102_Pos (4U)
+#define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
+#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW_Pos (1U)
+#define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
+#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
+#define ETH_MACMIIAR_MB_Pos (0U)
+#define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD_Pos (0U)
+#define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT_Pos (16U)
+#define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
+#define ETH_MACFCR_ZQPD_Pos (7U)
+#define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
+#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT_Pos (4U)
+#define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+#define ETH_MACFCR_PLT_Minus28_Pos (4U)
+#define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
+#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACFCR_PLT_Minus144_Pos (5U)
+#define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
+#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256_Pos (4U)
+#define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD_Pos (3U)
+#define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
+#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE_Pos (2U)
+#define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
+#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
+#define ETH_MACFCR_TFCE_Pos (1U)
+#define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
+#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA_Pos (0U)
+#define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
+#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC_Pos (16U)
+#define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
+#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI_Pos (0U)
+#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D_Pos (0U)
+#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
+#define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
+#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU_Pos (9U)
+#define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
+#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
+#define ETH_MACPMTCSR_WFR_Pos (6U)
+#define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
+#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR_Pos (5U)
+#define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
+#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE_Pos (2U)
+#define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
+#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE_Pos (1U)
+#define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
+#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD_Pos (0U)
+#define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
+#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
+
+/* Bit definition for Ethernet MAC debug Register */
+#define ETH_MACDBGR_TFF_Pos (25U)
+#define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
+#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
+#define ETH_MACDBGR_TFNE_Pos (24U)
+#define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
+#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
+#define ETH_MACDBGR_TFWA_Pos (22U)
+#define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
+#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
+#define ETH_MACDBGR_TFRS_Pos (20U)
+#define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
+#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
+#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
+#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
+#define ETH_MACDBGR_TFRS_READ_Pos (20U)
+#define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
+#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
+#define ETH_MACDBGR_MTP_Pos (19U)
+#define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
+#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
+#define ETH_MACDBGR_MTFCS_Pos (17U)
+#define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
+#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
+#define ETH_MACDBGR_MMTEA_Pos (16U)
+#define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
+#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
+#define ETH_MACDBGR_RFFL_Pos (8U)
+#define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
+#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
+#define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
+#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
+#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
+#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
+#define ETH_MACDBGR_RFRCS_Pos (5U)
+#define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
+#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
+#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
+#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
+#define ETH_MACDBGR_RFWRA_Pos (4U)
+#define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
+#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
+#define ETH_MACDBGR_MSFRWCS_Pos (1U)
+#define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
+#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
+#define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
+#define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
+#define ETH_MACDBGR_MMRPEA_Pos (0U)
+#define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
+#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS_Pos (9U)
+#define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
+#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS_Pos (6U)
+#define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
+#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
+#define ETH_MACSR_MMMCRS_Pos (5U)
+#define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
+#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
+#define ETH_MACSR_MMCS_Pos (4U)
+#define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
+#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
+#define ETH_MACSR_PMTS_Pos (3U)
+#define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
+#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM_Pos (9U)
+#define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
+#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM_Pos (3U)
+#define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
+#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H_Pos (0U)
+#define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L_Pos (0U)
+#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE_Pos (31U)
+#define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
+#define ETH_MACA1HR_SA_Pos (30U)
+#define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
+#define ETH_MACA1HR_MBC_Pos (24U)
+#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H_Pos (0U)
+#define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L_Pos (0U)
+#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE_Pos (31U)
+#define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
+#define ETH_MACA2HR_SA_Pos (30U)
+#define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
+#define ETH_MACA2HR_MBC_Pos (24U)
+#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H_Pos (0U)
+#define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L_Pos (0U)
+#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE_Pos (31U)
+#define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
+#define ETH_MACA3HR_SA_Pos (30U)
+#define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
+#define ETH_MACA3HR_MBC_Pos (24U)
+#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H_Pos (0U)
+#define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L_Pos (0U)
+#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP_Pos (5U)
+#define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP_Pos (4U)
+#define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
+#define ETH_MMCCR_MCF_Pos (3U)
+#define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR_Pos (2U)
+#define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
+#define ETH_MMCCR_CSR_Pos (1U)
+#define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
+#define ETH_MMCCR_CR_Pos (0U)
+#define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS_Pos (17U)
+#define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES_Pos (6U)
+#define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES_Pos (5U)
+#define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS_Pos (21U)
+#define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS_Pos (15U)
+#define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS_Pos (14U)
+#define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM_Pos (17U)
+#define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM_Pos (6U)
+#define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM_Pos (5U)
+#define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM_Pos (21U)
+#define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
+#define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM_Pos (14U)
+#define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
+#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC_Pos (0U)
+#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC_Pos (0U)
+#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC_Pos (0U)
+#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
+#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT_Pos (16U)
+#define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
+#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME_Pos (15U)
+#define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME_Pos (14U)
+#define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
+#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
+#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
+#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
+#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
+#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
+#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
+#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
+#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
+#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR_Pos (9U)
+#define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
+#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE_Pos (8U)
+#define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
+#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU_Pos (5U)
+#define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
+#define ETH_PTPTSCR_TSITE_Pos (4U)
+#define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU_Pos (3U)
+#define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
+#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI_Pos (2U)
+#define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
+#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU_Pos (1U)
+#define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
+#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE_Pos (0U)
+#define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
+#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI_Pos (0U)
+#define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
+#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS_Pos (0U)
+#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS_Pos (31U)
+#define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS_Pos (0U)
+#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS_Pos (0U)
+#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
+#define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS_Pos (0U)
+#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA_Pos (0U)
+#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH_Pos (0U)
+#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL_Pos (0U)
+#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR_Pos (5U)
+#define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO_Pos (4U)
+#define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB_Pos (25U)
+#define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
+#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
+#define ETH_DMABMR_FPM_Pos (24U)
+#define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
+#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
+#define ETH_DMABMR_USP_Pos (23U)
+#define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
+#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
+#define ETH_DMABMR_RDP_Pos (17U)
+#define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
+#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
+#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB_Pos (16U)
+#define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
+#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
+#define ETH_DMABMR_RTPR_Pos (14U)
+#define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
+#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL_Pos (8U)
+#define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
+#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
+#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE_Pos (7U)
+#define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
+#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL_Pos (2U)
+#define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
+#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
+#define ETH_DMABMR_DA_Pos (1U)
+#define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
+#define ETH_DMABMR_SR_Pos (0U)
+#define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD_Pos (0U)
+#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD_Pos (0U)
+#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL_Pos (0U)
+#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL_Pos (0U)
+#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS_Pos (29U)
+#define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
+#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS_Pos (28U)
+#define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
+#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
+#define ETH_DMASR_MMCS_Pos (27U)
+#define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
+#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
+#define ETH_DMASR_EBS_Pos (23U)
+#define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
+#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+#define ETH_DMASR_EBS_DescAccess_Pos (25U)
+#define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
+#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
+#define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
+#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
+#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
+#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS_Pos (20U)
+#define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
+#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMASR_TPS_Fetching_Pos (20U)
+#define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
+#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
+#define ETH_DMASR_TPS_Waiting_Pos (21U)
+#define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
+#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
+#define ETH_DMASR_TPS_Reading_Pos (20U)
+#define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
+#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
+#define ETH_DMASR_TPS_Suspended_Pos (21U)
+#define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
+#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
+#define ETH_DMASR_TPS_Closing_Pos (20U)
+#define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS_Pos (17U)
+#define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
+#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Fetching_Pos (17U)
+#define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
+#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
+#define ETH_DMASR_RPS_Waiting_Pos (17U)
+#define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
+#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
+#define ETH_DMASR_RPS_Suspended_Pos (19U)
+#define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
+#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
+#define ETH_DMASR_RPS_Closing_Pos (17U)
+#define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
+#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
+#define ETH_DMASR_RPS_Queuing_Pos (17U)
+#define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS_Pos (16U)
+#define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
+#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
+#define ETH_DMASR_AIS_Pos (15U)
+#define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
+#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS_Pos (14U)
+#define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
+#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
+#define ETH_DMASR_FBES_Pos (13U)
+#define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
+#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
+#define ETH_DMASR_ETS_Pos (10U)
+#define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
+#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
+#define ETH_DMASR_RWTS_Pos (9U)
+#define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
+#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS_Pos (8U)
+#define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
+#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
+#define ETH_DMASR_RBUS_Pos (7U)
+#define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
+#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
+#define ETH_DMASR_RS_Pos (6U)
+#define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
+#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
+#define ETH_DMASR_TUS_Pos (5U)
+#define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
+#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
+#define ETH_DMASR_ROS_Pos (4U)
+#define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
+#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
+#define ETH_DMASR_TJTS_Pos (3U)
+#define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
+#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS_Pos (2U)
+#define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
+#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS_Pos (1U)
+#define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
+#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
+#define ETH_DMASR_TS_Pos (0U)
+#define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
+#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD_Pos (26U)
+#define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
+#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF_Pos (25U)
+#define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
+#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
+#define ETH_DMAOMR_DFRF_Pos (24U)
+#define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
+#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF_Pos (21U)
+#define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
+#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
+#define ETH_DMAOMR_FTF_Pos (20U)
+#define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
+#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC_Pos (14U)
+#define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
+#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
+#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST_Pos (13U)
+#define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
+#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF_Pos (7U)
+#define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
+#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
+#define ETH_DMAOMR_FUGF_Pos (6U)
+#define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
+#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC_Pos (3U)
+#define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
+#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
+#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF_Pos (2U)
+#define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
+#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
+#define ETH_DMAOMR_SR_Pos (1U)
+#define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
+#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE_Pos (16U)
+#define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
+#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE_Pos (15U)
+#define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
+#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE_Pos (14U)
+#define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE_Pos (13U)
+#define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
+#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE_Pos (10U)
+#define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE_Pos (9U)
+#define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
+#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE_Pos (8U)
+#define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
+#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE_Pos (7U)
+#define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
+#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE_Pos (6U)
+#define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE_Pos (5U)
+#define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
+#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE_Pos (4U)
+#define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
+#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE_Pos (3U)
+#define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
+#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE_Pos (2U)
+#define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
+#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE_Pos (1U)
+#define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
+#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE_Pos (0U)
+#define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC_Pos (28U)
+#define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
+#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA_Pos (17U)
+#define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
+#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC_Pos (16U)
+#define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
+#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC_Pos (0U)
+#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
+#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP_Pos (0U)
+#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP_Pos (0U)
+#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP_Pos (0U)
+#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP_Pos (0U)
+#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
+#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
+
+#define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
+#define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+#define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F429xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ #define STM32F429xx /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/system_init_pre.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/system_init_pre.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015-2015, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "stm32f4xx.h"
+#include "nvic_addr.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* note: if uVisor is present the definition must go in system_init_pre.c */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+/* this function is needed to peform hardware initialization that must happen
+ * before the uVisor; the whole SystemInit function for the STM32F4 cannot be
+ * put here as it depends on some APIs that need uVisor to be enabled */
+void SystemInitPre(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,100 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int) ADC2_BASE,
+ ADC_3 = (int) ADC3_BASE
+} ADCName;
+
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE,
+ SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,138 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_DAC[] = {
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 - ARDUINO D13
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+const PinMap PinMap_PWM[] = {
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1N
+ {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,195 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03,
+ PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07,
+ PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B,
+ PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F,
+
+ PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13,
+ PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17,
+ PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B,
+ PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F,
+
+ PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23,
+ PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27,
+ PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B,
+ PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F,
+
+ PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33,
+ PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37,
+ PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B,
+ PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F,
+
+ PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43,
+ PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47,
+ PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B,
+ PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F,
+
+
+ PH_0 = 0x70, PH_1 = 0x71,
+
+ // Not connected
+ NC = -1,
+
+ // Power
+ PWR3V3 = PE_0, // 3.3V rail for the Arduino interface,
+ // user LEDs and GNSS power, should be
+ // set to open drain output
+
+ // GNSS
+ GNSSEN = PA_15, // VCC_IO to GNSS, should be set to push-pull, no pull-up, output
+ GNSSTXD = PC_6,
+ GNSSRXD = PC_7,
+
+ // Cellular modem (a DCE)
+ MDMPWRON = PE_14, // Power (active high)
+ MDMRST = PB_5, // Reset (active low)
+#if defined(TARGET_UBLOX_C030_R410M)
+ MDMTXD = PA_9, // Transmit Data
+ MDMRXD = PA_10, // Receive Data
+ MDMCTS = PA_11, // Clear to Send
+ MDMRTS = PA_12, // Request to Send
+#else
+ MDMTXD = PD_5, // Transmit Data
+ MDMRXD = PD_6, // Receive Data
+ MDMCTS = PD_3, // Clear to Send
+ MDMRTS = PD_4, // Request to Send
+#endif
+ MDMDCD = NC, // DCD line not connected
+ MDMDSR = NC, // DSR line not connected
+ MDMDTR = NC, // DTR line not connected
+ MDMRI = NC, // RI line not connected
+ MDMGPIO2 = PD_1, //
+ MDMGPIO3 = PB_4, //
+ MDMCURRENTSENSE = PC_2,
+
+ // SD card
+ SDPWRON = PE_10, // Set to high to power on the SD card
+ SDCSEL = PD_7, // SPI chip select for on-board SD card
+
+ // Board Pins
+ // A0-A5
+ A0 = PA_3,
+ A1 = PC_0,
+ A2 = PC_3,
+ A3 = PA_4,
+ A4 = PA_6,
+ A5 = PB_0,
+ // D0-D15
+ D0 = PD_9, // UART3-RX
+ D1 = PD_8, // UART3-TX
+ D2 = PD_11, // UART3-CTS
+ D3 = PB_14, // UART3-RTS
+ D4 = PB_1,
+ D5 = PA_5,
+ D6 = PB_8, // UART3-CTS
+ D7 = PB_15, // UART3-RTS
+ D8 = PD_15, // UART1-TX
+ D9 = PD_12, // SDCard-CS
+ D10 = PE_11, // SSEL
+ D11 = PE_6, // MOSI
+ D12 = PE_5, // MISO
+ D13 = PE_2, // SCK
+ D14 = PB_7, // SDA
+ D15 = PB_6, // SCL
+ // Internal
+ LED1 = PE_3, // Red / Mode
+ LED2 = PE_4, // Green / Switch-1
+ LED3 = PE_1, // Blue
+ LED4 = PE_7, // A definition is required by the mbed platform RTC test code, this is the Ethernet connector yellow LED
+ LED_RED = LED1,
+ SW0 = PC_13, // Switch-0
+
+ // Arduino header I2C
+ I2C_SDA = D14,
+ I2C_SCL = D15,
+
+ // On-board I2C
+ I2C_SDA_B = PC_9,
+ I2C_SCL_B = PA_8,
+
+ // SPI
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_CLK = D13,
+ SPI_NSS = D10,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+#if defined(TARGET_UBLOX_C030_R410M)
+ STDIO_UART_TX = PD_5,
+#else
+ STDIO_UART_TX = PA_9,
+#endif
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+#if defined(TARGET_UBLOX_C030_R410M)
+ STDIO_UART_RX = PD_6,
+#else
+ STDIO_UART_RX = PA_10,
+#endif
+#endif
+
+ // ST-Link
+ USBRX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ SWDIO = PA_13,
+ SWCLK = PA_14,
+ NTRST = PB_4,
+} PinName;
+
+#define ACTIVE_HIGH_POLARITY 1
+#define ACTIVE_LOW_POLARITY 0
+
+#define MDM_PIN_POLARITY ACTIVE_LOW_POLARITY
+
+// The default GNSS baud rate is set in targets.json
+// The default modem baud rate is set in the mbed_lib.json file under features/cellular/TARGET_UBLOX_MODEM_GENERIC/ubox_modem_driver
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "min_battery_voltage.h"
+
+/** Defining HAL_MspInit strong function
+ * in user defined file as described in documentation
+ */
+
+void HAL_MspInit(void)
+{
+ set_minimum_battery_voltage();
+}
+
+void set_minimum_battery_voltage()
+{
+ i2c_t i2c_obj = {0};
+ int data_read;
+ i2c_init(&i2c_obj, I2C_SDA_B, I2C_SCL_B);
+ i2c_frequency(&i2c_obj, I2C_FREQUENCY);
+
+ if (read_from_i2c(BQ24295_I2C_ADDRESS, 0, &data_read, i2c_obj)) {
+ data_read = data_read & MIN_BATTERY_VOLTAGE_MASK;
+ write_to_i2c(BQ24295_I2C_ADDRESS, 0, data_read, i2c_obj);
+ //Battery Voltage is set to 3880mV
+ } else {
+ // Minimum battery voltage could not be set. This is not a critical error, no need to stop execution
+ // It simply means that longer cabling or USB ports with lower output voltages may cause problems.
+ }
+}
+
+char write_to_i2c(int slave_addr, int reg_addr, int data_write, i2c_t i2c_obj)
+{
+ char ret_code = 0;
+ if (!i2c_start(&i2c_obj)) {
+ if ((i2c_byte_write(&i2c_obj, slave_addr << 1) == 1) &&
+ (i2c_byte_write(&i2c_obj, reg_addr) == 1) &&
+ (i2c_byte_write(&i2c_obj,data_write) ==1)) {
+ ret_code = 1;
+ }
+ i2c_stop(&i2c_obj);
+ }
+ return ret_code;
+}
+
+char read_from_i2c(int slave_addr, int reg_addr, int* data_read, i2c_t i2c_obj)
+{
+ char ret_code = 0;
+ if (!i2c_start(&i2c_obj)) {
+ if ((i2c_byte_write(&i2c_obj,(slave_addr << 1))==1) &&
+ (i2c_byte_write(&i2c_obj, reg_addr)==1) &&
+ (!i2c_start(&i2c_obj)) &&
+ (i2c_byte_write(&i2c_obj, ((slave_addr << 1) | 0x01)) == 1)) {
+ *data_read = i2c_byte_read(&i2c_obj,1);
+ ret_code = 1;
+ }
+ i2c_stop(&i2c_obj);
+ }
+ return ret_code;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MIN_BATTERY_VOLTAGE_H
+#define MIN_BATTERY_VOLTAGE_H
+
+#include "hal/i2c_api.h"
+
+#ifdef __cplusplus
+extern"C"{
+#endif
+
+#define BQ24295_I2C_ADDRESS (0x6B)
+#define I2C_FREQUENCY 100000
+#define MIN_BATTERY_VOLTAGE_MASK (0x87)
+
+/** Initializes an instance of class BatteryChargerI2c which is using the STM HAL I2C APIs
+ * This allows longer USB cables or USB ports with lower output voltages to power the board correctly.
+ */
+
+void set_minimum_battery_voltage(void);
+char read_from_i2c(int slave_addr, int reg_addr, int* data_read, i2c_t i2c_obj);
+char write_to_i2c(int slave_addr, int reg_addr,int data_write, i2c_t i2c_obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MIN_BATTERY_VOLTAGE_H
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/onboard_modem_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/onboard_modem_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if MBED_CONF_NSAPI_PRESENT
+
+#include "onboard_modem_api.h"
+#include "gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "PinNames.h"
+
+#if MODEM_ON_BOARD
+
+// Note microseconds not milliseconds
+static void press_power_button(int time_us)
+{
+ gpio_t gpio;
+
+#if defined(TARGET_UBLOX_C030_R410M)
+ gpio_init_inout(&gpio, MDMPWRON, PIN_OUTPUT, OpenDrain, 0);
+#else
+ gpio_init_out_ex(&gpio, MDMPWRON, 0);
+#endif
+
+ wait_us(time_us);
+ gpio_write(&gpio, 1);
+}
+
+void onboard_modem_init()
+{
+ gpio_t gpio;
+
+ // Take us out of reset
+ gpio_init_out_ex(&gpio, MDMRST, 1);
+}
+
+void onboard_modem_deinit()
+{
+ gpio_t gpio;
+
+ // Back into reset
+ gpio_init_out_ex(&gpio, MDMRST, 0);
+}
+
+void onboard_modem_power_up()
+{
+#if defined(TARGET_UBLOX_C030_R410M)
+ /* keep the power line low for 1 seconds */
+ press_power_button(1000000);
+#else
+ /* keep the power line low for 50 microseconds */
+ press_power_button(50);
+#endif
+
+ /* give modem a little time to respond */
+ wait_ms(100);
+}
+
+void onboard_modem_power_down()
+{
+#if defined(TARGET_UBLOX_C030_R410M)
+ /* keep the power line low for 1.5 seconds */
+ press_power_button(1500000);
+#else
+ /* keep the power line low for 1 seconds */
+ press_power_button(1000000);
+#endif
+}
+
+#endif //MODEM_ON_BOARD
+#endif //MBED_CONF_NSAPI_PRESENT
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,184 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *----------------------------------------------------------------------------------------------------------------------------------------
+ * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL | PLL_HSE_XTAL | PLL_HSE_XTAL
+ * | (external 8 MHz clock) | (external 8 MHz clock) | (external 12 MHz clock)| (external 12 MHz clock)
+ *----------------------------------------------------------------------------------------------------------------------------------------
+ * SYSCLK(MHz) | 168 | 84 | 168 | 84
+ *----------------------------------------------------------------------------------------------------------------------------------------
+ * AHBCLK (MHz) | 168 | 84 | 168 | 84
+ *----------------------------------------------------------------------------------------------------------------------------------------
+ * APB1CLK (MHz) | 42 | 42 | 42 | 42
+ *----------------------------------------------------------------------------------------------------------------------------------------
+ * APB2CLK (MHz) | 84 | 84 | 84 | 84
+ *----------------------------------------------------------------------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES | YES | YES
+ *----------------------------------------------------------------------------------------------------------------------------------------
+**/
+
+#include "ublox_low_level_api.h"
+#include "stm32f4xx.h"
+#include "nvic_addr.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/* Select the SYSCLOCK to start with (0=OFF, 1=ON) */
+#define USE_SYSCLOCK_168 (1) /* Use external 8MHz or 12 MHz xtal and sets SYSCLK to 168MHz */
+#define USE_SYSCLOCK_84 (0) /* Use external 8MHz or 12 MHz xtal and sets SYSCLK to 84MHz */
+
+
+void SetSysClock(void);
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+ ublox_board_init();
+}
+
+
+
+/** System Clock Configuration
+*/
+#if USE_SYSCLOCK_168 != 0
+/*
+ * Set SYSCLK=168MHZ
+ */
+void SetSysClock(void)
+{
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+#ifdef USE_DEBUG_8MHz_XTAL
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#else
+ RCC_OscInitStruct.PLL.PLLM = 12;
+#endif
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
+ | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+
+}
+
+#elif USE_SYSCLOCK_84 != 0
+/*
+Set SYSCLK=84MHZ
+ */
+void SetSysClock(void)
+{
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+#ifdef USE_DEBUG_8MHz_XTAL
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#else
+ RCC_OscInitStruct.PLL.PLLM = 12;
+#endif
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
+ | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+}
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/ublox_low_level_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/ublox_low_level_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "ublox_low_level_api.h"
+
+#include <stdbool.h>
+#include "gpio_api.h"
+
+void ublox_board_init(void) {
+ gpio_t gpio;
+
+ // Enable power to 3V3
+ gpio_init_inout(&gpio, PWR3V3, PIN_OUTPUT, OpenDrain, 1);
+
+ // start with modem disabled
+ gpio_init_out_ex(&gpio, MDMRST, 0);
+#if defined(TARGET_UBLOX_C030_R410M)
+ gpio_init_inout(&gpio, MDMPWRON, PIN_OUTPUT, OpenDrain, 1);
+#else
+ gpio_init_out_ex(&gpio, MDMPWRON, 0);
+#endif
+ gpio_init_out_ex(&gpio, MDMRTS, 0);
+ gpio_init_in_ex(&gpio, MDMCURRENTSENSE, PullNone);
+
+#if !defined (TARGET_UBLOX_C030_R410M)
+ // start with GNSS disabled, this is ONLY TEMPORARY and that once the HW issue with the GNSSEN pin on the R410M board is resolved then this line will become default for all platforms.
+ gpio_init_inout(&gpio, GNSSEN, PIN_OUTPUT, PushPullNoPull, 0);
+#endif
+
+ // power on SD card
+ gpio_init_out_ex(&gpio, SDPWRON, 1);
+
+ // led should be off
+ gpio_init_out_ex(&gpio, LED1, 1);
+ gpio_init_out_ex(&gpio, LED2, 1);
+ gpio_init_out_ex(&gpio, LED3, 1);
+ gpio_init_out_ex(&gpio, LED4, 1);
+}
+
+// End Of File
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/ublox_low_level_api.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/ublox_low_level_api.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,14 @@
+#ifndef UBLOX_LOW_LEVEL_API_H
+#define UBLOX_LOW_LEVEL_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ublox_board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // UBLOX_LOW_LEVEL_H
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/startup_stm32f437xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/startup_stm32f437xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,412 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f437xx.s +;* Author : MCD Application Team +;* Description : STM32F437x devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20030000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/stm32f437xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/stm32f437xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,61 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 1 MB FLASH (0x100000) + 192 KB SRAM (0x30000) + 64 KB CCBRAM (0x10000)+ 4 KB BKPSRAM
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ RW_IRAM2 (0x10000000) (0x10000) { ; RW data
+ .ANY (CCMRAM)
+ }
+
+ RW_IRAM3 0x40024000 4096 { ; 4 kbytes of Backup SRAM
+ .ANY (BKPSRAM)
+ }
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/STM32F437xx.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/STM32F437xx.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,182 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 1024k
+#endif
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+RAM (xrw) : ORIGIN = 0x200001AC, LENGTH = 192K - 0x1AC /* 0x1AC is to leave room for vectors */
+CCM_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K
+BACKUP_SRAM (rw) : ORIGIN = 0x40024000, LENGTH = 4096
+FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+ /* Code can explicitly ask for data to be
+ placed into CCMRAM which will be left
+ uninitialized.
+ */
+ .CCMRAM (NOLOAD):
+ {
+ Image$$RW_IRAM2$$Base = . ;
+ *(CCMRAM)
+ Image$$RW_IRAM2$$ZI$$Limit = .;
+ } > CCM_RAM
+
+ /* Backup SRAM, requires unlocking before access */
+ .BKPSRAM (NOLOAD):
+ {
+ Image$$RW_IRAM3$$Base = . ;
+ *(BKPSRAM)
+ Image$$RW_IRAM3$$ZI$$Limit = .;
+ } > BACKUP_SRAM
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,563 @@ +/** + ****************************************************************************** + * @file startup_stm32f437xx.s + * @author MCD Application Team + * @brief STM32F437xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2D_IRQHandler /* DMA2D */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/startup_stm32f437xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/startup_stm32f437xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,686 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f437xx.s +;* Author : MCD Application Team +;* Description : STM32F437xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/stm32f437xx.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/stm32f437xx.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x200001AF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200001B0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
+define symbol __ICFEDIT_region_BKPSRAM_start__ = 0x40024000;
+define symbol __ICFEDIT_region_BKPSRAM_end__ = 0x40024FFF;
+/*-Sizes-*/
+/*Heap 1/2 of ram and ISR stack 4 kbytes*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x18000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+define region BKPSRAM_region = mem:[from __ICFEDIT_region_BKPSRAM_start__ to __ICFEDIT_region_BKPSRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+do not initialize { section CCMRAM };
+do not initialize { section BKPSRAM };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+place in CCMRAM_region { section CCMRAM };
+place in BKPSRAM_region { section BKPSRAM };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F437VG +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB +// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM +#define NVIC_NUM_VECTORS 107 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,60 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +#if defined (STM32F427xx) || defined (STM32F437xx) +#define FLASH_SIZE (uint32_t) 0x100000 +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Base address of the Flash sectors */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,17071 @@
+/**
+ ******************************************************************************
+ * @file stm32f437xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F437xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f437xx
+ * @{
+ */
+
+#ifndef __STM32F437xx_H
+#define __STM32F437xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1;
+ __IO uint32_t MACDBGR;
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC123_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC123_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2_Pos (8U)
+#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos (9U)
+#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos (10U)
+#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos (11U)
+#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos (12U)
+#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos (13U)
+#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3_Pos (16U)
+#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos (17U)
+#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos (18U)
+#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos (19U)
+#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos (20U)
+#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos (21U)
+#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos (14U)
+#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos (15U)
+#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos (16U)
+#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos (17U)
+#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos (18U)
+#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos (19U)
+#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos (20U)
+#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos (21U)
+#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos (22U)
+#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos (23U)
+#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos (24U)
+#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos (25U)
+#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos (26U)
+#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos (27U)
+#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+#define CRYP_CR_ALGODIR_Pos (2U)
+#define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
+#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
+
+#define CRYP_CR_ALGOMODE_Pos (3U)
+#define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
+#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
+#define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
+#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
+#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
+#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
+#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
+#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
+#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
+#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
+#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
+#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
+#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
+#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
+#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
+#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
+#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
+#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
+#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
+
+#define CRYP_CR_DATATYPE_Pos (6U)
+#define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
+#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
+#define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
+#define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
+#define CRYP_CR_KEYSIZE_Pos (8U)
+#define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
+#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
+#define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
+#define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
+#define CRYP_CR_FFLUSH_Pos (14U)
+#define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
+#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
+#define CRYP_CR_CRYPEN_Pos (15U)
+#define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
+#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
+
+#define CRYP_CR_GCM_CCMPH_Pos (16U)
+#define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
+#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
+#define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
+#define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
+#define CRYP_CR_ALGOMODE_3 0x00080000U
+
+/****************** Bits definition for CRYP_SR register *********************/
+#define CRYP_SR_IFEM_Pos (0U)
+#define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
+#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
+#define CRYP_SR_IFNF_Pos (1U)
+#define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
+#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
+#define CRYP_SR_OFNE_Pos (2U)
+#define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
+#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
+#define CRYP_SR_OFFU_Pos (3U)
+#define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
+#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
+#define CRYP_SR_BUSY_Pos (4U)
+#define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
+#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
+/****************** Bits definition for CRYP_DMACR register ******************/
+#define CRYP_DMACR_DIEN_Pos (0U)
+#define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
+#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
+#define CRYP_DMACR_DOEN_Pos (1U)
+#define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
+#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
+/***************** Bits definition for CRYP_IMSCR register ******************/
+#define CRYP_IMSCR_INIM_Pos (0U)
+#define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
+#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
+#define CRYP_IMSCR_OUTIM_Pos (1U)
+#define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
+#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
+/****************** Bits definition for CRYP_RISR register *******************/
+#define CRYP_RISR_OUTRIS_Pos (0U)
+#define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
+#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
+#define CRYP_RISR_INRIS_Pos (1U)
+#define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
+#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
+/****************** Bits definition for CRYP_MISR register *******************/
+#define CRYP_MISR_INMIS_Pos (0U)
+#define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
+#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
+#define CRYP_MISR_OUTMIS_Pos (1U)
+#define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
+#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE_Pos (0U)
+#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos (1U)
+#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
+#define DCMI_CR_CM DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos (2U)
+#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos (3U)
+#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos (4U)
+#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos (5U)
+#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos (6U)
+#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos (7U)
+#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_ENABLE_Pos (14U)
+#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC_Pos (0U)
+#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos (1U)
+#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos (2U)
+#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS_Pos (0U)
+#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos (1U)
+#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos (2U)
+#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos (4U)
+#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE_Pos (0U)
+#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos (1U)
+#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos (2U)
+#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos (3U)
+#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos (4U)
+#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS_Pos (0U)
+#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos (1U)
+#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos (2U)
+#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos (4U)
+#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC_Pos (0U)
+#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos (1U)
+#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos (2U)
+#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos (4U)
+#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC_Pos (0U)
+#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos (8U)
+#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos (16U)
+#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos (24U)
+#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU_Pos (0U)
+#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos (8U)
+#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos (16U)
+#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos (24U)
+#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos (16U)
+#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos (16U)
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
+
+/******************** Bits definition for DCMI_DR register *********************/
+#define DCMI_DR_BYTE0_Pos (0U)
+#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos (8U)
+#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos (16U)
+#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos (24U)
+#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START_Pos (0U)
+#define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
+#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos (1U)
+#define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
+#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos (2U)
+#define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
+#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
+#define DMA2D_CR_TEIE_Pos (8U)
+#define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
+#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos (9U)
+#define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
+#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos (10U)
+#define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
+#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos (11U)
+#define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos (12U)
+#define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos (13U)
+#define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
+#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos (16U)
+#define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
+#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF_Pos (0U)
+#define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos (1U)
+#define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos (2U)
+#define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos (3U)
+#define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos (4U)
+#define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos (5U)
+#define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos (0U)
+#define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos (1U)
+#define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos (2U)
+#define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos (3U)
+#define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos (4U)
+#define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos (5U)
+#define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA_Pos (0U)
+#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO_Pos (0U)
+#define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA_Pos (0U)
+#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO_Pos (0U)
+#define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM_Pos (0U)
+#define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos (4U)
+#define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos (5U)
+#define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos (8U)
+#define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos (16U)
+#define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos (0U)
+#define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos (8U)
+#define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos (16U)
+#define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM_Pos (0U)
+#define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM_Pos (4U)
+#define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos (5U)
+#define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos (8U)
+#define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos (16U)
+#define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos (0U)
+#define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos (8U)
+#define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos (16U)
+#define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA_Pos (0U)
+#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA_Pos (0U)
+#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM_Pos (0U)
+#define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA_Pos (0U)
+#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO_Pos (0U)
+#define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL_Pos (0U)
+#define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos (16U)
+#define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW_Pos (0U)
+#define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN_Pos (0U)
+#define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos (8U)
+#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_MER2_Pos (15U)
+#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_BFB2_Pos (4U)
+#define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
+#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M_Pos (30U)
+#define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
+#define FLASH_OPTCR_SPRMOD_Pos (31U)
+#define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN_Pos (0U)
+#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN_Pos (1U)
+#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP_Pos (2U)
+#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR1_MWID_Pos (4U)
+#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR1_FACCEN_Pos (6U)
+#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN_Pos (8U)
+#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL_Pos (9U)
+#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD_Pos (10U)
+#define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG_Pos (11U)
+#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR1_WREN_Pos (12U)
+#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR1_WAITEN_Pos (13U)
+#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD_Pos (14U)
+#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE_Pos (16U)
+#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR1_CBURSTRW_Pos (19U)
+#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN_Pos (0U)
+#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN_Pos (1U)
+#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP_Pos (2U)
+#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR2_MWID_Pos (4U)
+#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR2_FACCEN_Pos (6U)
+#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN_Pos (8U)
+#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL_Pos (9U)
+#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD_Pos (10U)
+#define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG_Pos (11U)
+#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR2_WREN_Pos (12U)
+#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR2_WAITEN_Pos (13U)
+#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD_Pos (14U)
+#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR2_CPSIZE_Pos (16U)
+#define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR2_CBURSTRW_Pos (19U)
+#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN_Pos (0U)
+#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN_Pos (1U)
+#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP_Pos (2U)
+#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR3_MWID_Pos (4U)
+#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR3_FACCEN_Pos (6U)
+#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN_Pos (8U)
+#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL_Pos (9U)
+#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD_Pos (10U)
+#define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG_Pos (11U)
+#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR3_WREN_Pos (12U)
+#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR3_WAITEN_Pos (13U)
+#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD_Pos (14U)
+#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR3_CPSIZE_Pos (16U)
+#define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR3_CBURSTRW_Pos (19U)
+#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN_Pos (0U)
+#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN_Pos (1U)
+#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP_Pos (2U)
+#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR4_MWID_Pos (4U)
+#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR4_FACCEN_Pos (6U)
+#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN_Pos (8U)
+#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL_Pos (9U)
+#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD_Pos (10U)
+#define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG_Pos (11U)
+#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR4_WREN_Pos (12U)
+#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR4_WAITEN_Pos (13U)
+#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD_Pos (14U)
+#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR4_CPSIZE_Pos (16U)
+#define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR4_CBURSTRW_Pos (19U)
+#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET_Pos (0U)
+#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR1_ADDHLD_Pos (4U)
+#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR1_DATAST_Pos (8U)
+#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR1_BUSTURN_Pos (16U)
+#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR1_CLKDIV_Pos (20U)
+#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR1_DATLAT_Pos (24U)
+#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR1_ACCMOD_Pos (28U)
+#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET_Pos (0U)
+#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR2_ADDHLD_Pos (4U)
+#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR2_DATAST_Pos (8U)
+#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR2_BUSTURN_Pos (16U)
+#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR2_CLKDIV_Pos (20U)
+#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR2_DATLAT_Pos (24U)
+#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR2_ACCMOD_Pos (28U)
+#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET_Pos (0U)
+#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR3_ADDHLD_Pos (4U)
+#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR3_DATAST_Pos (8U)
+#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR3_BUSTURN_Pos (16U)
+#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR3_CLKDIV_Pos (20U)
+#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR3_DATLAT_Pos (24U)
+#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR3_ACCMOD_Pos (28U)
+#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET_Pos (0U)
+#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR4_ADDHLD_Pos (4U)
+#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR4_DATAST_Pos (8U)
+#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR4_BUSTURN_Pos (16U)
+#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR4_CLKDIV_Pos (20U)
+#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR4_DATLAT_Pos (24U)
+#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR4_ACCMOD_Pos (28U)
+#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET_Pos (0U)
+#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR1_ADDHLD_Pos (4U)
+#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR1_DATAST_Pos (8U)
+#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR1_BUSTURN_Pos (16U)
+#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR1_ACCMOD_Pos (28U)
+#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET_Pos (0U)
+#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR2_ADDHLD_Pos (4U)
+#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR2_DATAST_Pos (8U)
+#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR2_BUSTURN_Pos (16U)
+#define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR2_ACCMOD_Pos (28U)
+#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET_Pos (0U)
+#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR3_ADDHLD_Pos (4U)
+#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR3_DATAST_Pos (8U)
+#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR3_BUSTURN_Pos (16U)
+#define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR3_ACCMOD_Pos (28U)
+#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET_Pos (0U)
+#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR4_ADDHLD_Pos (4U)
+#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR4_DATAST_Pos (8U)
+#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR4_BUSTURN_Pos (16U)
+#define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR4_ACCMOD_Pos (28U)
+#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+
+#define FMC_PCR2_PWAITEN_Pos (1U)
+#define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN_Pos (2U)
+#define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP_Pos (3U)
+#define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR2_PWID_Pos (4U)
+#define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR2_ECCEN_Pos (6U)
+#define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR_Pos (9U)
+#define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR2_TAR_Pos (13U)
+#define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR2_ECCPS_Pos (17U)
+#define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN_Pos (1U)
+#define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN_Pos (2U)
+#define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP_Pos (3U)
+#define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR3_PWID_Pos (4U)
+#define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR3_ECCEN_Pos (6U)
+#define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR_Pos (9U)
+#define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR3_TAR_Pos (13U)
+#define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR3_ECCPS_Pos (17U)
+#define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN_Pos (1U)
+#define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN_Pos (2U)
+#define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP_Pos (3U)
+#define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR4_PWID_Pos (4U)
+#define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR4_ECCEN_Pos (6U)
+#define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR_Pos (9U)
+#define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR4_TAR_Pos (13U)
+#define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR4_ECCPS_Pos (17U)
+#define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS_Pos (0U)
+#define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS_Pos (1U)
+#define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR2_IFS_Pos (2U)
+#define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN_Pos (3U)
+#define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN_Pos (4U)
+#define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN_Pos (5U)
+#define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT_Pos (6U)
+#define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS_Pos (0U)
+#define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS_Pos (1U)
+#define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR3_IFS_Pos (2U)
+#define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN_Pos (3U)
+#define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN_Pos (4U)
+#define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN_Pos (5U)
+#define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT_Pos (6U)
+#define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS_Pos (0U)
+#define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS_Pos (1U)
+#define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR4_IFS_Pos (2U)
+#define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN_Pos (3U)
+#define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN_Pos (4U)
+#define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN_Pos (5U)
+#define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT_Pos (6U)
+#define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2_Pos (0U)
+#define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
+#define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
+#define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
+#define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
+#define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
+#define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
+#define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
+#define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
+#define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM2_MEMWAIT2_Pos (8U)
+#define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM2_MEMHOLD2_Pos (16U)
+#define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM2_MEMHIZ2_Pos (24U)
+#define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3_Pos (0U)
+#define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
+#define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
+#define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
+#define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
+#define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
+#define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
+#define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
+#define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
+#define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM3_MEMWAIT3_Pos (8U)
+#define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
+#define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
+#define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
+#define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
+#define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
+#define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
+#define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
+#define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM3_MEMHOLD3_Pos (16U)
+#define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
+#define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
+#define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
+#define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
+#define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
+#define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
+#define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
+#define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM3_MEMHIZ3_Pos (24U)
+#define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
+#define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
+#define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
+#define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
+#define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
+#define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
+#define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
+#define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4_Pos (0U)
+#define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
+#define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
+#define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
+#define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
+#define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
+#define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
+#define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
+#define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
+#define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM4_MEMWAIT4_Pos (8U)
+#define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM4_MEMHOLD4_Pos (16U)
+#define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM4_MEMHIZ4_Pos (24U)
+#define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2_Pos (0U)
+#define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
+#define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
+#define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
+#define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
+#define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
+#define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
+#define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
+#define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
+#define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT2_ATTWAIT2_Pos (8U)
+#define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT2_ATTHOLD2_Pos (16U)
+#define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT2_ATTHIZ2_Pos (24U)
+#define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3_Pos (0U)
+#define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
+#define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
+#define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
+#define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
+#define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
+#define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
+#define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
+#define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
+#define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT3_ATTWAIT3_Pos (8U)
+#define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
+#define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
+#define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
+#define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
+#define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
+#define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
+#define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
+#define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT3_ATTHOLD3_Pos (16U)
+#define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
+#define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
+#define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
+#define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
+#define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
+#define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
+#define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
+#define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT3_ATTHIZ3_Pos (24U)
+#define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
+#define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
+#define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
+#define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
+#define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
+#define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
+#define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
+#define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
+#define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4_Pos (0U)
+#define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
+#define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
+#define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
+#define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
+#define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
+#define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
+#define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
+#define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
+#define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT4_ATTWAIT4_Pos (8U)
+#define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT4_ATTHOLD4_Pos (16U)
+#define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT4_ATTHIZ4_Pos (24U)
+#define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4_Pos (0U)
+#define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PIO4_IOWAIT4_Pos (8U)
+#define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PIO4_IOHOLD4_Pos (16U)
+#define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PIO4_IOHIZ4_Pos (24U)
+#define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2_Pos (0U)
+#define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3_Pos (0U)
+#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC_Pos (0U)
+#define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR1_NR_Pos (2U)
+#define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR1_MWID_Pos (4U)
+#define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR1_NB_Pos (6U)
+#define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS_Pos (7U)
+#define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR1_WP_Pos (9U)
+#define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK_Pos (10U)
+#define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR1_RBURST_Pos (12U)
+#define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE_Pos (13U)
+#define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC_Pos (0U)
+#define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR2_NR_Pos (2U)
+#define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR2_MWID_Pos (4U)
+#define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR2_NB_Pos (6U)
+#define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS_Pos (7U)
+#define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR2_WP_Pos (9U)
+#define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK_Pos (10U)
+#define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR2_RBURST_Pos (12U)
+#define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE_Pos (13U)
+#define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD_Pos (0U)
+#define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR1_TXSR_Pos (4U)
+#define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR1_TRAS_Pos (8U)
+#define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR1_TRC_Pos (12U)
+#define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR1_TWR_Pos (16U)
+#define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR1_TRP_Pos (20U)
+#define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR1_TRCD_Pos (24U)
+#define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD_Pos (0U)
+#define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR2_TXSR_Pos (4U)
+#define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR2_TRAS_Pos (8U)
+#define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR2_TRC_Pos (12U)
+#define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR2_TWR_Pos (16U)
+#define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR2_TRP_Pos (20U)
+#define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR2_TRCD_Pos (24U)
+#define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE_Pos (0U)
+#define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
+#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
+
+#define FMC_SDCMR_CTB2_Pos (3U)
+#define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos (4U)
+#define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos (5U)
+#define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos (9U)
+#define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE_Pos (0U)
+#define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
+#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos (1U)
+#define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos (14U)
+#define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE_Pos (0U)
+#define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
+#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos (1U)
+#define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
+#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos (3U)
+#define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
+#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
+#define FMC_SDSR_BUSY_Pos (5U)
+#define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
+#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* HASH */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+#define HASH_CR_INIT_Pos (2U)
+#define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
+#define HASH_CR_INIT HASH_CR_INIT_Msk
+#define HASH_CR_DMAE_Pos (3U)
+#define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
+#define HASH_CR_DMAE HASH_CR_DMAE_Msk
+#define HASH_CR_DATATYPE_Pos (4U)
+#define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
+#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
+#define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
+#define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
+#define HASH_CR_MODE_Pos (6U)
+#define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
+#define HASH_CR_MODE HASH_CR_MODE_Msk
+#define HASH_CR_ALGO_Pos (7U)
+#define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
+#define HASH_CR_ALGO HASH_CR_ALGO_Msk
+#define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
+#define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
+#define HASH_CR_NBW_Pos (8U)
+#define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
+#define HASH_CR_NBW HASH_CR_NBW_Msk
+#define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
+#define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
+#define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
+#define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
+#define HASH_CR_DINNE_Pos (12U)
+#define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
+#define HASH_CR_DINNE HASH_CR_DINNE_Msk
+#define HASH_CR_MDMAT_Pos (13U)
+#define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
+#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
+#define HASH_CR_LKEY_Pos (16U)
+#define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
+#define HASH_CR_LKEY HASH_CR_LKEY_Msk
+
+/****************** Bits definition for HASH_STR register *******************/
+#define HASH_STR_NBLW_Pos (0U)
+#define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
+#define HASH_STR_NBLW HASH_STR_NBLW_Msk
+#define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
+#define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
+#define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
+#define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
+#define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
+#define HASH_STR_DCAL_Pos (8U)
+#define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
+#define HASH_STR_DCAL HASH_STR_DCAL_Msk
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
+
+/****************** Bits definition for HASH_IMR register *******************/
+#define HASH_IMR_DINIE_Pos (0U)
+#define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
+#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
+#define HASH_IMR_DCIE_Pos (1U)
+#define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
+#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
+/****************** Bits definition for HASH_SR register ********************/
+#define HASH_SR_DINIS_Pos (0U)
+#define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
+#define HASH_SR_DINIS HASH_SR_DINIS_Msk
+#define HASH_SR_DCIS_Pos (1U)
+#define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
+#define HASH_SR_DCIS HASH_SR_DCIS_Msk
+#define HASH_SR_DMAS_Pos (2U)
+#define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
+#define HASH_SR_DMAS HASH_SR_DMAS_Msk
+#define HASH_SR_BUSY_Pos (3U)
+#define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
+#define HASH_SR_BUSY HASH_SR_BUSY_Msk
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN_Pos (16U)
+#define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
+#define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
+#define PWR_CR_ODSWEN_Pos (17U)
+#define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
+#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN_Pos (18U)
+#define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
+#define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
+#define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY_Pos (16U)
+#define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
+#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY_Pos (17U)
+#define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
+#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
+#define PWR_CSR_UDRDY_Pos (18U)
+#define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
+#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
+/* Legacy define */
+#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
+
+#define RCC_CR_PLLSAION_Pos (28U)
+#define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
+#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
+#define RCC_CR_PLLSAIRDY_Pos (29U)
+#define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
+#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_PLLSAIRDYF_Pos (6U)
+#define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
+#define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
+#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+#define RCC_CIR_PLLSAIRDYC_Pos (22U)
+#define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
+#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
+#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
+#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
+#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
+#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
+#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
+#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
+#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
+#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
+#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
+#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
+#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
+#define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
+#define RCC_AHB2RSTR_HASHRST_Pos (5U)
+#define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
+ /* maintained for legacy purpose */
+#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
+#define RCC_APB1RSTR_UART7RST_Pos (30U)
+#define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
+#define RCC_APB1RSTR_UART8RST_Pos (31U)
+#define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SPI6RST_Pos (21U)
+#define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
+#define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
+#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
+#define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
+#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
+#define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
+#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
+#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
+#define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
+#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
+#define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
+#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
+#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
+#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
+#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
+#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
+#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
+#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_DCMIEN_Pos (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_CRYPEN_Pos (4U)
+#define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
+#define RCC_AHB2ENR_HASHEN_Pos (5U)
+#define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos (6U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FMCEN_Pos (0U)
+#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
+#define RCC_APB1ENR_UART7EN_Pos (30U)
+#define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
+#define RCC_APB1ENR_UART8EN_Pos (31U)
+#define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (1U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_ADC2EN_Pos (9U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
+#define RCC_APB2ENR_ADC3EN_Pos (10U)
+#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SPI6EN_Pos (21U)
+#define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
+#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos (22U)
+#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
+#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
+#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
+#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
+#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
+#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
+#define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
+#define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
+#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
+
+#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
+#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
+#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
+#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
+#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
+#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
+#define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
+#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
+#define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
+#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
+#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
+#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
+#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
+#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
+
+
+#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
+#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
+#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
+
+#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
+#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
+#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
+#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
+#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
+#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
+#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
+
+#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
+#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
+#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
+#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
+#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
+#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
+#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
+
+#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
+#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
+#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
+#define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
+#define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
+#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
+#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
+#define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
+#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_Pos (0U)
+#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos (4U)
+#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE_Pos (0U)
+#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos (2U)
+#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos (5U)
+#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
+#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
+#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos (8U)
+#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR_Pos (9U)
+#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN_Pos (10U)
+#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos (12U)
+#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV_Pos (13U)
+#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
+#define SAI_xCR1_SAIEN_Pos (16U)
+#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN_Pos (17U)
+#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
+#define SAI_xCR1_NODIV_Pos (19U)
+#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV_Pos (20U)
+#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH_Pos (0U)
+#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos (3U)
+#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS_Pos (4U)
+#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos (5U)
+#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL_Pos (6U)
+#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT_Pos (7U)
+#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos (13U)
+#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
+
+#define SAI_xCR2_COMP_Pos (14U)
+#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL_Pos (0U)
+#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos (8U)
+#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos (16U)
+#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos (17U)
+#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF_Pos (18U)
+#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF_Pos (0U)
+#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos (8U)
+#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos (16U)
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE_Pos (0U)
+#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE_Pos (1U)
+#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE_Pos (2U)
+#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE_Pos (3U)
+#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE_Pos (4U)
+#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE_Pos (5U)
+#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE_Pos (6U)
+#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR_Pos (0U)
+#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET_Pos (1U)
+#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
+#define SAI_xSR_WCKCFG_Pos (2U)
+#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ_Pos (3U)
+#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
+#define SAI_xSR_CNRDY_Pos (4U)
+#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
+#define SAI_xSR_AFSDET_Pos (5U)
+#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET_Pos (6U)
+#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL_Pos (16U)
+#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR_Pos (0U)
+#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ_Pos (3U)
+#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY_Pos (4U)
+#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET_Pos (5U)
+#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET_Pos (6U)
+#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA_Pos (0U)
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
+#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
+#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
+#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
+#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
+/* Legacy Defines */
+#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2_Pos (16U)
+#define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
+#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2_Pos (17U)
+#define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
+#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2_Pos (18U)
+#define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
+#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
+#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD_Pos (23U)
+#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
+#define ETH_MACCR_JD_Pos (22U)
+#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
+#define ETH_MACCR_IFG_Pos (17U)
+#define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
+#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD_Pos (16U)
+#define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES_Pos (14U)
+#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
+#define ETH_MACCR_ROD_Pos (13U)
+#define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
+#define ETH_MACCR_LM_Pos (12U)
+#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
+#define ETH_MACCR_DM_Pos (11U)
+#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
+#define ETH_MACCR_IPCO_Pos (10U)
+#define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
+#define ETH_MACCR_RD_Pos (9U)
+#define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
+#define ETH_MACCR_APCS_Pos (7U)
+#define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
+#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL_Pos (5U)
+#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC_Pos (4U)
+#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
+#define ETH_MACCR_TE_Pos (3U)
+#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
+#define ETH_MACCR_RE_Pos (2U)
+#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA_Pos (31U)
+#define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
+#define ETH_MACFFR_HPF_Pos (10U)
+#define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
+#define ETH_MACFFR_SAF_Pos (9U)
+#define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
+#define ETH_MACFFR_SAIF_Pos (8U)
+#define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
+#define ETH_MACFFR_PCF_Pos (6U)
+#define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
+#define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
+#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
+#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
+#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD_Pos (5U)
+#define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
+#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
+#define ETH_MACFFR_PAM_Pos (4U)
+#define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
+#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF_Pos (3U)
+#define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
+#define ETH_MACFFR_HM_Pos (2U)
+#define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
+#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
+#define ETH_MACFFR_HU_Pos (1U)
+#define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
+#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
+#define ETH_MACFFR_PM_Pos (0U)
+#define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
+#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos (0U)
+#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos (0U)
+#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA_Pos (11U)
+#define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
+#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
+#define ETH_MACMIIAR_MR_Pos (6U)
+#define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
+#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR_Pos (2U)
+#define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
+#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
+#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIAR_CR_Div62_Pos (2U)
+#define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
+#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define ETH_MACMIIAR_CR_Div16_Pos (3U)
+#define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
+#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ETH_MACMIIAR_CR_Div26_Pos (2U)
+#define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
+#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_CR_Div102_Pos (4U)
+#define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
+#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW_Pos (1U)
+#define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
+#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
+#define ETH_MACMIIAR_MB_Pos (0U)
+#define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD_Pos (0U)
+#define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT_Pos (16U)
+#define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
+#define ETH_MACFCR_ZQPD_Pos (7U)
+#define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
+#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT_Pos (4U)
+#define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+#define ETH_MACFCR_PLT_Minus28_Pos (4U)
+#define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
+#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACFCR_PLT_Minus144_Pos (5U)
+#define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
+#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256_Pos (4U)
+#define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD_Pos (3U)
+#define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
+#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE_Pos (2U)
+#define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
+#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
+#define ETH_MACFCR_TFCE_Pos (1U)
+#define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
+#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA_Pos (0U)
+#define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
+#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC_Pos (16U)
+#define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
+#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI_Pos (0U)
+#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D_Pos (0U)
+#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
+#define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
+#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU_Pos (9U)
+#define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
+#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
+#define ETH_MACPMTCSR_WFR_Pos (6U)
+#define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
+#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR_Pos (5U)
+#define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
+#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE_Pos (2U)
+#define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
+#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE_Pos (1U)
+#define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
+#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD_Pos (0U)
+#define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
+#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
+
+/* Bit definition for Ethernet MAC debug Register */
+#define ETH_MACDBGR_TFF_Pos (25U)
+#define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
+#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
+#define ETH_MACDBGR_TFNE_Pos (24U)
+#define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
+#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
+#define ETH_MACDBGR_TFWA_Pos (22U)
+#define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
+#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
+#define ETH_MACDBGR_TFRS_Pos (20U)
+#define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
+#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
+#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
+#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
+#define ETH_MACDBGR_TFRS_READ_Pos (20U)
+#define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
+#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
+#define ETH_MACDBGR_MTP_Pos (19U)
+#define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
+#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
+#define ETH_MACDBGR_MTFCS_Pos (17U)
+#define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
+#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
+#define ETH_MACDBGR_MMTEA_Pos (16U)
+#define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
+#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
+#define ETH_MACDBGR_RFFL_Pos (8U)
+#define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
+#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
+#define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
+#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
+#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
+#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
+#define ETH_MACDBGR_RFRCS_Pos (5U)
+#define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
+#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
+#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
+#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
+#define ETH_MACDBGR_RFWRA_Pos (4U)
+#define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
+#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
+#define ETH_MACDBGR_MSFRWCS_Pos (1U)
+#define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
+#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
+#define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
+#define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
+#define ETH_MACDBGR_MMRPEA_Pos (0U)
+#define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
+#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS_Pos (9U)
+#define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
+#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS_Pos (6U)
+#define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
+#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
+#define ETH_MACSR_MMMCRS_Pos (5U)
+#define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
+#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
+#define ETH_MACSR_MMCS_Pos (4U)
+#define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
+#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
+#define ETH_MACSR_PMTS_Pos (3U)
+#define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
+#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM_Pos (9U)
+#define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
+#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM_Pos (3U)
+#define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
+#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H_Pos (0U)
+#define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L_Pos (0U)
+#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE_Pos (31U)
+#define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
+#define ETH_MACA1HR_SA_Pos (30U)
+#define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
+#define ETH_MACA1HR_MBC_Pos (24U)
+#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H_Pos (0U)
+#define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L_Pos (0U)
+#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE_Pos (31U)
+#define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
+#define ETH_MACA2HR_SA_Pos (30U)
+#define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
+#define ETH_MACA2HR_MBC_Pos (24U)
+#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H_Pos (0U)
+#define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L_Pos (0U)
+#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE_Pos (31U)
+#define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
+#define ETH_MACA3HR_SA_Pos (30U)
+#define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
+#define ETH_MACA3HR_MBC_Pos (24U)
+#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H_Pos (0U)
+#define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L_Pos (0U)
+#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP_Pos (5U)
+#define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP_Pos (4U)
+#define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
+#define ETH_MMCCR_MCF_Pos (3U)
+#define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR_Pos (2U)
+#define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
+#define ETH_MMCCR_CSR_Pos (1U)
+#define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
+#define ETH_MMCCR_CR_Pos (0U)
+#define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS_Pos (17U)
+#define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES_Pos (6U)
+#define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES_Pos (5U)
+#define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS_Pos (21U)
+#define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS_Pos (15U)
+#define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS_Pos (14U)
+#define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM_Pos (17U)
+#define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM_Pos (6U)
+#define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM_Pos (5U)
+#define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM_Pos (21U)
+#define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
+#define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM_Pos (14U)
+#define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
+#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC_Pos (0U)
+#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC_Pos (0U)
+#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC_Pos (0U)
+#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
+#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT_Pos (16U)
+#define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
+#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME_Pos (15U)
+#define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME_Pos (14U)
+#define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
+#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
+#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
+#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
+#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
+#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
+#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
+#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
+#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
+#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR_Pos (9U)
+#define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
+#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE_Pos (8U)
+#define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
+#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU_Pos (5U)
+#define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
+#define ETH_PTPTSCR_TSITE_Pos (4U)
+#define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU_Pos (3U)
+#define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
+#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI_Pos (2U)
+#define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
+#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU_Pos (1U)
+#define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
+#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE_Pos (0U)
+#define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
+#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI_Pos (0U)
+#define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
+#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS_Pos (0U)
+#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS_Pos (31U)
+#define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS_Pos (0U)
+#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS_Pos (0U)
+#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
+#define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS_Pos (0U)
+#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA_Pos (0U)
+#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH_Pos (0U)
+#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL_Pos (0U)
+#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR_Pos (5U)
+#define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO_Pos (4U)
+#define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB_Pos (25U)
+#define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
+#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
+#define ETH_DMABMR_FPM_Pos (24U)
+#define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
+#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
+#define ETH_DMABMR_USP_Pos (23U)
+#define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
+#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
+#define ETH_DMABMR_RDP_Pos (17U)
+#define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
+#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
+#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB_Pos (16U)
+#define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
+#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
+#define ETH_DMABMR_RTPR_Pos (14U)
+#define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
+#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL_Pos (8U)
+#define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
+#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
+#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE_Pos (7U)
+#define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
+#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL_Pos (2U)
+#define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
+#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
+#define ETH_DMABMR_DA_Pos (1U)
+#define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
+#define ETH_DMABMR_SR_Pos (0U)
+#define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD_Pos (0U)
+#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD_Pos (0U)
+#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL_Pos (0U)
+#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL_Pos (0U)
+#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS_Pos (29U)
+#define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
+#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS_Pos (28U)
+#define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
+#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
+#define ETH_DMASR_MMCS_Pos (27U)
+#define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
+#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
+#define ETH_DMASR_EBS_Pos (23U)
+#define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
+#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+#define ETH_DMASR_EBS_DescAccess_Pos (25U)
+#define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
+#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
+#define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
+#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
+#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
+#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS_Pos (20U)
+#define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
+#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMASR_TPS_Fetching_Pos (20U)
+#define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
+#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
+#define ETH_DMASR_TPS_Waiting_Pos (21U)
+#define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
+#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
+#define ETH_DMASR_TPS_Reading_Pos (20U)
+#define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
+#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
+#define ETH_DMASR_TPS_Suspended_Pos (21U)
+#define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
+#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
+#define ETH_DMASR_TPS_Closing_Pos (20U)
+#define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS_Pos (17U)
+#define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
+#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Fetching_Pos (17U)
+#define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
+#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
+#define ETH_DMASR_RPS_Waiting_Pos (17U)
+#define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
+#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
+#define ETH_DMASR_RPS_Suspended_Pos (19U)
+#define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
+#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
+#define ETH_DMASR_RPS_Closing_Pos (17U)
+#define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
+#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
+#define ETH_DMASR_RPS_Queuing_Pos (17U)
+#define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS_Pos (16U)
+#define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
+#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
+#define ETH_DMASR_AIS_Pos (15U)
+#define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
+#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS_Pos (14U)
+#define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
+#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
+#define ETH_DMASR_FBES_Pos (13U)
+#define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
+#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
+#define ETH_DMASR_ETS_Pos (10U)
+#define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
+#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
+#define ETH_DMASR_RWTS_Pos (9U)
+#define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
+#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS_Pos (8U)
+#define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
+#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
+#define ETH_DMASR_RBUS_Pos (7U)
+#define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
+#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
+#define ETH_DMASR_RS_Pos (6U)
+#define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
+#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
+#define ETH_DMASR_TUS_Pos (5U)
+#define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
+#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
+#define ETH_DMASR_ROS_Pos (4U)
+#define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
+#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
+#define ETH_DMASR_TJTS_Pos (3U)
+#define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
+#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS_Pos (2U)
+#define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
+#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS_Pos (1U)
+#define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
+#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
+#define ETH_DMASR_TS_Pos (0U)
+#define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
+#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD_Pos (26U)
+#define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
+#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF_Pos (25U)
+#define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
+#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
+#define ETH_DMAOMR_DFRF_Pos (24U)
+#define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
+#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF_Pos (21U)
+#define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
+#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
+#define ETH_DMAOMR_FTF_Pos (20U)
+#define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
+#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC_Pos (14U)
+#define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
+#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
+#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST_Pos (13U)
+#define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
+#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF_Pos (7U)
+#define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
+#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
+#define ETH_DMAOMR_FUGF_Pos (6U)
+#define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
+#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC_Pos (3U)
+#define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
+#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
+#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF_Pos (2U)
+#define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
+#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
+#define ETH_DMAOMR_SR_Pos (1U)
+#define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
+#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE_Pos (16U)
+#define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
+#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE_Pos (15U)
+#define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
+#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE_Pos (14U)
+#define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE_Pos (13U)
+#define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
+#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE_Pos (10U)
+#define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE_Pos (9U)
+#define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
+#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE_Pos (8U)
+#define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
+#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE_Pos (7U)
+#define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
+#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE_Pos (6U)
+#define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE_Pos (5U)
+#define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
+#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE_Pos (4U)
+#define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
+#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE_Pos (3U)
+#define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
+#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE_Pos (2U)
+#define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
+#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE_Pos (1U)
+#define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
+#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE_Pos (0U)
+#define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC_Pos (28U)
+#define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
+#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA_Pos (17U)
+#define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
+#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC_Pos (16U)
+#define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
+#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC_Pos (0U)
+#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
+#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP_Pos (0U)
+#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP_Pos (0U)
+#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP_Pos (0U)
+#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP_Pos (0U)
+#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
+#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
+
+#define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
+#define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+#define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F437xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ #define STM32F437xx /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE,
+ SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,146 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+
+ {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
+ {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {NC, NC, 0}
+};
+
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+// TIM3 cannot be used because already used by the Bluetooth UART
+// TIM1 is used by LPO emulation. If external LPO is connected this can be used for PWM.
+const PinMap PinMap_PWM[] = {
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_CAN_RD[] = {
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,190 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03,
+ PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07,
+ PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B,
+ PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F,
+
+ PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13,
+ PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17,
+ PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B,
+ PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F,
+
+ PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23,
+ PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27,
+ PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B,
+ PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F,
+
+ PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33,
+ PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37,
+ PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B,
+ PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F,
+
+ PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43,
+ PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47,
+ PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B,
+ PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F,
+
+ PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53,
+ PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57,
+ PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B,
+ PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F,
+
+ PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63,
+ PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67,
+ PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B,
+ PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F,
+
+ PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73,
+ PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77,
+ PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B,
+ PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F,
+
+ // Module Pins
+ // A
+ P_A5 = PC_2, // UART-DTR
+ P_A6 = PF_2, // Switch-0
+ P_A7 = PE_0, // Red, Mode
+ P_A8 = PB_6, // Green, Switch-1
+ P_A9 = PB_8, // Blue
+ P_A10 = PA_11, // UART-CTS
+ P_A11 = PA_9, // UART-TXD
+ P_A12 = PA_12, // UART-RTS
+ P_A13 = PA_10, // UART-RXD
+ P_A14 = PD_9, // GPIO-0
+ P_A15 = PD_8, // GPIO-1
+ P_A16 = PD_11, // GPIO-2
+ P_A17 = PD_12, // GPIO-3
+ P_A18 = PA_3, // UART-DSR
+ // B
+ // C
+ P_C5 = PG_4, // SPI-IRQ
+ P_C6 = PE_13, // SPI-MISO
+ P_C8 = PE_12, // Res
+ P_C10 = PE_14, // SPI-MOSI
+ P_C11 = PE_11, // SPI-CS0
+ P_C12 = PE_9, // Res
+ P_C13 = PF_6, // GPIO-4
+ P_C14 = PC_1, // RMII-MDC
+ P_C15 = PA_2, // RMII-MDIO
+ P_C16 = PF_7, // GPIO-7
+ P_C17 = PF_1, // I2C-SCL
+ P_C18 = PF_0, // I2C-SDA
+ // D
+ P_D1 = PB_12, // RMII-TXD0
+ P_D2 = PB_13, // RMII-TXD1
+ P_D3 = PB_11, // RMII-TXEN
+ P_D4 = PA_7, // RMII-CRSDV
+ P_D5 = PC_4, // RMII-RXD0
+ P_D6 = PC_5, // RMII-RXD1
+ P_D8 = PA_1, // RMII-REFCLK
+ // TP
+ P_TP5 = PB_4, // NTRST
+ P_TP7 = PA_13, // TMS SWDIO
+ P_TP8 = PA_15, // TDI
+ P_TP9 = PA_14, // TCK SWCLK
+ P_TP10 = PB_3, // TDO
+ //P_TP11, // BOOT0
+
+ // Internal
+ LED1 = PD_9,
+ LED2 = PA_12,
+ LED3 = PD_8,
+ LED4 = PA_11,
+ LED5 = PC_2,
+ LED6 = PA_3,
+ LED7 = PF_6,
+ LED_RED = PE_0,
+ LED_GREEN = PB_6,
+ LED_BLUE = PB_8,
+ SW1 = PF_2,
+ SW2 = PG_4,
+
+ // Standardized button names
+ BUTTON1 = SW1,
+ BUTTON2 = SW2,
+
+ I2C_SDA = PF_0,
+ I2C_SCL = PF_1,
+ SPI0_MOSI = PE_14,
+ SPI0_MISO = PE_13,
+ SPI0_SCK = PE_12,
+ SPI0_CS = PE_11,
+ SPI1_CS = PE_9,
+
+ SPI_MOSI = SPI0_MOSI,
+ SPI_MISO = SPI0_MISO,
+ SPI_SCK = SPI0_SCK,
+ SPI_CS = SPI0_CS,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#elif MBED_CONF_TARGET_USB_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_TX,
+#else
+ STDIO_UART_TX = PA_9,
+#endif
+
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#elif MBED_CONF_TARGET_USB_RX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_RX,
+#else
+ STDIO_UART_RX = PA_10,
+#endif
+
+ // DAPLink
+ USBRX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ SWDIO = PA_15,
+ SWCLK = PA_14,
+ NTRST = PB_4,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,252 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03,
+ PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07,
+ PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B,
+ PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F,
+
+ PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13,
+ PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17,
+ PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B,
+ PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F,
+
+ PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23,
+ PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27,
+ PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B,
+ PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F,
+
+ PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33,
+ PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37,
+ PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B,
+ PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F,
+
+ PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43,
+ PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47,
+ PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B,
+ PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F,
+
+ PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53,
+ PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57,
+ PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B,
+ PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F,
+
+ PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63,
+ PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67,
+ PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B,
+ PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F,
+
+ PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73,
+ PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77,
+ PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B,
+ PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ // Module Pins
+ // PortA
+ P_A1 = NC,
+ P_A2 = NC,
+ P_A3 = NC,
+ P_A4 = NC,
+ P_A5 = PC_2, // UART-DTR
+ P_A6 = PF_2, // Switch-0
+ P_A7 = PE_0, // Red, Mode
+ P_A8 = PB_6, // Green, Switch-1
+ P_A9 = PB_8, // Blue
+ P_A10 = PA_11, // UART-CTS
+ P_A11 = PA_9, // UART-TXD
+ P_A12 = PA_12, // UART-RTS
+ P_A13 = PA_10, // UART-RXD
+ P_A14 = PD_9, // GPIO-0
+ P_A15 = PD_8, // GPIO-1
+ P_A16 = PD_11, // GPIO-2
+ P_A17 = PD_12, // GPIO-3
+ P_A18 = PA_3, // UART-DSR
+ // PortB
+ P_B1 = NC,
+ P_B2 = NC,
+ P_B3 = NC,
+ P_B4 = NC,
+ P_B5 = NC,
+ P_B6 = NC,
+ P_B7 = NC,
+ P_B8 = NC,
+ // PortC
+ P_C1 = NC,
+ P_C2 = NC,
+ P_C3 = NC,
+ P_C4 = NC,
+ P_C5 = PG_4, // SPI-IRQ
+ P_C6 = PE_13, // SPI-MISO
+ P_C7 = NC,
+ P_C8 = PE_12, // Res
+ P_C9 = NC,
+ P_C10 = PE_14, // SPI-MOSI
+ P_C11 = PE_11, // SPI-CS0
+ P_C12 = PE_9, // Res
+ P_C13 = PF_6, // GPIO-4
+ P_C14 = PC_1, // RMII-MDC
+ P_C15 = PA_2, // RMII-MDIO
+ P_C16 = PF_7, // GPIO-7
+ P_C17 = PF_1, // I2C-SCL
+ P_C18 = PF_0, // I2C-SDA
+ // PortD
+ P_D1 = PB_12, // RMII-TXD0
+ P_D2 = PB_13, // RMII-TXD1
+ P_D3 = PB_11, // RMII-TXEN
+ P_D4 = PA_7, // RMII-CRSDV
+ P_D5 = PC_4, // RMII-RXD0
+ P_D6 = PC_5, // RMII-RXD1
+ P_D7 = NC,
+ P_D8 = PA_1, // RMII-REFCLK
+ // TestPads
+ P_TP5 = PB_4, // NTRST
+ P_TP7 = PA_13, // TMS SWDIO
+ P_TP8 = PA_15, // TDI
+ P_TP9 = PA_14, // TCK SWCLK
+ P_TP10 = PB_3, // TDO
+ //P_TP11, // BOOT0
+
+ // Internal
+ LED_RED = PE_0,
+ LED_GREEN = PB_6,
+ LED_BLUE = PB_8,
+
+ LED1 = LED_RED,
+ LED2 = LED_GREEN,
+ LED3 = LED_BLUE,
+
+ SW1 = PF_2,
+ SW2 = PG_4,
+
+ // Standardized button names
+ BUTTON1 = SW1,
+ BUTTON2 = SW2,
+
+ I2C_SDA = PF_0,
+ I2C_SCL = PF_1,
+
+ SPI0_MOSI = PE_14,
+ SPI0_MISO = PE_13,
+ SPI0_SCK = PE_12,
+ SPI0_CS = PE_11,
+ SPI1_CS = PE_9,
+
+ SPI_MOSI = SPI0_MOSI,
+ SPI_MISO = SPI0_MISO,
+ SPI_SCK = SPI0_SCK,
+ SPI_CS = SPI0_CS,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#elif MBED_CONF_TARGET_USB_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_TX,
+#else
+ STDIO_UART_TX = PA_9,
+#endif
+
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#elif MBED_CONF_TARGET_USB_RX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_RX,
+#else
+ STDIO_UART_RX = PA_10,
+#endif
+
+ // DAPLink
+ USBRX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ SWDIO = PA_15,
+ SWCLK = PA_14,
+ NTRST = PB_4,
+
+ // MTB Aliases
+ // Left side (top view)
+ TGT_SWDIO = SWDIO,
+ TGT_SWCLK = SWCLK,
+ TGT_RESET = NTRST,
+ TGT_TX = USBTX,
+ TGT_RX = USBRX,
+ TX1 = P_A15,
+ RX1 = P_A14,
+ SDA1 = P_C18,
+ SCL1 = P_C17,
+ MOSI1 = P_C10,
+ MISO1 = P_C6,
+ SCK1 = SPI_SCK,
+ GP0 = BUTTON1,
+ GP1 = SPI_CS,
+ AIN0 = P_C13,
+ AIN1 = P_A18,
+ AIN2 = P_A5,
+
+ //Right side (top view)
+ GND = NC,
+ GP10 = NC,
+ RTS = NC,
+ CTS = NC,
+ GP7 = P_C12,
+ GP6 = P_A12,
+ GP5 = P_A10,
+ GP4 = P_A17,
+ TX2 = NC,
+ RX2 = NC,
+ SDA2 = NC,
+ SCL2 = NC,
+ MOSI2 = NC,
+ MISO2 = NC,
+ SCK2 = NC,
+ GP3 = P_A16,
+ GP2 = P_C5,
+ PWM2 = LED_GREEN,
+ PWM1 = LED_BLUE,
+ PWM0 = LED_RED,
+
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,213 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03,
+ PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07,
+ PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B,
+ PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F,
+
+ PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13,
+ PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17,
+ PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B,
+ PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F,
+
+ PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23,
+ PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27,
+ PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B,
+ PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F,
+
+ PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33,
+ PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37,
+ PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B,
+ PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F,
+
+ PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43,
+ PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47,
+ PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B,
+ PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F,
+
+ PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53,
+ PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57,
+ PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B,
+ PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F,
+
+ PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63,
+ PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67,
+ PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B,
+ PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F,
+
+ PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73,
+ PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77,
+ PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B,
+ PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F,
+
+ // Module Pins
+ // A
+ P_A5 = PC_2, // UART-DTR
+ P_A6 = PF_2, // Switch-0
+ P_A7 = PE_0, // Red, Mode
+ P_A8 = PB_6, // Green, Switch-1
+ P_A9 = PB_8, // Blue
+ P_A10 = PA_11, // UART-CTS
+ P_A11 = PA_9, // UART-TXD
+ P_A12 = PA_12, // UART-RTS
+ P_A13 = PA_10, // UART-RXD
+ P_A14 = PD_9, // GPIO-0
+ P_A15 = PD_8, // GPIO-1
+ P_A16 = PD_11, // GPIO-2
+ P_A17 = PD_12, // GPIO-3
+ P_A18 = PA_3, // UART-DSR
+ // B
+ // C
+ P_C5 = PG_4, // SPI-IRQ
+ P_C6 = PE_13, // SPI-MISO
+ P_C8 = PE_12, // Res
+ P_C10 = PE_14, // SPI-MOSI
+ P_C11 = PE_11, // SPI-CS0
+ P_C12 = PE_9, // Res
+ P_C13 = PF_6, // GPIO-4
+ P_C14 = PC_1, // RMII-MDC
+ P_C15 = PA_2, // RMII-MDIO
+ P_C16 = PF_7, // GPIO-7
+ P_C17 = PF_1, // I2C-SCL
+ P_C18 = PF_0, // I2C-SDA
+ // D
+ P_D1 = PB_12, // RMII-TXD0
+ P_D2 = PB_13, // RMII-TXD1
+ P_D3 = PB_11, // RMII-TXEN
+ P_D4 = PA_7, // RMII-CRSDV
+ P_D5 = PC_4, // RMII-RXD0
+ P_D6 = PC_5, // RMII-RXD1
+ P_D8 = PA_1, // RMII-REFCLK
+ // TP
+ P_TP5 = PB_4, // NTRST
+ P_TP7 = PA_13, // TMS SWDIO
+ P_TP8 = PA_15, // TDI
+ P_TP9 = PA_14, // TCK SWCLK
+ P_TP10 = PB_3, // TDO
+ //P_TP11, // BOOT0
+
+ // Board Pins
+ // A0-A5
+ A0 = PF_6, // AI4
+ A1 = PA_3, // AI3
+ A2 = PC_2, // AI12
+ A3 = PF_7, // LPOCLK, not AI
+ A4 = PG_4, // not AI
+ A5 = PE_0, // not AI
+ // D0-D15
+ D0 = PD_9, // UART3-RX
+ D1 = PD_8, // UART3-TX
+ D2 = PA_10, // UART1-RX
+ D3 = PA_11, // CAN1-RX
+ D4 = PA_12, // CAN1-TX
+ D5 = PB_8,
+ D6 = PD_11, // UART3-CTS
+ D7 = PD_12, // UART3-RTS
+ D8 = PA_9, // UART1-TX
+ D9 = PE_9, // SDCard-CS
+ D10 = PE_11, // SSEL
+ D11 = PE_14, // MOSI
+ D12 = PE_13, // MISO
+ D13 = PE_12, // SCK
+ D14 = PF_0, // SDA
+ D15 = PF_1, // SCL
+ // Internal
+ LED1 = PE_0, // Red / Mode
+ LED2 = PB_6, // Green / Switch-1
+ LED3 = PB_8, // Blue
+ LED4 = D10,
+ LED_RED = LED1,
+ LED_GREEN = LED2,
+ LED_BLUE = LED3,
+ SW0 = PF_2, // Switch-0
+ SW1 = PB_6, // Green / Switch-1
+
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI0_MOSI = D11,
+ SPI0_MISO = D12,
+ SPI0_SCK = D13,
+ SPI0_CS = D10,
+ SPI1_CS = D9,
+
+ SPI_MOSI = SPI0_MOSI,
+ SPI_MISO = SPI0_MISO,
+ SPI_SCK = SPI0_SCK,
+ SPI_CS = SPI0_CS,
+
+
+ // Standardized button names
+ BUTTON1 = SW0,
+ BUTTON2 = SW1,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#elif MBED_CONF_TARGET_USB_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_TX,
+#else
+ STDIO_UART_TX = D8,
+#endif
+
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#elif MBED_CONF_TARGET_USB_RX
+ STDIO_UART_TX = MBED_CONF_TARGET_USB_RX,
+#else
+ STDIO_UART_RX = D2,
+#endif
+
+ // ST-Link
+ USBRX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ SWDIO = PA_15,
+ SWCLK = PA_14,
+ NTRST = PB_4,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2017, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : HAL
+ * File : hal_overrides.c
+ *
+ * Description : Placeholder for HAL overrides.
+ *-------------------------------------------------------------------------*/
+
+#include "stm32f4xx_hal.h"
+#include "stm32f4xx_hal_rcc.h"
+#include "stm32f4xx_hal_gpio.h"
+
+void HAL_MspInit(void)
+{
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+
+ GPIO_InitTypeDef GPIO_InitDef;
+
+ GPIO_InitDef.Pin = GPIO_PIN_6 | GPIO_PIN_8;
+ GPIO_InitDef.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitDef.Pull = GPIO_NOPULL;
+ GPIO_InitDef.Speed = GPIO_SPEED_FREQ_HIGH;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitDef);
+
+ GPIO_InitDef.Pin = GPIO_PIN_0;
+ HAL_GPIO_Init(GPIOE, &GPIO_InitDef);
+
+ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET);
+ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_8, GPIO_PIN_SET);
+ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, GPIO_PIN_SET);
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,2 @@ +Unless specifically indicated otherwise in a file, files are licensed under the +Permissive Binary License1.0 (PBL-1.0) as can be found in: LICENSE-permissive-binary-license-1.0.txt
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,49 @@ +Permissive Binary License + +Version 1.0, September 2015 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named âDEPENDENCIESâ and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar Binary file mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar has changed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a Binary file mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a has changed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a Binary file mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a has changed
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,288 @@
+/* ODIN-W2 implementation of WiFiInterface
+ * Copyright (c) 2016 u-blox Malmö AB
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ODIN_WIFI_INTERFACE_H
+#define ODIN_WIFI_INTERFACE_H
+
+#include "WiFiInterface.h"
+#ifdef DEVICE_WIFI_AP
+#include "WiFiSoftAPInterface.h"
+#endif
+
+#include "mbed.h"
+#include "netsocket/WiFiAccessPoint.h"
+#include "netsocket/EMACInterface.h"
+#include "nsapi_types.h"
+#include "lwip/netif.h"
+#include "rtos.h"
+#include "cb_wlan.h"
+
+#define ODIN_WIFI_MAX_MAC_ADDR_STR (18)
+#define ODIN_WIFI_SCAN_CACHE_SIZE (5)
+
+struct odin_wifi_msg_s;
+struct user_connect_s;
+struct user_scan_s;
+struct user_ap_start_s;
+struct wlan_status_started_s;
+struct wlan_status_connected_s;
+struct wlan_status_connection_failure_s;
+struct wlan_scan_indication_s;
+
+/** OdinWiFiInterface class
+ * Implementation of the WiFiInterface for the ODIN-W2 module
+ */
+
+class OdinWiFiInterface : public WiFiInterface, public EMACInterface
+
+{
+public:
+ /** OdinWiFiInterface lifetime
+ */
+ OdinWiFiInterface();
+
+ OdinWiFiInterface(bool debug);
+
+ ~OdinWiFiInterface();
+
+ /** Set the WiFi network credentials
+ *
+ * @param ssid Name of the network to connect to
+ * @param pass Security passphrase to connect to the network
+ * @param security Type of encryption for connection
+ * (defaults to NSAPI_SECURITY_NONE)
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE);
+
+ /** Set the WiFi network channel
+ *
+ * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0)
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t set_channel(uint8_t channel);
+
+ /** Start the interface
+ *
+ * Attempts to connect to a WiFi network.
+ *
+ * @param ssid Name of the network to connect to
+ * @param pass Security passphrase to connect to the network
+ * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE)
+ * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0)
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t connect(
+ const char *ssid,
+ const char *pass,
+ nsapi_security_t security = NSAPI_SECURITY_NONE,
+ uint8_t channel = 0);
+
+ /** Start the interface
+ *
+ * Attempts to connect to a WiFi network. Requires ssid and passphrase to be set.
+ * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned.
+ *
+ * @return 0 on success, negative error code on failure
+ */
+ virtual nsapi_error_t connect();
+
+ /** Stop the interface
+ *
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t disconnect();
+
+
+
+
+ /** Gets the current radio signal strength for active connection
+ *
+ * @return Connection strength in dBm (negative value),
+ * or 0 if measurement impossible
+ */
+ virtual int8_t get_rssi();
+
+ /** Scan for available networks
+ *
+ * If the network interface is set to non-blocking mode, scan will attempt to scan
+ * for WiFi networks asynchronously and return NSAPI_ERROR_WOULD_BLOCK. If a callback
+ * is attached, the callback will be called when the operation has completed.
+ *
+ * @param ap Pointer to allocated array to store discovered AP
+ * @param count Size of allocated @a res array, or 0 to only count available AP
+ * @param timeout Timeout in milliseconds; 0 for no timeout (Default: 0)
+ * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error
+ * see @a nsapi_error
+ */
+ virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, nsapi_size_t count);
+
+ /** Sets timeout for connection setup. Note that the time for DHCP retrieval is not included.
+ *
+ * @param timeout Timeout in ms. Use 0 for waiting forever. The timeout might take up to X sec longer than
+ * specified since the Wi-Fi driver might need some time to finish and cleanup.
+ * @return 0 on success, negative error code on failure
+ */
+ virtual nsapi_error_t set_timeout(int ms);
+
+private:
+
+ enum OdinWifiState {
+ S_NOT_INITIALISED = 1,
+ S_WAIT_START,
+ S_STARTED,
+ S_WAIT_STOP,
+
+ S_STA_IDLE,
+ S_STA_WAIT_CONNECT,
+ S_STA_CONNECTED,
+ S_STA_DISCONNECTED_WAIT_CONNECT,
+ S_STA_CONNECTION_FAIL_WAIT_DISCONNECT,
+ //S_STA_LINK_LOSS_WAIT_DISCONNECT,
+ S_STA_WAIT_DISCONNECT,
+
+ S_AP_IDLE,
+ S_AP_WAIT_START,
+ S_AP_STARTED,
+ S_AP_WAIT_STOP,
+ S_AP_FAIL_WAIT_STOP,
+ S_AP_WAIT_DRV_STOP,
+ S_AP_WAIT_DRV_START,
+
+ S_INVALID
+ };
+
+ struct sta_s {
+ const char *ssid;
+ const char *passwd;
+ nsapi_security_t security;
+ uint8_t channel;
+ int timeout_ms;
+ };
+
+ struct ap_s {
+ const char *ssid;
+ const char *passwd;
+ nsapi_security_t security;
+ uint8_t channel;
+ bool use_dhcp;
+
+ char ip_address[IPADDR_STRLEN_MAX];
+ char netmask[IPADDR_STRLEN_MAX];
+ char gateway[IPADDR_STRLEN_MAX];
+
+ int cnt_connected;
+
+ nsapi_error_t error_code;
+ uint16_t beacon_interval;
+ };
+
+ struct scan_cache_s {
+ int count;
+ uint8_t last_channel;
+ cbWLAN_MACAddress bssid[ODIN_WIFI_SCAN_CACHE_SIZE];
+ };
+
+ OdinWifiState entry_connect_fail_wait_disconnect();
+ OdinWifiState entry_wait_connect();
+ OdinWifiState entry_wait_disconnect();
+ //OdinWifiState entry_link_loss_wait_disconnect(void);
+ OdinWifiState entry_ap_wait_start();
+ OdinWifiState entry_ap_started();
+ OdinWifiState entry_ap_wait_stop();
+ OdinWifiState entry_ap_fail_wait_stop();
+ OdinWifiState entry_ap_wait_drv_stop();
+ OdinWifiState entry_ap_wait_drv_start();
+
+ void handle_in_msg();
+ void handle_cached_msg();
+
+ void handle_user_connect(user_connect_s *user_connect);
+ void handle_user_disconnect();
+ void handle_user_scan(user_scan_s *user_scan);
+ void handle_user_connect_timeout();
+ void handle_user_stop();
+
+ void handle_user_ap_start(user_ap_start_s *user_ap_start);
+ void handle_user_ap_stop();
+
+ void handle_wlan_status_started(wlan_status_started_s *start);
+ void handle_wlan_status_stopped(void);
+ void handle_wlan_status_error(void);
+ void handle_wlan_status_connecting(void);
+ void handle_wlan_status_connected(wlan_status_connected_s *wlan_connect);
+ void handle_wlan_status_connection_failure(wlan_status_connection_failure_s *connect_failure);
+ void handle_wlan_status_disconnected(void);
+ void handle_wlan_scan_indication();
+
+ void handle_wlan_status_ap_up();
+ void handle_wlan_status_ap_down();
+
+ void init(bool debug);
+ nsapi_error_t wlan_set_channel(uint8_t channel);
+ nsapi_error_t wlan_connect(
+ const char *ssid,
+ const char *passwd,
+ nsapi_security_t security);
+ nsapi_error_t wlan_ap_start(
+ const char *ssid,
+ const char *pass,
+ nsapi_security_t security,
+ uint8_t channel,
+ uint16_t beacon_interval);
+
+ void timeout_user_connect();
+ void update_scan_list(cbWLAN_ScanIndicationInfo *scan_info);
+ void send_user_response_msg(unsigned int type, nsapi_error_t error_code);
+ void wlan_status_indication(cbWLAN_StatusIndicationInfo status, void *data);
+ void wlan_scan_indication(cbWLAN_ScanIndicationInfo *scan_info, cb_boolean is_last_result);
+
+ static bool _wlan_initialized; // Controls that cbWLAN is initiated only once
+ static int32_t _target_id;
+
+ OdinWifiState _state;
+ OdinWifiState _state_sta;
+ OdinWifiState _state_ap;
+
+ struct sta_s _sta;
+ struct ap_s _ap;
+ char _mac_addr_str[ODIN_WIFI_MAX_MAC_ADDR_STR];
+
+ cbWLAN_StatusConnectedInfo _wlan_status_connected_info;
+ cbWLAN_StatusDisconnectedInfo _wlan_status_disconnected_info;
+
+ bool _scan_active;
+ WiFiAccessPoint *_scan_list;
+ nsapi_size_t _scan_list_size;
+ nsapi_size_t _scan_list_cnt;
+ struct scan_cache_s _scan_cache;
+
+ friend struct wlan_callb_s;
+
+ Mutex _mutex;
+ Queue<odin_wifi_msg_s, 6> _in_queue;
+ Queue<odin_wifi_msg_s, 1> _out_queue;
+ Queue<odin_wifi_msg_s, 1> _cache_queue;
+ MemoryPool<odin_wifi_msg_s, 7> *_msg_pool;
+ Thread _thread;
+ //Timeout _timeout; //Randomly lost interrupts/callbacks; replaced by Timer
+ Timer _timer;
+
+ bool _debug;
+ int _dbg_timeout;
+};
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,216 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component :
+ * File : bt_types.h
+ *
+ * Description : Common Bluetooth types
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file bt_types.h
+ * @brief Common Bluetooth types
+ */
+
+#ifndef _BT_TYPES_H_
+#define _BT_TYPES_H_
+
+#include "cb_comdefs.h"
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+#define SIZE_OF_BD_ADDR (6)
+#define SIZE_OF_COD (3)
+#define SIZE_OF_LINK_KEY (16)
+#define SIZE_OF_NAME_INCOMING (248)
+#define SIZE_OF_NAME_OUTGOING (64)
+#define SIZE_OF_PIN_CODE ((cb_uint8)16)
+#define SIZE_OF_LAP (3)
+#define SIZE_OF_AFH_LMP_HCI_CHANNEL_MAP (10)
+#define CHANNEL_MAP_SIZE (5)
+#define SIZE_OF_EXT_INQ_RSP (240)
+#define MIN_PASSKEY_VALUE (0)
+#define MAX_PASSKEY_VALUE (999999)
+#define INVALID_CONN_HANDLE ((TConnHandle)0xFFFF)
+#define MAX_ADV_DATA_LENGTH (31)
+#define UUID_LENGTH (16)
+
+
+#define PACKET_TYPE_DM1 (0x0008)
+#define PACKET_TYPE_DH1 (0x0010)
+#define PACKET_TYPE_DM3 (0x0400)
+#define PACKET_TYPE_DH3 (0x0800)
+#define PACKET_TYPE_DM5 (0x4000)
+#define PACKET_TYPE_DH5 (0x8000)
+
+#define PACKET_TYPE_NO_2_DH1 (0x0002)
+#define PACKET_TYPE_NO_3_DH1 (0x0004)
+#define PACKET_TYPE_NO_2_DH3 (0x0100)
+#define PACKET_TYPE_NO_3_DH3 (0x0200)
+#define PACKET_TYPE_NO_2_DH5 (0x1000)
+#define PACKET_TYPE_NO_3_DH5 (0x2000)
+
+#define PACKET_TYPE_ALL (PACKET_TYPE_DM1 | PACKET_TYPE_DH1 | PACKET_TYPE_DM3 | PACKET_TYPE_DH3 | PACKET_TYPE_DM5 | PACKET_TYPE_DH5)
+
+#define BD_ADDR_IS_STATIC_RANDOM(BdAddress) ((BdAddress[0] & 0xC0) == 0xC0)
+#define BD_ADDR_IS_NON_RESOLVABLE(BdAddress) ((BdAddress[0] & 0xC0) == 0x00)
+#define BD_ADDR_IS_RESOLVABLE(BdAddress) ((BdAddress[0] & 0xC0) == 0x40)
+
+#define BT_INVALID_STATIC_LINK_KEY (0)
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+typedef cb_int32 int32;
+typedef cb_uint32 uint32;
+typedef cb_boolean boolean;
+typedef cb_int8 int8;
+typedef cb_uint8 uint8;
+typedef cb_int16 int16;
+typedef cb_uint16 uint16;
+
+typedef cb_uint8 TErrorCode;
+typedef cb_uint8 TLinkType;
+typedef cb_uint16 TPacketType;
+typedef cb_uint16 TConnHandle;
+
+typedef enum
+{
+ BT_SECURITY_MODE_1 = 1,
+ BT_SECURITY_MODE_2,
+ BT_SECURITY_MODE_3,
+ BT_SECURITY_MODE_4
+
+} TSecurityMode;
+
+typedef enum
+{
+ BT_SECURITY_LEVEL_0 = 0,
+ BT_SECURITY_LEVEL_1,
+ BT_SECURITY_LEVEL_2,
+ BT_SECURITY_LEVEL_3,
+ // Used with security modes 1,2,3 where security level is not applicable
+ BT_SECURITY_LEVEL_DUMMY = 5,
+
+} TSecurityLevel;
+
+
+typedef enum
+{
+ BT_MASTER_SLAVE_POLICY_ALWAYS_MASTER = 0,
+ BT_MASTER_SLAVE_POLICY_OTHER_SIDE_DECIDE = 1
+
+} TMasterSlavePolicy;
+
+typedef enum
+{
+ BT_TYPE_CLASSIC = 0,
+ BT_TYPE_LOW_ENERGY = 1
+
+} TBluetoothType;
+
+typedef enum
+{
+ BT_PUBLIC_ADDRESS = 0x00,
+ BT_RANDOM_ADDRESS = 0x01,
+
+} TAddressType;
+
+typedef struct
+{
+ cb_uint8 BdAddress[SIZE_OF_BD_ADDR];
+ TAddressType AddrType;
+
+} TBdAddr;
+
+typedef struct
+{
+ cb_uint8 Cod[SIZE_OF_COD];
+
+} TCod;
+
+typedef struct
+{
+ cb_uint8 LinkKey[SIZE_OF_LINK_KEY];
+
+} TLinkKey;
+
+typedef struct
+{
+ cb_uint8 Name[SIZE_OF_NAME_INCOMING];
+
+} TName;
+
+typedef struct
+{
+ cb_uint8 Name[SIZE_OF_NAME_OUTGOING];
+
+} TNameOutgoing;
+
+typedef struct
+{
+ cb_uint8 PinCode[SIZE_OF_PIN_CODE];
+
+} TPinCode;
+
+typedef cb_uint32 TPasskey;
+
+typedef struct
+{
+ cb_uint8 Lap[SIZE_OF_LAP];
+
+} TLap;
+
+typedef struct
+{
+ cb_uint8 Data[SIZE_OF_EXT_INQ_RSP];
+
+} TExtInqRsp;
+
+typedef cb_uint8 TAfhLmpHciChannelMap[SIZE_OF_AFH_LMP_HCI_CHANNEL_MAP];
+
+typedef struct
+{
+ uint16 channel[CHANNEL_MAP_SIZE];
+} TChannelMap;
+
+
+typedef enum
+{
+ BT_ADV_TYPE_ADV = 0x01,
+ BT_ADV_TYPE_SCAN = 0x00,
+} TAdvDataType;
+
+typedef struct
+{
+ TAdvDataType type;
+ cb_uint8 length;
+ cb_uint8 data[MAX_ADV_DATA_LENGTH];
+} TAdvData;
+
+typedef struct
+{
+ cb_uint16 createConnectionTimeout;
+ cb_uint16 connectionIntervalMin;
+ cb_uint16 connectionIntervalMax;
+ cb_uint16 connectionLatency;
+ cb_uint16 linkLossTimeout;
+ cb_uint16 scanInterval;
+ cb_uint16 scanWindow;
+} TAclParamsLe;
+
+#endif /* _BT_TYPES_H */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,94 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Assert
+ * File : cb_assert.h
+ *
+ * Description : ASSERT macro variations.
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_ASSERT_H_
+#define _CB_ASSERT_H_
+
+#include "cb_comdefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/*
+ * Internal platform function declaration.
+ * Shall never be called directly.
+ */
+
+extern void cbOS_error(cb_int32 errorCode, const cb_char *file, cb_uint32 line);
+extern void cbOS_error2(const cb_char *file, cb_uint32 line);
+
+#ifndef NASSERT
+
+#ifndef __CB_FILE__
+ #define __CB_FILE__ __FILE__
+#endif
+
+/*
+ * If the condition (C) evaluates to FALSE, the registered error handler in cbOS
+ * is called with file and line info before the system is reset.
+ */
+
+#define cb_ASSERT(C) do { if(!(C)){cbOS_error2(__CB_FILE__,__LINE__);} } while(0)
+
+#define cb_ASSERTC(C) do { if(!(C)){cbOS_error2(__CB_FILE__ , __LINE__);} } while(0)
+
+#define cb_ASSERT2(C, E) do { if(!(C)){cbOS_error(E, __CB_FILE__ , __LINE__);} } while(0)
+
+/*
+ * The registered error handler is called with the file and line info before a system reset.
+ */
+
+#define cb_EXIT(E) do { cbOS_error(((cb_int32)(E)), __CB_FILE__, __LINE__); } while(0)
+
+
+#else
+
+#define cb_ASSERT(C)
+
+#define cb_ASSERTC(C) do { if(!(C)){cbWD_systemReset();} } while(0) // Critical assert is never removed.
+
+#define cb_ASSERT2(C, E)
+
+#define cb_EXIT(E) do { cbWD_systemReset(); } while(0)
+
+#endif
+
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _cb_ASSERT_H_ */
+
+
+
+
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,878 @@
+/**
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Bluetooth Connection Manager
+ * File : cb_bt_conn_man.h
+ *
+ * Description : Bluetooth Connection Management
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_bt_conn_man.h
+ * @brief Connection management. Functionality for setting up and tearing
+ * down Bluetooth connections. Profile services are also enabled
+ * using this module.
+ */
+
+#ifndef _CB_BT_CONN_MAN_H_
+#define _CB_BT_CONN_MAN_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbBCM_OK (0)
+#define cbBCM_ERROR (-1)
+#define cbBCM_ILLEGAL_HANDLE (-2)
+#define cbBCM_NOT_IMPLEMENTED (-3)
+#define cbBCM_ERROR_DISCONNECTING (-4)
+#define cbBCM_ERROR_ALREADY_REGISTERED (-5)
+#define cbBCM_ERROR_ALREADY_CONNECTED (-6)
+
+#define cbBCM_ACL_CONNECTION_FAILED (-7)
+#define cbBCM_SERVICE_SEARCH_FAILED (-8)
+#define cbBCM_RFCOMM_CONNECTION_FAILED (-9)
+#define cbBCM_SPS_CONNECTION_FAILED (-10)
+#define cbBCM_ACL_DISCONNECTED (-11)
+
+#define cbBCM_INVALID_CONNECTION_HANDLE (cb_UINT32_MAX)
+#define cbBCM_INVALID_SERVER_CHANNEL (cb_UINT8_MAX)
+#define cbBCM_SERVICE_NAME_MAX_LEN (32)
+
+#define cbBCM_DEV_ID_VENDOR_ID_SRC_BLUETOOTH (0x0001)
+#define cbBCM_DEV_ID_VENDOR_ID_SRC_USB (0x0002)
+#define cbBCM_CONNECTBLUE_VENDOR_ID (0x0071)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+typedef cb_uint32 cbBCM_Handle;
+
+typedef enum
+{
+ cbBCM_INVALID_CONNECTION = 0,
+ cbBCM_SPP_CONNECTION, // Serial Port Profile
+ cbBCM_DUN_CONNECTION, // Dial Up Networking Profile
+ cbBCM_UUID_CONNECTION, // UUID
+ cbBCM_PAN_CONNECTION, // PAN
+
+ cbBCM_ACL_LE_CONNECTION, // GATT
+ cbBCM_SPS_CONNECTION // LE connectBlue Serial Service connection
+}cbBCM_ConnectionType;
+
+typedef enum
+{
+ cbBM_LINK_QUALITY_READY_OK,
+ cbBM_LINK_QUALITY_READY_ERROR
+} cbBCM_LinkQualityEvt;
+
+/**
+ * Bluetooth Classic Acl connection parameters
+ */
+typedef struct
+{
+ cb_uint16 pageTimeout; /** Length of connection attempt. Default value 5000ms. */
+ cb_uint16 packetType; /** Packet types allowed in the connection. By default all packets but 3MBit EDR are allowed. */
+ TMasterSlavePolicy masterSlavePolicy; /** Whether master slave switch shall be allowed or not. By default master slave switch is allowed. */
+ cb_uint16 clockOffset; /** Clock offset is part in inquiry response. Using this value may result in faster connection setup Default value 0. */
+ cb_uint16 linkSupervisionTimeout; /** Link supervision timeout. Default value 2000ms. */
+} cbBCM_ConnectionParameters;
+
+/**
+ * Bluetooth Low Energy Acl connection parameters
+ */
+typedef struct
+{
+ cb_uint32 createConnectionTimeout; /** Length of connection attempt in ms. Default value 5000ms. */
+ cb_uint16 connectionIntervalMin; /** Minimum connection interval in ms. Default value 6ms. */
+ cb_uint16 connectionIntervalMax; /** Maximum connection interval in ms. Default value 8ms. */
+ cb_uint16 connectionLatency; /** Slave latency. Default value 0. */
+ cb_uint16 linkLossTimeout; /** Link loss timeout in ms. Default 2000ms. */
+} cbBCM_ConnectionParametersLe;
+
+typedef enum
+{
+ cbBCM_PAN_ROLE_PANU = 0,
+ cbBCM_PAN_ROLE_NAP,
+ cbBCM_PAN_ROLE_NONE
+}cbBCM_PAN_Role;
+
+typedef struct
+{
+ TBdAddr address;
+ TNameOutgoing remoteName;
+ cb_int8 remoteRssi;
+ cbBCM_ConnectionType type;
+ TConnHandle aclHandle;
+ TBluetoothType btType;
+ cb_uint8 serverChannel;
+ cb_uint8 uuid[16] ;
+ cb_boolean uuidValid;
+ cb_char serviceName[cbBCM_SERVICE_NAME_MAX_LEN];
+} cbBCM_ConnectionInfo;
+
+typedef void (*cbBCM_ConnectInd)(
+ cbBCM_Handle handle,
+ cbBCM_ConnectionInfo info);
+
+typedef void (*cbBCM_ConnectEvt)(
+ cbBCM_Handle handle,
+ cbBCM_ConnectionInfo info);
+
+typedef void (*cbBCM_ConnectCnf)(
+ cbBCM_Handle handle,
+ cbBCM_ConnectionInfo info,
+ cb_int32 status);
+
+typedef void (*cbBCM_DisconnectEvt)(
+ cbBCM_Handle handle);
+
+typedef struct
+{
+ cbBCM_ConnectInd pfConnectInd;
+ cbBCM_ConnectEvt pfConnectEvt;
+ cbBCM_ConnectCnf pfConnectCnf;
+ cbBCM_DisconnectEvt pfDisconnectEvt;
+} cbBCM_ConnectionCallback;
+
+typedef void(*cbBCM_RoleDiscoveryCallback)(
+ cbBCM_Handle handle,
+ cb_int8 status,
+ cb_uint8 role);
+
+typedef void (*cbBCM_RssiCallback)(
+ cbBCM_Handle handle,
+ cb_int32 status,
+ cb_int8 rssi);
+
+typedef void (*cbBCM_DataEvt)(
+ cbBCM_Handle handle,
+ cb_uint8 *pBuf,
+ cb_uint32 nBytes);
+
+typedef void (*cbBCM_WriteCnf)(
+ cbBCM_Handle handle,
+ cb_int32 status);
+
+/**
+ * Set max number of Bluetooth links.
+ * Not used by application
+ * @return status TRUE if command was successful
+ */
+typedef cb_int32 (*cbBCM_SetMaxLinksCmd)(cb_uint32 maxLinks);
+
+/**
+ * Check if Handle is free to use
+ * @return TRUE if handle is free, FALSE otherwise
+ */
+typedef cb_boolean (*cbBCM_IsHandleFree)(cbBCM_Handle handle);
+
+/**
+ * Callback to indicate that remaining buffer size needs to be obtained from
+ * upper layer. The callback returns remaining buffer size and there is
+ * therefore no response function.
+ * Not used by application
+ * @return Number of free bytes in channel data buffer
+ */
+typedef cb_uint16 (*cbBCM_RemainBufSizeInd)(void);
+
+typedef struct
+{
+ cbBCM_ConnectEvt pfConnectEvt;
+ cbBCM_DisconnectEvt pfDisconnectEvt;
+ cbBCM_DataEvt pfDataEvt;
+ cbBCM_WriteCnf pfWriteCnf;
+ cbBCM_SetMaxLinksCmd pfSetMaxLinks;
+ cbBCM_RemainBufSizeInd pfRemainBufSizeInd;
+ cbBCM_IsHandleFree pfIsHandleFree;
+} cbBCM_DataCallback;
+
+typedef void (*cbBCM_ServiceSearchCompleteCallback)(cb_int32 status);
+
+typedef void (*cbBCM_ServiceSearchSppCallback)(
+ cb_uint8 serverChannel,
+ cb_char *pServiceName);
+
+typedef void (*cbBCM_ServiceSearchDunCallback)(
+ cb_uint8 serverChannel,
+ cb_char *pServiceName);
+
+typedef void (*cbBCM_ServiceSearchDeviceIdCallback)(
+ cb_uint16 didSpecVersion,
+ cb_uint16 didVendorId,
+ cb_uint16 didProductId,
+ cb_uint16 didProductVersion,
+ cb_boolean didPrimaryService,
+ cb_uint16 didVendorIdSource);
+
+typedef void(*cbBCM_LinkQualityCallback)(
+ cbBCM_LinkQualityEvt linkQualityEvt,
+ uint8 linkQuality);
+
+typedef void(*cbBCM_ServiceClassEnabled)(cb_uint8 serviceChannel);
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+/**
+ * Initialization of connection manager. Called during stack
+ * initialization. Shall not be called by application.
+ *
+ * @return None
+ */
+extern void cbBCM_init(void);
+
+/**
+ * Enable a Bluetooth Serial Port Profile (SPP)service record to
+ * allow other devices to connect to this device using SPP.
+ *
+ * @param pServiceName The name of the service
+ * @param pServerChannel Pointer to return variable. The server channel is used to identify
+ * incoming connections.
+ * @param pConnectionCallback Callback structure for connection management.
+ * @param pServiceClassEnabled Callback structure to inform when service is running.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableServerProfileSpp(
+ cb_char *pServiceName,
+ cb_uint8 *pServerChannel,
+ cbBCM_ConnectionCallback *pConnectionCallback,
+ cbBCM_ServiceClassEnabled pServiceClassEnabled);
+
+/**
+ * Enable a Dial Up Networking Profile (DUN)service record to
+ * allow other devices to connect to this device using DUN.
+ *
+ * @param pServiceName The name of the service
+ * @param pServerChannel Pointer to return variable. The server channel is used to identify
+ * incoming connections.
+ * @param pConnectionCallback Callback structure for connection management.
+ * @param pServiceClassEnabled Callback structure to inform when service is running.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableServerProfileDun(
+ cb_char *pServiceName,
+ cb_uint8 *pServerChannel,
+ cbBCM_ConnectionCallback *pConnectionCallback,
+ cbBCM_ServiceClassEnabled pServiceClassEnabled);
+
+/**
+ * Enable a service record with an application specific UUID.
+ * This is used to enable Android and iOS support.
+ *
+ * @param pUuid128 The UUID of the service.
+ * @param pServiceName The name of the service
+ * @param pServerChannel Pointer to return variable. The server channel is used to identify
+ * incoming connections.
+ * @param pConnectionCallback Callback structure for connection management.
+ * @param pServiceClassEnabled Callback structure to inform when service is running.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableServerProfileUuid128(
+ cb_uint8 *pUuid128,
+ cb_char *pServiceName,
+ cb_uint8 *pServerChannel,
+ cbBCM_ConnectionCallback *pConnectionCallback,
+ cbBCM_ServiceClassEnabled pServiceClassEnabled);
+
+/**
+* Registers the server role of the local device. If role is cbBCM_PAN_ROLE_NAP a service
+* record will be registred in the local service data base. The local device can only act as a
+* PAN NAP or Pan user at a time. If PAN NAP is enabled the device will only accept incoming
+* connections from PAN users. If PAN user is enabled it is only possible to be connected to
+* one remote PAN NAP device.
+*
+* @param pServiceName The name of the service
+* @param role The PAN role of the local device
+* @param pConnectionCallback Callback structure for connection management.
+* @param pServiceClassEnabled Callback structure to inform when service is running.
+* @return If the operation is successful cbBCM_OK is returned.
+*/
+extern cb_int32 cbBCM_enableServerProfilePan(
+ cb_char *pServiceName,
+ cbBCM_PAN_Role role,
+ cbBCM_ConnectionCallback *pConnectionCallback,
+ cbBCM_ServiceClassEnabled pServiceClassEnabled);
+
+/**
+ * Enable device id service record.The device id service record is a method by which
+ * Bluetooth devices may provide information that may be used by peer Bluetooth devices
+ * to find representative icons or load associated support software.
+ * This information is published as Bluetooth SDP records, and optionally in the
+ * Extended Inquiry Response.
+ * @param vendorId Uniquely identifier for the vendor of the device. Used in conjunction with required attribute 0x0205, VendorIDSource, which determines which organization assigned the VendorID value. Note: The Bluetooth Special Interest Group assigns Device ID Vendor ID and the USB Implementer's Forum assigns vendor IDs, either of which can be used for the VendorID value here. Device providers should procure the vendor ID from the USB Implementer's Forum or the Company Identifier from the Bluetooth SIG. The VendorID '0xFFFF' is reserved as the default VendorID when no Device ID Service Record is present in the device.
+ * @param productId This is intended to distinguish between different products made by the vendor above. These IDs are managed by the vendors themselves.
+ * @param version A numeric expression identifying the device release number in Binary-Coded Decimal. This is a vendor-assigned field, which defines the version of the product identified by the VendorID and ProductID attributes. This attribute is intended to differentiate between versions of products with identical VendorIDs and ProductIDs. The value of the field is 0xJJMN for version JJ.M.N (JJ - major version number, M - minor version number, N - sub-minor version number); e.g., version 2.1.3 is represented with value 0x0213 and version 2.0.0 is represented with a value of 0x0200. When upward-compatible changes are made to the device, it is recommended that the minor version number be incremented. If incompatible changes are made to the device, it is recommended that the major version number be incremented.
+ * @param vendorIdSource Organization that assigned the VendorID attribute. Use 0x0001 for Bluetooth SIG assigned Device ID Vendor ID value from the Assigned Numbers document and 0x0002 for USB Implementer's Forum assigned Vendor ID value
+ * @return If the operation is successful cbBCM_OK is returned. Note that only one device id service record can be registered.
+ */
+extern cb_int32 cbBCM_enableDeviceIdServiceRecord(
+ cb_uint16 vendorId,
+ cb_uint16 productId,
+ cb_uint16 version,
+ cb_uint16 vendorIdSource);
+
+/**
+ * Set Bluetooth watchdog settings
+ *
+ * @param disconnectReset Reset the device on any dropped Bluetooth connection
+ * @return void
+ */
+extern void cbBCM_setBluetoothWatchdogValue(cb_uint32 disconnectReset);
+
+/**
+ * Set the packet types to use. Call cbBCM_cmdChangePacketType()
+ * to start using the new packet types.
+ *
+ * @param packetType See packet types in bt_types.h
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_uint32 cbBCM_setPacketType(cb_uint16 packetType);
+
+/**
+ * Get BT classic packet type.
+ *
+ * @return Allowed packet types returned.
+ */
+extern cb_uint16 cbBCM_getPacketType(void);
+
+/**
+ * Set max number of Bluetooth classic links. Reconfigures buffer management.
+ *
+ * @param maxLinks Max number of Bluetooth classic connections.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_setMaxLinksClassic(cb_uint16 maxLinks);
+
+/**
+ * Get max number of Bluetooth classic links.
+ *
+ * @return The maximum number of Bluetooth classic links.
+ */
+extern cb_uint16 cbBCM_getMaxLinksClassic(void);
+
+/**
+ * Set max number of Bluetooth Low Energy links. Reconfigures buffer management.
+ *
+ * @param maxLinks Max number of Bluetooth Low Energy connections.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_setMaxLinksLE(cb_uint16 maxLinks);
+
+/**
+ * Get max number of Bluetooth Low Energy links.
+ *
+ * @return The maximum number of Bluetooth Low Energy links.
+ */
+extern cb_uint16 cbBCM_getMaxLinksLE(void);
+
+/**
+ * Initiate a Bluetooth Serial Port Profile connection.
+ * The connection sequence includes ACL connection setup, SDP service
+ * search and RFCOMM connection setup. The server channel of the first
+ * valid SPP service record will be used. A pfConnectCnf callback will
+ * be received when the connection is complete.The error code in the
+ * callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * @param pAddress Pointer to address of remote device.
+ * @param pServiceName Name of SPP service. Automatic service search
+ * is performed to find a service with matching name.
+ * If set to NULL then the last of the SPP services
+ * on the remote device will be used. If serverChannel
+ * parameter is different than cbBCM_INVALID_SERVER_CHANNEL
+ * this parameter is ignored and the specified server channel
+ * will be used.
+ * @param serverChannel RFCOMM server channel that shall be used. Set to
+ * cbBCM_INVALID_SERVER_CHANNEL to perform automatic
+ * service search to find the server channel.
+ * @param pRemoteName Pointer used in case user connects to the Bluetooth name
+ * @param pAclParameters Link configuration including link supervision timeout
+ * and master slave policy. Pass NULL to use default connection
+ * parameters.
+ * @param pConnectionCallback Callback structure for connection management.
+ * @return If the operation is successful the connection handle is returned. If
+ * not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectSpp(
+ TBdAddr *pAddress,
+ cb_char *pServiceName,
+ cb_uint8 serverChannel,
+ cb_char *pRemoteName,
+ cbBCM_ConnectionParameters *pAclParameters,
+ cb_boolean qosEnable,
+ cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Accept or reject an incoming SPP connection. This is a
+ * response to a cbBCM_ConnectInd connection indication.
+ *
+ * @param handle Connection handle
+ * @param accept TRUE to accept the incoming connection.
+ FALSE to reject.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_rspConnectSppCnf(
+ cbBCM_Handle handle,
+ cb_boolean accept);
+
+/**
+ * Initiate a Bluetooth Dial Up Networking Profile connection.
+ * The connection sequence includes ACL connection setup, SDP service
+ * search and RFCOMM connection setup. The server channel of the first
+ * valid SPP service record will be used. A pfConnectCnf callback will
+ * be received when the connection is complete.The error code in the
+ * callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * @param pAddress Pointer to address of remote device.
+ * @param pServiceName Name of DUN service. Automatic service search
+ * is performed to find a service with matching name.
+ * If set to NULL then the last of the DUN services
+ * on the remote device will be used. If serverChannel
+ * parameter is different than cbBCM_INVALID_SERVER_CHANNEL
+ * this parameter is ignored and the specified server channel
+ * will be used.
+ * @param serverChannel RFCOMM server channel that shall be used. Set to
+ * cbBCM_INVALID_SERVER_CHANNEL to perform automatic
+ * service search to find the server channel.
+ * @param pAclParameters Link configuration including link supervision timeout
+ * and master slave policy. Pass NULL to use default connection
+ * parameters.
+ * @param pConnectionCallback Callback structure for connection management.
+ * @return If the operation is successful the connection handle is returned. If
+ * not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectDun(
+ TBdAddr *pAddress,
+ cb_char *pServiceName,
+ cb_uint8 serverChannel,
+ cbBCM_ConnectionParameters *pAclParameters,
+ cb_boolean qosEnable,
+ cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Accept or reject an incoming DUN connection. This is a
+ * response to a cbBCM_ConnectInd connection indication.
+ *
+ * @param handle Connection handle
+ * @param accept TRUE to accept the incoming connection.
+ FALSE to reject.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_rspConnectDunCnf(
+ cbBCM_Handle handle,
+ cb_boolean accept);
+
+/**
+ * Initiate a Bluetooth Serial Port Profile connection with a specific UUID.
+ * The connection sequence includes ACL connection setup, SDP service
+ * search and RFCOMM connection setup. The server channel of the first
+ * valid SPP service record with the specified UUID will be used. A pfConnectCnf
+ * callback will be received when the connection is complete.The error code in the
+ * callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * @param pAddress Pointer to address of remote device.
+ * @param pUuid Pointer to uuid of the remote service.
+ * @param pServiceName Name of SPP service. Automatic service search
+ * is performed to find a service with matching name.
+ * If set to NULL then the last of the SPP services
+ * on the remote device will be used. If serverChannel
+ * parameter is different than cbBCM_INVALID_SERVER_CHANNEL
+ * this parameter is ignored and the specified server channel
+ * will be used.
+ * @param serverChannel RFCOMM server channel that shall be used. Set to
+ * cbBCM_INVALID_SERVER_CHANNEL to perform automatic
+ * service search to find the server channel.
+ * @param pAclParameters Link configuration including link supervision timeout
+ * and master slave policy. Pass NULL to use default connection
+ * parameters.
+ * @param pConnectionCallback Callback structure for connection management.
+ * @return If the operation is successful the connection handle is returned. If
+ * not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectUuid(
+ TBdAddr *pAddress,
+ cb_uint8 *pUuid,
+ cb_char *pServiceName,
+ cb_uint8 serverChannel,
+ cbBCM_ConnectionParameters *pAclParameters,
+ cb_boolean qosEnable,
+ cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Accept or reject an incoming SPP connection. This is a
+ * response to a cbBCM_ConnectInd connection indication.
+ *
+ * @param handle Connection handle
+ * @param accept TRUE to accept the incoming connection.
+ * FALSE to reject.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_rspConnectUuidCnf(
+ cbBCM_Handle handle,
+ cb_boolean accept);
+
+/**
+ * Initiate a Bluetooth PAN Profile connection.
+ * The connection sequence includes ACL connection setup and L2CAP connection setup.
+ * A pfConnectCnf callback will be received when the connection is complete.
+ * The error code in the*callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ *
+ * @param pAddress Pointer to address of remote device.
+ * @param remoteRole PAN role of the remote device
+ * @param localRole PAN role of the local device
+ * @param pAclParams Link configuration including link supervision timeout
+ * and master slave policy. Pass NULL to use default connection
+ * parameters.
+ * @param pConnectionCallback Callback structure for connection management.
+ * @return If the operation is successful the connection handle is returned. If
+ * not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectPan(
+ TBdAddr *pAddress,
+ cbBCM_PAN_Role remoteRole,
+ cbBCM_PAN_Role localRole,
+ cbBCM_ConnectionParameters *pAclParams,
+ cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Accept or reject an incoming PAN connection. This is a
+ * response to a cbBCM_ConnectInd connection indication.
+ *
+ * @param handle Connection handle
+ * @param accept TRUE to accept the incoming connection.
+ * FALSE to reject.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_rspConnectPan(
+ cbBCM_Handle handle,
+ cb_boolean accept);
+
+/**
+ * Enable Serial Port Service.
+ * When the device is acting Bluetooth Low Energy peripheral the Serial
+ * Port Service will be added to the attribute table.
+ *
+ * @param pConnectionCallback Callback structure for connection management.
+ * @return If the operation is successful cbBCM_OK is returned.
+ * @param pConnectionCallback Callback structure for connection management.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableSps(
+ cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Enable or disable Bluetooth low energy auto connect.
+ * When the device is acting as central and auto connect is enabled it runs
+ * passive scan and initiates an ACL connection to devices that performs
+ * directed advertisements.
+ * The serial port service muast be enabled using cbBCM_enableSps() before
+ * auto connect is enabled.
+ * If SPS is enabled the SPS Gatt client will initiate a SPS connection
+ * attempt on the ACL connection.
+ * When the device is acting peripheral this functionality is inactive.
+ *
+ * @param enable Set to TRUE to enable. Set to false to disable.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_autoConnect(
+ cb_boolean enable);
+
+/**
+ * Initiate a Serial Port Service connection.
+ * The connection sequence includes ACL connection setup , GATT service
+ * search and Serial Port Service connection setup. A connect confirm
+ * callback will be received when the connection is complete. The error
+ * code in the callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * The serial port service must be enabled using cbBCM_enableSps() before
+ * auto connect request is made..
+ * @param pAddress Address of remote device.
+ * @param pAclLeParams Link configuration parameters
+ * @param pConnectionCallback Callback structure for connection management.
+ * @return If the operation is successful the connection handle is returned. If
+ * not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectSps(
+ TBdAddr *pAddress,
+ cb_char *pRemoteName,
+ cbBCM_ConnectionParametersLe *pAclLeParams,
+ cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Accept or reject an incoming SPS connection. This is a
+ * response to a cbBCM_ConnectInd connection indication.
+ * @param handle Connection handle
+ * @param accept TRUE to accept the incoming connection.
+ * FALSE to reject.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_rspConnectSpsCnf(
+ cbBCM_Handle handle,
+ cb_boolean accept);
+
+/**
+ * Initiate a Bluetooth low energy ACL connection. The ACL connection is
+ * intended for GATT communication.
+ * A connect confirm callback will be received when the connection is complete. The error
+ * code in the callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * @param pAddress Address of remote device.
+ * @param pAclLeParams Link configuration parameters
+ * @param pConnectionCallback Callback structure for connection management.
+ * @return If the operation is successful the connection handle is returned. If
+ * not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectAclLe(
+ TBdAddr *pAddress,
+ cbBCM_ConnectionParametersLe *pAclLeParams,
+ cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * @brief Initiate disconnection of active connection. A disconnect event
+ * will be received when the disconnection is complete.
+ *
+ * @param handle Connection handle
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_cmdDisconnect(
+ cbBCM_Handle handle);
+
+/**
+ * @brief Initiate a Serial Port Profile (SPP) service search to find server channel and service name.
+ * @param pAddress Address of device on which service search shall be performed.
+ * @param maxServices Max number of services
+ * @param pCallback Callback used to notify each found service record
+ * @param pCompleteCallback Callback used to notify that the search is completed
+ * @return If the operation is successful initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_reqServiceSearchSpp(
+ TBdAddr *pAddress,
+ cb_uint16 maxServices,
+ cbBCM_ServiceSearchSppCallback pCallback,
+ cbBCM_ServiceSearchCompleteCallback pCompleteCallback);
+
+/**
+ * @brief Initiate a Dial Up Networking (DUN) service search to find server channel and service name.
+ * @param pAddress Address of device on which service search shall be performed.
+ * @param maxServices Max number of services
+ * @param pCallback Callback used to notify each found service record
+ * @param pCompleteCallback Callback used to notify that the search is completed
+ * @return If the operation is successful initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_reqServiceSearchDun(
+ TBdAddr *pAddress,
+ cb_uint16 maxServices,
+ cbBCM_ServiceSearchSppCallback pCallback,
+ cbBCM_ServiceSearchCompleteCallback pCompleteCallback);
+
+/**
+ * @brief Initiate a UUID service search to find server channel and service name.
+ * @param pAddress Address of device on which service search shall be performed.
+ * @param pUuid128 128 UUID to search for.
+ * @param maxServices Max number of services
+ * @param pCallback Callback used to notify each found service record
+ * @param pCompleteCallback Callback used to notify that the search is completed
+ * @return If the operation is successful initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_reqServiceSearchUuid(
+ TBdAddr *pAddress,
+ const cb_uint8 *pUuid128,
+ cb_uint16 maxServices,
+ cbBCM_ServiceSearchSppCallback pCallback,
+ cbBCM_ServiceSearchCompleteCallback pCompleteCallback);
+
+/**
+ * @brief Initiate a Device information service search.
+ * @param pAddress Address of device on which service search shall be performed.
+ * @param maxServices Max number of services
+ * @param pCallback Callback used to notify each found service record
+ * @param pCompleteCallback Callback used to notify that the search is completed
+ * @return If the operation is successful initiated cbBCM_OK is returned.
+ */
+cb_int32 cbBCM_reqServiceSearchDeviceId(
+ TBdAddr *pAddress,
+ cb_uint16 maxServices,
+ cbBCM_ServiceSearchDeviceIdCallback pCallback,
+ cbBCM_ServiceSearchCompleteCallback pCompleteCallback);
+
+/**
+ * @brief Get local Master/Slave role in an active connection.
+ * @param bdAddr address to the connection
+ * @param roleDiscoveryCallback Callback function used to notify the role
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_RoleDiscovery(
+ TBdAddr bdAddr,
+ cbBCM_RoleDiscoveryCallback roleDiscoveryCallback);
+
+/**
+ * @brief Get current Received Signal Strength Indication (RSSI)
+ * of an active connection.
+ * @param bdAddress bt address to the connected device
+ * @param rssiCallback Callback function used to notify the rssi value
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_getRssi(
+ TBdAddr bdAddress,
+ cbBCM_RssiCallback rssiCallback);
+
+/*
+ * Read the LinkQuality .
+ * @return status as int32.
+ * @cbBM_LinkQualityCallback is used to provide result.
+ */
+extern cb_int32 cbBCM_GetLinkQuality(TBdAddr bdAddr, cbBCM_LinkQualityCallback linkQualityCallback);
+
+/**
+ * @brief Change the packet types currently used for an active Bluetooth
+ * Classic connection.
+ * @param handle Connection handle
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_cmdChangePacketType(
+ cbBCM_Handle handle);
+
+/**
+ * @brief Get the current connection parameters for an active Bluetooth
+ * Low Energy ACL connection.
+ * @param handle Connection handle
+ * @param pConnectionInterval Connection interval
+ * @param pConnectionLatency Connection latency
+ * @param pLinkSupervisionTmo Link supervision timeout
+ * @return If the update is successfully initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_getConnectionParams(
+ cbBCM_Handle handle,
+ cb_uint16 *pConnectionInterval,
+ cb_uint16 *pConnectionLatency,
+ cb_uint16 *pLinkSupervisionTmo);
+
+/**
+ * @brief Update connection parameters for an active Bluetooth
+ * Low Energy ACL connection.
+ * @param handle Connection handle
+ * @param pAclLeParams New Link configuration parameters
+ * @return If the update is successfully initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_updateConnectionParams(
+ cbBCM_Handle handle,
+ cbBCM_ConnectionParametersLe *pAclLeParams);
+
+/**
+ * Register a GATT device information service. The device information service
+ * is used by remote devices to get for example the model and firmware version
+ * of this device.
+ * Note that an application easily can define and register its own device information
+ * service if other characteristics are required.
+ * @param pManufacturer String defining the manufacturer.
+ * @param pModel String defining the device model.
+ * @param pFwVersion String defining the firmware version.
+ * @param startIndex Start index of the attribute database for the device info service.
+ * Note that this must not change during the lifetime of the product.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableDevInfoService(
+ const cb_char *pManufacturer,
+ const cb_char *pModel,
+ const cb_char *pFwVersion,
+ cb_uint16 startIndex);
+
+/**
+ * @brief Get the address of the remote device on an
+ * active connection
+ *
+ * @param handle Connection handle
+ * @return Address of the remote device.
+ */
+extern TBdAddr cbBCM_getAddress(cbBCM_Handle handle);
+
+/**
+ * @brief Register a data manager for a type of connections. Shall not be
+ * used by the application. Only used by data managers.
+ *
+ * @param type Connection type.
+ * @param pDataCallback Data callback
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_registerDataCallback(
+ cbBCM_ConnectionType type,
+ const cbBCM_DataCallback *pDataCallback);
+
+/**
+ * @brief Get the protocol handle for an active connection. Shall not be used
+ * by the application. Only used by data managers.
+ *
+ * @param handle Connection handle
+ * @return If the operation is not successful cbBCM_INVALID_CONNECTION_HANDLE
+ * is returned. If the operation is successful the protocol handle is
+ * returned.
+ */
+extern cbBCM_Handle cbBCM_getProtocolHandle(
+ cbBCM_Handle handle);
+
+/**
+ * @brief Get the bcm id from acl handle for an active connection.
+ *
+ * @param handle Connection handle
+ * @return bcm handle.
+ */
+extern cbBCM_Handle cbBCM_getIdFromAclHandle(TConnHandle aclHandle);
+
+/**
+ * @brief Get the acl handle from bcm handle.
+ *
+ * @param handle bcm handle
+ * @return acl handle
+ */
+extern TConnHandle cbBCM_getAclFromIdHandle(cbBCM_Handle bcmHandle);
+
+/**
+ * @brief Set active poll mode to introduce periodic BT classic link polling.
+ * @param mode Active poll mode 0=disable, 1=enable (default period), 2-UINT16_MAX: period of poll
+ * @return If the update is successfully initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_setActivePollMode(cb_uint16 mode);
+
+/**
+ * @brief Get active poll mode.
+ * @return Active poll mode 0=disable, 1=enable
+ */
+extern cb_uint16 cbBCM_getActivePollMode(void);
+
+/**
+ * @brief Change which packet types can be used for the connection identified by the handle
+ * @param handle Connection handle
+ * @param aclPacketType bit map according to packet types defined in bt_types.h
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_changeConnectionPacketType(
+ cbBCM_Handle handle,
+ TPacketType aclPacketType);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _CB_BT_CONN_MAN_H_ */
\ No newline at end of file
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1024 @@
+/*
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Bluetooth Manager
+ * File : cb_bt_man.h
+ *
+ * Description : General Bluetooth functionality
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_bt_man.h
+ *
+ * @brief General Bluetooth functionality. This includes initialization of
+ * the Bluetooth radio and stack, handling properties such as device
+ * name, scanning for other devices using inquiry or Bluetooth Low Energy
+ * scan and more.
+ */
+
+#ifndef _CB_BT_MAN_H_
+#define _CB_BT_MAN_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+* DEFINES
+*=========================================================================*/
+#define cbBM_OK (0)
+#define cbBM_ERROR (-1)
+#define cbBM_MAX_OUTPUT_POWER (127)
+
+#define cbBM_ADV_CHANNEL_MAP_CH_37_BIT 0x01
+#define cbBM_ADV_CHANNEL_MAP_CH_38_BIT 0x02
+#define cbBM_ADV_CHANNEL_MAP_CH_39_BIT 0x04
+#define cbBM_ADV_CHANNEL_MAP_ALL (cbBM_ADV_CHANNEL_MAP_CH_37_BIT | cbBM_ADV_CHANNEL_MAP_CH_38_BIT | cbBM_ADV_CHANNEL_MAP_CH_39_BIT)
+/*===========================================================================
+* TYPES
+*=========================================================================*/
+
+extern const TBdAddr invalidBdAddress;
+
+typedef enum
+{
+ cbBM_INQUIRY_GENERAL = 0,
+ cbBM_INQUIRY_LIMITED = 1,
+} cbBM_InquiryType;
+
+typedef void(*cbBM_TIStatusCallback)(
+ cb_int32 status,
+ cb_int8 temperature);
+
+typedef void (*cbBM_InquiryEventCallback)(
+ TBdAddr *pBdAddress,
+ TCod cod,
+ cb_uint16 clockOffset,
+ cb_int8 rssi,
+ cb_char *pName,
+ TExtInqRsp* pExtInqRsp,
+ cb_uint8 length);
+
+typedef void (*cbBM_InquiryCompleteCallback)(
+ cb_int32 status);
+
+typedef void (*cbBM_RemoteNameCallback)(
+ TBdAddr *pBdAddress,
+ TName *pName,
+ cb_int32 status);
+
+typedef enum
+{
+ cbBM_DEVICE_DISCOVERY_LE_ALL = 0, // Limited size filtering to reduce duplicate results (for devices in filter).
+ cbBM_DEVICE_DISCOVERY_LE_GENERAL,
+ cbBM_DEVICE_DISCOVERY_LE_LIMITED,
+ cbBM_DEVICE_DISCOVERY_LE_ALL_NO_FILTERING // No found devices filtered out due to previously found
+} cbBM_DeviceDiscoveryTypeLe;
+
+typedef enum
+{
+ cbBM_ACTIVE_SCAN = 0,
+ cbBM_PASSIVE_SCAN = 1
+} cbBM_ScanTypeLe;
+
+
+typedef void (*cbBM_DeviceDiscoveryLeEventCallback)(
+ TBdAddr *pBdAddress, // Bluetooth address
+ cb_int8 rssi, // Tx power in dBm
+ cb_char *pName, // Remote name as null terminated string
+ TAdvData *pAdvData); // Advertisment data of remote device
+
+typedef void (*cbBM_DeviceDiscoveryLeCompleteCallback)(
+ cb_int32 status);
+
+typedef enum
+{
+ cbBM_DISCOVERABLE_MODE_NONE = 0,
+ cbBM_DISCOVERABLE_MODE_LIMITED = 1,
+ cbBM_DISCOVERABLE_MODE_GENERAL = 2,
+} cbBM_DiscoverableMode;
+
+typedef enum
+{
+ cbBM_CONNECTABLE_MODE_NOT_CONNECTABLE = 0,
+ cbBM_CONNECTABLE_MODE_CONNECTABLE
+} cbBM_ConnectableMode;
+
+typedef enum
+{
+ cbBM_DISCOVERABLE_MODE_LE_NONE = 0,
+ cbBM_DISCOVERABLE_MODE_LE_LIMITED = 1,
+ cbBM_DISCOVERABLE_MODE_LE_GENERAL = 2,
+} cbBM_DiscoverableModeLe;
+
+typedef enum
+{
+ cbBM_CONNECTABLE_MODE_LE_NOT_CONNECTABLE = 0,
+ cbBM_CONNECTABLE_MODE_LE_CONNECTABLE
+} cbBM_ConnectableModeLe;
+
+typedef enum
+{
+ cbBM_SET_CHANNEL_MAP_CNF_POS,
+ cbBM_SET_CHANNEL_MAP_CNF_NEG,
+} cbBM_ChannelMapEvt;
+
+typedef void (*cbBM_ChannelMapCallb)(
+ cbBM_ChannelMapEvt chMapEvt,
+ TChannelMap *pChMap); // Channel map bit mask
+
+typedef void (*cbBM_InitComplete)(void);
+typedef void(*cbBM_LocalAddressCb)(void);
+
+typedef enum
+{
+ cbBM_LE_ROLE_DISABLED = 0,
+ cbBM_LE_ROLE_CENTRAL = 1,
+ cbBM_LE_ROLE_PERIPHERAL = 2,
+} cbBM_LeRole;
+
+/**
+ * Bluetooth Manager initialization parameters.
+ */
+typedef struct
+{
+ TBdAddr address; /** Bluetooth address that shall be assigned to controller. Pass invalidBdAddress to use controller default address*/
+ cbBM_LeRole leRole; /** Bluetooth low energy role */
+ cb_int8 maxOutputPower; /** Maximum output power. */
+ cb_int32 nvdsStartIdLinkKeysClassic; /** Start id for CLASSIC link keys storage in NVDS. */
+ cb_int32 maxLinkKeysClassic; /** Max number of CLASSIC link keys */
+ cb_int32 nvdsStartIdLinkKeysLe; /** Start id for BLE link keys storage in NVDS. */
+ cb_int32 maxLinkKeysLe; /** Max number of link keys BLE*/
+} cbBM_InitParams;
+
+typedef void(*cbBM_ServiceEnabled)(cb_uint8 serviceChannel);
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Initialize the Bluetooth Radio, the connectBlue Embedded Bluetooth
+ * Stack and the Bluetooth Manager.
+ * The init complete callback is used to notify when the initialization is
+ * complete. During initialization default values are set for all properties.
+ * The application shall set desired values for the main Bluetooth properties
+ * such as local name after the initialization is complete. After init the device
+ * is non discoverable and non connectable.
+ *
+ * @param pInitParameters Init parameters
+ * @param initCompleteCallback Callback used to notify when the initialization is complete.
+ * @param pBtReadyCallback Callback used to notify when the customized Bluetooth
+ * initialization is ready.
+ * @return None
+ */
+extern void cbBM_init(
+ cbBM_InitParams *pInitParameters,
+ cbBM_InitComplete initCompleteCallback);
+
+/**
+ * This function executes cbBM_setQosParams command according to parameters.
+ * @param connectConfig decides whether to turn off connectability and discoverability
+ * when max links are reached.
+ * @param qosConfig QoS enable=1, disable=0
+ * @param connectConfig QoS "off during connection"=0, "on during connection"=1
+ * @return true if in parameters are valid.
+ */
+extern cb_int32 cbBM_setQosParams(
+ cb_uint8 qosConfig,
+ cb_uint8 connectConfig);
+
+/**
+ * This function sets the link supervision timeout in LLC.
+ * @param linkSupervisionTimeout in milliseconds
+ * @return true if in parameter is valid.
+ */
+extern cb_int32 cbBM_setLinkSupervisionTimeout(
+ cb_uint16 linkSupervisionTimeout);
+
+/**
+ * This function gets the link supervision timeout from LLC.
+ * @return link supervision timeout in milliseconds
+ */
+extern cb_uint16 cbBM_getLinkSupervisionTimeout(void);
+
+/**
+ * This function enables or disables the fast connect feature (interlaced page scan).
+ * @param fastConnect enable=TRUE, disable=FALSE
+ * @return cbBM_OK if in parameter is valid.
+ */
+extern cb_int32 cbBM_setFastConnect(
+ cb_boolean fastConnect);
+/**
+ * This function gets whether the fast connect feature is enabled or disabled.
+ * @return fast connect; enabled=TRUE, disabled=FALSE
+ */
+extern cb_boolean cbBM_getFastConnect(void);
+
+/**
+ * This function enables or disables the fast discovery feature (interlaced inquiry scan).
+ * @param fastDiscovery enable=TRUE, disable=FALSE
+ * @return cbBM_OK if in parameter is valid.
+ */
+extern cb_int32 cbBM_setFastDiscovery(
+ cb_boolean fastDiscovery);
+
+/**
+ * This function gets whether the fast discovery feature is enabled or disabled.
+ * @return fast connect enabled=TRUE, disabled=FALSE
+ */
+extern cb_boolean cbBM_getFastDiscovery(void);
+
+/**
+ * This function sets the page timeout in LLC.
+ * @param pageTimeout in milliseconds
+ * @return cbBM_OK if successful
+ */
+extern cb_int32 cbBM_setPageTimeout(
+ cb_uint16 pageTimeout);
+
+/**
+ * This function gets the page timeout from LLC.
+ * @return page timeout in milliseconds.
+ */
+extern cb_uint16 cbBM_getPageTimeout(void);
+
+/**
+ * This function sets all default parameters for LE.
+ * This function needs to be called before the cbBM_init.
+ */
+extern void cbBM_setDefaultValuesLeParams(void);
+
+/**
+ * This function executes HCI_cmdWrScanEnable command according to parameters.
+ * @param discoverableMode discoverable mode
+ * @param connectableMode connectable mode
+ * @return cbBM_OK if HCI command could be executed.
+ */
+extern cb_int32 cbBM_updateScan(
+ cbBM_DiscoverableMode discoverableMode,
+ cbBM_ConnectableMode connectableMode);
+
+/**
+ * Get the current Bluetooth address of the device from radio. This can
+ * be a way to get a alive-message from the radio. Also, if the radio resets,
+ * the address is set to a chip default value.
+ *
+ * @param callback to application when address has been read.
+ */
+extern void cbBM_checkRadioAlive(cbBM_LocalAddressCb callback);
+
+/**
+ * Get the current Bluetooth address of the device.
+ * @param pAddress Pointer to return variable.
+ * @return if the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getLocalAddress(TBdAddr *pAddress);
+
+/**
+ * Set local name
+ * This sets the Bluetooth Classic device name as well as the Bluetooth Low
+ * Energy device name. Inquiry and advertising is updated.
+ * @param pName The new local name (null terminated string). Max length is 32 chars.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setLocalName(cb_char* pName);
+
+/**
+ * Get local name.
+ * Get the current local name.
+ * @param pName Pointer to return variable.
+ * @param length Max length of the name string. Name will be truncated if length is too small.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getLocalName(
+ cb_char *pName,
+ cb_uint32 length);
+
+/**
+ * Set class of device
+ * @param cod New Class of Device.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setCod(TCod cod);
+
+/**
+ * Get current class of device.
+ * @param pCod Pointer to return variable.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getCod(TCod* pCod);
+
+/**
+ * Set discoverable mode for Bluetooth Classic.
+ * @param discoverable New discoverable mode.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setDiscoverableMode(cbBM_DiscoverableMode discoverable);
+
+/**
+ * Get current discoverable mode for Bluetooth Classic.
+ * @param pDiscoverable Pointer to return variable.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getDiscoverableMode(cbBM_DiscoverableMode *pDiscoverable);
+
+/**
+ * Set connectable mode for Bluetooth Classic.
+ * @param connectable Connectable mode
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setConnectableMode(cbBM_ConnectableMode connectable);
+
+/**
+ * Get current connectable mode for Bluetooth Classic
+ * @param pConnectable Pointer to return variable.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getConnectableMode(cbBM_ConnectableMode *pConnectable);
+
+/**
+ * Set master slave policy for Bluetooth Classic
+ * @param policy Master slave policy
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setMasterSlavePolicy(TMasterSlavePolicy policy);
+
+/**
+ * Set master slave policy for Bluetooth Classic
+ * @param pPolicy Pointer to return variable
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getMasterSlavePolicy(TMasterSlavePolicy *pPolicy);
+
+/**
+ * Enable/disable sniff mode
+ * @param enable TRUE=enable sniff mode, FALSE=disable sniff mode
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setSniffMode(cb_boolean enable);
+
+/**
+ * Get sniff mode
+ * @param pEnable Pointer to return variable
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getSniffMode(cb_boolean *pEnable);
+
+/**
+ * Set default channel map for Bluetooth Classic. Used to exclude channels
+ * from usage.
+ * Request an update of which channels shall be used by adaptive frequency hopping.
+ * typically this is not needed since the Bluetooth is very good at select which
+ * channels to use.
+ * @param channelMap Channel map bit mask. Note that at least 20 channels must be enabled.
+ * @param channelMapCallback Callback used to notify if the channel map
+ * is accepted by the radio.
+ * @return If the operation is successfully initiated cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setAfhChannelMap(
+ TChannelMap channelMap,
+ cbBM_ChannelMapCallb channelMapCallback);
+
+/**
+ * Get the default channel map.
+ * @param pMap Pointer to return variable where the channel map bit mask is stored.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getAfhChannelMap(TChannelMap *pMap);
+
+/**
+ * Start an Bluetooth inquiry.
+ * The event callback is called for every device that is found during inquiry.
+ * @param type Type of inquiry.
+ * @param inquiryLengthInMs Length of inquiry in ms
+ * @param eventCallback Callback used to notify each found device
+ * @param completeCallback Callback used to notify when the inquiry is completed
+ * @return If the inquiry is successfully started cbBM_OK is returned
+ */
+extern cb_int32 cbBM_inquiry(
+ cbBM_InquiryType type,
+ cb_uint32 inquiryLengthInMs,
+ cbBM_InquiryEventCallback eventCallback,
+ cbBM_InquiryCompleteCallback completeCallback);
+
+/**
+ * Cancel an ongoing inquiry.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_inquiryCancel(void);
+
+/**
+ * Perform a remote name request for Bluetooth Classic.
+ * @param pAddress Pointer to address of remote device.
+ * @param clockOffset Clock offset. Can be found in inquiry response. Use 0 if not available.
+ * @param pageTimeout Page timeout in ms (Length of connection attempt).
+ * @param remoteNameCallb Callback used to notify the completion of the
+ * name request.
+ * @return If the operation is successfully initiated cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_remoteName(
+ TBdAddr *pAddress,
+ cb_uint16 clockOffset,
+ cb_uint16 pageTimeout,
+ cbBM_RemoteNameCallback remoteNameCallb);
+
+/**
+ * Add service class to inquiry response data. Typically
+ * not used by the application.
+ * @param uuid16 The UUID to add. E.g. 0x1101=SPP, 0x1115=PANU, 0x1116=NAP
+ * @param pCallback callback to indicate service is enabled
+ * @param serviceChannel channel the service is started on
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_addServiceClass(cb_uint16 uuid16, cbBM_ServiceEnabled pCallback,cb_uint8 serviceChannel);
+
+/**
+ * Check if service class is already registered.
+ * @param uuid16 The UUID to check. E.g. 0x1101=SPP, 0x1115=PANU, 0x1116=NAP
+ * @return TRUE If the ServiceClass is registered, FALSE otherwise.
+ */
+cb_boolean cbBM_isServiceClassRegistered(cb_uint16 uuid16 );
+
+/**
+ * Add service class to inquiry response data. Typically
+ * not used by the application.
+ * @param uuid128 The UUID to add.
+ * @param pCallback callback to indicate service is enabled.
+ * @param serviceChannel channel the service is started on.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_add128BitsServiceClass(cb_uint8* uuid128, cbBM_ServiceEnabled pCallback, cb_uint8 serviceChannel);
+
+/**
+ * Set maximum Bluetooth Classic ACL links the stack
+ * shall allow.
+ * @param maxConnections Max ACL connections.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setMaxConnections(cb_uint32 maxConnections);
+
+/**
+ * Get controller version string.
+ * @return Pointer to NULL terminated version string.
+ */
+extern cb_char* cbBM_getControllerVersionString(void);
+
+/**
+ * Get stack version string.
+ * @return Pointer to NULL terminated version string.
+ */
+extern cb_char* cbBM_getStackVersionString(void);
+
+/**
+ * Get current Bluetooth Low Energy Role.
+ * @return Current Bluetooth Low Energy role.
+ */
+extern cbBM_LeRole cbBM_getLeRole(void);
+
+/**
+ * Set Bluetooth Low Energy discoverable mode.
+ * Only valid for peripheral role.
+ * @param discoverableMode Bluetooth Low Energy discoverable mode
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setDiscoverableModeLe(
+ cbBM_DiscoverableModeLe discoverableMode);
+
+/**
+ * Get Bluetooth Low Energy discoverable mode.
+ * @param pDiscoverableMode Pointer to return variable
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_getDiscoverableModeLe(
+ cbBM_DiscoverableModeLe *pDiscoverableMode);
+
+/**
+ * Set Bluetooth Low Energy connectable mode.
+ * Only valid for peripheral role.
+ * @param connectable Set to TRUE to accept connections
+ * Set to FALSE to reject incoming connections
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setConnectableModeLe(
+ cbBM_ConnectableModeLe connectable);
+
+/**
+ * Get current connectable mode.
+ * @param pConnectable Pointer to return variable.
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_getConnectableModeLe(
+ cbBM_ConnectableModeLe* pConnectable);
+
+/**
+ * Set custom advertising data.
+ * Only valid for peripheral role.
+ * @param pAdvData Pointer to advertising data.
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setCustomAdvData(
+ TAdvData* pAdvData);
+
+/**
+ * Set custom scan response data.
+ * Only valid for peripheral role.
+ * @param pScanRspData Pointer to scan response data.
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setCustomScanRspData(
+ TAdvData* pScanRspData);
+
+/**
+ * Set current scan response data.
+ * Only valid for peripheral role.
+ * @param pAdvData Pointer to scan response data.
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_getAdvData(
+ TAdvData* pAdvData);
+
+/**
+ * Get current scan response data.
+ * Only valid for peripheral role.
+ * @param pScanRspData Pointer to scan response data.
+ * @return cbBM_OK is returned on success.
+ */
+ extern cb_int32 cbBM_getScanRspData(
+ TAdvData* pScanRspData);
+
+/**
+ * Start an Bluetooth Low Energy device discovery.
+ * The event callback is called for every device that is found during inquiry.
+ * @param type Type of discovery.
+ * @param discoveryLength Length of inquiry in seconds.
+ * @param scanType Active or passive scan
+ * @param eventCallback Callback used to notify each found device
+ * @param completeCallback Callback used to notify when the inquiry is completed.
+ * @return If the device discovery is successfully started cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_deviceDiscoveryLe(
+ cbBM_DeviceDiscoveryTypeLe type,
+ cb_uint16 discoveryLength,
+ cbBM_ScanTypeLe scanType,
+ cbBM_DeviceDiscoveryLeEventCallback eventCallback,
+ cbBM_DeviceDiscoveryLeCompleteCallback completeCallback);
+
+/**
+ * Cancel an ongoing device discovery.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_deviceDiscoveryLeCancel(void);
+
+/**
+ * Perform a remote name request for Bluetooth Low Energy.
+ * @param pAddress Pointer to address of remote device.
+ * @param remoteNameCallback Callback used to notify the completion of the
+ * name request.
+ * @return If the operation is successfully initiated cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_remoteNameLe(TBdAddr *pAddress,
+ cbBM_RemoteNameCallback remoteNameCallback);
+
+
+
+/*
+ * Add 128bit service UUID to scan response data. Typically
+ * not used by the application.
+ * @param uuid128 Pointer to 128bit UUID
+ * @return If the operation is successfully initiated cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_add128BitsServiceClassLe(cb_uint8* uuid128);
+
+/*
+ * Read the used max tx power .
+ * @return max tx power level in dBm.
+ */
+extern cb_int8 cbBM_getMaxTxPower(void);
+
+/*
+ * Read the connection parameters for Bond.
+ * @param bondParams Pointer to structure where the connection parameters are stored.
+ * @return void
+ */
+void cbBM_getBondParameters(TAclParamsLe* bondParams);
+
+/*
+ * Read the connection parameters for connection.
+ * @param aclParams Pointer to structure where the connection parameters are stored.
+ * @return void
+ */
+void cbBM_getConnectParameters(TAclParamsLe* aclParams);
+
+/*
+ * Read the connection parameters for remote name request.
+ * @param aclParams Pointer to structure where the connection parameters are stored.
+ * @return void
+ */
+void cbBM_getRemoteNameReqParameters(TAclParamsLe* aclParams);
+
+/*
+ * Read the vendor specific status of the WL18 chipset.
+ * @param callback Callback used to notify the completion of the
+ * status request.
+ * @return Returns cbBM_OK if successfully started.
+ */
+cb_int32 cbBM_getTISystemStatus(cbBM_TIStatusCallback callback);
+
+/*
+ * Set BT classic as not supported in the peripheral advertisment.
+ * @param enforceDisable TRUE to set BT classic not supported
+ * @return cbBM_OK if successful
+ */
+cb_int32 cbBM_setForceClassicNotSupportedInAdv(cb_boolean enforceDisable);
+
+/*
+ * Set BT classic as not supported in the peripheral advertisment.
+ *
+ * @return TRUE if BT classic is set to not supported in the peripheral advertisment.
+ */
+cb_boolean cbBM_getForceClassicNotSupportedInAdv(void);
+
+/**
+ * Set min advertisment interval
+ *
+ * @param newValue Minimial interval value as slots (1 slot is 0.625ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setAdvertisingIntervalMin(cb_uint16 val);
+
+/**
+ * Set max advertisment interval
+ *
+ * @param newValue Time in slots (1 slot is 0.625ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setAdvertisingIntervalMax(cb_uint16 newValue);
+
+/**
+ * Set advertisment channel map
+ *
+ * @param Bit mask of channels to use; Channel 37, 38, 39
+ * (cbBM_ADV_CHANNEL_MAP_CH_37_BIT, cbBM_ADV_CHANNEL_MAP_CH_38_BIT, cbBM_ADV_CHANNEL_MAP_CH_39_BIT)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setAdvChannelmap(cb_uint16 newValue);
+
+/**
+ * Set min connection interval
+ *
+ * @param newValue Time in slots (1 slot is 1.25ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setConnectConnIntervalMin(cb_uint16 newValue);
+
+/**
+ * Set max connection interval
+ *
+ * @param newValue Time in slots (1 slot is 1.25ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setConnectConnIntervalMax(cb_uint16 newValue);
+
+/**
+ * Set connection latency
+ *
+ * @param newValue Time in slots (1 slot is 1.25ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setConnectConnLatency(cb_uint16 newValue);
+
+/**
+ * Set link loss (or supervision) timeout
+ *
+ * @param newValue Time in ms (make sure it is larger than the connection latency)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setConnectLinklossTmo(cb_uint16 newValue);
+
+/**
+ * Set create connection (or page) timeout
+ *
+ * @param newValue Time in ms
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setConnectCreateConnTmo(cb_uint16 newValue);
+
+/**
+ * Set connect scan interval
+ *
+ * @param newValue Time in slots (1 slot is 0.625ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setConnectScanInterval(cb_uint16 newValue);
+
+/**
+ * Set connect scan window
+ *
+ * @param newValue Time in slots (1 slot is 0.625ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setConnectScanWindow(cb_uint16 newValue);
+
+/**
+ * Set min bond connection interval
+ *
+ * @param newValue Time in slots (1 slot is 1.25ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setBondConnIntervalMin(cb_uint16 newValue);
+
+/**
+ * Set max bond connection interval
+ *
+ * @param newValue Time in slots (1 slot is 1.25ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setBondConnIntervalMax(cb_uint16 newValue);
+
+/**
+ * Set bond connection latency
+ *
+ * @param newValue Time in slots (1 slot is 1.25ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setBondConnLatency(cb_uint16 newValue);
+
+/**
+ * Set bond link loss (or supervision) timeout
+ *
+ * @param newValue Time in ms (make sure it is larger than the connection latency)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setBondLinklossTmo(cb_uint16 newValue);
+
+/**
+ * Set bond create connection (or page) timeout
+ *
+ * @param newValue Time in ms
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setBondCreateConnTmo(cb_uint16 newValue);
+
+/**
+ * Set bond scan interval
+ *
+ * @param newValue Time in slots (1 slot is 0.625ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setBondScanInterval(cb_uint16 newValue);
+
+/**
+ * Set bond scan window
+ *
+ * @param newValue Time in slots (1 slot is 0.625ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setBondScanWindow(cb_uint16 newValue);
+
+/**
+ * Set min remote name connection interval
+ *
+ * @param newValue Time in slots (1 slot is 1.25ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setRemoteNameConnIntervalMin(cb_uint16 newValue);
+
+/**
+ * Set max remote name connection interval
+ *
+ * @param newValue Time in slots (1 slot is 1.25ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setRemoteNameConnIntervalMax(cb_uint16 newValue);
+
+/**
+ * Set remote name connection latency
+ *
+ * @param newValue Time in slots (1 slot is 1.25ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setRemoteNameConnLatency(cb_uint16 newValue);
+
+/**
+ * Set remote name link loss (or supervision) timeout
+ *
+ * @param newValue Time in ms (make sure it is larger than the connection latency)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setRemoteNameLinklossTmo(cb_uint16 newValue);
+
+/**
+ * Set remote name create connection (or page) timeout
+ *
+ * @param newValue Time in ms
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setRemoteNameCreateConnTmo(cb_uint16 newValue);
+
+/**
+ * Set remote name scan interval
+ *
+ * @param newValue Time in slots (1 slot is 0.625ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setRemoteNameScanInterval(cb_uint16 newValue);
+
+/**
+ * Set remote name scan window
+ *
+ * @param newValue Time in slots (1 slot is 0.625ms)
+ * @return cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setRemoteNameScanWindow(cb_uint16 newValue);
+
+/**
+ * Get min advertisment interval
+ *
+ * @return Time in slots (1 slot is 0.625ms)
+ */
+extern cb_uint16 cbBM_getAdvertisingIntervalMin(void);
+
+/**
+ * Get max advertisment interval
+ *
+ * @return Time in slots (1 slot is 0.625ms)
+ */
+extern cb_uint16 cbBM_getAdvertisingIntervalMax(void);
+
+/**
+ * Get advertisment channel map
+ *
+ * @return Bit mask of channels to use; Channel 37, 38, 39
+ * (cbBM_ADV_CHANNEL_MAP_CH_37_BIT, cbBM_ADV_CHANNEL_MAP_CH_38_BIT, cbBM_ADV_CHANNEL_MAP_CH_39_BIT)
+ */
+extern cb_uint16 cbBM_getAdvChannelmap(void);
+
+/**
+ * Get min connection interval
+ *
+ * @return Time in slots (1 slot is 1.25ms)
+ */
+extern cb_uint16 cbBM_getConnectConnIntervalMin(void);
+
+/**
+ * Get max connection interval
+ *
+ * @return Time in slots (1 slot is 1.25ms)
+ */
+extern cb_uint16 cbBM_getConnectConnIntervalMax(void);
+
+/**
+ * Get connection latency
+ *
+ * @return Time in slots (1 slot is 1.25ms)
+ */
+extern cb_uint16 cbBM_getConnectConnLatency(void);
+
+/**
+ * Get link loss (or supervision) timeout
+ *
+ * @return Time in ms
+ */
+extern cb_uint16 cbBM_getConnectLinklossTmo(void);
+
+/**
+ * Get create connection (or page) timeout
+ *
+ * @return Time in ms
+ */
+extern cb_uint16 cbBM_getConnectCreateConnTmo(void);
+
+/**
+ * Get connection scan interval
+ *
+ * @return Time in slots (1 slot is 0.625ms)
+ */
+extern cb_uint16 cbBM_getConnectScanInterval(void);
+
+/**
+ * Get connection scan window
+ *
+ * @return Time in slots (1 slot is 0.625ms)
+ */
+extern cb_uint16 cbBM_getConnectScanWindow(void);
+
+/**
+ * Get min bond connection interval
+ *
+ * @return Time in slots (1 slot is 1.25ms)
+ */
+extern cb_uint16 cbBM_getBondConnIntervalMin(void);
+
+/**
+ * Get bond connection interval
+ *
+ * @return Time in slots (1 slot is 1.25ms)
+ */
+extern cb_uint16 cbBM_getBondConnIntervalMax(void);
+
+/**
+ * Get bond connection latency
+ *
+ * @return Time in slots (1 slot is 1.25ms)
+ */
+extern cb_uint16 cbBM_getBondConnLatency(void);
+
+/**
+ * Get bond link loss (or supervision) timeout
+ *
+ * @return Time in ms
+ */
+extern cb_uint16 cbBM_getBondLinklossTmo(void);
+
+/**
+ * Get bond connection (or page) timeout
+ *
+ * @return Time in ms
+ */
+extern cb_uint16 cbBM_getBondCreateConnTmo(void);
+
+/**
+ * Get bond scan interval
+ *
+ * @return Time in slots (1 slot is 0.625ms)
+ */
+extern cb_uint16 cbBM_getBondScanInterval(void);
+
+/**
+ * Get bond scan window
+ *
+ * @return Time in slots (1 slot is 0.625ms)
+ */
+extern cb_uint16 cbBM_getBondScanWindow(void);
+
+/**
+ * Get min remote name connection interval
+ *
+ * @return Time in slots (1 slot is 1.25ms)
+ */
+extern cb_uint16 cbBM_getRemoteNameConnIntervalMin(void);
+
+/**
+ * Get max remote name connection interval
+ *
+ * @return Time in slots (1 slot is 1.25ms)
+ */
+extern cb_uint16 cbBM_getRemoteNameConnIntervalMax(void);
+
+/**
+ * Get remote name connection latency
+ *
+ * @return Time in slots (1 slot is 1.25ms)
+ */
+extern cb_uint16 cbBM_getRemoteNameConnLatency(void);
+
+/**
+ * Get remote name link loss (or supervision) timeout
+ *
+ * @return Time in ms
+ */
+extern cb_uint16 cbBM_getRemoteNameLinklossTmo(void);
+
+/**
+ * Get remote name connection (or page) timeout
+ *
+ * @return Time in ms
+ */
+extern cb_uint16 cbBM_getRemoteNameCreateConnTmo(void);
+
+/**
+ * Get remote name scan interval
+ *
+ * @return Time in slots (1 slot is 0.625ms)
+ */
+extern cb_uint16 cbBM_getRemoteNameScanInterval(void);
+
+/**
+ * Get remote name scan window
+ *
+ * @return Time in slots (1 slot is 0.625ms)
+ */
+extern cb_uint16 cbBM_getRemoteNameScanWindow(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,142 @@
+/**
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Bluetooth PAN Data Manager
+ * File : cb_bt_pan.h
+ *
+ * Description : Data management for PAN profile
+ *
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_BT_PAN_H_
+#define _CB_BT_PAN_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+#include "cb_bt_conn_man.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbBTPAN_RESULT_OK ((cb_int32)0x00000000)
+#define cbBTPAN_RESULT_ERROR ((cb_int32)0x00000001)
+#define cbBTPAN_RESULT_ILLEGAL_HANDLE ((cb_int32)0x00000002)
+#define cbBTPAN_RESULT_FLOW_STOP ((cb_int32)0x00000003)
+#define cbBTPAN_RESULT_LINK_LOSS ((cb_int32)0x00000004)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+typedef cb_uint32 cbBTPAN_Handle;
+
+/*---------------------------------------------------------------------------
+ * Callback to indicate that a Bnep connection has been established.
+ *
+ * @param connHandle: Connection handle
+ * @param info: Information about the connection
+ *
+ * @return None
+ *-------------------------------------------------------------------------*/
+typedef void(*cbBTPAN_ConnectEvt) (cbBCM_Handle connHandle, cbBCM_ConnectionInfo info);
+
+/*---------------------------------------------------------------------------
+ * Callback to indicate that a Bnep connection has been disconnected.
+ *
+ * @param connHandle: Connection handle
+ *
+ * @return None
+ *-------------------------------------------------------------------------*/
+typedef void(*cbBTPAN_DisconnectEvt) (cbBCM_Handle connHandle);
+
+/*---------------------------------------------------------------------------
+ * Callback to indicate that data has been received from remote device.
+*
+ * @param btPanHandle: PAN handle
+ * @param length: Length of the data
+ * @param pData: Pointer to the data
+ *
+ * @return None
+ *-------------------------------------------------------------------------*/
+typedef void(*cbBTPAN_DataEvt) (cbBCM_Handle connHandle, cb_uint8 * pData, cb_uint16 length);
+
+/*---------------------------------------------------------------------------
+ * Callback to indicate that data has been taken care by PAN. New
+ * data can now be sent on this handle.
+ *
+ * @param btPanHandle: PAN handle
+ * @param result: cbBTPAN_RESULT_OK if the data sending succeeded
+ *
+ * @return None
+ *-------------------------------------------------------------------------*/
+typedef void(*cbBTPAN_DataCnf) (cbBCM_Handle connHandle, cb_int32 result);
+
+typedef struct
+{
+ cbBTPAN_ConnectEvt pfConnectEvt;
+ cbBTPAN_DisconnectEvt pfDisconnectEvt;
+ cbBTPAN_DataEvt pfDataEvt;
+ cbBTPAN_DataCnf pfWriteCnf;
+} cbBTPAN_Callback;
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+/**
+ * Initialization of Bluetooth PAN data. Called during stack
+ * initialization. Shall not be called by application.
+ *
+ * @return None
+ */
+extern void cbBTPAN_init(void);
+
+/**
+ * Registers for PAN data callbacks. Only one registration is supported.
+ *
+ * @param pDataCallback Data callback
+ *
+ * @return cbBTPAN_RESULT_OK if successful
+ */
+extern cb_uint32 cbBTPAN_registerDataCallback(cbBTPAN_Callback * pDataCallback);
+
+/*---------------------------------------------------------------------------
+ * Sends data to the remote device. Note that you have to wait for the
+ * confirmation callback (cbBTPAN_DataCnf) before calling another cbBTPAN_reqData.
+ *
+ * @param connHandle: Connection handle
+ * @param pBuf: Pointer to the data
+ * @param bufSize: Length of the data
+ *
+ * @return cbBTPAN_RESULT_OK if successful
+ *-------------------------------------------------------------------------*/
+extern cb_int32 cbBTPAN_reqData(cbBCM_Handle connHandle, cb_uint8 * pBuf, cb_uint16 bufSize);
+
+/*---------------------------------------------------------------------------
+ * Gets the max frame size that can be sent/received with
+ * cbBTPAN_reqData/pfDataEvt
+ *
+ * @return max frame size
+ *-------------------------------------------------------------------------*/
+extern cb_int32 cbBTPAN_getMaxFrameSize(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_cb_BT_PAN_H_
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,387 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Bluetooth Security Manager
+ * File : cb_bt_sec_man.h
+ *
+ * Description : Bluetooth security application support
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_bt_sec_man.h
+ * @brief Bluetooth security application support. This includes bonding,
+ * security modes, passkey and pin code handling.
+ */
+
+#ifndef _CB_BT_SEC_MAN_H_
+#define _CB_BT_SEC_MAN_H_
+
+#include "cb_comdefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbBSM_OK (0)
+#define cbBSM_ERROR (-1)
+
+#define cbBSM_PASSKEY_MAX_VALUE (999999)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+/**
+ * cbBSM_SECURITY_MODE_1_DISABLED
+ * Security disabled
+ * - Remote Device BT 2.1: Auto accept (No man-in-the-middle attack protection, encryption enabled)
+ * - Remote Device BT 2.0: Authentication and encryption disabled.
+ * - Bluetooth Low Energy: Auto accept (No man-in-the-middle attack protection, encryption enabled)
+ *
+ * cbBSM_SECURITY_MODE_2_BT_2_0
+ * - Enforce BT 2.0 (Service level authentication and encryption enabled)
+ * Please note that the device is not BT 2.1 qualified for this setting. It is included for backward compatibility. Invalid for Bluetooth Low Energy.
+ *
+ * cbBSM_SECURITY_MODE_3_FIXED_PIN
+ * - Remote Device BT 2.1: Service level authentication and encryption enabled.
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled.
+ * - Bluetooth Low Energy: Service level authentication and encryption enabled.
+ * Please note that this security mode will not work with a general BT 2.1 device. However, it will work between two connectBlue BT 2.1 Serial Port Adapters. Use security mode 4 to make the device work with a general BT 2.1 device.
+ *
+ * cbBSM_SECURITY_MODE_4_JUST_WORKS
+ * - Remote Device BT 2.1: Auto accept (no man-in-the-middle attack protection, encryption enabled)
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled.
+ * - Bluetooth Low Energy: Auto accept (no man-in-the-middle attack protection, encryption enabled)
+ * This security mode is intended for pairing in safe environments. When this mode is set, pairability (see AT*AGPM) is automatically disabled. In data mode, pairing can be enabled for 60 seconds by pressing the "External Connect" button for at least 5 seconds. When the module is pairable, the LED will blink. If the mode is changed from Just Works to another, pairability must be enabled again using the AT*AGPM command.
+ *
+ * cbBSM_SECURITY_MODE_5_DISPLAY_ONLY
+ * - Remote Device BT 2.1: Service level authentication and encryption enabled. User should be presented a passkey.
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled. No user interaction required.
+ * - Bluetooth Low Energy: Service level authentication and encryption enabled. User should be presented a passkey.
+ * This security mode is used when the device has a display that can present a 6-digit value that the user shall enter on the remote device.
+ *
+ * cbBSM_SECURITY_MODE_6_DISPLAY_YES_NO
+ * - Remote Device BT 2.1: Service level authentication and encryption enabled. User should compare two values.
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled. No user interaction required.
+ * This security mode is used when the device has a display that can present a 6-digit value that the user shall verify with yes or no to the remote device's presented value.
+ * Invalid for Bluetooth Low Energy.
+ *
+ * cbBSM_SECURITY_MODE_7_KEYBOARD_ONLY
+ * - Remote Device BT 2.1: Service level authentication and encryption enabled. User should enter a passkey.
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled. No user interaction required.
+ * - Bluetooth Low Energy: Service level authentication and encryption enabled. User should enter a passkey.
+ * This security mode is used when the device only has a keyboard where the user can enter a 6-digit value that is presented on the remote device.
+ */
+typedef enum
+{
+ cbBSM_SECURITY_MODE_1_DISABLED = 1,
+ cbBSM_SECURITY_MODE_2_BT_2_0,
+ cbBSM_SECURITY_MODE_3_FIXED_PIN,
+ cbBSM_SECURITY_MODE_4_JUST_WORKS,
+ cbBSM_SECURITY_MODE_5_DISPLAY_ONLY,
+ cbBSM_SECURITY_MODE_6_DISPLAY_YES_NO,
+ cbBSM_SECURITY_MODE_7_KEYBOARD_ONLY
+} cbBSM_SecurityMode;
+
+typedef struct
+{
+ TPinCode pin;
+ cb_uint8 nBytes;
+} cbBSM_PinCode;
+
+typedef enum
+{
+ cbBSM_BOND_TYPE_CLASSIC,
+ cbBSM_BOND_TYPE_LE,
+ cbBSM_BOND_TYPE_ALL,
+} cbBSM_BondTypes;
+
+typedef enum
+{
+ cbBSM_BOND_STATUS_OK = 0,
+ cbBSM_BOND_STATUS_ERR_PAGE_TMO,
+ cbBSM_BOND_STATUS_ERR_AUTH_FAIL,
+ cbBSM_BOND_STATUS_ERR_NO_MITM
+} cbBSM_BondStatus;
+
+/**
+ * Callback to indicate that bonding is finished.
+ * @param bdAddress Remote BD address
+ * @param bondStatus Bond status, e.g. cbBSM_BOND_STATUS_OK
+ * @return None
+ */
+typedef void (*cbBSM_BondCnf)(
+ cbBSM_BondStatus status,
+ TBdAddr* pBdAddress);
+
+/**
+ * Callback to indicate that a pin code is required from upper layer.
+ * Respond the pin code request with cbBSM_rspFixedPin/cbBSM_rspNegFixedPin
+ * This is only used when either local or remote side does not support
+ * BT 2.1 secure simple pairing.
+ * @param bdAddress Remote BD address
+ * @return None
+ */
+typedef void (*cbBSM_RequestPinInd)(
+ TBdAddr* pBdAddress);
+
+/**
+ * Callback to indicate that user confirmation is required. The user should
+ * compare numericValues on local and remote side and respond the confirmation
+ * request with cbBSM_rspUserConfirmation if values match and
+ * cbBSM_rspNegUserConfirmation if they do not match or user wants to interrupt
+ * the pairing attempt.
+ * This is only used when both sides support BT 2.1 secure simple pairing and
+ * security mode cbBSM_SECURITY_MODE_6_DISPLAY_YES_NO is used.
+ * @param bdAddress Remote BD address
+ * @param numericValue The numeric value to be compared
+ * @return None
+ */
+typedef void (*cbBSM_UserConfirmationInd)(
+ TBdAddr* pBdAddress,
+ cb_uint32 numericValue);
+
+/**
+ * Callback to indicate that a passkey is required from upper layer.
+ * Respond the passkey request with cbBSM_rspUserPasskey/cbBSM_rspNegUserPasskey.
+ * This is only used when both sides support BT 2.1 secure simple pairing and
+ * security modes cbBSM_SECURITY_MODE_3_FIXED_PIN or cbBSM_SECURITY_MODE_7_KEYBOARD_ONLY is used
+ * @param bdAddress Remote BD address
+ * @return None
+ */
+typedef void (*cbBSM_UserPasskeyInd)(
+ TBdAddr* pBdAddress);
+
+/**
+ * Callback to indicate that a passkey is used in the pairing procedure.
+ * The passkey should be displayed to the user.
+ * This is only used when both sides support BT 2.1 secure simple pairing and
+ * security mode cbBSM_SECURITY_MODE_5_DISPLAY_ONLY is used.
+ * @param bdAddress Remote BD address
+ * @param passkey Passkey
+ * @return None
+ */
+typedef void (*cbBSM_UserPasskeyEvt)(
+ TBdAddr* pBdAddress,
+ cb_uint32 passkey);
+
+typedef struct
+{
+ cbBSM_RequestPinInd requestPinInd;
+ cbBSM_UserConfirmationInd userConfirmationInd;
+ cbBSM_UserPasskeyInd userPasskeyInd;
+ cbBSM_UserPasskeyEvt userPasskeyEvt;
+ cbBSM_BondCnf bondConfirmation;
+ cbBSM_BondCnf bondEvent;
+} cbBSM_Callbacks;
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Initialization of BLuetooth security manager. Called during stack
+ * initialization. Shall not be called by application.
+ *
+ * @return None
+ */
+extern void cbBSM_init(void);
+
+/**
+ * Register security callbacks. Callbacks in the struct that are not
+ * of any interest can be set to NULL.
+ *
+ * @param pPairingCallbacks Pointer to the security callback struct
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_registerCallbacks(cbBSM_Callbacks* pPairingCallbacks);
+
+/**
+ * Set security mode. See comments on cbBSM_SecurityMode for
+ * description of the different security modes.
+ *
+ * @param securityMode Security mode. Default security is cbBSM_SECURITY_MODE_1_DISABLED
+ * @param allowPairingInNonBondableMode Normally FALSE. Set to TRUE if pairing should be allowed when not bondable.
+ * No link keys will then be stored.
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_setSecurityMode(
+ cbBSM_SecurityMode securityMode,
+ cb_boolean allowPairingInNonBondableMode);
+
+/**
+ * Read current security mode.
+ *
+ * @param pSecurityMode Security mode
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_getSecurityMode(cbBSM_SecurityMode* pSecurityMode);
+
+/**
+ * Sets the local device pairable mode.
+ *
+ * @param pairable TRUE=pairable, FALSE=not pairable (default)
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_setPairable(boolean pairable);
+
+/**
+ * Gets the local device pairable mode.
+ *
+ * @param pPairable Pointer to return value
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_getPairable(boolean* pPairable);
+
+/**
+ * Performs bonding with a remote device. The cbBSM_BondCnf callback will
+ * be called upon success/failure.
+ *
+ * @param remoteDevice Remote BD address
+ * @param type Classic or LE
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_reqBond(
+ TBdAddr remoteDevice,
+ TBluetoothType type);
+
+/**
+ * Responds on the cbBSM_RequestPinInd callback with a pin code
+ * This is only used when either local or remote side does not support
+ * BT 2.1 secure simple pairing.
+ *
+ * @param pBdAddress Pointer to the remote BD address
+ * @param pinCodeLength Length of the provided pin code
+ * @param pPinCode Pointer to the provided pin code
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspFixedPin(
+ TBdAddr* pBdAddress,
+ cb_uint8 pinCodeLength,
+ cb_uint8 *pPinCode);
+
+/**
+ * Responds the cbBSM_RequestPinInd callback. Can be used to interrupt a
+ * pairing attempt from the remote device.
+ * This is only used when either local or remote side does not support
+ * BT 2.1 secure simple pairing.
+ *
+ * @param pBdAddress Pointer to the remote BD address
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspNegFixedPin(TBdAddr* pBdAddress);
+
+/**
+ * Responds on the cbBSM_UserPasskeyInd callback.
+ * This is only used when both sides support BT 2.1 secure simple pairing.
+ *
+ * @param pBdAddress Pointer to the remote BD address
+ * @param passkey Passkey, range: 0-999999
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspUserPasskey(
+ TBdAddr *pBdAddress,
+ uint32 passkey);
+
+/**
+ * Responds on the cbBSM_UserPasskeyInd callback. Can be used to interrupt a
+ * pairing attempt from the remote device.
+ * This is only used when both sides support BT 2.1 secure simple pairing.
+ *
+ * @param pBdAddress Pointer to the remote BD address
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspNegUserPasskey(TBdAddr *pBdAddress);
+
+/**
+ * Responds on the cbBSM_UserConfirmationInd callback. Accepts the numeric value.
+ * This is only used when both sides support BT 2.1 secure simple pairing.
+ *
+ * @param pBdAddress Pointer to the remote BD address
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspUserConfirmation(TBdAddr* pBdAddress);
+
+/**
+ * Responds on the cbBSM_UserConfirmationInd callback. Rejects the numeric value.
+ * This is only used when both sides support BT 2.1 secure simple pairing.
+ *
+ * @param pBdAddress Pointer to the remote BD address
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspNegUserConfirmation(TBdAddr* pBdAddress);
+
+/**
+ * Get number of bonded devices.
+ *
+ * @param type Bond type
+ * @param pNo Pointer to return value.
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_getAllNumberBondedDevices(
+ cbBSM_BondTypes type,
+ uint32* pNo);
+
+/**
+* Get a bonded devices.
+*
+* @param deviceIndex Index of the bonded device
+* @param pBdAddr Pointer to remote BD address.
+* @param pIsLe Should be TRUE for LE and FALSE for classic
+* @return If the operation is successful cbBSM_OK is returned.
+*/
+extern cb_int32 cbBSM_getBondedDevice(
+ cb_int32 deviceIndex,
+ TBdAddr* pBdAddr,
+ cb_boolean pIsLe);
+
+/**
+ * Delete a bonded device and its link keys.
+ *
+ * @param pBdAddress to the address of the device which bond shall be deleted.
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_deleteBondedDevice(TBdAddr* pBdAddress);
+
+/**
+ * Delete all bonded devices and link keys.
+ *
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_deleteAllBondedDevices(void);
+
+/**
+ * Initializes the static Link Keys for both classic and LE.
+ * nvdsId: nvds id for the static link key,
+ * (0) disables the use of a static link key.
+ *
+ * @return cbBSM_OK.
+ */
+cb_int32 cbBSM_setStaticLinkKeyNvdsId(cb_int32 nvdsId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_BT_SEC_MAN_H_ */
+
+
+
+
+
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,156 @@
+/**
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Bluetooth Serial
+ * File : cb_bt_serial.h
+ *
+ * Description : Data management for RFCOMM based profiles such and Serial
+ * Port Profile (SPP).
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_bt_serial.h
+ * @brief Data management for RFCOMM based profiles such and Serial
+ * Port Profile (SPP).
+ */
+
+#ifndef _CB_BT_SERIAL_H_
+#define _CB_BT_SERIAL_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+#include "cb_bt_conn_man.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+* DEFINES
+*=========================================================================*/
+#define cbBSE_OK 0
+#define cbBSE_ERROR -1
+#define cbBSE_NO_DATA -2
+
+/*===========================================================================
+* TYPES
+*=========================================================================*/
+
+typedef void (*cbBSE_DataAvailEvt)(
+ cbBCM_Handle handle);
+
+typedef void (*cbBSE_WriteCnf)(
+ cbBCM_Handle handle,
+ cb_int32 status,
+ cb_uint32 nBytes,
+ cb_int32 tag);
+
+typedef struct
+{
+ cbBSE_DataAvailEvt pfDataEvt;
+ cbBSE_WriteCnf pfWriteCnf;
+} cbBSE_Callback;
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Initialization of Bluetooth serial manager. Called during stack
+ * initialization. Shall not be called by application.
+ *
+ * @return None
+ */
+extern void cbBSE_init(void);
+
+/**
+ * Open a data channel.
+ *
+ * @param handle Connection handle
+ * @param pCallback Callback for data events.
+ * @return If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSE_open(
+ cbBCM_Handle handle,
+ cbBSE_Callback *pCallback);
+
+/**
+ * Send data to remote device. A data confirmation event is generated when
+ * the data has been sent and a cbBSE_write call can be done.
+ *
+ * Detailed description optionally verbose.
+ * @param handle Connection handle
+ * @param pBuf Data pointer
+ * @param nBytes nBytes Size of data to be sent.
+ * @param tag Tag passed as argument in corresponding data confirmation callback.
+ * @return If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSE_write(
+ cbBCM_Handle handle,
+ cb_uint8 *pBuf,
+ cb_uint32 nBytes,
+ cb_int32 tag);
+
+/**
+ * Get received data.
+ *
+ * @param handle Connection handle
+ * @param ppBuf Pointer to data buffer
+ * @param pLength Pointer to buffer length variable.
+ * @return cbBSE_OK is returned if data is available. If no data is available
+ * then cbBSE_NO_DATA is returned.
+ */
+extern cb_int32 cbBSE_getReadBuf(
+ cbBCM_Handle handle,
+ cb_uint8 **ppBuf,
+ cb_uint32 *pLength);
+
+/**
+ * Notify that received data has been handled and underlying buffers
+ * can be freed.
+ *
+ * @param handle Connection handle
+ * @param nBytes Number of bytes consumed.
+ * @return If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSE_readBufConsumed(
+ cbBCM_Handle handle,
+ cb_uint32 nBytes);
+
+/**
+ * Read max frame size for a data channel.
+ *
+ * @param handle Connection handle
+ * @param pFrameSize Max frame size for connection.
+ * @return If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSE_frameSize(cbBCM_Handle handle, cb_uint32 *pFrameSize);
+
+/**
+ * Bluetooth serial message handling. Shall not be called by application.
+ *
+ * @param msgId Message id
+ * @param pData Pointer to message data
+ * @return None
+ */
+extern void cbBSE_handleMsg(cb_uint32 msgId, void* pData);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,154 @@
+/**
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Bluetooth Serial
+ * File : cb_bt_serial_le.h
+ *
+ * Description : Data management for Serial Port Service.
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_bt_serial_le.h
+ * @brief Data management for Serial Port Service.
+ */
+
+#ifndef _CB_BT_SERIAL_LE_H_
+#define _CB_BT_SERIAL_LE_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+#include "cb_bt_conn_man.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+* DEFINES
+*=========================================================================*/
+#define cbBSL_OK 0
+#define cbBSL_ERROR -1
+#define cbBSL_NO_DATA -2
+
+/*===========================================================================
+* TYPES
+*=========================================================================*/
+
+typedef void (*cbBSL_DataAvailEvt)(
+ cbBCM_Handle handle);
+
+typedef void (*cbBSL_WriteCnf)(
+ cbBCM_Handle handle,
+ cb_int32 status,
+ cb_uint32 nBytes,
+ cb_int32 tag);
+
+typedef struct
+{
+ cbBSL_DataAvailEvt pfDataEvt;
+ cbBSL_WriteCnf pfWriteCnf;
+} cbBSL_Callback;
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Initialization of Bluetooth serial manager. Called during stack
+ * initialization. Shall not be called by application.
+ *
+ * @return None
+ */
+extern void cbBSL_init(void);
+
+/**
+ * Open a data channel.
+ *
+ * @param handle Connection handle
+ * @param pCallback Callback for data events.
+ * @return If the operation is successful cbBSL_OK is returned.
+ */
+extern cb_int32 cbBSL_open(
+ cbBCM_Handle handle,
+ cbBSL_Callback *pCallback);
+
+/**
+ * Send data to remote device. A data confirmation event is generated when
+ * the data has been sent and a cbBSL_write call can be done.
+ *
+ * Detailed description optionally verbose.
+ * @param handle Connection handle
+ * @param pBuf Data pointer
+ * @param nBytes nBytes Size of data to be sent.
+ * @param tag Tag passed as argument in corresponding data confirmation callback.
+ * @return If the operation is successful cbBSL_OK is returned.
+ */
+extern cb_int32 cbBSL_write(
+ cbBCM_Handle handle,
+ cb_uint8 *pBuf,
+ cb_uint32 nBytes,
+ cb_int32 tag);
+
+/**
+ * Get received data.
+ *
+ * @param handle Connection handle
+ * @param ppBuf Pointer to data buffer
+ * @param pLength Pointer to buffer length variable.
+ * @return cbBSL_OK is returned if data is available. If no data is available
+ * then cbBSL_NO_DATA is returned.
+ */
+extern cb_int32 cbBSL_getReadBuf(
+ cbBCM_Handle handle,
+ cb_uint8 **ppBuf,
+ cb_uint32 *pLength);
+
+/**
+ * Notify that received data has been handled and underlying buffers
+ * can be freed.
+ *
+ * @param handle Connection handle
+ * @param nBytes Number of bytes consumed.
+ * @return If the operation is successful cbBSL_OK is returned.
+ */
+extern cb_int32 cbBSL_readBufConsumed(
+ cbBCM_Handle handle,
+ cb_uint32 nBytes);
+
+/**
+ * Read max frame size for a data channel.
+ *
+ * @param handle Connection handle
+ * @param pFrameSize Max frame size for connection.
+ * @return If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSL_frameSize(cbBCM_Handle handle, cb_uint32 *pFrameSize);
+
+/**
+ * Bluetooth serial message handling. Shall not be called by application.
+ *
+ * @param msgId Message id
+ * @param pData Pointer to message data
+ * @return None
+ */
+extern void cbBSL_handleMsg(cb_uint32 msgId, void* pData);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,253 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Bluetooth Test
+ * File : cb_bt_test_man.h
+ *
+ * Description : Functionality for Bluetooth radio tests and qualification.
+ *-------------------------------------------------------------------------*/
+
+/**
+* @file cb_bt_test_man.h
+* @brief Functionality for Bluetooth radio tests and qualification.
+ */
+
+#ifndef _CB_BT_TEST_MAN_H_
+#define _CB_BT_TEST_MAN_H_
+
+#include "cb_comdefs.h"
+
+#include "cb_bt_man.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbBTM_OK (0)
+#define cbBTM_ERROR (-1)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+typedef enum
+{
+ cbBTM_TEST_CONF_POS,
+ cbBTM_TEST_CONF_NEG
+} cbBTM_TestEvt;
+
+typedef void (*cbBTM_TestCallback)(cbBTM_TestEvt evt);
+typedef void (*cbBTM_LeTestEndCallback)(cbBTM_TestEvt evt, cb_uint16 nbrOfPackets);
+
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Init Bluetooth test manager
+ * @returns None
+ */
+extern void cbBTM_init(void);
+
+/**
+ * Enable Device under test mode. Used for Bluetooth Classic radio tests.
+ *
+ * @param callback Test callback used to notify if the test was successfully started.
+ * @returns cbBTM_OK is returned
+ */
+extern cb_int32 cbBTM_enableDUT(cbBTM_TestCallback callback);
+
+/**
+ * This command operates the RF transceiver in continuous transmission mode (which is most likely used in
+ * regulatory and standardization procedures and tests, such as FCC and ETSI certifications). Activating the
+ * VS runs the TX START sequence code using the configured frequency, modulation, pattern, and power
+ * level. The VS also enables the generation of a user-defined pattern (or correcting definitions without a
+ * patch) by setting a new pattern generator (also known as a PN generator) init value and mask.
+ * based on HCI_VS_DRPb_Tester_Con_TX, HCI Opcode 0xFDCA
+ * The cbBTM_TestCallback is used to notify if the test is sucessfully started.
+ *
+ * @param frequency Transmission frequency in MHz Range: 2402 - 2480
+ * @param modulationScheme Range: 0x00 - 0x05 where
+ * 0x00 = CW
+ * 0x01 = BT BR (GFSK)
+ * 0x02 = BT EDR 2MB (p/4-DQPSK)
+ * 0x03 = BT EDR 3MB (8-DPSK)
+ * 0x04 = BT LE (BLE, GMSK)
+ * 0x05 = ANT (GFSK)
+ * @param testPattern Range: 0x00 - 0x07
+ * 0x00 = PN9
+ * 0x01 = PN15
+ * 0x02 = ZOZO (101010101010101010)
+ * 0x03 = All 1
+ * 0x04 = All 0
+ * 0x05 = FOFO (1111000011110000)
+ * 0x06 = FFOO (1111111100000000)
+ * 0x07 = Not used
+ * @param powerLevelIndex Range: 0-7: 7 = Max Output Power, 0 = Min Output Power, 0x08 (PA off) 8 = PA Off (leakage)
+ * @param reserved1 shall be set to 0
+ * @param reserved2 shall be set to 0
+ * @param callback Test callback used to notify if the test was successfully started.
+ *
+ * @return cbBTM_OK is returned
+ */
+extern cb_int32 cbBTM_tiDrpbTesterConTx(
+ cb_uint16 frequency,
+ cb_uint8 modulationScheme,
+ cb_uint8 testPattern,
+ cb_uint8 powerLevelIndex,
+ cb_uint32 reserved1,
+ cb_uint32 reserved2,
+ cbBTM_TestCallback callback);
+
+/**
+ *This command operates the RF transceiver in continuous reception mode (most likely used in regulatory
+ * and standardization procedures and tests, such as FCC and ETSI certifications). By activating the VS, the
+ * RX START sequence code runs, using the configured frequency, RX mode, and modulation type.
+ * based on HCI_VS_DRPb_Tester_Con_RX, HCI Opcode 0xFDCB
+ *
+ * The cbBTM_TestCallback is used to notify if the test is successfully started.
+ * @param frequency Transmission frequency in MHz Range: 2402 - 2480
+ * @param rxMode Range: 0 -3:
+ * 0x00 = Connection mode
+ * 0x01 = Best RF mode (ADPL closed loop) - For expert use only!
+ * 0x02 = Low current mode (ADPLL open loop) - For expert use only!
+ * 0x03 = Scan mode
+ * @param modulationScheme Range: 0x03 - 0x05 where
+ * 0x03 = BT (BR, EDR 2MB, EDR 3MB)
+ * 0x04 = BT LE (BLE, GMSK)
+ * 0x05 = ANT (GFSK)
+ * @param callback Test callback used to notify if the test was successfully started.
+ *
+ * @return cbBTM_OK is returned
+ */
+extern cb_int32 cbBTM_tiDrpbTesterConRx(
+ cb_uint16 frequency,
+ cb_uint8 rxMode,
+ cb_uint8 modulationScheme,
+ cbBTM_TestCallback callback);
+
+/**
+ *
+ * This command operates the RF transceiver in continuous reception mode (most likely used in regulatory
+ * and standardization procedures and tests, such as FCC and ETSI certifications). Activating the VS runs
+ * the RX START sequence code using the configured frequency, RX mode, and modulation type.
+ * This command emulates Bluetooth connection mode. Connection does not require a setup procedure.
+ * Based on HCI_VS_DRPb_Tester_Packet_TX_RX HCI Opcode 0xFDCC
+ *
+ * @param aclPacketType ACL TX packet type. Range: 0x00 - 0x0B
+ * 0x00 = DM1
+ * 0x01 = DH1
+ * 0x02 = DM3
+ * 0x03 = DH3
+ * 0x04 = DM5
+ * 0x05 = DH5
+ * 0x06 = 2-DH1
+ * 0x07 = 2-DH3
+ * 0x08 = 2-DH5
+ * 0x09 = 3-DH1
+ * 0x0A = 3-DH3
+ * 0x0B = 3-DH5
+ * @param frequencyMode 0x00 = Hopping 0x03 = Single frequency
+ * @param txSingleFrequency Transmission frequency in MHz,Range 2402 - 2480, 0xFFFF = no TX
+ * @param rxSingleFrequency Transmission frequency in MHz,Range 2402 - 2480, 0xFFFF = no RX
+ * @param aclDataPattern ACL TX packet data pattern Range: 0x00 - 0x05
+ * 0x00 = All 0
+ * 0x01 = All 1
+ * 0x02 = ZOZO (101010101010101010)
+ * 0x03 = FOFO (1111000011110000)
+ * 0x04 = Ordered (1, 2, 3, 4, and so on)
+ * 0x05 = PRBS9 (pseudo-random bit sequence)
+ * @param useExtendedFeatures Shall be SET to 0
+ * @param aclDataLength ACL packet data length.
+ * DM1: 0 - 17 ACL packet data length in bytes
+ * DH1: 0 - 27
+ * DM3: 0 - 121
+ * DH3: 0 - 183
+ * DM5: 0 - 224
+ * DH5: 0 - 339
+ * 2-DH1: 0 - 54
+ * 2-DH3: 0 - 367
+ * 2-DH5: 0 - 679
+ * 3-DH1: 0 - 83
+ * 3-DH3: 0 - 552
+ * 3-DH5: 0 - 1021
+ * @param powerLevel Range 0-7: 7 = Max Output Power; 0 = Min Output; Power 8 = PA Off (leakage) 0x08 (PA off)
+ * @param disableWhitening 0x00 = Enable whitening, 0x01 = Disable whitening
+ * @param prbs9Init PRBS9 Init, range 0x0000 - 0x01FF
+ * @param callback Test callback used to notify if the test was successfully started.
+ *
+ * @return cbBTM_OK is returned
+ */
+extern cb_int32 cbBTM_tiDrpbTesterPacketTxRx(
+ cb_uint8 aclPacketType,
+ cb_uint8 frequencyMode,
+ cb_uint16 txSingleFrequency,
+ cb_uint16 rxSingleFrequency,
+ cb_uint8 aclDataPattern,
+ cb_uint8 useExtendedFeatures,
+ cb_uint16 aclDataLength,
+ cb_uint8 powerLevel,
+ cb_uint8 disableWhitening,
+ cb_uint16 prbs9Init,
+ cbBTM_TestCallback callback);
+
+/**
+ * Enable Bluetooth Low Energy Transmitter test.
+ * @param txFreq Transmit frequency. N = (F - 2402) / 2, Range: 0x00 to 0x27, Frequency Range : 2402 MHz to 2480 MHz,
+ Use oxFF to generate a pseudo random hopping frequency useful for some scenarios during type approval.
+ * @param length Length in bytes of payload data in each packet
+ * @param packetPayload 0x00 Pseudo-Random bit sequence 9
+ * 0x01 Pattern of alternating bits 11110000
+ * 0x02 Pattern of alternating bits 10101010
+ * 0x03 Pseudo-Random bit sequence 15
+ * 0x04 Pattern of All 1 bits
+ * 0x05 Pattern of All 0 bits
+ * 0x06 Pattern of alternating bits 00001111
+ * 0x07 Pattern of alternating bits 0101
+ * @param callback Test callback used to notify if the test was successfully started.
+ * @return cbBTM_OK is returned
+ */
+extern cb_int32 cbBTM_enableBleTransmitterTest(
+ cb_uint8 txFreq,
+ cb_uint8 length,
+ cb_uint8 packetPayload,
+ cbBTM_TestCallback callback);
+
+/**
+ * Enable Bluetooth Low Energy Receiver test.
+ * @param rxFreq Receive frequency. N = (F - 2402) / 2, Range: 0x00 to 0x27, Frequency Range : 2402 MHz to 2480 MHz,
+ * @param callback Test callback used to notify if the test was successfully started.
+ * @returns cbBTM_OK is returned
+ */
+extern cb_int32 cbBTM_enableBleReceiverTest(
+ cb_uint8 rxFreq,
+ cbBTM_TestCallback callback);
+
+/**
+ * End Bluetooth Low Energy Receiver or Transmitter test.
+ * @param callback Test callback used to notify if the test was successfully ended.
+ * @returns cbBTM_OK is returned
+ */
+extern cb_int32 cbBTM_bleTestEnd(cbBTM_LeTestEndCallback callback);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_BT_TEST_MAN_H_ */
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,86 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Bluetooth utility
+ * File : cb_bt_utils.h
+ *
+ * Description :
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_BT_UTILS_H_
+#define _CB_BT_UTILS_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================
+ */
+
+/**
+ * Compare two Bluetooth addresses
+ *
+ * @param addr1 Pointer to first address to compare
+ * @param addr2 Pointer to second address to compare
+ * @returns TRUE if equal otherwise FALSE
+ */
+extern cb_boolean cbBT_UTILS_cmpBdAddr(
+ TBdAddr* addr1,
+ TBdAddr* addr2);
+
+/**
+ * Check if address in invalid i.e. {{0,0,0,0,0,0},BT_PUBLIC_ADDRESS}
+ *
+ * @param addr Pointer to address to check
+ * @returns TRUE if invalid otherwise FALSE
+ */
+extern cb_boolean cbBT_UTILS_isInvalidBdAddr(
+ TBdAddr* addr);
+
+/**
+ * Set invalid address i.e. {{0,0,0,0,0,0},BT_PUBLIC_ADDRESS}
+ *
+ * @param addr Pointer where to put the address
+ */
+extern void cbBT_UTILS_setInvalidBdAddr(
+ TBdAddr* addr);
+
+/**
+ * Get invalid address
+ *
+ * @returns Pointer to the invalid address
+ */
+extern const TBdAddr* cbBT_UTILS_getInvalidBdAddr(void);
+
+/**
+ * Copy Bluetooth address
+ *
+ * @param dest Pointer to destination address
+ * @param src Pointer to source address
+ */
+extern void cbBT_UTILS_cpyBdAddr(
+ TBdAddr* dest,
+ TBdAddr* src);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_BT_UTILS_H_ */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,80 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : WLAN
+ * File : cb_cert_utils.h
+ *
+ * Description :
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_cert_utils.h The main WLAN component interface.
+ * All functions declared extern needs to be provided by another/upper layer.
+ * @ingroup wlan
+ */
+
+#ifndef _CB_CERT_UTILS_H_
+#define _CB_CERT_UTILS_H_
+
+#include "cb_types.h"
+#include "cb_status.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbCERT_CRT_MAX_CHAIN_LENGTH 5ul
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+typedef struct cbCERT_Stream_s cbCERT_Stream;
+typedef cb_uint32 cbCERT_StreamPosition;
+
+/**
+ * Stream vtable interface used by WLAN supplicant to access SSL certificates
+ * for WPA Enterprise authentication.
+ *
+ * @ingroup wlan
+ */
+struct cbCERT_Stream_s {
+ cb_int32(*read)(const cbCERT_Stream *stream, void *buf, cb_uint32 count); /**< Read function pointer, place count bytes in buf. */
+ cb_int32(*write)(const cbCERT_Stream *stream, void *buf, cb_uint32 count); /**< Read function pointer, place count bytes in buf. */
+ void(*rewind)(const cbCERT_Stream *stream); /**< Rewind function pointer, rewind stream internal iterator to the beginning. Mandatory for all streams. */
+ void(*setPosition)(const cbCERT_Stream *stream, cbCERT_StreamPosition position); /**< Set absolute position. */
+ cbCERT_StreamPosition(*getPosition)(const cbCERT_Stream *stream); /**< Get current position. */
+ cb_uint32(*getSize)(const cbCERT_Stream *stream); /**< GetSize function pointer, return total size of stream contents. */
+};
+
+/*===========================================================================
+ * CERT API
+ *=========================================================================*/
+
+cbRTSL_Status cbCERT_Util_parseDERCert(cbCERT_Stream const * const certificate, cbCERT_Stream const * const outputStream);
+cbRTSL_Status cbCERT_Util_parseDERKey(cbCERT_Stream const * const key, cbCERT_Stream const * const outputStream);
+cbRTSL_Status cbCERT_Util_parsePEMCert(cbCERT_Stream const * const certificate, cbCERT_Stream const * const outputStream);
+cbRTSL_Status cbCERT_Util_parsePEMKey(cbCERT_Stream const * const certificate, cb_char const * const key, cb_uint32 keyLength, cbCERT_Stream const * const outputStream);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_CERT_UTILS_H_ */
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,190 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Common Definitions
+ * File : cb_comdefs.h
+ *
+ * Description : Common definitions.
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_COMDEFS_H_
+#define _CB_COMDEFS_H_
+
+#include "cb_platform_basic_types.h"
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+#ifndef FALSE
+# define FALSE (0)
+#endif
+
+#ifndef TRUE
+# define TRUE (!FALSE)
+#endif
+
+#ifndef NULL
+# define NULL ((void*)0)
+#endif
+
+/**
+ * Returns the maximum value of the two parameters.
+ */
+#define cb_MAX(a,b) (((a) > (b)) ? (a) : (b))
+
+/**
+ * Returns the minimum value of the two parameters.
+ */
+#define cb_MIN(a,b) (((a) < (b)) ? (a) : (b))
+
+/**
+ * Used in function definitions to declare an input parameter unused to avoid warnings.
+ */
+#ifndef cb_UNUSED
+# define cb_UNUSED(x) x
+#endif
+
+
+#ifndef cb_ASSERT
+# error "No platform definition for ASSERT!"
+#endif
+
+/**
+ * Used when declaring an empty array that does not take up space in a struct.
+ * Example: struct { cb_uint8 payload[cb_EMPTY_ARRAY]; }
+ * In some compilers this is empty i.e. payload[]. While in some it requires a zero.
+ * I.e. payload[0];
+ * Use this define to get it working for your system.
+ */
+#ifndef cb_EMPTY_ARRAY
+# define cb_EMPTY_ARRAY (0)
+#endif
+
+
+#define cb_BIT_0 (1ul)
+#define cb_BIT_1 (1ul << 1)
+#define cb_BIT_2 (1ul << 2)
+#define cb_BIT_3 (1ul << 3)
+#define cb_BIT_4 (1ul << 4)
+#define cb_BIT_5 (1ul << 5)
+#define cb_BIT_6 (1ul << 6)
+#define cb_BIT_7 (1ul << 7)
+#define cb_BIT_8 (1ul << 8)
+#define cb_BIT_9 (1ul << 9)
+#define cb_BIT_10 (1ul << 10)
+#define cb_BIT_11 (1ul << 11)
+#define cb_BIT_12 (1ul << 12)
+#define cb_BIT_13 (1ul << 13)
+#define cb_BIT_14 (1ul << 14)
+#define cb_BIT_15 (1ul << 15)
+#define cb_BIT_16 (1ul << 16)
+#define cb_BIT_17 (1ul << 17)
+#define cb_BIT_18 (1ul << 18)
+#define cb_BIT_19 (1ul << 19)
+#define cb_BIT_20 (1ul << 20)
+#define cb_BIT_21 (1ul << 21)
+#define cb_BIT_22 (1ul << 22)
+#define cb_BIT_23 (1ul << 23)
+#define cb_BIT_24 (1ul << 24)
+#define cb_BIT_25 (1ul << 25)
+#define cb_BIT_26 (1ul << 26)
+#define cb_BIT_27 (1ul << 27)
+#define cb_BIT_28 (1ul << 28)
+#define cb_BIT_29 (1ul << 29)
+#define cb_BIT_30 (1ul << 30)
+#define cb_BIT_31 (1ul << 31)
+
+/**
+ * Clears (set to zero) a bit or bits in a variable.
+ * @param variable The variable.
+ * @param bit The bit or bits to clear
+ */
+#define cb_CLEAR_BIT(variable,bit) ((variable) &= ~((bit)))
+
+/**
+ * Gets a bit i.e. checks if it is set in a variable.
+ *
+ * Also works to see if any of several bits are set.
+ *
+ * @param variable The variable.
+ * @param bit The bit to check if it set.
+ * @return @ref TRUE if any of the bits are set, @ref FALSE otherwise.
+ */
+#define cb_GET_BIT(variable,bit) (((variable) & ((bit))) ? TRUE : FALSE)
+
+/**
+ * Calculate the number of elements in an array.
+ *
+ * @note Won't work on pointer to array as the sizeof(pointer) is 4.
+ *
+ * @param _array The array.
+ * @return Number of elements in array.
+ */
+#define ELEMENTS_OF(_array) (sizeof((_array)) / sizeof((_array)[0]))
+
+/**
+ * Sets (set to 1) a bit or bits in a variable.
+ *
+ * @param variable The variable.
+ * @param bit The bit or bits to set in the variable.
+ */
+#define cb_SET_BIT(variable,bit) ((variable) |= (bit))
+
+#define cb_UINT8_MAX ((cb_uint8)0xff)
+#define cb_UINT16_MAX ((cb_uint16)0xffff)
+#define cb_UINT32_MAX ((cb_uint32)0xffffffff)
+#define cb_INT8_MAX ((cb_int8)0x7f)
+#define cb_INT16_MAX ((cb_int16)0x7fff)
+#define cb_INT32_MAX ((cb_int32)0x7fffffff)
+#define cb_INT8_MIN ((cb_int8)0x80)
+#define cb_INT16_MIN ((cb_int16)0x8000)
+#define cb_INT32_MIN ((cb_int32)0x80000000)
+
+/* Packed struct default defines */
+#ifndef cb_PACKED_STRUCT_ATTR_INLINE_POST
+# define cb_PACKED_STRUCT_ATTR_INLINE_POST
+#endif
+#ifndef cb_PACKED_STRUCT_ATTR_INLINE_PRE
+# define cb_PACKED_STRUCT_ATTR_INLINE_PRE
+#endif
+#ifndef cb_PACKED_STRUCT_ATTR_PRE
+# define cb_PACKED_STRUCT_ATTR_PRE
+#endif
+#ifndef cb_PACKED_STRUCT_ATTR_POST
+# define cb_PACKED_STRUCT_ATTR_POST
+#endif
+
+#define cb_PACKED_STRUCT_BEGIN(name) \
+ cb_PACKED_STRUCT_ATTR_PRE \
+ typedef cb_PACKED_STRUCT_ATTR_INLINE_PRE struct name##_t
+
+#define cb_PACKED_STRUCT_END(name) \
+ cb_PACKED_STRUCT_ATTR_INLINE_POST name; \
+ cb_PACKED_STRUCT_ATTR_POST
+
+#ifdef __GNUC__
+# define DO_PRAGMA(x) _Pragma (#x)
+# define TODO(x) DO_PRAGMA(message ("TODO - " #x))
+#else
+# define TODO(x)
+#endif
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+#endif /* _cb_COMDEFS_H_ */
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,504 @@
+/*
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : GATT
+ * File : cb_gatt.h
+ *
+ * Description : Definitions and types for GATT(Generic Attribute Profile)
+ * that are in common for both client and server.
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_gatt.h
+ *
+ * @brief Definitions and types for GATT(Generic Attribute Profile)
+ * that are in common for both client and server.
+ */
+
+#ifndef _CB_GATT_H_
+#define _CB_GATT_H_
+
+#include "bt_types.h"
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define cbGATT_OK (0)
+#define cbGATT_ERROR (-1)
+#define cbGATT_ERROR_WRONG_STATE (-2)
+#define cbGATT_ERROR_WRONG_HANDLE (-3)
+#define cbGATT_ERROR_WRONG_PARAMETERS (-4)
+
+// This should be the same as in ATT
+#define cbGATT_DEFAULT_MTU_LE 23
+
+#define cbGATT_GET_MAX_READ_MULTIPLE_MTU(mtu) (mtu-1)
+#define cbGATT_GET_MAX_WRITE_CHARACTERISTIC_MTU(mtu) (mtu-3)
+#define cbGATT_GET_MAX_WRITE_SIGNED_CHARACTERISTIC_MTU(mtu) (mtu-13)
+#define cbGATT_GET_MAX_NOTIFICATION_MTU(mtu) (mtu-3)
+#define cbGATT_GET_MAX_INDICATION_MTU(mtu) (mtu-3)
+
+#define cbGATT_INVALID_ATTR_HANDLE 0x0000
+#define cbGATT_MIN_ATTR_HANDLE 0x0001
+#define cbGATT_MAX_ATTR_HANDLE 0xFFFF
+
+#define cbGATT_PROP_BCST 0x01 // Broadcast
+#define cbGATT_PROP_RD 0x02 // Readable
+#define cbGATT_PROP_WR_NO_RSP 0x04 // Write with no response
+#define cbGATT_PROP_WR 0x08 // Writable
+#define cbGATT_PROP_NOT 0x10 // Notify
+#define cbGATT_PROP_IND 0x20 // Indicate
+#define cbGATT_PROP_SIGN_WR 0x40 // Authenticated signed write
+#define cbGATT_PROP_EXT 0x80 // extended property
+
+#define cbGATT_PROP_EXT_REL_WR 0x0001 // Reliable write
+#define cbGATT_PROP_EXT_WR_AUX 0x0002 // auxiliary write
+#define cbGATT_CLIENT_CFG_NONE 0x0000 // Client configuration disabled
+#define cbGATT_CLIENT_CFG_NOT 0x0001 // Client notification configuration
+#define cbGATT_CLIENT_CFG_IND 0x0002 // Server indication configuration
+#define cbGATT_SERVER_CFG_BCST 0x0001 // Server broadcast configuration
+
+#define cbGATT_GET_BROADCAST_PROP(prop) ((0x01 & prop) == 0x01)
+#define cbGATT_GET_READ_PROP(prop) ((0x02 & prop) == 0x02)
+#define cbGATT_GET_WRITE_WITHOUT_RSP_PROP(prop) ((0x04 & prop) == 0x04)
+#define cbGATT_GET_WRITE_PROP(prop) ((0x08 & prop) == 0x08)
+#define cbGATT_GET_NOTIFY_PROP(prop) ((0x10 & prop) == 0x10)
+#define cbGATT_GET_INDICATE_PROP(prop) ((0x20 & prop) == 0x20)
+#define cbGATT_GET_AUTH_SIGNED_WRITES_PROP(prop) ((0x40 & prop) == 0x40)
+#define cbGATT_GET_EXTENDED_PROP(prop) ((0x80 & prop) == 0x80)
+
+#define cbGATT_GET_PROP_EXT_REL_WR(prop) ((0x0001 & prop) == 0x0001)
+#define cbGATT_GET_PROP_EXT_WR_AUX(prop) ((0x0002 & prop) == 0x0002)
+#define cbGATT_GET_CLIENT_CFG_NOT(cfg) ((0x0001 & cfg) == 0x0001)
+#define cbGATT_GET_CLIENT_CFG_IND(cfg) ((0x0002 & cfg) == 0x0002)
+#define cbGATT_GET_SERVER_CFG_BCST(cfg) ((0x0001 & cfg) == 0x0001)
+
+#define cbGATT_SET_BROADCAST_PROP(prop) (prop = prop | 0x01)
+#define cbGATT_SET_READ_PROPERTY(prop) (prop = prop | 0x02)
+#define cbGATT_SET_WRITE_WITHOUT_RSP_PROP(prop) (prop = prop | 0x04)
+#define cbGATT_SET_WRITE_PROP(prop) (prop = prop | 0x08)
+#define cbGATT_SET_NOTIFY_PROP(prop) (prop = prop | 0x10)
+#define cbGATT_SET_INDICATE_PROP(prop) (prop = prop | 0x20)
+#define cbGATT_SET_AUTH_SIGNED_WRITES_PROP(prop) (prop = prop | 0x40)
+#define cbGATT_SET_EXTENDED_PROP(prop) (prop = prop | 0x80)
+
+#define cbGATT_SET_PROP_EXT_REL_WR(prop) (prop = prop | 0x0001)
+#define cbGATT_SET_PROP_EXT_WR_AUX(prop) (prop = prop | 0x0002)
+#define cbGATT_SET_CLIENT_CFG_NOT(cfg) (cfg = cfg | 0x0001)
+#define cbGATT_SET_CLIENT_CFG_IND(cfg) (cfg = cfg | 0x0002)
+#define cbGATT_SET_SERVER_CFG_BCST(cfg) (cfg = cfg | 0x0001)
+
+// Below specification level as of 2011-09-13
+#define cbGATT_SERVICE_GENERIC_ACCESS 0x1800 // 0.5
+#define cbGATT_SERVICE_GENERIC_ATTRIBUTE 0x1801 // 0.5
+#define cbGATT_SERVICE_IMMEDIATE_ALERT 0x1802 // Adopted
+#define cbGATT_SERVICE_LINK_LOSS 0x1803 // Adopted
+#define cbGATT_SERVICE_TX_POWER 0x1804 // Adopted
+#define cbGATT_SERVICE_CURRENT_TIME 0x1805 // Prototype
+#define cbGATT_SERVICE_REFERENCE_TIME_UPDATE 0x1806 // Prototype
+#define cbGATT_SERVICE_NEXT_DST_CHANGE 0x1807 // Prototype
+#define cbGATT_SERVICE_HEALTH_THERMOMETER 0x1809 // Adopted
+#define cbGATT_SERVICE_DEVICE_INFORMATION 0x180A // Adopted
+#define cbGATT_SERVICE_NETWORK_AVAILABILITY 0x180B // 0.9
+#define cbGATT_SERVICE_WATCHDOG 0x180C // 0.5
+#define cbGATT_SERVICE_HEART_RATE 0x180D // Adopted
+#define cbGATT_SERVICE_PHONE_ALERT_STATUS 0x180E // Prototype
+#define cbGATT_SERVICE_BATTERY_SERVICE 0x180F // Prototype
+#define cbGATT_SERVICE_BLOOD_PRESSURE 0x1810 // 0.9
+#define cbGATT_SERVICE_ALERT_NOTIFICATION 0x1811 // Prototype
+#define cbGATT_SERVICE_HUMAN_INTERFACE_DEVICE 0x1812 // 0.5
+#define cbGATT_SERVICE_SCAN_PARAMETER 0x1813 // 0.5
+
+#define cbGATT_PRIMARY_SERVICE_DECL 0x2800
+#define cbGATT_SECONDARY_SERVICE_DECL 0x2801
+#define cbGATT_INCLUDE_DECL 0x2802
+#define cbGATT_CHAR_DECL 0x2803
+#define cbGATT_CHAR_EXT_PROP 0x2900
+#define cbGATT_CHAR_USER_DESC 0x2901
+#define cbGATT_CLIENT_CHAR_CONFIG 0x2902
+#define cbGATT_SERVER_CHAR_CONFIG 0x2903
+#define cbGATT_CHAR_FORMAT 0x2904
+#define cbGATT_CHAR_AGGR_FORMAT 0x2905
+
+#define cbGATT_CHAR_GAP_DEVICE_NAME 0x2A00 // Adopted
+#define cbGATT_CHAR_GAP_APPEARANCE 0x2A01 // Adopted
+#define cbGATT_CHAR_GAP_PERIP_PRIV 0x2A02 // Adopted
+#define cbGATT_CHAR_GAP_RECONN_ADDR 0x2A03 // Adopted
+#define cbGATT_CHAR_GAP_CONN_PARAMS 0x2A04 // Adopted
+#define cbGATT_CHAR_GATT_SVC_CHANGED 0x2A05 // Adopted
+#define cbGATT_CHAR_ALERT_LEVEL 0x2A06 // Adopted
+#define cbGATT_CHAR_TX_POWER_LEVEL 0x2A07 // Adopted
+#define cbGATT_CHAR_DATE_TIME 0x2A08 // Adopted
+#define cbGATT_CHAR_DAY_OF_WEEK 0x2A09 // Prototype
+#define cbGATT_CHAR_DAY_DATE_TIME 0x2A0A // Prototype
+#define cbGATT_CHAR_EXACT_TIME_100 0x2A0B // 0.9
+#define cbGATT_CHAR_EXACT_TIME_256 0x2A0C // Prototype
+#define cbGATT_CHAR_DST_OFFSET 0x2A0D // Prototype
+#define cbGATT_CHAR_TIME_ZONE 0x2A0E // Prototype
+#define cbGATT_CHAR_LOCAL_TIME_INFORMATION 0x2A0F // Prototype
+#define cbGATT_CHAR_SECONDARY_TIME_ZONE 0x2A10 // 0.9
+#define cbGATT_CHAR_TIME_WITH_DST 0x2A11 // Prototype
+#define cbGATT_CHAR_TIME_ACCURACY 0x2A12 // Prototype
+#define cbGATT_CHAR_TIME_SOURCE 0x2A13 // Prototype
+#define cbGATT_CHAR_REFERENCE_TIME_INFORMATION 0x2A14 // Prototype
+#define cbGATT_CHAR_TIME_BROADCAST 0x2A15 // 0.9
+#define cbGATT_CHAR_TIME_UPDATE_CONTROL_POINT 0x2A16 // Prototype
+#define cbGATT_CHAR_TIME_UPDATE_STATE 0x2A17 // Prototype
+#define cbGATT_CHAR_BOOLEAN 0x2A18 // 0.9
+#define cbGATT_CHAR_BATTERY_LEVEL 0x2A19 // 0.9
+#define cbGATT_CHAR_BATTERY_POWER_STATE 0x2A1A // 0.9
+#define cbGATT_CHAR_BATTERY_LEVEL_STATE 0x2A1B // 0.9
+#define cbGATT_CHAR_TEMP_MEASUREMENT 0x2A1C // Adopted
+#define cbGATT_CHAR_TEMP_TYPE 0x2A1D // Adopted
+#define cbGATT_CHAR_INTERMEDIATE_TEMP 0x2A1E // Adopted
+#define cbGATT_CHAR_TEMP_CELSIUS 0x2A1F // 0.9
+#define cbGATT_CHAR_TEMP_FAHRENHEIT 0x2A20 // 0.9
+#define cbGATT_CHAR_MEASUREMENT_INTERVAL 0x2A21 // Adopted
+#define cbGATT_CHAR_SYSTEM_ID 0x2A23 // Adopted
+#define cbGATT_CHAR_MODEL_NUMBER_STRING 0x2A24 // Adopted
+#define cbGATT_CHAR_SERIAL_NUMBER_STRING 0x2A25 // Adopted
+#define cbGATT_CHAR_FIRMWARE_REV_STRING 0x2A26 // Adopted
+#define cbGATT_CHAR_HARDWARE_REV_STRING 0x2A27 // Adopted
+#define cbGATT_CHAR_SOFTWARE_REV_STRING 0x2A28 // Adopted
+#define cbGATT_CHAR_MANUFACTURER_NAME_STRING 0x2A29 // Adopted
+#define cbGATT_CHAR_IEEE_REG_CERT_DATA_LIST 0x2A2A // Adopted
+#define cbGATT_CHAR_CURRENT_TIME 0x2A2B // Prototype
+#define cbGATT_CHAR_ELEVATION 0x2A2C // 0.5
+#define cbGATT_CHAR_LATITUDE 0x2A2D // 0.5
+#define cbGATT_CHAR_LONGITUDE 0x2A2E // 0.5
+#define cbGATT_CHAR_POSITION_2D 0x2A2F // 0.5
+#define cbGATT_CHAR_POSITION_3D 0x2A30 // 0.5
+#define cbGATT_CHAR_VENDOR_ID_V1_1 0x2A31 // 0.5
+#define cbGATT_CHAR_PRODUCT_ID 0x2A32 // 0.5
+#define cbGATT_CHAR_HID_VERSION 0x2A33 // 0.5
+#define cbGATT_CHAR_VENDOR_ID_SOURCE 0x2A34 // 0.5
+#define cbGATT_CHAR_BLOOD_PRESSURE_MEASUREMENT 0x2A35 // 0.9
+#define cbGATT_CHAR_INTERMEDIATE_BLOOD_PRESSURE 0x2A36 // 0.9
+#define cbGATT_CHAR_HEART_RATE_MEASUREMENT 0x2A37 // Adopted
+#define cbGATT_CHAR_BODY_SENSOR_LOCATION 0x2A38 // Adopted
+#define cbGATT_CHAR_HEART_RATE_CONTROL_POINT 0x2A39 // Adopted
+#define cbGATT_CHAR_REMOVABLE 0x2A3A // 0.5
+#define cbGATT_CHAR_SERVICE_REQUIRED 0x2A3B // 0.9
+#define cbGATT_CHAR_SCIENTIFIC_TEMP_CELSIUS 0x2A3C // 0.9
+#define cbGATT_CHAR_STRING 0x2A3D // 0.9
+#define cbGATT_CHAR_NETWORK_AVAILABILITY 0x2A3E // 0.9
+#define cbGATT_CHAR_ALERT_STATUS 0x2A3F // Prototype
+#define cbGATT_CHAR_RINGER_CONTROL_POINT 0x2A40 // Prototype
+#define cbGATT_CHAR_RINGER_SETTING 0x2A41 // Prototype
+#define cbGATT_CHAR_ALERT_CATEGORY_ID_BIT_MASK 0x2A42 // 0.9
+#define cbGATT_CHAR_ALERT_CATEGORY_ID 0x2A43 // 0.9
+#define cbGATT_CHAR_ALERT_NOTIF_CONTROL_POINT 0x2A44 // 0.9
+#define cbGATT_CHAR_UNREAD_ALERT_STATUS 0x2A45 // 0.9
+#define cbGATT_CHAR_NEW_ALERT 0x2A46 // 0.9
+#define cbGATT_CHAR_SUPPORTED_NEW_ALERT_CATEGORY 0x2A47 // 0.9
+#define cbGATT_CHAR_SUPPORTED_UNREAD_ALERT_CATEGORY 0x2A48 // 0.9
+#define cbGATT_CHAR_BLOOD_PRESSURE_FEATURE 0x2A49 // 0.9
+
+/*==============================================================================
+ * TYPES
+ *==============================================================================
+ */
+
+typedef enum
+{
+ cbGATT_WRITE_METHOD_WITH_RSP,
+ cbGATT_WRITE_METHOD_NO_RSP,
+ cbGATT_WRITE_METHOD_SIGN,
+ cbGATT_WRITE_METHOD_RELIABLE_PREPARE,
+} cbGATT_WriteMethod;
+
+typedef enum
+{
+ cbGATT_UNIT_UNITLESS = 0x2700,
+ cbGATT_UNIT_LENGTH_METRE = 0x2701,
+ cbGATT_UNIT_MASS_KILOGRAM = 0x2702,
+ cbGATT_UNIT_TIME_SECOND = 0x2703,
+ cbGATT_UNIT_ELECTRIC_CURRENT_AMPERE = 0x2704,
+ cbGATT_UNIT_THERMODYNAMIC_TEMPERATURE_KELVIN = 0x2705,
+ cbGATT_UNIT_AMOUNT_OF_SUBSTANCE_MOLE = 0x2706,
+ cbGATT_UNIT_LUMINOUS_INTENSITY_CANDELA = 0x2707,
+ cbGATT_UNIT_AREA_SQUARE_METRES = 0x2710,
+ cbGATT_UNIT_VOLUME_CUBIC_METRES = 0x2711,
+ cbGATT_UNIT_VELOCITY_METRES_PER_SECOND = 0x2712,
+ cbGATT_UNIT_ACCELERATION_METRES_PER_SECOND_SQUARED = 0x2713,
+ cbGATT_UNIT_WAVENUMBER_RECIPROCAL_METRE = 0x2714,
+ cbGATT_UNIT_DENSITY_KILOGRAM_PER_CUBIC_METRE = 0x2715,
+ cbGATT_UNIT_SURFACE_DENSITY_KILOGRAM_PER_SQUARE_METRE = 0x2716,
+ cbGATT_UNIT_SPECIFIC_VOLUME_CUBIC_METRE_PER_KILOGRAM = 0x2717,
+ cbGATT_UNIT_CURRENT_DENSITY_AMPERE_PER_SQUARE_METRE = 0x2718,
+ cbGATT_UNIT_MAGNETIC_FIELD_STRENGTH_AMPERE_PER_METRE = 0x2719,
+ cbGATT_UNIT_AMOUNT_CONCENTRATION_MOLE_PER_CUBIC_METRE = 0x271A,
+ cbGATT_UNIT_MASS_CONCENTRATION_KILOGRAM_PER_CUBIC_METRE = 0x271B,
+ cbGATT_UNIT_LUMINANCE_CANDELA_PER_SQUARE_METRE = 0x271C,
+ cbGATT_UNIT_REFRACTIVE_INDEX = 0x271D,
+ cbGATT_UNIT_RELATIVE_PERMEABILITY = 0x271E,
+ cbGATT_UNIT_PLANE_ANGLE_RADIAN = 0x2720,
+ cbGATT_UNIT_SOLID_ANGLE_STERADIAN = 0x2721,
+ cbGATT_UNIT_FREQUENCY_HERTZ = 0x2722,
+ cbGATT_UNIT_FORCE_NEWTON = 0x2723,
+ cbGATT_UNIT_PRESSURE_PASCAL = 0x2724,
+ cbGATT_UNIT_ENERGY_JOULE = 0x2725,
+ cbGATT_UNIT_POWER_WATT = 0x2726,
+ cbGATT_UNIT_ELECTRIC_CHARGE_COULOMB = 0x2727,
+ cbGATT_UNIT_ELECTRIC_POTENTIAL_DIFFERENCE_VOLT = 0x2728,
+ cbGATT_UNIT_CAPACITANCE_FARAD = 0x2729,
+ cbGATT_UNIT_ELECTRIC_RESISTANCE_OHM = 0x272A,
+ cbGATT_UNIT_ELECTRIC_CONDUCTANCE_SIEMENS = 0x272B,
+ cbGATT_UNIT_MAGNETIC_FLEX_WEBER = 0x272C,
+ cbGATT_UNIT_MAGNETIC_FLEX_DENSITY_TESLA = 0x272D,
+ cbGATT_UNIT_INDUCTANCE_HENRY = 0x272E,
+ cbGATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_CELSIUS = 0x272F,
+ cbGATT_UNIT_LUMINOUS_FLUX_LUMEN = 0x2730,
+ cbGATT_UNIT_ILLUMINANCE_LUX = 0x2731,
+ cbGATT_UNIT_ACTIVITY_REFERRED_TO_A_RADIONUCLIDE_BECQUEREL = 0x2732,
+ cbGATT_UNIT_ABSORBED_DOSE_GRAY = 0x2733,
+ cbGATT_UNIT_DOSE_EQUIVALENT_SIEVERT = 0x2734,
+ cbGATT_UNIT_CATALYTIC_ACTIVITY_KATAL = 0x2735,
+ cbGATT_UNIT_DYNAMIC_VISCOSITY_PASCAL_SECOND = 0x2740,
+ cbGATT_UNIT_MOMENT_OF_FORCE_NEWTON_METRE = 0x2741,
+ cbGATT_UNIT_SURFACE_TENSION_NEWTON_PER_METRE = 0x2742,
+ cbGATT_UNIT_ANGULAR_VELOCITY_RADIAN_PER_SECOND = 0x2743,
+ cbGATT_UNIT_ANGULAR_ACCELERATION_RADIAN_PER_SECOND_SQUARED = 0x2744,
+ cbGATT_UNIT_HEAT_FLUX_DENSITY_WATT_PER_SQUARE_METRE = 0x2745,
+ cbGATT_UNIT_HEAT_CAPACITY_JOULE_PER_KELVIN = 0x2746,
+ cbGATT_UNIT_SPECIFIC_HEAT_CAPACITY_JOULE_PER_KILOGRAM_KELVIN = 0x2747,
+ cbGATT_UNIT_SPECIFIC_ENERGY_JOULE_PER_KILOGRAM = 0x2748,
+ cbGATT_UNIT_THERMAL_CONDUCTIVITY_WATT_PER_METRE_KELVIN = 0x2749,
+ cbGATT_UNIT_ENERGY_DENSITY_JOULE_PER_CUBIC_METRE = 0x274A,
+ cbGATT_UNIT_ELECTRIC_FIELD_STRENGTH_VOLT_PER_METRE = 0x274B,
+ cbGATT_UNIT_ELECTRIC_CHARGE_DENSITY_COULOMB_PER_CUBIC_METRE = 0x274C,
+ cbGATT_UNIT_SURFACE_CHARGE_DENSITY_COULOMB_PER_SQUARE_METRE = 0x274D,
+ cbGATT_UNIT_ELECTRIC_FLUX_DENSITY_COULOMB_PER_SQUARE_METRE = 0x274E,
+ cbGATT_UNIT_PERMITTIVITY_FARAD_PER_METRE = 0x274F,
+ cbGATT_UNIT_PERMEABILITY_HENRY_PER_METRE = 0x2750,
+ cbGATT_UNIT_MOLAR_ENERGY_JOULE_PER_MOLE = 0x2751,
+ cbGATT_UNIT_MOLAR_ENTROPY_JOULE_PER_MOLE_KELVIN = 0x2752,
+ cbGATT_UNIT_EXPOSURE_COULOMB_PER_KILOGRAM = 0x2753,
+ cbGATT_UNIT_ABSORBED_DOSE_RATE_GRAY_PER_SECOND = 0x2754,
+ cbGATT_UNIT_RADIANT_INTENSITY_WATT_PER_STERADIAN = 0x2755,
+ cbGATT_UNIT_RADIANCE_WATT_PER_SQUARE_METER_STERADIAN = 0x2756,
+ cbGATT_UNIT_CATALYTIC_ACTIVITY_CONCENTRATION_KATAL_PER_CUBIC_METRE = 0x2757,
+ cbGATT_UNIT_TIME_MINUTE = 0x2760,
+ cbGATT_UNIT_TIME_HOUR = 0x2761,
+ cbGATT_UNIT_TIME_DAY = 0x2762,
+ cbGATT_UNIT_PLANE_ANGLE_DEGREE = 0x2763,
+ cbGATT_UNIT_PLANE_ANGLE_MINUTE = 0x2764,
+ cbGATT_UNIT_PLANE_ANGLE_SECOND = 0x2765,
+ cbGATT_UNIT_AREA_HECTARE = 0x2766,
+ cbGATT_UNIT_VOLUME_LITRE = 0x2767,
+ cbGATT_UNIT_MASS_TONNE = 0x2768,
+ cbGATT_UNIT_PRESSURE_BAR = 0x2780,
+ cbGATT_UNIT_PRESSURE_MILLIMETRE_OF_MERCURY = 0x2781,
+ cbGATT_UNIT_LENGTH_ANGSTROM = 0x2782,
+ cbGATT_UNIT_LENGTH_NAUTICAL_MILE = 0x2783,
+ cbGATT_UNIT_AREA_BARN = 0x2784,
+ cbGATT_UNIT_VELOCITY_KNOT = 0x2785,
+ cbGATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_NEPER = 0x2786,
+ cbGATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_BEL = 0x2787,
+ cbGATT_UNIT_LENGTH_YARD = 0x27A0,
+ cbGATT_UNIT_LENGTH_PARSEC = 0x27A1,
+ cbGATT_UNIT_LENGTH_INCH = 0x27A2,
+ cbGATT_UNIT_LENGTH_FOOT = 0x27A3,
+ cbGATT_UNIT_LENGTH_MILE = 0x27A4,
+ cbGATT_UNIT_PRESSURE_POUND_FORCE_PER_SQUARE_INCH = 0x27A5,
+ cbGATT_UNIT_VELOCITY_KILOMETRE_PER_HOUR = 0x27A6,
+ cbGATT_UNIT_VELOCITY_MILE_PER_HOUR = 0x27A7,
+ cbGATT_UNIT_ANGULAR_VELOCITY_REVOLUTION_PER_MINUTE = 0x27A8,
+ cbGATT_UNIT_ENERGY_GRAM_CALORIE = 0x27A9,
+ cbGATT_UNIT_ENERGY_KILOGRAM_CALORIE = 0x27AA,
+ cbGATT_UNIT_ENERGY_KILOWATT_HOUR = 0x27AB,
+ cbGATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_FAHRENHEIT = 0x27AC,
+ cbGATT_UNIT_PERCENTAGE = 0x27AD,
+ cbGATT_UNIT_PER_MILLE = 0x27AE,
+ cbGATT_UNIT_PERIOD_BEATS_PER_MINUTE = 0x27AF,
+ cbGATT_UNIT_ELECTRIC_CHARGE_AMPERE_HOURS = 0x27B0,
+ cbGATT_UNIT_MASS_DENSITY_MILLIGRAM_PER_DECILITRE = 0x27B1,
+ cbGATT_UNIT_MASS_DENSITY_MILLIMOLE_PER_LITRE = 0x27B2,
+ cbGATT_UNIT_TIME_YEAR = 0x27B3,
+ cbGATT_UNIT_TIME_MONTH = 0x27B4,
+} cbGATT_Unit;
+
+typedef enum
+{
+
+ // Note, check http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.cbGATT.characteristic_presentation_format.xml
+ // for any changes
+ cbGATT_FORMAT_TYPE_BOOLEAN = 0x01,
+ cbGATT_FORMAT_TYPE_2BIT = 0x02,
+ cbGATT_FORMAT_TYPE_NIBBLE = 0x03,
+ cbGATT_FORMAT_TYPE_UINT8 = 0x04,
+ cbGATT_FORMAT_TYPE_UINT12 = 0x05,
+ cbGATT_FORMAT_TYPE_UINT16 = 0x06,
+ cbGATT_FORMAT_TYPE_UINT24 = 0x07,
+ cbGATT_FORMAT_TYPE_UINT32 = 0x08,
+ cbGATT_FORMAT_TYPE_UINT48 = 0x09,
+ cbGATT_FORMAT_TYPE_UINT64 = 0x0A,
+ cbGATT_FORMAT_TYPE_UINT128 = 0x0B,
+ cbGATT_FORMAT_TYPE_SINT8 = 0x0C,
+ cbGATT_FORMAT_TYPE_SINT12 = 0x0D,
+ cbGATT_FORMAT_TYPE_SINT16 = 0x0E,
+ cbGATT_FORMAT_TYPE_SINT24 = 0x0F,
+ cbGATT_FORMAT_TYPE_SINT32 = 0x10,
+ cbGATT_FORMAT_TYPE_SINT48 = 0x11,
+ cbGATT_FORMAT_TYPE_SINT64 = 0x12,
+ cbGATT_FORMAT_TYPE_SINT128 = 0x13,
+ cbGATT_FORMAT_TYPE_FLOAT32 = 0x14,
+ cbGATT_FORMAT_TYPE_FLOAT64 = 0x15,
+ cbGATT_FORMAT_TYPE_SFLOAT = 0x16,
+ cbGATT_FORMAT_TYPE_FLOAT = 0x17,
+ cbGATT_FORMAT_TYPE_DUINT16 = 0x18,
+ cbGATT_FORMAT_TYPE_UTF8S = 0x19,
+ cbGATT_FORMAT_TYPE_UTF16S = 0x1A,
+ cbGATT_FORMAT_TYPE_STRUCT = 0x1B,
+} cbGATT_FormatType;
+
+typedef enum
+{
+ // This should map to ATT_TRole
+ cbGATT_ROLE_CLIENT = 0,
+ cbGATT_ROLE_SERVER = 1,
+ cbGATT_ROLE_BOTH = 2
+} cbGATT_Role;
+
+typedef enum
+{
+ cbGATT_NAMESPACE_BT_SIG = 0x01,
+} cbGATT_Namespace;
+
+typedef enum
+{
+ cbGATT_NAMESPACE_DESC_UNKNOWN = 0x0000,
+} cbGATT_NamespaceDesc;
+
+typedef struct
+{
+ cbGATT_FormatType format;
+ cb_uint8 exponent;
+ cbGATT_Unit unit;
+ cbGATT_Namespace gattNamespace;
+ cbGATT_NamespaceDesc namespaceDesc;
+} cbGATT_CharFormat;
+
+// This enum must match ATT_TErrorCode for the first two parts
+// (not the GATT specific)
+typedef enum
+{
+ cbGATT_ERROR_CODE_OK = 0x00,
+ cbGATT_ERROR_CODE_INVALID_HANDLE = 0x01,
+ cbGATT_ERROR_CODE_READ_NOT_PERMITTED = 0x02,
+ cbGATT_ERROR_CODE_WRITE_NOT_PERMITTED = 0x03,
+ cbGATT_ERROR_CODE_INVALID_PDU = 0x04,
+ cbGATT_ERROR_CODE_INSUFFICIENT_AUTHENTICATION = 0x05,
+ cbGATT_ERROR_CODE_REQUEST_NOT_SUPPORTED = 0x06,
+ cbGATT_ERROR_CODE_INVALID_OFFSET = 0x07,
+ cbGATT_ERROR_CODE_INSUFFICIENT_AUTHORIZATION = 0x08,
+ cbGATT_ERROR_CODE_PREPARE_FULL_QUEUE = 0x09,
+ cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND = 0x0A,
+ cbGATT_ERROR_CODE_ATTRIBUTE_NOT_LONG = 0x0B,
+ cbGATT_ERROR_CODE_INSUFFICIENT_ENCRYPT_KEY_SIZE = 0x0C,
+ cbGATT_ERROR_CODE_INVALID_ATTRIBUTE_VALUE_LENGTH = 0x0D,
+ cbGATT_ERROR_CODE_UNLIKELY_ERROR = 0x0E,
+ cbGATT_ERROR_CODE_INSUFFICIENT_ENCRYPTION = 0x0F,
+ cbGATT_ERROR_CODE_UNSUPPORTED_GROUP_TPYE = 0x10,
+ cbGATT_ERROR_CODE_INSUFFICIENT_RESOURCES = 0x11,
+
+ cbGATT_ERROR_CODE_OUT_OF_RANGE = 0xFF,
+ cbGATT_ERROR_CODE_PROCEDURE_ALREADY_IN_PROGRESS = 0xFE,
+ cbGATT_ERROR_CODE_IMPROPER_CLIENT_CHAR_CFG = 0xFD,
+
+ // Special error codes not according to BT spec.
+ // Will never be sent over the air.
+ cbGATT_ERROR_CODE_TRANSACTION_TIMEOUT = 0x80,
+ cbGATT_ERROR_CODE_DISCONNECTED = 0x81,
+ cbGATT_ERROR_CODE_RELIABLE_CHECK_FAILED = 0x82,
+ cbGATT_ERROR_CODE_DELAYED_RSP = 0x83,
+} cbGATT_ErrorCode;
+
+
+typedef enum
+{
+ // This must map to ATT_TUuidFormat
+ cbGATT_UUID_16 = 0x01,
+ cbGATT_UUID_128 = 0x02
+} cbGATT_UuidFormat;
+
+typedef enum
+{
+ cbGATT_FINAL_DATA = 0x00,
+ cbGATT_MORE_DATA = 0x01,
+ cbGATT_CANCEL_DATA = 0x02
+} cbGATT_WriteLongCharFlag;
+
+typedef struct
+{
+ // This must map to ATT_TUuid
+ union
+ {
+ cb_uint16 uuid16;
+ cb_uint8 uuid128[16];
+ };
+ cbGATT_UuidFormat format;
+} cbGATT_Uuid;
+
+/**
+ * Called when an ACL connection is established
+ * @param handle Connection handle
+ * @param errorCode Connect error code
+ * @param role TODO Add a proper type for role client/server master/slave central/peripheral
+ * @param peerBdAddress Address of remote device
+ * @param connInterval Connection interval
+ * @param connLatency Connection latency
+ * @param connTmo Connection timeout
+ * @param masterClkAccuracy Master clock accuracy
+ * @return None
+ */
+typedef void (*cbGATT_ConnComplEvt)(
+ TConnHandle handle,
+ TErrorCode errorCode,
+ cb_uint8 role,
+ TBdAddr peerBdAddress,
+ cb_uint16 connInterval,
+ cb_uint16 connLatency,
+ cb_uint16 connTmo,
+ cb_uint8 masterClkAccuracy);
+/**
+ * Called when ACL connection is lost.
+ * @param handle Connection handle
+ * @param errorCode Disconnect error code
+ * @return None
+ */
+typedef void (*cbGATT_DisconnectEvt)(
+ TConnHandle handle,
+ TErrorCode errorCode);
+
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,652 @@
+/*
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component GATT
+ * File cb_gatt_client.h
+ *
+ * Description Definitions and types for GATT client functionality
+ *
+ */
+
+/**
+ * @file cb_gatt_client.h
+ *
+ * This file contains all GATT client functionality. There are some restrictions
+ * on how this API is used.
+ * - Pointer data in callbacks are only valid in the context of the callback
+ * - Only one request at a time should be done from each app(app handle). The
+ * app must wait until all responses from an outstanding request have been
+ * received.
+ * - In the callback of the request another request can not be done except when
+ * the request is interrupted by setting the return value to FALSE
+ * or when in the last callback which contains an error code.
+ * - Most of the GATT requests can be interrupted by returning FALSE in the
+ * callback.
+ *
+ * See Bluetooth 4.0 specification for more info on GATT and ATT chapters:
+ * https://www.bluetooth.org/en-us/specification/adopted-specifications
+ *
+ */
+
+#ifndef _CB_GATT_CLIENT_H_
+#define _CB_GATT_CLIENT_H_
+
+#include "bt_types.h"
+#include "cb_gatt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*==============================================================================
+ * TYPES
+ *==============================================================================
+ */
+
+/**
+ * Callback for discover all primary services. This callback will be called
+ * for each primary service found.
+ * @param connHandle Connection handle
+ * @param errorCode cbGATT_ERROR_CODE_OK when succeeded
+ * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ * when search is finished.
+ * cbGATT_ERROR_CODE_ on failure
+ * @param startGroupHandle Start handle of the service
+ * @param endGroupHandle End handle of the service
+ * @param pUuid Pointer to UUID of the service
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverAllPrimaryServicesCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint16 startGroupHandle,
+ cb_uint16 endGroupHandle,
+ cbGATT_Uuid* pUuid);
+
+/**
+ * Callback for discover all secondary services. This callback will be called
+ * for each secondary service found.
+ * @param connHandle Connection handle
+ * @param errorCode cbGATT_ERROR_CODE_OK when succeeded
+ * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ * when search is finished.
+ * cbGATT_ERROR_CODE on failure
+ * @param startGroupHandle Start handle of the service
+ * @param endGroupHandle End handle of the service
+ * @param pUuid Pointer to UUID of the service
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverAllSecondaryServicesCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint16 startGroupHandle,
+ cb_uint16 endGroupHandle,
+ cbGATT_Uuid* pUuid);
+
+/**
+ * Callback for discover all primary services by UUID. This callback will be
+ * called for each primary service found.
+ * @param connHandle Connection handle
+ * @param errorCode cbGATT_ERROR_CODE_OK when succeeded
+ * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ * when search is finished.
+ * cbGATT_ERROR_CODE_* on failure
+ * @param startGroupHandle Start handle of the service
+ * @param endGroupHandle End handle of the service
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverPrimaryServiceByUuidCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint16 startHandle,
+ cb_uint16 endHandle);
+
+/**
+ * Callback for find included services. This callback will be called
+ * for each service found.
+ * @param connHandle Connection handle
+ * @param errorCode cbGATT_ERROR_CODE_OK when succeeded
+ * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ * when search is finished.
+ * cbGATT_ERROR_CODE_* on failure
+ * @param startGroupHandle Start handle of the service
+ * @param endGroupHandle End handle of the service
+ * @param pUuid Pointer to UUID of the service
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_FindIncludedServicesCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint16 attrHandle,
+ cb_uint16 startGroupHandle,
+ cb_uint16 endGroupHandle,
+ cbGATT_Uuid* pUuid);
+
+/**
+ * Callback for discover all characteristics of service. This callback will
+ * be called for each characteristic found.
+ * @param connHandle Connection handle
+ * @param errorCode cbGATT_ERROR_CODE_OK when succeeded
+ * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ * when search is finished.
+ * cbGATT_ERROR_CODE_* on failure
+ * @param attrHandle Attribute handle of the characteristic
+ * @param properties Bitmap of properties of the characteristic.
+ * See cbGATT_PROP_*.
+ * @param valueHandle Attribute handle of the characteristic value.
+ * This is where the actual data is located.
+ * @param pUuid Pointer to UUID of the characteristic
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverAllCharacteristicsOfServiceCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint16 attrHandle,
+ cb_uint8 properties,
+ cb_uint16 valueHandle,
+ cbGATT_Uuid* pUuid);
+
+/**
+ * Callback for discover all descriptors of a characteristic. This callback
+ * will be called for each descriptor found.
+ * @param connHandle Connection handle
+ * @param errorCode cbGATT_ERROR_CODE_OK when succeeded
+ * cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ * when search is finished.
+ * cbGATT_ERROR_CODE_* on failure
+ * @param charAttrHandle Attribute handle of the characteristic
+ * @param attrHandle Attribute handle of the characteristic descriptor.
+ * @param pUuid Pointer to UUID of the descriptor
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverAllCharacteristicDescriptorsCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint16 charAttrHandle,
+ cb_uint16 attrHandle,
+ cbGATT_Uuid* pUuid);
+
+/**
+ * Callback for read characteristic. This callback will be called for each
+ * data chunk read.
+ * The last callback will contain either an error code or moreToRead = FALSE
+ * @param connHandle Connection handle
+ * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded
+ * @param attrHandle Attribute handle of the characteristic
+ * @param pAttrValue Pointer to the read data chunk.
+ * @param length Length of the read data chunk
+ * @param moreToRead TRUE = more data to read from the characteristic
+ * FALSE = no more data to read
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_ReadCharacteristicCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint16 attrHandle,
+ cb_uint8* pAttrValue,
+ cb_uint16 length,
+ cb_boolean moreToRead);
+
+/**
+ * Callback for read characteristic by UUID. This callback will be called
+ * for each data chunk read.
+ * The last callback will contain either an error code or moreToRead = FALSE
+ * @param connHandle Connection handle
+ * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded
+ * @param attrHandle Attribute handle of the characteristic
+ * @param pAttrValue Pointer to the read data chunk.
+ * @param length Length of the read data chunk
+ * @param moreToRead TRUE = more data to read from the characteristic
+ * FALSE = no more data to read
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_ReadCharacteristicByUuidCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint16 attrHandle,
+ cb_uint8* pAttrValue,
+ cb_uint16 length,
+ cb_boolean moreToRead);
+
+// TODO to have or not??
+typedef void (*cbGATT_ReadLongCharacteristicCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint8* pAttrValue,
+ cb_uint16 length);
+
+/**
+ * Callback for read multiple characteristics. This callback will be called
+ * for each data chunk read.
+ * The last callback will contain either an error code or moreToRead = FALSE
+ * @param connHandle Connection handle
+ * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded
+ * @param pAttrValues Pointer to the read data chunk.
+ * @param length Length of the read data chunk
+ * @param moreToRead TRUE = more data to read from the characteristic(s)
+ * FALSE = no more data to read
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_ReadMultipleCharacteristicCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode,
+ cb_uint8* pAttrValues,
+ cb_uint16 length,
+ cb_boolean moreToRead);
+
+/**
+ * Callback for write characteristic with response from the remote side
+ * @param connHandle Connection handle
+ * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_WriteCharacteristicCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode);
+
+/**
+ * Callback for write characteristic with no response from the remote side
+ * @param connHandle Connection handle
+ * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_WriteCharacteristicNoRspCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode);
+
+/**
+ * Callback for write characteristic configuration with response from the
+ * remote side.
+ * @param connHandle Connection handle
+ * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_WriteCharacteristicConfigCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode);
+
+/**
+ * Callback for write long characteristic with response from the
+ * remote side.
+ * @param connHandle Connection handle
+ * @param errorCode Error code, cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_WriteLongCharacteristicCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode);
+
+/**
+* Callback for receiving value indication. The client configuration
+ * notifications must have been enabled before this will be sent to the app.
+ * Note that the indication is replied by GATT when exiting the callback.
+ * @param connHandle Connection handle
+ * @param attrHandle Attribute handle of the indicated value
+ * @param pAttrValue Pointer to the value data
+ * @param length Length of the value data
+ */
+typedef void (*cbGATT_CharacteristicValueIndication)(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint8* pAttrValue,
+ cb_uint16 length);
+
+/**
+ * Callback for receiving value notification. The client configuration
+ * notifications must have been enabled before this will be sent to the app.
+ * @param connHandle Connection handle
+ * @param attrHandle Attribute handle of the notified value
+ * @param pAttrValue Pointer to the value data
+ * @param length Length of the value data
+ */
+typedef void (*cbGATT_CharacteristicValueNotification)(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint8* pAttrValue,
+ cb_uint16 length);
+
+typedef struct
+{
+ cbGATT_ConnComplEvt connComplEvt;
+ cbGATT_DisconnectEvt disconnectEvt;
+ cbGATT_DiscoverAllPrimaryServicesCnf discoverAllPrimaryServicesCnf;
+ cbGATT_DiscoverAllSecondaryServicesCnf discoverAllSecondaryServicesCnf;
+ cbGATT_DiscoverPrimaryServiceByUuidCnf discoverPrimaryServiceByUuidCnf;
+ cbGATT_FindIncludedServicesCnf findIncludedServicesCnf;
+ cbGATT_DiscoverAllCharacteristicsOfServiceCnf discoverAllCharacteristicsOfServiceCnf;
+ cbGATT_DiscoverAllCharacteristicDescriptorsCnf discoverAllCharacteristicDescriptorsCnf;
+ cbGATT_ReadCharacteristicCnf readCharacteristicCnf;
+ cbGATT_ReadCharacteristicByUuidCnf readCharacteristicByUuidCnf;
+ cbGATT_ReadLongCharacteristicCnf readLongCharacteristicCnf;
+ cbGATT_ReadMultipleCharacteristicCnf readMultipleCharacteristicCnf;
+ cbGATT_WriteCharacteristicCnf writeCharacteristicCnf;
+ cbGATT_WriteCharacteristicNoRspCnf writeCharacteristicNoRspCnf;
+ cbGATT_WriteCharacteristicConfigCnf writeCharacteristicConfigCnf;
+ cbGATT_WriteLongCharacteristicCnf writeLongCharacteristicCnf;
+} cbGATT_ClientCallBack;
+
+
+typedef struct
+{
+ cbGATT_CharacteristicValueIndication characteristicValueIndication;
+ cbGATT_CharacteristicValueNotification characteristicValueNotification;
+} cbGATT_ClientNotIndCallBack;
+
+/*=============================================================================
+ * EXPORTED FUNCTIONS
+ *=============================================================================
+ */
+
+/**
+ * Register a GATT client. This must be done before any GATT client
+ * functionality can be used.
+ * @param pCallBack Callback structure that should be provided by the app. Use
+ * NULL as pointer for callbacks that are not used.
+ * @param pAppHandle Pointer where to put created app handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_registerClient(
+ const cbGATT_ClientCallBack* pCallBack,
+ cb_uint8* pAppHandle);
+
+/**
+ * Register a notification/indication handler for an attribute handle
+ * This is used when the application needs a specific handler for an
+ * attribute. This can be done first after connection setup.
+ * @param pCallBack Callback structure that should be provided by the app. Use
+ * NULL as pointer for callbacks that are not used.
+ * @param appHandle App handle
+ * @param attrHandle Attribute handle for the notification/indication to
+ * subscribe on.
+ * @param connHandle Connection handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_registerNotIndHandler(
+ const cbGATT_ClientNotIndCallBack* pCallBack,
+ cb_uint8 appHandle,
+ cb_uint16 attrHandle,
+ TConnHandle connHandle);
+
+/**
+ * De-register a notification/indication handler. This is used when the
+ * app does not want to subscribe to the attribute handle any longer e.g.
+ * the client characteristic configuration has been disabled. The handler is
+ * automatically de-registered on disconnection.
+ * @param pCallBack Registered callback.
+ * @param appHandle App handle
+ * @param attrHandle Attribute handle for the notification/indication to
+ * subscribe on.
+ * @param connHandle Connection handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_deregisterNotIndHandler(
+ const cbGATT_ClientNotIndCallBack* pCallBack,
+ cb_uint8 appHandle,
+ cb_uint16 attrHandle,
+ TConnHandle connHandle);
+
+/**
+ * Register a default notification/indication handler. This is used when the
+ * app wants to subscribe to all attribute handles notifications/indications
+ * for all connections. This can only be used by one app at a time.
+ * @param pCallBack Callback structure that should be provided by the app. Use
+ * NULL as pointer for callbacks that are not used.
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_registerDefaultNotIndHandler(
+ const cbGATT_ClientNotIndCallBack* pCallBack);
+
+/**
+ * Discover all primary services. Results will be provided in the
+ * cbGATT_DiscoverAllPrimaryServicesCnf callback.
+ * @param connHandle Connection handle
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverAllPrimaryServices(
+ TConnHandle connHandle,
+ cb_uint8 appHandle);
+
+/**
+ * Discover all secondary services. Results will be provided in the
+ * cbGATT_DiscoverAllSecondaryServicesCnf callback.
+ * @param connHandle Connection handle
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverAllSecondaryServices(
+ TConnHandle connHandle,
+ cb_uint8 appHandle);
+
+/**
+ * Discover all primary services by UUID. This will filter out all results
+ * based on the UUID. Results will be provided in the
+ * cbGATT_DiscoverPrimaryServiceByUuidCnf callback.
+ * @param connHandle Connection handle
+ * @param pUuid Pointer to the 16 or 128 bits UUID to search for
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverPrimaryServiceByUuid(
+ TConnHandle connHandle,
+ cbGATT_Uuid* pUuid,
+ cb_uint8 appHandle);
+
+/**
+ * Discover all characteristics of a service. The handles can be
+ * retrieved by doing a discover primary/secondary services request. Results
+ * will be provided in the cbGATT_DiscoverAllCharacteristicsOfServiceCnf
+ * callback.
+ * @param connHandle Connection handle
+ * @param startHandle Start handle of the service
+ * @param endHandle End handle of the service
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverAllCharacteristicsOfService(
+ TConnHandle connHandle,
+ cb_uint16 startHandle,
+ cb_uint16 endHandle,
+ cb_uint8 appHandle);
+
+/**
+ * Find included services of a given service. The handles can be
+ * retrieved by doing a discover primary/secondary services request. Results
+ * will be provided in the cbGATT_FindIncludedServicesCnf callback.
+ * @param connHandle Connection handle
+ * @param startHandle Start handle of the service
+ * @param endHandle End handle of the service
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_findIncludedServices(
+ TConnHandle connHandle,
+ cb_uint16 startHandle,
+ cb_uint16 endHandle,
+ cb_uint8 appHandle);
+
+/**
+ * Discover all descriptors of a characteristic. The handles can be
+ * retrieved by doing a cbGATT_discoverAllCharacteristicsOfService. Results
+ * will be provided in the cbGATT_DiscoverAllCharacteristicDescriptorsCnf.
+ * callback. If the app wants to do a discover characteristics by UUID this
+ * function can be used and in the callback filter on UUID.
+ * @param connHandle Connection handle
+ * @param valueHandle Handle of the characteristic value
+ * @param serviceEndHandle End handle of the service which the characteristic
+ * belongs to.
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverAllCharacteristicDescriptors(
+ TConnHandle connHandle,
+ cb_uint16 valueHandle,
+ cb_uint16 serviceEndHandle,
+ cb_uint8 appHandle);
+
+/**
+ * Read characteristic/descriptor value. The handles can be retrieved by
+ * doing a cbGATT_discoverAllCharacteristicsOfService or
+ * cbGATT_discoverAllCharacteristicDescriptors. Results will be provided in
+ * the cbGATT_ReadCharacteristicCnf callback.
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param offset Offset where to start read from
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_readCharacteristic(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint16 offset,
+ cb_uint8 appHandle);
+
+/**
+ * Read characteristic/descriptor value by UUID. The app can search the whole
+ * database by using cbGATT_MIN_ATTR_HANDLE and cbGATT_MAX_ATTR_HANDLE.
+ * Results will be provided in the cbGATT_ReadCharacteristicByUuidCnf
+ * callback.
+ * @param connHandle Connection handle
+ * @param startHandle Handle, where to start looking for the UUID
+ * @param endHandle Handle, where to stop looking for the UUID
+ * @param pUuid Pointer to the 16 or 128 bits UUID
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_readCharacteristicByUuid(
+ TConnHandle connHandle,
+ cb_uint16 startHandle,
+ cb_uint16 endHandle,
+ cbGATT_Uuid* pUuid,
+ cb_uint8 appHandle);
+
+// Used for reading long characteristics value or descriptor
+// TODO is this function necessary, because cbGATT_readCharacteristic will read long if needed
+cb_int32 cbGATT_readLongCharacteristic(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint8* pDest,
+ cb_uint8 appHandle);
+
+
+/**
+ * Read multiple characteristics in a single read. The app must know the
+ * length of each data element in the returned list. Therefore only the last
+ * data element may have a variable length.
+ * Results will be provided in the cbGATT_ReadMultipleCharacteristicCnf
+ * callback.
+ * @param connHandle Connection handle
+ * @param pAttrHandleList Pointer to a list of attribute handles
+ * @param nbrOfHandles Number of attribute handles in pAttrHandleList
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_readMultipleCharacteristic(
+ TConnHandle connHandle,
+ cb_uint16* pAttrHandleList,
+ cb_uint16 nbrOfHandles,
+ cb_uint8 appHandle);
+
+/**
+ * Write characteristic/descriptor and wait for response from remote side.
+ * Results will be provided in the cbGATT_WriteCharacteristicCnf
+ * callback.
+ * @param connHandle Connection handle
+ * @param attrHandle Attribute handle of the value
+ * @param pData Pointer to the data byte sequence
+ * @param length Number of bytes to write
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_writeCharacteristic(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint8* pData,
+ cb_uint16 length,
+ cb_uint8 appHandle);
+
+/**
+ * Write client/server characteristic/descriptor configuration.
+ * cbGATT_writeCharacteristic can also be used instead of this function.
+ * Results will be provided in the cbGATT_WriteCharacteristicConfigCnf
+ * callback.
+ * @param connHandle Connection handle
+ * @param attrHandle Attribute handle of the value
+ * @param config Configuration i.e. cbGATT_CLIENT_CFG_* or
+ * cbGATT_SERVER_CFG_*
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_writeCharacteristicConfig(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint16 config,
+ cb_uint8 appHandle);
+
+/**
+ * Write characteristic/descriptor with no response from remote side.
+ * Results will be provided in the cbGATT_WriteCharacteristicNoRspCnf
+ * callback.
+ * @param connHandle Connection handle
+ * @param attrHandle Attribute handle of the value
+ * @param pData Pointer to the data byte sequence
+ * @param length Number of bytes to write
+ * @param pSignature Pointer to encrypted signature which is checked by the
+ * server. If the check fails the write is discarded.
+ * The devices must be bonded and CSRK exchanged. Use NULL
+ * when no signature is being used.
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_writeCharacteristicNoRsp(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint8* pData,
+ cb_uint16 length,
+ cb_uint8* pSignature,
+ cb_uint8 appHandle);
+
+/**
+ * Write long characteristic/descriptor and wait for response from remote
+ * side. Results will be provided in the cbGATT_WriteLongCharacteristicCnf
+ * callback.
+ * @param connHandle Connection handle
+ * @param attrHandle Attribute handle of the value
+ * @param pData Pointer to the data byte sequence
+ * @param length Number of bytes to write
+ * @param reliable TRUE = the data will be sent back to client and
+ * checked by GATT.
+ * FALSE = no check of data
+ * @param flag Flag which is used when sending several packets
+ * or when data is canceled. If sending several packets all
+ * but the last packet should set the flag to more data.
+ * The last data packet should set the flag to final.
+ * @param offset Offset of the data to write. Is used when several packets
+ * need to be sent to write a complete data value.
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_writeLongCharacteristic(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint8* pData,
+ cb_uint16 length,
+ cb_boolean reliable,
+ cbGATT_WriteLongCharFlag flag,
+ cb_uint16 offset,
+ cb_uint8 appHandle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,329 @@
+/*------------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+*------------------------------------------------------------------------------
+* Component: GATT
+* File : cb_gatt_server.h
+*
+* Description:
+* GATT server functionality
+*------------------------------------------------------------------------------
+*/
+
+/**
+ * @file cb_gatt_server.h
+ *
+ * @brief GATT server functionality
+ */
+
+#ifndef _CB_GATT_SERVER_H_
+#define _CB_GATT_SERVER_H_
+
+#include "bt_types.h"
+#include "cb_gatt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*==============================================================================
+ * CONSTANTS
+ *==============================================================================
+ */
+
+#define cbGATT_RD_SEC_NONE 0x01
+#define cbGATT_RD_SEC_UNAUTH 0x02
+#define cbGATT_RD_SEC_AUTH 0x04
+#define cbGATT_WR_SEC_NONE 0x10
+#define cbGATT_WR_SEC_UNAUTH 0x20
+#define cbGATT_WR_SEC_AUTH 0x40
+
+#define cbGATT_NBR_OF_ATTR_OF_SERVICE(x) (sizeof(x)/sizeof(cbGATT_Attribute))
+
+#define cbGATT_APP_START_SERVICE_HANDLE 1024
+
+/*==============================================================================
+ * TYPES
+ *==============================================================================
+ */
+
+/**
+ * Attribute database entry
+ * @param pUuid 16 or 128-bits UUID
+ * @param uuidFormat Format of the pUuid
+ * @param properties Properties see cbGATT_PROP_* in cb_gatt.h
+ * @param security Read/write security properties for this characteristic see cbGATT_WR_SEC_* and cbGATT_RD_SEC_*
+ * @param pvValue1 Depends on pUuid, see below
+ * cbGATT_CHAR_EXT_PROP - properties as cb_uint32
+ * cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device reads the client config, cbGATT_ServerReadClientConfig
+ * cbGATT_SERVER_CHAR_CONFIG - callback that is called when remote device reads the server config, cbGATT_ServerReadServerConfig
+ * cbGATT_CHAR_FORMAT - Pointer to cbGATT_CharFormat
+ * cbGATT_CHAR_USER_DESC and all other CHARACTERISTICS value - cbGATT_ServerReadAttr callback
+ * cbGATT_INCLUDE_DECL - Pointer to inlcuded service cbGATT_Attribute
+ * @param pvValue2 Depends on pUuid, see below
+ * cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device writes the client config cbGATT_ServerWriteClientConfig
+ * cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device writes the client config cbGATT_ServerWriteClientConfig
+ * cbGATT_SERVER_CHAR_CONFIG - callback that is called when remote device writes the server config cbGATT_ServerWriteServerConfig
+ * cbGATT_CHAR_USER_DESC and all other CHARACTERISTICS value - cbGATT_ServerWriteAttr callback
+ * @param pAttrHandle Pointer where to write the attribute handle in case it's needed by the app.
+ * If not needed, pass NULL. Will be written after the service has been added.
+ */
+typedef struct
+{
+ void* pUuid;
+ cbGATT_UuidFormat uuidFormat;
+ cb_uint8 properties;
+ cb_uint8 security;
+ void* pvValue1;
+ void* pvValue2;
+ cb_uint16* pAttrHandle;
+} cbGATT_Attribute;
+
+/**
+ * Callback is called when the indication has been confirmed.
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param errorCode cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_CharacteristicValueIndicationCnf)(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cbGATT_ErrorCode errorCode);
+
+/**
+ * Callback is called when the notification has been sent.
+ * @param connHandle Connection handle
+ * @param errorCode cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_CharacteristicValueNotificationCnf)(
+ TConnHandle connHandle,
+ cbGATT_ErrorCode errorCode);
+
+/**
+ * Callback is called when the GATT client has commited a write long
+ * @param connHandle Connection handle
+ * @param commit TRUE = commit, FALSE = cancel
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_CharacteristicWriteLongCommitEvt)(
+ TConnHandle connHandle,
+ cb_boolean commit);
+
+// Callbacks to use in server table
+
+/**
+ * Callback is called when the client is reading an attribute
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param pAttr Pointer to attribute record
+ * @param pAttrValue Pointer where to put the read data
+ * @param pLength Pointer where to put the read length.
+ * @param maxLength Max number of bytes that is allowed for pAttrValue
+ * @param offset The offset of the read data
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerReadAttr)(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cbGATT_Attribute* pAttr,
+ cb_uint8* pAttrValue,
+ cb_uint16* pLength,
+ cb_uint16 maxLength,
+ cb_uint16 offset);
+
+/**
+ * Callback is called when the client is writing an attribute.
+ * If the application wants to send the response later it can
+ * return the cbGATT_ERROR_CODE_DELAYED_RSP error code and call cbGATT_writeRsp
+ * when ready.
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param pAttr Pointer to attribute record
+ * @param pAttrValue Pointer where to get the data
+ * @param length The length.
+ * @param writeMethod Which write method the client is using.
+ * This depends on the properties in the attribute table.
+ * @param offset The offset of the written data
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerWriteAttr)(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cbGATT_Attribute* pAttr,
+ cb_uint8* pAttrValue,
+ cb_uint16 length,
+ cbGATT_WriteMethod writeMethod,
+ cb_uint16 offset);
+
+/**
+ * Callback is called when the client is reading the client config
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param pConfig Pointer where to write the config
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerReadClientConfig)(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint16* pConfig);
+
+/**
+ * Callback is called when the client is writing the client config
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param config The config to be stored
+ * @param writeMethod Which write method the client is using.
+ * This depends on the properties in the attribute table.
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerWriteClientConfig)(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint16 config,
+ cbGATT_WriteMethod writeMethod);
+
+/**
+ * Callback is called when the client is reading the server config
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param pConfig Pointer where to write the config
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerReadServerConfig)(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint16* pConfig);
+
+/**
+ * Callback is called when the client is writing the server config
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param config The config to be stored
+ * @param writeMethod Which write method the client is using.
+ * This depends on the properties in the attribute table.
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerWriteServerConfig)(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint16 config,
+ cbGATT_WriteMethod writeMethod);
+
+typedef struct
+{
+ cbGATT_ConnComplEvt connComplEvt;
+ cbGATT_DisconnectEvt disconnectEvt;
+ cbGATT_CharacteristicValueIndicationCnf characteristicValueIndicationCnf;
+ cbGATT_CharacteristicValueNotificationCnf characteristicValueNotificationCnf;
+ cbGATT_CharacteristicWriteLongCommitEvt characteristicWriteLongCommitEvt;
+} cbGATT_ServerCallBack;
+
+
+/*=============================================================================
+ * EXPORTED FUNCTIONS
+ *=============================================================================
+ */
+
+/**
+ * Register server callbacks
+ * @param pCallBack Server callback
+ * @param pAppHandle Where to store app handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_registerServer(
+ const cbGATT_ServerCallBack* pCallBack,
+ cb_uint8* pAppHandle);
+
+/**
+ * Deregister all server callbacks
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_deregisterAllServers(void);
+
+/**
+ * Send notification to GATT client. The characteristicValueNotificationCnf
+ * callback will be called when finished and a new notification can be sent.
+ * The client config notification must have been enabled by the GATT client
+ * before an notification can be sent.
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param pData Pointer to data to send
+ * @param length Length of pData
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_notification(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint8* pData,
+ cb_uint16 length,
+ cb_uint8 appHandle);
+
+/**
+ * Send indication to GATT client. The characteristicValueIndicationCnf
+ * callback will be called when finished and a new indication can be sent.
+ * The client config indication must have been enabled by the GATT client
+ * before an indication can be sent.
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param pData Pointer to data to send
+ * @param length Length of pData
+ * @param appHandle App handle
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_indication(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint8* pData,
+ cb_uint16 length,
+ cb_uint8 appHandle);
+
+/**
+ * Delay write respone to client, see cbGATT_ServerWriteAttr
+ * @param connHandle Connection handle
+ * @param attrHandle Handle of the attribute value
+ * @param errorCode Error code, use cbGATT_ERROR_CODE_OK if OK otherwise some cbGATT_ERROR_CODE_*
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_writeRsp(
+ TConnHandle connHandle,
+ cb_uint16 attrHandle,
+ cb_uint8 errorCode); // For delayed write responses
+
+/**
+ * Add service list to attribute database
+ * @param pAttrList Attribute list
+ * @param attrListSize Size of the attribute list
+ * @param startHandle Start handle. Note that startHandle for the application
+ * should start at lowest 1024, cbGATT_APP_START_SERVICE_HANDLE.
+ * 1-1023 is reserved for GATT/GAP and other u-blox services.
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_addService(
+ const cbGATT_Attribute* pAttrList,
+ cb_uint16 attrListSize,
+ cb_uint16 startHandle);
+
+/**
+ * NOTE: Only for tests
+ * Free all services. Use with care since this will also remove GATT and GAP services.
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_freeServices(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,104 @@
+/*
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : GATT
+ * File : cb_gatt_utils.h
+ *
+ * Description : Helper functions for GATT
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_gatt_utils.h
+ *
+ * @brief Helper functions for GATT
+ */
+
+#ifndef _CB_GATT_UTILS_H_
+#define _CB_GATT_UTILS_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+#include "cb_gatt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*=============================================================================
+ * FUNCTIONS
+ *=============================================================================
+ */
+
+/**
+ * Returns a string representing the error code. NULL if the error code is
+ * not found.
+ * @param errorCode GATT error code
+ */
+cb_char* cbGATT_UTILS_getStringFromErrorCode(
+ cbGATT_ErrorCode errorCode);
+
+/**
+ * Returns a string representing the GATT/ATT properties for a characteristic.
+ * @param properties Bitmap of properties see cbGATT_PROP_*
+ */
+cb_char* cbGATT_UTILS_getStringFromProperties(
+ cb_uint8 properties);
+
+/**
+ * Returns a string representing the UUID. NULL if the UUID is not
+ * found.
+ * @param pUuid Pointer to 128 or 16-bit UUID
+ */
+cb_char* cbGATT_UTILS_getStringFromUuid(
+ cbGATT_Uuid* pUuid);
+
+/**
+ * Returns a string representing the UUID as hex bytes.
+ * @param pUuid Pointer to 128 or 16-bit UUID
+ * @param resultStr Allocated buffer to put hex string in.
+ * Should fit 16*2+1 = 33 bytes
+ */
+cb_char* cbGATT_UTILS_getHexStringFromUuid(
+ cbGATT_Uuid* pUuid,
+ cb_char* resultStr);
+
+/**
+ * Returns a string representing the data as hex bytes.
+ * @param pData Pointer to data
+ * @param len Length of data
+ * @param resultStr Pointer to allocated buffer to put hex string in.
+ * Should fit len*2+1 bytes
+ */
+cb_char* cbGATT_UTILS_dataToHex(
+ cb_uint8* pData,
+ cb_uint16 len,
+ cb_char* resultStr);
+
+/**
+ * Reverse bytes
+ * @param src Pointer to data to reverse bytes for
+ * @param nbrOfBytes Length of src
+ */
+void cbGATT_UTILS_reverseBytes(
+ cb_uint8* src,
+ cb_uint16 nbrOfBytes);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,222 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component: CB HW
+ * File : cb_hw.h
+ *
+ * Description: Setup of hardware.
+ * TODO clean up this interface..
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_HW_H_
+#define _CB_HW_H_
+
+#include "cb_comdefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbHW_SECUREBOOT_SIGN_LENGTH 344
+#define cbHW_FW_NAME_MAX_LENGTH 22
+#define cbHW_FW_NAME_MIN_LENGTH 1
+#define cbHW_FW_FLAG_MAX_LENGTH 8 // 8 bit fields
+#define cbHW_FW_FLAG_MIN_LENGTH 1
+#define cbHW_UNIQUE_ID_SIZE 12
+
+typedef enum {
+ cbHW_PCB_VERSION_UNKNOWN,
+ cbHW_PCB_VERSION_1,
+ cbHW_PCB_VERSION_2,
+ cbHW_PCB_VERSION_3,
+ cbHW_PCB_VERSION_4,
+ cbHW_PCB_VERSION_5
+} cbHW_PCBVersion;
+
+typedef enum {
+ cbHW_RESET_REASON_UNKNOWN = 0,
+ cbHW_RESET_REASON_FW_UPDATE,
+ cbHW_RESET_REASON_PRODUCTION_MODE
+} cbHW_ResetReason;
+
+typedef enum {
+ cbHW_FLOW_CONTROL_DISABLED = 0,
+ cbHW_FLOW_CONTROL_ENABLED
+} cbHW_FlowControl;
+
+typedef enum {
+ cbHW_IRQ_HIGH = 2U,
+ cbHW_IRQ_MEDIUM = 3U,
+ cbHW_IRQ_DEFAULT = 5U,
+ cbHW_IRQ_LOW = 12U
+} cbHW_PRIO_LVL;
+
+typedef enum {
+ cbHW_SYSTICK_DISABLED,
+ cbHW_SYSTICK_LOW_FREQ,
+ cbHW_SYSTICK_DEFAULT,
+} cbHW_SysTickMode;
+
+typedef enum {
+ cbHW_HASH_MD5
+} cbHW_HashType;
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+typedef void (*cbHW_StopModeStatusEvt)(cb_boolean enable);
+typedef void (*cbHW_SysTickCb)(void);
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+void cbHW_init(void);
+void cbHW_registerStopModeStatusEvt(cbHW_StopModeStatusEvt evt);
+void cbHW_disableIrq(void);
+void cbHW_enableIrq(void);
+void cbHW_disableAllIrq(void); // Should not be used unless extremely critical
+void cbHW_enableAllIrq(void);
+void cbHW_enterSleepMode(void);
+void cbHW_enterStopMode(void);
+void cbHW_setWakeupEvent(void);
+void cbHW_resetWakeupEvent(void);
+void cbHW_setSysTickMode(cbHW_SysTickMode sysTickMode);
+
+/**
+ * Wait for specified amount of microseconds. May be interrupt dependent.
+ * @note Granularity may vary between systems. Will be at least systick based.
+ * The system may go to sleep during the delay.
+ *
+ * @param us Time to delay in microseconds.
+ */
+void cbHW_delay(cb_uint32 us);
+
+/**
+* Puts the chip in NVIC soft reset
+* @note: this does not reset any watchdog timer already enabled
+*/
+void cbHW_reset(void);
+
+/**
+* Wait for specified amount of microseconds using a software loop.
+* @note Granularity may vary between systems.
+* The system will not go to sleep during the delay.
+*
+* @param us Time to delay in microseconds.
+*/
+void cbHW_softDelay(cb_uint32 us);
+cb_boolean cbHW_sysFreqIsSupported(cb_uint32 sysFreq);
+void cbHW_setSysFreq(cb_uint32 sysFreq);
+cb_uint32 cbHW_getSysFreq(void);
+void cbHW_writeBackupRegister(cb_uint32 registerId, cb_uint32 value);
+cb_uint32 cbHW_readBackupRegister(cb_int32 registerId);
+void cbHW_getHWId(cb_uint8 uid[cbHW_UNIQUE_ID_SIZE]);
+cbHW_PCBVersion cbHW_getPCBVersion(void);
+
+/**
+* Register a system tick callback.
+* The system tick will be generated once evert millisecond.
+*
+* @param cb Callback function for the system tick timer.
+*/
+void cbHW_registerSysTickISRCallback(cbHW_SysTickCb cb);
+
+/**
+* Get the current tick frequency for the @ref cbHW_getTicks tick counter.
+* @note The frequency may be altered with different system clocks and power modes.
+*
+* @return The current tick frequency.
+*/
+cb_uint32 cbHW_getTickFrequency(void);
+
+/**
+* Get the current value of the tick counter.
+* Time base in @ref cbHW_getTickFrequency.
+* @note The value may wrap.
+*
+* @return The current tick counter.
+*/
+cb_uint32 cbHW_getTicks(void);
+
+/**
+* Enter forced boot mode. The bootloader will start in x-modem
+* mode and emit CCCC.. to notify that it is ready to receive
+* a new fw.
+* This function will return and boot mode will be entered
+* after a device specific timeout.
+* @param address x-modem file download start address
+* @param baudrate x-modem download buadrate
+* @return None
+*/
+void cbHW_forceBoot(cb_uint32 address, cb_uint32 baudrate);
+
+/**
+* Enter forced boot mode. The bootloader will start in x-modem
+* mode and emit CCCC.. to notify that it is ready to receive
+* a new fw.
+* This function will return and boot mode will be entered
+* after a device specific timeout.
+* @param address x-modem file download start address
+* @param baudrate x-modem download buadrate
+* @param fwId firmware id
+* @param fwSize firmware file size
+* @param fwSignature firmware signature
+* @param fwName firmware name
+* @param fwFlags firmware flags
+* @return None
+*/
+void cbHW_forceBootSecure(
+ cb_uint32 address,
+ cb_uint32 baudrate,
+ cb_uint32 fwId,
+ cb_uint32 fwSize,
+ cb_char* fwSignature,
+ cb_char* fwName,
+ cb_char* fwFlags);
+
+/**
+* Cancel entry into boot mode. The user canceled entry
+* into forced boot mode.
+* This function will clean up the RTC memory that was
+* configured for a forced boot operation. Use this function
+* for both cbHW_forceBootSecure and cbHW_forceBoot
+* @return None
+*/
+void cbHW_cancelforceBoot(void);
+
+void cbHW_enterProductionMode(cbHW_FlowControl flowControl);
+cbHW_ResetReason cbHW_resetReason(void);
+cbHW_FlowControl cbHW_flowControl(void);
+
+/**
+* Calculates a hash over a dataset.
+* @param type: type of hashing, MD5 for now
+* @param pInData: pointer to Data over which the hashing should be done
+* @param indataSize: size of data buffer.
+* @param pOutData: pointer to result data
+* @return None
+*/
+void cbHW_hash(cbHW_HashType type, const cb_uint8* pInData,cb_uint32 indataSize, cb_uint8* pOutData);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,145 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component: Main for WiFi-driver and BT stack
+ * File : cb_main.h
+ *
+ * Description :
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_MAIN_H_
+#define _CB_MAIN_H_
+
+#include "bt_types.h"
+#include "cb_bt_man.h"
+#include "cb_wlan.h"
+#include "mbed_events.h"
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbMAIN_TARGET_INVALID_ID -1
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+typedef struct
+{
+ TBdAddr address; /** Bluetooth address that shall be assigned to controller. Pass invalidBdAddress to use controller default address*/
+ cbBM_LeRole leRole; /** Bluetooth low energy role */
+ cb_int8 maxOutputPower; /** Maximum output power. */
+ cb_uint32 maxLinkKeysClassic; /** Max number of CLASSIC link keys */
+ cb_uint32 maxLinkKeysLe; /** Max number of link keys BLE*/
+} cbMAIN_BtInitParams;
+
+typedef void(*cbMAIN_ErrorHandler)(
+ cb_int32 errorCode,
+ const cb_char* filename,
+ cb_uint32 line);
+
+typedef struct
+{
+ cbWLAN_MACAddress mac; /**< MAC of WLAN interface, set to all zeros if hardware programmed address should be used. */
+ cbWM_TxPowerSettings txPowerSettings; /**< Transmission power settings. */
+} cbMAIN_WlanStartParams;
+
+/*---------------------------------------------------------------------------
+ * Callback to indicate that initialization of BT stack is completed.
+ *-------------------------------------------------------------------------*/
+typedef void(*cbMAIN_initBtComplete)(void);
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Initialize OS, timers, GPIO's, heap and OTP.
+ *
+ * @return void
+ */
+extern void cbMAIN_initOS(void);
+
+/**
+ * Start Bluetooth HW.
+ *
+ * @param pInitParameters Initial configuration parameters. These parameters can
+ * not be changed once Bluetooth has been started.
+ * @param callback Will be invoked when initialisation is done.
+ * @return void
+ */
+extern void cbMAIN_initBt(cbMAIN_BtInitParams *pInitParameters, cbMAIN_initBtComplete callback);
+
+/**
+ * Initialize WLAN component.
+ * @return Port specific TARGET identifier
+ */
+extern cb_int32 cbMAIN_initWlan(void);
+
+/**
+ * Start WLAN component.
+ * Create WLAN driver instance, bind it to targetId and start the driver.
+ *
+ * @param targetId Port specific TARGET identifier.
+ * @param params Start parameters passed to WLAN driver instance.
+ * @return cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR.
+ */
+extern cb_int32 cbMAIN_startWlan(cb_int32 targetId, cbMAIN_WlanStartParams *params);
+
+/**
+ * Register error handler function.
+ *
+ * @param errHandler Function to be invoked in case of error.
+ * @return void
+ */
+extern void cbMAIN_registerErrorHandler(cbMAIN_ErrorHandler errHandler);
+
+/**
+ * Start driver OS. This must be called after all cbMAIN_initOS/cbMAIN_initBt/cbMAIN_initWlan
+ * to start the driver thread.
+ *
+ * @return void
+ */
+extern void cbMAIN_startOS(void);
+
+/**
+ * Get event queue. Used for running a function in the same thread context as the driver.
+ * Can not be called before cbMAIN_initOS/cbMAIN_initBt/cbMAIN_initWlan.
+ * Use cbMAIN_dispatchEventQueue to trigger the driver to call the queued up functions.
+ * @return EventQueue Pointer to the event queue where function calls can be enqueued.
+ */
+extern EventQueue* cbMAIN_getEventQueue(void);
+
+/**
+ * Lock driver from usage. This must be used if a C API function is used outside of the driver thread context.
+ * The driver should only be locked for as small time as possible.
+ * @return void
+ */
+extern void cbMAIN_driverLock(void);
+
+/**
+ * Unlock driver. used when the C API function has finished executing to release the driver for others to use.
+ *
+ * @return void
+ */
+extern void cbMAIN_driverUnlock(void);
+
+/**
+ * Dispatch event queue. Should be called to trigger calls that have been queued up in the driver context
+ *
+ * @return void
+ */
+extern void cbMAIN_dispatchEventQueue(void);
+
+#endif /*_CB_MAIN_H_*/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,72 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : OTP
+ * File : cb_otp.h
+ *
+ * Description : Support for One Time Programmable memory intended for
+ * storing production parameters such as mac addresses, trim
+ * values and product configuration. Writing to OTP memory shall
+ * only be done in a production environment.
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_otp.h
+ * @ingroup platform
+ */
+
+#ifndef _CB_OTP_H_
+#define _CB_OTP_H_
+
+#include "cb_comdefs.h"
+#include "cb_status.h"
+
+#define cbOTP_MAX_SIZE (30)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+ cbOTP_MAC_BLUETOOTH = 1,
+ cbOTP_MAC_WLAN,
+ cbOTP_MAC_ETHERNET,
+ cbOTP_MAC_FEATURE_INFO,
+ cbOTP_MAC_DEBUG_UNIT,
+ cbOTP_SERIAL_NUMBER,
+ cbOTP_TYPE_CODE,
+ cbOTP_SIGNATURE,
+ cbOTP_MAC_WLAN_AP,
+ cbOTP_UUID,
+ cbOTP_RF_FREQ_CALIBRATION,
+ cbOTP_RESERVED_UNUSED = 255
+} cbOTP_Id;
+
+
+/**
+ * Read a OTP parameter
+ * @param id The id of the parameter to write
+ * @param len The length of the parameter to write
+ * @param buf Pointer to data to be written
+ * @returns The read length of the id is returned. If the read fails 0 is returned
+ */
+cb_uint32 cbOTP_read(cbOTP_Id id, cb_uint32 len, cb_uint8 *buf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,130 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Wireless LAN driver
+ * File : cb_types.h
+ *
+ * Description : Common definitions for a GCC compatible compiler.
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_types.h Defines type required for the entire driver.
+ * The defines in this file will have to be adapted for the platform.
+ * @ingroup platform
+ */
+
+#ifndef _CB_PLATFORM_BASIC_TYPES_H_
+#define _CB_PLATFORM_BASIC_TYPES_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+/*===========================================================================
+ * COMMON SYSTEM DEFINES
+ *=========================================================================*/
+
+typedef int8_t cb_int8;
+typedef int16_t cb_int16;
+typedef int32_t cb_int32;
+typedef int64_t cb_int64;
+
+typedef uint8_t cb_uint8;
+typedef uint16_t cb_uint16;
+typedef uint32_t cb_uint32;
+typedef uint64_t cb_uint64;
+
+typedef bool cb_boolean;
+typedef char cb_char;
+typedef int cb_int;
+
+/**
+ * Used when declaring an empty array that does not take up space in a struct.
+ * Example: struct { cb_uint8 payload[cb_EMPTY_ARRAY]; }
+ * In some compilers this is empty i.e. payload[]. While in some it requires a zero.
+ * I.e. payload[0];
+ * Use this define to get it working for your system.
+ */
+#define cb_EMPTY_ARRAY (0)
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/**
+ * Used in function definitions to declare an input parameter unused to avoid warnings.
+ */
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define cb_UNUSED(x) UNUSED_ ## x __attribute__((unused))
+#else
+#define cb_UNUSED(x) UNUSED_ ## x
+#endif
+
+
+/**
+ * Define cb_ASSERT to the wanted assert handler.
+ */
+/*
+#define cb_ASSERT(exp) do { if (!(exp)) { \
+ W_PRINT("ASSERT %s:%d\n", __FILE__, __LINE__); \
+ while(1); \
+ } } while(0)
+*/
+#include "cb_assert.h"
+
+
+/**@{*/
+/**
+ * Packed struct defines.
+ * - cb_PACKED_STRUCT_ATTR_PRE is used before the typedef'ed struct declaration.
+ * - cb_PACKED_STRUCT_ATTR_INLINE_PRE is after the typedef but before the struct declaration.
+ * - cb_PACKED_STRUCT_ATTR_INLINE_POST is used after the struct declaration but before the typedef'ed name.
+ * - cb_PACKED_STRUCT_ATTR_POST is used after the entire struct declaration.
+ *
+ * example:
+ * cb_PACKED_STRUCT_ATTR_PRE
+ * typedef cb_PACKED_STRUCT_ATTR_INLINE_PRE struct myPackedStruct {
+ * int a;
+ * int b;
+ * } cb_PACKED_STRUCT_ATTR_INLINE_POST myPackedStruct
+ * cb_PACKED_STRUCT_ATTR_POST
+ *
+ */
+
+#define cb_PACKED_STRUCT_ATTR_PRE
+
+#if defined(__ICCARM__)
+#define cb_PACKED_STRUCT_ATTR_INLINE_PRE __packed
+#else
+#define cb_PACKED_STRUCT_ATTR_INLINE_PRE
+#endif
+
+#if defined(__ICCARM__)
+#define cb_PACKED_STRUCT_ATTR_INLINE_POST __packed
+#else
+#define cb_PACKED_STRUCT_ATTR_INLINE_POST __attribute__ ((__packed__))
+#endif
+
+
+#define cb_PACKED_STRUCT_ATTR_POST
+
+/**@}*/
+
+
+#endif /* _CB_PLATFORM_BASIC_TYPES_H_ */
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,36 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2016, u-blox Malmö, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Component : Wireless LAN driver + * File : cb_types.h + * + * Description : Common definitions for a GCC compatible compiler. + *-------------------------------------------------------------------------*/ + +/** + * @file cb_types.h Defines type required for the entire driver. + * The defines in this file will have to be adapted for the platform. + * @ingroup platform + */ + +#ifndef _CB_PORT_TYPES_H_ +#define _CB_PORT_TYPES_H_ + +#include <cb_comdefs.h> +#include "cb_assert.h" + + +#endif /* _CB_PORT_TYPES_H_ */ +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,47 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : RTSL
+ * File : cb_status.h
+ *
+ * Description : Common RTSL status codes
+ *-------------------------------------------------------------------------*/
+#ifndef _CB_STATUS_H_
+#define _CB_STATUS_H_
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+#define OK(status) (status == cbSTATUS_OK)
+#define BUSY(status) (status == cbSTATUS_BUSY)
+#define ERR(status) (status == cbSTATUS_ERROR)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+ typedef enum
+ {
+ cbSTATUS_OK,
+ cbSTATUS_ERROR,
+ cbSTATUS_BUSY,
+ cbSTATUS_RECEIVE_DATA_MODE,
+ cbSTATUS_TIMEOUT
+
+ } cbRTSL_Status;
+
+#endif /* _CB_STATUS_H_ */
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_target.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_target.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,178 @@
+/**
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : WLAN driver
+ * File : cb_target.h
+ *
+ * Description : OWL222a Wireless LAN module representation
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_target.h Handles the lowest layer of communication to the target
+ * before the SDIO stack.
+ *
+ * @note Create and Destroy methods are not specified here as these are not part
+ * of the interface used by the driver. The application should specify these
+ * as needed and simply supply the driver with a target handle.
+ *
+ * @ingroup port
+ */
+
+#ifndef _CB_TARGET_H_
+#define _CB_TARGET_H_
+
+#include "cb_wlan_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbTARGET_SDIO_BLOCK_SIZE (256)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+typedef struct cbTARGET_Handle cbTARGET_Handle;
+
+typedef struct cbTARGET_FunctionHandle cbTARGET_FunctionHandle;
+
+typedef void(*cbTARGET_ISRHandler)(void* hCallback);
+
+
+typedef enum {
+ cbTARGET_CBTYPE_IRQ,
+ cbTARGET_CBTYPE_START,
+ cbTARGET_CBTYPE_STOP,
+} cbTARGET_CallbackType;
+
+typedef enum cbTARGET_SDIO_Function {
+ cbTARGET_SDIO_FUNCTION_0,
+ cbTARGET_SDIO_FUNCTION_1,
+ cbTARGET_SDIO_FUNCTION_2,
+ cbTARGET_SDIO_FUNCTION_3,
+ cbTARGET_SDIO_FUNCTION_4,
+ cbTARGET_SDIO_FUNCTION_5,
+ cbTARGET_SDIO_FUNCTION_6,
+ cbTARGET_SDIO_FUNCTION_7,
+} cbTARGET_SDIO_Function;
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Map/resolve target handle from port specific identifier.
+ *
+ * @param targetId Port specific target identifier.
+ * @return Target handle matching target identifier.
+ */
+cbTARGET_Handle *cbTARGET_targetResolve(cb_int32 targetId);
+
+/**
+ * Perform a hardware reset of the TARGET.
+ */
+void cbTARGET_reset(cbTARGET_Handle *hTarget);
+
+/**
+ * Register a interrupt handler with the TARGET.
+ */
+void cbTARGET_registerISRHandler(cbTARGET_Handle *hTarget, cbTARGET_ISRHandler handler, void* hContext);
+
+
+/**
+ * Initiate a SDIO function and return a controlling object.
+ *
+ * @param hTarget Handle to target object.
+ * @param func SDIO function to initiate.
+ * @return Handle to a SDIO function object.
+ */
+cbTARGET_FunctionHandle* cbTARGET_initFunction(cbTARGET_Handle *hTarget, cbTARGET_SDIO_Function func);
+
+/**
+ * Write a buffer to the target using SDIO FIFO access.
+ *
+ * @param hFunction Handle to a SDIO target function object.
+ * @param address SDIO address.
+ * @param data Send buffer.
+ * @param dataSize Number of valid data bytes in transfer.
+ * @return True if successful, otherwise FALSE.
+ */
+cb_boolean cbTARGET_FIFOWrite(cbTARGET_FunctionHandle* hFunction, cb_uint32 address, cb_uint8* data, cb_uint32 dataSize);
+
+/**
+ * Read from the target into a buffer using SDIO FIFO access.
+ *
+ * @param hFunction Handle to a SDIO target function object.
+ * @param address SDIO address.
+ * @param data Receive buffer.
+ * @param dataSize Number of valid data bytes in transfer.
+ * @return TRUE if successful, otherwise FALSE.
+ */
+cb_boolean cbTARGET_FIFORead(cbTARGET_FunctionHandle* hFunction, cb_uint32 address, cb_uint8* data, cb_uint32 dataSize);
+
+/**
+ * Write a buffer to the target.
+ *
+ * @param hFunction Handle to a SDIO target function object.
+ * @param address SDIO address.
+ * @param data Send buffer.
+ * @param dataSize Number of valid data bytes in transfer.
+ * @return True if successful, otherwise FALSE.
+ */
+cb_boolean cbTARGET_write(cbTARGET_FunctionHandle* hFunction, cb_uint32 address, cb_uint8* data, cb_uint32 dataSize);
+
+/**
+ * Read from the target into a buffer.
+ *
+ * @param hFunction Handle to a SDIO target function object.
+ * @param address SDIO address.
+ * @param data Receive buffer.
+ * @param dataSize Number of valid data bytes in transfer.
+ * @return TRUE if successful, otherwise FALSE.
+ */
+cb_boolean cbTARGET_read(cbTARGET_FunctionHandle* hFunction, cb_uint32 address, cb_uint8* data, cb_uint32 dataSize);
+
+/**
+ * Write a single byte to the function 0 of the SDIO target.
+ *
+ * @param hTarget Handle to target object.
+ * @param address SDIO address.
+ * @param data Send buffer.
+ * @return True if successful, otherwise FALSE.
+ */
+cb_boolean cbTARGET_f0_writeByte(cbTARGET_Handle *hTarget, cb_uint32 address, cb_uint8 data);
+
+/**
+ * Read a single byte from the function 0 of the SDIO target.
+ *
+ * @param hTarget Handle to target object.
+ * @param address SDIO address.
+ * @param data Receive buffer.
+ * @return TRUE if successful, otherwise FALSE.
+ */
+cb_boolean cbTARGET_f0_readByte(cbTARGET_Handle *hTarget, cb_uint32 address, cb_uint8 *data);
+
+
+cb_uint16 cbTARGET_getBlockSize(cbTARGET_Handle *hTarget);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,287 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : RTSL
+ * File : cb_types.h
+ *
+ * Description : Common type definitions
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_types.h Defines type required for the entire driver.
+ * The defines in this file will have to be adapted for the platform.
+ * @ingroup platform
+ */
+
+#ifndef _CB_TYPES_H_
+#define _CB_TYPES_H_
+
+#include "cb_port_types.h"
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+/*===========================================================================
+ * COMMON SYSTEM DEFINES
+ *=========================================================================*/
+
+#ifndef FALSE
+# define FALSE (0)
+#endif
+#ifndef TRUE
+# define TRUE (!FALSE)
+#endif
+
+#ifndef NULL
+# define NULL ((void *) 0)
+#endif
+
+/**
+ * Returns the maximum value of the two parameters.
+ */
+#ifndef cb_MAX
+# define cb_MAX(x , y) (((x) > (y)) ? (x) : (y))
+#endif
+/**
+ * Returns the minimum value of the two parameters.
+ */
+#ifndef cb_MIN
+# define cb_MIN(x , y) (((x) < (y)) ? (x) : (y))
+#endif
+
+#ifndef ELEMENTS_OF
+# define ELEMENTS_OF(_array) (sizeof((_array)) / sizeof((_array)[0]))
+#endif
+
+#define cbWM_ARRAY_SIZE(a) ELEMENTS_OF(a)
+
+/**
+ * Used when declaring an empty array that does not take up space in a struct.
+ * Example: struct { cb_uint8 payload[cb_EMPTY_ARRAY]; }
+ * In some compilers this is empty i.e. payload[]. While in some it requires a zero.
+ * I.e. payload[0];
+ * Use this define to get it working for your system.
+ */
+#ifndef cb_EMPTY_ARRAY
+# define cb_EMPTY_ARRAY (0)
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+/**
+ * Used in function definitions to declare an inparameter unused to avoid warnings.
+ */
+#ifndef cb_UNUSED
+# define cb_UNUSED(x) x
+#endif
+
+#ifndef cb_ASSERT
+# error "No port definition for ASSERT!"
+#endif
+
+#ifndef cb_ARG_POINTER_CHECK
+# define cb_ARG_POINTER_CHECK(ptr) if((ptr) == NULL) {cb_ASSERT(FALSE); return;}
+#endif
+#ifndef cb_ARG_POINTER_CHECK_RETURN
+# define cb_ARG_POINTER_CHECK_RETURN(ptr, returnValue) if((ptr) == NULL) {cb_ASSERT(FALSE); return (returnValue);}
+#endif
+
+#ifndef cb_BIT_0
+#define cb_BIT_0 (1ul)
+#endif
+#ifndef cb_BIT_1
+#define cb_BIT_1 (1ul << 1)
+#endif
+#ifndef cb_BIT_2
+#define cb_BIT_2 (1ul << 2)
+#endif
+#ifndef cb_BIT_3
+#define cb_BIT_3 (1ul << 3)
+#endif
+#ifndef cb_BIT_4
+#define cb_BIT_4 (1ul << 4)
+#endif
+#ifndef cb_BIT_5
+#define cb_BIT_5 (1ul << 5)
+#endif
+#ifndef cb_BIT_6
+#define cb_BIT_6 (1ul << 6)
+#endif
+#ifndef cb_BIT_7
+#define cb_BIT_7 (1ul << 7)
+#endif
+#ifndef cb_BIT_8
+#define cb_BIT_8 (1ul << 8)
+#endif
+#ifndef cb_BIT_9
+#define cb_BIT_9 (1ul << 9)
+#endif
+#ifndef cb_BIT_10
+#define cb_BIT_10 (1ul << 10)
+#endif
+#ifndef cb_BIT_11
+#define cb_BIT_11 (1ul << 11)
+#endif
+#ifndef cb_BIT_12
+#define cb_BIT_12 (1ul << 12)
+#endif
+#ifndef cb_BIT_13
+#define cb_BIT_13 (1ul << 13)
+#endif
+#ifndef cb_BIT_14
+#define cb_BIT_14 (1ul << 14)
+#endif
+#ifndef cb_BIT_15
+#define cb_BIT_15 (1ul << 15)
+#endif
+#ifndef cb_BIT_16
+#define cb_BIT_16 (1ul << 16)
+#endif
+#ifndef cb_BIT_17
+#define cb_BIT_17 (1ul << 17)
+#endif
+#ifndef cb_BIT_18
+#define cb_BIT_18 (1ul << 18)
+#endif
+#ifndef cb_BIT_19
+#define cb_BIT_19 (1ul << 19)
+#endif
+#ifndef cb_BIT_20
+#define cb_BIT_20 (1ul << 20)
+#endif
+#ifndef cb_BIT_21
+#define cb_BIT_21 (1ul << 21)
+#endif
+#ifndef cb_BIT_22
+#define cb_BIT_22 (1ul << 22)
+#endif
+#ifndef cb_BIT_23
+#define cb_BIT_23 (1ul << 23)
+#endif
+#ifndef cb_BIT_24
+#define cb_BIT_24 (1ul << 24)
+#endif
+#ifndef cb_BIT_25
+#define cb_BIT_25 (1ul << 25)
+#endif
+#ifndef cb_BIT_26
+#define cb_BIT_26 (1ul << 26)
+#endif
+#ifndef cb_BIT_27
+#define cb_BIT_27 (1ul << 27)
+#endif
+#ifndef cb_BIT_28
+#define cb_BIT_28 (1ul << 28)
+#endif
+#ifndef cb_BIT_29
+#define cb_BIT_29 (1ul << 29)
+#endif
+#ifndef cb_BIT_30
+#define cb_BIT_30 (1ul << 30)
+#endif
+#ifndef cb_BIT_31
+#define cb_BIT_31 (1ul << 31)
+#endif
+
+#ifndef cb_UINT8_MAX
+#define cb_UINT8_MAX ((cb_uint8)0xff)
+#endif
+#ifndef cb_UINT16_MAX
+#define cb_UINT16_MAX ((cb_uint16)0xffff)
+#endif
+#ifndef cb_UINT32_MAX
+#define cb_UINT32_MAX ((cb_uint32)0xffffffff)
+#endif
+#ifndef cb_INT8_MAX
+#define cb_INT8_MAX ((cb_uint8)0x7f)
+#endif
+#ifndef cb_INT16_MAX
+#define cb_INT16_MAX ((cb_uint16)0x7fff)
+#endif
+#ifndef cb_INT32_MAX
+#define cb_INT32_MAX ((cb_uint32)0x7fffffff)
+#endif
+#ifndef cb_INT8_MIN
+#define cb_INT8_MIN ((cb_uint8)0x80)
+#endif
+#ifndef cb_INT16_MIN
+#define cb_INT16_MIN ((cb_uint16)0x8000)
+#endif
+#ifndef cb_INT32_MIN
+#define cb_INT32_MIN ((cb_uint32)0x80000000)
+#endif
+
+/**
+ * Clears (set to zero) a bit or bits in a variable.
+ * @param variable The variable.
+ * @param bit The bit or bits to clear
+ */
+#ifndef cb_CLEAR_BIT
+# define cb_CLEAR_BIT(variable,bit) ((variable) &= ~((bit)))
+#endif
+
+/**
+ * Gets a bit i.e. checks if it is set in a variable.
+ *
+ * Also works to see if any of several bits are set.
+ *
+ * @param variable The variable.
+ * @param bit The bit to check if it set.
+ * @return @ref TRUE if any of the bits are set, @ref FALSE otherwise.
+ */
+#ifndef cb_GET_BIT
+# define cb_GET_BIT(variable,bit) (((variable) & ((bit))) ? TRUE : FALSE)
+#endif
+
+/**
+ * Sets (set to 1) a bit or bits in a variable.
+ *
+ * @param variable The variable.
+ * @param bit The bit or bits to set in the variable.
+ */
+#ifndef cb_SET_BIT
+# define cb_SET_BIT(variable,bit) ((variable) |= (bit))
+#endif
+
+
+/*Packed struct defines*/
+#ifndef cb_PACKED_STRUCT_ATTR_INLINE_POST
+# define cb_PACKED_STRUCT_ATTR_INLINE_POST
+#endif
+#ifndef cb_PACKED_STRUCT_ATTR_INLINE_PRE
+# define cb_PACKED_STRUCT_ATTR_INLINE_PRE
+#endif
+#ifndef cb_PACKED_STRUCT_ATTR_PRE
+# define cb_PACKED_STRUCT_ATTR_PRE
+#endif
+#ifndef cb_PACKED_STRUCT_ATTR_POST
+# define cb_PACKED_STRUCT_ATTR_POST
+#endif
+
+#ifndef cb_PACKED_STRUCT_BEGIN
+# define cb_PACKED_STRUCT_BEGIN(name) \
+ cb_PACKED_STRUCT_ATTR_PRE \
+ typedef cb_PACKED_STRUCT_ATTR_INLINE_PRE struct name
+#endif
+
+#ifndef cb_PACKED_STRUCT_END
+# define cb_PACKED_STRUCT_END(name) \
+ cb_PACKED_STRUCT_ATTR_INLINE_POST name; \
+ cb_PACKED_STRUCT_ATTR_POST
+#endif
+
+#endif /* _CB_TYPES_H_ */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,71 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component: Watchdog
+ * File: cb_watchdog.h
+ *
+ * Description: Functionality for watchdog and reset.
+ *-------------------------------------------------------------------------*/
+#ifndef _CB_WATCHDOG_H_
+#define _CB_WATCHDOG_H_
+
+#include "cb_comdefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Put watchdog in a defined state.
+ */
+void cbWD_init(void);
+
+/**
+ * Resets the CPU.
+ */
+void cbWD_systemReset(void);
+
+/**
+ * Enables watchdog. Watchdog needs to be polled using cbWD_poll() with
+ * shorter intervals then specified by timeInMilliseconds.
+ *
+ * @param timeInMilliseconds Watchdog timeout in milliseconds.
+ */
+void cbWD_enable(cb_uint32 timeInMilliseconds);
+
+/**
+ * Poll the watchdog timer. This must be done with shorter intervalls
+ * than the time in cbWD_enable().
+ */
+void cbWD_poll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_WATCHDOG_H_ */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,588 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : WLAN
+ * File : cb_wlan.h
+ *
+ * Description : Main WLAN component, ties together WM, SUPPLICANT and
+ * TARGET to one streamlined API.
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_wlan.h The main WLAN component interface.
+ * All functions declared extern needs to be provided by another/upper layer.
+ * @ingroup wlan
+ */
+
+#ifndef _CB_WLAN_H_
+#define _CB_WLAN_H_
+
+#include "cb_types.h"
+#include "cb_wlan_types.h"
+#include "cb_cert_utils.h"
+#include "cb_status.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/**
+ * Max username length in @ref cbWLAN_EnterpriseConnectParameters
+ *
+ * @ingroup wlan
+ */
+#define cbWLAN_MAX_USERNAME_LENGTH 32
+
+/**
+ * Max password length in @ref cbWLAN_Util_PSKFromPWD and @ref cbWLAN_EnterpriseConnectParameters
+ *
+ * @ingroup wlan
+ */
+#define cbWLAN_MAX_PASSPHRASE_LENGTH 64
+
+/**
+ * PSK length in @ref cbWLAN_WPAPSKConnectParameters
+ *
+ * @ingroup wlan
+ */
+#define cbWLAN_PSK_LENGTH 32
+
+
+/**
+ * Max domain name length in @ref cbWLAN_EnterpriseConnectParameters
+ *
+ * @ingroup wlan
+ */
+#define cbWLAN_MAX_DOMAIN_LENGTH 64
+
+/**
+ * Size of the misc buffer in @ref cbWM_ChangeBSS and @ref cbWM_StartFT.
+ *
+ * @ingroup types
+ */
+#define MISC_BUFFER_SIZE 255
+
+#define cbWLAN_FTIE_SIZE 255
+#define cbWLAN_RSNIE_SIZE 44
+#define cbWLAN_MDIE_SIZE 5
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+/**
+ * Start parameters passed to WLAN driver.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_StartParameters {
+ cbWLAN_MACAddress mac; /**< MAC of WLAN interface, set to all zeros if hardware programmed address should be used. */
+ cbWM_ModuleType deviceType; /**< Specify current device type. */
+ union {
+ struct {
+ cbWM_TxPowerSettings txPowerSettings; /**< Transmission power settings. */
+ cb_uint8 numberOfAntennas; /**< Number of antennas use for wifi (MIMO supports 2x2). */
+ cb_uint8 primaryAntenna; /**< Primary antenna selection. */
+ } ODIN_W26X;
+ } deviceSpecific;
+} cbWLAN_StartParameters;
+
+/**
+ * Common connect parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_CommonConnectParameters {
+ cbWLAN_MACAddress bssid; /**< BSSID to connect to, set to all zero for any BSSID. */
+ cbWLAN_Ssid ssid; /**< SSID to connect to. */
+} cbWLAN_CommonConnectParameters;
+
+
+/**
+ * WEP specific connect parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_WEPConnectParameters {
+ cbWLAN_WEPKey keys[4]; /**< WEP keys. */
+ cb_uint32 txKey; /**< Active WEP transmission key index (0-3). */
+} cbWLAN_WEPConnectParameters;
+
+/**
+* WPA PSK parameters.
+*
+* @ingroup wlan
+*/
+typedef struct cbWLAN_WPAPSK {
+ cb_uint8 key[cbWLAN_PSK_LENGTH]; /**< WPA pre-shared key in binary form. */
+} cbWLAN_WPAPSK;
+
+/**
+ * WPA PSK specific connect parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_WPAPSKConnectParameters {
+ cbWLAN_WPAPSK psk; /**< WPA pre-shared key*/
+} cbWLAN_WPAPSKConnectParameters;
+
+#if defined(CB_FEATURE_802DOT11R)
+/**
+ * Associate information elements with FT elements.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_AssociateInformationElements{
+ cb_uint8 wpaIe[cbWLAN_RSNIE_SIZE];
+ cb_uint32 wpaIeLen;
+ cb_uint8 mdIe[cbWLAN_MDIE_SIZE];
+ cb_uint32 mdIeLen;
+ cb_uint8 ftIe[cbWLAN_FTIE_SIZE];
+ cb_uint32 ftIeLen;
+} cbWLAN_AssociateInformationElements;
+#endif
+
+#if defined(CB_FEATURE_802DOT11W)
+/**
+* 80211w PMF specific connect parameters.
+*
+* @ingroup wlan
+*/
+typedef struct cbWLAN_PMFApParameters {
+ cbWLAN_PMF pmf; /**< MFPR, MFPC RSN capabilties*/
+ cb_uint8 comeBackTime; /**< 1 - 10 sec */
+ cb_uint16 saQueryTimeOut; /**< 100 - 500 msec */
+} cbWLAN_PMFApParameters;
+#endif
+
+/**
+ * WPA Enterprise specific connect parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_EnterpriseConnectParameters {
+ cbWLAN_EnterpriseMode authMode; /**< Enterprise authentication mode. */
+ cb_uint8 username[cbWLAN_MAX_USERNAME_LENGTH]; /**< Username string. */
+ cb_uint8 passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH]; /**< Passphrase string. */
+ cb_uint8 domain[cbWLAN_MAX_DOMAIN_LENGTH]; /**< Domain string. */
+ cbCERT_Stream *clientCertificate; /**< Stream handle to provide SSL certificate for authentication. */
+ cbCERT_Stream *clientPrivateKey; /**< Stream handle to provide SSL private key for authentication. */
+ cbCERT_Stream *CACertificate; /**< Stream handle to provide CA certificate for server certificate validation,
+ Can be NULL if server certificate shouldn't be validated. */
+} cbWLAN_EnterpriseConnectParameters;
+
+/**
+ * Common access point parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_CommonApParameters {
+ cbWLAN_Ssid ssid; /**< SSID to connect to. */
+ cbWLAN_Channel channel; /**< Active channel. */
+ cbWLAN_RateMask basicRates; /**< Basic rates. */
+ cbWLAN_RateMask allowedRates; /**< BSS allowed rates. */
+ cb_uint8 dtimInterval; /**< Dtim Interval. */
+} cbWLAN_CommonApParameters;
+
+
+/**
+* WPA PSK specific AP parameters.
+*
+* @ingroup wlan
+*/
+typedef struct cbWLAN_WPAPSKApParameters {
+ cbWLAN_CipherSuite rsnCiphers; /**< Bit field indicating which ciphers that shall be displayed in RSN information elements. If 0 no RSN information elements is added to beacons and probe responses. */
+ cbWLAN_CipherSuite wpaCiphers; /**< Bit field indicating which ciphers that shall be displayed in WPA information elements. If 0 no WPA information elements is added to beacons and probe responses. */
+ cbWLAN_WPAPSK psk; /**< WPA pre-shared key*/
+#if defined(CB_FEATURE_802DOT11W)
+ cbWLAN_PMFApParameters pmfParameters;
+#endif
+ cb_uint32 gtkRekeyInterval; /**< Group rekey interval in seconds */
+} cbWLAN_WPAPSKApParameters;
+
+/**
+ * Scan parameters
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_ScanParameters {
+ cbWLAN_Ssid ssid; /**< SSID to scan for, set to zero length for broadcast scan. */
+ cbWLAN_Channel channel;
+} cbWLAN_ScanParameters;
+
+/**
+ * Scan result information reported from WLAN component. Contains info for
+ * one specific BSS.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_ScanIndicationInfo {
+ cbWLAN_MACAddress bssid; /**< BSS BSSID */
+ cbWLAN_Ssid ssid; /**< BSS SSID */
+ cbWLAN_Channel channel; /**< BSS channel */
+ cbWLAN_OperationalMode operationalMode; /**< BSS type */
+ cb_int32 rssi; /**< RSSI for scan result packet. */
+
+ cbWLAN_AuthenticationSuite authenticationSuites; /**< Supported authentication suites */
+ cbWLAN_CipherSuite unicastCiphers; /**< Supported unicast cipher suites */
+ cbWLAN_CipherSuite groupCipher; /**< Supported group cipher suites */
+#if defined(CB_FEATURE_802DOT11R)
+ cbWLAN_MDInformation mobilityDomainId; /**< Mobility Domain Id and Ft capability policy>*/
+#endif
+ cbWLAN_RateMask basicRateSet; /**< Basic rate set, i.e. required rates. */
+ cbWLAN_RateMask supportedRateSet; /**< Supported rate set, super set of basic rate set. */
+ cb_uint32 beaconPeriod; /**< Beacon period in ms. */
+ cb_uint32 DTIMPeriod; /**< DTIM period in beacon intervals */
+ cb_uint8 countryCode[2]; /**< Two letter country code */
+ cb_uint32 flags; /**< QoS, short preamble, DFS, privacy */
+ cb_uint16 RSNCapabilities; /**< Protected management frames capabilities*/
+} cbWLAN_ScanIndicationInfo;
+
+/**
+ * Status indications indicated by @ref cbWLAN_statusIndication.
+ *
+ * @ingroup wlan
+ */
+typedef enum {
+ cbWLAN_STATUS_STOPPED,
+ cbWLAN_STATUS_STARTED,
+ cbWLAN_STATUS_ERROR,
+ cbWLAN_STATUS_DISCONNECTED,
+ cbWLAN_STATUS_CONNECTING,
+ cbWLAN_STATUS_CONNECTED,
+ cbWLAN_STATUS_CONNECTION_FAILURE,
+ cbWLAN_STATUS_AP_UP,
+ cbWLAN_STATUS_AP_DOWN,
+ cbWLAN_STATUS_AP_STA_ADDED,
+ cbWLAN_STATUS_AP_STA_REMOVED,
+ cbWLAN_STATUS_80211r_REASSOCIATING,
+ cbWLAN_STATUS_80211r_REASSOCIATED,
+} cbWLAN_StatusIndicationInfo;
+
+/**
+ * Disconnection reasons for @ref cbWLAN_STATUS_DISCONNECTED.
+ *
+ * @ingroup wlan
+ */
+typedef enum {
+ cbWLAN_STATUS_DISCONNECTED_UNKNOWN,
+ cbWLAN_STATUS_DISCONNECTED_NO_BSSID_FOUND,
+ cbWLAN_STATUS_DISCONNECTED_AUTH_TIMEOUT,
+ cbWLAN_STATUS_DISCONNECTED_MIC_FAILURE,
+ cbWLAN_STATUS_DISCONNECTED_ROAMING,
+} cbWLAN_StatusDisconnectedInfo;
+
+/**
+ * IOCTL parameters @ref cbWLAN_ioctl
+ *
+ * @ingroup wlan
+ */
+typedef enum {
+ cbWLAN_IOCTL_FIRST
+} cbWLAN_Ioctl;
+
+
+/**
+ * Start parameters indicated from WLAN driver for status indication
+ * @ref cbWLAN_STATUS_STARTED.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_StatusStartedInfo {
+ cbWLAN_MACAddress macAddress; /**< MAC address of WLAN driver. */
+} cbWLAN_StatusStartedInfo;
+
+/**
+ * Connected parameters indicated from WLAN driver for status indication
+ * @ref cbWLAN_STATUS_CONNECTED.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_StatusConnectedInfo {
+ cbWLAN_MACAddress bssid; /**< BSSID of the BSS connected to. */
+ cbWLAN_Channel channel; /**< Operating channels of the BSS connected to. */
+ cb_uint16 mobilityDomainId;
+} cbWLAN_StatusConnectedInfo;
+
+/**
+ * Received Ethernet data packet information and properties.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_PacketIndicationInfo {
+ void *rxData; /**< Pointer to the port specific data type. */
+ cb_uint32 size; /**< Length of the data payload in the port specific packet data type. */
+ cb_boolean isChecksumVerified; /**< True if the TCP/UDP checksum is verified and correct. */
+} cbWLAN_PacketIndicationInfo;
+
+/**
+ * Status updates from WLAN component.
+ * @note The callback must not make any call back to WLAN.
+ *
+ * @param callbackContext Context pointer provided in @ref cbWLAN_registerStatusCallback.
+ * @param status Status indication type.
+ * @param data Additional status indication data, depends on indication type.
+ *
+ * @sa cbWLAN_registerStatusCallback
+ */
+typedef void (*cbWLAN_statusIndication)(void *callbackContext, cbWLAN_StatusIndicationInfo status, void *data);
+
+
+/**
+ * Indication of received Ethernet data packet.
+ *
+ * @param callbackContext Context pointer provided in @ref cbWLAN_registerPacketIndicationCallback.
+ * @param packetInfo Pointer to struct containing packet information and data pointers.
+ */
+typedef void (*cbWLAN_packetIndication)(void *callbackContext, cbWLAN_PacketIndicationInfo *packetInfo);
+
+/**
+* Scan result indication from WLAN component.
+*
+* @param callbackContext Context pointer provided in @ref cbWLAN_scan.
+* @param bssDescriptor Pointer to struct containing scan result information.
+* @param isLastResult @ref TRUE if scan scan is finished.
+*/
+typedef void (*cbWLAN_scanIndication)(void *callbackContext, cbWLAN_ScanIndicationInfo *bssDescriptor, cb_boolean isLastResult);
+
+/*===========================================================================
+ * WLAN API
+ *=========================================================================*/
+
+/**
+ * Initialize WLAN component.
+ *
+ * @return @ref cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_init();
+
+
+/**
+ * Stop WLAN component.
+ * Stop and destroy WLAN driver instance.
+ *
+ * @return @ref cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_stop(void);
+
+/**
+ * Connect to access point in open mode (no encryption).
+ * Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+ *
+ * @param commonParams Connection parameters.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_connectOpen(cbWLAN_CommonConnectParameters *commonParams);
+
+/**
+ * Connect to access point in open mode with WEP encryption.
+ * Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+ *
+ * @param commonParams Connection parameters.
+ * @param wepParams WEP specific connection parameters.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_connectWEP(cbWLAN_CommonConnectParameters *commonParams, cbWLAN_WEPConnectParameters *wepParams);
+
+/**
+ * Connect to access point with WPA PSK authentication.
+ * Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+ *
+ * @param commonParams Connection parameters.
+ * @param wpaParams WPA PSK specific connection parameters.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_connectWPAPSK(cbWLAN_CommonConnectParameters *commonParams, cbWLAN_WPAPSKConnectParameters *wpaParams);
+
+/**
+ * Connect to access point with WPA Enterprise authentication.
+ * Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+ *
+ * @param commonParams Connection parameters.
+ * @param enterpriseParams WPA Enterprise specific connection parameters.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_connectEnterprise(cbWLAN_CommonConnectParameters *commonParams, cbWLAN_EnterpriseConnectParameters *enterpriseParams);
+
+/**
+ * Disconnect from access point or stop ongoing connection attempt.
+ * Disconnection progress is reported as @ref cbWLAN_statusIndication callback.
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_disconnect(void);
+
+/**
+ * Initiate BSS scan.
+ * If specific channel is set in scan parameters, only that channel is
+ * scanned. If SSID is specified, a directed probe request against that SSID
+ * will be used. Scan results are reported in @ref cbWLAN_scanIndication
+ * callbacks.
+ * @note Depending on channel using DFS or not, passive scans may be used
+ * instead of active probe requests.
+ *
+ * @param params Scan parameters
+ * @param scanIndication Callback function for scan results.
+ * @param callbackContext Context pointer, will be sent back in callback.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_scan(cbWLAN_ScanParameters *params, cbWLAN_scanIndication scanIndication, void *callbackContext);
+
+
+/**
+* Retrieve an RSSI value for station mode.
+*
+* @note Depending on connection state and data transfer interval
+* the value may be incorrect.
+*
+* @return RSSI value in dBm
+*/
+cb_int16 cbWLAN_STA_getRSSI();
+
+/**
+ * Start access point in open mode (no encryption).
+ * Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+ *
+ * @param commonParams Common Accesspoint parameters.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_apStartOpen(cbWLAN_CommonApParameters *commonParams);
+
+/**
+* Start access point with WPA PSK authentication.
+* Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+*
+* @param commonParams Common Accesspoint parameters.
+* @param wpaParams WPA PSK specific parameters.
+* @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+*/
+cbRTSL_Status cbWLAN_apStartWPAPSK(cbWLAN_CommonApParameters *commonParams, cbWLAN_WPAPSKApParameters *wpaParams);
+
+/**
+ * Stop access point.
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_apStop(void);
+
+/**
+ * Send an Ethernet data packet.
+ * @note Data send when not in connected state is just dropped.
+ *
+ * @param txData Pointer to the port specific Ethernet data type containing transmit data
+ */
+void cbWLAN_sendPacket(void *txData);
+
+/**
+ * Register a status indication callback.
+ * @note There may be multiple clients connected.
+ *
+ * @param statusIndication Callback function.
+ * @param callbackContext Context pointer, will be sent back in callback.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_registerStatusCallback(cbWLAN_statusIndication statusIndication, void *callbackContext);
+
+
+/**
+ * Register a status indication callback.
+ *
+ * @param packetIndication Callback function.
+ * @param callbackContext Context pointer, will be sent back in callback.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_registerPacketIndicationCallback(cbWLAN_packetIndication packetIndication, void *callbackContext);
+
+/**
+ * Deregister the specified status indication callback.
+ *
+ * @param statusIndication Callback function.
+ * @param callbackContext Context pointer, will be sent back in callback.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_deregisterStatusCallback(cbWLAN_statusIndication statusIndication, void *callbackContext);
+
+
+cbRTSL_Status cbWLAN_Util_PSKFromPWD(cb_char passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH], cbWLAN_Ssid ssid, cb_uint8 psk[cbWLAN_PSK_LENGTH]);
+
+/**
+ * Set the channel list to be used for connection and scanning.
+ * The list will be filtered according to the allowed channel list
+ * set. The list can include both 2.4GHz and 5GHz channels.
+ * If channel list parameter is NULL the default channel list is
+ * restored.
+ *
+ * @param channelList Pointer to channel list for the driver to use.
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_setChannelList(const cbWLAN_ChannelList *channelList);
+
+/**
+ * Returns the wanted channel list.
+ *
+ * @param channelList Pointer to channel list
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_getChannelList(cbWLAN_ChannelList *channelList);
+
+/**
+ * Returns the channel list currently used. This channel list
+ * depend on the channel list specified by the user and the
+ * current regulatory domain.
+ *
+ * @param channelList Pointer to channel list
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_getActiveChannelList(cbWLAN_ChannelList *channelList);
+
+/**
+ * WLAN control settings. Both in and out parameters are supported.
+ * If an ioctl request is not supported cbSTATUS_ERROR is returned and
+ * the value parameter shall be ignored.
+ *
+ * @param ioctl Parameter that shall be set. @ref cbWLAN_Ioctl lists all supported parameters.
+ * @param value Value. @ref cbWLAN_Ioctl lists the type for all supported parameters.
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_ioctl(cbWLAN_Ioctl ioctl, void* value);
+
+cbRTSL_Status cbWLAN_getVersion(cbWM_Version* version);
+
+#if defined(CB_FEATURE_802DOT11R)
+
+/**
+ * Called for changing the BSS
+ *
+ * @param params Parameter containing the BSS parameters.
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_changeBSS(cbWLAN_BSSChangeParameters params);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_WLAN_H_ */
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_driver_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_driver_config.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,300 @@
+/**
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * Component : Wireless LAN driver
+ * File : cb_wlan_driver_config.h
+ *
+ * Description : OS related functions
+ *-------------------------------------------------------------------------*/
+/**
+ * @file cb_wlan_driver_config.h Driver configuration.
+ * @ingroup port
+ */
+#ifndef _CB_WLAN_DRIVER_CONFIG_H_
+#define _CB_WLAN_DRIVER_CONFIG_H_
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include "cb_target.h"
+#include "cb_status.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbWLAN_ENABLE_802_11b
+#define cbWLAN_ENABLE_802_11g
+#define cbWLAN_ENABLE_802_11n
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+#define cbTARGET_GSETTING_4_ADDRESS_MODE_STATION_DYNAMIC cb_BIT_0
+#define cbTARGET_GSETTING_4_ADDRESS_MODE_STATION_ALWAYS cb_BIT_1
+/**
+ * General settings and tuning parameters .
+ *
+ * @ingroup types
+ */
+typedef enum wm_gsetting_e {
+ cbTARGET_GSETTING_START = 0,
+ cbTARGET_GSETTING_PREAMBLE = cbTARGET_GSETTING_START, /**< 0 = Long preamble, 1 = Short preamble */
+ cbTARGET_GSETTING_MIN_SCAN_TIME, /**< Minimum scan time in TU per channel */
+ cbTARGET_GSETTING_MAX_SCAN_TIME, /**< Maximum scan time in TU per channel */
+ cbTARGET_GSETTING_SCAN_TYPE, /**< Use @ref cbWM_ScanType. */
+ cbTARGET_GSETTING_BEACON_INTERVAL, /**< Beacon interval for Ad-hoc/IBSS networks. */
+ cbTARGET_GSETTING_JOIN_FAILURE_TIMEOUT, /**< Time in beacons before the join procedure times out. */
+ cbTARGET_GSETTING_BT_COEX, /**< Bluetooth co-existence 0 = off, 1 = on */
+ cbTARGET_GSETTING_DATA_RATE, /**< Set the data rate to use. Use @ref cbWLAN_Rate */
+ cbTARGET_GSETTING_LINK_ADAPTION, /**< Dynamically adapt the data rate. 0 = off, 1 = on */
+ cbTARGET_GSETTING_POWER_SAVE, /**< 0 = off, 1 = Fast PSP, 2 = Max PSP */
+ cbTARGET_GSETTING_DTIM_ENABLE, /**< Enable DTIM when powersaving */
+ cbTARGET_GSETTING_QOS_ENABLE, /**< Enable QoS */
+ cbTARGET_GSETTING_RTS_THRESHOLD, /**< Set the RTS (Request to send) threshold */
+ cbTARGET_GSETTING_FRAGMENTATION_THRESHOLD, /**< Set the fragmentation threshold */
+ cbTARGET_GSETTING_TX_POWER, /**< Desired output power in dBm. */
+ cbTARGET_GSETTING_MAX_PASSIVE_SCAN_TIME, /**< Maximum scan time for passive scan */
+ cbTARGET_GSETTING_MODULE_TYPE, /**< Type of module. TODO: remove. Legacy parameter that shouldn't be possible to change. */
+ cbTARGET_GSETTING_SCAN_LISTEN_INTERVAL, /**< Listen interval between channel scans */
+ cbTARGET_GSETTING_SLEEP_TIMEOUT, /**< Only allow power save modes after this period of inactivity. Timeout in ms. Only used when power save is enabled */
+ cbTARGET_GSETTING_DOT11_SHORT_RETRY_LIMIT, /**< 802.11 short retry limit for station (dot11ShortRetryLimit). Bit 31-24 reserved, bit 23-16 EAPOL & Broadcast, bit 15-8 MGMT, bit 7-0 data. */
+ cbTARGET_GSETTING_DOT11_LONG_RETRY_LIMIT, /**< 802.11 long retry limit for station (dot11LongRetryLimit). Bit 31-24 reserved, bit 23-16 EAPOL & Broadcast, bit 15-8 MGMT, bit 7-0 data. */
+ cbTARGET_GSETTING_AP_DOT11_SHORT_RETRY_LIMIT, /**< 802.11 short retry limit for AP (dot11ShortRetryLimit). Bit 31-24 reserved, bit 23-16 EAPOL & Broadcast, bit 15-8 MGMT, bit 7-0 data. */
+ cbTARGET_GSETTING_AP_DOT11_LONG_RETRY_LIMIT, /**< 802.11 long retry limit for AP (dot11LongRetryLimit). Bit 31-24 reserved, bit 23-16 EAPOL & Broadcast, bit 15-8 MGMT, bit 7-0 data. */
+ cbTARGET_GSETTING_CHANNEL_TYPE, /**< 0-NO_HT, 1-HT20, 2-HT40MINUS, 3-HT40PLUS */
+ cbTARGET_GSETTING_PMF_STA, /**< Protected Management frame Option for STA*/
+ cbTARGET_GSETTING_REMAIN_ON_CHANNEL, /**< Set 0 disable, 1 enable */
+ cbTARGET_GSETTING_STA_TX_RATE_MASK, /**< TX rates for station. May be overridden if not supported by AP. Set to 0 for AP default. @sa cbWLAN_RateMask_e */
+ cbTARGET_GSETTING_RSSI_GOOD, /**< When to abort scanning and initiate connection */
+ cbTARGET_GSETTING_RSSI_BAD, /**< When to use BAD_RSSI_SCAN_YIELD_TIMEOUT for scanning between each channel for roaming */
+ cbTARGET_GSETTING_GOOD_RSSI_SCAN_YIELD_TIMEOUT, /**< Gap between each channel when doing background scan with a good connection */
+ cbTARGET_GSETTING_BAD_RSSI_SCAN_YIELD_TIMEOUT, /**< Gap between each channel when doing background scan with a bad connection */
+ cbTARGET_GSETTING_ROAM_BLACKLIST_LAST_BSSID_TIMEOUT, /**< How long a new connection to the last connected AP should be banned */
+ cbTARGET_GSETTING_FORCE_WORLD_MODE, /**< Set 0 disable, 1 enable */
+ cbTARGET_GSETTING_TX_PACKET_ACK_TIMEOUT_WD, /**< Max time for an Tx packet to not being acked by the radio before we send a soft-error event */
+ cbTARGET_GSETTING_CTS_PROTECTION, /** send CTS to self before transmission. 0 disable, 1 enable. */
+ cbTARGET_GSETTING_HIDDEN_SSID, /** Hidden ssid, 0 disable else enable. */
+ cbTARGET_GSETTING_AP_STA_INACTIVITY_TIMEOUT, /**< Aging period for Station in seconds */
+ cbTARGET_GSETTING_ROAMING_AREA_HYSTERESIS, /** Threshold between good and bad connection. */
+ cbTARGET_GSETTING_FT_MODE, /** 802.11r (FT) mode, 0 - Disabled, 1 - FT over air, 2 - FT over DS */
+ cbTARGET_GSETTING_4_ADDRESS_MODE, /** Bit0 - enable dynamic mode for station. Bit1 - always enable for station. */
+ cbTARGET_GSETTING_MAX,
+} cbWM_GSETTING;
+
+typedef enum targetConfigParams {
+ cbTARGET_CFG_FIRST,
+ cbTARGET_CFG_SET_POWER_SAVE_MODE = cbTARGET_CFG_FIRST, //!< Set power mode @ref cbWLAN_IoctlPowerSaveMode
+ cbTARGET_CFG_GET_POWER_SAVE_MODE, //!< Get power mode @ref cbWLAN_IoctlPowerSaveMode
+ cbTARGET_CFG_SET_LISTEN_INTERVAL, //!< Set listen interval, integer value 0 - 16
+ cbTARGET_CFG_GET_LISTEN_INTERVAL, //!< Get listen interval, integer value 0 - 16
+ cbTARGET_CFG_SET_DTIM_ENABLE, //!< Set DTIM enable 0, disable 1 enable
+ cbTARGET_CFG_GET_DTIM_ENABLE, //!< Get DTIM enable 0, disable 1 enable
+ cbTARGET_CFG_SET_SLEEP_TIMEOUT, //!< Set enter power save entry delay (in ms). Power save mode will be entered only if there no activity during this delay
+ cbTARGET_CFG_GET_SLEEP_TIMEOUT, //!< Get enter power save entry delay (in ms). Power save mode will be entered only if there no activity during this delay
+ cbTARGET_CFG_SET_RSSI_GOOD, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_GET_RSSI_GOOD, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_SET_RSSI_BAD, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_GET_RSSI_BAD, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_SET_GOOD_RSSI_YIELD_TMO, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_GET_GOOD_RSSI_YIELD_TMO, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_SET_BAD_RSSI_YIELD_TMO, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_GET_BAD_RSSI_YIELD_TMO, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_SET_BLACKLIST_LAST_BSSID_TIMEOUT, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_GET_BLACKLIST_LAST_BSSID_TIMEOUT, //!< SEE CORRESPONDING GSETTING
+ cbTARGET_CFG_LAST,
+ cbTARGET_CFG_SET_GSETTING = 1000, //!< Pipe to @ref cbWM_gSet.
+ cbTARGET_CFG_SET_TSETTING = 2000, //!< Pipe to @ref cbWM_tSet.
+ cbTARGET_CFG_GET_GSETTING = 3000, //!< Pipe to @ref cbWM_gGet.
+ cbTARGET_CFG_GET_TSETTING = 4000, //!< Pipe to @ref cbWM_tGet.
+} cbTARGET_ConfigParams;
+
+#define cbTARGET_GSETTING_REG(X) ((cb_uint32)((X) - cbTARGET_GSETTING_START))
+
+/**
+ * Target specific settings and tuning parameters .
+ *
+ * @ingroup types
+ */
+typedef enum wm_tsetting_e {
+ cbTARGET_TSETTING_START = 1000,
+ cbTARGET_TSETTING_PS_LISTEN_INTERVAL = cbTARGET_TSETTING_START, /**< Powersave: Listen interval in beacons. */
+ cbTARGET_TSETTING_PS_FAST_PSP_TIMEOUT, /**< Powersave: In mode Fast PSP timeout in ms before entering PS. */
+ cbTARGET_TSETTING_ANTENNA_RECEIVE_DIVERSITY, /**< Enable receive antenna diversity. 0 = off, 1 = on. */
+ cbTARGET_TSETTING_QOS_WMM_NOACK, /**< Enable WMM QoS no-ack acknowledgment policy. 0 = normal ack, 1 = no-ack. */
+ cbTARGET_TSETTING_PS_BEACON_EARLY_TERMINATION, /**< Powersave: In Max PSP, use beacon early termination. */
+ cbTARGET_TSETTING_MAX,
+} cbWM_TSETTING;
+
+#define cbTARGET_TSETTING_REG(X) ((cb_uint32)((X) - cbTARGET_TSETTING_START))
+
+/**
+ * Defines the type of scanning procedure.
+ * Passive scan will only listen for beacons.
+ * Active scan will send out a probe request
+ * and listen for both probe responses and beacons.
+ *
+ * @ingroup types
+ */
+typedef enum cbWM_ScanType_e {
+ cbWM_SCAN_INVALID,
+ cbWM_SCAN_ACTIVE,
+ cbWM_SCAN_PASSIVE,
+} cbWM_ScanType;
+
+/**
+ * Power save levels.
+ * @note Levels between 2 and cbWM_POWERSAVE_MAX are target specific.
+ *
+ * @ingroup types
+ */
+typedef enum cbWM_PowerSaveType_e {
+ cbWM_POWERSAVE_OFF = 0,
+ cbWM_POWERSAVE_FAST_PSP = 1,
+ cbWM_POWERSAVE_MAX_PSP = 2,
+ cbWM_POWERSAVE_MAX = cb_UINT8_MAX,
+} cbWM_PowerSaveType;
+
+/**
+ * Power save modes set using @ref cbWLAN_ioctl
+ *
+ * @ingroup wlan
+ */
+typedef enum {
+ cbTARGET_POWER_SAVE_MODE_OFF,
+ cbTARGET_POWER_SAVE_MODE_SLEEP,
+ cbTARGET_POWER_SAVE_MODE_DEEP_SLEEP
+} cbTARGET_PowerSaveMode;
+
+typedef enum {
+ cbWLAN_ONE_ANTENNA = 1,
+ cbWLAN_TWO_ANTENNAS
+} cbWLAN_NUMBER_OF_ANTENNAS;
+
+typedef enum {
+ cbWLAN_PRIMARY_ANTENNA_ONE = 1,
+ cbWLAN_PRIMARY_ANTENNA_TWO
+} cbWLAN_PRIMARY_ANTENNA;
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Get general tuning parameter.
+ *
+ * @param hTarget Handle to the current driver instance.
+ * @param setting setting to read.
+ * @return parameter value
+ */
+cb_uint32 cbTARGET_gGet(cbTARGET_Handle* hTarget, cbWM_GSETTING setting);
+
+/**
+ * Set general tuning parameter.
+ *
+ * @param hTarget Handle to the current driver instance.
+ * @param setting setting to modify.
+ * @param value value to set.
+ */
+void cbTARGET_gSet(cbTARGET_Handle* hTarget, cbWM_GSETTING setting, cb_uint32 value);
+
+/**
+ * Get target specific tuning parameter.
+ *
+ * @param hTarget Handle to the current driver instance.
+ * @param setting setting to read.
+ * @return parameter value
+ */
+cb_uint32 cbTARGET_tGet(cbTARGET_Handle* hTarget, cbWM_TSETTING setting);
+
+/**
+ * Set target specific tuning parameter.
+ *
+ * @param hTarget Handle to the current driver instance.
+ * @param setting setting to modify.
+ * @param value value to set.
+ */
+void cbTARGET_tSet(cbTARGET_Handle* hTarget, cbWM_TSETTING setting, cb_uint32 value);
+
+struct cb_wlan_configuration* cbTARGET_configuration_create();
+
+cbRTSL_Status cbTARGET_configure(cbTARGET_Handle* hTarget, cbTARGET_ConfigParams parameter, void* value);
+
+/*--------------------------------------------------------------------------
+ * Constants
+ *-------------------------------------------------------------------------*/
+
+#define W_CONST_PREAMBLE (1)
+#define W_CONST_LISTEN_INTERVAL (16)
+#define W_CONST_MIN_SCAN_TIME (25)
+#define W_CONST_MAX_SCAN_TIME (50)
+#define W_CONST_SCAN_TYPE (cbWM_SCAN_ACTIVE)
+#define W_CONST_BEACON_INTERVAL (100)
+#define W_CONST_JOIN_FAILURE_TIMEOUT (600)
+#define W_CONST_WLAN_BT_COEX (0)
+#define W_CONST_DATA_RATE (cbWLAN_RATE_24)
+#define W_CONST_LINK_ADAPTION (1)
+#define W_CONST_POWER_SAVE (2)
+#define W_CONST_DTIM_ENABLE (1)
+#define W_CONST_QOS_ENABLE (1)
+#define W_CONST_CHANNEL_TYPE (1) //HT20MHz
+#define W_CONST_RTS_THRESHOLD (2347)
+#define W_CONST_FRAGMENTATION_THRESHOLD (2346)
+#define W_CONST_TX_POWER (15)
+#define W_CONST_MAX_PASSIVE_SCAN_TIME (150)
+#define W_CONST_SCAN_LISTEN_INTERVAL (150)
+#define W_CONST_SLEEP_TIMEOUT (100) // Timeout in ms, 100ms timeout gives almost same throughput as without power save but still low power consumption
+#define W_CONST_DEFAULT_MODULE_TYPE (cbWM_MODULE_UNKNOWN)
+#define W_CONST_PMF_OPTIONAL (cbWLAN_PMF_OPTIONAL)
+#define W_CONST_REMAIN_ON_CHANNEL (1) // Enabled
+#define W_CONST_DEFAULT_STA_TX_RATES (0) // Use AP default
+#define W_CONST_GOOD_RSSI (55)
+#define W_CONST_BAD_RSSI (70)
+#define W_CONST_GOOD_RSSI_SCAN_YIELD_TIMEOUT (1500)
+#define W_CONST_BAD_RSSI_SCAN_YIELD_TIMEOUT (W_CONST_SCAN_LISTEN_INTERVAL)
+#define W_CONST_BLACKLIST_LAST_BSSID_TIMEOUT (20) // Seconds
+#define W_CONST_ROAMING_AREA_HYSTERESIS (3)
+#define W_CONST_TX_PACKET_ACK_TIMEOUT (10000)
+#define W_CONST_FT_MODE (2)
+
+#define W_CONST_DEFAULT_FORCE_WORLD_MODE (0)
+
+#define W_CONST_DEFAULT_AP_STA_INACTIVITY_TIMEOUT (120)
+
+
+#define W_CONST_DEFAULT_DOT11_SHORT_RETRY_LIMIT (0x0a0a0a0aul)
+#define W_CONST_DEFAULT_DOT11_LONG_RETRY_LIMIT (0x0a0a0a0aul)
+#define W_CONST_DEFAULT_AP_DOT11_SHORT_RETRY_LIMIT (0x0a0a0a0aul)
+#define W_CONST_DEFAULT_AP_DOT11_LONG_RETRY_LIMIT (0x0a0a0a0aul)
+
+//Target specific values
+#define W_CONST_PS_LISTEN_INTERVAL (0)
+#define W_CONST_PS_FAST_PSP_TIMEOUT (50)
+#define W_CONST_ANTENNA_RECEIVE_DIVERSITY (0)
+#define W_CONST_PS_BEACON_EARLY_TERMINATION (0)
+
+#define W_CONST_2_4GHZ_MGMT_RATE (cbWLAN_RATE_01)
+#define W_CONST_5GHZ_MGMT_RATE (cbWLAN_RATE_06)
+
+#define W_CONST_DEFAULT_RSSI (-100)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_SYSTEM_H_ */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,119 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : Wireless LAN driver
+ * File : cb_wlan_target_data.h
+ *
+ * Description : Port specific data buffer handling (ethernet frames)
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_wlan_target_data.h Handles the anonymous port specific packetization
+ * of ethernet frames.
+ * @ingroup target
+ */
+
+#ifndef _CB_WLANTARGET_DATA_H_
+#define _CB_WLANTARGET_DATA_H_
+
+#include "cb_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+typedef struct cbWLANTARGET_dataFrame cbWLANTARGET_dataFrame;
+typedef struct cbWLANTARGET_Handle cbWLANTARGET_Handle;
+
+
+/**
+ * Copy data from frame data memory to buffer.
+ *
+ * @param buffer The destination buffer.
+ * @param frame Frame memory pointer (@ref cbWLANTARGET_allocDataFrame).
+ * @param size Number of bytes to copy.
+ * @param offsetInFrame Offset into frame memory.
+ * @return @ref TRUE if successful, otherwise @ref FALSE.
+ */
+typedef cb_boolean(*cbWLANTARGET_copyFromDataFrame)(cb_uint8* buffer, cbWLANTARGET_dataFrame* frame, cb_uint32 size, cb_uint32 offsetInFrame);
+
+/**
+ * Copy data from buffer to frame data memory.
+ *
+ * @param frame Frame memory pointer (@ref cbWLANTARGET_allocDataFrame).
+ * @param buffer The destination buffer.
+ * @param size Number of bytes to copy.
+ * @param offsetInFrame Offset into frame memory.
+ * @return @ref TRUE if successful, otherwise @ref FALSE.
+ */
+typedef cb_boolean(*cbWLANTARGET_copyToDataFrame)(cbWLANTARGET_dataFrame* frame, cb_uint8* buffer, cb_uint32 size, cb_uint32 offsetInFrame);
+
+/**
+ * Allocate memory in frame data memory.
+ *
+ * @param size Number of bytes to allocate.
+ * @return Pointer to the frame memory.
+ *
+ * @ref cbWLANTARGET_freeDataFrame
+ */
+typedef cbWLANTARGET_dataFrame*(*cbWLANTARGET_allocDataFrame)(cb_uint32 size);
+
+/**
+ * Destroy memory in frame data memory.
+ *
+ * @param frame Pointer to the frame memory that should be destroyed.
+ * @ref cbWLANTARGET_allocDataFrame
+ */
+typedef void(*cbWLANTARGET_freeDataFrame)(cbWLANTARGET_dataFrame* frame);
+
+typedef cb_uint32(*cbWLANTARGET_getDataFrameSize)(cbWLANTARGET_dataFrame* frame);
+
+typedef cb_uint8(*cbWLANTARGET_getDataFrameTID)(cbWLANTARGET_dataFrame* frame);
+
+typedef struct
+{
+ cbWLANTARGET_copyFromDataFrame copyFromDataFrameIndication;
+ cbWLANTARGET_copyToDataFrame copyToDataFrameIndication;
+ cbWLANTARGET_allocDataFrame allocDataFrameIndication;
+ cbWLANTARGET_freeDataFrame freeDataFrameIndication;
+ cbWLANTARGET_getDataFrameSize getDataFrameSizeIndication;
+ cbWLANTARGET_getDataFrameTID getDataFrameTIDIndication;
+}cbWLANTARGET_Callback;
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Register WLAN target callbacks. This should be done for packetization between
+ * the WLAN driver and an IP stack.
+ *
+ * @param callbacks Callbacks
+ */
+void cbWLANTARGET_registerCallbacks(cbWLANTARGET_Callback* callbacks);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,699 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component : WLAN driver
+ * File : cb_wlan_types.h
+ *
+ * Description : Common wireless LAN defines and types.
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_wlan_types.h The main WLAN 802.11 interface
+ *
+ * @ingroup WLANDriver
+ */
+
+#ifndef _CB_WLAN_TYPES_H_
+#define _CB_WLAN_TYPES_H_
+
+#include "cb_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/**
+ * Max length for an SSID
+ *
+ * @ingroup wlantypes
+ */
+#define cbWLAN_SSID_MAX_LENGTH (32)
+
+/**
+ * EAPOL ethernet type
+ *
+ * @ingroup wlantypes
+ */
+#define cbWLAN_ETHTYPE_EAPOL (0x888E)
+
+/**
+ * Maximum size of a predefined WEP key
+ *
+ * @ingroup wlantypes
+ */
+#define cbWLAN_KEY_SIZE_WEP_MAX (cbWLAN_KEY_SIZE_WEP128)
+
+#define cbWLAN_OUI_SIZE 3
+
+#define cbRATE_MASK_B (cbRATE_MASK_01 | cbRATE_MASK_02 | cbRATE_MASK_5_5 | cbRATE_MASK_11)
+#define cbRATE_MASK_G (cbRATE_MASK_06 | cbRATE_MASK_09 | cbRATE_MASK_12 | cbRATE_MASK_18 | cbRATE_MASK_24 | cbRATE_MASK_36 | cbRATE_MASK_48 | cbRATE_MASK_54)
+#define cbRATE_MASK_A (cbRATE_MASK_G)
+#define cbRATE_MASK_N (cbRATE_MASK_MCS0 | cbRATE_MASK_MCS1 | cbRATE_MASK_MCS2 | cbRATE_MASK_MCS3 | cbRATE_MASK_MCS4 | cbRATE_MASK_MCS5 | cbRATE_MASK_MCS6 | cbRATE_MASK_MCS7)
+#define cbRATE_TX_MIMO (cbRATE_MASK_MCS8 | cbRATE_MASK_MCS9 | cbRATE_MASK_MCS10 | cbRATE_MASK_MCS11 | cbRATE_MASK_MCS12 | cbRATE_MASK_MCS13 | cbRATE_MASK_MCS14 | cbRATE_MASK_MCS15)
+#define cbRATE_TX_WIDE (cbRATE_MASK_WIDE)
+#define cbRATE_MASK_ALL (cbRATE_MASK_B | cbRATE_MASK_G | cbRATE_MASK_N | cbRATE_TX_MIMO | cbRATE_TX_WIDE)
+
+#define cbWLAN_MAX_CHANNEL_LIST_LENGTH 38
+
+#define cbWLAN_TX_POWER_AUTO 0xFF
+
+#define cbWLAN_PMF_MFPR cb_BIT_6 // Bit 6: Management Frame Protection Required (MFPR)
+#define cbWLAN_PMF_MFPC cb_BIT_7 // Bit 7: Management Frame Protection Capable (MFPC).
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+/**
+ * The encryption mode.
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_EncryptionMode_e {
+ cbWLAN_ENC_NONE,
+ cbWLAN_ENC_WEP64,
+ cbWLAN_ENC_WEP128,
+ cbWLAN_ENC_TKIP,
+ cbWLAN_ENC_AES,
+ cbWLAN_ENC_BIP,
+} cbWLAN_EncryptionMode;
+
+typedef enum cbWLAN_CipherSuite {
+ cbWLAN_CIPHER_SUITE_NONE = 0x00,
+ cbWLAN_CIPHER_SUITE_WEP64 = 0x01,
+ cbWLAN_CIPHER_SUITE_WEP128 = 0x02,
+ cbWLAN_CIPHER_SUITE_TKIP = 0x04,
+ cbWLAN_CIPHER_SUITE_AES_CCMP = 0x08,
+ cbWLAN_CIPHER_SUITE_BIP = 0x10,
+} cbWLAN_CipherSuite;
+
+typedef enum cbWLAN_AuthenticationSuite {
+ cbWLAN_AUTHENTICATION_SUITE_NONE = 0x0000,
+ cbWLAN_AUTHENTICATION_SUITE_SHARED_SECRET = 0x0001,
+ cbWLAN_AUTHENTICATION_SUITE_PSK = 0x0002,
+ cbWLAN_AUTHENTICATION_SUITE_8021X = 0x0004,
+ cbWLAN_AUTHENTICATION_SUITE_USE_WPA = 0x0008,
+ cbWLAN_AUTHENTICATION_SUITE_USE_WPA2 = 0x0010,
+ cbWLAN_AUTHENTICATION_SUITE_PSK_SHA256 = 0x0020,
+ cbWLAN_AUTHENTICATION_SUITE_8021X_SHA256 = 0x0040,
+ cbWLAN_AUTHENTICATION_SUITE_8021X_FT = 0x0080,
+ cbWLAN_AUTHENTICATION_SUITE_PSK_FT = 0x0100,
+} cbWLAN_AuthenticationSuite;
+
+
+/**
+ * Enterprise authentication mode.
+ *
+ * @ingroup wlan
+ */
+typedef enum cbWLAN_EnterpriseMode {
+ cbWLAN_ENTERPRISE_MODE_LEAP,
+ cbWLAN_ENTERPRISE_MODE_PEAP,
+ cbWLAN_ENTERPRISE_MODE_EAPTLS,
+} cbWLAN_EnterpriseMode;
+
+/**
+ * Key sizes for the supported encryptions.
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_EncryptionKeySize_e {
+ cbWLAN_KEY_SIZE_WEP64 = 5,
+ cbWLAN_KEY_SIZE_WEP128 = 13,
+ cbWLAN_KEY_SIZE_WEP2 = 16,
+ cbWLAN_KEY_SIZE_TKIP = 16,
+ cbWLAN_KEY_SIZE_AES = 16,
+ cbWLAN_KEY_SIZE_TKIP_MIC = 8
+} cbWLAN_EncryptionKeySize;
+
+enum cbWLAN_Channel_e {
+ cbWLAN_CHANNEL_ALL = 0,
+ cbWLAN_CHANNEL_01 = 1,
+ cbWLAN_CHANNEL_02,
+ cbWLAN_CHANNEL_03,
+ cbWLAN_CHANNEL_04,
+ cbWLAN_CHANNEL_05,
+ cbWLAN_CHANNEL_06,
+ cbWLAN_CHANNEL_07,
+ cbWLAN_CHANNEL_08,
+ cbWLAN_CHANNEL_09,
+ cbWLAN_CHANNEL_10,
+ cbWLAN_CHANNEL_11,
+ cbWLAN_CHANNEL_12,
+ cbWLAN_CHANNEL_13,
+ cbWLAN_CHANNEL_14,
+
+ cbWLAN_CHANNEL_36 = 36,
+ cbWLAN_CHANNEL_40 = 40,
+ cbWLAN_CHANNEL_44 = 44,
+ cbWLAN_CHANNEL_48 = 48,
+ cbWLAN_CHANNEL_52 = 52,
+ cbWLAN_CHANNEL_56 = 56,
+ cbWLAN_CHANNEL_60 = 60,
+ cbWLAN_CHANNEL_64 = 64,
+ cbWLAN_CHANNEL_100 = 100,
+ cbWLAN_CHANNEL_104 = 104,
+ cbWLAN_CHANNEL_108 = 108,
+ cbWLAN_CHANNEL_112 = 112,
+ cbWLAN_CHANNEL_116 = 116,
+ cbWLAN_CHANNEL_120 = 120,
+ cbWLAN_CHANNEL_124 = 124,
+ cbWLAN_CHANNEL_128 = 128,
+ cbWLAN_CHANNEL_132 = 132,
+ cbWLAN_CHANNEL_136 = 136,
+ cbWLAN_CHANNEL_140 = 140,
+ cbWLAN_CHANNEL_149 = 149,
+ cbWLAN_CHANNEL_153 = 153,
+ cbWLAN_CHANNEL_157 = 157,
+ cbWLAN_CHANNEL_161 = 161,
+ cbWLAN_CHANNEL_165 = 165
+};
+
+/**
+ * WLAN Channels
+ * Valid values are found in @ref cbWLAN_Channel_e
+ * @ingroup wlantypes
+ */
+typedef cb_uint8 cbWLAN_Channel;
+
+/**
+ * WLAN Channel list
+ * @ingroup wlantypes
+ */
+typedef struct {
+ cb_uint32 length;
+ cbWLAN_Channel channels[cbWLAN_MAX_CHANNEL_LIST_LENGTH];
+} cbWLAN_ChannelList;
+
+/**
+ * Standard 802.11 rates
+ *
+ * @ingroup wlantypes
+ */
+enum cbWLAN_Rate_e {
+ cbWLAN_RATE_01 = 1, // 1
+ cbWLAN_RATE_02, // 2
+ cbWLAN_RATE_5_5, // 3
+ cbWLAN_RATE_06, // 4
+ cbWLAN_RATE_09, // 5
+ cbWLAN_RATE_11, // 6
+ cbWLAN_RATE_12, // 7
+ cbWLAN_RATE_18, // 8
+ cbWLAN_RATE_24, // 9
+ cbWLAN_RATE_36, // 10
+ cbWLAN_RATE_48, // 11
+ cbWLAN_RATE_54, // 12
+ cbWLAN_RATE_MCS0, // 13
+ cbWLAN_RATE_MCS1, // 14
+ cbWLAN_RATE_MCS2, // 15
+ cbWLAN_RATE_MCS3, // 16
+ cbWLAN_RATE_MCS4, // 17
+ cbWLAN_RATE_MCS5, // 18
+ cbWLAN_RATE_MCS6, // 19
+ cbWLAN_RATE_MCS7, // 20
+ cbWLAN_RATE_MCS8, // 21
+ cbWLAN_RATE_MCS9, // 22
+ cbWLAN_RATE_MCS10, // 23
+ cbWLAN_RATE_MCS11, // 24
+ cbWLAN_RATE_MCS12, // 25
+ cbWLAN_RATE_MCS13, // 26
+ cbWLAN_RATE_MCS14, // 27
+ cbWLAN_RATE_MCS15, // 28
+ cbWLAN_RATE_MAX, // 29
+ cbWLAN_RATE_UNSUPPORTED = 0xff
+};
+
+/**
+ * Type for containing values found in @ref cbWLAN_Rate_e
+ * @ingroup wlantypes
+ */
+typedef cb_uint8 cbWLAN_Rate;
+
+
+/**
+ * Mask bits for standard 802.11 rates
+ *
+ * @ingroup wlantypes
+ */
+enum cbWLAN_RateMask_e {
+ cbRATE_MASK_01 = 0x00000001,
+ cbRATE_MASK_02 = 0x00000002,
+ cbRATE_MASK_5_5 = 0x00000004,
+ cbRATE_MASK_11 = 0x00000008,
+ cbRATE_MASK_06 = 0x00000010,
+ cbRATE_MASK_09 = 0x00000020,
+ cbRATE_MASK_12 = 0x00000040,
+ cbRATE_MASK_18 = 0x00000080,
+ cbRATE_MASK_24 = 0x00000100,
+ cbRATE_MASK_36 = 0x00000200,
+ cbRATE_MASK_48 = 0x00000400,
+ cbRATE_MASK_54 = 0x00000800,
+ // NOTE: Don't move MCS rates bit offset, see note on define below
+ cbRATE_MASK_MCS0 = 0x00001000,
+ cbRATE_MASK_MCS1 = 0x00002000,
+ cbRATE_MASK_MCS2 = 0x00004000,
+ cbRATE_MASK_MCS3 = 0x00008000,
+ cbRATE_MASK_MCS4 = 0x00010000,
+ cbRATE_MASK_MCS5 = 0x00020000,
+ cbRATE_MASK_MCS6 = 0x00040000,
+ cbRATE_MASK_MCS7 = 0x00080000,
+ //TX MIMO RATES
+ cbRATE_MASK_MCS8 = 0x00100000,
+ cbRATE_MASK_MCS9 = 0x00200000,
+ cbRATE_MASK_MCS10 = 0x00400000,
+ cbRATE_MASK_MCS11 = 0x00800000,
+ cbRATE_MASK_MCS12 = 0x01000000,
+ cbRATE_MASK_MCS13 = 0x02000000,
+ cbRATE_MASK_MCS14 = 0x04000000,
+ cbRATE_MASK_MCS15 = 0x08000000,
+ //TX RATE USE WIDE CHANNEL
+ cbRATE_MASK_WIDE = 0x80000000
+};
+
+
+/**
+ * Access categories
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_AccessCategory_e {
+ cbWLAN_AC_BK = 1, /**< Background */
+ cbWLAN_AC_SP = 2, /**< Background (Spare) */
+
+ cbWLAN_AC_BE = 0, /**< Best effort */
+ cbWLAN_AC_EE = 3, /**< Best effort (Excellent Effort) */
+
+ cbWLAN_AC_CL = 4, /**< Video (Controlled Load) */
+ cbWLAN_AC_VI = 5, /**< Video */
+
+ cbWLAN_AC_VO = 6, /**< Voice */
+ cbWLAN_AC_NC = 7, /**< Voice (Network Control)*/
+} cbWLAN_AccessCategory;
+
+/**
+* Fast Transition (802.11r) modes.
+*
+* @ingroup wlantypes
+*/
+typedef enum cbWLAN_FTMode_e {
+ cbWLAN_FT_OFF,
+ cbWLAN_FT_OVER_AIR,
+ cbWLAN_FT_OVER_DS,
+} cbWLAN_FTMode;
+/**
+* connectBlue Hardware Identification
+*
+* @ingroup types
+*/
+typedef enum cbWM_ModuleType_e {
+ cbWM_MODULE_UNKNOWN,
+ cbWM_MODULE_OWL22X,
+ cbWM_MODULE_OWL253,
+ cbWM_MODULE_OWS451,
+ cbWM_MODULE_OWL351,
+ cbWM_MODULE_ODIN_W16X = cbWM_MODULE_OWL351,
+ cbWM_MODULE_ODIN_W26X,
+} cbWM_ModuleType;
+
+/**
+ * Mac address type
+ *
+ * @ingroup wlantypes
+ */
+typedef cb_uint8 cbWLAN_MACAddress[6];
+
+/**
+ * Type for containing values found in @ref cbWLAN_RateMask_e
+ * @ingroup wlantypes
+ */
+typedef cb_uint32 cbWLAN_RateMask;
+
+/**
+ * Transmission power
+ *
+ * @ingroup wlantypes
+ */
+typedef cb_uint8 cbWLAN_TxPower;
+
+/**
+ * The different frequency bands to choose from.
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_Band_e {
+ cbWLAN_BAND_UNDEFINED,
+ cbWLAN_BAND_2_4GHz,
+ cbWLAN_BAND_5GHz,
+} cbWLAN_Band;
+
+/**
+ * The operational mode.
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_OperationalMode_e {
+ cbWLAN_OPMODE_MANAGED,
+ cbWLAN_OPMODE_ADHOC,
+} cbWLAN_OperationalMode;
+
+/**
+ * Encryption key type
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_KeyType_e {
+ cbWLAN_KEY_UNICAST,
+ cbWLAN_KEY_BROADCAST,
+ cbWLAN_KEY_IGTK,
+} cbWLAN_KeyType;
+
+typedef enum {
+ cbWLAN_CONNECT_MODE_OPEN,
+ cbWLAN_CONNECT_MODE_WEP_OPEN,
+ cbWLAN_CONNECT_MODE_WPA_PSK,
+ cbWLAN_CONNECT_MODE_ENTERPRISE,
+} cbWLAN_ConnectMode;
+
+typedef enum {
+ cbWLAN_AP_MODE_OPEN,
+ cbWLAN_AP_MODE_WEP_OPEN,
+ cbWLAN_AP_MODE_WPA_PSK,
+ cbWLAN_AP_MODE_ENTERPRISE,
+} cbWLAN_ApMode;
+
+#if defined(CB_FEATURE_802DOT11R)
+/**
+ * Description of the Mobility Domain Information Element
+ *
+ * @ingroup wlantypes
+ */
+
+cb_PACKED_STRUCT_BEGIN(cbWLAN_MDInformation) {
+ cb_uint8 eId;
+ cb_uint8 len;
+ cb_uint16 MDID;
+ cb_uint8 FtCapabilityPolicy;
+} cb_PACKED_STRUCT_END(cbWLAN_MDInformation);
+
+/**
+ * Description of the Timeout Interval Information Element
+ *
+ * @ingroup wlantypes
+ */
+
+cb_PACKED_STRUCT_BEGIN(cbWLAN_TimeOutInformation){
+ cb_uint8 eId;
+ cb_uint8 len;
+ cb_uint8 timeOutType;
+ cb_uint32 value;
+} cb_PACKED_STRUCT_END(cbWLAN_TimeOutInformation);
+
+/**
+ * Description of the Mobility Domain Information Element
+ *
+ * @ingroup wlantypes
+ */
+
+cb_PACKED_STRUCT_BEGIN(cbWLAN_FtInformation){
+ cb_uint8 eId;
+ cb_uint8 len;
+ cb_uint16 micControl;
+ cb_uint8 mic[16];
+ cb_uint8 ANonce[32];
+ cb_uint8 SNonce[32];
+ cb_uint8 optionalParams[174]; // length field can maximum be 256, therefore optional params can be max 172 bytes
+} cb_PACKED_STRUCT_END(cbWLAN_FtInformation);
+
+
+
+typedef struct cbWLAN_BSSChangeParameters {
+ cbWLAN_MACAddress currentBssid; /**< BSSID of connected AP. > */
+ cbWLAN_MACAddress targetBssid; /**< BSSID to connect to. > */
+ cbWLAN_Channel channel; /**< The channel the BSS is located on. > */
+ cb_uint32 reAssocDeadline; /**< Reassociation Deadline time*/
+} cbWLAN_BSSChangeParameters;
+#endif
+
+//#if defined(CB_FEATURE_802DOT11W)
+typedef enum {
+ cbWLAN_PMF_DISABLE = 0, /**< MFPC = 0, MFPR = 0 */
+ cbWLAN_PMF_OPTIONAL = 1, /**< MFPC = 1, MFPR = 0 */
+ cbWLAN_PMF_REQUIRED = 2, /**< MFPC = 1, MFPR = 1 */
+} cbWLAN_PMF;
+//#endif
+typedef enum cbAP_KdeType_e {
+ RESERVED,
+ GTK_KDE,
+ RESERVED_2,
+ MAC_ADDRESS_KDE,
+ PMKID_KDE,
+ SMK_KDE,
+ NONCE_KDE,
+ LIFETIME_KDE,
+ ERROR_KDE,
+ IGTK_KDE,
+ KEY_ID_KDE,
+} cbAP_KdeType;
+
+
+/**
+ * Ethernet header
+ *
+ * @ingroup wlantypes
+ */
+cb_PACKED_STRUCT_BEGIN(cbWLAN_EthernetHeader) {
+ cbWLAN_MACAddress dest;
+ cbWLAN_MACAddress src;
+ cb_uint16 type;
+} cb_PACKED_STRUCT_END(cbWLAN_EthernetHeader);
+
+
+cb_PACKED_STRUCT_BEGIN(cbWLAN_EthernetFrame) {
+ cbWLAN_EthernetHeader header;
+ cb_uint8 payload[cb_EMPTY_ARRAY];
+} cb_PACKED_STRUCT_END(cbWLAN_EthernetFrame);
+
+/**
+ * SNAP header
+ *
+ * @ingroup wlantypes
+ */
+cb_PACKED_STRUCT_BEGIN(cbWLAN_SNAPHeader) {
+ cb_uint8 dsap;
+ cb_uint8 ssap;
+ cb_uint8 ctrl;
+ cb_uint8 encapsulation[3];
+ cb_uint16 ethType;
+} cb_PACKED_STRUCT_END(cbWLAN_SNAPHeader);
+
+cb_PACKED_STRUCT_BEGIN(cbWLAN_SNAPFrame) {
+ cbWLAN_SNAPHeader header;
+ cb_uint8 payload[cb_EMPTY_ARRAY];
+} cb_PACKED_STRUCT_END(cbWLAN_SNAPFrame);
+
+
+/**
+ * Defines an ssid.
+ *
+ * @ingroup wlantypes
+ */
+typedef struct cbWLAN_Ssid_s {
+ cb_uint8 ssid[cbWLAN_SSID_MAX_LENGTH];
+ cb_uint32 ssidLength;
+} cbWLAN_Ssid;
+
+/**
+ * Defines one wep key.
+ *
+ * @ingroup wlantypes
+ */
+typedef struct cbWLAN_WepKey_s {
+ cb_uint8 key[cbWLAN_KEY_SIZE_WEP_MAX];
+ cb_uint32 length;
+} cbWLAN_WEPKey;
+
+/**
+ * Describes host revisions.
+ * @see cbWM_Version
+ *
+ * @ingroup types
+ */
+typedef struct {
+ struct {
+ cb_uint32 major;
+ cb_uint32 minor;
+ cb_uint32 patch1;
+ } software;
+ struct {
+ const char* id;
+ } manufacturer;
+} cbWM_DriverRevision;
+
+/**
+ * Describes firmware revisions.
+ * @see cbWM_Version
+ *
+ * @ingroup types
+ */
+typedef struct {
+ struct {
+ cb_uint32 major;
+ cb_uint32 minor;
+ cb_uint32 patch1;
+ cb_uint32 patch2;
+ } firmware;
+ struct {
+ const char* id;
+ } manufacturer;
+} cbWM_FWRevision;
+
+/**
+ * Describes firmware revisions. Is divided into three parts; one for the
+ * host driver side, one for target firmware, and one information string
+ * descibing the HW manufacturer.
+ *
+ * @ingroup types
+ */
+typedef struct version_st{
+ cbWM_DriverRevision host;
+ cbWM_FWRevision target;
+} cbWM_Version;
+
+/**
+ * Describes power levels for dynamic power level control.
+ *
+ * @ingroup types
+ */
+typedef struct cbWM_TxPowerSettings_s {
+ cbWLAN_TxPower lowTxPowerLevel;
+ cbWLAN_TxPower medTxPowerLevel;
+ cbWLAN_TxPower maxTxPowerLevel;
+} cbWM_TxPowerSettings;
+
+/**
+ * Describes the startup settings needed to boot properly.
+ *
+ * @ingroup types
+ */
+typedef struct cbWM_BootParameters_s {
+ cbWM_TxPowerSettings txPowerSettings;
+ cb_uint8 primaryAntenna;
+ cb_uint8 numberOfAntennas;
+} cbWM_BootParameters;
+
+/**
+ * Describes an access point.
+ *
+ * @ingroup types
+ */
+typedef struct cbWLAN_ApInformation {
+ cbWLAN_Ssid ssid; /**< SSID */
+ cbWLAN_MACAddress bssid; /**< BSSID */
+ cbWLAN_Channel channel; /**< Channel */
+} cbWLAN_ApInformation;
+
+/**
+ * Describes a station connected to an access point.
+ *
+ * @ingroup types
+ */
+typedef struct cbWLAN_ApStaInformation {
+ cbWLAN_MACAddress MAC;
+} cbWLAN_ApStaInformation;
+
+typedef struct cbWLAN_HTCapabilities_st {
+ cbWLAN_RateMask rates;
+ cb_uint16 info;
+} cbWLAN_HTCapabilities;
+/*---------------------------------------------------------------------------
+ * VARIABLE DECLARATIONS
+ *-------------------------------------------------------------------------*/
+extern const cbWLAN_MACAddress nullMac;
+extern const cbWLAN_MACAddress broadcastMac;
+
+extern const cb_uint8 OUI_Microsoft[cbWLAN_OUI_SIZE];
+extern const cb_uint8 OUI_Epigram[cbWLAN_OUI_SIZE];
+extern const cb_uint8 OUI_ConnectBlue[cbWLAN_OUI_SIZE];
+extern const cb_uint8 OUI_IEEE8021[cbWLAN_OUI_SIZE];
+
+extern const cb_uint8 PATTERN_TKIP[2];
+extern const cb_uint8 PATTERN_WME_IE[3];
+extern const cb_uint8 PATTERN_WME_PE[3];
+
+/*---------------------------------------------------------------------------
+ * FUNCTIONS
+ *-------------------------------------------------------------------------*/
+
+/**
+ * Misc
+ */
+
+/**
+ * Returns the correct frequency @ref cbWLAN_Band band based on the input channel.
+ *
+ * For @ref cbWLAN_CHANNEL_ALL This function will return @ref cbWLAN_BAND_2_4GHz.
+ *
+ * @param channel The channel to be queried for band.
+ * @return The @ref cbWLAN_Band band for the requested channel.
+ */
+cbWLAN_Band cbWLAN_getBandFromChannel(cbWLAN_Channel channel);
+
+/**
+ * Returns the valid rates @ref cbWLAN_RateMask based for the channel.
+ *
+ * @param channel The channel to be queried for rates.
+ * @return The valid rates @ref cbWLAN_RateMask for the requested channel.
+ */
+cbWLAN_RateMask cbWLAN_getRatesForChannel(cbWLAN_Channel channel, cb_uint8 numberOfAntennas);
+
+/**
+ * Checks is the input rate is a 802.11n rate or not.
+ *
+ * @param rate The rate to check
+ * @return @ref TRUE if the input rate is an n-rate. @ref FALSE otherwise.
+ */
+cb_boolean cbWLAN_isNRate(cbWLAN_Rate rate);
+
+/**
+ * Checks if a channel is valid
+ *
+ * @return @ref TRUE if the channel is valid. @ref FALSE otherwise.
+ */
+cb_boolean cbWLAN_isValidChannel(cbWLAN_Channel channel);
+
+/**
+ * Checks if a channel is valid for HT40-
+ *
+ * @return @ref TRUE if the channel is valid. @ref FALSE otherwise.
+ */
+cb_boolean cbWLAN_isValidHT40MinusChannel(cbWLAN_Channel channel);
+
+/**
+ * Checks if a channel is valid for HT40+
+ *
+ * @return @ref TRUE if the channel is valid. @ref FALSE otherwise.
+ */
+cb_boolean cbWLAN_isValidHT40PlusChannel(cbWLAN_Channel channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/default_wifi_interface.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/default_wifi_interface.cpp Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, Arm Limited and affiliates.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "OdinWiFiInterface.h"
+
+WiFiInterface *WiFiInterface::get_target_default_instance()
+{
+ static OdinWiFiInterface wifi;
+ return &wifi;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *--------------------------------------------------------------------------------------
+ * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL
+ * | (external 8 MHz clock) | (external 8 MHz clock)
+ *--------------------------------------------------------------------------------------
+ * SYSCLK(MHz) | 168 | 180
+ *--------------------------------------------------------------------------------------
+ * AHBCLK (MHz) | 168 | 180
+ *--------------------------------------------------------------------------------------
+ * APB1CLK (MHz) | 42 | 45
+ *--------------------------------------------------------------------------------------
+ * APB2CLK (MHz) | 84 | 90
+ *--------------------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | NO
+ *--------------------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "nvic_addr.h"
+
+
+/* Select the SYSCLOCK to start with (0=OFF, 1=ON) */
+#define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */
+#define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */
+
+
+void SetSysClock(void);
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/** System Clock Configuration
+*/
+#if USE_SYSCLOCK_168 != 0
+/*
+ * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
+ * and SYSCLK=168MHZ
+ */
+void SetSysClock(void)
+{
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 24;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
+ | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+
+}
+
+#elif USE_SYSCLOCK_180 != 0
+/*
+ * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
+ * and SYSCLK=180MHZ
+ */
+void SetSysClock(void)
+{
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+ RCC_OscInitStruct.PLL.PLLN = 360;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ HAL_PWREx_EnableOverDrive();
+
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
+ | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+}
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE,
+ SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,362 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0
+ {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
+ {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to LD1
+ {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to LD1
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
+ {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC]
+ {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC]
+ {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC]
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+ {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
+ {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to RMII_RXD0 [LAN8742A-CZ-TR_RXD0]
+ {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to RMII_RXD0 [LAN8742A-CZ-TR_RXD0]
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to RMII_RXD1 [LAN8742A-CZ-TR_RXD1]
+ {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to RMII_RXD1 [LAN8742A-CZ-TR_RXD1]
+ {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9
+ {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14
+ {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15
+ {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
+ {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5
+ {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
+ {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
+ {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue]
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to USB_SOF [TP1]
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_SOF [TP1]
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD1
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LD1
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD1
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD2 [Blue]
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LD3 [Red]
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX
+ {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue]
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX
+ {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red]
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to RMII_TXD0 [LAN8742A-CZ-TR_TXD0]
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red]
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to RMII_TXD0 [LAN8742A-CZ-TR_TXD0]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,356 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_0_ALT0 = PA_0 | ALT0,
+ PA_0_ALT1 = PA_0 | ALT1,
+ PA_1 = 0x01,
+ PA_1_ALT0 = PA_1 | ALT0,
+ PA_1_ALT1 = PA_1 | ALT1,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_2_ALT1 = PA_2 | ALT1,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_3_ALT1 = PA_3 | ALT1,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_5_ALT1 = PA_5 | ALT1,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_0_ALT0 = PC_0 | ALT0,
+ PC_0_ALT1 = PC_0 | ALT1,
+ PC_1 = 0x21,
+ PC_1_ALT0 = PC_1 | ALT0,
+ PC_1_ALT1 = PC_1 | ALT1,
+ PC_2 = 0x22,
+ PC_2_ALT0 = PC_2 | ALT0,
+ PC_2_ALT1 = PC_2 | ALT1,
+ PC_3 = 0x23,
+ PC_3_ALT0 = PC_3 | ALT0,
+ PC_3_ALT1 = PC_3 | ALT1,
+ PC_4 = 0x24,
+ PC_4_ALT0 = PC_4 | ALT0,
+ PC_5 = 0x25,
+ PC_5_ALT0 = PC_5 | ALT0,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_10_ALT0 = PC_10 | ALT0,
+ PC_11 = 0x2B,
+ PC_11_ALT0 = PC_11 | ALT0,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_3,
+ A1 = PC_0,
+ A2 = PC_3,
+ A3 = PF_3,
+ A4 = PF_5,
+ A5 = PF_10,
+ D0 = PG_9,
+ D1 = PG_14,
+ D2 = PF_15,
+ D3 = PE_13,
+ D4 = PF_14,
+ D5 = PE_11,
+ D6 = PE_9,
+ D7 = PF_13,
+ D8 = PF_12,
+ D9 = PD_15,
+ D10 = PD_14,
+ D11 = STM32_D11_SPI_ETHERNET_PIN, /* config in targets.json file */
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PD_8,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PD_9,
+#endif
+
+ // Generic signals namings
+ LED1 = PB_0, // LD1 = GREEN
+ LED2 = PB_7, // Blue
+ LED3 = PB_14, // Red
+ LED4 = PB_0,
+ LED_RED = LED2,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX, // Virtual Com Port
+ SERIAL_RX = STDIO_UART_RX, // Virtual Com Port
+ USBTX = STDIO_UART_TX, // Virtual Com Port
+ USBRX = STDIO_UART_RX, // Virtual Com Port
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ PWM_OUT = D9,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_HS_DM = PB_14,
+ USB_OTG_HS_DP = PB_15,
+ USB_OTG_HS_ID = PB_12,
+ USB_OTG_HS_SOF = PA_4,
+ USB_OTG_HS_ULPI_CK = PA_5,
+ USB_OTG_HS_ULPI_D0 = PA_3,
+ USB_OTG_HS_ULPI_D1 = PB_0,
+ USB_OTG_HS_ULPI_D2 = PB_1,
+ USB_OTG_HS_ULPI_D3 = PB_10,
+ USB_OTG_HS_ULPI_D4 = PB_11,
+ USB_OTG_HS_ULPI_D5 = PB_12,
+ USB_OTG_HS_ULPI_D6 = PB_13,
+ USB_OTG_HS_ULPI_D7 = PB_5,
+ USB_OTG_HS_ULPI_DIR = PC_2,
+ USB_OTG_HS_ULPI_NXT = PC_3,
+ USB_OTG_HS_ULPI_STP = PC_0,
+ USB_OTG_HS_VBUS = PB_13,
+
+ /**** ETHERNET pins ****/
+ ETH_COL = PA_3,
+ ETH_CRS = PA_0,
+ ETH_CRS_DV = PA_7,
+ ETH_MDC = PC_1,
+ ETH_MDIO = PA_2,
+ ETH_PPS_OUT = PG_8,
+ ETH_PPS_OUT_ALT0 = PB_5,
+ ETH_REF_CLK = PA_1,
+ ETH_RXD0 = PC_4,
+ ETH_RXD1 = PC_5,
+ ETH_RXD2 = PB_0,
+ ETH_RXD3 = PB_1,
+ ETH_RX_CLK = PA_1,
+ ETH_RX_DV = PA_7,
+ ETH_RX_ER = PB_10,
+ ETH_TXD0 = PB_12,
+ ETH_TXD0_ALT0 = PG_13,
+ ETH_TXD1 = PB_13,
+ ETH_TXD1_ALT0 = PG_14,
+ ETH_TXD2 = PC_2,
+ ETH_TXD3 = PE_2,
+ ETH_TXD3_ALT0 = PB_8,
+ ETH_TX_CLK = PC_3,
+ ETH_TX_EN = PB_11,
+ ETH_TX_EN_ALT0 = PG_11,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED3 = PE_6,
+ SYS_WKUP = PA_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,244 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (CLOCK_SOURCE_USB=1) | 3- USE_PLL_HSI (CLOCK_SOURCE_USB=1)
+ * | (external 8 MHz clock) | (internal 16 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------------
+ * SYSCLK(MHz) | 180 (168)
+ *-----------------------------------------------------------------------------------
+ * AHBCLK (MHz) | 180 (168)
+ *-----------------------------------------------------------------------------------
+ * APB1CLK (MHz) | 45 (42)
+ *-----------------------------------------------------------------------------------
+ * APB2CLK (MHz) | 90 (84)
+ *-----------------------------------------------------------------------------------
+ * USB capable (48 MHz) | YES (HSI calibration needed)
+ *-----------------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "nvic_addr.h"
+#include "mbed_error.h"
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 336;
+#else
+ RCC_OscInitStruct.PLL.PLLN = 360;
+#endif
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
+ RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+ return 1;
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 168;
+#else
+ RCC_OscInitStruct.PLL.PLLN = 180;
+#endif
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
+ RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+ return 1;
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE,
+ SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,352 @@
+/* mbed Microcontroller Library
+ '*******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+// {PA_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0
+// {PA_0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0
+// {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 (pin used by ethernet)
+// {PA_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 (pin used by ethernet)
+// {PA_1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 (pin used by ethernet)
+// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 (pin used by ethernet)
+// {PA_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 (pin used by ethernet)
+// {PA_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 (pin used by ethernet)
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - ARDUINO A0
+// {PA_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - ARDUINO A0
+// {PA_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 - ARDUINO A0
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+// {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - ARDUINO D13
+// {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - ARDUINO D13
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - ARDUINO D12
+// {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO D12
+// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
+ {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
+// {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 (pin used by LED1)
+// {PB_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 (pin used by LED1)
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+// {PB_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - ARDUINO A1
+// {PC_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - ARDUINO A1
+// {PC_0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 - ARDUINO A1
+// {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 (pin used by ethernet)
+// {PC_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 (pin used by ethernet)
+// {PC_1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 (pin used by ethernet)
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+// {PC_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+// {PC_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - ARDUINO A2
+// {PC_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - ARDUINO A2
+// {PC_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 - ARDUINO A2
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 (pin used by ethernet when JP6 ON)
+// {PC_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 (pin used by ethernet when JP6 ON)
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 (pin used by ethernet when JP6 ON)
+// {PC_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 (pin used by ethernet when JP6 ON)
+ {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 - ARDUINO A3
+ {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14
+ {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 - ARDUINO A4
+ {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
+ {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5
+ {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
+ {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
+ {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 - ARDUINO D13
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+// {PB_7, I2C_1 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // (pin used by LED2)
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D15
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 (TIM5 used by us_ticker)
+// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 (pin used by ethernet)
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 (TIM5 used by us_ticker) (pin used by ethernet)
+// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 (pin used by ethernet)
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 (TIM5 used by us_ticker)
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 (pin used by ethernet)
+// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - ARDUINO A0
+ {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 (TIM5 used by us_ticker) - ARDUINO A0
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - ARDUINO A0
+// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - ARDUINO D13
+ {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - ARDUINO D13
+// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO D12
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D12
+ {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
+// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
+// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration)
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 (pin used by usb)
+// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 (pin used by usb)
+// {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 (pin used by usb)
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N (pin used by LED1)
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 (pin used by LED1)
+// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N (pin used by LED1)
+// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 (need HW and SW updates)
+ // HW solder bridge update : SB121 off, SB122 on
+ // SW : config from json files
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (pin used by LED2)
+// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D15
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO D15
+ {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - ARDUINO D14
+// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO D14
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP7 ON)
+// {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 (pin used by LED3)
+// {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N (pin used by LED3)
+// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N (pin used by LED3)
+ {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+// {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO D10
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO D9
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - ARDUINO D6
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - ARDUINO D5
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - ARDUINO D3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // (pin used by ethernet)
+// {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (pin used by usb)
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+// {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+// {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // (pin used by ethernet)
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+// {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (pin used by usb)
+// {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (pin used by LED2)
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)},
+ {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D0
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // (pin used by ethernet)
+// {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (pin used by usb)
+// {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // (pin used by LED3)
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+// {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (pin used by usb)
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // (pin used by ethernet when JP7 ON)
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+// {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // (pin used by ethernet)
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // pin used by ethernet when JP6 ON - ARDUINO D11 (default configuration)
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11 (need HW and SW updates)
+ // HW solder bridge update : SB121 off, SB122 on
+ // SW : config from json files
+// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO A2
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+ {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+ {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, // ARDUINO D1
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // (pin used by LED3)
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // ARDUINO D3
+ {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+ {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // (pin used by ethernet when JP7 ON)
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+// {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, // (pin used by ethernet)
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO D14
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // ARDUINO D5
+ {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)},
+ {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // ARDUINO D11 (need HW and SW updates)
+ // HW solder bridge update : SB121 off, SB122 on
+ // SW : config from json files
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Grove connector namings
+ D38 = PC_6,
+ D39 = PC_7,
+ A4 = PA_4,
+ A5 = PA_5,
+ A6 = PA_6,
+ A7 = PA_7,
+ TXD = PB_6,
+ RXD = PB_7,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PD_8,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PD_9,
+#endif
+
+
+ // Quectel UG96 cellular modem
+ MDMTXD = PA_2,
+ MDMRXD = PA_3,
+ MDMCTS = PA_0,
+ MDMRTS = PA_1,
+
+ MDMSTAT = PB_15,
+ MDMDTR = PC_5,
+ M_POWR = PE_9,
+
+ /*
+ MDMDCD = NC, // Data Carrier Detect
+ MDMDSR = NC, // Data Set Ready
+ MDMRI = NC, // Ring Indicator
+ */
+
+ // Internal control signals
+ RGB_POWR = PE_8,
+ GRO_POWR = PB_10,
+ PWRKEY = PB_5,
+ RESET_MODULE = PD_5,
+
+ // Generic signals namings
+ LED1 = PB_11, // LD1 = GREEN
+ LED2 = PB_12, // Blue
+ LED3 = PB_13, // Red
+ LED4 = PB_14,
+ LED_RED = LED2,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = PC_13,
+ SERIAL_TX = STDIO_UART_TX, // Virtual Com Port
+ SERIAL_RX = STDIO_UART_RX, // Virtual Com Port
+ USBTX = STDIO_UART_TX, // Virtual Com Port
+ USBRX = STDIO_UART_RX, // Virtual Com Port
+ SPI_MOSI = PC_12,
+ SPI_MISO = PC_11,
+ SPI_SCK = PC_10,
+ SPI_CS = PD_0,
+ PWM_OUT = D39,
+
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/onboard_modem_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/onboard_modem_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if MBED_CONF_NSAPI_PRESENT
+
+#include "cellular/onboard_modem_api.h"
+#include "gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "PinNames.h"
+
+#if MODEM_ON_BOARD
+
+static void press_power_button(int time_ms)
+{
+ gpio_t gpio;
+
+ gpio_init_out_ex(&gpio, PWRKEY, 1);
+ gpio_write(&gpio, 1);
+ wait_ms(time_ms);
+ gpio_write(&gpio, 0);
+}
+
+void onboard_modem_init()
+{
+ gpio_t gpio;
+ // start with modem disabled
+ gpio_init_out_ex(&gpio, RESET_MODULE, 0);
+ gpio_init_in_ex(&gpio, MDMSTAT, PullUp);
+ gpio_init_out_ex(&gpio, MDMDTR, 0);
+ gpio_init_out_ex(&gpio, M_POWR, 1);
+
+// gpio_write(&gpio, M_POWR, 1);
+ wait_ms(500);
+}
+
+void onboard_modem_deinit()
+{
+// wio3g_mdm_powerOff();
+}
+
+void onboard_modem_power_up()
+{
+ /* keep the power line HIGH for 200 milisecond */
+ press_power_button(200);
+ /* give modem a little time to respond */
+ wait_ms(100);
+}
+
+void onboard_modem_power_down()
+{
+ /* keep the power line low for 1 second */
+// press_power_button(1000);
+
+// gpio_write(&mpowr, M_POWR, 0);
+}
+#endif //MODEM_ON_BOARD
+#endif //MBED_CONF_NSAPI_PRESENT
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,244 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2018 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (CLOCK_SOURCE_USB=1) | 3- USE_PLL_HSI (CLOCK_SOURCE_USB=1)
+ * | (external 8 MHz clock) | (internal 16 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------------
+ * SYSCLK(MHz) | 180 (168)
+ *-----------------------------------------------------------------------------------
+ * AHBCLK (MHz) | 180 (168)
+ *-----------------------------------------------------------------------------------
+ * APB1CLK (MHz) | 45 (42)
+ *-----------------------------------------------------------------------------------
+ * APB2CLK (MHz) | 90 (84)
+ *-----------------------------------------------------------------------------------
+ * USB capable (48 MHz) | YES (HSI calibration needed)
+ *-----------------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "nvic_addr.h"
+#include "mbed_error.h"
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 336;
+#else
+ RCC_OscInitStruct.PLL.PLLN = 360;
+#endif
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
+ RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+ return 1;
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 168;
+#else
+ RCC_OscInitStruct.PLL.PLLN = 180;
+#endif
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
+ RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+ return 1;
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,443 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20030000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,57 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+; STM32F439xI: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 107 vectors = 428 bytes (0x1AC) to be used
+ ; should match ER_IROM1::RESET/4 and cmsis_nvic.h::NVIC_NUM_VECTORS
+ RW_IRAM1 (0x20000000 + (107*4)) (0x30000 - (107*4)) { ; RW data
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 (0x10000000) 0x10000 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,416 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20030000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/stm32f439xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/stm32f439xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,57 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+; 2 MB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ RW_IRAM2 (0x10000000) (0x10000) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,162 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 2048k
+#endif
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x200001AC, LENGTH = 192k - 0x1AC
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,573 @@ +/** + ****************************************************************************** + * @file startup_stm32f439xx.s + * @author MCD Application Team + * @brief STM32F439xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + + + +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_IAR/startup_stm32f439xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_IAR/startup_stm32f439xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,696 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Description : STM32F439xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_IAR/stm32f439xx_flash.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_IAR/stm32f439xx_flash.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; }
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x200001AF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200001B0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
+/*-Sizes-*/
+/*Heap 89kB and stack 1kB */
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x15C00;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F439xI +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB +// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM +#define NVIC_NUM_VECTORS 107 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Flash Size */ +#define FLASH_SIZE (uint32_t) 0x200000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +/* Base address of the Flash sectors Bank 2 */ +#define ADDR_FLASH_SECTOR_12 ((uint32_t)0x08100000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_13 ((uint32_t)0x08104000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_14 ((uint32_t)0x08108000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_15 ((uint32_t)0x0810C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_16 ((uint32_t)0x08110000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_17 ((uint32_t)0x08120000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_18 ((uint32_t)0x08140000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_19 ((uint32_t)0x08160000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_20 ((uint32_t)0x08180000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_21 ((uint32_t)0x081A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_22 ((uint32_t)0x081C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_23 ((uint32_t)0x081E0000) /* Base @ of Sector 11, 128 Kbytes */ + + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,17421 @@
+/**
+ ******************************************************************************
+ * @file stm32f439xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f439xx
+ * @{
+ */
+
+#ifndef __STM32F439xx_H
+#define __STM32F439xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1;
+ __IO uint32_t MACDBGR;
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
+} LTDC_Layer_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC123_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC123_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2_Pos (8U)
+#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos (9U)
+#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos (10U)
+#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos (11U)
+#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos (12U)
+#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos (13U)
+#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3_Pos (16U)
+#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos (17U)
+#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos (18U)
+#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos (19U)
+#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos (20U)
+#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos (21U)
+#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos (14U)
+#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos (15U)
+#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos (16U)
+#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos (17U)
+#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos (18U)
+#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos (19U)
+#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos (20U)
+#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos (21U)
+#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos (22U)
+#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos (23U)
+#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos (24U)
+#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos (25U)
+#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos (26U)
+#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos (27U)
+#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+#define CRYP_CR_ALGODIR_Pos (2U)
+#define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
+#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
+
+#define CRYP_CR_ALGOMODE_Pos (3U)
+#define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
+#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
+#define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
+#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
+#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
+#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
+#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
+#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
+#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
+#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
+#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
+#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
+#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
+#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
+#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
+#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
+#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
+#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
+#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
+
+#define CRYP_CR_DATATYPE_Pos (6U)
+#define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
+#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
+#define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
+#define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
+#define CRYP_CR_KEYSIZE_Pos (8U)
+#define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
+#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
+#define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
+#define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
+#define CRYP_CR_FFLUSH_Pos (14U)
+#define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
+#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
+#define CRYP_CR_CRYPEN_Pos (15U)
+#define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
+#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
+
+#define CRYP_CR_GCM_CCMPH_Pos (16U)
+#define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
+#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
+#define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
+#define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
+#define CRYP_CR_ALGOMODE_3 0x00080000U
+
+/****************** Bits definition for CRYP_SR register *********************/
+#define CRYP_SR_IFEM_Pos (0U)
+#define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
+#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
+#define CRYP_SR_IFNF_Pos (1U)
+#define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
+#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
+#define CRYP_SR_OFNE_Pos (2U)
+#define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
+#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
+#define CRYP_SR_OFFU_Pos (3U)
+#define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
+#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
+#define CRYP_SR_BUSY_Pos (4U)
+#define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
+#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
+/****************** Bits definition for CRYP_DMACR register ******************/
+#define CRYP_DMACR_DIEN_Pos (0U)
+#define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
+#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
+#define CRYP_DMACR_DOEN_Pos (1U)
+#define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
+#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
+/***************** Bits definition for CRYP_IMSCR register ******************/
+#define CRYP_IMSCR_INIM_Pos (0U)
+#define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
+#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
+#define CRYP_IMSCR_OUTIM_Pos (1U)
+#define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
+#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
+/****************** Bits definition for CRYP_RISR register *******************/
+#define CRYP_RISR_OUTRIS_Pos (0U)
+#define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
+#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
+#define CRYP_RISR_INRIS_Pos (1U)
+#define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
+#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
+/****************** Bits definition for CRYP_MISR register *******************/
+#define CRYP_MISR_INMIS_Pos (0U)
+#define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
+#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
+#define CRYP_MISR_OUTMIS_Pos (1U)
+#define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
+#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE_Pos (0U)
+#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos (1U)
+#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
+#define DCMI_CR_CM DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos (2U)
+#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos (3U)
+#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos (4U)
+#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos (5U)
+#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos (6U)
+#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos (7U)
+#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_ENABLE_Pos (14U)
+#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC_Pos (0U)
+#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos (1U)
+#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos (2U)
+#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS_Pos (0U)
+#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos (1U)
+#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos (2U)
+#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos (4U)
+#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE_Pos (0U)
+#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos (1U)
+#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos (2U)
+#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos (3U)
+#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos (4U)
+#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS_Pos (0U)
+#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos (1U)
+#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos (2U)
+#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos (4U)
+#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC_Pos (0U)
+#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos (1U)
+#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos (2U)
+#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos (4U)
+#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC_Pos (0U)
+#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos (8U)
+#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos (16U)
+#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos (24U)
+#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU_Pos (0U)
+#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos (8U)
+#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos (16U)
+#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos (24U)
+#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos (16U)
+#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos (16U)
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
+
+/******************** Bits definition for DCMI_DR register *********************/
+#define DCMI_DR_BYTE0_Pos (0U)
+#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos (8U)
+#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos (16U)
+#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos (24U)
+#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START_Pos (0U)
+#define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
+#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos (1U)
+#define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
+#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos (2U)
+#define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
+#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
+#define DMA2D_CR_TEIE_Pos (8U)
+#define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
+#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos (9U)
+#define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
+#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos (10U)
+#define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
+#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos (11U)
+#define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos (12U)
+#define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos (13U)
+#define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
+#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos (16U)
+#define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
+#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF_Pos (0U)
+#define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos (1U)
+#define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos (2U)
+#define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos (3U)
+#define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos (4U)
+#define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos (5U)
+#define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos (0U)
+#define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos (1U)
+#define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos (2U)
+#define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos (3U)
+#define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos (4U)
+#define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos (5U)
+#define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA_Pos (0U)
+#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO_Pos (0U)
+#define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA_Pos (0U)
+#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO_Pos (0U)
+#define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM_Pos (0U)
+#define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos (4U)
+#define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos (5U)
+#define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos (8U)
+#define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos (16U)
+#define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos (0U)
+#define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos (8U)
+#define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos (16U)
+#define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM_Pos (0U)
+#define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM_Pos (4U)
+#define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos (5U)
+#define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos (8U)
+#define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos (16U)
+#define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos (0U)
+#define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos (8U)
+#define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos (16U)
+#define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA_Pos (0U)
+#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA_Pos (0U)
+#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM_Pos (0U)
+#define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA_Pos (0U)
+#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO_Pos (0U)
+#define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL_Pos (0U)
+#define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos (16U)
+#define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW_Pos (0U)
+#define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN_Pos (0U)
+#define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos (8U)
+#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_MER2_Pos (15U)
+#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_BFB2_Pos (4U)
+#define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
+#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M_Pos (30U)
+#define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
+#define FLASH_OPTCR_SPRMOD_Pos (31U)
+#define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN_Pos (0U)
+#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN_Pos (1U)
+#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP_Pos (2U)
+#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR1_MWID_Pos (4U)
+#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR1_FACCEN_Pos (6U)
+#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN_Pos (8U)
+#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL_Pos (9U)
+#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD_Pos (10U)
+#define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG_Pos (11U)
+#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR1_WREN_Pos (12U)
+#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR1_WAITEN_Pos (13U)
+#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD_Pos (14U)
+#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE_Pos (16U)
+#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR1_CBURSTRW_Pos (19U)
+#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN_Pos (0U)
+#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN_Pos (1U)
+#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP_Pos (2U)
+#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR2_MWID_Pos (4U)
+#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR2_FACCEN_Pos (6U)
+#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN_Pos (8U)
+#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL_Pos (9U)
+#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD_Pos (10U)
+#define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG_Pos (11U)
+#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR2_WREN_Pos (12U)
+#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR2_WAITEN_Pos (13U)
+#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD_Pos (14U)
+#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR2_CPSIZE_Pos (16U)
+#define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR2_CBURSTRW_Pos (19U)
+#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN_Pos (0U)
+#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN_Pos (1U)
+#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP_Pos (2U)
+#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR3_MWID_Pos (4U)
+#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR3_FACCEN_Pos (6U)
+#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN_Pos (8U)
+#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL_Pos (9U)
+#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD_Pos (10U)
+#define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG_Pos (11U)
+#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR3_WREN_Pos (12U)
+#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR3_WAITEN_Pos (13U)
+#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD_Pos (14U)
+#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR3_CPSIZE_Pos (16U)
+#define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR3_CBURSTRW_Pos (19U)
+#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN_Pos (0U)
+#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN_Pos (1U)
+#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP_Pos (2U)
+#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR4_MWID_Pos (4U)
+#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR4_FACCEN_Pos (6U)
+#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN_Pos (8U)
+#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL_Pos (9U)
+#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD_Pos (10U)
+#define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG_Pos (11U)
+#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR4_WREN_Pos (12U)
+#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR4_WAITEN_Pos (13U)
+#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD_Pos (14U)
+#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR4_CPSIZE_Pos (16U)
+#define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR4_CBURSTRW_Pos (19U)
+#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET_Pos (0U)
+#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR1_ADDHLD_Pos (4U)
+#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR1_DATAST_Pos (8U)
+#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR1_BUSTURN_Pos (16U)
+#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR1_CLKDIV_Pos (20U)
+#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR1_DATLAT_Pos (24U)
+#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR1_ACCMOD_Pos (28U)
+#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET_Pos (0U)
+#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR2_ADDHLD_Pos (4U)
+#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR2_DATAST_Pos (8U)
+#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR2_BUSTURN_Pos (16U)
+#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR2_CLKDIV_Pos (20U)
+#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR2_DATLAT_Pos (24U)
+#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR2_ACCMOD_Pos (28U)
+#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET_Pos (0U)
+#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR3_ADDHLD_Pos (4U)
+#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR3_DATAST_Pos (8U)
+#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR3_BUSTURN_Pos (16U)
+#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR3_CLKDIV_Pos (20U)
+#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR3_DATLAT_Pos (24U)
+#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR3_ACCMOD_Pos (28U)
+#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET_Pos (0U)
+#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR4_ADDHLD_Pos (4U)
+#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR4_DATAST_Pos (8U)
+#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR4_BUSTURN_Pos (16U)
+#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR4_CLKDIV_Pos (20U)
+#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR4_DATLAT_Pos (24U)
+#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR4_ACCMOD_Pos (28U)
+#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET_Pos (0U)
+#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR1_ADDHLD_Pos (4U)
+#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR1_DATAST_Pos (8U)
+#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR1_BUSTURN_Pos (16U)
+#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR1_ACCMOD_Pos (28U)
+#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET_Pos (0U)
+#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR2_ADDHLD_Pos (4U)
+#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR2_DATAST_Pos (8U)
+#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR2_BUSTURN_Pos (16U)
+#define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR2_ACCMOD_Pos (28U)
+#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET_Pos (0U)
+#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR3_ADDHLD_Pos (4U)
+#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR3_DATAST_Pos (8U)
+#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR3_BUSTURN_Pos (16U)
+#define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR3_ACCMOD_Pos (28U)
+#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET_Pos (0U)
+#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR4_ADDHLD_Pos (4U)
+#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR4_DATAST_Pos (8U)
+#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR4_BUSTURN_Pos (16U)
+#define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR4_ACCMOD_Pos (28U)
+#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+
+#define FMC_PCR2_PWAITEN_Pos (1U)
+#define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN_Pos (2U)
+#define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP_Pos (3U)
+#define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR2_PWID_Pos (4U)
+#define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR2_ECCEN_Pos (6U)
+#define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR_Pos (9U)
+#define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR2_TAR_Pos (13U)
+#define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR2_ECCPS_Pos (17U)
+#define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN_Pos (1U)
+#define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN_Pos (2U)
+#define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP_Pos (3U)
+#define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR3_PWID_Pos (4U)
+#define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR3_ECCEN_Pos (6U)
+#define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR_Pos (9U)
+#define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR3_TAR_Pos (13U)
+#define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR3_ECCPS_Pos (17U)
+#define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN_Pos (1U)
+#define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN_Pos (2U)
+#define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP_Pos (3U)
+#define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR4_PWID_Pos (4U)
+#define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR4_ECCEN_Pos (6U)
+#define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR_Pos (9U)
+#define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR4_TAR_Pos (13U)
+#define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR4_ECCPS_Pos (17U)
+#define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS_Pos (0U)
+#define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS_Pos (1U)
+#define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR2_IFS_Pos (2U)
+#define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN_Pos (3U)
+#define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN_Pos (4U)
+#define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN_Pos (5U)
+#define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT_Pos (6U)
+#define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS_Pos (0U)
+#define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS_Pos (1U)
+#define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR3_IFS_Pos (2U)
+#define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN_Pos (3U)
+#define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN_Pos (4U)
+#define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN_Pos (5U)
+#define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT_Pos (6U)
+#define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS_Pos (0U)
+#define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS_Pos (1U)
+#define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR4_IFS_Pos (2U)
+#define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN_Pos (3U)
+#define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN_Pos (4U)
+#define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN_Pos (5U)
+#define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT_Pos (6U)
+#define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2_Pos (0U)
+#define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
+#define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
+#define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
+#define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
+#define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
+#define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
+#define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
+#define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
+#define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM2_MEMWAIT2_Pos (8U)
+#define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM2_MEMHOLD2_Pos (16U)
+#define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM2_MEMHIZ2_Pos (24U)
+#define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3_Pos (0U)
+#define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
+#define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
+#define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
+#define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
+#define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
+#define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
+#define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
+#define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
+#define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM3_MEMWAIT3_Pos (8U)
+#define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
+#define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
+#define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
+#define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
+#define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
+#define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
+#define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
+#define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM3_MEMHOLD3_Pos (16U)
+#define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
+#define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
+#define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
+#define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
+#define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
+#define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
+#define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
+#define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM3_MEMHIZ3_Pos (24U)
+#define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
+#define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
+#define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
+#define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
+#define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
+#define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
+#define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
+#define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4_Pos (0U)
+#define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
+#define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
+#define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
+#define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
+#define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
+#define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
+#define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
+#define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
+#define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM4_MEMWAIT4_Pos (8U)
+#define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM4_MEMHOLD4_Pos (16U)
+#define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM4_MEMHIZ4_Pos (24U)
+#define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2_Pos (0U)
+#define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
+#define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
+#define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
+#define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
+#define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
+#define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
+#define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
+#define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
+#define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT2_ATTWAIT2_Pos (8U)
+#define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT2_ATTHOLD2_Pos (16U)
+#define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT2_ATTHIZ2_Pos (24U)
+#define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3_Pos (0U)
+#define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
+#define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
+#define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
+#define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
+#define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
+#define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
+#define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
+#define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
+#define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT3_ATTWAIT3_Pos (8U)
+#define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
+#define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
+#define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
+#define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
+#define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
+#define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
+#define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
+#define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT3_ATTHOLD3_Pos (16U)
+#define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
+#define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
+#define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
+#define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
+#define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
+#define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
+#define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
+#define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT3_ATTHIZ3_Pos (24U)
+#define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
+#define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
+#define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
+#define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
+#define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
+#define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
+#define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
+#define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
+#define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4_Pos (0U)
+#define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
+#define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
+#define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
+#define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
+#define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
+#define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
+#define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
+#define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
+#define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT4_ATTWAIT4_Pos (8U)
+#define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT4_ATTHOLD4_Pos (16U)
+#define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT4_ATTHIZ4_Pos (24U)
+#define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4_Pos (0U)
+#define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PIO4_IOWAIT4_Pos (8U)
+#define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PIO4_IOHOLD4_Pos (16U)
+#define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PIO4_IOHIZ4_Pos (24U)
+#define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2_Pos (0U)
+#define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3_Pos (0U)
+#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC_Pos (0U)
+#define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR1_NR_Pos (2U)
+#define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR1_MWID_Pos (4U)
+#define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR1_NB_Pos (6U)
+#define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS_Pos (7U)
+#define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR1_WP_Pos (9U)
+#define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK_Pos (10U)
+#define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR1_RBURST_Pos (12U)
+#define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE_Pos (13U)
+#define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC_Pos (0U)
+#define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR2_NR_Pos (2U)
+#define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR2_MWID_Pos (4U)
+#define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR2_NB_Pos (6U)
+#define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS_Pos (7U)
+#define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR2_WP_Pos (9U)
+#define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK_Pos (10U)
+#define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR2_RBURST_Pos (12U)
+#define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE_Pos (13U)
+#define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD_Pos (0U)
+#define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR1_TXSR_Pos (4U)
+#define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR1_TRAS_Pos (8U)
+#define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR1_TRC_Pos (12U)
+#define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR1_TWR_Pos (16U)
+#define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR1_TRP_Pos (20U)
+#define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR1_TRCD_Pos (24U)
+#define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD_Pos (0U)
+#define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR2_TXSR_Pos (4U)
+#define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR2_TRAS_Pos (8U)
+#define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR2_TRC_Pos (12U)
+#define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR2_TWR_Pos (16U)
+#define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR2_TRP_Pos (20U)
+#define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR2_TRCD_Pos (24U)
+#define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE_Pos (0U)
+#define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
+#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
+
+#define FMC_SDCMR_CTB2_Pos (3U)
+#define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos (4U)
+#define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos (5U)
+#define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos (9U)
+#define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE_Pos (0U)
+#define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
+#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos (1U)
+#define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos (14U)
+#define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE_Pos (0U)
+#define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
+#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos (1U)
+#define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
+#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos (3U)
+#define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
+#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
+#define FMC_SDSR_BUSY_Pos (5U)
+#define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
+#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* HASH */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+#define HASH_CR_INIT_Pos (2U)
+#define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
+#define HASH_CR_INIT HASH_CR_INIT_Msk
+#define HASH_CR_DMAE_Pos (3U)
+#define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
+#define HASH_CR_DMAE HASH_CR_DMAE_Msk
+#define HASH_CR_DATATYPE_Pos (4U)
+#define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
+#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
+#define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
+#define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
+#define HASH_CR_MODE_Pos (6U)
+#define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
+#define HASH_CR_MODE HASH_CR_MODE_Msk
+#define HASH_CR_ALGO_Pos (7U)
+#define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
+#define HASH_CR_ALGO HASH_CR_ALGO_Msk
+#define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
+#define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
+#define HASH_CR_NBW_Pos (8U)
+#define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
+#define HASH_CR_NBW HASH_CR_NBW_Msk
+#define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
+#define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
+#define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
+#define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
+#define HASH_CR_DINNE_Pos (12U)
+#define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
+#define HASH_CR_DINNE HASH_CR_DINNE_Msk
+#define HASH_CR_MDMAT_Pos (13U)
+#define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
+#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
+#define HASH_CR_LKEY_Pos (16U)
+#define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
+#define HASH_CR_LKEY HASH_CR_LKEY_Msk
+
+/****************** Bits definition for HASH_STR register *******************/
+#define HASH_STR_NBLW_Pos (0U)
+#define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
+#define HASH_STR_NBLW HASH_STR_NBLW_Msk
+#define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
+#define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
+#define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
+#define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
+#define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
+#define HASH_STR_DCAL_Pos (8U)
+#define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
+#define HASH_STR_DCAL HASH_STR_DCAL_Msk
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
+
+/****************** Bits definition for HASH_IMR register *******************/
+#define HASH_IMR_DINIE_Pos (0U)
+#define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
+#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
+#define HASH_IMR_DCIE_Pos (1U)
+#define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
+#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
+/****************** Bits definition for HASH_SR register ********************/
+#define HASH_SR_DINIS_Pos (0U)
+#define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
+#define HASH_SR_DINIS HASH_SR_DINIS_Msk
+#define HASH_SR_DCIS_Pos (1U)
+#define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
+#define HASH_SR_DCIS HASH_SR_DCIS_Msk
+#define HASH_SR_DMAS_Pos (2U)
+#define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
+#define HASH_SR_DMAS HASH_SR_DMAS_Msk
+#define HASH_SR_BUSY_Pos (3U)
+#define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
+#define HASH_SR_BUSY HASH_SR_BUSY_Msk
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH_Pos (0U)
+#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
+#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW_Pos (16U)
+#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP_Pos (0U)
+#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP_Pos (16U)
+#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH_Pos (0U)
+#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW_Pos (16U)
+#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH_Pos (0U)
+#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW_Pos (16U)
+#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN_Pos (0U)
+#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW_Pos (4U)
+#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
+#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
+#define LTDC_GCR_DGW_Pos (8U)
+#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
+#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
+#define LTDC_GCR_DRW_Pos (12U)
+#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
+#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
+#define LTDC_GCR_DEN_Pos (16U)
+#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
+#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
+#define LTDC_GCR_PCPOL_Pos (28U)
+#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL_Pos (29U)
+#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL_Pos (30U)
+#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL_Pos (31U)
+#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN LTDC_GCR_DEN
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR_Pos (0U)
+#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
+#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
+#define LTDC_SRCR_VBR_Pos (1U)
+#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
+#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos (0U)
+#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN_Pos (8U)
+#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos (16U)
+#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE_Pos (0U)
+#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
+#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE_Pos (1U)
+#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
+#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE_Pos (2U)
+#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
+#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE_Pos (3U)
+#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
+#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF_Pos (0U)
+#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
+#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos (1U)
+#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
+#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos (2U)
+#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos (3U)
+#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
+#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF_Pos (0U)
+#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
+#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos (1U)
+#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos (2U)
+#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos (3U)
+#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos (0U)
+#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS_Pos (0U)
+#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos (16U)
+#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES_Pos (0U)
+#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
+#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES_Pos (1U)
+#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
+#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS_Pos (2U)
+#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS_Pos (3U)
+#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN_Pos (0U)
+#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
+#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN_Pos (1U)
+#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN_Pos (4U)
+#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN_Pos (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos (16U)
+#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF_Pos (0U)
+#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos (0U)
+#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN_Pos (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos (16U)
+#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA_Pos (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2_Pos (0U)
+#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos (8U)
+#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP_Pos (16U)
+#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN_Pos (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
+#define LTDC_LxCLUTWR_RED_Pos (16U)
+#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN_Pos (16U)
+#define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
+#define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
+#define PWR_CR_ODSWEN_Pos (17U)
+#define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
+#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN_Pos (18U)
+#define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
+#define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
+#define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY_Pos (16U)
+#define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
+#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY_Pos (17U)
+#define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
+#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
+#define PWR_CSR_UDRDY_Pos (18U)
+#define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
+#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
+/* Legacy define */
+#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
+
+#define RCC_CR_PLLSAION_Pos (28U)
+#define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
+#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
+#define RCC_CR_PLLSAIRDY_Pos (29U)
+#define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
+#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_PLLSAIRDYF_Pos (6U)
+#define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
+#define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
+#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+#define RCC_CIR_PLLSAIRDYC_Pos (22U)
+#define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
+#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
+#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
+#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
+#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
+#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
+#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
+#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
+#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
+#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
+#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
+#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
+#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
+#define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
+#define RCC_AHB2RSTR_HASHRST_Pos (5U)
+#define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
+ /* maintained for legacy purpose */
+#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
+#define RCC_APB1RSTR_UART7RST_Pos (30U)
+#define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
+#define RCC_APB1RSTR_UART8RST_Pos (31U)
+#define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SPI6RST_Pos (21U)
+#define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_LTDCRST_Pos (26U)
+#define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
+#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
+#define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
+#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
+#define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
+#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
+#define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
+#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
+#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
+#define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
+#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
+#define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
+#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
+#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
+#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
+#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
+#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
+#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
+#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_DCMIEN_Pos (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_CRYPEN_Pos (4U)
+#define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
+#define RCC_AHB2ENR_HASHEN_Pos (5U)
+#define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos (6U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FMCEN_Pos (0U)
+#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
+#define RCC_APB1ENR_UART7EN_Pos (30U)
+#define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
+#define RCC_APB1ENR_UART8EN_Pos (31U)
+#define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (1U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_ADC2EN_Pos (9U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
+#define RCC_APB2ENR_ADC3EN_Pos (10U)
+#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SPI6EN_Pos (21U)
+#define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
+#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos (22U)
+#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_LTDCEN_Pos (26U)
+#define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
+#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
+#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
+#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
+#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
+#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
+#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
+#define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
+#define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
+#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
+
+#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
+#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
+#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
+#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
+#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
+#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
+#define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
+#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
+#define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
+#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
+#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
+#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
+#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
+#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
+#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
+
+
+#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
+#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
+#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
+
+#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
+#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
+#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
+#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
+#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
+#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
+#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
+
+#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
+#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
+#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
+#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
+#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
+#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
+#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
+
+#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
+#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
+#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
+#define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
+#define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
+#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
+#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
+#define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
+#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_Pos (0U)
+#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos (4U)
+#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE_Pos (0U)
+#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos (2U)
+#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos (5U)
+#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
+#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
+#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos (8U)
+#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR_Pos (9U)
+#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN_Pos (10U)
+#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos (12U)
+#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV_Pos (13U)
+#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
+#define SAI_xCR1_SAIEN_Pos (16U)
+#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN_Pos (17U)
+#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
+#define SAI_xCR1_NODIV_Pos (19U)
+#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV_Pos (20U)
+#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH_Pos (0U)
+#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos (3U)
+#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS_Pos (4U)
+#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos (5U)
+#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL_Pos (6U)
+#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT_Pos (7U)
+#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos (13U)
+#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
+
+#define SAI_xCR2_COMP_Pos (14U)
+#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL_Pos (0U)
+#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos (8U)
+#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos (16U)
+#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos (17U)
+#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF_Pos (18U)
+#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF_Pos (0U)
+#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos (8U)
+#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos (16U)
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE_Pos (0U)
+#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE_Pos (1U)
+#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE_Pos (2U)
+#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE_Pos (3U)
+#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE_Pos (4U)
+#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE_Pos (5U)
+#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE_Pos (6U)
+#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR_Pos (0U)
+#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET_Pos (1U)
+#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
+#define SAI_xSR_WCKCFG_Pos (2U)
+#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ_Pos (3U)
+#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
+#define SAI_xSR_CNRDY_Pos (4U)
+#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
+#define SAI_xSR_AFSDET_Pos (5U)
+#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET_Pos (6U)
+#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL_Pos (16U)
+#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR_Pos (0U)
+#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ_Pos (3U)
+#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY_Pos (4U)
+#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET_Pos (5U)
+#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET_Pos (6U)
+#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA_Pos (0U)
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
+#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
+#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
+#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
+#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
+/* Legacy Defines */
+#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2_Pos (16U)
+#define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
+#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2_Pos (17U)
+#define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
+#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2_Pos (18U)
+#define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
+#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
+#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD_Pos (23U)
+#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
+#define ETH_MACCR_JD_Pos (22U)
+#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
+#define ETH_MACCR_IFG_Pos (17U)
+#define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
+#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD_Pos (16U)
+#define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES_Pos (14U)
+#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
+#define ETH_MACCR_ROD_Pos (13U)
+#define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
+#define ETH_MACCR_LM_Pos (12U)
+#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
+#define ETH_MACCR_DM_Pos (11U)
+#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
+#define ETH_MACCR_IPCO_Pos (10U)
+#define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
+#define ETH_MACCR_RD_Pos (9U)
+#define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
+#define ETH_MACCR_APCS_Pos (7U)
+#define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
+#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL_Pos (5U)
+#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC_Pos (4U)
+#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
+#define ETH_MACCR_TE_Pos (3U)
+#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
+#define ETH_MACCR_RE_Pos (2U)
+#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA_Pos (31U)
+#define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
+#define ETH_MACFFR_HPF_Pos (10U)
+#define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
+#define ETH_MACFFR_SAF_Pos (9U)
+#define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
+#define ETH_MACFFR_SAIF_Pos (8U)
+#define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
+#define ETH_MACFFR_PCF_Pos (6U)
+#define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
+#define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
+#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
+#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
+#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD_Pos (5U)
+#define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
+#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
+#define ETH_MACFFR_PAM_Pos (4U)
+#define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
+#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF_Pos (3U)
+#define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
+#define ETH_MACFFR_HM_Pos (2U)
+#define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
+#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
+#define ETH_MACFFR_HU_Pos (1U)
+#define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
+#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
+#define ETH_MACFFR_PM_Pos (0U)
+#define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
+#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos (0U)
+#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos (0U)
+#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA_Pos (11U)
+#define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
+#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
+#define ETH_MACMIIAR_MR_Pos (6U)
+#define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
+#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR_Pos (2U)
+#define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
+#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
+#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIAR_CR_Div62_Pos (2U)
+#define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
+#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define ETH_MACMIIAR_CR_Div16_Pos (3U)
+#define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
+#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ETH_MACMIIAR_CR_Div26_Pos (2U)
+#define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
+#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_CR_Div102_Pos (4U)
+#define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
+#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW_Pos (1U)
+#define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
+#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
+#define ETH_MACMIIAR_MB_Pos (0U)
+#define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD_Pos (0U)
+#define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT_Pos (16U)
+#define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
+#define ETH_MACFCR_ZQPD_Pos (7U)
+#define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
+#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT_Pos (4U)
+#define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+#define ETH_MACFCR_PLT_Minus28_Pos (4U)
+#define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
+#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACFCR_PLT_Minus144_Pos (5U)
+#define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
+#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256_Pos (4U)
+#define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD_Pos (3U)
+#define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
+#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE_Pos (2U)
+#define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
+#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
+#define ETH_MACFCR_TFCE_Pos (1U)
+#define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
+#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA_Pos (0U)
+#define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
+#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC_Pos (16U)
+#define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
+#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI_Pos (0U)
+#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D_Pos (0U)
+#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
+#define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
+#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU_Pos (9U)
+#define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
+#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
+#define ETH_MACPMTCSR_WFR_Pos (6U)
+#define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
+#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR_Pos (5U)
+#define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
+#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE_Pos (2U)
+#define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
+#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE_Pos (1U)
+#define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
+#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD_Pos (0U)
+#define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
+#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
+
+/* Bit definition for Ethernet MAC debug Register */
+#define ETH_MACDBGR_TFF_Pos (25U)
+#define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
+#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
+#define ETH_MACDBGR_TFNE_Pos (24U)
+#define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
+#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
+#define ETH_MACDBGR_TFWA_Pos (22U)
+#define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
+#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
+#define ETH_MACDBGR_TFRS_Pos (20U)
+#define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
+#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
+#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
+#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
+#define ETH_MACDBGR_TFRS_READ_Pos (20U)
+#define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
+#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
+#define ETH_MACDBGR_MTP_Pos (19U)
+#define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
+#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
+#define ETH_MACDBGR_MTFCS_Pos (17U)
+#define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
+#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
+#define ETH_MACDBGR_MMTEA_Pos (16U)
+#define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
+#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
+#define ETH_MACDBGR_RFFL_Pos (8U)
+#define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
+#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
+#define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
+#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
+#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
+#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
+#define ETH_MACDBGR_RFRCS_Pos (5U)
+#define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
+#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
+#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
+#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
+#define ETH_MACDBGR_RFWRA_Pos (4U)
+#define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
+#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
+#define ETH_MACDBGR_MSFRWCS_Pos (1U)
+#define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
+#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
+#define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
+#define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
+#define ETH_MACDBGR_MMRPEA_Pos (0U)
+#define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
+#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS_Pos (9U)
+#define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
+#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS_Pos (6U)
+#define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
+#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
+#define ETH_MACSR_MMMCRS_Pos (5U)
+#define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
+#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
+#define ETH_MACSR_MMCS_Pos (4U)
+#define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
+#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
+#define ETH_MACSR_PMTS_Pos (3U)
+#define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
+#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM_Pos (9U)
+#define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
+#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM_Pos (3U)
+#define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
+#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H_Pos (0U)
+#define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L_Pos (0U)
+#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE_Pos (31U)
+#define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
+#define ETH_MACA1HR_SA_Pos (30U)
+#define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
+#define ETH_MACA1HR_MBC_Pos (24U)
+#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H_Pos (0U)
+#define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L_Pos (0U)
+#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE_Pos (31U)
+#define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
+#define ETH_MACA2HR_SA_Pos (30U)
+#define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
+#define ETH_MACA2HR_MBC_Pos (24U)
+#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H_Pos (0U)
+#define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L_Pos (0U)
+#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE_Pos (31U)
+#define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
+#define ETH_MACA3HR_SA_Pos (30U)
+#define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
+#define ETH_MACA3HR_MBC_Pos (24U)
+#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H_Pos (0U)
+#define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L_Pos (0U)
+#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP_Pos (5U)
+#define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP_Pos (4U)
+#define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
+#define ETH_MMCCR_MCF_Pos (3U)
+#define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR_Pos (2U)
+#define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
+#define ETH_MMCCR_CSR_Pos (1U)
+#define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
+#define ETH_MMCCR_CR_Pos (0U)
+#define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS_Pos (17U)
+#define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES_Pos (6U)
+#define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES_Pos (5U)
+#define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS_Pos (21U)
+#define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS_Pos (15U)
+#define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS_Pos (14U)
+#define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM_Pos (17U)
+#define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM_Pos (6U)
+#define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM_Pos (5U)
+#define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM_Pos (21U)
+#define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
+#define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM_Pos (14U)
+#define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
+#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC_Pos (0U)
+#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC_Pos (0U)
+#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC_Pos (0U)
+#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
+#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT_Pos (16U)
+#define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
+#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME_Pos (15U)
+#define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME_Pos (14U)
+#define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
+#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
+#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
+#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
+#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
+#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
+#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
+#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
+#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
+#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR_Pos (9U)
+#define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
+#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE_Pos (8U)
+#define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
+#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU_Pos (5U)
+#define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
+#define ETH_PTPTSCR_TSITE_Pos (4U)
+#define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU_Pos (3U)
+#define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
+#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI_Pos (2U)
+#define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
+#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU_Pos (1U)
+#define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
+#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE_Pos (0U)
+#define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
+#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI_Pos (0U)
+#define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
+#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS_Pos (0U)
+#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS_Pos (31U)
+#define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS_Pos (0U)
+#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS_Pos (0U)
+#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
+#define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS_Pos (0U)
+#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA_Pos (0U)
+#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH_Pos (0U)
+#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL_Pos (0U)
+#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR_Pos (5U)
+#define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO_Pos (4U)
+#define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB_Pos (25U)
+#define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
+#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
+#define ETH_DMABMR_FPM_Pos (24U)
+#define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
+#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
+#define ETH_DMABMR_USP_Pos (23U)
+#define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
+#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
+#define ETH_DMABMR_RDP_Pos (17U)
+#define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
+#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
+#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB_Pos (16U)
+#define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
+#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
+#define ETH_DMABMR_RTPR_Pos (14U)
+#define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
+#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL_Pos (8U)
+#define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
+#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
+#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE_Pos (7U)
+#define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
+#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL_Pos (2U)
+#define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
+#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
+#define ETH_DMABMR_DA_Pos (1U)
+#define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
+#define ETH_DMABMR_SR_Pos (0U)
+#define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD_Pos (0U)
+#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD_Pos (0U)
+#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL_Pos (0U)
+#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL_Pos (0U)
+#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS_Pos (29U)
+#define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
+#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS_Pos (28U)
+#define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
+#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
+#define ETH_DMASR_MMCS_Pos (27U)
+#define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
+#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
+#define ETH_DMASR_EBS_Pos (23U)
+#define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
+#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+#define ETH_DMASR_EBS_DescAccess_Pos (25U)
+#define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
+#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
+#define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
+#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
+#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
+#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS_Pos (20U)
+#define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
+#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMASR_TPS_Fetching_Pos (20U)
+#define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
+#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
+#define ETH_DMASR_TPS_Waiting_Pos (21U)
+#define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
+#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
+#define ETH_DMASR_TPS_Reading_Pos (20U)
+#define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
+#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
+#define ETH_DMASR_TPS_Suspended_Pos (21U)
+#define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
+#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
+#define ETH_DMASR_TPS_Closing_Pos (20U)
+#define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS_Pos (17U)
+#define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
+#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Fetching_Pos (17U)
+#define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
+#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
+#define ETH_DMASR_RPS_Waiting_Pos (17U)
+#define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
+#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
+#define ETH_DMASR_RPS_Suspended_Pos (19U)
+#define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
+#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
+#define ETH_DMASR_RPS_Closing_Pos (17U)
+#define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
+#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
+#define ETH_DMASR_RPS_Queuing_Pos (17U)
+#define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS_Pos (16U)
+#define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
+#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
+#define ETH_DMASR_AIS_Pos (15U)
+#define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
+#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS_Pos (14U)
+#define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
+#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
+#define ETH_DMASR_FBES_Pos (13U)
+#define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
+#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
+#define ETH_DMASR_ETS_Pos (10U)
+#define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
+#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
+#define ETH_DMASR_RWTS_Pos (9U)
+#define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
+#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS_Pos (8U)
+#define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
+#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
+#define ETH_DMASR_RBUS_Pos (7U)
+#define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
+#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
+#define ETH_DMASR_RS_Pos (6U)
+#define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
+#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
+#define ETH_DMASR_TUS_Pos (5U)
+#define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
+#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
+#define ETH_DMASR_ROS_Pos (4U)
+#define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
+#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
+#define ETH_DMASR_TJTS_Pos (3U)
+#define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
+#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS_Pos (2U)
+#define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
+#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS_Pos (1U)
+#define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
+#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
+#define ETH_DMASR_TS_Pos (0U)
+#define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
+#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD_Pos (26U)
+#define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
+#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF_Pos (25U)
+#define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
+#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
+#define ETH_DMAOMR_DFRF_Pos (24U)
+#define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
+#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF_Pos (21U)
+#define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
+#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
+#define ETH_DMAOMR_FTF_Pos (20U)
+#define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
+#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC_Pos (14U)
+#define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
+#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
+#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST_Pos (13U)
+#define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
+#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF_Pos (7U)
+#define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
+#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
+#define ETH_DMAOMR_FUGF_Pos (6U)
+#define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
+#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC_Pos (3U)
+#define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
+#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
+#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF_Pos (2U)
+#define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
+#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
+#define ETH_DMAOMR_SR_Pos (1U)
+#define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
+#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE_Pos (16U)
+#define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
+#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE_Pos (15U)
+#define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
+#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE_Pos (14U)
+#define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE_Pos (13U)
+#define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
+#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE_Pos (10U)
+#define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE_Pos (9U)
+#define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
+#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE_Pos (8U)
+#define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
+#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE_Pos (7U)
+#define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
+#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE_Pos (6U)
+#define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE_Pos (5U)
+#define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
+#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE_Pos (4U)
+#define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
+#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE_Pos (3U)
+#define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
+#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE_Pos (2U)
+#define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
+#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE_Pos (1U)
+#define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
+#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE_Pos (0U)
+#define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC_Pos (28U)
+#define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
+#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA_Pos (17U)
+#define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
+#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC_Pos (16U)
+#define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
+#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC_Pos (0U)
+#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
+#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP_Pos (0U)
+#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP_Pos (0U)
+#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP_Pos (0U)
+#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP_Pos (0U)
+#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
+#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
+#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
+
+#define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
+#define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+#define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F439xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ #define STM32F439xx /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ DMA_1 = (int)DMA1_BASE,
+ DMA_2 = (int)DMA2_BASE
+} DMAName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,319 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - ARDUINO A0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - ARDUINO A1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO A2
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - ARDUINO A3
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - ARDUINO A5
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - ARDUINO A4
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
+ {NC, NC, 0}
+};
+
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PC_12, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D15
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PA_6, PWM_13,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13,1, 0)}, // TIM13_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO D11
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+// {PA_7, PWM_14,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14,1, 0)}, // TIM14_CH1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO D3
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D5
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO D10
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_8, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+// {PB_9, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO D6
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+// {PB_14, PWM_12,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+// {PB_15, PWM_12,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D9
+// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+// {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PE_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PE_7, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+// {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+// {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs
+ {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+// {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+// {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+// {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+// {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // unsolder JP69 to use it
+// {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // unsolder JP14 to use it
+// {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+ {NC, NC, 0}
+};
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PD_0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
+// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)},
+ {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)},
+ {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)},
+// {PC_1, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PD_0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
+// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
+ {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)},
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+// {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+// {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // unsolder JP73 to use it
+// {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // unsolder JP36 to use it
+// {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // connected to MEMs
+// {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+// {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // unsolder JP74 to use it
+// {PB_6 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // unsolder JP43 to use it
+// {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // connected to MEMs
+// {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,222 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_1,
+ A1 = PA_2,
+ A2 = PC_3,
+ A3 = PC_2,
+ A4 = PB_1,
+ A5 = PC_0,
+ D0 = PD_6,
+ D1 = PD_5,
+ D2 = PD_4,
+ D3 = PC_8,
+ D4 = PD_2,
+ D5 = PD_15,
+ D6 = PD_14,
+ D7 = PE_15,
+ D8 = PE_3,
+ D9 = PB_4,
+ D10 = PE_4,
+ D11 = PE_6,
+ D12 = PE_5,
+ D13 = PE_2,
+ D14 = PC_12,
+ D15 = PB_10,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PC_10,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PC_11,
+#endif
+
+ // Generic signals namings
+ LED1 = PD_10,
+ LED2 = LED1,
+ LED3 = PD_11,
+ LED4 = PD_12,
+ LED_RED = LED1,
+ USER_BUTTON = PD_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ PWM_OUT = D3,
+
+ //USB pins
+ USB_OTG_HS_ULPI_D0 = PA_3,
+ USB_OTG_HS_SOF = PA_4,
+ USB_OTG_HS_ULPI_CK = PA_5,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_HS_ULPI_D1 = PB_0,
+ USB_OTG_HS_ULPI_D2 = PB_1,
+ USB_OTG_HS_ULPI_D4 = PB_2,
+ USB_OTG_HS_ULPI_D7 = PB_5,
+ USB_OTG_HS_ULPI_D3 = PB_10,
+ USB_OTG_HS_ID = PB_12,
+ USB_OTG_HS_ULPI_D5 = PB_12,
+ USB_OTG_HS_ULPI_D6 = PB_13,
+ USB_OTG_HS_VBUS = PB_13,
+ USB_OTG_HS_DM = PB_14,
+ USB_OTG_HS_DP = PB_15,
+ USB_OTG_HS_ULPI_STP = PC_0,
+ USB_OTG_HS_ULPI_DIR = PC_2,
+ USB_OTG_HS_ULPI_NXT = PC_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,256 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_XTAL | 3- PLL_HSI
+ * | (external 16 MHz xtal) | (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 180 | 180
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 180 | 180
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 45 | 45
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 90 | 90
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | NO
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+#define DEBUG_MCO (0) // 0=OFF
+// 1=Output the MCO1 on PA8
+// 2=Output the MCO2 on PC9
+
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0) {
+ while (1) {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO2 pin(PC9) for debugging purpose
+#if DEBUG_MCO == 2
+ HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 180/4 = 45 MHz
+#endif
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; //
+ RCC_OscInitStruct.PLL.PLLR = 6; //
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLLSAI output as USB clock source
+ PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ if (bypass == 0) {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 16 MHz with xtal
+ } else {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // xx MHz with external clock (MCO)
+ }
+#endif
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; //
+ RCC_OscInitStruct.PLL.PLLQ = 6; //
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 180 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+ return 1; // OK
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,311 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0
+ {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
+ {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
+// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to STDIO_UART_TX
+// {PA_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to STDIO_UART_TX
+// {PA_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to STDIO_UART_TX
+// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX
+// {PA_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // Connected to STDIO_UART_RX
+// {PA_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // Connected to STDIO_UART_RX
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to LD2 [Green Led]
+ {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // Connected to LD2 [Green Led]
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
+ {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
+ {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+ {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
+ {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 // Connected to LD2 [Green Led]
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to SWO
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PC_12, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to STDIO_UART_TX
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to STDIO_UART_TX
+// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to STDIO_UART_RX
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // Connected to STDIO_UART_RX
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to LD2 [Green Led]
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to LD2 [Green Led]
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_8_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT1, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_9_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT1, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)},
+ {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},
+ {PC_1_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD2 [Green Led]
+ {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,258 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_0_ALT0 = PA_0 | ALT0,
+ PA_0_ALT1 = PA_0 | ALT1,
+ PA_1 = 0x01,
+ PA_1_ALT0 = PA_1 | ALT0,
+ PA_1_ALT1 = PA_1 | ALT1,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_4_ALT1 = PB_4 | ALT1,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_5_ALT1 = PB_5 | ALT1,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_8_ALT1 = PB_8 | ALT1,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_9_ALT1 = PB_9 | ALT1,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_0_ALT0 = PC_0 | ALT0,
+ PC_0_ALT1 = PC_0 | ALT1,
+ PC_1 = 0x21,
+ PC_1_ALT0 = PC_1 | ALT0,
+ PC_1_ALT1 = PC_1 | ALT1,
+ PC_2 = 0x22,
+ PC_2_ALT0 = PC_2 | ALT0,
+ PC_2_ALT1 = PC_2 | ALT1,
+ PC_3 = 0x23,
+ PC_3_ALT0 = PC_3 | ALT0,
+ PC_3_ALT1 = PC_3 | ALT1,
+ PC_4 = 0x24,
+ PC_4_ALT0 = PC_4 | ALT0,
+ PC_5 = 0x25,
+ PC_5_ALT0 = PC_5 | ALT0,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_10_ALT0 = PC_10 | ALT0,
+ PC_11 = 0x2B,
+ PC_11_ALT0 = PC_11 | ALT0,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_0,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = PC_7,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_2,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_3,
+#endif
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ LED_RED = LED1,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_HS_DM = PB_14,
+ USB_OTG_HS_DP = PB_15,
+ USB_OTG_HS_ID = PB_12,
+ USB_OTG_HS_SOF = PA_4,
+ USB_OTG_HS_ULPI_CK = PA_5,
+ USB_OTG_HS_ULPI_D0 = PA_3,
+ USB_OTG_HS_ULPI_D1 = PB_0,
+ USB_OTG_HS_ULPI_D2 = PB_1,
+ USB_OTG_HS_ULPI_D3 = PB_10,
+ USB_OTG_HS_ULPI_D4 = PB_2,
+ USB_OTG_HS_ULPI_D5 = PB_12,
+ USB_OTG_HS_ULPI_D6 = PB_13,
+ USB_OTG_HS_ULPI_D7 = PB_5,
+ USB_OTG_HS_ULPI_DIR = PC_2,
+ USB_OTG_HS_ULPI_NXT = PC_3,
+ USB_OTG_HS_ULPI_STP = PC_0,
+ USB_OTG_HS_VBUS = PB_13,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACED0 = PC_8,
+ SYS_WKUP0 = PA_0,
+ SYS_WKUP1 = PC_13,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,268 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC | 3- USE_PLL_HSI
+ * | (external 8 MHz clock) | (internal 16 MHz)
+ * | 2- USE_PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 180 | 180
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 180 | 180
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 45 | 45
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 90 | 90
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES (HSI calibration needed)
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+//#define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)
+
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO2 pin(PC9) for debugging purpose
+#if DEBUG_MCO == 1
+ HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; //
+ RCC_OscInitStruct.PLL.PLLR = 2; //
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLLSAI output as USB clock source
+ PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ if (bypass == 0) {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ } else {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
+ }
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; //
+ RCC_OscInitStruct.PLL.PLLQ = 6; //
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLLSAI output as USB clock source
+ PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ FMPI2C_1 = (int)FMPI2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,382 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0
+ {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
+ {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
+ {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
+ {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to LD1
+ {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to LD1
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
+ {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
+ {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+ {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
+ {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
+ {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9
+ {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14
+ {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15
+ {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
+ {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5
+ {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
+ {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
+ {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue]
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PC_12, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to USB_SOF [TP1]
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PD_12, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PD_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_SOF [TP1]
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD1
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LD1
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD1
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD2 [Blue]
+ {PB_8, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_8_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT1, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_9_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT1, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LD3 [Red]
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+// {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO UART
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+// {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO UART
+ {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX
+ {PE_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue]
+// {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO UART
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO UART
+ {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX
+ {PE_7, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
+ {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red]
+ {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
+ {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD1
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Connected to LD1
+ {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},
+ {PC_1_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PG_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red]
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PG_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_VBUS
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PG_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PG_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,336 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_0_ALT0 = PA_0 | ALT0,
+ PA_0_ALT1 = PA_0 | ALT1,
+ PA_1 = 0x01,
+ PA_1_ALT0 = PA_1 | ALT0,
+ PA_1_ALT1 = PA_1 | ALT1,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_2_ALT1 = PA_2 | ALT1,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_3_ALT1 = PA_3 | ALT1,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_4_ALT1 = PB_4 | ALT1,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_5_ALT1 = PB_5 | ALT1,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_8_ALT1 = PB_8 | ALT1,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_9_ALT1 = PB_9 | ALT1,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_0_ALT0 = PC_0 | ALT0,
+ PC_0_ALT1 = PC_0 | ALT1,
+ PC_1 = 0x21,
+ PC_1_ALT0 = PC_1 | ALT0,
+ PC_1_ALT1 = PC_1 | ALT1,
+ PC_2 = 0x22,
+ PC_2_ALT0 = PC_2 | ALT0,
+ PC_2_ALT1 = PC_2 | ALT1,
+ PC_3 = 0x23,
+ PC_3_ALT0 = PC_3 | ALT0,
+ PC_3_ALT1 = PC_3 | ALT1,
+ PC_4 = 0x24,
+ PC_4_ALT0 = PC_4 | ALT0,
+ PC_5 = 0x25,
+ PC_5_ALT0 = PC_5 | ALT0,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+ PH_2 = 0x72,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PA_3,
+ A1 = PC_0,
+ A2 = PC_3,
+ A3 = PF_3,
+ A4 = PF_5,
+ A5 = PF_10,
+ D0 = PG_9,
+ D1 = PG_14,
+ D2 = PF_15,
+ D3 = PE_13,
+ D4 = PF_14,
+ D5 = PE_11,
+ D6 = PE_9,
+ D7 = PF_13,
+ D8 = PF_12,
+ D9 = PD_15,
+ D10 = PD_14,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PD_8,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PD_9,
+#endif
+
+ // Generic signals namings
+ LED1 = PB_0,
+ LED2 = PB_7,
+ LED3 = PB_14,
+ LED4 = LED1,
+ LED_RED = LED3,
+ USER_BUTTON = PC_13,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX, // Virtual Com Port
+ SERIAL_RX = STDIO_UART_RX, // Virtual Com Port
+ USBTX = STDIO_UART_TX, // Virtual Com Port
+ USBRX = STDIO_UART_RX, // Virtual Com Port
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ PWM_OUT = D9,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_HS_DM = PB_14,
+ USB_OTG_HS_DP = PB_15,
+ USB_OTG_HS_ID = PB_12,
+ USB_OTG_HS_SOF = PA_4,
+ USB_OTG_HS_ULPI_CK = PA_5,
+ USB_OTG_HS_ULPI_D0 = PA_3,
+ USB_OTG_HS_ULPI_D1 = PB_0,
+ USB_OTG_HS_ULPI_D2 = PB_1,
+ USB_OTG_HS_ULPI_D3 = PB_10,
+ USB_OTG_HS_ULPI_D4 = PB_2,
+ USB_OTG_HS_ULPI_D5 = PB_12,
+ USB_OTG_HS_ULPI_D6 = PB_13,
+ USB_OTG_HS_ULPI_D7 = PB_5,
+ USB_OTG_HS_ULPI_DIR = PC_2,
+ USB_OTG_HS_ULPI_NXT = PC_3,
+ USB_OTG_HS_ULPI_STP = PC_0,
+ USB_OTG_HS_VBUS = PB_13,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED0_ALT0 = PC_8,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED1_ALT0 = PD_3,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED2_ALT0 = PG_13,
+ SYS_TRACED3 = PE_6,
+ SYS_TRACED3_ALT0 = PG_14,
+ SYS_WKUP0 = PA_0,
+ SYS_WKUP1 = PC_13,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,276 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 180
+ * AHBCLK (MHz) | 180
+ * APB1CLK (MHz) | 45
+ * APB2CLK (MHz) | 90
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+//#define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)
+
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO2 pin(PC9) for debugging purpose
+#if DEBUG_MCO == 1
+ HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; //
+ RCC_OscInitStruct.PLL.PLLR = 2; //
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLLSAI output as USB clock source
+ PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ if (bypass == 0) {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ } else {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
+ }
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; //
+ RCC_OscInitStruct.PLL.PLLR = 6; //
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 180 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,438 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f446xx.s +;* Author : MCD Application Team +;* Description : STM32F446x devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QuadSPI_IRQHandler ; QuadSPI + DCD CEC_IRQHandler ; CEC + DCD SPDIF_RX_IRQHandler ; SPDIF RX + DCD I2C4_Event_IRQHandler ; I2C 4 Event + DCD I2C4_Error_IRQHandler ; I2C 4 Error +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QuadSPI_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT I2C4_Event_IRQHandler [WEAK] + EXPORT I2C4_Error_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +QuadSPI_IRQHandler +CEC_IRQHandler +SPDIF_RX_IRQHandler +I2C4_Event_IRQHandler +I2C4_Error_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/stm32f446xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/stm32f446xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+LR_IROM1 0x08000000 0x80000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C4) (0x20000-0x1C4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,411 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f446xx.s +;* Author : MCD Application Team +;* Description : STM32F446x devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QuadSPI_IRQHandler ; QuadSPI + DCD CEC_IRQHandler ; CEC + DCD SPDIF_RX_IRQHandler ; SPDIF RX + DCD I2C4_Event_IRQHandler ; I2C 4 Event + DCD I2C4_Error_IRQHandler ; I2C 4 Error +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QuadSPI_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT I2C4_Event_IRQHandler [WEAK] + EXPORT I2C4_Error_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +QuadSPI_IRQHandler +CEC_IRQHandler +SPDIF_RX_IRQHandler +I2C4_Event_IRQHandler +I2C4_Error_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/stm32f446xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/stm32f446xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+LR_IROM1 0x08000000 0x80000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C4) (0x20000-0x1C4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,161 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 512K
+#endif
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = 0x200001C4, LENGTH = 128k - 0x1C4
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f446xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f446xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,557 @@ +/** + ****************************************************************************** + * @file startup_stm32f446xx.s + * @author MCD Application Team + * @brief STM32F446xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SAI1_IRQHandler /* SAI1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SAI2_IRQHandler /* SAI2 */ + .word QuadSPI_IRQHandler /* QuadSPI */ + .word CEC_IRQHandler /* CEC */ + .word SPDIF_RX_IRQHandler /* SPDIF RX */ + .word FMPI2C1_Event_IRQHandler /* FMPI2C 1 Event */ + .word FMPI2C1_Error_IRQHandler /* FMPI2C 1 Error */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QuadSPI_IRQHandler + .thumb_set QuadSPI_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak FMPI2C1_Event_IRQHandler + .thumb_set FMPI2C1_Event_IRQHandler,Default_Handler + + .weak FMPI2C1_Error_IRQHandler + .thumb_set FMPI2C1_Error_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,676 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f446xx.s +;* Author : MCD Application Team +;* Description : STM32F446xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QuadSPI + DCD CEC_IRQHandler ; CEC + DCD SPDIF_RX_IRQHandler ; SPDIF RX + DCD FMPI2C1_Event_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_Error_IRQHandler ; FMPI2C1 Error + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK FMPI2C1_Event_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_Event_IRQHandler + B FMPI2C1_Event_IRQHandler + + PUBWEAK FMPI2C1_Error_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_Error_IRQHandler + B FMPI2C1_Error_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/stm32f446xx.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/stm32f446xx.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,31 @@
+/* [ROM = 512kb = 0x80000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0807FFFF;
+
+/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x200001C3; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x200001C4;
+define symbol __region_RAM_end__ = 0x2001FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x4000;
+define symbol __size_heap__ = 0x8000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 97 vectors = 388 bytes from 0x40 to 0x1C3 +// Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM +#define NVIC_NUM_VECTORS 113 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x80000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f446xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f446xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,15934 @@
+/**
+ ******************************************************************************
+ * @file stm32f446xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f446xx
+ * @{
+ */
+
+#ifndef __STM32F446xx_H
+#define __STM32F446xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ CEC_IRQn = 93, /*!< CEC global Interrupt */
+ SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+
+/**
+ * @brief Consumer Electronics Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief SPDIFRX Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
+ __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
+ __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
+ uint16_t RESERVED2; /*!< Reserved, 0x1A */
+} SPDIFRX_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC123_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC123_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2_Pos (8U)
+#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos (9U)
+#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos (10U)
+#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos (11U)
+#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos (12U)
+#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos (13U)
+#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3_Pos (16U)
+#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos (17U)
+#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos (18U)
+#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos (19U)
+#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos (20U)
+#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos (21U)
+#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos (14U)
+#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos (15U)
+#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos (16U)
+#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos (17U)
+#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos (18U)
+#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos (19U)
+#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos (20U)
+#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos (21U)
+#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos (22U)
+#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos (23U)
+#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos (24U)
+#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos (25U)
+#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos (26U)
+#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos (27U)
+#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* HDMI-CEC (CEC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN_Pos (0U)
+#define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
+#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
+#define CEC_CR_TXSOM_Pos (1U)
+#define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
+#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
+#define CEC_CR_TXEOM_Pos (2U)
+#define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
+#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT_Pos (0U)
+#define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
+#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
+#define CEC_CFGR_RXTOL_Pos (3U)
+#define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
+#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
+#define CEC_CFGR_BRESTP_Pos (4U)
+#define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
+#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
+#define CEC_CFGR_BREGEN_Pos (5U)
+#define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
+#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
+#define CEC_CFGR_LBPEGEN_Pos (6U)
+#define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
+#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
+#define CEC_CFGR_SFTOPT_Pos (8U)
+#define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
+#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
+#define CEC_CFGR_BRDNOGEN_Pos (7U)
+#define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
+#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
+#define CEC_CFGR_OAR_Pos (16U)
+#define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
+#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
+#define CEC_CFGR_LSTN_Pos (31U)
+#define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
+#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD_Pos (0U)
+#define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
+#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_RXDR_RXD_Pos (0U)
+#define CEC_RXDR_RXD_Msk (0xFFU << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
+#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
+/*legacy define*/
+#define CEC_TXDR_RXD CEC_RXDR_RXD /*!< CEC Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR_Pos (0U)
+#define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
+#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
+#define CEC_ISR_RXEND_Pos (1U)
+#define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
+#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
+#define CEC_ISR_RXOVR_Pos (2U)
+#define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
+#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
+#define CEC_ISR_BRE_Pos (3U)
+#define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
+#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
+#define CEC_ISR_SBPE_Pos (4U)
+#define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
+#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
+#define CEC_ISR_LBPE_Pos (5U)
+#define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
+#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
+#define CEC_ISR_RXACKE_Pos (6U)
+#define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
+#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST_Pos (7U)
+#define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
+#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
+#define CEC_ISR_TXBR_Pos (8U)
+#define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
+#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
+#define CEC_ISR_TXEND_Pos (9U)
+#define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
+#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
+#define CEC_ISR_TXUDR_Pos (10U)
+#define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
+#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
+#define CEC_ISR_TXERR_Pos (11U)
+#define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
+#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
+#define CEC_ISR_TXACKE_Pos (12U)
+#define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
+#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE_Pos (0U)
+#define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
+#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE_Pos (1U)
+#define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
+#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE_Pos (2U)
+#define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
+#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
+#define CEC_IER_BREIE_Pos (3U)
+#define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
+#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE_Pos (4U)
+#define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
+#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
+#define CEC_IER_LBPEIE_Pos (5U)
+#define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
+#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE_Pos (6U)
+#define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
+#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE_Pos (7U)
+#define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
+#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE_Pos (8U)
+#define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
+#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE_Pos (9U)
+#define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
+#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE_Pos (10U)
+#define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
+#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE_Pos (11U)
+#define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
+#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE_Pos (12U)
+#define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
+#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE_Pos (0U)
+#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos (1U)
+#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
+#define DCMI_CR_CM DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos (2U)
+#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos (3U)
+#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos (4U)
+#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos (5U)
+#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos (6U)
+#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos (7U)
+#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_OUTEN_Pos (13U)
+#define DCMI_CR_OUTEN_Msk (0x1U << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */
+#define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
+#define DCMI_CR_ENABLE_Pos (14U)
+#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_0 0x00010000U
+#define DCMI_CR_BSM_1 0x00020000U
+#define DCMI_CR_OEBS_Pos (18U)
+#define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
+#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos (19U)
+#define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
+#define DCMI_CR_LSM DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos (20U)
+#define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
+#define DCMI_CR_OELS DCMI_CR_OELS_Msk
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC_Pos (0U)
+#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos (1U)
+#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos (2U)
+#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS_Pos (0U)
+#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos (1U)
+#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos (2U)
+#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos (4U)
+#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE_Pos (0U)
+#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos (1U)
+#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos (2U)
+#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos (3U)
+#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos (4U)
+#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS_Pos (0U)
+#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos (1U)
+#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos (2U)
+#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos (4U)
+#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC_Pos (0U)
+#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos (1U)
+#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos (2U)
+#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos (4U)
+#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC_Pos (0U)
+#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos (8U)
+#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos (16U)
+#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos (24U)
+#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU_Pos (0U)
+#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos (8U)
+#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos (16U)
+#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos (24U)
+#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos (16U)
+#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos (16U)
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
+
+/******************** Bits definition for DCMI_DR register *********************/
+#define DCMI_DR_BYTE0_Pos (0U)
+#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos (8U)
+#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos (16U)
+#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos (24U)
+#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_MER2_Pos (15U)
+#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_BFB2_Pos (4U)
+#define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
+#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M_Pos (30U)
+#define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
+#define FLASH_OPTCR_SPRMOD_Pos (31U)
+#define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN_Pos (0U)
+#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN_Pos (1U)
+#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP_Pos (2U)
+#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR1_MWID_Pos (4U)
+#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR1_FACCEN_Pos (6U)
+#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN_Pos (8U)
+#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL_Pos (9U)
+#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR1_WAITCFG_Pos (11U)
+#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR1_WREN_Pos (12U)
+#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR1_WAITEN_Pos (13U)
+#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD_Pos (14U)
+#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE_Pos (16U)
+#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR1_CBURSTRW_Pos (19U)
+#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_WFDIS_Pos (21U)
+#define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN_Pos (0U)
+#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN_Pos (1U)
+#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP_Pos (2U)
+#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR2_MWID_Pos (4U)
+#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR2_FACCEN_Pos (6U)
+#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN_Pos (8U)
+#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL_Pos (9U)
+#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR2_WAITCFG_Pos (11U)
+#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR2_WREN_Pos (12U)
+#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR2_WAITEN_Pos (13U)
+#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD_Pos (14U)
+#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW_Pos (19U)
+#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN_Pos (0U)
+#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN_Pos (1U)
+#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP_Pos (2U)
+#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR3_MWID_Pos (4U)
+#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR3_FACCEN_Pos (6U)
+#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN_Pos (8U)
+#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL_Pos (9U)
+#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR3_WAITCFG_Pos (11U)
+#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR3_WREN_Pos (12U)
+#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR3_WAITEN_Pos (13U)
+#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD_Pos (14U)
+#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW_Pos (19U)
+#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN_Pos (0U)
+#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN_Pos (1U)
+#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP_Pos (2U)
+#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR4_MWID_Pos (4U)
+#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR4_FACCEN_Pos (6U)
+#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN_Pos (8U)
+#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL_Pos (9U)
+#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR4_WAITCFG_Pos (11U)
+#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR4_WREN_Pos (12U)
+#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR4_WAITEN_Pos (13U)
+#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD_Pos (14U)
+#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW_Pos (19U)
+#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET_Pos (0U)
+#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR1_ADDHLD_Pos (4U)
+#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR1_DATAST_Pos (8U)
+#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR1_BUSTURN_Pos (16U)
+#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR1_CLKDIV_Pos (20U)
+#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR1_DATLAT_Pos (24U)
+#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR1_ACCMOD_Pos (28U)
+#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET_Pos (0U)
+#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR2_ADDHLD_Pos (4U)
+#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR2_DATAST_Pos (8U)
+#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR2_BUSTURN_Pos (16U)
+#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR2_CLKDIV_Pos (20U)
+#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR2_DATLAT_Pos (24U)
+#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR2_ACCMOD_Pos (28U)
+#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET_Pos (0U)
+#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR3_ADDHLD_Pos (4U)
+#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR3_DATAST_Pos (8U)
+#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR3_BUSTURN_Pos (16U)
+#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR3_CLKDIV_Pos (20U)
+#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR3_DATLAT_Pos (24U)
+#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR3_ACCMOD_Pos (28U)
+#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET_Pos (0U)
+#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR4_ADDHLD_Pos (4U)
+#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR4_DATAST_Pos (8U)
+#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR4_BUSTURN_Pos (16U)
+#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR4_CLKDIV_Pos (20U)
+#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR4_DATLAT_Pos (24U)
+#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR4_ACCMOD_Pos (28U)
+#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET_Pos (0U)
+#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR1_ADDHLD_Pos (4U)
+#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR1_DATAST_Pos (8U)
+#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR1_BUSTURN_Pos (16U)
+#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR1_ACCMOD_Pos (28U)
+#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET_Pos (0U)
+#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR2_ADDHLD_Pos (4U)
+#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR2_DATAST_Pos (8U)
+#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR2_BUSTURN_Pos (16U)
+#define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR2_ACCMOD_Pos (28U)
+#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET_Pos (0U)
+#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR3_ADDHLD_Pos (4U)
+#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR3_DATAST_Pos (8U)
+#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR3_BUSTURN_Pos (16U)
+#define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR3_ACCMOD_Pos (28U)
+#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET_Pos (0U)
+#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR4_ADDHLD_Pos (4U)
+#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR4_DATAST_Pos (8U)
+#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR4_BUSTURN_Pos (16U)
+#define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR4_ACCMOD_Pos (28U)
+#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_PCR register *******************/
+#define FMC_PCR_PWAITEN_Pos (1U)
+#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN_Pos (2U)
+#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos (3U)
+#define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR_PWID_Pos (4U)
+#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos (6U)
+#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR_Pos (9U)
+#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos (13U)
+#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos (17U)
+#define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FMC_SR register *******************/
+#define FMC_SR_IRS_Pos (0U)
+#define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS_Pos (1U)
+#define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR_IFS_Pos (2U)
+#define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN_Pos (3U)
+#define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN_Pos (4U)
+#define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN_Pos (5U)
+#define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos (6U)
+#define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET2_Pos (0U)
+#define FMC_PMEM_MEMSET2_Msk (0xFFU << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET2_0 (0x01U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET2_1 (0x02U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET2_2 (0x04U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET2_3 (0x08U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET2_4 (0x10U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET2_5 (0x20U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET2_6 (0x40U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET2_7 (0x80U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT2_Pos (8U)
+#define FMC_PMEM_MEMWAIT2_Msk (0xFFU << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT2_0 (0x01U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT2_1 (0x02U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT2_2 (0x04U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT2_3 (0x08U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT2_4 (0x10U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT2_5 (0x20U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT2_6 (0x40U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT2_7 (0x80U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD2_Pos (16U)
+#define FMC_PMEM_MEMHOLD2_Msk (0xFFU << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD2_0 (0x01U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD2_1 (0x02U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD2_2 (0x04U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD2_3 (0x08U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD2_4 (0x10U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD2_5 (0x20U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD2_6 (0x40U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD2_7 (0x80U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ2_Pos (24U)
+#define FMC_PMEM_MEMHIZ2_Msk (0xFFU << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ2_0 (0x01U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ2_1 (0x02U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ2_2 (0x04U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ2_3 (0x08U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ2_4 (0x10U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ2_5 (0x20U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ2_6 (0x40U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ2_7 (0x80U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT register ******************/
+#define FMC_PATT_ATTSET2_Pos (0U)
+#define FMC_PATT_ATTSET2_Msk (0xFFU << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */
+#define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET2_0 (0x01U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */
+#define FMC_PATT_ATTSET2_1 (0x02U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */
+#define FMC_PATT_ATTSET2_2 (0x04U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */
+#define FMC_PATT_ATTSET2_3 (0x08U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */
+#define FMC_PATT_ATTSET2_4 (0x10U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */
+#define FMC_PATT_ATTSET2_5 (0x20U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */
+#define FMC_PATT_ATTSET2_6 (0x40U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */
+#define FMC_PATT_ATTSET2_7 (0x80U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT2_Pos (8U)
+#define FMC_PATT_ATTWAIT2_Msk (0xFFU << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT2_0 (0x01U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT2_1 (0x02U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT2_2 (0x04U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT2_3 (0x08U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT2_4 (0x10U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT2_5 (0x20U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT2_6 (0x40U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT2_7 (0x80U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD2_Pos (16U)
+#define FMC_PATT_ATTHOLD2_Msk (0xFFU << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD2_0 (0x01U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD2_1 (0x02U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD2_2 (0x04U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD2_3 (0x08U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD2_4 (0x10U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD2_5 (0x20U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD2_6 (0x40U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD2_7 (0x80U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ2_Pos (24U)
+#define FMC_PATT_ATTHIZ2_Msk (0xFFU << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ2_0 (0x01U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ2_1 (0x02U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ2_2 (0x04U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ2_3 (0x08U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ2_4 (0x10U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ2_5 (0x20U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ2_6 (0x40U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ2_7 (0x80U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_ECCR register ******************/
+#define FMC_ECCR_ECC2_Pos (0U)
+#define FMC_ECCR_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC_Pos (0U)
+#define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR1_NR_Pos (2U)
+#define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR1_MWID_Pos (4U)
+#define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR1_NB_Pos (6U)
+#define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS_Pos (7U)
+#define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR1_WP_Pos (9U)
+#define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK_Pos (10U)
+#define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR1_RBURST_Pos (12U)
+#define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE_Pos (13U)
+#define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC_Pos (0U)
+#define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR2_NR_Pos (2U)
+#define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR2_MWID_Pos (4U)
+#define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR2_NB_Pos (6U)
+#define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS_Pos (7U)
+#define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR2_WP_Pos (9U)
+#define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK_Pos (10U)
+#define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR2_RBURST_Pos (12U)
+#define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE_Pos (13U)
+#define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD_Pos (0U)
+#define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR1_TXSR_Pos (4U)
+#define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR1_TRAS_Pos (8U)
+#define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR1_TRC_Pos (12U)
+#define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR1_TWR_Pos (16U)
+#define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR1_TRP_Pos (20U)
+#define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR1_TRCD_Pos (24U)
+#define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD_Pos (0U)
+#define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR2_TXSR_Pos (4U)
+#define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR2_TRAS_Pos (8U)
+#define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR2_TRC_Pos (12U)
+#define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR2_TWR_Pos (16U)
+#define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR2_TRP_Pos (20U)
+#define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR2_TRCD_Pos (24U)
+#define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE_Pos (0U)
+#define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
+#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
+
+#define FMC_SDCMR_CTB2_Pos (3U)
+#define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos (4U)
+#define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos (5U)
+#define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos (9U)
+#define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE_Pos (0U)
+#define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
+#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos (1U)
+#define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos (14U)
+#define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE_Pos (0U)
+#define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
+#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos (1U)
+#define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
+#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos (3U)
+#define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
+#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
+#define FMC_SDSR_BUSY_Pos (5U)
+#define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
+#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE_Pos (0U)
+#define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE_Pos (1U)
+#define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE_Pos (2U)
+#define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE_Pos (3U)
+#define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE_Pos (4U)
+#define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE_Pos (5U)
+#define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE_Pos (6U)
+#define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE_Pos (7U)
+#define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN_Pos (8U)
+#define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
+#define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF_Pos (12U)
+#define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN_Pos (14U)
+#define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN_Pos (15U)
+#define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC_Pos (16U)
+#define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH_Pos (17U)
+#define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN_Pos (19U)
+#define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN_Pos (20U)
+#define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN_Pos (21U)
+#define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN_Pos (22U)
+#define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN_Pos (23U)
+#define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD_Pos (0U)
+#define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN_Pos (10U)
+#define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10_Pos (11U)
+#define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R_Pos (12U)
+#define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START_Pos (13U)
+#define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
+#define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
+#define FMPI2C_CR2_STOP_Pos (14U)
+#define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK_Pos (15U)
+#define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES_Pos (16U)
+#define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD_Pos (24U)
+#define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND_Pos (25U)
+#define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE_Pos (26U)
+#define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1_Pos (0U)
+#define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE_Pos (10U)
+#define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN_Pos (15U)
+#define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2_Pos (1U)
+#define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK_Pos (8U)
+#define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN_Pos (15U)
+#define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL_Pos (0U)
+#define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH_Pos (8U)
+#define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL_Pos (16U)
+#define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
+#define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC_Pos (28U)
+#define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
+#define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE_Pos (0U)
+#define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS_Pos (1U)
+#define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE_Pos (2U)
+#define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR_Pos (3U)
+#define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF_Pos (4U)
+#define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF_Pos (5U)
+#define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define FMPI2C_ISR_TC_Pos (6U)
+#define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR_Pos (7U)
+#define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR_Pos (8U)
+#define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
+#define FMPI2C_ISR_ARLO_Pos (9U)
+#define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR_Pos (10U)
+#define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR_Pos (11U)
+#define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT_Pos (12U)
+#define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT_Pos (13U)
+#define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY_Pos (15U)
+#define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
+#define FMPI2C_ISR_DIR_Pos (16U)
+#define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE_Pos (17U)
+#define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF_Pos (3U)
+#define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF_Pos (4U)
+#define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF_Pos (5U)
+#define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF_Pos (8U)
+#define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF_Pos (9U)
+#define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF_Pos (10U)
+#define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF_Pos (11U)
+#define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF_Pos (12U)
+#define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF_Pos (13U)
+#define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC_Pos (0U)
+#define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA_Pos (0U)
+#define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA_Pos (0U)
+#define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN_Pos (16U)
+#define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
+#define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
+#define PWR_CR_ODSWEN_Pos (17U)
+#define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
+#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN_Pos (18U)
+#define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
+#define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
+#define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
+#define PWR_CR_FMSSR_Pos (20U)
+#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
+#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR_Pos (21U)
+#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
+#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_EWUP2_Pos (7U)
+#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY_Pos (16U)
+#define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
+#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY_Pos (17U)
+#define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
+#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
+#define PWR_CSR_UDRDY_Pos (18U)
+#define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
+#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
+/* Legacy define */
+#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN_Pos (0U)
+#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos (1U)
+#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos (2U)
+#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos (3U)
+#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos (4U)
+#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos (6U)
+#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
+#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos (7U)
+#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos (8U)
+#define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
+#define QUADSPI_CR_TEIE_Pos (16U)
+#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos (17U)
+#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos (18U)
+#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos (19U)
+#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos (20U)
+#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos (22U)
+#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos (23U)
+#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos (24U)
+#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE_Pos (0U)
+#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos (8U)
+#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos (16U)
+#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF_Pos (0U)
+#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos (1U)
+#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos (2U)
+#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos (3U)
+#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos (4U)
+#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos (5U)
+#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos (8U)
+#define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF_Pos (0U)
+#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos (1U)
+#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos (3U)
+#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos (4U)
+#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL_Pos (0U)
+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos (8U)
+#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos (10U)
+#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos (12U)
+#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos (14U)
+#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos (16U)
+#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos (18U)
+#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos (24U)
+#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos (26U)
+#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos (28U)
+#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos (30U)
+#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM_Pos (31U)
+#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS_Pos (0U)
+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA_Pos (0U)
+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK_Pos (0U)
+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH_Pos (0U)
+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL_Pos (0U)
+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
+
+#define RCC_CR_PLLSAION_Pos (28U)
+#define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
+#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
+#define RCC_CR_PLLSAIRDY_Pos (29U)
+#define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
+#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLR_SYSCLK_SUPPORT /*!< Support PLLR as system clock */
+#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
+
+#define RCC_PLLCFGR_PLLR_Pos (28U)
+#define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
+#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_PLLR 0x00000003U /*!< PLL/PLLR selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_PLLR 0x0000000CU /*!< PLL/PLLR used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_PLLSAIRDYF_Pos (6U)
+#define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
+#define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
+#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+#define RCC_CIR_PLLSAIRDYC_Pos (22U)
+#define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
+#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
+#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
+#define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1U << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
+#define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
+#define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
+#define RCC_APB1RSTR_CECRST_Pos (27U)
+#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_SAI2RST_Pos (23U)
+#define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
+#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_DCMIEN_Pos (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FMCEN_Pos (0U)
+#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos (1U)
+#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
+#define RCC_APB1ENR_SPDIFRXEN_Msk (0x1U << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
+#define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
+#define RCC_APB1ENR_CECEN_Pos (27U)
+#define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (1U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_ADC2EN_Pos (9U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
+#define RCC_APB2ENR_ADC3EN_Pos (10U)
+#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos (22U)
+#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_SAI2EN_Pos (23U)
+#define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
+#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
+#define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1U << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
+#define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
+#define RCC_APB1LPENR_CECLPEN_Pos (27U)
+#define RCC_APB1LPENR_CECLPEN_Msk (0x1U << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1U << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+#define RCC_BDCR_LSEMOD_Pos (3U)
+#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
+#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
+#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
+#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
+#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
+#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
+#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
+#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
+#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
+#define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
+#define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
+#define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
+#define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIM_Pos (0U)
+#define RCC_PLLSAICFGR_PLLSAIM_Msk (0x3FU << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x0000003F */
+#define RCC_PLLSAICFGR_PLLSAIM RCC_PLLSAICFGR_PLLSAIM_Msk
+#define RCC_PLLSAICFGR_PLLSAIM_0 (0x01U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000001 */
+#define RCC_PLLSAICFGR_PLLSAIM_1 (0x02U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000002 */
+#define RCC_PLLSAICFGR_PLLSAIM_2 (0x04U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000004 */
+#define RCC_PLLSAICFGR_PLLSAIM_3 (0x08U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000008 */
+#define RCC_PLLSAICFGR_PLLSAIM_4 (0x10U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000010 */
+#define RCC_PLLSAICFGR_PLLSAIM_5 (0x20U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000020 */
+#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
+#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
+#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
+#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
+#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
+#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
+#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
+#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
+#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
+#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
+
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
+#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
+#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
+#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
+
+#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
+#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
+#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
+#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
+#define RCC_DCKCFGR_SAI1SRC_Pos (20U)
+#define RCC_DCKCFGR_SAI1SRC_Msk (0x3U << RCC_DCKCFGR_SAI1SRC_Pos) /*!< 0x00300000 */
+#define RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_Msk
+#define RCC_DCKCFGR_SAI1SRC_0 (0x1U << RCC_DCKCFGR_SAI1SRC_Pos) /*!< 0x00100000 */
+#define RCC_DCKCFGR_SAI1SRC_1 (0x2U << RCC_DCKCFGR_SAI1SRC_Pos) /*!< 0x00200000 */
+#define RCC_DCKCFGR_SAI2SRC_Pos (22U)
+#define RCC_DCKCFGR_SAI2SRC_Msk (0x3U << RCC_DCKCFGR_SAI2SRC_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_Msk
+#define RCC_DCKCFGR_SAI2SRC_0 (0x1U << RCC_DCKCFGR_SAI2SRC_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR_SAI2SRC_1 (0x2U << RCC_DCKCFGR_SAI2SRC_Pos) /*!< 0x00800000 */
+
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+#define RCC_DCKCFGR_I2S1SRC_Pos (25U)
+#define RCC_DCKCFGR_I2S1SRC_Msk (0x3U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x06000000 */
+#define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
+#define RCC_DCKCFGR_I2S1SRC_0 (0x1U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x02000000 */
+#define RCC_DCKCFGR_I2S1SRC_1 (0x2U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x04000000 */
+
+#define RCC_DCKCFGR_I2S2SRC_Pos (27U)
+#define RCC_DCKCFGR_I2S2SRC_Msk (0x3U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x18000000 */
+#define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
+#define RCC_DCKCFGR_I2S2SRC_0 (0x1U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x08000000 */
+#define RCC_DCKCFGR_I2S2SRC_1 (0x2U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
+#define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
+#define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
+#define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
+#define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
+#define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
+#define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
+#define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1U << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
+#define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
+#define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
+#define RCC_CKGATENR_SPARE_CKEN_Msk (0x1U << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
+#define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
+#define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
+#define RCC_CKGATENR_SRAM_CKEN_Msk (0x1U << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
+#define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
+#define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
+#define RCC_CKGATENR_FLITF_CKEN_Msk (0x1U << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
+#define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
+#define RCC_CKGATENR_RCC_CKEN_Pos (6U)
+#define RCC_CKGATENR_RCC_CKEN_Msk (0x1U << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
+#define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
+#define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
+#define RCC_DCKCFGR2_CECSEL_Pos (26U)
+#define RCC_DCKCFGR2_CECSEL_Msk (0x1U << RCC_DCKCFGR2_CECSEL_Pos) /*!< 0x04000000 */
+#define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
+#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
+#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
+#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
+#define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
+#define RCC_DCKCFGR2_SDIOSEL_Msk (0x1U << RCC_DCKCFGR2_SDIOSEL_Pos) /*!< 0x10000000 */
+#define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
+#define RCC_DCKCFGR2_SPDIFRXSEL_Pos (29U)
+#define RCC_DCKCFGR2_SPDIFRXSEL_Msk (0x1U << RCC_DCKCFGR2_SPDIFRXSEL_Pos) /*!< 0x20000000 */
+#define RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_Msk
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
+#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_Pos (0U)
+#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos (4U)
+#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE_Pos (0U)
+#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos (2U)
+#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos (5U)
+#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
+#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
+#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos (8U)
+#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR_Pos (9U)
+#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN_Pos (10U)
+#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos (12U)
+#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV_Pos (13U)
+#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
+#define SAI_xCR1_SAIEN_Pos (16U)
+#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN_Pos (17U)
+#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
+#define SAI_xCR1_NODIV_Pos (19U)
+#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV_Pos (20U)
+#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH_Pos (0U)
+#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos (3U)
+#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS_Pos (4U)
+#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos (5U)
+#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL_Pos (6U)
+#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT_Pos (7U)
+#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos (13U)
+#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
+
+#define SAI_xCR2_COMP_Pos (14U)
+#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL_Pos (0U)
+#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos (8U)
+#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos (16U)
+#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos (17U)
+#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF_Pos (18U)
+#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF_Pos (0U)
+#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos (8U)
+#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos (16U)
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE_Pos (0U)
+#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE_Pos (1U)
+#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE_Pos (2U)
+#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE_Pos (3U)
+#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE_Pos (4U)
+#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE_Pos (5U)
+#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE_Pos (6U)
+#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR_Pos (0U)
+#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET_Pos (1U)
+#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
+#define SAI_xSR_WCKCFG_Pos (2U)
+#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ_Pos (3U)
+#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
+#define SAI_xSR_CNRDY_Pos (4U)
+#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
+#define SAI_xSR_AFSDET_Pos (5U)
+#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET_Pos (6U)
+#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL_Pos (16U)
+#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR_Pos (0U)
+#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ_Pos (3U)
+#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY_Pos (4U)
+#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET_Pos (5U)
+#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET_Pos (6U)
+#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA_Pos (0U)
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
+
+/******************************************************************************/
+/* */
+/* SPDIF-RX Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SPDIFRX_CR register *******************/
+#define SPDIFRX_CR_SPDIFEN_Pos (0U)
+#define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
+#define SPDIFRX_CR_RXDMAEN_Pos (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
+#define SPDIFRX_CR_RXSTEO_Pos (3U)
+#define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
+#define SPDIFRX_CR_DRFMT_Pos (4U)
+#define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
+#define SPDIFRX_CR_PMSK_Pos (6U)
+#define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
+#define SPDIFRX_CR_VMSK_Pos (7U)
+#define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
+#define SPDIFRX_CR_CUMSK_Pos (8U)
+#define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
+#define SPDIFRX_CR_PTMSK_Pos (9U)
+#define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
+#define SPDIFRX_CR_CBDMAEN_Pos (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
+#define SPDIFRX_CR_CHSEL_Pos (11U)
+#define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
+#define SPDIFRX_CR_NBTR_Pos (12U)
+#define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos (14U)
+#define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
+#define SPDIFRX_CR_INSEL_Pos (16U)
+#define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIFRX input selection */
+
+/******************* Bit definition for SPDIFRX_IMR register *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
+#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
+#define SPDIFRX_IMR_PERRIE_Pos (2U)
+#define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
+#define SPDIFRX_IMR_OVRIE_Pos (3U)
+#define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
+#define SPDIFRX_IMR_SBLKIE_Pos (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
+#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
+#define SPDIFRX_IMR_IFEIE_Pos (6U)
+#define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
+
+/******************* Bit definition for SPDIFRX_SR register *******************/
+#define SPDIFRX_SR_RXNE_Pos (0U)
+#define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
+#define SPDIFRX_SR_CSRNE_Pos (1U)
+#define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
+#define SPDIFRX_SR_PERR_Pos (2U)
+#define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
+#define SPDIFRX_SR_OVR_Pos (3U)
+#define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
+#define SPDIFRX_SR_SBD_Pos (4U)
+#define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
+#define SPDIFRX_SR_SYNCD_Pos (5U)
+#define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
+#define SPDIFRX_SR_FERR_Pos (6U)
+#define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
+#define SPDIFRX_SR_SERR_Pos (7U)
+#define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
+#define SPDIFRX_SR_TERR_Pos (8U)
+#define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
+#define SPDIFRX_SR_WIDTH5_Pos (16U)
+#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with SPDIFRX_clk */
+
+/******************* Bit definition for SPDIFRX_IFCR register *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
+#define SPDIFRX_IFCR_OVRCF_Pos (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
+#define SPDIFRX_IFCR_SBDCF_Pos (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
+#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos (0U)
+#define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
+#define SPDIFRX_DR0_PE_Pos (24U)
+#define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
+#define SPDIFRX_DR0_V_Pos (25U)
+#define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
+#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
+#define SPDIFRX_DR0_U_Pos (26U)
+#define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
+#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
+#define SPDIFRX_DR0_C_Pos (27U)
+#define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
+#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
+#define SPDIFRX_DR0_PT_Pos (28U)
+#define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos (8U)
+#define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
+#define SPDIFRX_DR1_PT_Pos (4U)
+#define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
+#define SPDIFRX_DR1_C_Pos (3U)
+#define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
+#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
+#define SPDIFRX_DR1_U_Pos (2U)
+#define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
+#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
+#define SPDIFRX_DR1_V_Pos (1U)
+#define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
+#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
+#define SPDIFRX_DR1_PE_Pos (0U)
+#define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos (16U)
+#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
+#define SPDIFRX_DR1_DRNL2_Pos (0U)
+#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
+
+/******************* Bit definition for SPDIFRX_CSR register *******************/
+#define SPDIFRX_CSR_USR_Pos (0U)
+#define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
+#define SPDIFRX_CSR_CS_Pos (16U)
+#define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
+#define SPDIFRX_CSR_SOB_Pos (24U)
+#define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
+
+/******************* Bit definition for SPDIFRX_DIR register *******************/
+#define SPDIFRX_DIR_THI_Pos (0U)
+#define SPDIFRX_DIR_THI_Msk (0x13FFU << SPDIFRX_DIR_THI_Pos) /*!< 0x000013FF */
+#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
+#define SPDIFRX_DIR_TLO_Pos (16U)
+#define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define I2S_APB1_APB2_FEATURE /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
+#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
+#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
+#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
+#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
+/* Legacy Defines */
+#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2_Pos (16U)
+#define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
+#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2_Pos (17U)
+#define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
+#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2_Pos (18U)
+#define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
+#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+/****************** Bit definition for SYSCFG_CFGR register ****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
+#define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
+#define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
+#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN_Pos (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL_Pos (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B) || \
+ ((PERIPH) == SAI2_Block_A) || \
+ ((PERIPH) == SAI2_Block_B))
+/* Legacy define */
+
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/******************************* CEC Instances ********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/******************************* SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 5U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 5U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLSAICFGR_RST_VALUE 0x04003010U
+
+#define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
+#define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+#define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+#define QuadSPI_IRQHandler QUADSPI_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F446xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ #define STM32F446xx /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE,
+ SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE,
+ CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,390 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 // Connected to WAKEUP [B2]
+ {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 // Connected to WAKEUP [B2]
+ {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 // Connected to WAKEUP [B2]
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
+ {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
+ {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+ {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+ {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to EXT_RESET
+ {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to EXT_RESET
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to SDNWE [MT48LC4M32B2B5-6A_WE]
+ {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to SDNWE [MT48LC4M32B2B5-6A_WE]
+ {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 // Connected to SDNWE [MT48LC4M32B2B5-6A_WE]
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
+ {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+ {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
+ {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
+ {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 // Connected to A3
+ {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 // Connected to A4
+ {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 // Connected to A5
+ {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
+ {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+ {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0]
+ {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1]
+ {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 // Connected to QSPI_CLK [N25Q128A13EF840F_C]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to OTG_FS1_OverCurrent [STMPS2151STR_FAULT]
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to I2C1_SDA
+// {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to STDIO_UART_RX
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to uSD_D1
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to A0
+ {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to I2C2_SDA [CS43L22_SDA]
+ {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to D16
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to I2C1_SCL
+// {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to STDIO_UART_TX
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to A1
+ {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to I2C2_SCL [CS43L22_SCL]
+ {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to GPIO_Output
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to WAKEUP [B2]
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to WAKEUP [B2]
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+ {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to VBUS_FS1
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_FS1_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_FS1_N
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to EXT_RESET
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to EXT_RESET
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to EXT_RESET
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to I2S3_CK
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to OTG_FS1_OverCurrent [STMPS2151STR_FAULT]
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to I2C1_SCL
+ {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 // Connected to I2C1_SCL
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to I2C1_SDA
+ {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to I2C1_SDA
+// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX
+// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to uSD_D0
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to uSD_D0
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to uSD_D1
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to uSD_D1
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to MIC_CK [MP34DT01TR_CLK]
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to D0
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to D1
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to SAI1_SCKA [CS43L22_CLK]
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to D5
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to D6
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to D7
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to D8
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to D9
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to D10
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to D11
+ {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
+ {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+ {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0]
+ {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1]
+ {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
+ {PH_9, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 // Connected to D17
+// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to D18
+// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to D19
+// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to D20
+ {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to D21
+ {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to D22
+ {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to D23
+// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to D24
+ {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to D26
+ {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to FMC_NBL3 [MT48LC4M32B2B5-6A_DQM3]
+ {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to D28
+ {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to D29
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to WAKEUP [B2]
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to VBUS_FS1
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+// {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_D2 // STDIO UART
+ {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to uSD_D2
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to uSD_CLK
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to LED3 [Red]
+// {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D13 // STDIO UART
+ {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_NBL1 [ MT48LC4M32B2B5-6A_DQM1]
+ {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to D5
+ {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to ARDUINO USART6_TX
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to LCD_BL_CTRL [STLD40DPUR_EN]
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_FS1_ID
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS1_OverCurrent [STMPS2151STR_FAULT]
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_D3 // STDIO UART
+ {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to uSD_D3
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to uSD_CMD
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to MIC_DATA [MP34DT01TR_DOUT]
+// {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D14 // STDIO UART
+ {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_NBL0 [ MT48LC4M32B2B5-6A_DQM0]
+ {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to D4
+ {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
+ {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to USART6_RX
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_FS1_P
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to LED2 [Orange]
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to SDCLK [MT48LC4M32B2B5-6A_CLK]
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to WAKEUP [B2]
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_FS1_N
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to SDNCAS [MT48LC4M32B2B5-6A_CAS]
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to uSD_CLK
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, // Connected to MIC_DATA [MP34DT01TR_DOUT]
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D11
+ {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1]
+ {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to SDNMT48LC4M32B2B5-6A_RAS]RAS [
+ {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to ARDUINO USART6_TX
+ {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to D27
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to uSD_D3
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to SAI1_SCKA [CS43L22_CLK]
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D10
+ {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0]
+ {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)},
+ {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to GPIO_Output
+ {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to D26
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to VBUS_FS1
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to I2S3_CK
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_CK
+// {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to STDIO_UART_TX
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to uSD_D2
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to AUDIO_RST [CS43L22_RESET]
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D9
+ {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+ {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)},
+ {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},
+ {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to D25
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to I2C1_SDA
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to SAI1_FSA [CS43L22_LRCK]
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D8
+ {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
+ {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to SDCLK [MT48LC4M32B2B5-6A_CLK]
+ {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to I2C2_SDA [CS43L22_SDA]
+ {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to D24
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_FS1_N
+ {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to I2C1_SCL
+ {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D2
+ {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D30
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_FS1_P
+ {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to I2C1_SDA
+ {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D3
+ {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D21
+ {NC, NC, 0}
+};
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,417 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_0_ALT0 = PA_0 | ALT0,
+ PA_0_ALT1 = PA_0 | ALT1,
+ PA_1 = 0x01,
+ PA_1_ALT0 = PA_1 | ALT0,
+ PA_1_ALT1 = PA_1 | ALT1,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_2_ALT1 = PA_2 | ALT1,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_3_ALT1 = PA_3 | ALT1,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_4_ALT1 = PB_4 | ALT1,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_5_ALT1 = PB_5 | ALT1,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_0_ALT0 = PC_0 | ALT0,
+ PC_0_ALT1 = PC_0 | ALT1,
+ PC_1 = 0x21,
+ PC_1_ALT0 = PC_1 | ALT0,
+ PC_1_ALT1 = PC_1 | ALT1,
+ PC_2 = 0x22,
+ PC_2_ALT0 = PC_2 | ALT0,
+ PC_2_ALT1 = PC_2 | ALT1,
+ PC_3 = 0x23,
+ PC_3_ALT0 = PC_3 | ALT0,
+ PC_3_ALT1 = PC_3 | ALT1,
+ PC_4 = 0x24,
+ PC_4_ALT0 = PC_4 | ALT0,
+ PC_5 = 0x25,
+ PC_5_ALT0 = PC_5 | ALT0,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+ PH_2 = 0x72,
+ PH_3 = 0x73,
+ PH_4 = 0x74,
+ PH_5 = 0x75,
+ PH_6 = 0x76,
+ PH_7 = 0x77,
+ PH_8 = 0x78,
+ PH_9 = 0x79,
+ PH_10 = 0x7A,
+ PH_11 = 0x7B,
+ PH_12 = 0x7C,
+ PH_13 = 0x7D,
+ PH_14 = 0x7E,
+ PH_15 = 0x7F,
+
+ PI_0 = 0x80,
+ PI_1 = 0x81,
+ PI_2 = 0x82,
+ PI_3 = 0x83,
+ PI_4 = 0x84,
+ PI_5 = 0x85,
+ PI_6 = 0x86,
+ PI_7 = 0x87,
+ PI_8 = 0x88,
+ PI_9 = 0x89,
+ PI_10 = 0x8A,
+ PI_11 = 0x8B,
+ PI_12 = 0x8C,
+ PI_13 = 0x8D,
+ PI_14 = 0x8E,
+ PI_15 = 0x8F,
+
+ PJ_0 = 0x90,
+ PJ_1 = 0x91,
+ PJ_2 = 0x92,
+ PJ_3 = 0x93,
+ PJ_4 = 0x94,
+ PJ_5 = 0x95,
+ PJ_12 = 0x9C,
+ PJ_13 = 0x9D,
+ PJ_14 = 0x9E,
+ PJ_15 = 0x9F,
+
+ PK_3 = 0xA3,
+ PK_4 = 0xA4,
+ PK_5 = 0xA5,
+ PK_6 = 0xA6,
+ PK_7 = 0xA7,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PB_1,
+ A1 = PC_2,
+ A2 = PC_3,
+ A3 = PC_4,
+ A4 = PC_5,
+ A5 = PA_4,
+ D0 = PG_9,
+ D1 = PG_14,
+ D2 = PG_13,
+ D3 = PA_1,
+ D4 = PG_12,
+ D5 = PA_2,
+ D6 = PA_6,
+ D7 = PG_11,
+ D8 = PG_10,
+ D9 = PA_7,
+ D10 = PH_6,
+ D11 = PB_15,
+ D12 = PB_14,
+ D13 = PD_3,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PB_10,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PB_11,
+#endif
+
+ // Generic signals namings
+ LED1 = PG_6,
+ LED2 = PD_4,
+ LED3 = PD_5,
+ LED4 = PK_3,
+ LED7 = PD_3,
+ LED_RED = LED1,
+ USER_BUTTON = PA_0,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PB_15,
+ SPI_MISO = PB_14,
+ SPI_SCK = PD_3,
+ SPI_CS = PH_6,
+ PWM_OUT = PA_1,
+
+ /**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_HS_DM = PB_14,
+ USB_OTG_HS_DP = PB_15,
+ USB_OTG_HS_ID = PB_12,
+ USB_OTG_HS_SOF = PA_4,
+ USB_OTG_HS_ULPI_CK = PA_5,
+ USB_OTG_HS_ULPI_D0 = PA_3,
+ USB_OTG_HS_ULPI_D1 = PB_0,
+ USB_OTG_HS_ULPI_D2 = PB_1,
+ USB_OTG_HS_ULPI_D3 = PB_10,
+ USB_OTG_HS_ULPI_D4 = PB_11,
+ USB_OTG_HS_ULPI_D5 = PB_12,
+ USB_OTG_HS_ULPI_D6 = PB_13,
+ USB_OTG_HS_ULPI_D7 = PB_5,
+ USB_OTG_HS_ULPI_DIR = PI_11,
+ USB_OTG_HS_ULPI_DIR_ALT0 = PC_2,
+ USB_OTG_HS_ULPI_NXT = PH_4,
+ USB_OTG_HS_ULPI_NXT_ALT0 = PC_3,
+ USB_OTG_HS_ULPI_STP = PC_0,
+ USB_OTG_HS_VBUS = PB_13,
+
+ /**** ETHERNET pins ****/
+ ETH_COL = PH_3,
+ ETH_COL_ALT0 = PA_3,
+ ETH_CRS = PH_2,
+ ETH_CRS_ALT0 = PA_0,
+ ETH_CRS_DV = PA_7,
+ ETH_MDC = PC_1,
+ ETH_MDIO = PA_2,
+ ETH_PPS_OUT = PB_5,
+ ETH_PPS_OUT_ALT0 = PG_8,
+ ETH_REF_CLK = PA_1,
+ ETH_RXD0 = PC_4,
+ ETH_RXD1 = PC_5,
+ ETH_RXD2 = PH_6,
+ ETH_RXD2_ALT0 = PB_0,
+ ETH_RXD3 = PH_7,
+ ETH_RXD3_ALT0 = PB_1,
+ ETH_RX_CLK = PA_1,
+ ETH_RX_DV = PA_7,
+ ETH_RX_ER = PI_10,
+ ETH_RX_ER_ALT0 = PB_10,
+ ETH_TXD0 = PG_13,
+ ETH_TXD0_ALT0 = PB_12,
+ ETH_TXD1 = PG_14,
+ ETH_TXD1_ALT0 = PB_13,
+ ETH_TXD2 = PC_2,
+ ETH_TXD3 = PE_2,
+ ETH_TXD3_ALT0 = PB_8,
+ ETH_TX_CLK = PC_3,
+ ETH_TX_EN = PG_11,
+ ETH_TX_EN_ALT0 = PB_11,
+
+ /**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+ /**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED0_ALT0 = PG_13,
+ SYS_TRACED0_ALT1 = PC_1,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED1_ALT0 = PG_14,
+ SYS_TRACED1_ALT1 = PC_8,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED2_ALT0 = PD_2,
+ SYS_TRACED3 = PC_12,
+ SYS_TRACED3_ALT0 = PE_6,
+ SYS_WKUP = PA_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,274 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 180
+ * AHBCLK (MHz) | 180
+ * APB1CLK (MHz) | 45
+ * APB2CLK (MHz) | 90
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_error.h"
+
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+//#define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)
+
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO2 pin(PC9) for debugging purpose
+#if DEBUG_MCO == 1
+ HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; //
+ RCC_OscInitStruct.PLL.PLLR = 2; //
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Activate the OverDrive to reach the 180 MHz Frequency
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLLSAI output as USB clock source
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ if (bypass == 0) {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ } else {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
+ }
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; //
+ RCC_OscInitStruct.PLL.PLLR = 6; //
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 180 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,447 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Description : STM32F469x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20050000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +QUADSPI_IRQHandler +DSI_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/stm32f469xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/stm32f469xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 2 MB FLASH (0x200000) + 320 KB SRAM (0x50000)
+LR_IROM1 0x08000000 0x200000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B4) (0x50000-0x1B4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,420 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Description : STM32F469x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20050000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +QUADSPI_IRQHandler +DSI_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/stm32f469xx.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/stm32f469xx.sct Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 2 MB FLASH (0x200000) + 320 KB SRAM (0x50000)
+LR_IROM1 0x08000000 0x200000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B4) (0x50000-0x1B4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/STM32F469XI.ld
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/STM32F469XI.ld Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2M
+ RAM (rwx) : ORIGIN = 0x200001B4, LENGTH = 320k - 0x1B4
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,577 @@ +/** + ****************************************************************************** + * @file startup_stm32f469xx.s + * @author MCD Application Team + * @brief STM32F469xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word DSI_IRQHandler /* DSI */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + + + +
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.S Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,702 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Description : STM32F469xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI Controller + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSI_IRQHandler + B DSI_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/stm32f469xx.icf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/stm32f469xx.icf Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,30 @@
+/* [ROM = 2mb = 0x200000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x081FFFFF;
+
+/* [RAM = 384kb = 0x60000] Vector table dynamic copy: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x200001B3; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x200001B4;
+define symbol __region_RAM_end__ = 0x2004FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x4000;
+define symbol __size_heap__ = 0x10000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/cmsis.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/cmsis_nvic.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/cmsis_nvic.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F429ZI +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 93 vectors = 372 bytes from 0x40 to 0x1B3 +// Total: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM +#define NVIC_NUM_VECTORS 109 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/flash_data.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/flash_data.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x200000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +/* Base address of the Flash sectors Bank 2 */ +#define ADDR_FLASH_SECTOR_12 ((uint32_t)0x08100000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_13 ((uint32_t)0x08104000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_14 ((uint32_t)0x08108000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_15 ((uint32_t)0x0810C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_16 ((uint32_t)0x08110000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_17 ((uint32_t)0x08120000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_18 ((uint32_t)0x08140000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_19 ((uint32_t)0x08160000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_20 ((uint32_t)0x08180000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_21 ((uint32_t)0x081A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_22 ((uint32_t)0x081C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_23 ((uint32_t)0x081E0000) /* Base @ of Sector 11, 128 Kbytes */ + + +#endif +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,20235 @@
+/**
+ ******************************************************************************
+ * @file stm32f469xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f469xx
+ * @{
+ */
+
+#ifndef __STM32F469xx_H
+#define __STM32F469xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+/* MBED */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT 1U /*!< FPU present */
+#endif /* __FPU_PRESENT */
+/* MBED */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
+ QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
+ DSI_IRQn = 92 /*!< DSI global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief DSI Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
+ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
+ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
+ __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
+ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
+ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
+ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
+ __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
+ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
+ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
+ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
+ __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
+ __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
+ __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
+ __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
+ __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
+ __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
+ __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
+ __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
+ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
+ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
+ __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
+ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
+ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
+ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
+ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
+ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
+ __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
+ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
+ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
+ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
+ __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
+ __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
+ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
+ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
+ __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
+ __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
+ __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
+ uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
+ __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
+ uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
+ __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
+ __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
+ uint32_t RESERVED5; /*!< Reserved, 0x114 */
+ __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
+ uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
+ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
+ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
+ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
+ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
+ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
+ __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
+ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
+ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
+ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
+ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
+ __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
+ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
+ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
+ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
+ __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
+ __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
+ __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
+ uint32_t RESERVED9; /*!< Reserved, 0x414 */
+ __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
+ uint32_t RESERVED10; /*!< Reserved, 0x42C */
+ __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
+} DSI_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1;
+ __IO uint32_t MACDBGR;
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
+} LTDC_Layer_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(160 KB) base address in the alias region */
+#define SRAM2_BASE 0x20028000U /*!< SRAM2(32 KB) base address in the alias region */
+#define SRAM3_BASE 0x20030000U /*!< SRAM3(128 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC123_COMMON_BASE
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
+#define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC123_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define DSI ((DSI_TypeDef *)DSI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos (1U)
+#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
+#define ADC_SR_JEOC_Pos (2U)
+#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos (5U)
+#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos (5U)
+#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos (7U)
+#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos (24U)
+#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
+#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos (26U)
+#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos (9U)
+#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos (10U)
+#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos (16U)
+#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos (20U)
+#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos (22U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos (24U)
+#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos (28U)
+#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos (30U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos (24U)
+#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_Pos (0U)
+#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos (1U)
+#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos (2U)
+#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos (3U)
+#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos (4U)
+#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos (5U)
+#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2_Pos (8U)
+#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos (9U)
+#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos (10U)
+#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos (11U)
+#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos (12U)
+#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos (13U)
+#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3_Pos (16U)
+#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos (17U)
+#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos (18U)
+#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos (19U)
+#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos (20U)
+#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos (21U)
+#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_Pos (0U)
+#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos (13U)
+#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos (14U)
+#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos (16U)
+#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos (22U)
+#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos (23U)
+#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_Pos (0U)
+#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos (16U)
+#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos (14U)
+#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos (15U)
+#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos (16U)
+#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos (17U)
+#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos (18U)
+#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos (19U)
+#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos (20U)
+#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos (21U)
+#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos (22U)
+#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos (23U)
+#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos (24U)
+#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos (25U)
+#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos (26U)
+#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos (27U)
+#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE_Pos (0U)
+#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos (1U)
+#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
+#define DCMI_CR_CM DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos (2U)
+#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos (3U)
+#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos (4U)
+#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos (5U)
+#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos (6U)
+#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos (7U)
+#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_OUTEN_Pos (13U)
+#define DCMI_CR_OUTEN_Msk (0x1U << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */
+#define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
+#define DCMI_CR_ENABLE_Pos (14U)
+#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_0 0x00010000U
+#define DCMI_CR_BSM_1 0x00020000U
+#define DCMI_CR_OEBS_Pos (18U)
+#define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
+#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos (19U)
+#define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
+#define DCMI_CR_LSM DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos (20U)
+#define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
+#define DCMI_CR_OELS DCMI_CR_OELS_Msk
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC_Pos (0U)
+#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos (1U)
+#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos (2U)
+#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS_Pos (0U)
+#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos (1U)
+#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos (2U)
+#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos (4U)
+#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE_Pos (0U)
+#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos (1U)
+#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos (2U)
+#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos (3U)
+#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos (4U)
+#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS_Pos (0U)
+#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos (1U)
+#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos (2U)
+#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos (4U)
+#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC_Pos (0U)
+#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos (1U)
+#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos (2U)
+#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos (4U)
+#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC_Pos (0U)
+#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos (8U)
+#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos (16U)
+#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos (24U)
+#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU_Pos (0U)
+#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos (8U)
+#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos (16U)
+#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos (24U)
+#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos (16U)
+#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos (16U)
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
+
+/******************** Bits definition for DCMI_DR register *********************/
+#define DCMI_DR_BYTE0_Pos (0U)
+#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos (8U)
+#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos (16U)
+#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos (24U)
+#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_Pos (25U)
+#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/****************** Bit definition for DMA_SxPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_SxM0AR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+
+/****************** Bit definition for DMA_SxM1AR register ********************/
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START_Pos (0U)
+#define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
+#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos (1U)
+#define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
+#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos (2U)
+#define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
+#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
+#define DMA2D_CR_TEIE_Pos (8U)
+#define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
+#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos (9U)
+#define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
+#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos (10U)
+#define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
+#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos (11U)
+#define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos (12U)
+#define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos (13U)
+#define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
+#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos (16U)
+#define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
+#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF_Pos (0U)
+#define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos (1U)
+#define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos (2U)
+#define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos (3U)
+#define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos (4U)
+#define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos (5U)
+#define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos (0U)
+#define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos (1U)
+#define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos (2U)
+#define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos (3U)
+#define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos (4U)
+#define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos (5U)
+#define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA_Pos (0U)
+#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO_Pos (0U)
+#define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA_Pos (0U)
+#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO_Pos (0U)
+#define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM_Pos (0U)
+#define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos (4U)
+#define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos (5U)
+#define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos (8U)
+#define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos (16U)
+#define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos (0U)
+#define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos (8U)
+#define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos (16U)
+#define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM_Pos (0U)
+#define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM_Pos (4U)
+#define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos (5U)
+#define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos (8U)
+#define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos (16U)
+#define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos (0U)
+#define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos (8U)
+#define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos (16U)
+#define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA_Pos (0U)
+#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA_Pos (0U)
+#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM_Pos (0U)
+#define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA_Pos (0U)
+#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO_Pos (0U)
+#define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
+#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL_Pos (0U)
+#define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos (16U)
+#define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW_Pos (0U)
+#define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN_Pos (0U)
+#define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos (8U)
+#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* Display Serial Interface (DSI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DSI_VR register *****************/
+#define DSI_VR_Pos (1U)
+#define DSI_VR_Msk (0x18999815U << DSI_VR_Pos) /*!< 0x3133302A */
+#define DSI_VR DSI_VR_Msk /*!< DSI Host Version */
+
+/******************* Bit definition for DSI_CR register *****************/
+#define DSI_CR_EN_Pos (0U)
+#define DSI_CR_EN_Msk (0x1U << DSI_CR_EN_Pos) /*!< 0x00000001 */
+#define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */
+
+/******************* Bit definition for DSI_CCR register ****************/
+#define DSI_CCR_TXECKDIV_Pos (0U)
+#define DSI_CCR_TXECKDIV_Msk (0xFFU << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */
+#define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0_Pos (0U)
+#define DSI_CCR_TXECKDIV0_Msk (0x1U << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */
+#define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
+#define DSI_CCR_TXECKDIV1_Pos (1U)
+#define DSI_CCR_TXECKDIV1_Msk (0x1U << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */
+#define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
+#define DSI_CCR_TXECKDIV2_Pos (2U)
+#define DSI_CCR_TXECKDIV2_Msk (0x1U << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */
+#define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
+#define DSI_CCR_TXECKDIV3_Pos (3U)
+#define DSI_CCR_TXECKDIV3_Msk (0x1U << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */
+#define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
+#define DSI_CCR_TXECKDIV4_Pos (4U)
+#define DSI_CCR_TXECKDIV4_Msk (0x1U << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */
+#define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
+#define DSI_CCR_TXECKDIV5_Pos (5U)
+#define DSI_CCR_TXECKDIV5_Msk (0x1U << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */
+#define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
+#define DSI_CCR_TXECKDIV6_Pos (6U)
+#define DSI_CCR_TXECKDIV6_Msk (0x1U << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */
+#define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
+#define DSI_CCR_TXECKDIV7_Pos (7U)
+#define DSI_CCR_TXECKDIV7_Msk (0x1U << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */
+#define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
+
+#define DSI_CCR_TOCKDIV_Pos (8U)
+#define DSI_CCR_TOCKDIV_Msk (0xFFU << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */
+#define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0_Pos (8U)
+#define DSI_CCR_TOCKDIV0_Msk (0x1U << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */
+#define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
+#define DSI_CCR_TOCKDIV1_Pos (9U)
+#define DSI_CCR_TOCKDIV1_Msk (0x1U << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */
+#define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
+#define DSI_CCR_TOCKDIV2_Pos (10U)
+#define DSI_CCR_TOCKDIV2_Msk (0x1U << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */
+#define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
+#define DSI_CCR_TOCKDIV3_Pos (11U)
+#define DSI_CCR_TOCKDIV3_Msk (0x1U << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */
+#define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
+#define DSI_CCR_TOCKDIV4_Pos (12U)
+#define DSI_CCR_TOCKDIV4_Msk (0x1U << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */
+#define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
+#define DSI_CCR_TOCKDIV5_Pos (13U)
+#define DSI_CCR_TOCKDIV5_Msk (0x1U << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */
+#define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
+#define DSI_CCR_TOCKDIV6_Pos (14U)
+#define DSI_CCR_TOCKDIV6_Msk (0x1U << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */
+#define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
+#define DSI_CCR_TOCKDIV7_Pos (15U)
+#define DSI_CCR_TOCKDIV7_Msk (0x1U << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */
+#define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
+
+/******************* Bit definition for DSI_LVCIDR register *************/
+#define DSI_LVCIDR_VCID_Pos (0U)
+#define DSI_LVCIDR_VCID_Msk (0x3U << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */
+#define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0_Pos (0U)
+#define DSI_LVCIDR_VCID0_Msk (0x1U << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */
+#define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
+#define DSI_LVCIDR_VCID1_Pos (1U)
+#define DSI_LVCIDR_VCID1_Msk (0x1U << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */
+#define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
+
+/******************* Bit definition for DSI_LCOLCR register *************/
+#define DSI_LCOLCR_COLC_Pos (0U)
+#define DSI_LCOLCR_COLC_Msk (0xFU << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */
+#define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */
+#define DSI_LCOLCR_COLC0_Pos (0U)
+#define DSI_LCOLCR_COLC0_Msk (0x1U << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */
+#define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
+#define DSI_LCOLCR_COLC1_Pos (5U)
+#define DSI_LCOLCR_COLC1_Msk (0x1U << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */
+#define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
+#define DSI_LCOLCR_COLC2_Pos (6U)
+#define DSI_LCOLCR_COLC2_Msk (0x1U << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */
+#define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
+#define DSI_LCOLCR_COLC3_Pos (7U)
+#define DSI_LCOLCR_COLC3_Msk (0x1U << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */
+#define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
+
+#define DSI_LCOLCR_LPE_Pos (8U)
+#define DSI_LCOLCR_LPE_Msk (0x1U << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
+#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
+
+/******************* Bit definition for DSI_LPCR register ***************/
+#define DSI_LPCR_DEP_Pos (0U)
+#define DSI_LPCR_DEP_Msk (0x1U << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */
+#define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP_Pos (1U)
+#define DSI_LPCR_VSP_Msk (0x1U << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */
+#define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP_Pos (2U)
+#define DSI_LPCR_HSP_Msk (0x1U << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */
+#define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */
+
+/******************* Bit definition for DSI_LPMCR register **************/
+#define DSI_LPMCR_VLPSIZE_Pos (0U)
+#define DSI_LPMCR_VLPSIZE_Msk (0xFFU << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */
+#define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0_Pos (0U)
+#define DSI_LPMCR_VLPSIZE0_Msk (0x1U << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */
+#define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
+#define DSI_LPMCR_VLPSIZE1_Pos (1U)
+#define DSI_LPMCR_VLPSIZE1_Msk (0x1U << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */
+#define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
+#define DSI_LPMCR_VLPSIZE2_Pos (2U)
+#define DSI_LPMCR_VLPSIZE2_Msk (0x1U << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */
+#define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
+#define DSI_LPMCR_VLPSIZE3_Pos (3U)
+#define DSI_LPMCR_VLPSIZE3_Msk (0x1U << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */
+#define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
+#define DSI_LPMCR_VLPSIZE4_Pos (4U)
+#define DSI_LPMCR_VLPSIZE4_Msk (0x1U << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */
+#define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
+#define DSI_LPMCR_VLPSIZE5_Pos (5U)
+#define DSI_LPMCR_VLPSIZE5_Msk (0x1U << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */
+#define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
+#define DSI_LPMCR_VLPSIZE6_Pos (6U)
+#define DSI_LPMCR_VLPSIZE6_Msk (0x1U << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */
+#define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
+#define DSI_LPMCR_VLPSIZE7_Pos (7U)
+#define DSI_LPMCR_VLPSIZE7_Msk (0x1U << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */
+#define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
+
+#define DSI_LPMCR_LPSIZE_Pos (16U)
+#define DSI_LPMCR_LPSIZE_Msk (0xFFU << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */
+#define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0_Pos (16U)
+#define DSI_LPMCR_LPSIZE0_Msk (0x1U << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */
+#define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
+#define DSI_LPMCR_LPSIZE1_Pos (17U)
+#define DSI_LPMCR_LPSIZE1_Msk (0x1U << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */
+#define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
+#define DSI_LPMCR_LPSIZE2_Pos (18U)
+#define DSI_LPMCR_LPSIZE2_Msk (0x1U << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */
+#define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
+#define DSI_LPMCR_LPSIZE3_Pos (19U)
+#define DSI_LPMCR_LPSIZE3_Msk (0x1U << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */
+#define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
+#define DSI_LPMCR_LPSIZE4_Pos (20U)
+#define DSI_LPMCR_LPSIZE4_Msk (0x1U << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */
+#define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
+#define DSI_LPMCR_LPSIZE5_Pos (21U)
+#define DSI_LPMCR_LPSIZE5_Msk (0x1U << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */
+#define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
+#define DSI_LPMCR_LPSIZE6_Pos (22U)
+#define DSI_LPMCR_LPSIZE6_Msk (0x1U << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */
+#define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
+#define DSI_LPMCR_LPSIZE7_Pos (23U)
+#define DSI_LPMCR_LPSIZE7_Msk (0x1U << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */
+#define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
+
+/******************* Bit definition for DSI_PCR register ****************/
+#define DSI_PCR_ETTXE_Pos (0U)
+#define DSI_PCR_ETTXE_Msk (0x1U << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */
+#define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE_Pos (1U)
+#define DSI_PCR_ETRXE_Msk (0x1U << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */
+#define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE_Pos (2U)
+#define DSI_PCR_BTAE_Msk (0x1U << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */
+#define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE_Pos (3U)
+#define DSI_PCR_ECCRXE_Msk (0x1U << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */
+#define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE_Pos (4U)
+#define DSI_PCR_CRCRXE_Msk (0x1U << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */
+#define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */
+
+/******************* Bit definition for DSI_GVCIDR register *************/
+#define DSI_GVCIDR_VCID_Pos (0U)
+#define DSI_GVCIDR_VCID_Msk (0x3U << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */
+#define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0_Pos (0U)
+#define DSI_GVCIDR_VCID0_Msk (0x1U << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */
+#define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
+#define DSI_GVCIDR_VCID1_Pos (1U)
+#define DSI_GVCIDR_VCID1_Msk (0x1U << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */
+#define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
+
+/******************* Bit definition for DSI_MCR register ****************/
+#define DSI_MCR_CMDM_Pos (0U)
+#define DSI_MCR_CMDM_Msk (0x1U << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */
+#define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */
+
+/******************* Bit definition for DSI_VMCR register ***************/
+#define DSI_VMCR_VMT_Pos (0U)
+#define DSI_VMCR_VMT_Msk (0x3U << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */
+#define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */
+#define DSI_VMCR_VMT0_Pos (0U)
+#define DSI_VMCR_VMT0_Msk (0x1U << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */
+#define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
+#define DSI_VMCR_VMT1_Pos (1U)
+#define DSI_VMCR_VMT1_Msk (0x1U << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */
+#define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
+
+#define DSI_VMCR_LPVSAE_Pos (8U)
+#define DSI_VMCR_LPVSAE_Msk (0x1U << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */
+#define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE_Pos (9U)
+#define DSI_VMCR_LPVBPE_Msk (0x1U << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */
+#define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE_Pos (10U)
+#define DSI_VMCR_LPVFPE_Msk (0x1U << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */
+#define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE_Pos (11U)
+#define DSI_VMCR_LPVAE_Msk (0x1U << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */
+#define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE_Pos (12U)
+#define DSI_VMCR_LPHBPE_Msk (0x1U << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */
+#define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE_Pos (13U)
+#define DSI_VMCR_LPHFPE_Msk (0x1U << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */
+#define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE_Pos (14U)
+#define DSI_VMCR_FBTAAE_Msk (0x1U << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */
+#define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE_Pos (15U)
+#define DSI_VMCR_LPCE_Msk (0x1U << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */
+#define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE_Pos (16U)
+#define DSI_VMCR_PGE_Msk (0x1U << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */
+#define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM_Pos (20U)
+#define DSI_VMCR_PGM_Msk (0x1U << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */
+#define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO_Pos (24U)
+#define DSI_VMCR_PGO_Msk (0x1U << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */
+#define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */
+
+/******************* Bit definition for DSI_VPCR register ***************/
+#define DSI_VPCR_VPSIZE_Pos (0U)
+#define DSI_VPCR_VPSIZE_Msk (0x3FFFU << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */
+#define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0_Pos (0U)
+#define DSI_VPCR_VPSIZE0_Msk (0x1U << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */
+#define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
+#define DSI_VPCR_VPSIZE1_Pos (1U)
+#define DSI_VPCR_VPSIZE1_Msk (0x1U << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */
+#define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
+#define DSI_VPCR_VPSIZE2_Pos (2U)
+#define DSI_VPCR_VPSIZE2_Msk (0x1U << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */
+#define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
+#define DSI_VPCR_VPSIZE3_Pos (3U)
+#define DSI_VPCR_VPSIZE3_Msk (0x1U << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */
+#define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
+#define DSI_VPCR_VPSIZE4_Pos (4U)
+#define DSI_VPCR_VPSIZE4_Msk (0x1U << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */
+#define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
+#define DSI_VPCR_VPSIZE5_Pos (5U)
+#define DSI_VPCR_VPSIZE5_Msk (0x1U << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */
+#define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
+#define DSI_VPCR_VPSIZE6_Pos (6U)
+#define DSI_VPCR_VPSIZE6_Msk (0x1U << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */
+#define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
+#define DSI_VPCR_VPSIZE7_Pos (7U)
+#define DSI_VPCR_VPSIZE7_Msk (0x1U << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */
+#define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
+#define DSI_VPCR_VPSIZE8_Pos (8U)
+#define DSI_VPCR_VPSIZE8_Msk (0x1U << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */
+#define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
+#define DSI_VPCR_VPSIZE9_Pos (9U)
+#define DSI_VPCR_VPSIZE9_Msk (0x1U << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */
+#define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
+#define DSI_VPCR_VPSIZE10_Pos (10U)
+#define DSI_VPCR_VPSIZE10_Msk (0x1U << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */
+#define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
+#define DSI_VPCR_VPSIZE11_Pos (11U)
+#define DSI_VPCR_VPSIZE11_Msk (0x1U << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */
+#define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
+#define DSI_VPCR_VPSIZE12_Pos (12U)
+#define DSI_VPCR_VPSIZE12_Msk (0x1U << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */
+#define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
+#define DSI_VPCR_VPSIZE13_Pos (13U)
+#define DSI_VPCR_VPSIZE13_Msk (0x1U << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */
+#define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
+
+/******************* Bit definition for DSI_VCCR register ***************/
+#define DSI_VCCR_NUMC_Pos (0U)
+#define DSI_VCCR_NUMC_Msk (0x1FFFU << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */
+#define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0_Pos (0U)
+#define DSI_VCCR_NUMC0_Msk (0x1U << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */
+#define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
+#define DSI_VCCR_NUMC1_Pos (1U)
+#define DSI_VCCR_NUMC1_Msk (0x1U << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */
+#define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
+#define DSI_VCCR_NUMC2_Pos (2U)
+#define DSI_VCCR_NUMC2_Msk (0x1U << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */
+#define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
+#define DSI_VCCR_NUMC3_Pos (3U)
+#define DSI_VCCR_NUMC3_Msk (0x1U << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */
+#define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
+#define DSI_VCCR_NUMC4_Pos (4U)
+#define DSI_VCCR_NUMC4_Msk (0x1U << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */
+#define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
+#define DSI_VCCR_NUMC5_Pos (5U)
+#define DSI_VCCR_NUMC5_Msk (0x1U << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */
+#define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
+#define DSI_VCCR_NUMC6_Pos (6U)
+#define DSI_VCCR_NUMC6_Msk (0x1U << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */
+#define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
+#define DSI_VCCR_NUMC7_Pos (7U)
+#define DSI_VCCR_NUMC7_Msk (0x1U << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */
+#define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
+#define DSI_VCCR_NUMC8_Pos (8U)
+#define DSI_VCCR_NUMC8_Msk (0x1U << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */
+#define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
+#define DSI_VCCR_NUMC9_Pos (9U)
+#define DSI_VCCR_NUMC9_Msk (0x1U << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */
+#define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
+#define DSI_VCCR_NUMC10_Pos (10U)
+#define DSI_VCCR_NUMC10_Msk (0x1U << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */
+#define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
+#define DSI_VCCR_NUMC11_Pos (11U)
+#define DSI_VCCR_NUMC11_Msk (0x1U << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */
+#define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
+#define DSI_VCCR_NUMC12_Pos (12U)
+#define DSI_VCCR_NUMC12_Msk (0x1U << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */
+#define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
+
+/******************* Bit definition for DSI_VNPCR register **************/
+#define DSI_VNPCR_NPSIZE_Pos (0U)
+#define DSI_VNPCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */
+#define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0_Pos (0U)
+#define DSI_VNPCR_NPSIZE0_Msk (0x1U << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */
+#define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
+#define DSI_VNPCR_NPSIZE1_Pos (1U)
+#define DSI_VNPCR_NPSIZE1_Msk (0x1U << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */
+#define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
+#define DSI_VNPCR_NPSIZE2_Pos (2U)
+#define DSI_VNPCR_NPSIZE2_Msk (0x1U << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */
+#define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
+#define DSI_VNPCR_NPSIZE3_Pos (3U)
+#define DSI_VNPCR_NPSIZE3_Msk (0x1U << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */
+#define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
+#define DSI_VNPCR_NPSIZE4_Pos (4U)
+#define DSI_VNPCR_NPSIZE4_Msk (0x1U << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */
+#define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
+#define DSI_VNPCR_NPSIZE5_Pos (5U)
+#define DSI_VNPCR_NPSIZE5_Msk (0x1U << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */
+#define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
+#define DSI_VNPCR_NPSIZE6_Pos (6U)
+#define DSI_VNPCR_NPSIZE6_Msk (0x1U << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */
+#define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
+#define DSI_VNPCR_NPSIZE7_Pos (7U)
+#define DSI_VNPCR_NPSIZE7_Msk (0x1U << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */
+#define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
+#define DSI_VNPCR_NPSIZE8_Pos (8U)
+#define DSI_VNPCR_NPSIZE8_Msk (0x1U << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */
+#define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
+#define DSI_VNPCR_NPSIZE9_Pos (9U)
+#define DSI_VNPCR_NPSIZE9_Msk (0x1U << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */
+#define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
+#define DSI_VNPCR_NPSIZE10_Pos (10U)
+#define DSI_VNPCR_NPSIZE10_Msk (0x1U << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */
+#define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
+#define DSI_VNPCR_NPSIZE11_Pos (11U)
+#define DSI_VNPCR_NPSIZE11_Msk (0x1U << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */
+#define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
+#define DSI_VNPCR_NPSIZE12_Pos (12U)
+#define DSI_VNPCR_NPSIZE12_Msk (0x1U << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */
+#define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
+
+/******************* Bit definition for DSI_VHSACR register *************/
+#define DSI_VHSACR_HSA_Pos (0U)
+#define DSI_VHSACR_HSA_Msk (0xFFFU << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */
+#define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0_Pos (0U)
+#define DSI_VHSACR_HSA0_Msk (0x1U << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */
+#define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
+#define DSI_VHSACR_HSA1_Pos (1U)
+#define DSI_VHSACR_HSA1_Msk (0x1U << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */
+#define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
+#define DSI_VHSACR_HSA2_Pos (2U)
+#define DSI_VHSACR_HSA2_Msk (0x1U << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */
+#define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
+#define DSI_VHSACR_HSA3_Pos (3U)
+#define DSI_VHSACR_HSA3_Msk (0x1U << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */
+#define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
+#define DSI_VHSACR_HSA4_Pos (4U)
+#define DSI_VHSACR_HSA4_Msk (0x1U << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */
+#define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
+#define DSI_VHSACR_HSA5_Pos (5U)
+#define DSI_VHSACR_HSA5_Msk (0x1U << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */
+#define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
+#define DSI_VHSACR_HSA6_Pos (6U)
+#define DSI_VHSACR_HSA6_Msk (0x1U << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */
+#define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
+#define DSI_VHSACR_HSA7_Pos (7U)
+#define DSI_VHSACR_HSA7_Msk (0x1U << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */
+#define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
+#define DSI_VHSACR_HSA8_Pos (8U)
+#define DSI_VHSACR_HSA8_Msk (0x1U << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */
+#define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
+#define DSI_VHSACR_HSA9_Pos (9U)
+#define DSI_VHSACR_HSA9_Msk (0x1U << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */
+#define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
+#define DSI_VHSACR_HSA10_Pos (10U)
+#define DSI_VHSACR_HSA10_Msk (0x1U << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */
+#define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
+#define DSI_VHSACR_HSA11_Pos (11U)
+#define DSI_VHSACR_HSA11_Msk (0x1U << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */
+#define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
+
+/******************* Bit definition for DSI_VHBPCR register *************/
+#define DSI_VHBPCR_HBP_Pos (0U)
+#define DSI_VHBPCR_HBP_Msk (0xFFFU << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */
+#define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0_Pos (0U)
+#define DSI_VHBPCR_HBP0_Msk (0x1U << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */
+#define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
+#define DSI_VHBPCR_HBP1_Pos (1U)
+#define DSI_VHBPCR_HBP1_Msk (0x1U << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */
+#define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
+#define DSI_VHBPCR_HBP2_Pos (2U)
+#define DSI_VHBPCR_HBP2_Msk (0x1U << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */
+#define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
+#define DSI_VHBPCR_HBP3_Pos (3U)
+#define DSI_VHBPCR_HBP3_Msk (0x1U << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */
+#define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
+#define DSI_VHBPCR_HBP4_Pos (4U)
+#define DSI_VHBPCR_HBP4_Msk (0x1U << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */
+#define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
+#define DSI_VHBPCR_HBP5_Pos (5U)
+#define DSI_VHBPCR_HBP5_Msk (0x1U << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */
+#define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
+#define DSI_VHBPCR_HBP6_Pos (6U)
+#define DSI_VHBPCR_HBP6_Msk (0x1U << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */
+#define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
+#define DSI_VHBPCR_HBP7_Pos (7U)
+#define DSI_VHBPCR_HBP7_Msk (0x1U << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */
+#define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
+#define DSI_VHBPCR_HBP8_Pos (8U)
+#define DSI_VHBPCR_HBP8_Msk (0x1U << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */
+#define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
+#define DSI_VHBPCR_HBP9_Pos (9U)
+#define DSI_VHBPCR_HBP9_Msk (0x1U << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */
+#define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
+#define DSI_VHBPCR_HBP10_Pos (10U)
+#define DSI_VHBPCR_HBP10_Msk (0x1U << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */
+#define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
+#define DSI_VHBPCR_HBP11_Pos (11U)
+#define DSI_VHBPCR_HBP11_Msk (0x1U << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */
+#define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
+
+/******************* Bit definition for DSI_VLCR register ***************/
+#define DSI_VLCR_HLINE_Pos (0U)
+#define DSI_VLCR_HLINE_Msk (0x7FFFU << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */
+#define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0_Pos (0U)
+#define DSI_VLCR_HLINE0_Msk (0x1U << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */
+#define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
+#define DSI_VLCR_HLINE1_Pos (1U)
+#define DSI_VLCR_HLINE1_Msk (0x1U << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */
+#define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
+#define DSI_VLCR_HLINE2_Pos (2U)
+#define DSI_VLCR_HLINE2_Msk (0x1U << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */
+#define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
+#define DSI_VLCR_HLINE3_Pos (3U)
+#define DSI_VLCR_HLINE3_Msk (0x1U << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */
+#define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
+#define DSI_VLCR_HLINE4_Pos (4U)
+#define DSI_VLCR_HLINE4_Msk (0x1U << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */
+#define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
+#define DSI_VLCR_HLINE5_Pos (5U)
+#define DSI_VLCR_HLINE5_Msk (0x1U << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */
+#define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
+#define DSI_VLCR_HLINE6_Pos (6U)
+#define DSI_VLCR_HLINE6_Msk (0x1U << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */
+#define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
+#define DSI_VLCR_HLINE7_Pos (7U)
+#define DSI_VLCR_HLINE7_Msk (0x1U << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */
+#define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
+#define DSI_VLCR_HLINE8_Pos (8U)
+#define DSI_VLCR_HLINE8_Msk (0x1U << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */
+#define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
+#define DSI_VLCR_HLINE9_Pos (9U)
+#define DSI_VLCR_HLINE9_Msk (0x1U << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */
+#define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
+#define DSI_VLCR_HLINE10_Pos (10U)
+#define DSI_VLCR_HLINE10_Msk (0x1U << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */
+#define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
+#define DSI_VLCR_HLINE11_Pos (11U)
+#define DSI_VLCR_HLINE11_Msk (0x1U << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */
+#define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
+#define DSI_VLCR_HLINE12_Pos (12U)
+#define DSI_VLCR_HLINE12_Msk (0x1U << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */
+#define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
+#define DSI_VLCR_HLINE13_Pos (13U)
+#define DSI_VLCR_HLINE13_Msk (0x1U << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */
+#define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
+#define DSI_VLCR_HLINE14_Pos (14U)
+#define DSI_VLCR_HLINE14_Msk (0x1U << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */
+#define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
+
+/******************* Bit definition for DSI_VVSACR register *************/
+#define DSI_VVSACR_VSA_Pos (0U)
+#define DSI_VVSACR_VSA_Msk (0x3FFU << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */
+#define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0_Pos (0U)
+#define DSI_VVSACR_VSA0_Msk (0x1U << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */
+#define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
+#define DSI_VVSACR_VSA1_Pos (1U)
+#define DSI_VVSACR_VSA1_Msk (0x1U << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */
+#define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
+#define DSI_VVSACR_VSA2_Pos (2U)
+#define DSI_VVSACR_VSA2_Msk (0x1U << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */
+#define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
+#define DSI_VVSACR_VSA3_Pos (3U)
+#define DSI_VVSACR_VSA3_Msk (0x1U << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */
+#define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
+#define DSI_VVSACR_VSA4_Pos (4U)
+#define DSI_VVSACR_VSA4_Msk (0x1U << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */
+#define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
+#define DSI_VVSACR_VSA5_Pos (5U)
+#define DSI_VVSACR_VSA5_Msk (0x1U << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */
+#define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
+#define DSI_VVSACR_VSA6_Pos (6U)
+#define DSI_VVSACR_VSA6_Msk (0x1U << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */
+#define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
+#define DSI_VVSACR_VSA7_Pos (7U)
+#define DSI_VVSACR_VSA7_Msk (0x1U << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */
+#define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
+#define DSI_VVSACR_VSA8_Pos (8U)
+#define DSI_VVSACR_VSA8_Msk (0x1U << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */
+#define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
+#define DSI_VVSACR_VSA9_Pos (9U)
+#define DSI_VVSACR_VSA9_Msk (0x1U << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */
+#define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
+
+/******************* Bit definition for DSI_VVBPCR register *************/
+#define DSI_VVBPCR_VBP_Pos (0U)
+#define DSI_VVBPCR_VBP_Msk (0x3FFU << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */
+#define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0_Pos (0U)
+#define DSI_VVBPCR_VBP0_Msk (0x1U << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */
+#define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
+#define DSI_VVBPCR_VBP1_Pos (1U)
+#define DSI_VVBPCR_VBP1_Msk (0x1U << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */
+#define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
+#define DSI_VVBPCR_VBP2_Pos (2U)
+#define DSI_VVBPCR_VBP2_Msk (0x1U << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */
+#define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
+#define DSI_VVBPCR_VBP3_Pos (3U)
+#define DSI_VVBPCR_VBP3_Msk (0x1U << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */
+#define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
+#define DSI_VVBPCR_VBP4_Pos (4U)
+#define DSI_VVBPCR_VBP4_Msk (0x1U << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */
+#define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
+#define DSI_VVBPCR_VBP5_Pos (5U)
+#define DSI_VVBPCR_VBP5_Msk (0x1U << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */
+#define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
+#define DSI_VVBPCR_VBP6_Pos (6U)
+#define DSI_VVBPCR_VBP6_Msk (0x1U << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */
+#define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
+#define DSI_VVBPCR_VBP7_Pos (7U)
+#define DSI_VVBPCR_VBP7_Msk (0x1U << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */
+#define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
+#define DSI_VVBPCR_VBP8_Pos (8U)
+#define DSI_VVBPCR_VBP8_Msk (0x1U << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */
+#define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
+#define DSI_VVBPCR_VBP9_Pos (9U)
+#define DSI_VVBPCR_VBP9_Msk (0x1U << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */
+#define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
+
+/******************* Bit definition for DSI_VVFPCR register *************/
+#define DSI_VVFPCR_VFP_Pos (0U)
+#define DSI_VVFPCR_VFP_Msk (0x3FFU << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */
+#define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0_Pos (0U)
+#define DSI_VVFPCR_VFP0_Msk (0x1U << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */
+#define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
+#define DSI_VVFPCR_VFP1_Pos (1U)
+#define DSI_VVFPCR_VFP1_Msk (0x1U << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */
+#define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
+#define DSI_VVFPCR_VFP2_Pos (2U)
+#define DSI_VVFPCR_VFP2_Msk (0x1U << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */
+#define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
+#define DSI_VVFPCR_VFP3_Pos (3U)
+#define DSI_VVFPCR_VFP3_Msk (0x1U << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */
+#define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
+#define DSI_VVFPCR_VFP4_Pos (4U)
+#define DSI_VVFPCR_VFP4_Msk (0x1U << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */
+#define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
+#define DSI_VVFPCR_VFP5_Pos (5U)
+#define DSI_VVFPCR_VFP5_Msk (0x1U << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */
+#define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
+#define DSI_VVFPCR_VFP6_Pos (6U)
+#define DSI_VVFPCR_VFP6_Msk (0x1U << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */
+#define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
+#define DSI_VVFPCR_VFP7_Pos (7U)
+#define DSI_VVFPCR_VFP7_Msk (0x1U << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */
+#define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
+#define DSI_VVFPCR_VFP8_Pos (8U)
+#define DSI_VVFPCR_VFP8_Msk (0x1U << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */
+#define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
+#define DSI_VVFPCR_VFP9_Pos (9U)
+#define DSI_VVFPCR_VFP9_Msk (0x1U << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */
+#define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
+
+/******************* Bit definition for DSI_VVACR register **************/
+#define DSI_VVACR_VA_Pos (0U)
+#define DSI_VVACR_VA_Msk (0x3FFFU << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */
+#define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */
+#define DSI_VVACR_VA0_Pos (0U)
+#define DSI_VVACR_VA0_Msk (0x1U << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */
+#define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
+#define DSI_VVACR_VA1_Pos (1U)
+#define DSI_VVACR_VA1_Msk (0x1U << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */
+#define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
+#define DSI_VVACR_VA2_Pos (2U)
+#define DSI_VVACR_VA2_Msk (0x1U << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */
+#define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
+#define DSI_VVACR_VA3_Pos (3U)
+#define DSI_VVACR_VA3_Msk (0x1U << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */
+#define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
+#define DSI_VVACR_VA4_Pos (4U)
+#define DSI_VVACR_VA4_Msk (0x1U << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */
+#define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
+#define DSI_VVACR_VA5_Pos (5U)
+#define DSI_VVACR_VA5_Msk (0x1U << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */
+#define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
+#define DSI_VVACR_VA6_Pos (6U)
+#define DSI_VVACR_VA6_Msk (0x1U << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */
+#define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
+#define DSI_VVACR_VA7_Pos (7U)
+#define DSI_VVACR_VA7_Msk (0x1U << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */
+#define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
+#define DSI_VVACR_VA8_Pos (8U)
+#define DSI_VVACR_VA8_Msk (0x1U << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */
+#define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
+#define DSI_VVACR_VA9_Pos (9U)
+#define DSI_VVACR_VA9_Msk (0x1U << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */
+#define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
+#define DSI_VVACR_VA10_Pos (10U)
+#define DSI_VVACR_VA10_Msk (0x1U << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */
+#define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
+#define DSI_VVACR_VA11_Pos (11U)
+#define DSI_VVACR_VA11_Msk (0x1U << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */
+#define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
+#define DSI_VVACR_VA12_Pos (12U)
+#define DSI_VVACR_VA12_Msk (0x1U << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */
+#define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
+#define DSI_VVACR_VA13_Pos (13U)
+#define DSI_VVACR_VA13_Msk (0x1U << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */
+#define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
+
+/******************* Bit definition for DSI_LCCR register ***************/
+#define DSI_LCCR_CMDSIZE_Pos (0U)
+#define DSI_LCCR_CMDSIZE_Msk (0xFFFFU << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */
+#define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0_Pos (0U)
+#define DSI_LCCR_CMDSIZE0_Msk (0x1U << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */
+#define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
+#define DSI_LCCR_CMDSIZE1_Pos (1U)
+#define DSI_LCCR_CMDSIZE1_Msk (0x1U << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */
+#define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
+#define DSI_LCCR_CMDSIZE2_Pos (2U)
+#define DSI_LCCR_CMDSIZE2_Msk (0x1U << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */
+#define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
+#define DSI_LCCR_CMDSIZE3_Pos (3U)
+#define DSI_LCCR_CMDSIZE3_Msk (0x1U << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */
+#define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
+#define DSI_LCCR_CMDSIZE4_Pos (4U)
+#define DSI_LCCR_CMDSIZE4_Msk (0x1U << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */
+#define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
+#define DSI_LCCR_CMDSIZE5_Pos (5U)
+#define DSI_LCCR_CMDSIZE5_Msk (0x1U << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */
+#define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
+#define DSI_LCCR_CMDSIZE6_Pos (6U)
+#define DSI_LCCR_CMDSIZE6_Msk (0x1U << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */
+#define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
+#define DSI_LCCR_CMDSIZE7_Pos (7U)
+#define DSI_LCCR_CMDSIZE7_Msk (0x1U << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */
+#define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
+#define DSI_LCCR_CMDSIZE8_Pos (8U)
+#define DSI_LCCR_CMDSIZE8_Msk (0x1U << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */
+#define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
+#define DSI_LCCR_CMDSIZE9_Pos (9U)
+#define DSI_LCCR_CMDSIZE9_Msk (0x1U << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */
+#define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
+#define DSI_LCCR_CMDSIZE10_Pos (10U)
+#define DSI_LCCR_CMDSIZE10_Msk (0x1U << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */
+#define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
+#define DSI_LCCR_CMDSIZE11_Pos (11U)
+#define DSI_LCCR_CMDSIZE11_Msk (0x1U << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */
+#define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
+#define DSI_LCCR_CMDSIZE12_Pos (12U)
+#define DSI_LCCR_CMDSIZE12_Msk (0x1U << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */
+#define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
+#define DSI_LCCR_CMDSIZE13_Pos (13U)
+#define DSI_LCCR_CMDSIZE13_Msk (0x1U << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */
+#define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
+#define DSI_LCCR_CMDSIZE14_Pos (14U)
+#define DSI_LCCR_CMDSIZE14_Msk (0x1U << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */
+#define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
+#define DSI_LCCR_CMDSIZE15_Pos (15U)
+#define DSI_LCCR_CMDSIZE15_Msk (0x1U << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */
+#define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
+
+/******************* Bit definition for DSI_CMCR register ***************/
+#define DSI_CMCR_TEARE_Pos (0U)
+#define DSI_CMCR_TEARE_Msk (0x1U << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */
+#define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE_Pos (1U)
+#define DSI_CMCR_ARE_Msk (0x1U << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */
+#define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX_Pos (8U)
+#define DSI_CMCR_GSW0TX_Msk (0x1U << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */
+#define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX_Pos (9U)
+#define DSI_CMCR_GSW1TX_Msk (0x1U << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */
+#define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX_Pos (10U)
+#define DSI_CMCR_GSW2TX_Msk (0x1U << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */
+#define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX_Pos (11U)
+#define DSI_CMCR_GSR0TX_Msk (0x1U << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */
+#define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX_Pos (12U)
+#define DSI_CMCR_GSR1TX_Msk (0x1U << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */
+#define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX_Pos (13U)
+#define DSI_CMCR_GSR2TX_Msk (0x1U << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */
+#define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX_Pos (14U)
+#define DSI_CMCR_GLWTX_Msk (0x1U << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */
+#define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX_Pos (16U)
+#define DSI_CMCR_DSW0TX_Msk (0x1U << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */
+#define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX_Pos (17U)
+#define DSI_CMCR_DSW1TX_Msk (0x1U << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */
+#define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX_Pos (18U)
+#define DSI_CMCR_DSR0TX_Msk (0x1U << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */
+#define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX_Pos (19U)
+#define DSI_CMCR_DLWTX_Msk (0x1U << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */
+#define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS_Pos (24U)
+#define DSI_CMCR_MRDPS_Msk (0x1U << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */
+#define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */
+
+/******************* Bit definition for DSI_GHCR register ***************/
+#define DSI_GHCR_DT_Pos (0U)
+#define DSI_GHCR_DT_Msk (0x3FU << DSI_GHCR_DT_Pos) /*!< 0x0000003F */
+#define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */
+#define DSI_GHCR_DT0_Pos (0U)
+#define DSI_GHCR_DT0_Msk (0x1U << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */
+#define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
+#define DSI_GHCR_DT1_Pos (1U)
+#define DSI_GHCR_DT1_Msk (0x1U << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */
+#define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
+#define DSI_GHCR_DT2_Pos (2U)
+#define DSI_GHCR_DT2_Msk (0x1U << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */
+#define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
+#define DSI_GHCR_DT3_Pos (3U)
+#define DSI_GHCR_DT3_Msk (0x1U << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */
+#define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
+#define DSI_GHCR_DT4_Pos (4U)
+#define DSI_GHCR_DT4_Msk (0x1U << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */
+#define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
+#define DSI_GHCR_DT5_Pos (5U)
+#define DSI_GHCR_DT5_Msk (0x1U << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */
+#define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
+
+#define DSI_GHCR_VCID_Pos (6U)
+#define DSI_GHCR_VCID_Msk (0x3U << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */
+#define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */
+#define DSI_GHCR_VCID0_Pos (6U)
+#define DSI_GHCR_VCID0_Msk (0x1U << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */
+#define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
+#define DSI_GHCR_VCID1_Pos (7U)
+#define DSI_GHCR_VCID1_Msk (0x1U << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */
+#define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
+
+#define DSI_GHCR_WCLSB_Pos (8U)
+#define DSI_GHCR_WCLSB_Msk (0xFFU << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */
+#define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0_Pos (8U)
+#define DSI_GHCR_WCLSB0_Msk (0x1U << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */
+#define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
+#define DSI_GHCR_WCLSB1_Pos (9U)
+#define DSI_GHCR_WCLSB1_Msk (0x1U << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */
+#define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
+#define DSI_GHCR_WCLSB2_Pos (10U)
+#define DSI_GHCR_WCLSB2_Msk (0x1U << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */
+#define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
+#define DSI_GHCR_WCLSB3_Pos (11U)
+#define DSI_GHCR_WCLSB3_Msk (0x1U << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */
+#define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
+#define DSI_GHCR_WCLSB4_Pos (12U)
+#define DSI_GHCR_WCLSB4_Msk (0x1U << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */
+#define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
+#define DSI_GHCR_WCLSB5_Pos (13U)
+#define DSI_GHCR_WCLSB5_Msk (0x1U << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */
+#define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
+#define DSI_GHCR_WCLSB6_Pos (14U)
+#define DSI_GHCR_WCLSB6_Msk (0x1U << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */
+#define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
+#define DSI_GHCR_WCLSB7_Pos (15U)
+#define DSI_GHCR_WCLSB7_Msk (0x1U << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */
+#define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
+
+#define DSI_GHCR_WCMSB_Pos (16U)
+#define DSI_GHCR_WCMSB_Msk (0xFFU << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */
+#define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0_Pos (16U)
+#define DSI_GHCR_WCMSB0_Msk (0x1U << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */
+#define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
+#define DSI_GHCR_WCMSB1_Pos (17U)
+#define DSI_GHCR_WCMSB1_Msk (0x1U << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */
+#define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
+#define DSI_GHCR_WCMSB2_Pos (18U)
+#define DSI_GHCR_WCMSB2_Msk (0x1U << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */
+#define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
+#define DSI_GHCR_WCMSB3_Pos (19U)
+#define DSI_GHCR_WCMSB3_Msk (0x1U << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */
+#define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
+#define DSI_GHCR_WCMSB4_Pos (20U)
+#define DSI_GHCR_WCMSB4_Msk (0x1U << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */
+#define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
+#define DSI_GHCR_WCMSB5_Pos (21U)
+#define DSI_GHCR_WCMSB5_Msk (0x1U << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */
+#define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
+#define DSI_GHCR_WCMSB6_Pos (22U)
+#define DSI_GHCR_WCMSB6_Msk (0x1U << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */
+#define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
+#define DSI_GHCR_WCMSB7_Pos (23U)
+#define DSI_GHCR_WCMSB7_Msk (0x1U << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */
+#define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
+
+/******************* Bit definition for DSI_GPDR register ***************/
+#define DSI_GPDR_DATA1_Pos (0U)
+#define DSI_GPDR_DATA1_Msk (0xFFU << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */
+#define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0 (0x01U << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */
+#define DSI_GPDR_DATA1_1 (0x02U << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */
+#define DSI_GPDR_DATA1_2 (0x04U << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */
+#define DSI_GPDR_DATA1_3 (0x08U << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */
+#define DSI_GPDR_DATA1_4 (0x10U << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */
+#define DSI_GPDR_DATA1_5 (0x20U << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */
+#define DSI_GPDR_DATA1_6 (0x40U << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */
+#define DSI_GPDR_DATA1_7 (0x80U << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */
+
+#define DSI_GPDR_DATA2_Pos (8U)
+#define DSI_GPDR_DATA2_Msk (0xFFU << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
+#define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0 (0x01U << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
+#define DSI_GPDR_DATA2_1 (0x02U << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
+#define DSI_GPDR_DATA2_2 (0x04U << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
+#define DSI_GPDR_DATA2_3 (0x08U << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
+#define DSI_GPDR_DATA2_4 (0x10U << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
+#define DSI_GPDR_DATA2_5 (0x20U << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
+#define DSI_GPDR_DATA2_6 (0x40U << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
+#define DSI_GPDR_DATA2_7 (0x80U << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
+
+#define DSI_GPDR_DATA3_Pos (16U)
+#define DSI_GPDR_DATA3_Msk (0xFFU << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
+#define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0 (0x01U << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
+#define DSI_GPDR_DATA3_1 (0x02U << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
+#define DSI_GPDR_DATA3_2 (0x04U << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
+#define DSI_GPDR_DATA3_3 (0x08U << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
+#define DSI_GPDR_DATA3_4 (0x10U << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
+#define DSI_GPDR_DATA3_5 (0x20U << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
+#define DSI_GPDR_DATA3_6 (0x40U << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
+#define DSI_GPDR_DATA3_7 (0x80U << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
+
+#define DSI_GPDR_DATA4_Pos (24U)
+#define DSI_GPDR_DATA4_Msk (0xFFU << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */
+#define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0 (0x01U << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */
+#define DSI_GPDR_DATA4_1 (0x02U << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */
+#define DSI_GPDR_DATA4_2 (0x04U << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */
+#define DSI_GPDR_DATA4_3 (0x08U << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */
+#define DSI_GPDR_DATA4_4 (0x10U << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */
+#define DSI_GPDR_DATA4_5 (0x20U << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */
+#define DSI_GPDR_DATA4_6 (0x40U << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */
+#define DSI_GPDR_DATA4_7 (0x80U << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for DSI_GPSR register ***************/
+#define DSI_GPSR_CMDFE_Pos (0U)
+#define DSI_GPSR_CMDFE_Msk (0x1U << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */
+#define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF_Pos (1U)
+#define DSI_GPSR_CMDFF_Msk (0x1U << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */
+#define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE_Pos (2U)
+#define DSI_GPSR_PWRFE_Msk (0x1U << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */
+#define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF_Pos (3U)
+#define DSI_GPSR_PWRFF_Msk (0x1U << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */
+#define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE_Pos (4U)
+#define DSI_GPSR_PRDFE_Msk (0x1U << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */
+#define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF_Pos (5U)
+#define DSI_GPSR_PRDFF_Msk (0x1U << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */
+#define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB_Pos (6U)
+#define DSI_GPSR_RCB_Msk (0x1U << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */
+#define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */
+
+/******************* Bit definition for DSI_TCCR0 register **************/
+#define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
+#define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */
+#define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
+#define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */
+#define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
+#define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
+#define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */
+#define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
+#define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
+#define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */
+#define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
+#define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
+#define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */
+#define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
+#define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
+#define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */
+#define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
+#define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
+#define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */
+#define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
+#define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
+#define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */
+#define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
+#define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
+#define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */
+#define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
+#define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
+#define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */
+#define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
+#define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
+#define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */
+#define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
+#define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
+#define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */
+#define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
+#define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
+#define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */
+#define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
+#define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
+#define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */
+#define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
+#define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
+#define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */
+#define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
+#define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
+#define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */
+#define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
+#define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
+#define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */
+#define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
+
+#define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
+#define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */
+#define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
+#define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */
+#define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
+#define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
+#define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */
+#define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
+#define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
+#define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */
+#define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
+#define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
+#define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */
+#define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
+#define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
+#define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */
+#define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
+#define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
+#define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */
+#define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
+#define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
+#define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */
+#define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
+#define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
+#define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */
+#define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
+#define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
+#define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */
+#define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
+#define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
+#define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */
+#define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
+#define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
+#define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */
+#define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
+#define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
+#define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */
+#define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
+#define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
+#define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */
+#define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
+#define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
+#define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */
+#define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
+#define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
+#define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */
+#define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
+#define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
+#define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */
+#define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
+
+/******************* Bit definition for DSI_TCCR1 register **************/
+#define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
+#define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFU << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */
+#define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
+#define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */
+#define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
+#define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
+#define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */
+#define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
+#define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
+#define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */
+#define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
+#define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
+#define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */
+#define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
+#define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
+#define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */
+#define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
+#define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
+#define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */
+#define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
+#define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
+#define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */
+#define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
+#define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
+#define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */
+#define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
+#define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
+#define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */
+#define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
+#define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
+#define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */
+#define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
+#define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
+#define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */
+#define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
+#define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
+#define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */
+#define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
+#define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
+#define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */
+#define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
+#define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
+#define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */
+#define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
+#define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
+#define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */
+#define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
+#define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
+#define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */
+#define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
+
+/******************* Bit definition for DSI_TCCR2 register **************/
+#define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
+#define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFU << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */
+#define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
+#define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */
+#define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
+#define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
+#define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */
+#define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
+#define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
+#define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */
+#define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
+#define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
+#define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */
+#define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
+#define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
+#define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */
+#define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
+#define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
+#define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */
+#define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
+#define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
+#define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */
+#define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
+#define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
+#define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */
+#define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
+#define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
+#define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */
+#define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
+#define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
+#define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */
+#define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
+#define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
+#define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */
+#define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
+#define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
+#define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */
+#define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
+#define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
+#define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */
+#define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
+#define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
+#define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */
+#define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
+#define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
+#define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */
+#define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
+#define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
+#define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */
+#define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
+
+/******************* Bit definition for DSI_TCCR3 register **************/
+#define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
+#define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFU << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */
+#define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
+#define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */
+#define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
+#define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
+#define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */
+#define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
+#define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
+#define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */
+#define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
+#define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
+#define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */
+#define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
+#define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
+#define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */
+#define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
+#define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
+#define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */
+#define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
+#define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
+#define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */
+#define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
+#define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
+#define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */
+#define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
+#define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
+#define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */
+#define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
+#define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
+#define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */
+#define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
+#define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
+#define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */
+#define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
+#define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
+#define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */
+#define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
+#define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
+#define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */
+#define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
+#define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
+#define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */
+#define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
+#define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
+#define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */
+#define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
+#define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
+#define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */
+#define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
+
+#define DSI_TCCR3_PM_Pos (24U)
+#define DSI_TCCR3_PM_Msk (0x1U << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */
+#define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */
+
+/******************* Bit definition for DSI_TCCR4 register **************/
+#define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
+#define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFU << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */
+#define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
+#define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */
+#define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
+#define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
+#define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */
+#define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
+#define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
+#define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */
+#define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
+#define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
+#define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */
+#define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
+#define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
+#define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */
+#define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
+#define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
+#define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */
+#define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
+#define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
+#define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */
+#define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
+#define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
+#define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */
+#define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
+#define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
+#define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */
+#define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
+#define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
+#define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */
+#define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
+#define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
+#define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */
+#define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
+#define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
+#define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */
+#define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
+#define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
+#define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */
+#define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
+#define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
+#define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */
+#define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
+#define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
+#define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */
+#define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
+#define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
+#define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */
+#define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
+
+/******************* Bit definition for DSI_TCCR5 register **************/
+#define DSI_TCCR5_BTA_TOCNT_Pos (0U)
+#define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFU << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */
+#define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
+#define DSI_TCCR5_BTA_TOCNT0_Msk (0x1U << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */
+#define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
+#define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
+#define DSI_TCCR5_BTA_TOCNT1_Msk (0x1U << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */
+#define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
+#define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
+#define DSI_TCCR5_BTA_TOCNT2_Msk (0x1U << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */
+#define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
+#define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
+#define DSI_TCCR5_BTA_TOCNT3_Msk (0x1U << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */
+#define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
+#define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
+#define DSI_TCCR5_BTA_TOCNT4_Msk (0x1U << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */
+#define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
+#define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
+#define DSI_TCCR5_BTA_TOCNT5_Msk (0x1U << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */
+#define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
+#define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
+#define DSI_TCCR5_BTA_TOCNT6_Msk (0x1U << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */
+#define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
+#define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
+#define DSI_TCCR5_BTA_TOCNT7_Msk (0x1U << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */
+#define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
+#define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
+#define DSI_TCCR5_BTA_TOCNT8_Msk (0x1U << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */
+#define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
+#define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
+#define DSI_TCCR5_BTA_TOCNT9_Msk (0x1U << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */
+#define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
+#define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
+#define DSI_TCCR5_BTA_TOCNT10_Msk (0x1U << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */
+#define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
+#define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
+#define DSI_TCCR5_BTA_TOCNT11_Msk (0x1U << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */
+#define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
+#define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
+#define DSI_TCCR5_BTA_TOCNT12_Msk (0x1U << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */
+#define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
+#define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
+#define DSI_TCCR5_BTA_TOCNT13_Msk (0x1U << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */
+#define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
+#define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
+#define DSI_TCCR5_BTA_TOCNT14_Msk (0x1U << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */
+#define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
+#define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
+#define DSI_TCCR5_BTA_TOCNT15_Msk (0x1U << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */
+#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
+
+/******************* Bit definition for DSI_TDCR register ***************/
+#define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
+#define DSI_TDCR_3DM0 0x00000001U
+#define DSI_TDCR_3DM1 0x00000002U
+
+#define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
+#define DSI_TDCR_3DF0 0x00000004U
+#define DSI_TDCR_3DF1 0x00000008U
+
+#define DSI_TDCR_SVS_Pos (4U)
+#define DSI_TDCR_SVS_Msk (0x1U << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
+#define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */
+#define DSI_TDCR_RF_Pos (5U)
+#define DSI_TDCR_RF_Msk (0x1U << DSI_TDCR_RF_Pos) /*!< 0x00000020 */
+#define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */
+#define DSI_TDCR_S3DC_Pos (16U)
+#define DSI_TDCR_S3DC_Msk (0x1U << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */
+#define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_CLCR register ***************/
+#define DSI_CLCR_DPCC_Pos (0U)
+#define DSI_CLCR_DPCC_Msk (0x1U << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */
+#define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR_Pos (1U)
+#define DSI_CLCR_ACR_Msk (0x1U << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */
+#define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */
+
+/******************* Bit definition for DSI_CLTCR register **************/
+#define DSI_CLTCR_LP2HS_TIME_Pos (0U)
+#define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFU << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */
+#define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
+#define DSI_CLTCR_LP2HS_TIME0_Msk (0x1U << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */
+#define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
+#define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
+#define DSI_CLTCR_LP2HS_TIME1_Msk (0x1U << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */
+#define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
+#define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
+#define DSI_CLTCR_LP2HS_TIME2_Msk (0x1U << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */
+#define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
+#define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
+#define DSI_CLTCR_LP2HS_TIME3_Msk (0x1U << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */
+#define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
+#define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
+#define DSI_CLTCR_LP2HS_TIME4_Msk (0x1U << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */
+#define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
+#define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
+#define DSI_CLTCR_LP2HS_TIME5_Msk (0x1U << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */
+#define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
+#define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
+#define DSI_CLTCR_LP2HS_TIME6_Msk (0x1U << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */
+#define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
+#define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
+#define DSI_CLTCR_LP2HS_TIME7_Msk (0x1U << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */
+#define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
+#define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
+#define DSI_CLTCR_LP2HS_TIME8_Msk (0x1U << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */
+#define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
+#define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
+#define DSI_CLTCR_LP2HS_TIME9_Msk (0x1U << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */
+#define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
+
+#define DSI_CLTCR_HS2LP_TIME_Pos (16U)
+#define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFU << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */
+#define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
+#define DSI_CLTCR_HS2LP_TIME0_Msk (0x1U << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */
+#define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
+#define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
+#define DSI_CLTCR_HS2LP_TIME1_Msk (0x1U << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */
+#define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
+#define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
+#define DSI_CLTCR_HS2LP_TIME2_Msk (0x1U << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */
+#define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
+#define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
+#define DSI_CLTCR_HS2LP_TIME3_Msk (0x1U << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */
+#define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
+#define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
+#define DSI_CLTCR_HS2LP_TIME4_Msk (0x1U << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */
+#define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
+#define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
+#define DSI_CLTCR_HS2LP_TIME5_Msk (0x1U << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */
+#define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
+#define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
+#define DSI_CLTCR_HS2LP_TIME6_Msk (0x1U << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */
+#define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
+#define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
+#define DSI_CLTCR_HS2LP_TIME7_Msk (0x1U << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */
+#define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
+#define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
+#define DSI_CLTCR_HS2LP_TIME8_Msk (0x1U << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */
+#define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
+#define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
+#define DSI_CLTCR_HS2LP_TIME9_Msk (0x1U << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */
+#define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
+
+/******************* Bit definition for DSI_DLTCR register **************/
+#define DSI_DLTCR_MRD_TIME_Pos (0U)
+#define DSI_DLTCR_MRD_TIME_Msk (0x7FFFU << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */
+#define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */
+#define DSI_DLTCR_MRD_TIME0_Pos (0U)
+#define DSI_DLTCR_MRD_TIME0_Msk (0x1U << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */
+#define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
+#define DSI_DLTCR_MRD_TIME1_Pos (1U)
+#define DSI_DLTCR_MRD_TIME1_Msk (0x1U << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */
+#define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
+#define DSI_DLTCR_MRD_TIME2_Pos (2U)
+#define DSI_DLTCR_MRD_TIME2_Msk (0x1U << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */
+#define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
+#define DSI_DLTCR_MRD_TIME3_Pos (3U)
+#define DSI_DLTCR_MRD_TIME3_Msk (0x1U << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */
+#define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
+#define DSI_DLTCR_MRD_TIME4_Pos (4U)
+#define DSI_DLTCR_MRD_TIME4_Msk (0x1U << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */
+#define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
+#define DSI_DLTCR_MRD_TIME5_Pos (5U)
+#define DSI_DLTCR_MRD_TIME5_Msk (0x1U << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */
+#define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
+#define DSI_DLTCR_MRD_TIME6_Pos (6U)
+#define DSI_DLTCR_MRD_TIME6_Msk (0x1U << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */
+#define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
+#define DSI_DLTCR_MRD_TIME7_Pos (7U)
+#define DSI_DLTCR_MRD_TIME7_Msk (0x1U << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */
+#define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
+#define DSI_DLTCR_MRD_TIME8_Pos (8U)
+#define DSI_DLTCR_MRD_TIME8_Msk (0x1U << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */
+#define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
+#define DSI_DLTCR_MRD_TIME9_Pos (9U)
+#define DSI_DLTCR_MRD_TIME9_Msk (0x1U << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */
+#define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
+#define DSI_DLTCR_MRD_TIME10_Pos (10U)
+#define DSI_DLTCR_MRD_TIME10_Msk (0x1U << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */
+#define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
+#define DSI_DLTCR_MRD_TIME11_Pos (11U)
+#define DSI_DLTCR_MRD_TIME11_Msk (0x1U << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */
+#define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
+#define DSI_DLTCR_MRD_TIME12_Pos (12U)
+#define DSI_DLTCR_MRD_TIME12_Msk (0x1U << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */
+#define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
+#define DSI_DLTCR_MRD_TIME13_Pos (13U)
+#define DSI_DLTCR_MRD_TIME13_Msk (0x1U << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */
+#define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
+#define DSI_DLTCR_MRD_TIME14_Pos (14U)
+#define DSI_DLTCR_MRD_TIME14_Msk (0x1U << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */
+#define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
+
+#define DSI_DLTCR_LP2HS_TIME_Pos (16U)
+#define DSI_DLTCR_LP2HS_TIME_Msk (0xFFU << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */
+#define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
+#define DSI_DLTCR_LP2HS_TIME0_Msk (0x1U << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */
+#define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
+#define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
+#define DSI_DLTCR_LP2HS_TIME1_Msk (0x1U << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */
+#define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
+#define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
+#define DSI_DLTCR_LP2HS_TIME2_Msk (0x1U << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */
+#define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
+#define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
+#define DSI_DLTCR_LP2HS_TIME3_Msk (0x1U << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */
+#define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
+#define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
+#define DSI_DLTCR_LP2HS_TIME4_Msk (0x1U << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */
+#define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
+#define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
+#define DSI_DLTCR_LP2HS_TIME5_Msk (0x1U << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */
+#define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
+#define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
+#define DSI_DLTCR_LP2HS_TIME6_Msk (0x1U << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */
+#define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
+#define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
+#define DSI_DLTCR_LP2HS_TIME7_Msk (0x1U << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */
+#define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
+
+#define DSI_DLTCR_HS2LP_TIME_Pos (24U)
+#define DSI_DLTCR_HS2LP_TIME_Msk (0xFFU << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */
+#define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
+#define DSI_DLTCR_HS2LP_TIME0_Msk (0x1U << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */
+#define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
+#define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
+#define DSI_DLTCR_HS2LP_TIME1_Msk (0x1U << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */
+#define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
+#define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
+#define DSI_DLTCR_HS2LP_TIME2_Msk (0x1U << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */
+#define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
+#define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
+#define DSI_DLTCR_HS2LP_TIME3_Msk (0x1U << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */
+#define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
+#define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
+#define DSI_DLTCR_HS2LP_TIME4_Msk (0x1U << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */
+#define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
+#define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
+#define DSI_DLTCR_HS2LP_TIME5_Msk (0x1U << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */
+#define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
+#define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
+#define DSI_DLTCR_HS2LP_TIME6_Msk (0x1U << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */
+#define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
+#define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
+#define DSI_DLTCR_HS2LP_TIME7_Msk (0x1U << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */
+#define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
+
+/******************* Bit definition for DSI_PCTLR register **************/
+#define DSI_PCTLR_DEN_Pos (1U)
+#define DSI_PCTLR_DEN_Msk (0x1U << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */
+#define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */
+#define DSI_PCTLR_CKE_Pos (2U)
+#define DSI_PCTLR_CKE_Msk (0x1U << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */
+#define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */
+
+/******************* Bit definition for DSI_PCONFR register *************/
+#define DSI_PCONFR_NL_Pos (0U)
+#define DSI_PCONFR_NL_Msk (0x3U << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */
+#define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */
+#define DSI_PCONFR_NL0_Pos (0U)
+#define DSI_PCONFR_NL0_Msk (0x1U << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */
+#define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
+#define DSI_PCONFR_NL1_Pos (1U)
+#define DSI_PCONFR_NL1_Msk (0x1U << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */
+#define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
+
+#define DSI_PCONFR_SW_TIME_Pos (8U)
+#define DSI_PCONFR_SW_TIME_Msk (0xFFU << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */
+#define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0_Pos (8U)
+#define DSI_PCONFR_SW_TIME0_Msk (0x1U << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */
+#define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
+#define DSI_PCONFR_SW_TIME1_Pos (9U)
+#define DSI_PCONFR_SW_TIME1_Msk (0x1U << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */
+#define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
+#define DSI_PCONFR_SW_TIME2_Pos (10U)
+#define DSI_PCONFR_SW_TIME2_Msk (0x1U << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */
+#define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
+#define DSI_PCONFR_SW_TIME3_Pos (11U)
+#define DSI_PCONFR_SW_TIME3_Msk (0x1U << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */
+#define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
+#define DSI_PCONFR_SW_TIME4_Pos (12U)
+#define DSI_PCONFR_SW_TIME4_Msk (0x1U << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */
+#define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
+#define DSI_PCONFR_SW_TIME5_Pos (13U)
+#define DSI_PCONFR_SW_TIME5_Msk (0x1U << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */
+#define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
+#define DSI_PCONFR_SW_TIME6_Pos (14U)
+#define DSI_PCONFR_SW_TIME6_Msk (0x1U << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */
+#define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
+#define DSI_PCONFR_SW_TIME7_Pos (15U)
+#define DSI_PCONFR_SW_TIME7_Msk (0x1U << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */
+#define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
+
+/******************* Bit definition for DSI_PUCR register ***************/
+#define DSI_PUCR_URCL_Pos (0U)
+#define DSI_PUCR_URCL_Msk (0x1U << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */
+#define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL_Pos (1U)
+#define DSI_PUCR_UECL_Msk (0x1U << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */
+#define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL_Pos (2U)
+#define DSI_PUCR_URDL_Msk (0x1U << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */
+#define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL_Pos (3U)
+#define DSI_PUCR_UEDL_Msk (0x1U << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */
+#define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */
+
+/******************* Bit definition for DSI_PTTCR register **************/
+#define DSI_PTTCR_TX_TRIG_Pos (0U)
+#define DSI_PTTCR_TX_TRIG_Msk (0xFU << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */
+#define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0_Pos (0U)
+#define DSI_PTTCR_TX_TRIG0_Msk (0x1U << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */
+#define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
+#define DSI_PTTCR_TX_TRIG1_Pos (1U)
+#define DSI_PTTCR_TX_TRIG1_Msk (0x1U << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */
+#define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
+#define DSI_PTTCR_TX_TRIG2_Pos (2U)
+#define DSI_PTTCR_TX_TRIG2_Msk (0x1U << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */
+#define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
+#define DSI_PTTCR_TX_TRIG3_Pos (3U)
+#define DSI_PTTCR_TX_TRIG3_Msk (0x1U << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */
+#define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
+
+/******************* Bit definition for DSI_PSR register ****************/
+#define DSI_PSR_PD_Pos (1U)
+#define DSI_PSR_PD_Msk (0x1U << DSI_PSR_PD_Pos) /*!< 0x00000002 */
+#define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */
+#define DSI_PSR_PSSC_Pos (2U)
+#define DSI_PSR_PSSC_Msk (0x1U << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */
+#define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC_Pos (3U)
+#define DSI_PSR_UANC_Msk (0x1U << DSI_PSR_UANC_Pos) /*!< 0x00000008 */
+#define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0_Pos (4U)
+#define DSI_PSR_PSS0_Msk (0x1U << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */
+#define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0_Pos (5U)
+#define DSI_PSR_UAN0_Msk (0x1U << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */
+#define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0_Pos (6U)
+#define DSI_PSR_RUE0_Msk (0x1U << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */
+#define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1_Pos (7U)
+#define DSI_PSR_PSS1_Msk (0x1U << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */
+#define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1_Pos (8U)
+#define DSI_PSR_UAN1_Msk (0x1U << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */
+#define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */
+
+/******************* Bit definition for DSI_ISR0 register ***************/
+#define DSI_ISR0_AE0_Pos (0U)
+#define DSI_ISR0_AE0_Msk (0x1U << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */
+#define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1_Pos (1U)
+#define DSI_ISR0_AE1_Msk (0x1U << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */
+#define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2_Pos (2U)
+#define DSI_ISR0_AE2_Msk (0x1U << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */
+#define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3_Pos (3U)
+#define DSI_ISR0_AE3_Msk (0x1U << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */
+#define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4_Pos (4U)
+#define DSI_ISR0_AE4_Msk (0x1U << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */
+#define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5_Pos (5U)
+#define DSI_ISR0_AE5_Msk (0x1U << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */
+#define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6_Pos (6U)
+#define DSI_ISR0_AE6_Msk (0x1U << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */
+#define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7_Pos (7U)
+#define DSI_ISR0_AE7_Msk (0x1U << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */
+#define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8_Pos (8U)
+#define DSI_ISR0_AE8_Msk (0x1U << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */
+#define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9_Pos (9U)
+#define DSI_ISR0_AE9_Msk (0x1U << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */
+#define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10_Pos (10U)
+#define DSI_ISR0_AE10_Msk (0x1U << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */
+#define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11_Pos (11U)
+#define DSI_ISR0_AE11_Msk (0x1U << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */
+#define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12_Pos (12U)
+#define DSI_ISR0_AE12_Msk (0x1U << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */
+#define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13_Pos (13U)
+#define DSI_ISR0_AE13_Msk (0x1U << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */
+#define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14_Pos (14U)
+#define DSI_ISR0_AE14_Msk (0x1U << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */
+#define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15_Pos (15U)
+#define DSI_ISR0_AE15_Msk (0x1U << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */
+#define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0_Pos (16U)
+#define DSI_ISR0_PE0_Msk (0x1U << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */
+#define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */
+#define DSI_ISR0_PE1_Pos (17U)
+#define DSI_ISR0_PE1_Msk (0x1U << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */
+#define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */
+#define DSI_ISR0_PE2_Pos (18U)
+#define DSI_ISR0_PE2_Msk (0x1U << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */
+#define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */
+#define DSI_ISR0_PE3_Pos (19U)
+#define DSI_ISR0_PE3_Msk (0x1U << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */
+#define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */
+#define DSI_ISR0_PE4_Pos (20U)
+#define DSI_ISR0_PE4_Msk (0x1U << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */
+#define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */
+
+/******************* Bit definition for DSI_ISR1 register ***************/
+#define DSI_ISR1_TOHSTX_Pos (0U)
+#define DSI_ISR1_TOHSTX_Msk (0x1U << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */
+#define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX_Pos (1U)
+#define DSI_ISR1_TOLPRX_Msk (0x1U << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */
+#define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE_Pos (2U)
+#define DSI_ISR1_ECCSE_Msk (0x1U << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */
+#define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME_Pos (3U)
+#define DSI_ISR1_ECCME_Msk (0x1U << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */
+#define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE_Pos (4U)
+#define DSI_ISR1_CRCE_Msk (0x1U << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */
+#define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */
+#define DSI_ISR1_PSE_Pos (5U)
+#define DSI_ISR1_PSE_Msk (0x1U << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */
+#define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE_Pos (6U)
+#define DSI_ISR1_EOTPE_Msk (0x1U << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */
+#define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */
+#define DSI_ISR1_LPWRE_Pos (7U)
+#define DSI_ISR1_LPWRE_Msk (0x1U << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */
+#define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE_Pos (8U)
+#define DSI_ISR1_GCWRE_Msk (0x1U << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */
+#define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE_Pos (9U)
+#define DSI_ISR1_GPWRE_Msk (0x1U << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */
+#define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE_Pos (10U)
+#define DSI_ISR1_GPTXE_Msk (0x1U << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */
+#define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE_Pos (11U)
+#define DSI_ISR1_GPRDE_Msk (0x1U << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */
+#define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE_Pos (12U)
+#define DSI_ISR1_GPRXE_Msk (0x1U << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */
+#define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_IER0 register ***************/
+#define DSI_IER0_AE0IE_Pos (0U)
+#define DSI_IER0_AE0IE_Msk (0x1U << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */
+#define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE_Pos (1U)
+#define DSI_IER0_AE1IE_Msk (0x1U << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */
+#define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE_Pos (2U)
+#define DSI_IER0_AE2IE_Msk (0x1U << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */
+#define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE_Pos (3U)
+#define DSI_IER0_AE3IE_Msk (0x1U << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */
+#define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE_Pos (4U)
+#define DSI_IER0_AE4IE_Msk (0x1U << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */
+#define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE_Pos (5U)
+#define DSI_IER0_AE5IE_Msk (0x1U << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */
+#define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE_Pos (6U)
+#define DSI_IER0_AE6IE_Msk (0x1U << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */
+#define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE_Pos (7U)
+#define DSI_IER0_AE7IE_Msk (0x1U << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */
+#define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE_Pos (8U)
+#define DSI_IER0_AE8IE_Msk (0x1U << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */
+#define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE_Pos (9U)
+#define DSI_IER0_AE9IE_Msk (0x1U << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */
+#define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE_Pos (10U)
+#define DSI_IER0_AE10IE_Msk (0x1U << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */
+#define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE_Pos (11U)
+#define DSI_IER0_AE11IE_Msk (0x1U << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */
+#define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE_Pos (12U)
+#define DSI_IER0_AE12IE_Msk (0x1U << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */
+#define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE_Pos (13U)
+#define DSI_IER0_AE13IE_Msk (0x1U << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */
+#define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE_Pos (14U)
+#define DSI_IER0_AE14IE_Msk (0x1U << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */
+#define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE_Pos (15U)
+#define DSI_IER0_AE15IE_Msk (0x1U << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */
+#define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE_Pos (16U)
+#define DSI_IER0_PE0IE_Msk (0x1U << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */
+#define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE_Pos (17U)
+#define DSI_IER0_PE1IE_Msk (0x1U << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */
+#define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE_Pos (18U)
+#define DSI_IER0_PE2IE_Msk (0x1U << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */
+#define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE_Pos (19U)
+#define DSI_IER0_PE3IE_Msk (0x1U << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */
+#define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE_Pos (20U)
+#define DSI_IER0_PE4IE_Msk (0x1U << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */
+#define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */
+
+/******************* Bit definition for DSI_IER1 register ***************/
+#define DSI_IER1_TOHSTXIE_Pos (0U)
+#define DSI_IER1_TOHSTXIE_Msk (0x1U << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */
+#define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE_Pos (1U)
+#define DSI_IER1_TOLPRXIE_Msk (0x1U << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */
+#define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE_Pos (2U)
+#define DSI_IER1_ECCSEIE_Msk (0x1U << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */
+#define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE_Pos (3U)
+#define DSI_IER1_ECCMEIE_Msk (0x1U << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */
+#define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE_Pos (4U)
+#define DSI_IER1_CRCEIE_Msk (0x1U << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */
+#define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE_Pos (5U)
+#define DSI_IER1_PSEIE_Msk (0x1U << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */
+#define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE_Pos (6U)
+#define DSI_IER1_EOTPEIE_Msk (0x1U << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */
+#define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE_Pos (7U)
+#define DSI_IER1_LPWREIE_Msk (0x1U << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */
+#define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE_Pos (8U)
+#define DSI_IER1_GCWREIE_Msk (0x1U << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */
+#define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE_Pos (9U)
+#define DSI_IER1_GPWREIE_Msk (0x1U << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */
+#define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE_Pos (10U)
+#define DSI_IER1_GPTXEIE_Msk (0x1U << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */
+#define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE_Pos (11U)
+#define DSI_IER1_GPRDEIE_Msk (0x1U << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */
+#define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE_Pos (12U)
+#define DSI_IER1_GPRXEIE_Msk (0x1U << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */
+#define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */
+
+/******************* Bit definition for DSI_FIR0 register ***************/
+#define DSI_FIR0_FAE0_Pos (0U)
+#define DSI_FIR0_FAE0_Msk (0x1U << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */
+#define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1_Pos (1U)
+#define DSI_FIR0_FAE1_Msk (0x1U << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */
+#define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2_Pos (2U)
+#define DSI_FIR0_FAE2_Msk (0x1U << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */
+#define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3_Pos (3U)
+#define DSI_FIR0_FAE3_Msk (0x1U << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */
+#define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4_Pos (4U)
+#define DSI_FIR0_FAE4_Msk (0x1U << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */
+#define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5_Pos (5U)
+#define DSI_FIR0_FAE5_Msk (0x1U << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */
+#define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6_Pos (6U)
+#define DSI_FIR0_FAE6_Msk (0x1U << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */
+#define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7_Pos (7U)
+#define DSI_FIR0_FAE7_Msk (0x1U << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */
+#define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8_Pos (8U)
+#define DSI_FIR0_FAE8_Msk (0x1U << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */
+#define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9_Pos (9U)
+#define DSI_FIR0_FAE9_Msk (0x1U << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */
+#define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10_Pos (10U)
+#define DSI_FIR0_FAE10_Msk (0x1U << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */
+#define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11_Pos (11U)
+#define DSI_FIR0_FAE11_Msk (0x1U << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */
+#define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12_Pos (12U)
+#define DSI_FIR0_FAE12_Msk (0x1U << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */
+#define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13_Pos (13U)
+#define DSI_FIR0_FAE13_Msk (0x1U << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */
+#define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14_Pos (14U)
+#define DSI_FIR0_FAE14_Msk (0x1U << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */
+#define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15_Pos (15U)
+#define DSI_FIR0_FAE15_Msk (0x1U << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */
+#define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0_Pos (16U)
+#define DSI_FIR0_FPE0_Msk (0x1U << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */
+#define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1_Pos (17U)
+#define DSI_FIR0_FPE1_Msk (0x1U << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */
+#define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2_Pos (18U)
+#define DSI_FIR0_FPE2_Msk (0x1U << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */
+#define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3_Pos (19U)
+#define DSI_FIR0_FPE3_Msk (0x1U << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */
+#define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4_Pos (20U)
+#define DSI_FIR0_FPE4_Msk (0x1U << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */
+#define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */
+
+/******************* Bit definition for DSI_FIR1 register ***************/
+#define DSI_FIR1_FTOHSTX_Pos (0U)
+#define DSI_FIR1_FTOHSTX_Msk (0x1U << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */
+#define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX_Pos (1U)
+#define DSI_FIR1_FTOLPRX_Msk (0x1U << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */
+#define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE_Pos (2U)
+#define DSI_FIR1_FECCSE_Msk (0x1U << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */
+#define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME_Pos (3U)
+#define DSI_FIR1_FECCME_Msk (0x1U << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */
+#define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE_Pos (4U)
+#define DSI_FIR1_FCRCE_Msk (0x1U << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */
+#define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */
+#define DSI_FIR1_FPSE_Pos (5U)
+#define DSI_FIR1_FPSE_Msk (0x1U << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */
+#define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE_Pos (6U)
+#define DSI_FIR1_FEOTPE_Msk (0x1U << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */
+#define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE_Pos (7U)
+#define DSI_FIR1_FLPWRE_Msk (0x1U << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */
+#define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE_Pos (8U)
+#define DSI_FIR1_FGCWRE_Msk (0x1U << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */
+#define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE_Pos (9U)
+#define DSI_FIR1_FGPWRE_Msk (0x1U << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */
+#define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE_Pos (10U)
+#define DSI_FIR1_FGPTXE_Msk (0x1U << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */
+#define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE_Pos (11U)
+#define DSI_FIR1_FGPRDE_Msk (0x1U << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */
+#define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE_Pos (12U)
+#define DSI_FIR1_FGPRXE_Msk (0x1U << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */
+#define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_VSCR register ***************/
+#define DSI_VSCR_EN_Pos (0U)
+#define DSI_VSCR_EN_Msk (0x1U << DSI_VSCR_EN_Pos) /*!< 0x00000001 */
+#define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */
+#define DSI_VSCR_UR_Pos (8U)
+#define DSI_VSCR_UR_Msk (0x1U << DSI_VSCR_UR_Pos) /*!< 0x00000100 */
+#define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */
+
+/******************* Bit definition for DSI_LCVCIDR register ************/
+#define DSI_LCVCIDR_VCID_Pos (0U)
+#define DSI_LCVCIDR_VCID_Msk (0x3U << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */
+#define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0_Pos (0U)
+#define DSI_LCVCIDR_VCID0_Msk (0x1U << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */
+#define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
+#define DSI_LCVCIDR_VCID1_Pos (1U)
+#define DSI_LCVCIDR_VCID1_Msk (0x1U << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */
+#define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
+
+/******************* Bit definition for DSI_LCCCR register **************/
+#define DSI_LCCCR_COLC_Pos (0U)
+#define DSI_LCCCR_COLC_Msk (0xFU << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */
+#define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */
+#define DSI_LCCCR_COLC0_Pos (0U)
+#define DSI_LCCCR_COLC0_Msk (0x1U << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */
+#define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
+#define DSI_LCCCR_COLC1_Pos (1U)
+#define DSI_LCCCR_COLC1_Msk (0x1U << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */
+#define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
+#define DSI_LCCCR_COLC2_Pos (2U)
+#define DSI_LCCCR_COLC2_Msk (0x1U << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */
+#define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
+#define DSI_LCCCR_COLC3_Pos (3U)
+#define DSI_LCCCR_COLC3_Msk (0x1U << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */
+#define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
+
+#define DSI_LCCCR_LPE_Pos (8U)
+#define DSI_LCCCR_LPE_Msk (0x1U << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */
+#define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */
+
+/******************* Bit definition for DSI_LPMCCR register *************/
+#define DSI_LPMCCR_VLPSIZE_Pos (0U)
+#define DSI_LPMCCR_VLPSIZE_Msk (0xFFU << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */
+#define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0_Pos (0U)
+#define DSI_LPMCCR_VLPSIZE0_Msk (0x1U << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */
+#define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
+#define DSI_LPMCCR_VLPSIZE1_Pos (1U)
+#define DSI_LPMCCR_VLPSIZE1_Msk (0x1U << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */
+#define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
+#define DSI_LPMCCR_VLPSIZE2_Pos (2U)
+#define DSI_LPMCCR_VLPSIZE2_Msk (0x1U << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */
+#define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
+#define DSI_LPMCCR_VLPSIZE3_Pos (3U)
+#define DSI_LPMCCR_VLPSIZE3_Msk (0x1U << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */
+#define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
+#define DSI_LPMCCR_VLPSIZE4_Pos (4U)
+#define DSI_LPMCCR_VLPSIZE4_Msk (0x1U << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */
+#define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
+#define DSI_LPMCCR_VLPSIZE5_Pos (5U)
+#define DSI_LPMCCR_VLPSIZE5_Msk (0x1U << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */
+#define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
+#define DSI_LPMCCR_VLPSIZE6_Pos (6U)
+#define DSI_LPMCCR_VLPSIZE6_Msk (0x1U << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */
+#define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
+#define DSI_LPMCCR_VLPSIZE7_Pos (7U)
+#define DSI_LPMCCR_VLPSIZE7_Msk (0x1U << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */
+#define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
+
+#define DSI_LPMCCR_LPSIZE_Pos (16U)
+#define DSI_LPMCCR_LPSIZE_Msk (0xFFU << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */
+#define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0_Pos (16U)
+#define DSI_LPMCCR_LPSIZE0_Msk (0x1U << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */
+#define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
+#define DSI_LPMCCR_LPSIZE1_Pos (17U)
+#define DSI_LPMCCR_LPSIZE1_Msk (0x1U << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */
+#define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
+#define DSI_LPMCCR_LPSIZE2_Pos (18U)
+#define DSI_LPMCCR_LPSIZE2_Msk (0x1U << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */
+#define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
+#define DSI_LPMCCR_LPSIZE3_Pos (19U)
+#define DSI_LPMCCR_LPSIZE3_Msk (0x1U << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */
+#define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
+#define DSI_LPMCCR_LPSIZE4_Pos (20U)
+#define DSI_LPMCCR_LPSIZE4_Msk (0x1U << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */
+#define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
+#define DSI_LPMCCR_LPSIZE5_Pos (21U)
+#define DSI_LPMCCR_LPSIZE5_Msk (0x1U << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */
+#define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
+#define DSI_LPMCCR_LPSIZE6_Pos (22U)
+#define DSI_LPMCCR_LPSIZE6_Msk (0x1U << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */
+#define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
+#define DSI_LPMCCR_LPSIZE7_Pos (23U)
+#define DSI_LPMCCR_LPSIZE7_Msk (0x1U << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */
+#define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
+
+/******************* Bit definition for DSI_VMCCR register **************/
+#define DSI_VMCCR_VMT_Pos (0U)
+#define DSI_VMCCR_VMT_Msk (0x3U << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */
+#define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0_Pos (0U)
+#define DSI_VMCCR_VMT0_Msk (0x1U << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */
+#define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
+#define DSI_VMCCR_VMT1_Pos (1U)
+#define DSI_VMCCR_VMT1_Msk (0x1U << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */
+#define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
+
+#define DSI_VMCCR_LPVSAE_Pos (8U)
+#define DSI_VMCCR_LPVSAE_Msk (0x1U << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */
+#define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE_Pos (9U)
+#define DSI_VMCCR_LPVBPE_Msk (0x1U << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */
+#define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE_Pos (10U)
+#define DSI_VMCCR_LPVFPE_Msk (0x1U << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */
+#define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE_Pos (11U)
+#define DSI_VMCCR_LPVAE_Msk (0x1U << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */
+#define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE_Pos (12U)
+#define DSI_VMCCR_LPHBPE_Msk (0x1U << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */
+#define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE_Pos (13U)
+#define DSI_VMCCR_LPHFE_Msk (0x1U << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */
+#define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE_Pos (14U)
+#define DSI_VMCCR_FBTAAE_Msk (0x1U << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */
+#define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE_Pos (15U)
+#define DSI_VMCCR_LPCE_Msk (0x1U << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */
+#define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */
+
+/******************* Bit definition for DSI_VPCCR register **************/
+#define DSI_VPCCR_VPSIZE_Pos (0U)
+#define DSI_VPCCR_VPSIZE_Msk (0x3FFFU << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */
+#define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0_Pos (0U)
+#define DSI_VPCCR_VPSIZE0_Msk (0x1U << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */
+#define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
+#define DSI_VPCCR_VPSIZE1_Pos (1U)
+#define DSI_VPCCR_VPSIZE1_Msk (0x1U << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */
+#define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
+#define DSI_VPCCR_VPSIZE2_Pos (2U)
+#define DSI_VPCCR_VPSIZE2_Msk (0x1U << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */
+#define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
+#define DSI_VPCCR_VPSIZE3_Pos (3U)
+#define DSI_VPCCR_VPSIZE3_Msk (0x1U << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */
+#define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
+#define DSI_VPCCR_VPSIZE4_Pos (4U)
+#define DSI_VPCCR_VPSIZE4_Msk (0x1U << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */
+#define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
+#define DSI_VPCCR_VPSIZE5_Pos (5U)
+#define DSI_VPCCR_VPSIZE5_Msk (0x1U << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */
+#define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
+#define DSI_VPCCR_VPSIZE6_Pos (6U)
+#define DSI_VPCCR_VPSIZE6_Msk (0x1U << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */
+#define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
+#define DSI_VPCCR_VPSIZE7_Pos (7U)
+#define DSI_VPCCR_VPSIZE7_Msk (0x1U << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */
+#define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
+#define DSI_VPCCR_VPSIZE8_Pos (8U)
+#define DSI_VPCCR_VPSIZE8_Msk (0x1U << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */
+#define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
+#define DSI_VPCCR_VPSIZE9_Pos (9U)
+#define DSI_VPCCR_VPSIZE9_Msk (0x1U << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */
+#define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
+#define DSI_VPCCR_VPSIZE10_Pos (10U)
+#define DSI_VPCCR_VPSIZE10_Msk (0x1U << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */
+#define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
+#define DSI_VPCCR_VPSIZE11_Pos (11U)
+#define DSI_VPCCR_VPSIZE11_Msk (0x1U << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */
+#define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
+#define DSI_VPCCR_VPSIZE12_Pos (12U)
+#define DSI_VPCCR_VPSIZE12_Msk (0x1U << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */
+#define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
+#define DSI_VPCCR_VPSIZE13_Pos (13U)
+#define DSI_VPCCR_VPSIZE13_Msk (0x1U << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */
+#define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
+
+/******************* Bit definition for DSI_VCCCR register **************/
+#define DSI_VCCCR_NUMC_Pos (0U)
+#define DSI_VCCCR_NUMC_Msk (0x1FFFU << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */
+#define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0_Pos (0U)
+#define DSI_VCCCR_NUMC0_Msk (0x1U << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */
+#define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
+#define DSI_VCCCR_NUMC1_Pos (1U)
+#define DSI_VCCCR_NUMC1_Msk (0x1U << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */
+#define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
+#define DSI_VCCCR_NUMC2_Pos (2U)
+#define DSI_VCCCR_NUMC2_Msk (0x1U << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */
+#define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
+#define DSI_VCCCR_NUMC3_Pos (3U)
+#define DSI_VCCCR_NUMC3_Msk (0x1U << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */
+#define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
+#define DSI_VCCCR_NUMC4_Pos (4U)
+#define DSI_VCCCR_NUMC4_Msk (0x1U << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */
+#define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
+#define DSI_VCCCR_NUMC5_Pos (5U)
+#define DSI_VCCCR_NUMC5_Msk (0x1U << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */
+#define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
+#define DSI_VCCCR_NUMC6_Pos (6U)
+#define DSI_VCCCR_NUMC6_Msk (0x1U << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */
+#define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
+#define DSI_VCCCR_NUMC7_Pos (7U)
+#define DSI_VCCCR_NUMC7_Msk (0x1U << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */
+#define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
+#define DSI_VCCCR_NUMC8_Pos (8U)
+#define DSI_VCCCR_NUMC8_Msk (0x1U << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */
+#define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
+#define DSI_VCCCR_NUMC9_Pos (9U)
+#define DSI_VCCCR_NUMC9_Msk (0x1U << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */
+#define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
+#define DSI_VCCCR_NUMC10_Pos (10U)
+#define DSI_VCCCR_NUMC10_Msk (0x1U << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */
+#define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
+#define DSI_VCCCR_NUMC11_Pos (11U)
+#define DSI_VCCCR_NUMC11_Msk (0x1U << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */
+#define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
+#define DSI_VCCCR_NUMC12_Pos (12U)
+#define DSI_VCCCR_NUMC12_Msk (0x1U << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */
+#define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
+
+/******************* Bit definition for DSI_VNPCCR register *************/
+#define DSI_VNPCCR_NPSIZE_Pos (0U)
+#define DSI_VNPCCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */
+#define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0_Pos (0U)
+#define DSI_VNPCCR_NPSIZE0_Msk (0x1U << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */
+#define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
+#define DSI_VNPCCR_NPSIZE1_Pos (1U)
+#define DSI_VNPCCR_NPSIZE1_Msk (0x1U << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */
+#define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
+#define DSI_VNPCCR_NPSIZE2_Pos (2U)
+#define DSI_VNPCCR_NPSIZE2_Msk (0x1U << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */
+#define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
+#define DSI_VNPCCR_NPSIZE3_Pos (3U)
+#define DSI_VNPCCR_NPSIZE3_Msk (0x1U << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */
+#define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
+#define DSI_VNPCCR_NPSIZE4_Pos (4U)
+#define DSI_VNPCCR_NPSIZE4_Msk (0x1U << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */
+#define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
+#define DSI_VNPCCR_NPSIZE5_Pos (5U)
+#define DSI_VNPCCR_NPSIZE5_Msk (0x1U << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */
+#define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
+#define DSI_VNPCCR_NPSIZE6_Pos (6U)
+#define DSI_VNPCCR_NPSIZE6_Msk (0x1U << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */
+#define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
+#define DSI_VNPCCR_NPSIZE7_Pos (7U)
+#define DSI_VNPCCR_NPSIZE7_Msk (0x1U << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */
+#define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
+#define DSI_VNPCCR_NPSIZE8_Pos (8U)
+#define DSI_VNPCCR_NPSIZE8_Msk (0x1U << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */
+#define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
+#define DSI_VNPCCR_NPSIZE9_Pos (9U)
+#define DSI_VNPCCR_NPSIZE9_Msk (0x1U << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */
+#define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
+#define DSI_VNPCCR_NPSIZE10_Pos (10U)
+#define DSI_VNPCCR_NPSIZE10_Msk (0x1U << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */
+#define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
+#define DSI_VNPCCR_NPSIZE11_Pos (11U)
+#define DSI_VNPCCR_NPSIZE11_Msk (0x1U << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */
+#define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
+#define DSI_VNPCCR_NPSIZE12_Pos (12U)
+#define DSI_VNPCCR_NPSIZE12_Msk (0x1U << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */
+#define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
+
+/******************* Bit definition for DSI_VHSACCR register ************/
+#define DSI_VHSACCR_HSA_Pos (0U)
+#define DSI_VHSACCR_HSA_Msk (0xFFFU << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */
+#define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0_Pos (0U)
+#define DSI_VHSACCR_HSA0_Msk (0x1U << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */
+#define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
+#define DSI_VHSACCR_HSA1_Pos (1U)
+#define DSI_VHSACCR_HSA1_Msk (0x1U << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */
+#define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
+#define DSI_VHSACCR_HSA2_Pos (2U)
+#define DSI_VHSACCR_HSA2_Msk (0x1U << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */
+#define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
+#define DSI_VHSACCR_HSA3_Pos (3U)
+#define DSI_VHSACCR_HSA3_Msk (0x1U << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */
+#define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
+#define DSI_VHSACCR_HSA4_Pos (4U)
+#define DSI_VHSACCR_HSA4_Msk (0x1U << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */
+#define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
+#define DSI_VHSACCR_HSA5_Pos (5U)
+#define DSI_VHSACCR_HSA5_Msk (0x1U << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */
+#define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
+#define DSI_VHSACCR_HSA6_Pos (6U)
+#define DSI_VHSACCR_HSA6_Msk (0x1U << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */
+#define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
+#define DSI_VHSACCR_HSA7_Pos (7U)
+#define DSI_VHSACCR_HSA7_Msk (0x1U << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */
+#define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
+#define DSI_VHSACCR_HSA8_Pos (8U)
+#define DSI_VHSACCR_HSA8_Msk (0x1U << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */
+#define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
+#define DSI_VHSACCR_HSA9_Pos (9U)
+#define DSI_VHSACCR_HSA9_Msk (0x1U << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */
+#define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
+#define DSI_VHSACCR_HSA10_Pos (10U)
+#define DSI_VHSACCR_HSA10_Msk (0x1U << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */
+#define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
+#define DSI_VHSACCR_HSA11_Pos (11U)
+#define DSI_VHSACCR_HSA11_Msk (0x1U << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */
+#define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
+
+/******************* Bit definition for DSI_VHBPCCR register ************/
+#define DSI_VHBPCCR_HBP_Pos (0U)
+#define DSI_VHBPCCR_HBP_Msk (0xFFFU << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */
+#define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0_Pos (0U)
+#define DSI_VHBPCCR_HBP0_Msk (0x1U << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */
+#define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
+#define DSI_VHBPCCR_HBP1_Pos (1U)
+#define DSI_VHBPCCR_HBP1_Msk (0x1U << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */
+#define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
+#define DSI_VHBPCCR_HBP2_Pos (2U)
+#define DSI_VHBPCCR_HBP2_Msk (0x1U << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */
+#define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
+#define DSI_VHBPCCR_HBP3_Pos (3U)
+#define DSI_VHBPCCR_HBP3_Msk (0x1U << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */
+#define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
+#define DSI_VHBPCCR_HBP4_Pos (4U)
+#define DSI_VHBPCCR_HBP4_Msk (0x1U << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */
+#define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
+#define DSI_VHBPCCR_HBP5_Pos (5U)
+#define DSI_VHBPCCR_HBP5_Msk (0x1U << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */
+#define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
+#define DSI_VHBPCCR_HBP6_Pos (6U)
+#define DSI_VHBPCCR_HBP6_Msk (0x1U << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */
+#define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
+#define DSI_VHBPCCR_HBP7_Pos (7U)
+#define DSI_VHBPCCR_HBP7_Msk (0x1U << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */
+#define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
+#define DSI_VHBPCCR_HBP8_Pos (8U)
+#define DSI_VHBPCCR_HBP8_Msk (0x1U << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */
+#define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
+#define DSI_VHBPCCR_HBP9_Pos (9U)
+#define DSI_VHBPCCR_HBP9_Msk (0x1U << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */
+#define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
+#define DSI_VHBPCCR_HBP10_Pos (10U)
+#define DSI_VHBPCCR_HBP10_Msk (0x1U << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */
+#define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
+#define DSI_VHBPCCR_HBP11_Pos (11U)
+#define DSI_VHBPCCR_HBP11_Msk (0x1U << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */
+#define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
+
+/******************* Bit definition for DSI_VLCCR register **************/
+#define DSI_VLCCR_HLINE_Pos (0U)
+#define DSI_VLCCR_HLINE_Msk (0x7FFFU << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */
+#define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0_Pos (0U)
+#define DSI_VLCCR_HLINE0_Msk (0x1U << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */
+#define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
+#define DSI_VLCCR_HLINE1_Pos (1U)
+#define DSI_VLCCR_HLINE1_Msk (0x1U << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */
+#define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
+#define DSI_VLCCR_HLINE2_Pos (2U)
+#define DSI_VLCCR_HLINE2_Msk (0x1U << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */
+#define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
+#define DSI_VLCCR_HLINE3_Pos (3U)
+#define DSI_VLCCR_HLINE3_Msk (0x1U << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */
+#define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
+#define DSI_VLCCR_HLINE4_Pos (4U)
+#define DSI_VLCCR_HLINE4_Msk (0x1U << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */
+#define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
+#define DSI_VLCCR_HLINE5_Pos (5U)
+#define DSI_VLCCR_HLINE5_Msk (0x1U << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */
+#define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
+#define DSI_VLCCR_HLINE6_Pos (6U)
+#define DSI_VLCCR_HLINE6_Msk (0x1U << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */
+#define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
+#define DSI_VLCCR_HLINE7_Pos (7U)
+#define DSI_VLCCR_HLINE7_Msk (0x1U << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */
+#define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
+#define DSI_VLCCR_HLINE8_Pos (8U)
+#define DSI_VLCCR_HLINE8_Msk (0x1U << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */
+#define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
+#define DSI_VLCCR_HLINE9_Pos (9U)
+#define DSI_VLCCR_HLINE9_Msk (0x1U << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */
+#define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
+#define DSI_VLCCR_HLINE10_Pos (10U)
+#define DSI_VLCCR_HLINE10_Msk (0x1U << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */
+#define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
+#define DSI_VLCCR_HLINE11_Pos (11U)
+#define DSI_VLCCR_HLINE11_Msk (0x1U << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */
+#define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
+#define DSI_VLCCR_HLINE12_Pos (12U)
+#define DSI_VLCCR_HLINE12_Msk (0x1U << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */
+#define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
+#define DSI_VLCCR_HLINE13_Pos (13U)
+#define DSI_VLCCR_HLINE13_Msk (0x1U << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */
+#define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
+#define DSI_VLCCR_HLINE14_Pos (14U)
+#define DSI_VLCCR_HLINE14_Msk (0x1U << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */
+#define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
+
+/******************* Bit definition for DSI_VVSACCR register ***************/
+#define DSI_VVSACCR_VSA_Pos (0U)
+#define DSI_VVSACCR_VSA_Msk (0x3FFU << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */
+#define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0_Pos (0U)
+#define DSI_VVSACCR_VSA0_Msk (0x1U << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */
+#define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
+#define DSI_VVSACCR_VSA1_Pos (1U)
+#define DSI_VVSACCR_VSA1_Msk (0x1U << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */
+#define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
+#define DSI_VVSACCR_VSA2_Pos (2U)
+#define DSI_VVSACCR_VSA2_Msk (0x1U << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */
+#define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
+#define DSI_VVSACCR_VSA3_Pos (3U)
+#define DSI_VVSACCR_VSA3_Msk (0x1U << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */
+#define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
+#define DSI_VVSACCR_VSA4_Pos (4U)
+#define DSI_VVSACCR_VSA4_Msk (0x1U << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */
+#define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
+#define DSI_VVSACCR_VSA5_Pos (5U)
+#define DSI_VVSACCR_VSA5_Msk (0x1U << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */
+#define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
+#define DSI_VVSACCR_VSA6_Pos (6U)
+#define DSI_VVSACCR_VSA6_Msk (0x1U << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */
+#define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
+#define DSI_VVSACCR_VSA7_Pos (7U)
+#define DSI_VVSACCR_VSA7_Msk (0x1U << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */
+#define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
+#define DSI_VVSACCR_VSA8_Pos (8U)
+#define DSI_VVSACCR_VSA8_Msk (0x1U << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */
+#define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
+#define DSI_VVSACCR_VSA9_Pos (9U)
+#define DSI_VVSACCR_VSA9_Msk (0x1U << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */
+#define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
+
+/******************* Bit definition for DSI_VVBPCCR register ************/
+#define DSI_VVBPCCR_VBP_Pos (0U)
+#define DSI_VVBPCCR_VBP_Msk (0x3FFU << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */
+#define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0_Pos (0U)
+#define DSI_VVBPCCR_VBP0_Msk (0x1U << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */
+#define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
+#define DSI_VVBPCCR_VBP1_Pos (1U)
+#define DSI_VVBPCCR_VBP1_Msk (0x1U << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */
+#define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
+#define DSI_VVBPCCR_VBP2_Pos (2U)
+#define DSI_VVBPCCR_VBP2_Msk (0x1U << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */
+#define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
+#define DSI_VVBPCCR_VBP3_Pos (3U)
+#define DSI_VVBPCCR_VBP3_Msk (0x1U << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */
+#define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
+#define DSI_VVBPCCR_VBP4_Pos (4U)
+#define DSI_VVBPCCR_VBP4_Msk (0x1U << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */
+#define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
+#define DSI_VVBPCCR_VBP5_Pos (5U)
+#define DSI_VVBPCCR_VBP5_Msk (0x1U << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */
+#define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
+#define DSI_VVBPCCR_VBP6_Pos (6U)
+#define DSI_VVBPCCR_VBP6_Msk (0x1U << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */
+#define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
+#define DSI_VVBPCCR_VBP7_Pos (7U)
+#define DSI_VVBPCCR_VBP7_Msk (0x1U << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */
+#define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
+#define DSI_VVBPCCR_VBP8_Pos (8U)
+#define DSI_VVBPCCR_VBP8_Msk (0x1U << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */
+#define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
+#define DSI_VVBPCCR_VBP9_Pos (9U)
+#define DSI_VVBPCCR_VBP9_Msk (0x1U << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */
+#define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
+
+/******************* Bit definition for DSI_VVFPCCR register ************/
+#define DSI_VVFPCCR_VFP_Pos (0U)
+#define DSI_VVFPCCR_VFP_Msk (0x3FFU << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */
+#define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0_Pos (0U)
+#define DSI_VVFPCCR_VFP0_Msk (0x1U << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */
+#define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
+#define DSI_VVFPCCR_VFP1_Pos (1U)
+#define DSI_VVFPCCR_VFP1_Msk (0x1U << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */
+#define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
+#define DSI_VVFPCCR_VFP2_Pos (2U)
+#define DSI_VVFPCCR_VFP2_Msk (0x1U << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */
+#define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
+#define DSI_VVFPCCR_VFP3_Pos (3U)
+#define DSI_VVFPCCR_VFP3_Msk (0x1U << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */
+#define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
+#define DSI_VVFPCCR_VFP4_Pos (4U)
+#define DSI_VVFPCCR_VFP4_Msk (0x1U << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */
+#define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
+#define DSI_VVFPCCR_VFP5_Pos (5U)
+#define DSI_VVFPCCR_VFP5_Msk (0x1U << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */
+#define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
+#define DSI_VVFPCCR_VFP6_Pos (6U)
+#define DSI_VVFPCCR_VFP6_Msk (0x1U << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */
+#define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
+#define DSI_VVFPCCR_VFP7_Pos (7U)
+#define DSI_VVFPCCR_VFP7_Msk (0x1U << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */
+#define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
+#define DSI_VVFPCCR_VFP8_Pos (8U)
+#define DSI_VVFPCCR_VFP8_Msk (0x1U << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */
+#define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
+#define DSI_VVFPCCR_VFP9_Pos (9U)
+#define DSI_VVFPCCR_VFP9_Msk (0x1U << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */
+#define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
+
+/******************* Bit definition for DSI_VVACCR register *************/
+#define DSI_VVACCR_VA_Pos (0U)
+#define DSI_VVACCR_VA_Msk (0x3FFFU << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */
+#define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0_Pos (0U)
+#define DSI_VVACCR_VA0_Msk (0x1U << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */
+#define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
+#define DSI_VVACCR_VA1_Pos (1U)
+#define DSI_VVACCR_VA1_Msk (0x1U << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */
+#define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
+#define DSI_VVACCR_VA2_Pos (2U)
+#define DSI_VVACCR_VA2_Msk (0x1U << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */
+#define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
+#define DSI_VVACCR_VA3_Pos (3U)
+#define DSI_VVACCR_VA3_Msk (0x1U << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */
+#define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
+#define DSI_VVACCR_VA4_Pos (4U)
+#define DSI_VVACCR_VA4_Msk (0x1U << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */
+#define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
+#define DSI_VVACCR_VA5_Pos (5U)
+#define DSI_VVACCR_VA5_Msk (0x1U << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */
+#define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
+#define DSI_VVACCR_VA6_Pos (6U)
+#define DSI_VVACCR_VA6_Msk (0x1U << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */
+#define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
+#define DSI_VVACCR_VA7_Pos (7U)
+#define DSI_VVACCR_VA7_Msk (0x1U << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */
+#define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
+#define DSI_VVACCR_VA8_Pos (8U)
+#define DSI_VVACCR_VA8_Msk (0x1U << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */
+#define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
+#define DSI_VVACCR_VA9_Pos (9U)
+#define DSI_VVACCR_VA9_Msk (0x1U << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */
+#define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
+#define DSI_VVACCR_VA10_Pos (10U)
+#define DSI_VVACCR_VA10_Msk (0x1U << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */
+#define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
+#define DSI_VVACCR_VA11_Pos (11U)
+#define DSI_VVACCR_VA11_Msk (0x1U << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */
+#define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
+#define DSI_VVACCR_VA12_Pos (12U)
+#define DSI_VVACCR_VA12_Msk (0x1U << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */
+#define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
+#define DSI_VVACCR_VA13_Pos (13U)
+#define DSI_VVACCR_VA13_Msk (0x1U << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */
+#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
+
+/******************* Bit definition for DSI_TDCCR register **************/
+#define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
+#define DSI_TDCCR_3DM0 0x00000001U
+#define DSI_TDCCR_3DM1 0x00000002U
+
+#define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
+#define DSI_TDCCR_3DF0 0x00000004U
+#define DSI_TDCCR_3DF1 0x00000008U
+
+#define DSI_TDCCR_SVS_Pos (4U)
+#define DSI_TDCCR_SVS_Msk (0x1U << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
+#define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */
+#define DSI_TDCCR_RF_Pos (5U)
+#define DSI_TDCCR_RF_Msk (0x1U << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */
+#define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */
+#define DSI_TDCCR_S3DC_Pos (16U)
+#define DSI_TDCCR_S3DC_Msk (0x1U << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */
+#define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_WCFGR register ***************/
+#define DSI_WCFGR_DSIM_Pos (0U)
+#define DSI_WCFGR_DSIM_Msk (0x1U << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */
+#define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */
+#define DSI_WCFGR_COLMUX_Pos (1U)
+#define DSI_WCFGR_COLMUX_Msk (0x7U << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */
+#define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0_Pos (1U)
+#define DSI_WCFGR_COLMUX0_Msk (0x1U << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */
+#define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
+#define DSI_WCFGR_COLMUX1_Pos (2U)
+#define DSI_WCFGR_COLMUX1_Msk (0x1U << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */
+#define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
+#define DSI_WCFGR_COLMUX2_Pos (3U)
+#define DSI_WCFGR_COLMUX2_Msk (0x1U << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */
+#define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
+
+#define DSI_WCFGR_TESRC_Pos (4U)
+#define DSI_WCFGR_TESRC_Msk (0x1U << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */
+#define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL_Pos (5U)
+#define DSI_WCFGR_TEPOL_Msk (0x1U << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */
+#define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR_Pos (6U)
+#define DSI_WCFGR_AR_Msk (0x1U << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */
+#define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL_Pos (7U)
+#define DSI_WCFGR_VSPOL_Msk (0x1U << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */
+#define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */
+
+/******************* Bit definition for DSI_WCR register *****************/
+#define DSI_WCR_COLM_Pos (0U)
+#define DSI_WCR_COLM_Msk (0x1U << DSI_WCR_COLM_Pos) /*!< 0x00000001 */
+#define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */
+#define DSI_WCR_SHTDN_Pos (1U)
+#define DSI_WCR_SHTDN_Msk (0x1U << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */
+#define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */
+#define DSI_WCR_LTDCEN_Pos (2U)
+#define DSI_WCR_LTDCEN_Msk (0x1U << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */
+#define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */
+#define DSI_WCR_DSIEN_Pos (3U)
+#define DSI_WCR_DSIEN_Msk (0x1U << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */
+#define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */
+
+/******************* Bit definition for DSI_WIER register ****************/
+#define DSI_WIER_TEIE_Pos (0U)
+#define DSI_WIER_TEIE_Msk (0x1U << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */
+#define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE_Pos (1U)
+#define DSI_WIER_ERIE_Msk (0x1U << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */
+#define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE_Pos (9U)
+#define DSI_WIER_PLLLIE_Msk (0x1U << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */
+#define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE_Pos (10U)
+#define DSI_WIER_PLLUIE_Msk (0x1U << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */
+#define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE_Pos (13U)
+#define DSI_WIER_RRIE_Msk (0x1U << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */
+#define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */
+
+/******************* Bit definition for DSI_WISR register ****************/
+#define DSI_WISR_TEIF_Pos (0U)
+#define DSI_WISR_TEIF_Msk (0x1U << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */
+#define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF_Pos (1U)
+#define DSI_WISR_ERIF_Msk (0x1U << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */
+#define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY_Pos (2U)
+#define DSI_WISR_BUSY_Msk (0x1U << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */
+#define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */
+#define DSI_WISR_PLLLS_Pos (8U)
+#define DSI_WISR_PLLLS_Msk (0x1U << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */
+#define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF_Pos (9U)
+#define DSI_WISR_PLLLIF_Msk (0x1U << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */
+#define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF_Pos (10U)
+#define DSI_WISR_PLLUIF_Msk (0x1U << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */
+#define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS_Pos (12U)
+#define DSI_WISR_RRS_Msk (0x1U << DSI_WISR_RRS_Pos) /*!< 0x00001000 */
+#define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF_Pos (13U)
+#define DSI_WISR_RRIF_Msk (0x1U << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */
+#define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WIFCR register ***************/
+#define DSI_WIFCR_CTEIF_Pos (0U)
+#define DSI_WIFCR_CTEIF_Msk (0x1U << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */
+#define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF_Pos (1U)
+#define DSI_WIFCR_CERIF_Msk (0x1U << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */
+#define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF_Pos (9U)
+#define DSI_WIFCR_CPLLLIF_Msk (0x1U << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */
+#define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF_Pos (10U)
+#define DSI_WIFCR_CPLLUIF_Msk (0x1U << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */
+#define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF_Pos (13U)
+#define DSI_WIFCR_CRRIF_Msk (0x1U << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */
+#define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WPCR0 register ***************/
+#define DSI_WPCR0_UIX4_Pos (0U)
+#define DSI_WPCR0_UIX4_Msk (0x3FU << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */
+#define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0 (0x01U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */
+#define DSI_WPCR0_UIX4_1 (0x02U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */
+#define DSI_WPCR0_UIX4_2 (0x04U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */
+#define DSI_WPCR0_UIX4_3 (0x08U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */
+#define DSI_WPCR0_UIX4_4 (0x10U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */
+#define DSI_WPCR0_UIX4_5 (0x20U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */
+
+#define DSI_WPCR0_SWCL_Pos (6U)
+#define DSI_WPCR0_SWCL_Msk (0x1U << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */
+#define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0_Pos (7U)
+#define DSI_WPCR0_SWDL0_Msk (0x1U << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */
+#define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1_Pos (8U)
+#define DSI_WPCR0_SWDL1_Msk (0x1U << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */
+#define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL_Pos (9U)
+#define DSI_WPCR0_HSICL_Msk (0x1U << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */
+#define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0_Pos (10U)
+#define DSI_WPCR0_HSIDL0_Msk (0x1U << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */
+#define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1_Pos (11U)
+#define DSI_WPCR0_HSIDL1_Msk (0x1U << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */
+#define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL_Pos (12U)
+#define DSI_WPCR0_FTXSMCL_Msk (0x1U << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */
+#define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL_Pos (13U)
+#define DSI_WPCR0_FTXSMDL_Msk (0x1U << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */
+#define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL_Pos (14U)
+#define DSI_WPCR0_CDOFFDL_Msk (0x1U << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */
+#define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL_Pos (16U)
+#define DSI_WPCR0_TDDL_Msk (0x1U << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */
+#define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */
+#define DSI_WPCR0_PDEN_Pos (18U)
+#define DSI_WPCR0_PDEN_Msk (0x1U << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */
+#define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */
+#define DSI_WPCR0_TCLKPREPEN_Pos (19U)
+#define DSI_WPCR0_TCLKPREPEN_Msk (0x1U << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */
+#define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */
+#define DSI_WPCR0_TCLKZEROEN_Pos (20U)
+#define DSI_WPCR0_TCLKZEROEN_Msk (0x1U << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */
+#define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */
+#define DSI_WPCR0_THSPREPEN_Pos (21U)
+#define DSI_WPCR0_THSPREPEN_Msk (0x1U << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */
+#define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */
+#define DSI_WPCR0_THSTRAILEN_Pos (22U)
+#define DSI_WPCR0_THSTRAILEN_Msk (0x1U << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */
+#define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */
+#define DSI_WPCR0_THSZEROEN_Pos (23U)
+#define DSI_WPCR0_THSZEROEN_Msk (0x1U << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */
+#define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */
+#define DSI_WPCR0_TLPXDEN_Pos (24U)
+#define DSI_WPCR0_TLPXDEN_Msk (0x1U << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */
+#define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */
+#define DSI_WPCR0_THSEXITEN_Pos (25U)
+#define DSI_WPCR0_THSEXITEN_Msk (0x1U << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */
+#define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */
+#define DSI_WPCR0_TLPXCEN_Pos (26U)
+#define DSI_WPCR0_TLPXCEN_Msk (0x1U << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */
+#define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */
+#define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
+#define DSI_WPCR0_TCLKPOSTEN_Msk (0x1U << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */
+#define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */
+
+/******************* Bit definition for DSI_WPCR1 register ***************/
+#define DSI_WPCR1_HSTXDCL_Pos (0U)
+#define DSI_WPCR1_HSTXDCL_Msk (0x3U << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */
+#define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXDCL0_Pos (0U)
+#define DSI_WPCR1_HSTXDCL0_Msk (0x1U << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */
+#define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
+#define DSI_WPCR1_HSTXDCL1_Pos (1U)
+#define DSI_WPCR1_HSTXDCL1_Msk (0x1U << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */
+#define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
+
+#define DSI_WPCR1_HSTXDDL_Pos (2U)
+#define DSI_WPCR1_HSTXDDL_Msk (0x3U << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */
+#define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXDDL0_Pos (2U)
+#define DSI_WPCR1_HSTXDDL0_Msk (0x1U << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */
+#define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
+#define DSI_WPCR1_HSTXDDL1_Pos (3U)
+#define DSI_WPCR1_HSTXDDL1_Msk (0x1U << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */
+#define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
+
+#define DSI_WPCR1_LPSRCCL_Pos (6U)
+#define DSI_WPCR1_LPSRCCL_Msk (0x3U << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */
+#define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
+#define DSI_WPCR1_LPSRCCL0_Pos (6U)
+#define DSI_WPCR1_LPSRCCL0_Msk (0x1U << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */
+#define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
+#define DSI_WPCR1_LPSRCCL1_Pos (7U)
+#define DSI_WPCR1_LPSRCCL1_Msk (0x1U << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */
+#define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
+
+#define DSI_WPCR1_LPSRCDL_Pos (8U)
+#define DSI_WPCR1_LPSRCDL_Msk (0x3U << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */
+#define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
+#define DSI_WPCR1_LPSRCDL0_Pos (8U)
+#define DSI_WPCR1_LPSRCDL0_Msk (0x1U << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */
+#define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
+#define DSI_WPCR1_LPSRCDL1_Pos (9U)
+#define DSI_WPCR1_LPSRCDL1_Msk (0x1U << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */
+#define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
+
+#define DSI_WPCR1_SDDC_Pos (12U)
+#define DSI_WPCR1_SDDC_Msk (0x1U << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */
+#define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */
+
+#define DSI_WPCR1_LPRXVCDL_Pos (14U)
+#define DSI_WPCR1_LPRXVCDL_Msk (0x3U << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */
+#define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */
+#define DSI_WPCR1_LPRXVCDL0_Pos (14U)
+#define DSI_WPCR1_LPRXVCDL0_Msk (0x1U << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */
+#define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
+#define DSI_WPCR1_LPRXVCDL1_Pos (15U)
+#define DSI_WPCR1_LPRXVCDL1_Msk (0x1U << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */
+#define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
+
+#define DSI_WPCR1_HSTXSRCCL_Pos (16U)
+#define DSI_WPCR1_HSTXSRCCL_Msk (0x3U << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */
+#define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
+#define DSI_WPCR1_HSTXSRCCL0_Msk (0x1U << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */
+#define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
+#define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
+#define DSI_WPCR1_HSTXSRCCL1_Msk (0x1U << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */
+#define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
+
+#define DSI_WPCR1_HSTXSRCDL_Pos (18U)
+#define DSI_WPCR1_HSTXSRCDL_Msk (0x3U << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */
+#define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
+#define DSI_WPCR1_HSTXSRCDL0_Msk (0x1U << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */
+#define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
+#define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
+#define DSI_WPCR1_HSTXSRCDL1_Msk (0x1U << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */
+#define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
+
+#define DSI_WPCR1_FLPRXLPM_Pos (22U)
+#define DSI_WPCR1_FLPRXLPM_Msk (0x1U << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */
+#define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
+
+#define DSI_WPCR1_LPRXFT_Pos (25U)
+#define DSI_WPCR1_LPRXFT_Msk (0x3U << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */
+#define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */
+#define DSI_WPCR1_LPRXFT0_Pos (25U)
+#define DSI_WPCR1_LPRXFT0_Msk (0x1U << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */
+#define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
+#define DSI_WPCR1_LPRXFT1_Pos (26U)
+#define DSI_WPCR1_LPRXFT1_Msk (0x1U << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */
+#define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
+
+/******************* Bit definition for DSI_WPCR2 register ***************/
+#define DSI_WPCR2_TCLKPREP_Pos (0U)
+#define DSI_WPCR2_TCLKPREP_Msk (0xFFU << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */
+#define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
+#define DSI_WPCR2_TCLKPREP0_Pos (0U)
+#define DSI_WPCR2_TCLKPREP0_Msk (0x1U << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */
+#define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
+#define DSI_WPCR2_TCLKPREP1_Pos (1U)
+#define DSI_WPCR2_TCLKPREP1_Msk (0x1U << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */
+#define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
+#define DSI_WPCR2_TCLKPREP2_Pos (2U)
+#define DSI_WPCR2_TCLKPREP2_Msk (0x1U << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */
+#define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
+#define DSI_WPCR2_TCLKPREP3_Pos (3U)
+#define DSI_WPCR2_TCLKPREP3_Msk (0x1U << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */
+#define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
+#define DSI_WPCR2_TCLKPREP4_Pos (4U)
+#define DSI_WPCR2_TCLKPREP4_Msk (0x1U << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */
+#define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
+#define DSI_WPCR2_TCLKPREP5_Pos (5U)
+#define DSI_WPCR2_TCLKPREP5_Msk (0x1U << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */
+#define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
+#define DSI_WPCR2_TCLKPREP6_Pos (6U)
+#define DSI_WPCR2_TCLKPREP6_Msk (0x1U << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */
+#define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
+#define DSI_WPCR2_TCLKPREP7_Pos (7U)
+#define DSI_WPCR2_TCLKPREP7_Msk (0x1U << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */
+#define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
+
+#define DSI_WPCR2_TCLKZERO_Pos (8U)
+#define DSI_WPCR2_TCLKZERO_Msk (0xFFU << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */
+#define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
+#define DSI_WPCR2_TCLKZERO0_Pos (8U)
+#define DSI_WPCR2_TCLKZERO0_Msk (0x1U << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */
+#define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
+#define DSI_WPCR2_TCLKZERO1_Pos (9U)
+#define DSI_WPCR2_TCLKZERO1_Msk (0x1U << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */
+#define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
+#define DSI_WPCR2_TCLKZERO2_Pos (10U)
+#define DSI_WPCR2_TCLKZERO2_Msk (0x1U << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */
+#define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
+#define DSI_WPCR2_TCLKZERO3_Pos (11U)
+#define DSI_WPCR2_TCLKZERO3_Msk (0x1U << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */
+#define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
+#define DSI_WPCR2_TCLKZERO4_Pos (12U)
+#define DSI_WPCR2_TCLKZERO4_Msk (0x1U << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */
+#define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
+#define DSI_WPCR2_TCLKZERO5_Pos (13U)
+#define DSI_WPCR2_TCLKZERO5_Msk (0x1U << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */
+#define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
+#define DSI_WPCR2_TCLKZERO6_Pos (14U)
+#define DSI_WPCR2_TCLKZERO6_Msk (0x1U << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */
+#define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
+#define DSI_WPCR2_TCLKZERO7_Pos (15U)
+#define DSI_WPCR2_TCLKZERO7_Msk (0x1U << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */
+#define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
+
+#define DSI_WPCR2_THSPREP_Pos (16U)
+#define DSI_WPCR2_THSPREP_Msk (0xFFU << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */
+#define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
+#define DSI_WPCR2_THSPREP0_Pos (16U)
+#define DSI_WPCR2_THSPREP0_Msk (0x1U << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */
+#define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
+#define DSI_WPCR2_THSPREP1_Pos (17U)
+#define DSI_WPCR2_THSPREP1_Msk (0x1U << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */
+#define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
+#define DSI_WPCR2_THSPREP2_Pos (18U)
+#define DSI_WPCR2_THSPREP2_Msk (0x1U << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */
+#define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
+#define DSI_WPCR2_THSPREP3_Pos (19U)
+#define DSI_WPCR2_THSPREP3_Msk (0x1U << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */
+#define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
+#define DSI_WPCR2_THSPREP4_Pos (20U)
+#define DSI_WPCR2_THSPREP4_Msk (0x1U << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */
+#define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
+#define DSI_WPCR2_THSPREP5_Pos (21U)
+#define DSI_WPCR2_THSPREP5_Msk (0x1U << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */
+#define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
+#define DSI_WPCR2_THSPREP6_Pos (22U)
+#define DSI_WPCR2_THSPREP6_Msk (0x1U << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */
+#define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
+#define DSI_WPCR2_THSPREP7_Pos (23U)
+#define DSI_WPCR2_THSPREP7_Msk (0x1U << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */
+#define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
+
+#define DSI_WPCR2_THSTRAIL_Pos (24U)
+#define DSI_WPCR2_THSTRAIL_Msk (0xFFU << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */
+#define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
+#define DSI_WPCR2_THSTRAIL0_Pos (24U)
+#define DSI_WPCR2_THSTRAIL0_Msk (0x1U << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */
+#define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
+#define DSI_WPCR2_THSTRAIL1_Pos (25U)
+#define DSI_WPCR2_THSTRAIL1_Msk (0x1U << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */
+#define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
+#define DSI_WPCR2_THSTRAIL2_Pos (26U)
+#define DSI_WPCR2_THSTRAIL2_Msk (0x1U << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */
+#define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
+#define DSI_WPCR2_THSTRAIL3_Pos (27U)
+#define DSI_WPCR2_THSTRAIL3_Msk (0x1U << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */
+#define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
+#define DSI_WPCR2_THSTRAIL4_Pos (28U)
+#define DSI_WPCR2_THSTRAIL4_Msk (0x1U << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */
+#define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
+#define DSI_WPCR2_THSTRAIL5_Pos (29U)
+#define DSI_WPCR2_THSTRAIL5_Msk (0x1U << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */
+#define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
+#define DSI_WPCR2_THSTRAIL6_Pos (30U)
+#define DSI_WPCR2_THSTRAIL6_Msk (0x1U << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */
+#define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
+#define DSI_WPCR2_THSTRAIL7_Pos (31U)
+#define DSI_WPCR2_THSTRAIL7_Msk (0x1U << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */
+#define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
+
+/******************* Bit definition for DSI_WPCR3 register ***************/
+#define DSI_WPCR3_THSZERO_Pos (0U)
+#define DSI_WPCR3_THSZERO_Msk (0xFFU << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */
+#define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
+#define DSI_WPCR3_THSZERO0_Pos (0U)
+#define DSI_WPCR3_THSZERO0_Msk (0x1U << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */
+#define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
+#define DSI_WPCR3_THSZERO1_Pos (1U)
+#define DSI_WPCR3_THSZERO1_Msk (0x1U << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */
+#define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
+#define DSI_WPCR3_THSZERO2_Pos (2U)
+#define DSI_WPCR3_THSZERO2_Msk (0x1U << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */
+#define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
+#define DSI_WPCR3_THSZERO3_Pos (3U)
+#define DSI_WPCR3_THSZERO3_Msk (0x1U << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */
+#define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
+#define DSI_WPCR3_THSZERO4_Pos (4U)
+#define DSI_WPCR3_THSZERO4_Msk (0x1U << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */
+#define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
+#define DSI_WPCR3_THSZERO5_Pos (5U)
+#define DSI_WPCR3_THSZERO5_Msk (0x1U << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */
+#define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
+#define DSI_WPCR3_THSZERO6_Pos (6U)
+#define DSI_WPCR3_THSZERO6_Msk (0x1U << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */
+#define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
+#define DSI_WPCR3_THSZERO7_Pos (7U)
+#define DSI_WPCR3_THSZERO7_Msk (0x1U << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */
+#define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
+
+#define DSI_WPCR3_TLPXD_Pos (8U)
+#define DSI_WPCR3_TLPXD_Msk (0xFFU << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */
+#define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
+#define DSI_WPCR3_TLPXD0_Pos (8U)
+#define DSI_WPCR3_TLPXD0_Msk (0x1U << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */
+#define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
+#define DSI_WPCR3_TLPXD1_Pos (9U)
+#define DSI_WPCR3_TLPXD1_Msk (0x1U << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */
+#define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
+#define DSI_WPCR3_TLPXD2_Pos (10U)
+#define DSI_WPCR3_TLPXD2_Msk (0x1U << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */
+#define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
+#define DSI_WPCR3_TLPXD3_Pos (11U)
+#define DSI_WPCR3_TLPXD3_Msk (0x1U << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */
+#define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
+#define DSI_WPCR3_TLPXD4_Pos (12U)
+#define DSI_WPCR3_TLPXD4_Msk (0x1U << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */
+#define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
+#define DSI_WPCR3_TLPXD5_Pos (13U)
+#define DSI_WPCR3_TLPXD5_Msk (0x1U << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */
+#define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
+#define DSI_WPCR3_TLPXD6_Pos (14U)
+#define DSI_WPCR3_TLPXD6_Msk (0x1U << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */
+#define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
+#define DSI_WPCR3_TLPXD7_Pos (15U)
+#define DSI_WPCR3_TLPXD7_Msk (0x1U << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */
+#define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
+
+#define DSI_WPCR3_THSEXIT_Pos (16U)
+#define DSI_WPCR3_THSEXIT_Msk (0xFFU << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */
+#define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
+#define DSI_WPCR3_THSEXIT0_Pos (16U)
+#define DSI_WPCR3_THSEXIT0_Msk (0x1U << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */
+#define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
+#define DSI_WPCR3_THSEXIT1_Pos (17U)
+#define DSI_WPCR3_THSEXIT1_Msk (0x1U << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */
+#define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
+#define DSI_WPCR3_THSEXIT2_Pos (18U)
+#define DSI_WPCR3_THSEXIT2_Msk (0x1U << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */
+#define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
+#define DSI_WPCR3_THSEXIT3_Pos (19U)
+#define DSI_WPCR3_THSEXIT3_Msk (0x1U << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */
+#define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
+#define DSI_WPCR3_THSEXIT4_Pos (20U)
+#define DSI_WPCR3_THSEXIT4_Msk (0x1U << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */
+#define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
+#define DSI_WPCR3_THSEXIT5_Pos (21U)
+#define DSI_WPCR3_THSEXIT5_Msk (0x1U << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */
+#define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
+#define DSI_WPCR3_THSEXIT6_Pos (22U)
+#define DSI_WPCR3_THSEXIT6_Msk (0x1U << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */
+#define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
+#define DSI_WPCR3_THSEXIT7_Pos (23U)
+#define DSI_WPCR3_THSEXIT7_Msk (0x1U << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */
+#define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
+
+#define DSI_WPCR3_TLPXC_Pos (24U)
+#define DSI_WPCR3_TLPXC_Msk (0xFFU << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */
+#define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
+#define DSI_WPCR3_TLPXC0_Pos (24U)
+#define DSI_WPCR3_TLPXC0_Msk (0x1U << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */
+#define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
+#define DSI_WPCR3_TLPXC1_Pos (25U)
+#define DSI_WPCR3_TLPXC1_Msk (0x1U << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */
+#define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
+#define DSI_WPCR3_TLPXC2_Pos (26U)
+#define DSI_WPCR3_TLPXC2_Msk (0x1U << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */
+#define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
+#define DSI_WPCR3_TLPXC3_Pos (27U)
+#define DSI_WPCR3_TLPXC3_Msk (0x1U << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */
+#define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
+#define DSI_WPCR3_TLPXC4_Pos (28U)
+#define DSI_WPCR3_TLPXC4_Msk (0x1U << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */
+#define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
+#define DSI_WPCR3_TLPXC5_Pos (29U)
+#define DSI_WPCR3_TLPXC5_Msk (0x1U << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */
+#define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
+#define DSI_WPCR3_TLPXC6_Pos (30U)
+#define DSI_WPCR3_TLPXC6_Msk (0x1U << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */
+#define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
+#define DSI_WPCR3_TLPXC7_Pos (31U)
+#define DSI_WPCR3_TLPXC7_Msk (0x1U << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */
+#define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
+
+/******************* Bit definition for DSI_WPCR4 register ***************/
+#define DSI_WPCR4_TCLKPOST_Pos (0U)
+#define DSI_WPCR4_TCLKPOST_Msk (0xFFU << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */
+#define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
+#define DSI_WPCR4_TCLKPOST0_Pos (0U)
+#define DSI_WPCR4_TCLKPOST0_Msk (0x1U << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */
+#define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
+#define DSI_WPCR4_TCLKPOST1_Pos (1U)
+#define DSI_WPCR4_TCLKPOST1_Msk (0x1U << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */
+#define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
+#define DSI_WPCR4_TCLKPOST2_Pos (2U)
+#define DSI_WPCR4_TCLKPOST2_Msk (0x1U << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */
+#define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
+#define DSI_WPCR4_TCLKPOST3_Pos (3U)
+#define DSI_WPCR4_TCLKPOST3_Msk (0x1U << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */
+#define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
+#define DSI_WPCR4_TCLKPOST4_Pos (4U)
+#define DSI_WPCR4_TCLKPOST4_Msk (0x1U << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */
+#define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
+#define DSI_WPCR4_TCLKPOST5_Pos (5U)
+#define DSI_WPCR4_TCLKPOST5_Msk (0x1U << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */
+#define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
+#define DSI_WPCR4_TCLKPOST6_Pos (6U)
+#define DSI_WPCR4_TCLKPOST6_Msk (0x1U << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */
+#define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
+#define DSI_WPCR4_TCLKPOST7_Pos (7U)
+#define DSI_WPCR4_TCLKPOST7_Msk (0x1U << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */
+#define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
+
+/******************* Bit definition for DSI_WRPCR register ***************/
+#define DSI_WRPCR_PLLEN_Pos (0U)
+#define DSI_WRPCR_PLLEN_Msk (0x1U << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */
+#define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */
+#define DSI_WRPCR_PLL_NDIV_Pos (2U)
+#define DSI_WRPCR_PLL_NDIV_Msk (0x7FU << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */
+#define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0_Pos (2U)
+#define DSI_WRPCR_PLL_NDIV0_Msk (0x1U << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */
+#define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
+#define DSI_WRPCR_PLL_NDIV1_Pos (3U)
+#define DSI_WRPCR_PLL_NDIV1_Msk (0x1U << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */
+#define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
+#define DSI_WRPCR_PLL_NDIV2_Pos (4U)
+#define DSI_WRPCR_PLL_NDIV2_Msk (0x1U << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */
+#define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
+#define DSI_WRPCR_PLL_NDIV3_Pos (5U)
+#define DSI_WRPCR_PLL_NDIV3_Msk (0x1U << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */
+#define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
+#define DSI_WRPCR_PLL_NDIV4_Pos (6U)
+#define DSI_WRPCR_PLL_NDIV4_Msk (0x1U << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */
+#define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
+#define DSI_WRPCR_PLL_NDIV5_Pos (7U)
+#define DSI_WRPCR_PLL_NDIV5_Msk (0x1U << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */
+#define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
+#define DSI_WRPCR_PLL_NDIV6_Pos (8U)
+#define DSI_WRPCR_PLL_NDIV6_Msk (0x1U << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */
+#define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
+
+#define DSI_WRPCR_PLL_IDF_Pos (11U)
+#define DSI_WRPCR_PLL_IDF_Msk (0xFU << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */
+#define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0_Pos (11U)
+#define DSI_WRPCR_PLL_IDF0_Msk (0x1U << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */
+#define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
+#define DSI_WRPCR_PLL_IDF1_Pos (12U)
+#define DSI_WRPCR_PLL_IDF1_Msk (0x1U << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */
+#define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
+#define DSI_WRPCR_PLL_IDF2_Pos (13U)
+#define DSI_WRPCR_PLL_IDF2_Msk (0x1U << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */
+#define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
+#define DSI_WRPCR_PLL_IDF3_Pos (14U)
+#define DSI_WRPCR_PLL_IDF3_Msk (0x1U << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */
+#define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
+
+#define DSI_WRPCR_PLL_ODF_Pos (16U)
+#define DSI_WRPCR_PLL_ODF_Msk (0x3U << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */
+#define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0_Pos (16U)
+#define DSI_WRPCR_PLL_ODF0_Msk (0x1U << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */
+#define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
+#define DSI_WRPCR_PLL_ODF1_Pos (17U)
+#define DSI_WRPCR_PLL_ODF1_Msk (0x1U << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */
+#define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
+
+#define DSI_WRPCR_REGEN_Pos (24U)
+#define DSI_WRPCR_REGEN_Msk (0x1U << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */
+#define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos (20U)
+#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos (21U)
+#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos (22U)
+#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos (20U)
+#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos (21U)
+#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos (22U)
+#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#define EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos (20U)
+#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos (21U)
+#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos (22U)
+#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos (20U)
+#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos (21U)
+#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos (22U)
+#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos (20U)
+#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos (21U)
+#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos (22U)
+#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos (20U)
+#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos (21U)
+#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos (22U)
+#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
+#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
+#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
+#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_SOP_Pos (1U)
+#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_SOP FLASH_SR_SOP_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_PGPERR_Pos (6U)
+#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_RDERR_Pos (8U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_SER_Pos (1U)
+#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_SER FLASH_CR_SER_Msk
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB_Pos (3U)
+#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
+#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
+#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
+#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
+#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
+#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos (8U)
+#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
+#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_MER2_Pos (15U)
+#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
+
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
+#define FLASH_OPTCR_BFB2_Pos (4U)
+#define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
+#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
+#define FLASH_OPTCR_WDG_SW_Pos (5U)
+#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
+#define FLASH_OPTCR_RDP_Pos (8U)
+#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
+#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos (16U)
+#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M_Pos (30U)
+#define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
+#define FLASH_OPTCR_SPRMOD_Pos (31U)
+#define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP_Pos (16U)
+#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
+#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN_Pos (0U)
+#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN_Pos (1U)
+#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP_Pos (2U)
+#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR1_MWID_Pos (4U)
+#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR1_FACCEN_Pos (6U)
+#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN_Pos (8U)
+#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL_Pos (9U)
+#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR1_WAITCFG_Pos (11U)
+#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR1_WREN_Pos (12U)
+#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR1_WAITEN_Pos (13U)
+#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD_Pos (14U)
+#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE_Pos (16U)
+#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+#define FMC_BCR1_CBURSTRW_Pos (19U)
+#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_WFDIS_Pos (21U)
+#define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN_Pos (0U)
+#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN_Pos (1U)
+#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP_Pos (2U)
+#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR2_MWID_Pos (4U)
+#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR2_FACCEN_Pos (6U)
+#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN_Pos (8U)
+#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL_Pos (9U)
+#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR2_WAITCFG_Pos (11U)
+#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR2_WREN_Pos (12U)
+#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR2_WAITEN_Pos (13U)
+#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD_Pos (14U)
+#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW_Pos (19U)
+#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN_Pos (0U)
+#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN_Pos (1U)
+#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP_Pos (2U)
+#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR3_MWID_Pos (4U)
+#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR3_FACCEN_Pos (6U)
+#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN_Pos (8U)
+#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL_Pos (9U)
+#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR3_WAITCFG_Pos (11U)
+#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR3_WREN_Pos (12U)
+#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR3_WAITEN_Pos (13U)
+#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD_Pos (14U)
+#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW_Pos (19U)
+#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN_Pos (0U)
+#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN_Pos (1U)
+#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP_Pos (2U)
+#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR4_MWID_Pos (4U)
+#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR4_FACCEN_Pos (6U)
+#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN_Pos (8U)
+#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL_Pos (9U)
+#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR4_WAITCFG_Pos (11U)
+#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR4_WREN_Pos (12U)
+#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR4_WAITEN_Pos (13U)
+#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD_Pos (14U)
+#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW_Pos (19U)
+#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET_Pos (0U)
+#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR1_ADDHLD_Pos (4U)
+#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR1_DATAST_Pos (8U)
+#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR1_BUSTURN_Pos (16U)
+#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR1_CLKDIV_Pos (20U)
+#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR1_DATLAT_Pos (24U)
+#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR1_ACCMOD_Pos (28U)
+#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET_Pos (0U)
+#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR2_ADDHLD_Pos (4U)
+#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR2_DATAST_Pos (8U)
+#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR2_BUSTURN_Pos (16U)
+#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR2_CLKDIV_Pos (20U)
+#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR2_DATLAT_Pos (24U)
+#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR2_ACCMOD_Pos (28U)
+#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET_Pos (0U)
+#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR3_ADDHLD_Pos (4U)
+#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR3_DATAST_Pos (8U)
+#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR3_BUSTURN_Pos (16U)
+#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR3_CLKDIV_Pos (20U)
+#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR3_DATLAT_Pos (24U)
+#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR3_ACCMOD_Pos (28U)
+#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET_Pos (0U)
+#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR4_ADDHLD_Pos (4U)
+#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR4_DATAST_Pos (8U)
+#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR4_BUSTURN_Pos (16U)
+#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR4_CLKDIV_Pos (20U)
+#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR4_DATLAT_Pos (24U)
+#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR4_ACCMOD_Pos (28U)
+#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET_Pos (0U)
+#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR1_ADDHLD_Pos (4U)
+#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR1_DATAST_Pos (8U)
+#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR1_BUSTURN_Pos (16U)
+#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR1_ACCMOD_Pos (28U)
+#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET_Pos (0U)
+#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR2_ADDHLD_Pos (4U)
+#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR2_DATAST_Pos (8U)
+#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR2_BUSTURN_Pos (16U)
+#define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR2_ACCMOD_Pos (28U)
+#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET_Pos (0U)
+#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR3_ADDHLD_Pos (4U)
+#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR3_DATAST_Pos (8U)
+#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR3_BUSTURN_Pos (16U)
+#define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR3_ACCMOD_Pos (28U)
+#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET_Pos (0U)
+#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR4_ADDHLD_Pos (4U)
+#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR4_DATAST_Pos (8U)
+#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR4_BUSTURN_Pos (16U)
+#define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTR4_ACCMOD_Pos (28U)
+#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_PCR register *******************/
+#define FMC_PCR_PWAITEN_Pos (1U)
+#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN_Pos (2U)
+#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos (3U)
+#define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR_PWID_Pos (4U)
+#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos (6U)
+#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR_Pos (9U)
+#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos (13U)
+#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos (17U)
+#define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FMC_SR register *******************/
+#define FMC_SR_IRS_Pos (0U)
+#define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS_Pos (1U)
+#define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR_IFS_Pos (2U)
+#define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN_Pos (3U)
+#define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN_Pos (4U)
+#define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN_Pos (5U)
+#define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos (6U)
+#define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET2_Pos (0U)
+#define FMC_PMEM_MEMSET2_Msk (0xFFU << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET2_0 (0x01U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET2_1 (0x02U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET2_2 (0x04U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET2_3 (0x08U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET2_4 (0x10U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET2_5 (0x20U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET2_6 (0x40U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET2_7 (0x80U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT2_Pos (8U)
+#define FMC_PMEM_MEMWAIT2_Msk (0xFFU << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT2_0 (0x01U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT2_1 (0x02U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT2_2 (0x04U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT2_3 (0x08U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT2_4 (0x10U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT2_5 (0x20U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT2_6 (0x40U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT2_7 (0x80U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD2_Pos (16U)
+#define FMC_PMEM_MEMHOLD2_Msk (0xFFU << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD2_0 (0x01U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD2_1 (0x02U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD2_2 (0x04U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD2_3 (0x08U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD2_4 (0x10U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD2_5 (0x20U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD2_6 (0x40U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD2_7 (0x80U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ2_Pos (24U)
+#define FMC_PMEM_MEMHIZ2_Msk (0xFFU << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ2_0 (0x01U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ2_1 (0x02U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ2_2 (0x04U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ2_3 (0x08U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ2_4 (0x10U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ2_5 (0x20U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ2_6 (0x40U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ2_7 (0x80U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT register ******************/
+#define FMC_PATT_ATTSET2_Pos (0U)
+#define FMC_PATT_ATTSET2_Msk (0xFFU << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */
+#define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET2_0 (0x01U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */
+#define FMC_PATT_ATTSET2_1 (0x02U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */
+#define FMC_PATT_ATTSET2_2 (0x04U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */
+#define FMC_PATT_ATTSET2_3 (0x08U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */
+#define FMC_PATT_ATTSET2_4 (0x10U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */
+#define FMC_PATT_ATTSET2_5 (0x20U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */
+#define FMC_PATT_ATTSET2_6 (0x40U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */
+#define FMC_PATT_ATTSET2_7 (0x80U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT2_Pos (8U)
+#define FMC_PATT_ATTWAIT2_Msk (0xFFU << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT2_0 (0x01U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT2_1 (0x02U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT2_2 (0x04U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT2_3 (0x08U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT2_4 (0x10U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT2_5 (0x20U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT2_6 (0x40U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT2_7 (0x80U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD2_Pos (16U)
+#define FMC_PATT_ATTHOLD2_Msk (0xFFU << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD2_0 (0x01U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD2_1 (0x02U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD2_2 (0x04U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD2_3 (0x08U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD2_4 (0x10U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD2_5 (0x20U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD2_6 (0x40U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD2_7 (0x80U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ2_Pos (24U)
+#define FMC_PATT_ATTHIZ2_Msk (0xFFU << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ2_0 (0x01U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ2_1 (0x02U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ2_2 (0x04U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ2_3 (0x08U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ2_4 (0x10U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ2_5 (0x20U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ2_6 (0x40U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ2_7 (0x80U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_ECCR register ******************/
+#define FMC_ECCR_ECC2_Pos (0U)
+#define FMC_ECCR_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC_Pos (0U)
+#define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR1_NR_Pos (2U)
+#define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR1_MWID_Pos (4U)
+#define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR1_NB_Pos (6U)
+#define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS_Pos (7U)
+#define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR1_WP_Pos (9U)
+#define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK_Pos (10U)
+#define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR1_RBURST_Pos (12U)
+#define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE_Pos (13U)
+#define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC_Pos (0U)
+#define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
+#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
+#define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
+
+#define FMC_SDCR2_NR_Pos (2U)
+#define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
+#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
+#define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
+
+#define FMC_SDCR2_MWID_Pos (4U)
+#define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_SDCR2_NB_Pos (6U)
+#define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
+#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS_Pos (7U)
+#define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
+#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
+#define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCR2_WP_Pos (9U)
+#define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
+#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK_Pos (10U)
+#define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
+#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
+#define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
+
+#define FMC_SDCR2_RBURST_Pos (12U)
+#define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
+#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE_Pos (13U)
+#define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
+#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
+#define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD_Pos (0U)
+#define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR1_TXSR_Pos (4U)
+#define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR1_TRAS_Pos (8U)
+#define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR1_TRC_Pos (12U)
+#define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR1_TWR_Pos (16U)
+#define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR1_TRP_Pos (20U)
+#define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR1_TRCD_Pos (24U)
+#define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD_Pos (0U)
+#define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
+#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
+#define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
+#define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
+#define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
+
+#define FMC_SDTR2_TXSR_Pos (4U)
+#define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
+#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
+#define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
+#define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
+#define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
+
+#define FMC_SDTR2_TRAS_Pos (8U)
+#define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
+#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
+#define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
+#define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
+#define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
+
+#define FMC_SDTR2_TRC_Pos (12U)
+#define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
+#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
+#define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
+#define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
+
+#define FMC_SDTR2_TWR_Pos (16U)
+#define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
+#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
+#define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
+#define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
+
+#define FMC_SDTR2_TRP_Pos (20U)
+#define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
+#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
+#define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
+#define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
+
+#define FMC_SDTR2_TRCD_Pos (24U)
+#define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
+#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
+#define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
+#define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE_Pos (0U)
+#define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
+#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
+
+#define FMC_SDCMR_CTB2_Pos (3U)
+#define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos (4U)
+#define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos (5U)
+#define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos (9U)
+#define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE_Pos (0U)
+#define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
+#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos (1U)
+#define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos (14U)
+#define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE_Pos (0U)
+#define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
+#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos (1U)
+#define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
+#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos (3U)
+#define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
+#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
+#define FMC_SDSR_BUSY_Pos (5U)
+#define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
+#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF_Pos (0U)
+#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
+#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos (4U)
+#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH_Pos (0U)
+#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
+#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW_Pos (16U)
+#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP_Pos (0U)
+#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP_Pos (16U)
+#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH_Pos (0U)
+#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW_Pos (16U)
+#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH_Pos (0U)
+#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW_Pos (16U)
+#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN_Pos (0U)
+#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW_Pos (4U)
+#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
+#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
+#define LTDC_GCR_DGW_Pos (8U)
+#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
+#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
+#define LTDC_GCR_DRW_Pos (12U)
+#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
+#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
+#define LTDC_GCR_DEN_Pos (16U)
+#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
+#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
+#define LTDC_GCR_PCPOL_Pos (28U)
+#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL_Pos (29U)
+#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL_Pos (30U)
+#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL_Pos (31U)
+#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN LTDC_GCR_DEN
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR_Pos (0U)
+#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
+#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
+#define LTDC_SRCR_VBR_Pos (1U)
+#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
+#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos (0U)
+#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN_Pos (8U)
+#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos (16U)
+#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE_Pos (0U)
+#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
+#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE_Pos (1U)
+#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
+#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE_Pos (2U)
+#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
+#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE_Pos (3U)
+#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
+#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF_Pos (0U)
+#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
+#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos (1U)
+#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
+#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos (2U)
+#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos (3U)
+#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
+#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF_Pos (0U)
+#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
+#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos (1U)
+#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos (2U)
+#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos (3U)
+#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos (0U)
+#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS_Pos (0U)
+#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos (16U)
+#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES_Pos (0U)
+#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
+#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES_Pos (1U)
+#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
+#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS_Pos (2U)
+#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS_Pos (3U)
+#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN_Pos (0U)
+#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
+#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN_Pos (1U)
+#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN_Pos (4U)
+#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN_Pos (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos (16U)
+#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF_Pos (0U)
+#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos (0U)
+#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN_Pos (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos (16U)
+#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA_Pos (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2_Pos (0U)
+#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos (8U)
+#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP_Pos (16U)
+#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN_Pos (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
+#define LTDC_LxCLUTWR_RED_Pos (16U)
+#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS_Pos (9U)
+#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
+#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS_Pos (10U)
+#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
+#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS_Pos (11U)
+#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
+#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1_Pos (13U)
+#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
+#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS_Pos (14U)
+#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN_Pos (16U)
+#define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
+#define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
+#define PWR_CR_ODSWEN_Pos (17U)
+#define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
+#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN_Pos (18U)
+#define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
+#define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
+#define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_BRR_Pos (3U)
+#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
+#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
+#define PWR_CSR_WUPP_Pos (7U)
+#define PWR_CSR_WUPP_Msk (0x1U << PWR_CSR_WUPP_Pos) /*!< 0x00000080 */
+#define PWR_CSR_WUPP PWR_CSR_WUPP_Msk /*!< WKUP pin Polarity */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+#define PWR_CSR_BRE_Pos (9U)
+#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
+#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY_Pos (14U)
+#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY_Pos (16U)
+#define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
+#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY_Pos (17U)
+#define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
+#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
+#define PWR_CSR_UDRDY_Pos (18U)
+#define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
+#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
+/* Legacy define */
+#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN_Pos (0U)
+#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos (1U)
+#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos (2U)
+#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos (3U)
+#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos (4U)
+#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos (6U)
+#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
+#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos (7U)
+#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos (8U)
+#define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
+#define QUADSPI_CR_TEIE_Pos (16U)
+#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos (17U)
+#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos (18U)
+#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos (19U)
+#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos (20U)
+#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos (22U)
+#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos (23U)
+#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos (24U)
+#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE_Pos (0U)
+#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos (8U)
+#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos (16U)
+#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF_Pos (0U)
+#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos (1U)
+#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos (2U)
+#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos (3U)
+#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos (4U)
+#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos (5U)
+#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos (8U)
+#define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF_Pos (0U)
+#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos (1U)
+#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos (3U)
+#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos (4U)
+#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL_Pos (0U)
+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos (8U)
+#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos (10U)
+#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos (12U)
+#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos (14U)
+#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos (16U)
+#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos (18U)
+#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos (24U)
+#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos (26U)
+#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos (28U)
+#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos (30U)
+#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM_Pos (31U)
+#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS_Pos (0U)
+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA_Pos (0U)
+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK_Pos (0U)
+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH_Pos (0U)
+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL_Pos (0U)
+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
+
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
+#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
+#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos (26U)
+#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
+#define RCC_CR_PLLI2SRDY_Pos (27U)
+#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
+
+#define RCC_CR_PLLSAION_Pos (28U)
+#define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
+#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
+#define RCC_CR_PLLSAIRDY_Pos (29U)
+#define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
+#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_Pos (0U)
+#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos (6U)
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos (16U)
+#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
+#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
+
+#define RCC_PLLCFGR_PLLR_Pos (28U)
+#define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
+#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (10U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (13U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos (16U)
+#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
+#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos (21U)
+#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
+#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos (23U)
+#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
+
+#define RCC_CFGR_MCO1PRE_Pos (24U)
+#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
+#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos (27U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
+#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos (30U)
+#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
+#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
+
+#define RCC_CIR_PLLSAIRDYF_Pos (6U)
+#define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
+
+#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
+#define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
+#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
+#define RCC_CIR_PLLSAIRDYC_Pos (22U)
+#define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
+#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
+
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
+#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
+#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
+#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
+#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
+#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
+#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
+#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
+#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
+#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
+#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
+#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
+#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
+#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
+
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
+#define RCC_APB1RSTR_UART7RST_Pos (30U)
+#define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
+#define RCC_APB1RSTR_UART8RST_Pos (31U)
+#define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (4U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos (5U)
+#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_ADCRST_Pos (8U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
+#define RCC_APB2RSTR_SDIORST_Pos (11U)
+#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SPI6RST_Pos (21U)
+#define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_LTDCRST_Pos (26U)
+#define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
+#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
+#define RCC_APB2RSTR_DSIRST_Pos (27U)
+#define RCC_APB2RSTR_DSIRST_Msk (0x1U << RCC_APB2RSTR_DSIRST_Pos) /*!< 0x08000000 */
+#define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
+#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
+#define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
+#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
+#define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
+#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
+#define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
+#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
+#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
+#define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
+#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
+#define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
+#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
+#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
+#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
+#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
+#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
+#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
+#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_DCMIEN_Pos (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos (6U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FMCEN_Pos (0U)
+#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos (1U)
+#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
+#define RCC_APB1ENR_I2C3EN_Pos (23U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
+#define RCC_APB1ENR_UART7EN_Pos (30U)
+#define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
+#define RCC_APB1ENR_UART8EN_Pos (31U)
+#define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_Pos (0U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (1U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (4U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos (5U)
+#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_ADC1EN_Pos (8U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
+#define RCC_APB2ENR_ADC2EN_Pos (9U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
+#define RCC_APB2ENR_ADC3EN_Pos (10U)
+#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
+#define RCC_APB2ENR_SDIOEN_Pos (11U)
+#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos (13U)
+#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_TIM9EN_Pos (16U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
+#define RCC_APB2ENR_TIM10EN_Pos (17U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
+#define RCC_APB2ENR_TIM11EN_Pos (18U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos (20U)
+#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SPI6EN_Pos (21U)
+#define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
+#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos (22U)
+#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_LTDCEN_Pos (26U)
+#define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
+#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
+#define RCC_APB2ENR_DSIEN_Pos (27U)
+#define RCC_APB2ENR_DSIEN_Msk (0x1U << RCC_APB2ENR_DSIEN_Pos) /*!< 0x08000000 */
+#define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
+#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
+#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
+#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
+#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
+#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
+#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
+#define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
+#define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
+#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
+
+#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
+#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
+#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
+#define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
+#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
+#define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
+#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
+#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
+#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
+#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
+#define RCC_APB2LPENR_DSILPEN_Pos (27U)
+#define RCC_APB2LPENR_DSILPEN_Msk (0x1U << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+#define RCC_BDCR_LSEMOD_Pos (3U)
+#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_BORRSTF_Pos (25U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_Pos (0U)
+#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
+#define RCC_SSCGR_INCSTEP_Pos (13U)
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
+#define RCC_SSCGR_SPREADSEL_Pos (30U)
+#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
+#define RCC_SSCGR_SSCGEN_Pos (31U)
+#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
+#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
+#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
+#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
+#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
+#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
+#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
+#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
+#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
+#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
+
+#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
+#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
+#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
+#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
+#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
+#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
+#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
+
+#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
+#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
+#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
+#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
+#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
+#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
+#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
+
+#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
+#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
+#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
+#define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
+#define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
+#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
+#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
+#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
+#define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
+#define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
+#define RCC_DCKCFGR_TIMPRE_Pos (24U)
+#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
+#define RCC_DCKCFGR_CK48MSEL_Pos (27U)
+#define RCC_DCKCFGR_CK48MSEL_Msk (0x1U << RCC_DCKCFGR_CK48MSEL_Pos) /*!< 0x08000000 */
+#define RCC_DCKCFGR_CK48MSEL RCC_DCKCFGR_CK48MSEL_Msk
+#define RCC_DCKCFGR_SDIOSEL_Pos (28U)
+#define RCC_DCKCFGR_SDIOSEL_Msk (0x1U << RCC_DCKCFGR_SDIOSEL_Pos) /*!< 0x10000000 */
+#define RCC_DCKCFGR_SDIOSEL RCC_DCKCFGR_SDIOSEL_Msk
+#define RCC_DCKCFGR_DSISEL_Pos (29U)
+#define RCC_DCKCFGR_DSISEL_Msk (0x1U << RCC_DCKCFGR_DSISEL_Pos) /*!< 0x20000000 */
+#define RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_Msk
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
+#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos (7U)
+#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
+#define RTC_CR_DCE RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS_Pos (7U)
+#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
+#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos (0U)
+#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
+#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TSINSEL_Pos (17U)
+#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
+#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
+#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos (11U)
+#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos (7U)
+#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos (3U)
+#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos (2U)
+#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos (0U)
+#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 0x000000014U
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_Pos (0U)
+#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos (4U)
+#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE_Pos (0U)
+#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos (2U)
+#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos (5U)
+#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
+#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
+#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos (8U)
+#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR_Pos (9U)
+#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN_Pos (10U)
+#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos (12U)
+#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV_Pos (13U)
+#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
+#define SAI_xCR1_SAIEN_Pos (16U)
+#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN_Pos (17U)
+#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
+#define SAI_xCR1_NODIV_Pos (19U)
+#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV_Pos (20U)
+#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH_Pos (0U)
+#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos (3U)
+#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS_Pos (4U)
+#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos (5U)
+#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL_Pos (6U)
+#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT_Pos (7U)
+#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos (13U)
+#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
+
+#define SAI_xCR2_COMP_Pos (14U)
+#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL_Pos (0U)
+#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos (8U)
+#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos (16U)
+#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos (17U)
+#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF_Pos (18U)
+#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF_Pos (0U)
+#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos (8U)
+#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos (16U)
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE_Pos (0U)
+#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE_Pos (1U)
+#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE_Pos (2U)
+#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE_Pos (3U)
+#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE_Pos (4U)
+#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE_Pos (5U)
+#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE_Pos (6U)
+#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR_Pos (0U)
+#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET_Pos (1U)
+#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
+#define SAI_xSR_WCKCFG_Pos (2U)
+#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ_Pos (3U)
+#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
+#define SAI_xSR_CNRDY_Pos (4U)
+#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
+#define SAI_xSR_AFSDET_Pos (5U)
+#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET_Pos (6U)
+#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL_Pos (16U)
+#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR_Pos (0U)
+#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ_Pos (3U)
+#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY_Pos (4U)
+#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET_Pos (5U)
+#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET_Pos (6U)
+#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA_Pos (0U)
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
+#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
+#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
+#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
+#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
+/* Legacy Defines */
+#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2_Pos (16U)
+#define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
+#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2_Pos (17U)
+#define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
+#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2_Pos (18U)
+#define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
+#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
+#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1_RMP_Pos (0U)
+#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos (6U)
+#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos (10U)
+#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD_Pos (23U)
+#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
+#define ETH_MACCR_JD_Pos (22U)
+#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
+#define ETH_MACCR_IFG_Pos (17U)
+#define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
+#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD_Pos (16U)
+#define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES_Pos (14U)
+#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
+#define ETH_MACCR_ROD_Pos (13U)
+#define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
+#define ETH_MACCR_LM_Pos (12U)
+#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
+#define ETH_MACCR_DM_Pos (11U)
+#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
+#define ETH_MACCR_IPCO_Pos (10U)
+#define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
+#define ETH_MACCR_RD_Pos (9U)
+#define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
+#define ETH_MACCR_APCS_Pos (7U)
+#define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
+#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL_Pos (5U)
+#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC_Pos (4U)
+#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
+#define ETH_MACCR_TE_Pos (3U)
+#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
+#define ETH_MACCR_RE_Pos (2U)
+#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA_Pos (31U)
+#define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
+#define ETH_MACFFR_HPF_Pos (10U)
+#define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
+#define ETH_MACFFR_SAF_Pos (9U)
+#define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
+#define ETH_MACFFR_SAIF_Pos (8U)
+#define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
+#define ETH_MACFFR_PCF_Pos (6U)
+#define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
+#define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
+#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
+#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
+#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD_Pos (5U)
+#define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
+#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
+#define ETH_MACFFR_PAM_Pos (4U)
+#define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
+#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF_Pos (3U)
+#define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
+#define ETH_MACFFR_HM_Pos (2U)
+#define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
+#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
+#define ETH_MACFFR_HU_Pos (1U)
+#define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
+#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
+#define ETH_MACFFR_PM_Pos (0U)
+#define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
+#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos (0U)
+#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos (0U)
+#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA_Pos (11U)
+#define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
+#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
+#define ETH_MACMIIAR_MR_Pos (6U)
+#define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
+#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR_Pos (2U)
+#define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
+#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
+#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIAR_CR_Div62_Pos (2U)
+#define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
+#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define ETH_MACMIIAR_CR_Div16_Pos (3U)
+#define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
+#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ETH_MACMIIAR_CR_Div26_Pos (2U)
+#define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
+#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_CR_Div102_Pos (4U)
+#define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
+#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW_Pos (1U)
+#define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
+#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
+#define ETH_MACMIIAR_MB_Pos (0U)
+#define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD_Pos (0U)
+#define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT_Pos (16U)
+#define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
+#define ETH_MACFCR_ZQPD_Pos (7U)
+#define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
+#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT_Pos (4U)
+#define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+#define ETH_MACFCR_PLT_Minus28_Pos (4U)
+#define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
+#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACFCR_PLT_Minus144_Pos (5U)
+#define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
+#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256_Pos (4U)
+#define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD_Pos (3U)
+#define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
+#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE_Pos (2U)
+#define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
+#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
+#define ETH_MACFCR_TFCE_Pos (1U)
+#define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
+#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA_Pos (0U)
+#define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
+#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC_Pos (16U)
+#define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
+#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI_Pos (0U)
+#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D_Pos (0U)
+#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
+#define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
+#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU_Pos (9U)
+#define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
+#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
+#define ETH_MACPMTCSR_WFR_Pos (6U)
+#define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
+#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR_Pos (5U)
+#define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
+#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE_Pos (2U)
+#define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
+#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE_Pos (1U)
+#define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
+#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD_Pos (0U)
+#define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
+#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
+
+/* Bit definition for Ethernet MAC debug Register */
+#define ETH_MACDBGR_TFF_Pos (25U)
+#define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
+#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
+#define ETH_MACDBGR_TFNE_Pos (24U)
+#define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
+#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
+#define ETH_MACDBGR_TFWA_Pos (22U)
+#define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
+#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
+#define ETH_MACDBGR_TFRS_Pos (20U)
+#define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
+#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
+#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
+#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
+#define ETH_MACDBGR_TFRS_READ_Pos (20U)
+#define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
+#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
+#define ETH_MACDBGR_MTP_Pos (19U)
+#define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
+#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
+#define ETH_MACDBGR_MTFCS_Pos (17U)
+#define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
+#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
+#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
+#define ETH_MACDBGR_MMTEA_Pos (16U)
+#define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
+#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
+#define ETH_MACDBGR_RFFL_Pos (8U)
+#define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
+#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
+#define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
+#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
+#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
+#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
+#define ETH_MACDBGR_RFRCS_Pos (5U)
+#define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
+#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
+#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
+#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
+#define ETH_MACDBGR_RFWRA_Pos (4U)
+#define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
+#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
+#define ETH_MACDBGR_MSFRWCS_Pos (1U)
+#define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
+#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
+#define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
+#define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
+#define ETH_MACDBGR_MMRPEA_Pos (0U)
+#define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
+#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS_Pos (9U)
+#define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
+#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS_Pos (6U)
+#define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
+#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
+#define ETH_MACSR_MMMCRS_Pos (5U)
+#define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
+#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
+#define ETH_MACSR_MMCS_Pos (4U)
+#define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
+#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
+#define ETH_MACSR_PMTS_Pos (3U)
+#define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
+#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM_Pos (9U)
+#define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
+#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM_Pos (3U)
+#define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
+#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H_Pos (0U)
+#define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L_Pos (0U)
+#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE_Pos (31U)
+#define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
+#define ETH_MACA1HR_SA_Pos (30U)
+#define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
+#define ETH_MACA1HR_MBC_Pos (24U)
+#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H_Pos (0U)
+#define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L_Pos (0U)
+#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE_Pos (31U)
+#define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
+#define ETH_MACA2HR_SA_Pos (30U)
+#define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
+#define ETH_MACA2HR_MBC_Pos (24U)
+#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H_Pos (0U)
+#define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L_Pos (0U)
+#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE_Pos (31U)
+#define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
+#define ETH_MACA3HR_SA_Pos (30U)
+#define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
+#define ETH_MACA3HR_MBC_Pos (24U)
+#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H_Pos (0U)
+#define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L_Pos (0U)
+#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP_Pos (5U)
+#define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP_Pos (4U)
+#define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
+#define ETH_MMCCR_MCF_Pos (3U)
+#define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR_Pos (2U)
+#define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
+#define ETH_MMCCR_CSR_Pos (1U)
+#define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
+#define ETH_MMCCR_CR_Pos (0U)
+#define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS_Pos (17U)
+#define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES_Pos (6U)
+#define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES_Pos (5U)
+#define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS_Pos (21U)
+#define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS_Pos (15U)
+#define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS_Pos (14U)
+#define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM_Pos (17U)
+#define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM_Pos (6U)
+#define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM_Pos (5U)
+#define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM_Pos (21U)
+#define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
+#define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM_Pos (14U)
+#define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
+#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC_Pos (0U)
+#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC_Pos (0U)
+#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC_Pos (0U)
+#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
+#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT_Pos (16U)
+#define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
+#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME_Pos (15U)
+#define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME_Pos (14U)
+#define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
+#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
+#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
+#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
+#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
+#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
+#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
+#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
+#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
+#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR_Pos (9U)
+#define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
+#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE_Pos (8U)
+#define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
+#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU_Pos (5U)
+#define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
+#define ETH_PTPTSCR_TSITE_Pos (4U)
+#define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU_Pos (3U)
+#define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
+#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI_Pos (2U)
+#define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
+#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU_Pos (1U)
+#define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
+#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE_Pos (0U)
+#define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
+#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI_Pos (0U)
+#define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
+#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS_Pos (0U)
+#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS_Pos (31U)
+#define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS_Pos (0U)
+#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS_Pos (0U)
+#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
+#define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS_Pos (0U)
+#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA_Pos (0U)
+#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH_Pos (0U)
+#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL_Pos (0U)
+#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR_Pos (5U)
+#define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO_Pos (4U)
+#define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB_Pos (25U)
+#define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
+#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
+#define ETH_DMABMR_FPM_Pos (24U)
+#define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
+#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
+#define ETH_DMABMR_USP_Pos (23U)
+#define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
+#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
+#define ETH_DMABMR_RDP_Pos (17U)
+#define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
+#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
+#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB_Pos (16U)
+#define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
+#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
+#define ETH_DMABMR_RTPR_Pos (14U)
+#define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
+#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL_Pos (8U)
+#define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
+#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
+#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE_Pos (7U)
+#define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
+#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL_Pos (2U)
+#define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
+#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
+#define ETH_DMABMR_DA_Pos (1U)
+#define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
+#define ETH_DMABMR_SR_Pos (0U)
+#define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD_Pos (0U)
+#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD_Pos (0U)
+#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL_Pos (0U)
+#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL_Pos (0U)
+#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS_Pos (29U)
+#define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
+#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS_Pos (28U)
+#define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
+#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
+#define ETH_DMASR_MMCS_Pos (27U)
+#define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
+#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
+#define ETH_DMASR_EBS_Pos (23U)
+#define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
+#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+#define ETH_DMASR_EBS_DescAccess_Pos (25U)
+#define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
+#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
+#define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
+#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
+#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
+#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS_Pos (20U)
+#define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
+#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMASR_TPS_Fetching_Pos (20U)
+#define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
+#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
+#define ETH_DMASR_TPS_Waiting_Pos (21U)
+#define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
+#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
+#define ETH_DMASR_TPS_Reading_Pos (20U)
+#define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
+#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
+#define ETH_DMASR_TPS_Suspended_Pos (21U)
+#define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
+#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
+#define ETH_DMASR_TPS_Closing_Pos (20U)
+#define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS_Pos (17U)
+#define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
+#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Fetching_Pos (17U)
+#define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
+#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
+#define ETH_DMASR_RPS_Waiting_Pos (17U)
+#define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
+#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
+#define ETH_DMASR_RPS_Suspended_Pos (19U)
+#define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
+#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
+#define ETH_DMASR_RPS_Closing_Pos (17U)
+#define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
+#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
+#define ETH_DMASR_RPS_Queuing_Pos (17U)
+#define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS_Pos (16U)
+#define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
+#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
+#define ETH_DMASR_AIS_Pos (15U)
+#define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
+#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS_Pos (14U)
+#define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
+#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
+#define ETH_DMASR_FBES_Pos (13U)
+#define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
+#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
+#define ETH_DMASR_ETS_Pos (10U)
+#define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
+#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
+#define ETH_DMASR_RWTS_Pos (9U)
+#define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
+#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS_Pos (8U)
+#define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
+#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
+#define ETH_DMASR_RBUS_Pos (7U)
+#define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
+#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
+#define ETH_DMASR_RS_Pos (6U)
+#define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
+#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
+#define ETH_DMASR_TUS_Pos (5U)
+#define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
+#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
+#define ETH_DMASR_ROS_Pos (4U)
+#define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
+#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
+#define ETH_DMASR_TJTS_Pos (3U)
+#define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
+#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS_Pos (2U)
+#define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
+#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS_Pos (1U)
+#define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
+#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
+#define ETH_DMASR_TS_Pos (0U)
+#define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
+#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD_Pos (26U)
+#define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
+#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF_Pos (25U)
+#define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
+#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
+#define ETH_DMAOMR_DFRF_Pos (24U)
+#define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
+#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF_Pos (21U)
+#define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
+#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
+#define ETH_DMAOMR_FTF_Pos (20U)
+#define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
+#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC_Pos (14U)
+#define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
+#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
+#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST_Pos (13U)
+#define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
+#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF_Pos (7U)
+#define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
+#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
+#define ETH_DMAOMR_FUGF_Pos (6U)
+#define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
+#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC_Pos (3U)
+#define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
+#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
+#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF_Pos (2U)
+#define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
+#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
+#define ETH_DMAOMR_SR_Pos (1U)
+#define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
+#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE_Pos (16U)
+#define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
+#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE_Pos (15U)
+#define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
+#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE_Pos (14U)
+#define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE_Pos (13U)
+#define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
+#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE_Pos (10U)
+#define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE_Pos (9U)
+#define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
+#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE_Pos (8U)
+#define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
+#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE_Pos (7U)
+#define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
+#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE_Pos (6U)
+#define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE_Pos (5U)
+#define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
+#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE_Pos (4U)
+#define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
+#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE_Pos (3U)
+#define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
+#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE_Pos (2U)
+#define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
+#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE_Pos (1U)
+#define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
+#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE_Pos (0U)
+#define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC_Pos (28U)
+#define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
+#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA_Pos (17U)
+#define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
+#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC_Pos (16U)
+#define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
+#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC_Pos (0U)
+#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
+#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP_Pos (0U)
+#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP_Pos (0U)
+#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP_Pos (0U)
+#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP_Pos (0U)
+#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
+#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN_Pos (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL_Pos (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/* Legacy define */
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+ ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10)|| \
+ ((INSTANCE) == TIM11)|| \
+ ((INSTANCE) == TIM12)|| \
+ ((INSTANCE) == TIM13)|| \
+ ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+ ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE 0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
+#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
+
+#define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
+#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
+#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE 50U
+#define RCC_PLLN_MAX_VALUE 432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
+
+#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
+#define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
+
+#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+#define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F469xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ #define STM32F469xx /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.2
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+ #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+ #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/system_stm32f4xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/system_stm32f4xx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/us_ticker_data.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/us_ticker_data.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM2
+#define TIM_MST_IRQ TIM2_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/analogin_device.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/analogin_device.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,196 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ uint32_t function = (uint32_t)NC;
+
+ // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...)
+ // are described in PinNames.h and PeripheralPins.c
+ // Pin value must be between 0xF0 and 0xFF
+ if ((pin < 0xF0) || (pin >= 0x100)) {
+ // Normal channels
+ // Get the peripheral name from the pin and assign it to the object
+ obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
+ // Get the functions (adc channel) from the pin and assign it to the object
+ function = pinmap_function(pin, PinMap_ADC);
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_ADC);
+ } else {
+ // Internal channels
+ obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
+ function = pinmap_function(pin, PinMap_ADC_Internal);
+ // No GPIO configuration for internal channels
+ }
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+ MBED_ASSERT(function != (uint32_t)NC);
+
+ obj->channel = STM_PIN_CHANNEL(function);
+
+ // Save pin number for the read function
+ obj->pin = pin;
+
+ // Configure ADC object structures
+ obj->handle.State = HAL_ADC_STATE_RESET;
+ obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+ obj->handle.Init.Resolution = ADC_RESOLUTION_12B;
+ obj->handle.Init.ScanConvMode = DISABLE;
+ obj->handle.Init.ContinuousConvMode = DISABLE;
+ obj->handle.Init.DiscontinuousConvMode = DISABLE;
+ obj->handle.Init.NbrOfDiscConversion = 0;
+ obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.NbrOfConversion = 1;
+ obj->handle.Init.DMAContinuousRequests = DISABLE;
+ obj->handle.Init.EOCSelection = DISABLE;
+
+#if defined(ADC1)
+ if ((ADCName)obj->handle.Instance == ADC_1) {
+ __HAL_RCC_ADC1_CLK_ENABLE();
+ }
+#endif
+#if defined(ADC2)
+ if ((ADCName)obj->handle.Instance == ADC_2) {
+ __HAL_RCC_ADC2_CLK_ENABLE();
+ }
+#endif
+#if defined(ADC3)
+ if ((ADCName)obj->handle.Instance == ADC_3) {
+ __HAL_RCC_ADC3_CLK_ENABLE();
+ }
+#endif
+
+ if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
+ error("Cannot initialize ADC");
+ }
+}
+
+uint16_t adc_read(analogin_t *obj)
+{
+ ADC_ChannelConfTypeDef sConfig = {0};
+
+ // Configure ADC channel
+ sConfig.Rank = 1;
+ sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES;
+ sConfig.Offset = 0;
+
+ switch (obj->channel) {
+ case 0:
+ sConfig.Channel = ADC_CHANNEL_0;
+ break;
+ case 1:
+ sConfig.Channel = ADC_CHANNEL_1;
+ break;
+ case 2:
+ sConfig.Channel = ADC_CHANNEL_2;
+ break;
+ case 3:
+ sConfig.Channel = ADC_CHANNEL_3;
+ break;
+ case 4:
+ sConfig.Channel = ADC_CHANNEL_4;
+ break;
+ case 5:
+ sConfig.Channel = ADC_CHANNEL_5;
+ break;
+ case 6:
+ sConfig.Channel = ADC_CHANNEL_6;
+ break;
+ case 7:
+ sConfig.Channel = ADC_CHANNEL_7;
+ break;
+ case 8:
+ sConfig.Channel = ADC_CHANNEL_8;
+ break;
+ case 9:
+ sConfig.Channel = ADC_CHANNEL_9;
+ break;
+ case 10:
+ sConfig.Channel = ADC_CHANNEL_10;
+ break;
+ case 11:
+ sConfig.Channel = ADC_CHANNEL_11;
+ break;
+ case 12:
+ sConfig.Channel = ADC_CHANNEL_12;
+ break;
+ case 13:
+ sConfig.Channel = ADC_CHANNEL_13;
+ break;
+ case 14:
+ sConfig.Channel = ADC_CHANNEL_14;
+ break;
+ case 15:
+ sConfig.Channel = ADC_CHANNEL_15;
+ break;
+ case 16:
+ sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+ sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; // Minimum ADC sampling time when reading the temperature is 10us
+ break;
+ case 17:
+ sConfig.Channel = ADC_CHANNEL_VREFINT;
+ sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; // Minimum ADC sampling time when reading the internal reference voltage is 10us
+ break;
+ case 18:
+ sConfig.Channel = ADC_CHANNEL_VBAT;
+ sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; // Minimum ADC sampling time when reading the VBAT is 5us
+ break;
+ default:
+ return 0;
+ }
+
+ // Measuring VBAT sets the ADC_CCR_VBATE bit in ADC->CCR, and there is not
+ // possibility with the ST HAL driver to clear it. If it isn't cleared,
+ // VBAT remains connected to the ADC channel in preference to temperature,
+ // so VBAT readings are returned in place of temperature.
+ ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
+
+ HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+
+ HAL_ADC_Start(&obj->handle); // Start conversion
+
+ // Wait end of conversion and get value
+ if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+ return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+ } else {
+ return 0;
+ }
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,95 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "analogout_api.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "stm32f4xx_hal.h"
+#include "PeripheralPins.h"
+
+void analogout_init(dac_t *obj, PinName pin)
+{
+ DAC_ChannelConfTypeDef sConfig = {0};
+
+ // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
+ obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+ // Get the functions (dac channel) from the pin and assign it to the object
+ uint32_t function = pinmap_function(pin, PinMap_DAC);
+ MBED_ASSERT(function != (uint32_t)NC);
+
+ // Save the channel for the write and read functions
+ switch (STM_PIN_CHANNEL(function)) {
+ case 1:
+ obj->channel = DAC_CHANNEL_1;
+ break;
+#if defined(DAC_CHANNEL_2)
+ case 2:
+ obj->channel = DAC_CHANNEL_2;
+ break;
+#endif
+ default:
+ error("Unknown DAC channel");
+ break;
+ }
+
+ if (obj->dac == (DACName)NC) {
+ error("DAC pin mapping failed");
+ }
+
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_DAC);
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+
+ __HAL_RCC_DAC_CLK_ENABLE();
+
+ obj->handle.Instance = DAC;
+ obj->handle.State = HAL_DAC_STATE_RESET;
+
+ if (HAL_DAC_Init(&obj->handle) != HAL_OK) {
+ error("HAL_DAC_Init failed");
+ }
+
+ sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+
+ if (HAL_DAC_ConfigChannel(&obj->handle, &sConfig, obj->channel) != HAL_OK) {
+ error("HAL_DAC_ConfigChannel failed");
+ }
+
+ analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj)
+{
+}
+
+#endif // DEVICE_ANALOGOUT
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/can_device.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/can_device.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_DEVICE_H
+#define MBED_CAN_DEVICE_H
+
+#include "cmsis.h"
+#include "stm32f4xx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef DEVICE_CAN
+
+#if defined(CAN3_BASE)
+
+#define CAN_NUM 3 // Number of CAN peripherals present in the STM32 serie
+
+#define CAN3_IRQ_RX_IRQN CAN3_RX0_IRQn
+#define CAN3_IRQ_RX_VECT CAN3_RX0_IRQHandler
+#define CAN3_IRQ_TX_IRQN CAN3_TX_IRQn
+#define CAN3_IRQ_TX_VECT CAN3_TX_IRQHandler
+#define CAN3_IRQ_ERROR_IRQN CAN3_SCE_IRQn
+#define CAN3_IRQ_ERROR_VECT CAN3_SCE_IRQHandler
+#define CAN3_IRQ_PASSIVE_IRQN CAN3_SCE_IRQn
+#define CAN3_IRQ_PASSIVE_VECT CAN3_SCE_IRQHandler
+#define CAN3_IRQ_BUS_IRQN CAN3_SCE_IRQn
+#define CAN3_IRQ_BUS_VECT CAN3_SCE_IRQHandler
+
+#else
+
+#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie
+
+#endif
+
+#define CAN1_IRQ_RX_IRQN CAN1_RX0_IRQn
+#define CAN1_IRQ_RX_VECT CAN1_RX0_IRQHandler
+#define CAN1_IRQ_TX_IRQN CAN1_TX_IRQn
+#define CAN1_IRQ_TX_VECT CAN1_TX_IRQHandler
+#define CAN1_IRQ_ERROR_IRQN CAN1_SCE_IRQn
+#define CAN1_IRQ_ERROR_VECT CAN1_SCE_IRQHandler
+#define CAN1_IRQ_PASSIVE_IRQN CAN1_SCE_IRQn
+#define CAN1_IRQ_PASSIVE_VECT CAN1_SCE_IRQHandler
+#define CAN1_IRQ_BUS_IRQN CAN1_SCE_IRQn
+#define CAN1_IRQ_BUS_VECT CAN1_SCE_IRQHandler
+
+#define CAN2_IRQ_RX_IRQN CAN2_RX0_IRQn
+#define CAN2_IRQ_RX_VECT CAN2_RX0_IRQHandler
+#define CAN2_IRQ_TX_IRQN CAN2_TX_IRQn
+#define CAN2_IRQ_TX_VECT CAN2_TX_IRQHandler
+#define CAN2_IRQ_ERROR_IRQN CAN2_SCE_IRQn
+#define CAN2_IRQ_ERROR_VECT CAN2_SCE_IRQHandler
+#define CAN2_IRQ_PASSIVE_IRQN CAN2_SCE_IRQn
+#define CAN2_IRQ_PASSIVE_VECT CAN2_SCE_IRQHandler
+#define CAN2_IRQ_BUS_IRQN CAN2_SCE_IRQn
+#define CAN2_IRQ_BUS_VECT CAN2_SCE_IRQHandler
+
+#endif // DEVICE_CAN
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/common_objects.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/common_objects.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,149 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_COMMON_OBJECTS_H
+#define MBED_COMMON_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t prescaler;
+ uint32_t period;
+ uint32_t pulse;
+ uint8_t channel;
+ uint8_t inverted;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index;
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+ PinName pin_tx;
+ PinName pin_rx;
+#if DEVICE_SERIAL_ASYNCH
+ uint32_t events;
+#endif
+#if DEVICE_SERIAL_FC
+ uint32_t hw_flow_ctl;
+ PinName pin_rts;
+ PinName pin_cts;
+#endif
+};
+
+struct spi_s {
+ SPI_HandleTypeDef handle;
+ IRQn_Type spiIRQ;
+ SPIName spi;
+ PinName pin_miso;
+ PinName pin_mosi;
+ PinName pin_sclk;
+ PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+ uint32_t event;
+ uint8_t transfer_type;
+#endif
+};
+
+struct i2c_s {
+ /* The 1st 2 members I2CName i2c
+ * and I2C_HandleTypeDef handle should
+ * be kept as the first members of this struct
+ * to have get_i2c_obj() function work as expected
+ */
+ I2CName i2c;
+ I2C_HandleTypeDef handle;
+ uint8_t index;
+ int hz;
+ PinName sda;
+ PinName scl;
+ IRQn_Type event_i2cIRQ;
+ IRQn_Type error_i2cIRQ;
+ uint8_t XferOperation;
+ volatile uint8_t event;
+#if DEVICE_I2CSLAVE
+ uint8_t slave;
+ volatile uint8_t pending_slave_tx_master_rx;
+ volatile uint8_t pending_slave_rx_maxter_tx;
+#endif
+#if DEVICE_I2C_ASYNCH
+ uint32_t address;
+ uint8_t stop;
+ uint8_t available_events;
+#endif
+};
+
+#if DEVICE_FLASH
+struct flash_s {
+ uint32_t dummy;
+};
+#endif
+
+struct analogin_s {
+ ADC_HandleTypeDef handle;
+ PinName pin;
+ uint8_t channel;
+};
+
+#define GPIO_IP_WITHOUT_BRR
+#include "gpio_object.h"
+
+#if DEVICE_ANALOGOUT
+struct dac_s {
+ DACName dac;
+ uint32_t channel;
+ DAC_HandleTypeDef handle;
+};
+#endif
+
+#if DEVICE_CAN
+struct can_s {
+ CAN_HandleTypeDef CanHandle;
+ int index;
+ int hz;
+};
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,42 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +//======================================= +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" +/* WORKAROUND waiting for mbed-os issue 4408 to be addressed */ +#include "stm32f4xx_ll_usart.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,3309 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_HAL_LEGACY
+#define __STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
+/* to the second dedicated IO (only for COMP2). */
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE 0x00000000U
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#else
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
+
+#if defined(STM32L1)
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+ #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+ #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+ #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+ #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+ #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+ #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+
+ #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+ #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+ #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+ #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+ #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+ #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+ #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+ #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+
+#endif /* STM32H7 */
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+#if defined(STM32F7)
+ #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define __DIV_LPUART UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR 0x00000100U
+#define ETH_MMCRIR 0x00000104U
+#define ETH_MMCTIR 0x00000108U
+#define ETH_MMCRIMR 0x0000010CU
+#define ETH_MMCTIMR 0x00000110U
+#define ETH_MMCTGFSCCR 0x0000014CU
+#define ETH_MMCTGFMSCCR 0x00000150U
+#define ETH_MMCTGFCR 0x00000168U
+#define ETH_MMCRFCECR 0x00000194U
+#define ETH_MMCRFAECR 0x00000198U
+#define ETH_MMCRGUFCR 0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
+
+/**
+ * @}
+ */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
+/**
+ * @}
+ */
+#endif /* STM32L4 || STM32F7*/
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
+#define CR_PMODE_BB CR_VOS_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro */
+/* is COMP_FLAG_LOCK. */
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
+/* argument. */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+ * @}
+ */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE RCC_IT_LSECSS
+#define RCC_IT_CSSHSE RCC_IT_CSS
+
+#define RCC_PLLMUL_3 RCC_PLL_MUL3
+#define RCC_PLLMUL_4 RCC_PLL_MUL4
+#define RCC_PLLMUL_6 RCC_PLL_MUL6
+#define RCC_PLLMUL_8 RCC_PLL_MUL8
+#define RCC_PLLMUL_12 RCC_PLL_MUL12
+#define RCC_PLLMUL_16 RCC_PLL_MUL16
+#define RCC_PLLMUL_24 RCC_PLL_MUL24
+#define RCC_PLLMUL_32 RCC_PLL_MUL32
+#define RCC_PLLMUL_48 RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2 RCC_PLL_DIV2
+#define RCC_PLLDIV_3 RCC_PLL_DIV3
+#define RCC_PLLDIV_4 RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#elif defined(STM32WB) || defined(STM32G0)
+#else
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32G0)
+#else
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4) || defined(STM32F2)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,607 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal.c
+ * @author MCD Application Team
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs' categories:
+ (+) Common HAL APIs
+ (+) Services HAL APIs
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Constants
+ * @{
+ */
+/**
+ * @brief STM32F4xx HAL Driver version number V1.7.3
+ */
+#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
+ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
+ |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
+ |(__STM32F4xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK 0x00000FFFU
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
+/* --- MEMRMP Register ---*/
+/* Alias word address of UFB_MODE bit */
+#define MEMRMP_OFFSET SYSCFG_OFFSET
+#define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos
+#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U))
+
+/* --- CMPCR Register ---*/
+/* Alias word address of CMP_PD bit */
+#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U)
+#define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos
+#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
+
+/* --- MCHDLYCR Register ---*/
+/* Alias word address of BSCKSEL bit */
+#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U)
+#define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos
+#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U))
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Private_Variables
+ * @{
+ */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface the NVIC allocation and initial clock
+ configuration. It initializes the systick also when timeout is needed
+ and the backup domain when enabled.
+ (+) De-Initializes common part of the HAL.
+ (+) Configure the time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) SysTick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __weak
+ to make override possible in case of other implementations in user file.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is used to initialize the HAL Library; it must be the first
+ * instruction to be executed in the main program (before to call any other
+ * HAL function), it performs the following:
+ * Configure the Flash prefetch, instruction and Data caches.
+ * Configures the SysTick to generate an interrupt each 1 millisecond,
+ * which is clocked by the HSI (at this stage, the clock is not yet
+ * configured and thus the system is running from the internal HSI at 16 MHz).
+ * Set NVIC Group Priority to 4.
+ * Calls the HAL_MspInit() callback function defined in user file
+ * "stm32f4xx_hal_msp.c" to do the global low level hardware initialization
+ *
+ * @note SysTick is used as time base for the HAL_Delay() function, the application
+ * need to ensure that the SysTick time base is always set to 1 millisecond
+ * to have correct HAL operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ /* Configure Flash prefetch, Instruction cache, Data cache */
+#if (INSTRUCTION_CACHE_ENABLE != 0U)
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (DATA_CACHE_ENABLE != 0U)
+ __HAL_FLASH_DATA_CACHE_ENABLE();
+#endif /* DATA_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+/* MBED : moved to HAL_InitPre() */
+#if !defined (TARGET_STM32F429xI)
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+#endif
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the systick.
+ * This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
+
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
+
+ __HAL_RCC_AHB1_FORCE_RESET();
+ __HAL_RCC_AHB1_RELEASE_RESET();
+
+ __HAL_RCC_AHB2_FORCE_RESET();
+ __HAL_RCC_AHB2_RELEASE_RESET();
+
+ __HAL_RCC_AHB3_FORCE_RESET();
+ __HAL_RCC_AHB3_RELEASE_RESET();
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+ (+) Enable/Disable Debug module during SLEEP mode
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick += uwTickFreq;
+}
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq.
+ * @retval Status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq)
+ {
+ uwTickFreq = Freq;
+
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return tick frequency.
+ * @retval tick period in Hz
+ */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(uint32_t Delay)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait += (uint32_t)(uwTickFreq);
+ }
+
+ while((HAL_GetTick() - tickstart) < wait)
+ {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+{
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief Returns the HAL revision
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32F4xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return((DBGMCU->IDCODE) >> 16U);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Enables the I/O Compensation Cell.
+ * @note The I/O compensation cell can be used only when the device supply
+ * voltage ranges from 2.4 to 3.6 V.
+ * @retval None
+ */
+void HAL_EnableCompensationCell(void)
+{
+ *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Power-down the I/O Compensation Cell.
+ * @note The I/O compensation cell can be used only when the device supply
+ * voltage ranges from 2.4 to 3.6 V.
+ * @retval None
+ */
+void HAL_DisableCompensationCell(void)
+{
+ *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Return the unique device identifier (UID based on 96 bits)
+ * @param UID pointer to 3 words array.
+ * @retval Device identifier
+ */
+void HAL_GetUID(uint32_t *UID)
+{
+ UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
+ UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+ UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Enables the Internal FLASH Bank Swapping.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
+ * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
+ * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
+ *
+ * @retval None
+ */
+void HAL_EnableMemorySwappingBank(void)
+{
+ *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the Internal FLASH Bank Swapping.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
+ * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
+ * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
+ *
+ * @retval None
+ */
+void HAL_DisableMemorySwappingBank(void)
+{
+ *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,300 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_H
+#define __STM32F4xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_conf.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
+/** @brief Freeze/Unfreeze Peripherals in Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+/** @brief Main Flash memory mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
+
+/** @brief System Flash memory mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
+ }while(0);
+
+/** @brief Embedded SRAM mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+
+/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
+ }while(0);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
+ * @{
+ */
+/** @brief SYSCFG Break Lockup lock
+ * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+
+/** @defgroup PVD_Lock_Enable PVD Lock
+ * @{
+ */
+/** @brief SYSCFG Break PVD lock
+ * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and Configuration functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+void HAL_GetUID(uint32_t *UID);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+void HAL_EnableMemorySwappingBank(void);
+void HAL_DisableMemorySwappingBank(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1701 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_adc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + State and errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### ADC Peripheral features #####
+ ==============================================================================
+ [..]
+ (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+ (#) Interrupt generation at the end of conversion, end of injected conversion,
+ and in case of analog watchdog or overrun events
+ (#) Single and continuous conversion modes.
+ (#) Scan mode for automatic conversion of channel 0 to channel x.
+ (#) Data alignment with in-built data coherency.
+ (#) Channel-wise programmable sampling time.
+ (#) External trigger option with configurable polarity for both regular and
+ injected conversion.
+ (#) Dual/Triple mode (on devices with 2 ADCs or more).
+ (#) Configurable DMA data storage in Dual/Triple ADC mode.
+ (#) Configurable delay between conversions in Dual/Triple interleaved mode.
+ (#) ADC conversion type (refer to the datasheets).
+ (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
+ slower speed.
+ (#) ADC input range: VREF(minus) = VIN = VREF(plus).
+ (#) DMA request generation during regular channel conversion.
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
+ (##) ADC pins configuration
+ (+++) Enable the clock for the ADC GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE()
+ (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
+ (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
+ (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
+ (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
+ (+++) Configure and enable two DMA streams stream for managing data
+ transfer from peripheral to memory (output stream)
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the two DMA Streams. The output stream should have higher
+ priority than the input stream.
+
+ *** Configuration of ADC, groups regular/injected, channels parameters ***
+ ==============================================================================
+ [..]
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the injected group parameters (conversion trigger,
+ sequencer, ..., of injected group)
+ and the channels for injected group parameters (channel number,
+ channel rank into sequencer, ..., into injected group)
+ using function HAL_ADCEx_InjectedConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
+
+ (#) Optionally, for devices with several ADC instances: configure the
+ multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
+
+ *** Execution of ADC conversions ***
+ ==============================================================================
+ [..]
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the ADC peripheral using HAL_ADC_Start()
+ (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
+ user can specify the value of timeout according to his end application
+ (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
+ (+) Stop the ADC peripheral using HAL_ADC_Stop()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the ADC peripheral using HAL_ADC_Start_IT()
+ (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
+ (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
+ (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
+ (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
+ (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
+
+ *** ADC HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in ADC HAL driver.
+
+ (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
+ (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
+ (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
+ (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
+ (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
+ (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
+ (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
+ (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
+
+ [..]
+ (@) You can refer to the ADC HAL driver header file for more useful macros
+
+ *** Deinitialization of ADC ***
+ ==============================================================================
+ [..]
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
+ (++) ADC clock disable using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA using function HAL_DMA_DeInit().
+ (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+/* Private function prototypes -----------------------------------------------*/
+static void ADC_Init(ADC_HandleTypeDef* hadc);
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct and initializes the ADC MSP.
+ *
+ * @note This function is used to configure the global features of the ADC (
+ * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
+ * the rest of the configuration parameters are specific to the regular
+ * channels group (scan mode activation, continuous mode activation,
+ * External trigger source and edge, DMA continuous request after the
+ * last transfer and End of conversion selection).
+ *
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ }
+
+ if(hadc->State == HAL_ADC_STATE_RESET)
+ {
+ /* Initialize ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+ }
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Set ADC parameters */
+ ADC_Init(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Initializes the ADC MSP.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the ADC MSP.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular channel.
+ (+) Stop conversion of regular channel.
+ (+) Start conversion of regular channel and enable interrupt.
+ (+) Stop conversion of regular channel and disable interrupt.
+ (+) Start conversion of regular channel and enable DMA transfer.
+ (+) Stop conversion of regular channel and disable DMA transfer.
+ (+) Handle ADC interrupt request.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables ADC and starts conversion of the regular channels.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+ __IO uint32_t counter = 0U;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ /* Check if ADC peripheral is disabled in order to enable it and wait during
+ Tstab time the ADC's stabilization */
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ {
+ /* Enable the Peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(counter != 0U)
+ {
+ counter--;
+ }
+ }
+
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
+ {
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ else
+ {
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables ADC and stop conversion of regular channels.
+ *
+ * @note Caution: This function will stop also injected channels.
+ *
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ *
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Poll for regular conversion complete
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function.
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and polling for end of each conversion. */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
+ HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check End of conversion flag */
+ while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F4, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+
+/**
+ * @brief Poll for conversion event
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param EventType the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
+ * @arg ADC_OVR_EVENT: ADC Overrun event.
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Analog watchdog (level out of window) event */
+ if(EventType == ADC_AWD_EVENT)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ }
+ /* Overrun event */
+ else
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Enables the interrupt and starts ADC conversion of regular channels.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+ __IO uint32_t counter = 0U;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ /* Check if ADC peripheral is disabled in order to enable it and wait during
+ Tstab time the ADC's stabilization */
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ {
+ /* Enable the Peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(counter != 0U)
+ {
+ counter--;
+ }
+ }
+
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+
+ /* Enable end of conversion interrupt for regular group */
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
+ {
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ else
+ {
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the interrupt and stop ADC conversion of regular channels.
+ *
+ * @note Caution: This function will stop also injected channels.
+ *
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles ADC interrupt request
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tmp1 = 0U, tmp2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+ assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
+ /* Check End of conversion flag for regular channels */
+ if(tmp1 && tmp2)
+ {
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F4, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+ }
+
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
+ /* Check End of conversion flag for injected channels */
+ if(tmp1 && tmp2)
+ {
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger, scan sequence on going or by automatic injected */
+ /* conversion from group regular (same conditions as group regular */
+ /* interruption disabling above). */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
+ {
+ /* Disable ADC end of single conversion interrupt on group injected */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
+ }
+
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
+ /* Check Analog watchdog flag */
+ if(tmp1 && tmp2)
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+
+ /* Clear the ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ }
+ }
+
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
+ /* Check Overrun flag */
+ if(tmp1 && tmp2)
+ {
+ /* Note: On STM32F4, ADC overrun can be set through other parameters */
+ /* refer to description of parameter "EOCSelection" for more */
+ /* details. */
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+
+ /* Clear the Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+}
+
+/**
+ * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ __IO uint32_t counter = 0U;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ /* Check if ADC peripheral is disabled in order to enable it and wait during
+ Tstab time the ADC's stabilization */
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ {
+ /* Enable the Peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(counter != 0U)
+ {
+ counter--;
+ }
+ }
+
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Enable ADC DMA mode */
+ hadc->Instance->CR2 |= ADC_CR2_DMA;
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
+ {
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ else
+ {
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable the selected ADC DMA mode */
+ hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Gets the converted value from data register of regular channel.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval Converted value
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+ /* Return the selected ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief Regular conversion complete callback in non blocking mode
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADC_ConvCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Regular conversion half DMA transfer callback in non blocking mode
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Analog watchdog callback in non blocking mode
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error ADC callback.
+ * @note In case of error due to overrun when using ADC with DMA transfer
+ * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+ * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+ * - If needed, restart a new ADC conversion using function
+ * "HAL_ADC_Start_DMA()"
+ * (this function is also clearing overrun flag)
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADC_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure regular channels.
+ (+) Configure injected channels.
+ (+) Configure multimode.
+ (+) Configure the analog watch dog.
+
+@endverbatim
+ * @{
+ */
+
+ /**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param sConfig ADC configuration structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ __IO uint32_t counter = 0U;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+ if (sConfig->Channel > ADC_CHANNEL_9)
+ {
+ /* Clear the old sample time */
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
+
+ /* Set the new sample time */
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Clear the old sample time */
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
+
+ /* Set the new sample time */
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
+ }
+
+ /* For Rank 1 to 6 */
+ if (sConfig->Rank < 7U)
+ {
+ /* Clear the old SQx bits for the selected rank */
+ hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
+
+ /* Set the SQx bits for the selected rank */
+ hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
+ }
+ /* For Rank 7 to 12 */
+ else if (sConfig->Rank < 13U)
+ {
+ /* Clear the old SQx bits for the selected rank */
+ hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
+
+ /* Set the SQx bits for the selected rank */
+ hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Clear the old SQx bits for the selected rank */
+ hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
+
+ /* Set the SQx bits for the selected rank */
+ hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
+ }
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* if ADC1 Channel_18 is selected enable VBAT Channel */
+ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
+ {
+ /* Enable the VBAT channel*/
+ tmpADC_Common->CCR |= ADC_CCR_VBATE;
+ }
+
+ /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
+ if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
+ {
+ /* Enable the TSVREFE channel*/
+ tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
+
+ if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(counter != 0U)
+ {
+ counter--;
+ }
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the analog watchdog.
+ * @note Analog watchdog thresholds can be modified while ADC conversion
+ * is on going.
+ * In this case, some constraints must be taken into account:
+ * The programmed threshold values are effective from the next
+ * ADC EOC (end of unitary conversion).
+ * Considering that registers write delay may happen due to
+ * bus activity, this might cause an uncertainty on the
+ * effective timing of the new programmed threshold values.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure
+ * that contains the configuration information of ADC analog watchdog.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+#ifdef USE_FULL_ASSERT
+ uint32_t tmp = 0U;
+#endif /* USE_FULL_ASSERT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+#ifdef USE_FULL_ASSERT
+ tmp = ADC_GET_RESOLUTION(hadc);
+ assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
+#endif /* USE_FULL_ASSERT */
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ /* Enable the ADC Analog watchdog interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+ }
+ else
+ {
+ /* Disable the ADC Analog watchdog interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+ }
+
+ /* Clear AWDEN, JAWDEN and AWDSGL bits */
+ hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
+
+ /* Set the analog watchdog enable mode */
+ hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
+
+ /* Set the high threshold */
+ hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
+
+ /* Set the low threshold */
+ hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
+
+ /* Clear the Analog watchdog channel select bits */
+ hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
+
+ /* Set the Analog watchdog channel */
+ hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
+ * @brief ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the ADC state
+ (+) Check the ADC Error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the ADC state
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval HAL state
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+ /* Return ADC state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval ADC Error Code
+ */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct without initializing the ADC MSP.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval None
+ */
+static void ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Set ADC parameters */
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Set the ADC clock prescaler */
+ tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
+ tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
+
+ /* Set ADC scan mode */
+ hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
+ hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
+
+ /* Set ADC resolution */
+ hadc->Instance->CR1 &= ~(ADC_CR1_RES);
+ hadc->Instance->CR1 |= hadc->Init.Resolution;
+
+ /* Set ADC data alignment */
+ hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
+ hadc->Instance->CR2 |= hadc->Init.DataAlign;
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ /* Select external trigger to start conversion */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
+
+ /* Select external trigger polarity */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+ }
+ else
+ {
+ /* Reset the external trigger */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ }
+
+ /* Enable or disable ADC continuous conversion mode */
+ hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
+ hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
+
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
+
+ /* Enable the selected ADC regular discontinuous mode */
+ hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
+
+ /* Set the number of channels to be converted in discontinuous mode */
+ hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
+ hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
+ }
+
+ /* Set ADC number of conversion */
+ hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
+ hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
+
+ /* Enable or disable ADC DMA continuous request */
+ hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
+ hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
+
+ /* Enable or disable ADC end of conversion selection */
+ hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
+ hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+ {
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F4, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+ }
+ else
+ {
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hadc->State= HAL_ADC_STATE_ERROR_DMA;
+ /* Set ADC error code to DMA error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+ HAL_ADC_ErrorCallback(hadc);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,861 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_adc.h
+ * @author MCD Application Team
+ * @brief Header file containing functions prototypes of ADC HAL library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_H
+#define __STM32F4xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32f4xx_ll_adc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief Structure definition of ADC and regular group initialization
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
+ * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
+ * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
+ * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
+ all the ADCs.
+ This parameter can be a value of @ref ADC_ClockPrescaler */
+ uint32_t Resolution; /*!< Configures the ADC resolution.
+ This parameter can be a value of @ref ADC_Resolution */
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+ or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
+ This parameter can be a value of @ref ADC_Data_align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+ Scan direction is upward: from rank1 to rank 'n'.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+ This parameter can be a value of @ref ADC_EOCSelection.
+ Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
+ Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
+ or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
+ Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
+ If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+ To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge by default.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+ uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+ or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
+ This parameter can be set to ENABLE or DISABLE. */
+}ADC_InitTypeDef;
+
+
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADC_channels */
+ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+ uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
+}ADC_ChannelConfTypeDef;
+
+/**
+ * @brief ADC Configuration multi-mode structure definition
+ */
+typedef struct
+{
+ uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
+ This parameter can be a value of @ref ADC_analog_watchdog_selection */
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a 12-bit value. */
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a 12-bit value. */
+ uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
+ This parameter has an effect only if watchdog mode is configured on single channel
+ This parameter can be a value of @ref ADC_channels */
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
+ is interrupt mode or in polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
+}ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
+
+
+/**
+ * @brief ADC handle Structure definition
+ */
+typedef struct
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+
+ ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+ __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+ __IO uint32_t State; /*!< ADC communication state */
+
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+}ADC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
+ enable/disable, erroneous state */
+#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
+ * @{
+ */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
+#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
+#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
+#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
+#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
+#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
+#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
+#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
+#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Resolution ADC Resolution
+ * @{
+ */
+#define ADC_RESOLUTION_12B 0x00000000U
+#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
+#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
+#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
+ * @{
+ */
+/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
+/* compatibility with other STM32 devices. */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
+#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
+#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
+#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Data_align ADC Data Align
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT 0x00000000U
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels ADC Common Channels
+ * @{
+ */
+#define ADC_CHANNEL_0 0x00000000U
+#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
+#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
+#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
+#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
+
+#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
+#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times ADC Sampling Times
+ * @{
+ */
+#define ADC_SAMPLETIME_3CYCLES 0x00000000U
+#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
+#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
+#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
+#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
+#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
+/**
+ * @}
+ */
+
+ /** @defgroup ADC_EOCSelection ADC EOC Selection
+ * @{
+ */
+#define ADC_EOC_SEQ_CONV 0x00000000U
+#define ADC_EOC_SINGLE_CONV 0x00000001U
+#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type ADC Event Type
+ * @{
+ */
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
+#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
+ * @{
+ */
+#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
+#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
+#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
+#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC Flags Definition
+ * @{
+ */
+#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
+#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
+#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
+#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
+#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
+#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels_type ADC Channels Type
+ * @{
+ */
+#define ADC_ALL_CHANNELS 0x00000001U
+#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */
+#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @brief Reset ADC handle state
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+ * @brief Enable the ADC peripheral.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
+
+/**
+ * @brief Disable the ADC peripheral.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
+
+/**
+ * @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__ specifies the ADC Handle.
+ * @param __INTERRUPT__ ADC Interrupt.
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__ specifies the ADC Handle.
+ * @param __INTERRUPT__ ADC interrupt.
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
+
+/** @brief Check if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the ADC Handle.
+ * @param __INTERRUPT__ specifies the ADC interrupt source to check.
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Clear the ADC's pending flags.
+ * @param __HANDLE__ specifies the ADC Handle.
+ * @param __FLAG__ ADC flag.
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
+
+/**
+ * @brief Get the selected ADC's flag status.
+ * @param __HANDLE__ specifies the ADC Handle.
+ * @param __FLAG__ ADC flag.
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extension module */
+#include "stm32f4xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions ***************************************************/
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+/* Delay for ADC stabilization time. */
+/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
+/* Unit: us */
+#define ADC_STAB_DELAY_US 3U
+/* Delay for temperature sensor stabilization time. */
+/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_TEMPSENSOR_DELAY_US 10U
+/**
+ * @}
+ */
+
+/* Private macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in
+ code of final user */
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__ ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
+ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B))
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
+ ((REGTRIG) == ADC_SOFTWARE_START))
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT))
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_480CYCLES))
+#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
+ ((EOCSelection) == ADC_EOC_SEQ_CONV) || \
+ ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+ ((EVENT) == ADC_OVR_EVENT))
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
+#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
+ ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
+ ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U)))
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
+ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
+ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \
+ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU)))
+
+/**
+ * @brief Set ADC Regular channel sequence length.
+ * @param _NbrOfConversion_ Regular channel sequence length.
+ * @retval None
+ */
+#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.
+ * @param _SAMPLETIME_ Sample time parameter.
+ * @param _CHANNELNB_ Channel number.
+ * @retval None
+ */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.
+ * @param _SAMPLETIME_ Sample time parameter.
+ * @param _CHANNELNB_ Channel number.
+ * @retval None
+ */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 1 and 6.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 7 and 12.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 13 and 16.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @retval None
+ */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_ Continuous mode.
+ * @retval None
+ */
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
+
+/**
+ * @brief Configures the number of discontinuous conversions for the regular group channels.
+ * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos)
+
+/**
+ * @brief Enable ADC scan mode.
+ * @param _SCANCONV_MODE_ Scan conversion mode.
+ * @retval None
+ */
+#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
+
+/**
+ * @brief Enable the ADC end of conversion selection.
+ * @param _EOCSelection_MODE_ End of conversion selection mode.
+ * @retval None
+ */
+#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param _DMAContReq_MODE_ DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
+
+/**
+ * @brief Return resolution bits in CR1 register.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1114 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the ADC extension peripheral:
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
+ (##) ADC pins configuration
+ (+++) Enable the clock for the ADC GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE()
+ (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
+ (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
+ (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
+ (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
+ (+++) Configure and enable two DMA streams stream for managing data
+ transfer from peripheral to memory (output stream)
+ (+++) Associate the initialized DMA handle to the ADC DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the two DMA Streams. The output stream should have higher
+ priority than the input stream.
+ (#) Configure the ADC Prescaler, conversion resolution and data alignment
+ using the HAL_ADC_Init() function.
+
+ (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
+ and HAL_ADC_ConfigChannel() functions.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
+ (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
+ user can specify the value of timeout according to his end application
+ (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
+ (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
+ (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
+ (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
+ (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
+ (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
+
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
+ (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
+ (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
+ (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
+
+ *** Multi mode ADCs Regular channels configuration ***
+ ======================================================
+ [..]
+ (+) Select the Multi mode ADC regular channels features (dual or triple mode)
+ and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
+ (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
+ (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx
+ * @brief ADC Extended driver modules
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup ADCEx_Private_Functions
+ * @{
+ */
+/* Private function prototypes -----------------------------------------------*/
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of injected channel.
+ (+) Stop conversion of injected channel.
+ (+) Start multimode and enable DMA transfer.
+ (+) Stop multimode and disable DMA transfer.
+ (+) Get result of injected channel conversion.
+ (+) Get result of multimode conversion.
+ (+) Configure injected channels.
+ (+) Configure multimode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables the selected ADC software start conversion of the injected channels.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+{
+ __IO uint32_t counter = 0U;
+ uint32_t tmp1 = 0U, tmp2 = 0U;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+
+ /* Check if ADC peripheral is disabled in order to enable it and wait during
+ Tstab time the ADC's stabilization */
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ {
+ /* Enable the Peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(counter != 0U)
+ {
+ counter--;
+ }
+ }
+
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
+ {
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if(tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
+ }
+ else
+ {
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if((hadc->Instance == ADC1) && tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the interrupt and starts ADC conversion of injected channels.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ *
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{
+ __IO uint32_t counter = 0U;
+ uint32_t tmp1 = 0U, tmp2 = 0U;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+
+ /* Check if ADC peripheral is disabled in order to enable it and wait during
+ Tstab time the ADC's stabilization */
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ {
+ /* Enable the Peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(counter != 0U)
+ {
+ counter--;
+ }
+ }
+
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Enable end of conversion interrupt for injected channels */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
+ {
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if(tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
+ }
+ else
+ {
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if((hadc->Instance == ADC1) && tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Poll for injected conversion complete
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check End of conversion flag */
+ while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hadc->State= HAL_ADC_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F4, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @param hadc ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Gets the converted value from data register of injected channel.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param InjectedRank the ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
+ * @retval None
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+{
+ __IO uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Clear injected group conversion flag to have similar behaviour as */
+ /* regular group: reading data register also clears end of conversion flag. */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Return the selected ADC converted value */
+ switch(InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ {
+ tmp = hadc->Instance->JDR4;
+ }
+ break;
+ case ADC_INJECTED_RANK_3:
+ {
+ tmp = hadc->Instance->JDR3;
+ }
+ break;
+ case ADC_INJECTED_RANK_2:
+ {
+ tmp = hadc->Instance->JDR2;
+ }
+ break;
+ case ADC_INJECTED_RANK_1:
+ {
+ tmp = hadc->Instance->JDR1;
+ }
+ break;
+ default:
+ break;
+ }
+ return tmp;
+}
+
+/**
+ * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
+ *
+ * @note Caution: This function must be used only with the ADC master.
+ *
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ __IO uint32_t counter = 0U;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Check if ADC peripheral is disabled in order to enable it and wait during
+ Tstab time the ADC's stabilization */
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ {
+ /* Enable the Peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(counter != 0U)
+ {
+ counter--;
+ }
+ }
+
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ if (hadc->Init.DMAContinuousRequests != DISABLE)
+ {
+ /* Enable the selected ADC DMA request after last transfer */
+ tmpADC_Common->CCR |= ADC_CCR_DDS;
+ }
+ else
+ {
+ /* Disable the selected ADC EOC rising on each regular channel conversion */
+ tmpADC_Common->CCR &= ~ADC_CCR_DDS;
+ }
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
+
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable the selected ADC DMA mode for multimode */
+ tmpADC_Common->CCR &= ~ADC_CCR_DDS;
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
+ * data in the selected multi mode.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval The converted data value.
+ */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
+{
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Return the multi mode conversion value */
+ return tmpADC_Common->CDR;
+}
+
+/**
+ * @brief Injected conversion complete callback in non blocking mode
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param sConfigInjected ADC configuration structure for injected channel.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+{
+
+#ifdef USE_FULL_ASSERT
+ uint32_t tmp = 0U;
+
+#endif /* USE_FULL_ASSERT */
+
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+ assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+
+#ifdef USE_FULL_ASSERT
+ tmp = ADC_GET_RESOLUTION(hadc);
+ assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
+#endif /* USE_FULL_ASSERT */
+
+ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+ if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
+ {
+ /* Clear the old sample time */
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
+
+ /* Set the new sample time */
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Clear the old sample time */
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
+
+ /* Set the new sample time */
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+ }
+
+ /*---------------------------- ADCx JSQR Configuration -----------------*/
+ hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
+ hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
+
+ /* Rank configuration */
+
+ /* Clear the old SQx bits for the selected rank */
+ hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+
+ /* Set the SQx bits for the selected rank */
+ hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ /* Select external trigger to start conversion */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
+
+ /* Select external trigger polarity */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ }
+ else
+ {
+ /* Reset the external trigger */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+ }
+
+ if (sConfigInjected->AutoInjectedConv != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ hadc->Instance->CR1 |= ADC_CR1_JAUTO;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
+ }
+
+ if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
+ }
+
+ switch(sConfigInjected->InjectedRank)
+ {
+ case 1U:
+ /* Set injected channel 1 offset */
+ hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
+ hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
+ break;
+ case 2U:
+ /* Set injected channel 2 offset */
+ hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
+ hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
+ break;
+ case 3U:
+ /* Set injected channel 3 offset */
+ hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
+ hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
+ break;
+ default:
+ /* Set injected channel 4 offset */
+ hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
+ hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
+ break;
+ }
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* if ADC1 Channel_18 is selected enable VBAT Channel */
+ if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
+ {
+ /* Enable the VBAT channel*/
+ tmpADC_Common->CCR |= ADC_CCR_VBATE;
+ }
+
+ /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
+ if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
+ {
+ /* Enable the TSVREFE channel*/
+ tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the ADC multi-mode
+ * @param hadc pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains
+ * the configuration information for multimode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
+{
+
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MODE(multimode->Mode));
+ assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
+ assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */
+ /* control register) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Set ADC mode */
+ tmpADC_Common->CCR &= ~(ADC_CCR_MULTI);
+ tmpADC_Common->CCR |= multimode->Mode;
+
+ /* Set the ADC DMA access mode */
+ tmpADC_Common->CCR &= ~(ADC_CCR_DMA);
+ tmpADC_Common->CCR |= multimode->DMAAccessMode;
+
+ /* Set delay between two sampling phases */
+ tmpADC_Common->CCR &= ~(ADC_CCR_DELAY);
+ tmpADC_Common->CCR |= multimode->TwoSamplingDelay;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+ {
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F4, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+ }
+ else
+ {
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
+{
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hadc->State= HAL_ADC_STATE_ERROR_DMA;
+ /* Set ADC error code to DMA error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+ HAL_ADC_ErrorCallback(hadc);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,428 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_EX_H
+#define __STM32F4xx_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC Configuration injected Channel structure definition
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
+ * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+ * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
+ * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
+ This parameter can be a value of @ref ADC_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t InjectedRank; /*!< Rank in the injected group sequencer
+ This parameter must be a value of @ref ADCEx_injected_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
+ If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+}ADC_InjectionConfTypeDef;
+
+/**
+ * @brief ADC Configuration multi-mode structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
+ This parameter can be a value of @ref ADCEx_Common_mode */
+ uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
+ This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
+}ADC_MultiModeTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADCEx_Common_mode ADC Common Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT 0x00000000U
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
+#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
+ * @{
+ */
+#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */
+#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
+#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_rank ADC Injected Rank
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 0x00000001U
+#define ADC_INJECTED_RANK_2 0x00000002U
+#define ADC_INJECTED_RANK_3 0x00000003U
+#define ADC_INJECTED_RANK_4 0x00000004U
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_channels ADC Specific Channels
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
+ defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
+ defined(STM32F412Cx)
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx ||
+ STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18)
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
+#endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/**
+ * @brief Disable internal path of ADC channel Vbat
+ * @note Use case of this macro:
+ * On devices STM32F42x and STM32F43x, ADC internal channels
+ * Vbat and VrefInt share the same internal path, only
+ * one of them can be enabled.This macro is to be used when ADC
+ * channels Vbat and VrefInt are selected, and must be called
+ * before starting conversion of ADC channel VrefInt in order
+ * to disable ADC channel Vbat.
+ * @retval None
+ */
+#define __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() (ADC->CCR &= ~(ADC_CCR_VBATE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Macros ADC Private Macros
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||
+ STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INTERL) || \
+ ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
+ ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_INTERL) || \
+ ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
+ ((MODE) == ADC_DMAACCESSMODE_1) || \
+ ((MODE) == ADC_DMAACCESSMODE_2) || \
+ ((MODE) == ADC_DMAACCESSMODE_3))
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= 4U))
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @param _JSQR_JL_ Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
+
+/**
+ * @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1
+ * if available (ADC2, ADC3 availability depends on STM32 product)
+ * @param __HANDLE__ ADC handle
+ * @retval Common control register ADC123 or ADC1
+ */
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define ADC_COMMON_REGISTER(__HANDLE__) ADC123_COMMON
+#else
+#define ADC_COMMON_REGISTER(__HANDLE__) ADC1_COMMON
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx || STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1993 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_can.c
+ * @author MCD Application Team
+ * @brief CAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + Configuration functions
+ * + Control functions
+ * + Interrupts management
+ * + Callbacks functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the CAN low level resources by implementing the
+ HAL_CAN_MspInit():
+ (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
+ (++) Configure CAN pins
+ (+++) Enable the clock for the CAN GPIOs
+ (+++) Configure CAN pins as alternate function open-drain
+ (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
+ (+++) Configure the CAN interrupt priority using
+ HAL_NVIC_SetPriority()
+ (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()
+
+ (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This
+ function resorts to HAL_CAN_MspInit() for low-level initialization.
+
+ (#) Configure the reception filters using the following configuration
+ functions:
+ (++) HAL_CAN_ConfigFilter()
+
+ (#) Start the CAN module using HAL_CAN_Start() function. At this level
+ the node is active on the bus: it receive messages, and can send
+ messages.
+
+ (#) To manage messages transmission, the following Tx control functions
+ can be used:
+ (++) HAL_CAN_AddTxMessage() to request transmission of a new
+ message.
+ (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending
+ message.
+ (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx
+ mailboxes.
+ (++) HAL_CAN_IsTxMessagePending() to check if a message is pending
+ in a Tx mailbox.
+ (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message
+ sent, if time triggered communication mode is enabled.
+
+ (#) When a message is received into the CAN Rx FIFOs, it can be retrieved
+ using the HAL_CAN_GetRxMessage() function. The function
+ HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are
+ stored in the Rx Fifo.
+
+ (#) Calling the HAL_CAN_Stop() function stops the CAN module.
+
+ (#) The deinitialization is achieved with HAL_CAN_DeInit() function.
+
+
+ *** Polling mode operation ***
+ ==============================
+ [..]
+ (#) Reception:
+ (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()
+ until at least one message is received.
+ (++) Then get the message using HAL_CAN_GetRxMessage().
+
+ (#) Transmission:
+ (++) Monitor the Tx mailboxes availability until at least one Tx
+ mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().
+ (++) Then request transmission of a message using
+ HAL_CAN_AddTxMessage().
+
+
+ *** Interrupt mode operation ***
+ ================================
+ [..]
+ (#) Notifications are activated using HAL_CAN_ActivateNotification()
+ function. Then, the process can be controlled through the
+ available user callbacks: HAL_CAN_xxxCallback(), using same APIs
+ HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().
+
+ (#) Notifications can be deactivated using
+ HAL_CAN_DeactivateNotification() function.
+
+ (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and
+ CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig
+ the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and
+ HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options
+ here.
+ (++) Directly get the Rx message in the callback, using
+ HAL_CAN_GetRxMessage().
+ (++) Or deactivate the notification in the callback without
+ getting the Rx message. The Rx message can then be got later
+ using HAL_CAN_GetRxMessage(). Once the Rx message have been
+ read, the notification can be activated again.
+
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (#) The CAN peripheral can be put in sleep mode (low power), using
+ HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the
+ current CAN activity (transmission or reception of a CAN frame) will
+ be completed.
+
+ (#) A notification can be activated to be informed when the sleep mode
+ will be entered.
+
+ (#) It can be checked if the sleep mode is entered using
+ HAL_CAN_IsSleepActive().
+ Note that the CAN state (accessible from the API HAL_CAN_GetState())
+ is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is
+ submitted (the sleep mode is not yet entered), and become
+ HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
+
+ (#) The wake-up from sleep mode can be trigged by two ways:
+ (++) Using HAL_CAN_WakeUp(). When returning from this function,
+ the sleep mode is exited (if return status is HAL_OK).
+ (++) When a start of Rx CAN frame is detected by the CAN peripheral,
+ if automatic wake up mode is enabled.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#if defined(CAN1)
+
+/** @defgroup CAN CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
+#endif
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_Init : Initialize and configure the CAN.
+ (+) HAL_CAN_DeInit : De-initialize the CAN.
+ (+) HAL_CAN_MspInit : Initialize the CAN MSP.
+ (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check CAN handle */
+ if (hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
+ assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
+ assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+ if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Init the low level hardware: CLOCK, NVIC */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check Sleep mode leave acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait initialisation acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TimeTriggeredMode == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.AutoBusOff == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AutoWakeUp == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+ }
+
+ /* Set the automatic retransmission */
+ if (hcan->Init.AutoRetransmission == ENABLE)
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+ }
+ else
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.ReceiveFifoLocked == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TransmitFifoPriority == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+ }
+
+ /* Set the bit timing register */
+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
+ hcan->Init.SyncJumpWidth |
+ hcan->Init.TimeSeg1 |
+ hcan->Init.TimeSeg2 |
+ (hcan->Init.Prescaler - 1U)));
+
+ /* Initialize the error code */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default
+ * reset values.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
+{
+ /* Check CAN handle */
+ if (hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Stop the CAN module */
+ HAL_CAN_Stop(hcan);
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Reset the CAN peripheral */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
+
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Configuration functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0U;
+ CAN_TypeDef *can_ip = hcan->Instance;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+
+#if defined(CAN3)
+ /* Check the CAN instance */
+ if (hcan->Instance == CAN3)
+ {
+ /* CAN3 is single instance with 14 dedicated filters banks */
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+ }
+ else
+ {
+ /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+ /* Select master instance to access the filter banks */
+ can_ip = CAN1;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+ }
+#elif defined(CAN2)
+ /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+ /* Select master instance to access the filter banks */
+ can_ip = CAN1;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+#else
+ /* CAN1 is single instance with 14 dedicated filters banks */
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+#endif
+
+ /* Initialisation mode for the filter */
+ SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+#if defined(CAN3)
+ /* Check the CAN instance */
+ if (can_ip == CAN1)
+ {
+ /* Select the start filter number of CAN2 slave instance */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+ SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+ }
+
+#elif defined(CAN2)
+ /* Select the start filter number of CAN2 slave instance */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+ SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+
+#endif
+ /* Convert filter number into bit position */
+ filternbrbitpos = (1U) << sFilterConfig->FilterBank;
+
+ /* Filter Deactivation */
+ CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ SET_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* 32-bit identifier or First 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* 32-bit mask or Second 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /* Id/Mask mode for the filter*/
+ CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /* Identifier list mode for the filter*/
+ SET_BIT(can_ip->FM1R, filternbrbitpos);
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
+ }
+ else
+ {
+ /* FIFO 1 assignation for the filter */
+ SET_BIT(can_ip->FFA1R, filternbrbitpos);
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ SET_BIT(can_ip->FA1R, filternbrbitpos);
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_Start : Start the CAN module
+ (+) HAL_CAN_Stop : Stop the CAN module
+ (+) HAL_CAN_RequestSleep : Request sleep mode entry.
+ (+) HAL_CAN_WakeUp : Wake up from sleep mode.
+ (+) HAL_CAN_IsSleepActive : Check is sleep mode is active.
+ (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes
+ and activate the corresponding
+ transmission request
+ (+) HAL_CAN_AbortTxRequest : Abort transmission request
+ (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level
+ (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is
+ pending on the selected Tx mailbox
+ (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO
+ (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the CAN module.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
+{
+ uint32_t tickstart = 0U;
+
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_LISTENING;
+
+ /* Request leave initialisation */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Stop the CAN module and enable access to configuration registers.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
+{
+ uint32_t tickstart = 0U;
+
+ if (hcan->State == HAL_CAN_STATE_LISTENING)
+ {
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Request the sleep mode (low power) entry.
+ * When returning from this function, Sleep mode will be entered
+ * as soon as the current CAN activity (transmission or reception
+ * of a CAN frame) has been completed.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
+{
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Request Sleep mode */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Wake up from sleep mode.
+ * When returning with HAL_OK status from this function, Sleep mode
+ * is exited.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
+{
+ __IO uint32_t count = 0;
+ uint32_t timeout = 1000000U;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Wake up request */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Wait sleep mode is exited */
+ do
+ {
+ /* Check if timeout is reached */
+ if (++count > timeout)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ return HAL_ERROR;
+ }
+ }
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Check is sleep mode is active.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Status
+ * - 0 : Sleep mode is not active.
+ * - 1 : Sleep mode is active.
+ */
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
+{
+ uint32_t status = 0U;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Sleep mode */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ {
+ status = 1U;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Add a message to the first free Tx mailbox and activate the
+ * corresponding transmission request.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param pHeader pointer to a CAN_TxHeaderTypeDef structure.
+ * @param aData array containing the payload of the Tx frame.
+ * @param pTxMailbox pointer to a variable where the function will return
+ * the TxMailbox used to store the Tx message.
+ * This parameter can be a value of @arg CAN_Tx_Mailboxes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
+{
+ uint32_t transmitmailbox;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(pHeader->IDE));
+ assert_param(IS_CAN_RTR(pHeader->RTR));
+ assert_param(IS_CAN_DLC(pHeader->DLC));
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(pHeader->StdId));
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(pHeader->ExtId));
+ }
+ assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check that all the Tx mailboxes are not full */
+ if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) ||
+ ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) ||
+ ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET))
+ {
+ /* Select an empty transmit mailbox */
+ transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+
+ /* Store the Tx mailbox */
+ *pTxMailbox = 1U << transmitmailbox;
+
+ /* Set up the Id */
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
+ pHeader->RTR);
+ }
+ else
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
+ pHeader->IDE |
+ pHeader->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
+
+ /* Set up the Transmit Global Time mode */
+ if (pHeader->TransmitGlobalTime == ENABLE)
+ {
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
+ }
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
+ ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
+ ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
+ ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
+ ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
+ ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
+
+ /* Request transmission */
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Abort transmission requests
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of the Tx Mailboxes to abort.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Tx Mailbox 0 */
+ if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET)
+ {
+ /* Add cancellation request for Tx Mailbox 0 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
+ }
+
+ /* Check Tx Mailbox 1 */
+ if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET)
+ {
+ /* Add cancellation request for Tx Mailbox 1 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
+ }
+
+ /* Check Tx Mailbox 2 */
+ if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET)
+ {
+ /* Add cancellation request for Tx Mailbox 2 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Number of free Tx Mailboxes.
+ */
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
+{
+ uint32_t freelevel = 0U;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Tx Mailbox 0 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET)
+ {
+ freelevel++;
+ }
+
+ /* Check Tx Mailbox 1 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET)
+ {
+ freelevel++;
+ }
+
+ /* Check Tx Mailbox 2 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)
+ {
+ freelevel++;
+ }
+ }
+
+ /* Return Tx Mailboxes free level */
+ return freelevel;
+}
+
+/**
+ * @brief Check if a transmission request is pending on the selected Tx
+ * Mailboxes.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of Tx Mailboxes to check.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval Status
+ * - 0 : No pending transmission request on any selected Tx Mailboxes.
+ * - 1 : Pending transmission request on at least one of the selected
+ * Tx Mailbox.
+ */
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+ uint32_t status = 0U;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check pending transmission request on the selected Tx Mailboxes */
+ if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
+ {
+ status = 1U;
+ }
+ }
+
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Return timestamp of Tx message sent, if time triggered communication
+ mode is enabled.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailbox Tx Mailbox where the timestamp of message sent will be
+ * read.
+ * This parameter can be one value of @arg CAN_Tx_Mailboxes.
+ * @retval Timestamp of message sent from Tx Mailbox.
+ */
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
+{
+ uint32_t timestamp = 0U;
+ uint32_t transmitmailbox;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Select the Tx mailbox */
+ transmitmailbox = POSITION_VAL(TxMailbox);
+
+ /* Get timestamp */
+ timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
+ }
+
+ /* Return the timestamp */
+ return timestamp;
+}
+
+/**
+ * @brief Get an CAN frame from the Rx FIFO zone into the message RAM.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Fifo number of the received message to be read.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header
+ * of the Rx frame will be stored.
+ * @param aData array where the payload of the Rx frame will be stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
+{
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check the Rx FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+ else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Check that the Rx FIFO 1 is not empty */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get the header */
+ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
+ }
+ else
+ {
+ pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
+ }
+ pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;
+ pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+ pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
+ pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
+
+ /* Get the data */
+ aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos;
+ aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos;
+ aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos;
+ aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos;
+ aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos;
+ aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos;
+ aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos;
+ aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos;
+
+ /* Release the FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Release RX FIFO 0 */
+ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
+ }
+ else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Release RX FIFO 1 */
+ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Return Rx FIFO fill level.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @retval Number of messages available in Rx FIFO.
+ */
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
+{
+ uint32_t filllevel = 0U;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ if (RxFifo == CAN_RX_FIFO0)
+ {
+ filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
+ }
+ else /* RxFifo == CAN_RX_FIFO1 */
+ {
+ filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
+ }
+ }
+
+ /* Return Rx FIFO fill level */
+ return filllevel;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupts management #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_ActivateNotification : Enable interrupts
+ (+) HAL_CAN_DeactivateNotification : Disable interrupts
+ (+) HAL_CAN_IRQHandler : Handles CAN interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param ActiveITs indicates which interrupts will be enabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
+{
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(ActiveITs));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Enable the selected interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param InactiveITs indicates which interrupts will be disabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
+{
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(InactiveITs));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Disable the selected interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, InactiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
+{
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+ uint32_t interrupts = READ_REG(hcan->Instance->IER);
+ uint32_t msrflags = READ_REG(hcan->Instance->MSR);
+ uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
+ uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
+ uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
+ uint32_t esrflags = READ_REG(hcan->Instance->ESR);
+
+ /* Transmit Mailbox empty interrupt management *****************************/
+ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET)
+ {
+ /* Transmit Mailbox 0 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP0) != RESET)
+ {
+ /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
+
+ if ((tsrflags & CAN_TSR_TXOK0) != RESET)
+ {
+ /* Transmission Mailbox 0 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST0) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST0;
+ }
+ else if ((tsrflags & CAN_TSR_TERR0) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR0;
+ }
+ else
+ {
+ /* Transmission Mailbox 0 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0AbortCallback(hcan);
+ }
+ }
+ }
+
+ /* Transmit Mailbox 1 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP1) != RESET)
+ {
+ /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
+
+ if ((tsrflags & CAN_TSR_TXOK1) != RESET)
+ {
+ /* Transmission Mailbox 1 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST1) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST1;
+ }
+ else if ((tsrflags & CAN_TSR_TERR1) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR1;
+ }
+ else
+ {
+ /* Transmission Mailbox 1 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1AbortCallback(hcan);
+ }
+ }
+ }
+
+ /* Transmit Mailbox 2 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP2) != RESET)
+ {
+ /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
+
+ if ((tsrflags & CAN_TSR_TXOK2) != RESET)
+ {
+ /* Transmission Mailbox 2 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST2) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST2;
+ }
+ else if ((tsrflags & CAN_TSR_TERR2) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR2;
+ }
+ else
+ {
+ /* Transmission Mailbox 2 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2AbortCallback(hcan);
+ }
+ }
+ }
+ }
+
+ /* Receive FIFO 0 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET)
+ {
+ if ((rf0rflags & CAN_RF0R_FOVR0) != RESET)
+ {
+ /* Set CAN error code to Rx Fifo 0 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+ }
+
+ /* Receive FIFO 0 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET)
+ {
+ if ((rf0rflags & CAN_RF0R_FULL0) != RESET)
+ {
+ /* Clear FIFO 0 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
+
+ /* Receive FIFO 0 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0FullCallback(hcan);
+ }
+ }
+
+ /* Receive FIFO 0 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET)
+ {
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET)
+ {
+ /* Receive FIFO 0 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+ }
+ }
+
+ /* Receive FIFO 1 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET)
+ {
+ if ((rf1rflags & CAN_RF1R_FOVR1) != RESET)
+ {
+ /* Set CAN error code to Rx Fifo 1 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+ }
+
+ /* Receive FIFO 1 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET)
+ {
+ if ((rf1rflags & CAN_RF1R_FULL1) != RESET)
+ {
+ /* Clear FIFO 1 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
+
+ /* Receive FIFO 1 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1FullCallback(hcan);
+ }
+ }
+
+ /* Receive FIFO 1 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET)
+ {
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET)
+ {
+ /* Receive FIFO 1 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+ }
+ }
+
+ /* Sleep interrupt management *********************************************/
+ if ((interrupts & CAN_IT_SLEEP_ACK) != RESET)
+ {
+ if ((msrflags & CAN_MSR_SLAKI) != RESET)
+ {
+ /* Clear Sleep interrupt Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
+
+ /* Sleep Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_SleepCallback(hcan);
+ }
+ }
+
+ /* WakeUp interrupt management *********************************************/
+ if ((interrupts & CAN_IT_WAKEUP) != RESET)
+ {
+ if ((msrflags & CAN_MSR_WKUI) != RESET)
+ {
+ /* Clear WakeUp Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
+
+ /* WakeUp Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_WakeUpFromRxMsgCallback(hcan);
+ }
+ }
+
+ /* Error interrupts management *********************************************/
+ if ((interrupts & CAN_IT_ERROR) != RESET)
+ {
+ if ((msrflags & CAN_MSR_ERRI) != RESET)
+ {
+ /* Check Error Warning Flag */
+ if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) &&
+ ((esrflags & CAN_ESR_EWGF) != RESET))
+ {
+ /* Set CAN error code to Error Warning */
+ errorcode |= HAL_CAN_ERROR_EWG;
+
+ /* No need for clear of Error Warning Flag as read-only */
+ }
+
+ /* Check Error Passive Flag */
+ if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) &&
+ ((esrflags & CAN_ESR_EPVF) != RESET))
+ {
+ /* Set CAN error code to Error Passive */
+ errorcode |= HAL_CAN_ERROR_EPV;
+
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ /* Check Bus-off Flag */
+ if (((interrupts & CAN_IT_BUSOFF) != RESET) &&
+ ((esrflags & CAN_ESR_BOFF) != RESET))
+ {
+ /* Set CAN error code to Bus-Off */
+ errorcode |= HAL_CAN_ERROR_BOF;
+
+ /* No need for clear of Error Bus-Off as read-only */
+ }
+
+ /* Check Last Error Code Flag */
+ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) &&
+ ((esrflags & CAN_ESR_LEC) != RESET))
+ {
+ switch (esrflags & CAN_ESR_LEC)
+ {
+ case (CAN_ESR_LEC_0):
+ /* Set CAN error code to Stuff error */
+ errorcode |= HAL_CAN_ERROR_STF;
+ break;
+ case (CAN_ESR_LEC_1):
+ /* Set CAN error code to Form error */
+ errorcode |= HAL_CAN_ERROR_FOR;
+ break;
+ case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Acknowledgement error */
+ errorcode |= HAL_CAN_ERROR_ACK;
+ break;
+ case (CAN_ESR_LEC_2):
+ /* Set CAN error code to Bit recessive error */
+ errorcode |= HAL_CAN_ERROR_BR;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Bit Dominant error */
+ errorcode |= HAL_CAN_ERROR_BD;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ errorcode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+ }
+ }
+
+ /* Clear ERRI Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if (errorcode != HAL_CAN_ERROR_NONE)
+ {
+ /* Update error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ /* Call Error callback function */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief CAN Callback functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..]
+ This subsection provides the following callback functions:
+ (+) HAL_CAN_TxMailbox0CompleteCallback
+ (+) HAL_CAN_TxMailbox1CompleteCallback
+ (+) HAL_CAN_TxMailbox2CompleteCallback
+ (+) HAL_CAN_TxMailbox0AbortCallback
+ (+) HAL_CAN_TxMailbox1AbortCallback
+ (+) HAL_CAN_TxMailbox2AbortCallback
+ (+) HAL_CAN_RxFifo0MsgPendingCallback
+ (+) HAL_CAN_RxFifo0FullCallback
+ (+) HAL_CAN_RxFifo1MsgPendingCallback
+ (+) HAL_CAN_RxFifo1FullCallback
+ (+) HAL_CAN_SleepCallback
+ (+) HAL_CAN_WakeUpFromRxMsgCallback
+ (+) HAL_CAN_ErrorCallback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmission Mailbox 0 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 1 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 2 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 0 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 1 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 2 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0FullCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo1FullCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Sleep callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_SleepCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief WakeUp from Rx message callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) HAL_CAN_GetState() : Return the CAN state.
+ (+) HAL_CAN_GetError() : Return the CAN error codes if any.
+ (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CAN state.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
+{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check sleep mode acknowledge flag */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ {
+ /* Sleep mode is active */
+ state = HAL_CAN_STATE_SLEEP_ACTIVE;
+ }
+ /* Check sleep mode request flag */
+ else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET)
+ {
+ /* Sleep mode request is pending */
+ state = HAL_CAN_STATE_SLEEP_PENDING;
+ }
+ }
+
+ /* Return CAN state */
+ return state;
+}
+
+/**
+ * @brief Return the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ /* Return CAN error code */
+ return hcan->ErrorCode;
+}
+
+/**
+ * @brief Reset the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Reset CAN error code */
+ hcan->ErrorCode = 0U;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ status = HAL_ERROR;
+ }
+
+ /* Return the status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+#endif /* CAN1 */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,784 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_can.h
+ * @author MCD Application Team
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_CAN_H
+#define STM32F4xx_HAL_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#if defined (CAN1)
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
+ HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
+ HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
+ HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
+
+} HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
+ is allowed to lengthen or shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE. */
+
+} CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
+ For single CAN instance(14 dedicated filter banks),
+ this parameter must be a number between Min_Data = 0 and Max_Data = 13.
+ For dual CAN instances(28 filter banks shared),
+ this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
+ For single CAN instances, this parameter is meaningless.
+ For dual CAN instances, all filter banks with lower index are assigned to master
+ CAN instance, whereas all filter banks with greater index are assigned to slave
+ CAN instance.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
+
+} CAN_FilterTypeDef;
+
+/**
+ * @brief CAN Tx message header structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
+ of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
+ @note: Time Triggered Communication Mode must be enabled.
+ @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
+ This parameter can be set to ENABLE or DISABLE. */
+
+} CAN_TxHeaderTypeDef;
+
+/**
+ * @brief CAN Rx message header structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
+ @note: Time Triggered Communication Mode must be enabled.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+} CAN_RxHeaderTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct __CAN_HandleTypeDef
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code.
+ This parameter can be a value of @ref CAN_Error_Code */
+
+} CAN_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+ * @{
+ */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
+#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
+#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
+#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
+#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
+#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
+#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
+#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
+#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
+#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
+#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
+#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
+#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
+#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_InitStatus CAN InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+ * @{
+ */
+#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
+ * @{
+ */
+#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
+ * @{
+ */
+#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
+ * @{
+ */
+#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type CAN Identifier Type
+ * @{
+ */
+#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
+#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+ * @{
+ */
+#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
+#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
+ * @{
+ */
+#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
+#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
+ * @{
+ */
+#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
+#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
+#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags CAN Flags
+ * @{
+ */
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
+#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
+#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
+#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
+#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
+#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
+#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
+#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
+#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
+#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
+#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
+#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
+#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
+#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
+#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
+#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
+#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
+#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
+#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
+#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
+
+/* Error Flags */
+#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
+#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
+#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_Interrupts CAN Interrupts
+ * @{
+ */
+/* Transmit Interrupt */
+#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__ CAN handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to enable.
+ * This parameter can be any combination of @arg CAN_Interrupts
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to disable.
+ * This parameter can be any combination of @arg CAN_Interrupts
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __INTERRUPT__ specifies the CAN interrupt source to check.
+ * This parameter can be a value of @arg CAN_Interrupts
+ * @retval The state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of @arg CAN_flags
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
+ * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
+ * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
+ * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
+ * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
+ * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
+ * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
+ * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
+ * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
+ * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
+ * @retval None
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ * @{
+ */
+
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief Callback functions
+ * @{
+ */
+/* Callbacks functions ********************************************************/
+
+void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_FLAG_MASK (0x000000FFU)
+/**
+ * @}
+ */
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
+ ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
+ ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
+ ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
+ ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
+ ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
+ ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
+ ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
+#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
+ ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
+ ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
+ ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
+#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
+#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
+#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
+#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
+#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
+ CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
+ CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
+ CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
+ CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
+ CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
+ CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+
+#endif /* CAN1 */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1697 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_can.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### User NOTE #####
+ ==============================================================================
+ [..]
+ (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations.
+ Another HAL CAN driver version has been designed with new API's, to fix these limitations.
+
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the CAN controller interface clock using
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
+ and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
+ -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
+
+ (#) CAN pins configuration
+ (++) Enable the clock for the CAN GPIOs using the following function:
+ __GPIOx_CLK_ENABLE()
+ (++) Connect and configure the involved CAN pins to AF9 using the
+ following function HAL_GPIO_Init()
+
+ (#) Initialize and configure the CAN using CAN_Init() function.
+
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
+
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
+
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the CAN peripheral transmission and wait the end of this operation
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+ according to his end application
+ (+) Start the CAN peripheral reception and wait the end of this operation
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+ according to his end application
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback
+
+ *** CAN HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in CAN HAL driver.
+
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+
+ [..]
+ (@) You can refer to the CAN Legacy HAL driver header file for more useful macros
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CAN CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+
+#ifdef HAL_CAN_MODULE_ENABLED
+/* Select HAL CAN module in stm32f4xx_hal_conf.h file:
+ (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations
+ (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */
+#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f4xx_hal_conf.h file'
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+// #warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver'
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CAN_Private_Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the CAN.
+ (+) De-initialize the CAN.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+ uint32_t InitStatus = CAN_INITSTATUS_FAILED;
+ uint32_t tickstart = 0U;
+
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+
+ if(hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Initialize the CAN state*/
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Exit from sleep mode */
+ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ hcan->Instance->MCR |= CAN_MCR_INRQ ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledge */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TTCM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TTCM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.ABOM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_ABOM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AWUM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_AWUM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (hcan->Init.NART == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_NART;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.RFLM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_RFLM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TXFP == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TXFP;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
+ ((uint32_t)hcan->Init.SJW) | \
+ ((uint32_t)hcan->Init.BS1) | \
+ ((uint32_t)hcan->Init.BS2) | \
+ ((uint32_t)hcan->Init.Prescaler - 1U);
+
+ /* Request leave initialisation */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledged */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ InitStatus = CAN_INITSTATUS_SUCCESS;
+ }
+ }
+
+ if(InitStatus == CAN_INITSTATUS_SUCCESS)
+ {
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0U;
+ CAN_TypeDef *can_ip;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
+
+ filternbrbitpos = 1U << sFilterConfig->FilterNumber;
+#if defined (CAN3)
+ /* Check the CAN instance */
+ if(hcan->Instance == CAN3)
+ {
+ can_ip = CAN3;
+ }
+ else
+ {
+ can_ip = CAN1;
+ }
+#else
+ can_ip = CAN1;
+#endif
+
+ /* Initialisation mode for the filter */
+ can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
+
+#if defined (CAN2)
+ /* Select the start slave bank */
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
+ can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
+#endif
+
+ /* Filter Deactivation */
+ can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ can_ip->FS1R |= filternbrbitpos;
+
+ /* 32-bit identifier or First 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /*Id/Mask mode for the filter*/
+ can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ can_ip->FM1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
+ }
+
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ can_ip->FFA1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ can_ip->FA1R |= filternbrbitpos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CANx peripheral registers to their default reset values.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a CAN frame message.
+ (+) Receive a CAN frame message.
+ (+) Enter CAN peripheral in sleep mode.
+ (+) Wake up the CAN peripheral from sleep mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Select one empty transmit mailbox */
+ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[0U]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[4U]));
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check End of transmission flag */
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcan);
+
+ /* Select one empty transmit mailbox */
+ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[0U]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[4U]));
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Enable Error warning, Error passive, Bus-off,
+ Last error and Error Interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME);
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber FIFO Number value
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check pending message */
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ }
+ else
+ {
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ }
+
+ pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the data field */
+ pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+
+ /* Release the FIFO */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Release FIFO0 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ /* Release FIFO1 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber Specify the FIFO number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ else
+ {
+ /* Enable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the Sleep (low power) mode.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Request Sleep mode */
+ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
+ * is in the normal mode.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Wake up request */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Sleep mode status */
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+ /* Check Overrun flag for FIFO0 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
+ if(tmp1 && tmp2)
+ {
+ /* Set CAN error code to FOV0 error */
+ errorcode |= HAL_CAN_ERROR_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+ /* Check Overrun flag for FIFO1 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
+
+ if(tmp1 && tmp2)
+ {
+ /* Set CAN error code to FOV1 error */
+ errorcode |= HAL_CAN_ERROR_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+
+ /* Check End of transmission flag */
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+ {
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
+ if(tmp1 || tmp2 || tmp3)
+ {
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
+ tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
+ tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
+ /* Check Transmit success */
+ if(tmp1 || tmp2 || tmp3)
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ else /* Transmit failure */
+ {
+ /* Set CAN error code to TXFAIL error */
+ errorcode |= HAL_CAN_ERROR_TXFAIL;
+ }
+
+ /* Clear transmission status flags (RQCPx and TXOKx) */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
+ CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
+ }
+ }
+
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
+ /* Check End of reception flag for FIFO0 */
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO0);
+ }
+
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
+ /* Check End of reception flag for FIFO1 */
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO1);
+ }
+
+ /* Set error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Error Warning Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to EWG error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Error Passive Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to EPV error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Bus-Off Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to BOF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+ }
+
+ tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Last error code Flag */
+ if((!tmp1) && tmp2 && tmp3)
+ {
+ tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
+ switch(tmp1)
+ {
+ case(CAN_ESR_LEC_0):
+ /* Set CAN error code to STF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+ break;
+ case(CAN_ESR_LEC_1):
+ /* Set CAN error code to FOR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+ break;
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to ACK error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+ break;
+ case(CAN_ESR_LEC_2):
+ /* Set CAN error code to BR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to BD error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ hcan->Instance->ESR &= ~(CAN_ESR_LEC);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+ {
+ /* Clear ERRI Flag */
+ hcan->Instance->MSR = CAN_MSR_ERRI;
+ /* Set the CAN state ready to be able to start again the process */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ /* - Disable FIFO 0 message pending Interrupt */
+ /* - Disable FIFO 0 Overrun Interrupt */
+ /* - Disable FIFO 1 message pending Interrupt */
+ /* - Disable FIFO 1 Overrun Interrupt */
+ /* - Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_FMP0|
+ CAN_IT_FOV0|
+ CAN_IT_FMP1|
+ CAN_IT_FOV1|
+ CAN_IT_TME);
+
+ /* Call Error callback function */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Check the CAN state.
+ (+) Check CAN Errors detected during interrupt process
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CAN state
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+ /* Return CAN state */
+ return hcan->State;
+}
+
+/**
+ * @brief Return the CAN error code
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ return hcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ /* Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Disable Error warning, Error passive, Bus-off, Last error code
+ and Error Interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
+ }
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Transmission complete callback */
+ HAL_CAN_TxCpltCallback(hcan);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber Specify the FIFO number
+ * @retval HAL status
+ * @retval None
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ uint32_t tmp1 = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ }
+ else
+ {
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ }
+
+ pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the FMI */
+ pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the data field */
+ pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+
+ /* Disable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+
+ /* Disable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ tmp1 = hcan->State;
+ if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
+ {
+ /* Disable Error warning, Error passive, Bus-off, Last error code
+ and Error Interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Receive complete callback */
+ HAL_CAN_RxCpltCallback(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,785 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_can_legacy.h
+ * @author MCD Application Team
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CAN_LEGACY_H
+#define __STM32F4xx_HAL_CAN_LEGACY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE */
+}CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+
+}CAN_FilterConfTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_Identifier_Type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+}CanTxMsgTypeDef;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_Identifier_Type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
+
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
+
+ CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code */
+
+}CAN_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+ * @{
+ */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
+#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
+#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
+#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
+#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
+#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
+#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
+#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_InitStatus CAN InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+ * @{
+ */
+#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
+ * @{
+ */
+#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
+ * @{
+ */
+#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
+ * @{
+ */
+#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Identifier_Type CAN Identifier Type
+ * @{
+ */
+#define CAN_ID_STD 0x00000000U /*!< Standard Id */
+#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+ * @{
+ */
+#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
+#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags CAN Flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */
+#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */
+#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */
+
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */
+#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */
+#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Interrupts CAN Interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
+ * @{
+ */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle
+ * @param __INTERRUPT__ CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle
+ * @param __INTERRUPT__ CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Return the number of pending received messages.
+ * @param __HANDLE__ CAN handle
+ * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval The number of pending message.
+ */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__ CAN Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__ CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ CAN Handle
+ * @param __INTERRUPT__ specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
+ * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check the transmission status of a CAN Frame.
+ * @param __HANDLE__ CAN Handle
+ * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
+ * @retval The new status of transmission (TRUE or FALSE).
+ */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+/**
+ * @brief Release the specified receive FIFO.
+ * @param __HANDLE__ CAN handle
+ * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None
+ */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
+
+/**
+ * @brief Cancel a transmit request.
+ * @param __HANDLE__ CAN Handle
+ * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
+ * @retval None
+ */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
+
+/**
+ * @brief Enable or disable the DBG Freeze for CAN.
+ * @param __HANDLE__ CAN Handle
+ * @param __NEWSTATE__ new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ***************************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_FLAG_MASK 0x000000FFU
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CAN_LEGACY_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,671 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cec.c
+ * @author MCD Application Team
+ * @brief CEC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Definition Multimedia Interface
+ * Consumer Electronics Control Peripheral (CEC).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The CEC HAL driver can be used as follow:
+
+ (#) Declare a CEC_HandleTypeDef handle structure.
+ (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
+ (##) Enable the CEC interface clock.
+ (##) CEC pins configuration:
+ (+++) Enable the clock for the CEC GPIOs.
+ (+++) Configure these CEC pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
+ and HAL_CEC_Receive_IT() APIs):
+ (+++) Configure the CEC interrupt priority.
+ (+++) Enable the NVIC CEC IRQ handle.
+ (+++) The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
+
+ (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
+ in case of Bit Rising Error, Error-Bit generation conditions, device logical
+ address and Listen mode in the hcec Init structure.
+
+ (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
+
+ [..]
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...)
+ by calling the customed HAL_CEC_MspInit() API.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CEC CEC
+ * @brief HAL CEC module driver
+ * @{
+ */
+#ifdef HAL_CEC_MODULE_ENABLED
+
+#if defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+
+/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the CEC
+ (+) The following parameters need to be configured:
+ (++) SignalFreeTime
+ (++) Tolerance
+ (++) BRERxStop (RX stopped or not upon Bit Rising Error)
+ (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
+ (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
+ (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
+ (++) SignalFreeTimeOption (SFT Timer start definition)
+ (++) OwnAddress (CEC device address)
+ (++) ListenMode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CEC mode according to the specified
+ * parameters in the CEC_InitTypeDef and creates the associated handle .
+ * @param hcec CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+ assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
+ assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
+ assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
+ assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
+ assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
+ assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
+ assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
+ assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
+ assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
+
+ if(hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcec->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_CEC_MspInit(hcec);
+ }
+ hcec->gState = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Write to CEC Control Register */
+ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
+ hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
+ hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
+ hcec->Init.ListenMode;
+
+ /* Enable the following CEC Transmission/Reception interrupts as
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+
+ /* Enable the CEC Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->gState = HAL_CEC_STATE_READY;
+ hcec->RxState = HAL_CEC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CEC peripheral
+ * @param hcec CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+
+ hcec->gState = HAL_CEC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CEC_MspDeInit(hcec);
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Clear Flags */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
+
+ /* Disable the following CEC Transmission/Reception interrupts as
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->gState = HAL_CEC_STATE_RESET;
+ hcec->RxState = HAL_CEC_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the Own Address of the CEC device
+ * @param hcec CEC handle
+ * @param CEC_OwnAddress The CEC own address.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
+{
+ /* Check the parameters */
+ assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
+
+ if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->gState = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
+ {
+ hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U);
+ }
+ else
+ {
+ hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
+ }
+
+ hcec->gState = HAL_CEC_STATE_READY;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief CEC MSP Init
+ * @param hcec CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC MSP DeInit
+ * @param hcec CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief CEC Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the CEC data transfers.
+
+ (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
+ logical addresses (4-bit long addresses, 0x0F for broadcast messages destination)
+
+ (#) The communication is performed using Interrupts.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated CEC IRQ when using Interrupt mode.
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ error is detected
+
+ (#) API's with Interrupt are :
+ (+) HAL_CEC_Transmit_IT()
+ (+) HAL_CEC_IRQHandler()
+
+ (#) A set of User Callbacks are provided:
+ (+) HAL_CEC_TxCpltCallback()
+ (+) HAL_CEC_RxCpltCallback()
+ (+) HAL_CEC_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send data in interrupt mode
+ * @param hcec CEC handle
+ * @param InitiatorAddress Initiator logical address
+ * @param DestinationAddress destination logical address
+ * @param pData pointer to input byte data buffer
+ * @param Size amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+{
+ /* if the IP isn't already busy and if there is no previous transmission
+ already pending due to arbitration lost */
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ if((pData == NULL ) && (Size > 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_ADDRESS(InitiatorAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->pTxBuffPtr = pData;
+ hcec->gState = HAL_CEC_STATE_BUSY_TX;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* initialize the number of bytes to send,
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = Size;
+
+ /* in case of no payload (Size = 0), sender is only pinging the system;
+ Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ if (Size == 0U)
+ {
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Get size of the received frame.
+ * @param hcec CEC handle
+ * @retval Frame size
+ */
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
+{
+ return hcec->RxXferSize;
+}
+
+/**
+ * @brief Change Rx Buffer.
+ * @param hcec CEC handle
+ * @param Rxbuffer Rx Buffer
+ * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
+ * @retval Frame size
+ */
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
+{
+ hcec->Init.RxBuffer = Rxbuffer;
+}
+
+/**
+ * @brief This function handles CEC interrupt requests.
+ * @param hcec CEC handle
+ * @retval None
+ */
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
+{
+
+ /* save interrupts register for further error or interrupts handling purposes */
+ uint32_t reg = 0U;
+ reg = hcec->Instance->ISR;
+
+
+ /* ----------------------------Arbitration Lost Management----------------------------------*/
+ /* CEC TX arbitration error interrupt occurred --------------------------------------*/
+ if((reg & CEC_FLAG_ARBLST) != RESET)
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
+ }
+
+ /* ----------------------------Rx Management----------------------------------*/
+ /* CEC RX byte received interrupt ---------------------------------------------------*/
+ if((reg & CEC_FLAG_RXBR) != RESET)
+ {
+ /* reception is starting */
+ hcec->RxState = HAL_CEC_STATE_BUSY_RX;
+ hcec->RxXferSize++;
+ /* read received byte */
+ *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
+ }
+
+ /* CEC RX end received interrupt ---------------------------------------------------*/
+ if((reg & CEC_FLAG_RXEND) != RESET)
+ {
+ /* clear IT */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
+
+ /* Rx process is completed, restore hcec->RxState to Ready */
+ hcec->RxState = HAL_CEC_STATE_READY;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->Init.RxBuffer -= hcec->RxXferSize;
+ HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
+ hcec->RxXferSize = 0U;
+ }
+
+ /* ----------------------------Tx Management----------------------------------*/
+ /* CEC TX byte request interrupt ------------------------------------------------*/
+ if((reg & CEC_FLAG_TXBR) != RESET)
+ {
+ if (hcec->TxXferCount == 0U)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ }
+ else
+ {
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
+ }
+
+ /* CEC TX end interrupt ------------------------------------------------*/
+ if((reg & CEC_FLAG_TXEND) != RESET)
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
+
+ /* Tx process is ended, restore hcec->gState to Ready */
+ hcec->gState = HAL_CEC_STATE_READY;
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+ start again the Transmission under the Tx call back API */
+ __HAL_UNLOCK(hcec);
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ HAL_CEC_TxCpltCallback(hcec);
+ }
+
+ /* ----------------------------Rx/Tx Error Management----------------------------------*/
+ if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U)
+ {
+ hcec->ErrorCode = reg;
+ __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
+
+
+ if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
+ {
+ hcec->Init.RxBuffer-=hcec->RxXferSize;
+ hcec->RxXferSize = 0U;
+ hcec->RxState = HAL_CEC_STATE_READY;
+ }
+ else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
+ {
+ /* Set the CEC state ready to be able to start again the process */
+ hcec->gState = HAL_CEC_STATE_READY;
+ }
+
+ /* Error Call Back */
+ HAL_CEC_ErrorCallback(hcec);
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback
+ * @param hcec CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param hcec CEC handle
+ * @param RxFrameSize Size of frame
+ * @retval None
+ */
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ UNUSED(RxFrameSize);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC error callbacks
+ * @param hcec CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcec);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_ErrorCallback can be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
+ * @brief CEC control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control function #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CEC.
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+ (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
+@endverbatim
+ * @{
+ */
+/**
+ * @brief return the CEC state
+ * @param hcec pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC module.
+ * @retval HAL state
+ */
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
+{
+ uint32_t temp1 = 0x00U, temp2 = 0x00U;
+ temp1 = hcec->gState;
+ temp2 = hcec->RxState;
+
+ return (HAL_CEC_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the CEC error code
+ * @param hcec pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC.
+ * @retval CEC Error Code
+ */
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
+{
+ return hcec->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F446xx */
+
+#endif /* HAL_CEC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,745 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cec.h
+ * @author MCD Application Team
+ * @brief Header file of CEC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CEC_H
+#define __STM32F4xx_HAL_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CEC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CEC_Exported_Types CEC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CEC Init Structure definition
+ */
+typedef struct
+{
+ uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
+ It can be one of @ref CEC_Signal_Free_Time
+ and belongs to the set {0,...,7} where
+ 0x0 is the default configuration
+ else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
+
+ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
+ it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
+ or CEC_EXTENDED_TOLERANCE */
+
+ uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+ CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
+ CEC_RX_STOP_ON_BRE: reception is stopped. */
+
+ uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Bit Rising Error detection.
+ CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
+
+ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Long Bit Period Error detection.
+ CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
+
+ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
+ upon an error detected on a broadcast message.
+
+ It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
+
+ 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
+ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
+ and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
+ b) LBPE detection: error-bit generation on the CEC line
+ if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
+
+ 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
+ no error-bit generation in case neither a) nor b) are satisfied. Additionally,
+ there is no error-bit generation in case of Short Bit Period Error detection in
+ a broadcast message while LSTN bit is set. */
+
+ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
+ CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
+ CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
+
+ uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
+
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
+ own address (OAR). Messages addressed to different destination are ignored.
+ Broadcast messages are always received.
+
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
+ address (OAR) with positive acknowledge. Messages addressed to different destination
+ are received, but without interfering with the CEC bus: no acknowledge sent. */
+
+ uint16_t OwnAddress; /*!< Own addresses configuration
+ This parameter can be a value of @ref CEC_OWN_ADDRESS */
+
+ uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
+
+
+}CEC_InitTypeDef;
+
+/**
+ * @brief HAL CEC State structures definition
+ * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains CEC state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7 (not used)
+ * x : Should be set to 0
+ * b6 Error information
+ * 0 : No Error
+ * 1 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized. HAL CEC Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef enum
+{
+ HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
+}HAL_CEC_StateTypeDef;
+
+/**
+ * @brief CEC handle Structure definition
+ */
+typedef struct
+{
+ CEC_TypeDef *Instance; /*!< CEC registers base address */
+
+ CEC_InitTypeDef Init; /*!< CEC communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
+
+ uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
+
+ uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+
+ HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
+ This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+
+ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
+ in case error is reported */
+}CEC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CEC_Exported_Constants CEC Exported Constants
+ * @{
+ */
+
+/** @defgroup CEC_Error_Code CEC Error Code
+ * @{
+ */
+#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
+#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
+#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
+#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
+#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
+#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
+#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
+#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
+#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
+#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
+ * @{
+ */
+#define CEC_DEFAULT_SFT 0x00000000U
+#define CEC_0_5_BITPERIOD_SFT 0x00000001U
+#define CEC_1_5_BITPERIOD_SFT 0x00000002U
+#define CEC_2_5_BITPERIOD_SFT 0x00000003U
+#define CEC_3_5_BITPERIOD_SFT 0x00000004U
+#define CEC_4_5_BITPERIOD_SFT 0x00000005U
+#define CEC_5_5_BITPERIOD_SFT 0x00000006U
+#define CEC_6_5_BITPERIOD_SFT 0x00000007U
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Tolerance CEC Receiver Tolerance
+ * @{
+ */
+#define CEC_STANDARD_TOLERANCE 0x00000000U
+#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
+ * @{
+ */
+#define CEC_NO_RX_STOP_ON_BRE 0x00000000U
+#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
+ * @{
+ */
+#define CEC_BRE_ERRORBIT_NO_GENERATION 0x00000000U
+#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
+ * @{
+ */
+#define CEC_LBPE_ERRORBIT_NO_GENERATION 0x00000000U
+#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
+ * @{
+ */
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION 0x00000000U
+#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
+ * @{
+ */
+#define CEC_SFT_START_ON_TXSOM 0x00000000U
+#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Listening_Mode CEC Listening mode option
+ * @{
+ */
+#define CEC_REDUCED_LISTENING_MODE 0x00000000U
+#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
+ * @{
+ */
+#define CEC_CFGR_OAR_LSB_POS 16U
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
+ * @{
+ */
+#define CEC_INITIATOR_LSB_POS 4U
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OWN_ADDRESS CEC Own Address
+ * @{
+ */
+#define CEC_OWN_ADDRESS_NONE ((uint16_t)0x0000) /* Reset value */
+#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0001) /* Logical Address 0 */
+#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0002) /* Logical Address 1 */
+#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0004) /* Logical Address 2 */
+#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0008) /* Logical Address 3 */
+#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0010) /* Logical Address 4 */
+#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0020) /* Logical Address 5 */
+#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0040) /* Logical Address 6 */
+#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0080) /* Logical Address 7 */
+#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0100) /* Logical Address 9 */
+#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0200) /* Logical Address 10 */
+#define CEC_OWN_ADDRESS_10 ((uint16_t)0x0400) /* Logical Address 11 */
+#define CEC_OWN_ADDRESS_11 ((uint16_t)0x0800) /* Logical Address 12 */
+#define CEC_OWN_ADDRESS_12 ((uint16_t)0x1000) /* Logical Address 13 */
+#define CEC_OWN_ADDRESS_13 ((uint16_t)0x2000) /* Logical Address 14 */
+#define CEC_OWN_ADDRESS_14 ((uint16_t)0x4000) /* Logical Address 15 */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
+ * @{
+ */
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE
+#define CEC_IT_TXERR CEC_IER_TXERRIE
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE
+#define CEC_IT_TXEND CEC_IER_TXENDIE
+#define CEC_IT_TXBR CEC_IER_TXBRIE
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE
+#define CEC_IT_LBPE CEC_IER_LBPEIE
+#define CEC_IT_SBPE CEC_IER_SBPEIE
+#define CEC_IT_BRE CEC_IER_BREIE
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE
+#define CEC_IT_RXEND CEC_IER_RXENDIE
+#define CEC_IT_RXBR CEC_IER_RXBRIE
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Flags_Definitions CEC Flags definition
+ * @{
+ */
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND CEC_ISR_TXEND
+#define CEC_FLAG_TXBR CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE CEC_ISR_LBPE
+#define CEC_FLAG_SBPE CEC_ISR_SBPE
+#define CEC_FLAG_BRE CEC_ISR_BRE
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND CEC_ISR_RXEND
+#define CEC_FLAG_RXBR CEC_ISR_RXBR
+/**
+ * @}
+ */
+
+/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
+ * @{
+ */
+#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CEC_Exported_Macros CEC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CEC handle gstate & RxState
+ * @param __HANDLE__ CEC handle.
+ * @retval None
+ */
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
+ } while(0)
+
+/** @brief Checks whether or not the specified CEC interrupt flag is set.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rising Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval ITStatus
+ */
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/** @brief Clears the interrupt or status flag when raised (write at 1)
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __FLAG__ specifies the interrupt/status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rising Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
+
+/** @brief Enables the specified CEC interrupt.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief Disables the specified CEC interrupt.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief Checks whether or not the specified CEC interrupt is enabled.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+
+/** @brief Enables the CEC device
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
+
+/** @brief Disables the CEC device
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
+
+/** @brief Set Transmission Start flag
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
+
+/** @brief Set Transmission End flag
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
+ */
+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
+
+/** @brief Get Transmission Start flag
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
+
+/** @brief Get Transmission End flag
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
+
+/** @brief Clear OAR register
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
+
+/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
+ * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
+ * @retval none
+ */
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CEC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CEC_Private_Types CEC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Variables CEC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Macros CEC Private Macros
+ * @{
+ */
+
+#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
+
+#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
+ ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
+
+#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
+ ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
+
+#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
+
+#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
+
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+
+#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
+ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
+
+#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
+ ((__MODE__) == CEC_FULL_LISTENING_MODE))
+
+/** @brief Check CEC message size.
+ * The message size is the payload size: without counting the header,
+ * it varies from 0 byte (ping operation, one header only, no payload) to
+ * 15 bytes (1 opcode and up to 14 operands following the header).
+ * @param __SIZE__ CEC message size.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
+
+/** @brief Check CEC device Own Address Register (OAR) setting.
+ * OAR address is written in a 15-bit field within CEC_CFGR register.
+ * @param __ADDRESS__ CEC own address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
+
+/** @brief Check CEC initiator or destination logical address setting.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__ CEC initiator or logical address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
+/**
+ * @}
+ */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,451 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+/* #define HAL_CAN_MODULE_ENABLED */
+#define HAL_CAN_LEGACY_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_DSI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_FMPI2C_MODULE_ENABLED
+#define HAL_SPDIFRX_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 1U
+#define DATA_CACHE_ENABLE 1U
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2U
+#define MAC_ADDR1 0U
+#define MAC_ADDR2 0U
+#define MAC_ADDR3 0U
+#define MAC_ADDR4 0U
+#define MAC_ADDR5 0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY 0x00000FFFU
+
+#define PHY_READ_TO 0x0000FFFFU
+#define PHY_WRITE_TO 0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC 1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/* ALL MBED targets use same stm32_assert.h */
+#include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,521 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cortex.c
+ * @author MCD Application Team
+ * @brief CORTEX HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M4 exceptions are managed by CMSIS functions.
+
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+ function according to the following table.
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+ (#) please refer to programming manual for details in how to configure priority.
+
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
+ The pending IRQ priority will be managed only by the sub priority.
+
+ -@- IRQ priority order (sorted by highest to lowest priority):
+ (+@) Lowest preemption priority
+ (+@) Lowest sub priority
+ (+@) Lowest hardware priority (IRQ number)
+
+ [..]
+ *** How to configure Systick using CORTEX HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base.
+
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+ inside the stm32f4xx_hal_cortex.h file.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @brief CORTEX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ Systick functionalities
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Sets the priority grouping field (preemption priority and subpriority)
+ * using the required unlock sequence.
+ * @param PriorityGroup The priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+ * 0 bits for subpriority
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+ * @param PreemptPriority The preemption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority
+ * @param SubPriority the subpriority level for the IRQ channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t prioritygroup = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ * @brief Disables the MPU
+ * @retval None
+ */
+void HAL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU and clear the control register*/
+ MPU->CTRL = 0U;
+}
+
+/**
+ * @brief Enable the MPU.
+ * @param MPU_Control Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Ensure MPU setting take effects */
+ __DSB();
+ __ISB();
+}
+
+/**
+ * @brief Initializes and configures the Region and the memory to be protected.
+ * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ if ((MPU_Init->Enable) != RESET)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ }
+ else
+ {
+ MPU->RBAR = 0x00U;
+ MPU->RASR = 0x00U;
+ }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+ /* Get the PRIGROUP[10:8] field value */
+ return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+ * @param PriorityGroup the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+ * 0 bits for subpriority
+ * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority Pointer on the Subpriority value (starting from 0).
+ * @retval None
+ */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * and returns the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Return 1 if active else 0 */
+ return NVIC_GetActive(IRQn);
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param CLKSource specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief This function handles SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,426 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CORTEX_H
+#define __STM32F4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1U)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief MPU Region initialization structure
+ * @{
+ */
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint8_t Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
+}MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
+
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
+#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
+#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
+#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1U)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
+ ((TYPE) == MPU_TEX_LEVEL1) || \
+ ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
+ ((SIZE) == MPU_REGION_SIZE_64B) || \
+ ((SIZE) == MPU_REGION_SIZE_128B) || \
+ ((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || \
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \
+ ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,344 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_crc.c
+ * @author MCD Application Team
+ * @brief CRC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The CRC HAL driver can be used as follows:
+
+ (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+
+ (#) Use HAL_CRC_Accumulate() function to compute the CRC value of
+ a 32-bit data buffer using combination of the previous CRC value
+ and the new one.
+
+ (#) Use HAL_CRC_Calculate() function to compute the CRC Value of
+ a new 32-bit data buffer. This function resets the CRC computation
+ unit before starting the computation to avoid getting wrong CRC values.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC according to the specified parameters
+ in the CRC_InitTypeDef and create the associated handle
+ (+) DeInitialize the CRC peripheral
+ (+) Initialize the CRC MSP
+ (+) DeInitialize CRC MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRC according to the specified
+ * parameters in the CRC_InitTypeDef and creates the associated handle.
+ * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ if(hcrc->State == HAL_CRC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcrc->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CRC_MspInit(hcrc);
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CRC peripheral.
+ * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CRC_MspDeInit(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRC MSP.
+ * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval None
+ */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CRC MSP.
+ * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval None
+ */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group2
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Compute the 32-bit CRC value of 32-bit data buffer,
+ using combination of the previous CRC value and the new one.
+ (+) Compute the 32-bit CRC value of 32-bit data buffer,
+ independently of the previous CRC value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Computes the 32-bit CRC of 32-bit data buffer using combination
+ * of the previous CRC value and the new one.
+ * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @param pBuffer pointer to the buffer containing the data to be computed
+ * @param BufferLength length of the buffer to be computed
+ * @retval 32-bit CRC
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Enter Data to the CRC calculator */
+ for(index = 0U; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of 32-bit data buffer independently
+ * of the previous CRC value.
+ * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @param pBuffer Pointer to the buffer containing the data to be computed
+ * @param BufferLength Length of the buffer to be computed
+ * @retval 32-bit CRC
+ */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC Calculation Unit */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ /* Enter Data to the CRC calculator */
+ for(index = 0U; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup CRC_Exported_Functions_Group3
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the CRC state.
+ * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval HAL state
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+ return hcrc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,247 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_crc.h
+ * @author MCD Application Team
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRC_H
+#define __STM32F4xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRC CRC
+ * @brief CRC HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
+ * @{
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
+
+}HAL_CRC_StateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Types_Group2 CRC Handle Structure definition
+ * @{
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ HAL_LockTypeDef Lock; /*!< CRC locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+}CRC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @brief Resets CRC handle state
+ * @param __HANDLE__ CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+ * @brief Resets CRC Data Register.
+ * @param __HANDLE__ CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param __HANDLE__ CRC handle
+ * @param __VALUE__ 8-bit value to be stored in the ID register
+ * @retval None
+ */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
+ * @param __HANDLE__ CRC handle
+ * @retval 8-bit value of the ID register
+ */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRC_Private_Types CRC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRC_Private_Defines CRC Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Variables CRC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Constants CRC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,5159 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cryp.c
+ * @author MCD Application Team
+ * @brief CRYP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cryptography (CRYP) peripheral:
+ * + Initialization and de-initialization functions
+ * + AES processing functions
+ * + DES processing functions
+ * + TDES processing functions
+ * + DMA callback functions
+ * + CRYP IRQ handler management
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The CRYP HAL driver can be used as follows:
+
+ (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
+ (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
+ (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
+ (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++) Configure and enable two DMA streams one for managing data transfer from
+ memory to peripheral (input stream) and another stream for managing data
+ transfer from peripheral to memory (output stream)
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the two DMA Streams. The output stream should have higher
+ priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+
+ (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
+ (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
+ (##) The encryption/decryption key. It's size depends on the algorithm
+ used for encryption/decryption
+ (##) The initialization vector (counter). It is not used ECB mode.
+
+ (#)Three processing (encryption/decryption) functions are available:
+ (##) Polling mode: encryption and decryption APIs are blocking functions
+ i.e. they process the data and wait till the processing is finished,
+ e.g. HAL_CRYP_AESCBC_Encrypt()
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+ i.e. they process the data under interrupt,
+ e.g. HAL_CRYP_AESCBC_Encrypt_IT()
+ (##) DMA mode: encryption and decryption APIs are not blocking functions
+ i.e. the data transfer is ensured by DMA,
+ e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
+
+ (#)When the processing function is called at first time after HAL_CRYP_Init()
+ the CRYP peripheral is initialized and processes the buffer in input.
+ At second call, the processing function performs an append of the already
+ processed buffer.
+ When a new data block is to be processed, call HAL_CRYP_Init() then the
+ processing function.
+
+ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+#if defined(CRYP)
+
+/** @defgroup CRYP CRYP
+ * @brief CRYP HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CRYP_Private_define
+ * @{
+ */
+#define CRYP_TIMEOUT_VALUE 1U
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions_prototypes
+ * @{
+ */
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup CRYP_Private_Functions
+ * @{
+ */
+
+
+/**
+ * @brief DMA CRYP Input Data process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+
+ /* Call input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP Output Data process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ hcryp->State= HAL_CRYP_STATE_READY;
+ HAL_CRYP_ErrorCallback(hcryp);
+}
+
+/**
+ * @brief Writes the Key in Key registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Key Pointer to Key buffer
+ * @param KeySize Size of Key
+ * @retval None
+ */
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
+{
+ uint32_t keyaddr = (uint32_t)Key;
+
+ switch(KeySize)
+ {
+ case CRYP_KEYSIZE_256B:
+ /* Key Initialisation */
+ hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Writes the InitVector/InitCounter in IV registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param InitVector Pointer to InitVector/InitCounter buffer
+ * @param IVSize Size of the InitVector/InitCounter
+ * @retval None
+ */
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
+{
+ uint32_t ivaddr = (uint32_t)InitVector;
+
+ switch(IVSize)
+ {
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
+ break;
+ /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ break;
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Process Data: Writes Input data in polling mode and read the output data
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input Pointer to the Input buffer
+ * @param Ilength Length of the Input buffer, must be a multiple of 16.
+ * @param Output Pointer to the returned buffer
+ * @param Timeout Timeout value
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ uint32_t i = 0U;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
+
+ for(i=0U; (i < Ilength); i+=16U)
+ {
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Process Data: Write Input data in polling mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input Pointer to the Input buffer
+ * @param Ilength Length of the Input buffer, must be a multiple of 8
+ * @param Output Pointer to the returned buffer
+ * @param Timeout Specify Timeout value
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ uint32_t i = 0U;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
+
+ for(i=0U; (i < Ilength); i+=8U)
+ {
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the DMA configuration and start the DMA transfer
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr address of the Input buffer
+ * @param Size Size of the Input buffer, must be a multiple of 16.
+ * @param outputaddr address of the Output buffer
+ * @retval None
+ */
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4U);
+
+ /* Enable In DMA request */
+ hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
+
+ /* Enable the DMA Out DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4U);
+
+ /* Enable Out DMA request */
+ hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
+
+}
+
+/**
+ * @brief Sets the CRYP peripheral in DES ECB mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
+
+ /* Set the key */
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4U));
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
+
+/**
+ * @brief Sets the CRYP peripheral in DES CBC mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
+
+ /* Set the key */
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4U));
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
+
+/**
+ * @brief Sets the CRYP peripheral in TDES ECB mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
+
+/**
+ * @brief Sets the CRYP peripheral in TDES CBC mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Direction Encryption or decryption
+ * @retval None
+ */
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the CRYP peripheral in AES CBC mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+}
+
+/**
+ * @}
+ */
+
+ /* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRYP_Exported_Functions
+ * @{
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRYP according to the specified parameters
+ in the CRYP_InitTypeDef and creates the associated handle
+ (+) DeInitialize the CRYP peripheral
+ (+) Initialize the CRYP MSP
+ (+) DeInitialize CRYP MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRYP according to the specified
+ * parameters in the CRYP_InitTypeDef and creates the associated handle.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+ assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+
+ if(hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CRYP_MspInit(hcryp);
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the key size and data type*/
+ CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = HAL_CRYP_PHASE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CRYP peripheral.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = HAL_CRYP_PHASE_READY;
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+
+ /* Disable the CRYP Peripheral Clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_CRYP_MspDeInit(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP MSP.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes CRYP MSP.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
+ * @brief processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### AES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Encrypt plaintext using AES-128/192/256 using chaining modes
+ (+) Decrypt cyphertext using AES-128/192/256 using chaining modes
+ [..] Three processing functions are available:
+ (+) Polling mode
+ (+) Interrupt mode
+ (+) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES ECB decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES CBC decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CTR mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Locked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CBC mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Locked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CTR mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t tickstart = 0U;
+
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES ECB decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES CBC decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CTR mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES ECB decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES Key mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the ALGOMODE bits*/
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+
+ /* Set the CRYP peripheral in AES CBC decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CTR mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions
+ * @brief processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### DES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Encrypt plaintext using DES using ECB or CBC chaining modes
+ (+) Decrypt cyphertext using ECB or CBC chaining modes
+ [..] Three processing functions are available:
+ (+) Polling mode
+ (+) Interrupt mode
+ (+) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRYP peripheral in DES ECB encryption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES ECB encryption mode */
+ CRYP_SetDESECBMode(hcryp, 0U);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES ECB decryption mode */
+ CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES CBC encryption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES CBC encryption mode */
+ CRYP_SetDESCBCMode(hcryp, 0U);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES CBC decryption mode */
+ CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES ECB encryption mode */
+ CRYP_SetDESECBMode(hcryp, 0U);
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+
+ hcryp->pCrypInBuffPtr += 8U;
+ hcryp->CrypInCount -= 8U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+
+ hcryp->pCrypOutBuffPtr += 8U;
+ hcryp->CrypOutCount -= 8U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ /* Disable IT */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES CBC encryption mode */
+ CRYP_SetDESCBCMode(hcryp, 0U);
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+
+ hcryp->pCrypInBuffPtr += 8U;
+ hcryp->CrypInCount -= 8U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+
+ hcryp->pCrypOutBuffPtr += 8U;
+ hcryp->CrypOutCount -= 8U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ /* Disable IT */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES ECB decryption mode */
+ CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+
+ hcryp->pCrypInBuffPtr += 8U;
+ hcryp->CrypInCount -= 8U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+
+ hcryp->pCrypOutBuffPtr += 8U;
+ hcryp->CrypOutCount -= 8U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ /* Disable IT */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES CBC decryption mode */
+ CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+
+ hcryp->pCrypInBuffPtr += 8U;
+ hcryp->CrypInCount -= 8U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+
+ hcryp->pCrypOutBuffPtr += 8U;
+ hcryp->CrypOutCount -= 8U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ /* Disable IT */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES ECB encryption mode */
+ CRYP_SetDESECBMode(hcryp, 0U);
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES CBC encryption mode */
+ CRYP_SetDESCBCMode(hcryp, 0U);
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES ECB decryption mode */
+ CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in DES CBC decryption mode */
+ CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions
+ * @brief processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### TDES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
+ (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
+ [..] Three processing functions are available:
+ (+) Polling mode
+ (+) Interrupt mode
+ (+) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES ECB encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES ECB encryption mode */
+ CRYP_SetTDESECBMode(hcryp, 0U);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES ECB decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES ECB decryption mode */
+ CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write Cypher Data and Get Plain Data */
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES CBC encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES CBC encryption mode */
+ CRYP_SetTDESCBCMode(hcryp, 0U);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES CBC decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES CBC decryption mode */
+ CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write Cypher Data and Get Plain Data */
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES ECB encryption mode */
+ CRYP_SetTDESECBMode(hcryp, 0U);
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+
+ hcryp->pCrypInBuffPtr += 8U;
+ hcryp->CrypInCount -= 8U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+
+ hcryp->pCrypOutBuffPtr += 8U;
+ hcryp->CrypOutCount -= 8U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ /* Disable IT */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call the Output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES CBC encryption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES CBC encryption mode */
+ CRYP_SetTDESCBCMode(hcryp, 0U);
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+
+ hcryp->pCrypInBuffPtr += 8U;
+ hcryp->CrypInCount -= 8U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+
+ hcryp->pCrypOutBuffPtr += 8U;
+ hcryp->CrypOutCount -= 8U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES ECB decryption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES ECB decryption mode */
+ CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+
+ hcryp->pCrypInBuffPtr += 8U;
+ hcryp->CrypInCount -= 8U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+
+ hcryp->pCrypOutBuffPtr += 8U;
+ hcryp->CrypOutCount -= 8U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES CBC decryption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES CBC decryption mode */
+ CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+
+ hcryp->pCrypInBuffPtr += 8U;
+ hcryp->CrypInCount -= 8U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+
+ hcryp->pCrypOutBuffPtr += 8U;
+ hcryp->CrypOutCount -= 8U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES ECB encryption mode */
+ CRYP_SetTDESECBMode(hcryp, 0U);
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES CBC encryption mode */
+ CRYP_SetTDESCBCMode(hcryp, 0U);
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES ECB decryption mode */
+ CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 8
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set CRYP peripheral in TDES CBC decryption mode */
+ CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions
+ * @brief DMA callback functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### DMA callback functions #####
+ ==============================================================================
+ [..] This section provides DMA callback functions:
+ (+) DMA Input data transfer complete
+ (+) DMA Output data transfer complete
+ (+) DMA error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Input FIFO transfer completed callbacks.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_InCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Output FIFO transfer completed callbacks.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_OutCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CRYP error callbacks.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management
+ * @brief CRYP IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### CRYP IRQ handler management #####
+ ==============================================================================
+[..] This section provides CRYP IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles CRYP interrupt request.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+ switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
+ {
+ case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
+ HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
+ HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
+ HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
+ HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
+ HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
+ HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
+ HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
+ HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
+ HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
+ HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
+ HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
+ HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
+ HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
+ HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the CRYP state.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL state
+ */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+{
+ return hcryp->State;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* CRYP */
+
+#if defined (AES)
+
+/** @defgroup AES AES
+ * @brief AES HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions --------------------------------------------------------*/
+
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
+ * @{
+ */
+
+static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+ * @{
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and deinitialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRYP according to the specified parameters
+ in the CRYP_InitTypeDef and creates the associated handle
+ (+) DeInitialize the CRYP peripheral
+ (+) Initialize the CRYP MSP (MCU Specific Package)
+ (+) De-Initialize the CRYP MSP
+
+ [..]
+ (@) Specific care must be taken to format the key and the Initialization Vector IV!
+
+ [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
+ b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
+ (+) as a sequence of words where the MSB word comes first (occupies the
+ lowest memory address)
+ (+) where each word is byte-swapped:
+ (++) address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120
+ (++) address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88
+ (++) address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56
+ (++) address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24
+ [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
+ The 4 32-bit words that make the key must be stored as follows in MCU memory:
+ (+) address n+0 : 0x B12 B13 B14 B15
+ (+) address n+4 : 0x B8 B9 B10 B11
+ (+) address n+8 : 0x B4 B5 B6 B7
+ (+) address n+C : 0x B0 B1 B2 B3
+ [..] which leads to the expected setting
+ (+) AES_KEYR3 = 0x B15 B14 B13 B12
+ (+) AES_KEYR2 = 0x B11 B10 B9 B8
+ (+) AES_KEYR1 = 0x B7 B6 B5 B4
+ (+) AES_KEYR0 = 0x B3 B2 B1 B0
+
+ [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
+ The 8 32-bit words that make the key must be stored as follows in MCU memory:
+ (+) address n+00 : 0x B28 B29 B30 B31
+ (+) address n+04 : 0x B24 B25 B26 B27
+ (+) address n+08 : 0x B20 B21 B22 B23
+ (+) address n+0C : 0x B16 B17 B18 B19
+ (+) address n+10 : 0x B12 B13 B14 B15
+ (+) address n+14 : 0x B8 B9 B10 B11
+ (+) address n+18 : 0x B4 B5 B6 B7
+ (+) address n+1C : 0x B0 B1 B2 B3
+ [..] which leads to the expected setting
+ (+) AES_KEYR7 = 0x B31 B30 B29 B28
+ (+) AES_KEYR6 = 0x B27 B26 B25 B24
+ (+) AES_KEYR5 = 0x B23 B22 B21 B20
+ (+) AES_KEYR4 = 0x B19 B18 B17 B16
+ (+) AES_KEYR3 = 0x B15 B14 B13 B12
+ (+) AES_KEYR2 = 0x B11 B10 B9 B8
+ (+) AES_KEYR1 = 0x B7 B6 B5 B4
+ (+) AES_KEYR0 = 0x B3 B2 B1 B0
+
+ [..] Initialization Vector IV (4 32-bit words) format must follow the same as
+ that of a 128-bit long key.
+
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CRYP according to the specified
+ * parameters in the CRYP_InitTypeDef and initialize the associated handle.
+ * @note Specific care must be taken to format the key and the Initialization Vector IV
+ * stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations
+ * hereabove.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the instance */
+ assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
+
+ /* Check the parameters */
+ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+ assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+ assert_param(IS_CRYP_ALGOMODE(hcryp->Init.OperatingMode));
+ /* ChainingMode parameter is irrelevant when mode is set to Key derivation */
+ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+ {
+ assert_param(IS_CRYP_CHAINMODE(hcryp->Init.ChainingMode));
+ }
+ assert_param(IS_CRYP_WRITE(hcryp->Init.KeyWriteFlag));
+
+ /*========================================================*/
+ /* Check the proper operating/chaining modes combinations */
+ /*========================================================*/
+ /* Check the proper chaining when the operating mode is key derivation and decryption */
+#if defined(AES_CR_NPBLB)
+ if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
+ ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \
+ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \
+ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)))
+#else
+ if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
+ ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \
+ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \
+ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)))
+#endif
+ {
+ return HAL_ERROR;
+ }
+ /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */
+#if defined(AES_CR_NPBLB)
+ if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+ && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))
+#else
+ if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+ && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
+#endif
+ {
+ return HAL_ERROR;
+ }
+
+
+ /*================*/
+ /* Initialization */
+ /*================*/
+ /* Initialization start */
+ if(hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_CRYP_MspInit(hcryp);
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CRYP_DISABLE();
+
+ /*=============================================================*/
+ /* AES initialization common to all operating modes */
+ /*=============================================================*/
+ /* Set the Key size selection */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize);
+
+ /* Set the default CRYP phase when this parameter is not used.
+ Phase is updated below in case of GCM/GMAC/CMAC(/CCM) setting. */
+ hcryp->Phase = HAL_CRYP_PHASE_NOT_USED;
+
+
+
+ /*=============================================================*/
+ /* Carry on the initialization based on the AES operating mode */
+ /*=============================================================*/
+ /* Key derivation */
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_ALGOMODE_KEYDERIVATION);
+
+ /* Configure the Key registers */
+ if (CRYP_SetKey(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ /* Encryption / Decryption (with or without key derivation) / authentication */
+ {
+ /* Set data type, operating and chaining modes.
+ In case of GCM or GMAC, data type is forced to 0b00 */
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
+ }
+ else
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
+ }
+
+
+ /* Specify the encryption/decryption phase in case of Galois counter mode (GCM),
+ Galois message authentication code (GMAC), cipher message authentication code (CMAC)
+ or Counter with Cipher Mode (CCM) when applicable */
+#if defined(AES_CR_NPBLB)
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))
+#else
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
+#endif
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase);
+ hcryp->Phase = HAL_CRYP_PHASE_START;
+ }
+
+
+ /* Configure the Key registers if no need to bypass this step */
+ if (hcryp->Init.KeyWriteFlag == CRYP_KEY_WRITE_ENABLE)
+ {
+ if (CRYP_SetKey(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* If applicable, configure the Initialization Vector */
+ if (hcryp->Init.ChainingMode != CRYP_CHAINMODE_AES_ECB)
+ {
+ if (CRYP_SetInitVector(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+
+#if defined(AES_CR_NPBLB)
+ /* Clear NPBLB field */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
+#endif
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+
+ /* Reset ErrorCode field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
+ /* Reset Mode suspension request */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Enable the Peripheral */
+ __HAL_CRYP_ENABLE();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the CRYP peripheral.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = HAL_CRYP_PHASE_READY;
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+
+ /* Disable the CRYP Peripheral Clock */
+ __HAL_CRYP_DISABLE();
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_CRYP_MspDeInit(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the CRYP MSP.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize CRYP MSP.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
+ * @brief Processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### AES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Encrypt plaintext using AES algorithm in different chaining modes
+ (+) Decrypt cyphertext using AES algorithm in different chaining modes
+ [..] Three processing functions are available:
+ (+) Polling mode
+ (+) Interrupt mode
+ (+) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
+}
+
+
+/**
+ * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
+}
+
+
+/**
+ * @brief Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Specify Timeout value
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
+}
+
+/**
+ * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation,
+ * the decyphered data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Specify Timeout value
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
+}
+
+/**
+ * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation,
+ * the decyphered data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Specify Timeout value
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
+}
+
+/**
+ * @brief Decrypt pCypherData in AES CTR decryption mode,
+ * the decyphered data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Specify Timeout value
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
+}
+
+/**
+ * @brief Encrypt pPlainData in AES ECB encryption mode using Interrupt,
+ * the cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
+}
+
+/**
+ * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt,
+ * the cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
+}
+
+
+/**
+ * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt,
+ * the cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
+}
+
+/**
+ * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt,
+ * the decyphered data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer.
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+ * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt,
+ * the decyphered data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+ * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt,
+ * the decyphered data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+ * @brief Encrypt pPlainData in AES ECB encryption mode using DMA,
+ * the cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+ * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
+}
+
+
+
+/**
+ * @brief Encrypt pPlainData in AES CBC encryption mode using DMA,
+ * the cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+ * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
+}
+
+/**
+ * @brief Encrypt pPlainData in AES CTR encryption mode using DMA,
+ * the cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pCypherData Pointer to the cyphertext buffer.
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+ * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
+}
+
+/**
+ * @brief Decrypt pCypherData in AES ECB decryption mode using DMA,
+ * the decyphered data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+ * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+ * @brief Decrypt pCypherData in AES CBC decryption mode using DMA,
+ * the decyphered data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+ * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
+}
+
+/**
+ * @brief Decrypt pCypherData in AES CTR decryption mode using DMA,
+ * the decyphered data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
+ * @param pPlainData Pointer to the plaintext buffer
+ * @note This API is provided only to maintain compatibility with legacy software. Users should directly
+ * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
+ * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ /* Re-initialize AES IP with proper parameters */
+ if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
+ hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
+ hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+ if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group3 Callback functions
+ * @brief Callback functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..] This section provides Interruption and DMA callback functions:
+ (+) DMA Input data transfer complete
+ (+) DMA Output data transfer complete
+ (+) DMA or Interrupt error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief CRYP error callback.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input DMA transfer complete callback.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_InCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Output DMA transfer complete callback.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_OutCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
+ * @brief AES IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### AES IRQ handler management #####
+ ==============================================================================
+[..] This section provides AES IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle AES interrupt request.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check if error occurred */
+ if (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_ERRIE) != RESET)
+ {
+ /* If Write Error occurred */
+ if (__HAL_CRYP_GET_FLAG(CRYP_IT_WRERR) != RESET)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_WRITE_ERROR;
+ hcryp->State = HAL_CRYP_STATE_ERROR;
+ }
+ /* If Read Error occurred */
+ if (__HAL_CRYP_GET_FLAG(CRYP_IT_RDERR) != RESET)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_READ_ERROR;
+ hcryp->State = HAL_CRYP_STATE_ERROR;
+ }
+
+ /* If an error has been reported */
+ if (hcryp->State == HAL_CRYP_STATE_ERROR)
+ {
+ /* Disable Error and Computation Complete Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Clear all Interrupt flags */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR|CRYP_CCF_CLEAR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ HAL_CRYP_ErrorCallback(hcryp);
+
+ return;
+ }
+ }
+
+ /* Check if computation complete interrupt is enabled
+ and if the computation complete flag is raised */
+ if((__HAL_CRYP_GET_FLAG(CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_CCFIE) != RESET))
+ {
+#if defined(AES_CR_NPBLB)
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))
+#else
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
+#endif
+ {
+ /* To ensure proper suspension requests management, CCF flag
+ is reset in CRYP_AES_Auth_IT() according to the current
+ phase under handling */
+ CRYP_AES_Auth_IT(hcryp);
+ }
+ else
+ {
+ /* Clear Computation Complete Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ CRYP_AES_IT(hcryp);
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CRYP handle state.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL state
+ */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+{
+ /* Return CRYP handle state */
+ return hcryp->State;
+}
+
+/**
+ * @brief Return the CRYP peripheral error.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @note The returned error is a bit-map combination of possible errors
+ * @retval Error bit-map
+ */
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
+{
+ return hcryp->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Private_Functions
+ * @{
+ */
+
+
+/**
+ * @brief Write the Key in KeyRx registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t keyaddr = 0x0U;
+
+ if ((uint32_t)(hcryp->Init.pKey == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+
+ keyaddr = (uint32_t)(hcryp->Init.pKey);
+
+ if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+ {
+ hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ }
+
+ hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write the InitVector/InitCounter in IVRx registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t ivaddr = 0x0U;
+
+#if !defined(AES_CR_NPBLB)
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+ {
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+ }
+ else
+#endif
+ {
+ if (hcryp->Init.pInitVect == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ ivaddr = (uint32_t)(hcryp->Init.pInitVect);
+
+ hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
+ }
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief Handle CRYP block input/output data handling under interruption.
+ * @note The function is called under interruption only, once
+ * interruptions have been enabled by HAL_CRYPEx_AES_IT().
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t inputaddr = 0U;
+ uint32_t outputaddr = 0U;
+
+ if(hcryp->State == HAL_CRYP_STATE_BUSY)
+ {
+ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+ {
+ /* Get the output data address */
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+
+ /* Read the last available output block from the Data Output Register */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+
+ }
+ else
+ {
+ /* Read the derived key from the Key registers */
+ if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+ {
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
+ outputaddr+=4U;
+ }
+
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
+ }
+
+ /* In case of ciphering or deciphering, check if all output text has been retrieved;
+ In case of key derivation, stop right there */
+ if ((hcryp->CrypOutCount == 0U) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION))
+ {
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Call computation complete callback */
+ HAL_CRYPEx_ComputationCpltCallback(hcryp);
+
+ return HAL_OK;
+ }
+ /* If suspension flag has been raised, suspend processing */
+ else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+ {
+ /* reset ModeSuspend */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+ else /* Process the rest of input data */
+ {
+ /* Get the Intput data address */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Increment/decrement instance pointer/counter */
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+
+ /* Write the next input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* AES */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1160 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cryp.h
+ * @author MCD Application Team
+ * @brief Header file of CRYP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRYP_H
+#define __STM32F4xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+#if defined(CRYP)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+ * @{
+ */
+
+/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref CRYP_Data_Type */
+
+ uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
+ This parameter can be a value of @ref CRYP_Key_Size */
+
+ uint8_t* pKey; /*!< The key used for encryption/decryption */
+
+ uint8_t* pInitVect; /*!< The initialization vector used also as initialization
+ counter in CTR mode */
+
+ uint8_t IVSize; /*!< The size of initialization vector.
+ This parameter (called nonce size in CCM) is used only
+ in AES-128/192/256 encryption/decryption CCM mode */
+
+ uint8_t TagSize; /*!< The size of returned authentication TAG.
+ This parameter is used only in AES-128/192/256
+ encryption/decryption CCM mode */
+
+ uint8_t* Header; /*!< The header used in GCM and CCM modes */
+
+ uint32_t HeaderSize; /*!< The size of header buffer in bytes */
+
+ uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
+ This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
+}CRYP_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
+ * @{
+ */
+
+
+typedef enum
+{
+ HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
+ HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
+ HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */
+ HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */
+ HAL_CRYP_STATE_ERROR = 0x04U /*!< CRYP error state */
+}HAL_CRYP_STATETypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
+ * @{
+ */
+
+
+typedef enum
+{
+ HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */
+ HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */
+ HAL_CRYP_PHASE_FINAL = 0x03U /*!< CRYP peripheral is in final phase
+ This is relevant only with CCM and GCM modes */
+}HAL_PhaseTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
+ * @{
+ */
+
+typedef struct
+{
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+
+ CRYP_InitTypeDef Init; /*!< CRYP required parameters */
+
+ uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ __IO uint16_t CrypInCount; /*!< Counter of inputed data */
+
+ __IO uint16_t CrypOutCount; /*!< Counter of output data */
+
+ HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
+
+ HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+}CRYP_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+ * @{
+ */
+
+/** @defgroup CRYP_Key_Size CRYP Key Size
+ * @{
+ */
+#define CRYP_KEYSIZE_128B 0x00000000U
+#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
+#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Data_Type CRYP Data Type
+ * @{
+ */
+#define CRYP_DATATYPE_32B 0x00000000U
+#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
+ * @{
+ */
+#define CRYP_CR_ALGOMODE_DIRECTION 0x0008003CU
+#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT 0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT 0x00000004U
+#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT 0x00000008U
+#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT 0x0000000CU
+#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT 0x00000010U
+#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT 0x00000014U
+#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT 0x00000018U
+#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT 0x0000001CU
+#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT 0x00000020U
+#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT 0x00000024U
+#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT 0x00000028U
+#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT 0x0000002CU
+#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT 0x00000030U
+#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT 0x00000034U
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
+ * @{
+ */
+#define CRYP_IT_INI ((uint32_t)CRYP_IMSCR_INIM) /*!< Input FIFO Interrupt */
+#define CRYP_IT_OUTI ((uint32_t)CRYP_IMSCR_OUTIM) /*!< Output FIFO Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
+ * @{
+ */
+#define CRYP_FLAG_BUSY 0x00000010U /*!< The CRYP core is currently
+ processing a block of data
+ or a key preparation (for
+ AES decryption). */
+#define CRYP_FLAG_IFEM 0x00000001U /*!< Input FIFO is empty */
+#define CRYP_FLAG_IFNF 0x00000002U /*!< Input FIFO is not Full */
+#define CRYP_FLAG_OFNE 0x00000004U /*!< Output FIFO is not empty */
+#define CRYP_FLAG_OFFU 0x00000008U /*!< Output FIFO is Full */
+#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw
+ interrupt status */
+#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw
+ interrupt status */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRYP handle state
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @retval None
+ */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
+/**
+ * @brief Enable/Disable the CRYP peripheral.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
+
+/**
+ * @brief Flush the data FIFO.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @retval None
+ */
+#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
+
+/**
+ * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param MODE The algorithm mode.
+ * @retval None
+ */
+#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
+
+/** @brief Check whether the specified CRYP flag is set or not.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+ * or a key preparation (for AES decryption).
+ * @arg CRYP_FLAG_IFEM: Input FIFO is empty
+ * @arg CRYP_FLAG_IFNF: Input FIFO is not full
+ * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
+ * @arg CRYP_FLAG_OFNE: Output FIFO is not empty
+ * @arg CRYP_FLAG_OFFU: Output FIFO is full
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24U)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+
+/** @brief Check whether the specified CRYP interrupt is set or not.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ specifies the interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
+ * @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Enable the CRYP interrupt.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ CRYP Interrupt.
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the CRYP interrupt.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ CRYP interrupt.
+ * @retval None
+ */
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Include CRYP HAL Extension module */
+#include "stm32f4xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group2
+ * @{
+ */
+/* AES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group3
+ * @{
+ */
+/* DES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* DES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* DES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group4
+ * @{
+ */
+/* TDES encryption/decryption using polling **********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* TDES encryption/decryption using interrupt ********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* TDES encryption/decryption using DMA **************************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group5
+ * @{
+ */
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group6
+ * @{
+ */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group7
+ * @{
+ */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRYP_Private_Types CRYP Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Variables CRYP Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Constants CRYP Private Constants
+ * @{
+ */
+#define CRYP_FLAG_MASK 0x0000001FU
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros CRYP Private Macros
+ * @{
+ */
+
+#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
+ ((__KEYSIZE__) == CRYP_KEYSIZE_192B) || \
+ ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
+
+
+#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_8B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_1B))
+
+
+ /**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* CRYP */
+
+#if defined (AES)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+ * @{
+ */
+
+/**
+ * @brief CRYP Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref CRYP_Data_Type */
+
+ uint32_t KeySize; /*!< 128 or 256-bit key length.
+ This parameter can be a value of @ref CRYP_Key_Size */
+
+ uint32_t OperatingMode; /*!< AES operating mode.
+ This parameter can be a value of @ref CRYP_AES_OperatingMode */
+
+ uint32_t ChainingMode; /*!< AES chaining mode.
+ This parameter can be a value of @ref CRYP_AES_ChainingMode */
+
+ uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption.
+ This parameter can be a value of @ref CRYP_Key_Write */
+
+ uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM),
+ Galois Message Authentication Code (GMAC) or Cipher Message
+ Authentication Code (CMAC) or Counter with Cipher Mode (CCM) when
+ the latter is applicable.
+ This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */
+
+ uint8_t* pKey; /*!< Encryption/Decryption Key */
+
+ uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC,
+ (and CCM when applicable) modes */
+
+ uint8_t* Header; /*!< Header used in GCM/GMAC, CMAC (and CCM when applicable) modes */
+
+ uint64_t HeaderSize; /*!< Header size in bytes */
+
+}CRYP_InitTypeDef;
+
+/**
+ * @brief HAL CRYP State structures definition
+ */
+typedef enum
+{
+ HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
+ HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
+ HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */
+ HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */
+ HAL_CRYP_STATE_ERROR = 0x04U, /*!< CRYP error state */
+ HAL_CRYP_STATE_SUSPENDED = 0x05U /*!< CRYP suspended */
+}HAL_CRYP_STATETypeDef;
+
+/**
+ * @brief HAL CRYP phase structures definition
+ */
+typedef enum
+{
+ HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */
+ HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */
+ HAL_CRYP_PHASE_START = 0x03U, /*!< CRYP peripheral has been initialized but
+ GCM/GMAC/CMAC(/CCM) initialization phase has not started */
+ HAL_CRYP_PHASE_INIT_OVER = 0x04U, /*!< GCM/GMAC/CMAC(/CCM) init phase has been carried out */
+ HAL_CRYP_PHASE_HEADER_OVER = 0x05U, /*!< GCM/GMAC/CMAC(/CCM) header phase has been carried out */
+ HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06U, /*!< GCM(/CCM) payload phase has been carried out */
+ HAL_CRYP_PHASE_FINAL_OVER = 0x07U, /*!< GCM/GMAC/CMAC(/CCM) final phase has been carried out */
+ HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08U, /*!< GCM/GMAC/CMAC(/CCM) header phase has been suspended */
+ HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09U, /*!< GCM(/CCM) payload phase has been suspended */
+ HAL_CRYP_PHASE_NOT_USED = 0x0AU /*!< Phase is irrelevant to the current chaining mode */
+}HAL_PhaseTypeDef;
+
+/**
+ * @brief HAL CRYP mode suspend definitions
+ */
+typedef enum
+{
+ HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP peripheral suspension not requested */
+ HAL_CRYP_SUSPEND = 0x01U /*!< CRYP peripheral suspension requested */
+}HAL_SuspendTypeDef;
+
+
+/**
+ * @brief HAL CRYP Error Codes definition
+ */
+#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_CRYP_WRITE_ERROR 0x00000001U /*!< Write error */
+#define HAL_CRYP_READ_ERROR 0x00000002U /*!< Read error */
+#define HAL_CRYP_DMA_ERROR 0x00000004U /*!< DMA error */
+#define HAL_CRYP_BUSY_ERROR 0x00000008U /*!< Busy flag error */
+
+/**
+ * @brief CRYP handle Structure definition
+ */
+typedef struct
+{
+ AES_TypeDef *Instance; /*!< Register base address */
+
+ CRYP_InitTypeDef Init; /*!< CRYP initialization parameters */
+
+ uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */
+
+ uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */
+
+ uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining
+ number of bytes to process */
+
+ uint32_t CrypOutCount; /*!< Output data size in bytes */
+
+ HAL_PhaseTypeDef Phase; /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC
+ (or CCM when applicable) modes.
+ Indicates the last phase carried out to ease
+ phase transitions */
+
+ DMA_HandleTypeDef *hdmain; /*!< CRYP peripheral Input DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP peripheral Output DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+
+ __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
+
+ HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
+}CRYP_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+ * @{
+ */
+
+/** @defgroup CRYP_Key_Size Key size selection
+ * @{
+ */
+#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Data_Type AES Data Type selection
+ * @{
+ */
+#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
+#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
+#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
+#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
+/**
+ * @}
+ */
+
+ /** @defgroup CRYP_AES_State AES Enable state
+ * @{
+ */
+#define CRYP_AES_DISABLE 0x00000000U /*!< Disable AES */
+#define CRYP_AES_ENABLE AES_CR_EN /*!< Enable AES */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_AES_OperatingMode AES operating mode
+ * @{
+ */
+#define CRYP_ALGOMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
+#define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */
+#define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
+#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption */
+#define CRYP_ALGOMODE_TAG_GENERATION 0x00000000U /*!< GMAC or CMAC authentication tag generation */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_AES_ChainingMode AES chaining mode
+ * @{
+ */
+#define CRYP_CHAINMODE_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
+#define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
+#define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
+#define CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
+#define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2 /*!< Cipher message authentication code */
+#if defined(AES_CR_NPBLB)
+#define CRYP_CHAINMODE_AES_CCM_CMAC AES_CR_CHMOD_2 /*!< Counter with Cipher Mode - Cipher message authentication code */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Key_Write AES decryption key write-up flag
+ * @{
+ */
+#define CRYP_KEY_WRITE_ENABLE 0x00000000U /*!< Enable decryption key writing */
+#define CRYP_KEY_WRITE_DISABLE 0x00000001U /*!< Disable decryption key writing */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_DMAIN DMA Input phase management enable state
+ * @{
+ */
+#define CRYP_DMAIN_DISABLE 0x00000000U /*!< Disable DMA Input phase management */
+#define CRYP_DMAIN_ENABLE AES_CR_DMAINEN /*!< Enable DMA Input phase management */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_DMAOUT DMA Output phase management enable state
+ * @{
+ */
+#define CRYP_DMAOUT_DISABLE 0x00000000U /*!< Disable DMA Output phase management */
+#define CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN /*!< Enable DMA Output phase management */
+/**
+ * @}
+ */
+
+
+/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection
+ * @{
+ */
+#define CRYP_GCM_INIT_PHASE 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC or (CCM/)CMAC header phase */
+#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC or (CCM/)CMAC final phase */
+/* Definitions duplication for code readibility's sake:
+ supported or not supported chain modes are not specified for each phase */
+#define CRYP_INIT_PHASE 0x00000000U /*!< Init phase */
+#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */
+#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */
+#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Flags AES status flags
+ * @{
+ */
+
+#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
+#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
+#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
+#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Clear_Flags AES clearing flags
+ * @{
+ */
+
+#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
+#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
+/**
+ * @}
+ */
+
+/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits
+ * @{
+ */
+#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
+#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Interrupts_Flags AES Interrupts flags
+ * @{
+ */
+#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
+#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
+#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRYP handle state.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @retval None
+ */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
+/**
+ * @brief Enable the CRYP AES peripheral.
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN)
+
+/**
+ * @brief Disable the CRYP AES peripheral.
+ * @retval None
+ */
+#define __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN)
+
+/**
+ * @brief Set the algorithm operating mode.
+ * @param __OPERATING_MODE__ specifies the operating mode
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
+ * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation
+ * @arg @ref CRYP_ALGOMODE_DECRYPT decryption
+ * @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption
+ * @retval None
+ */
+#define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))
+
+
+/**
+ * @brief Set the algorithm chaining mode.
+ * @param __CHAINING_MODE__ specifies the chaining mode
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
+ * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
+ * @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
+ * @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code
+ * @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)
+ * @retval None
+ */
+#define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
+
+
+
+/** @brief Check whether the specified CRYP status flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief Clear the CRYP pending status flag.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
+ * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+ * @retval None
+ */
+#define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
+
+
+
+/** @brief Check whether the specified CRYP interrupt source is enabled or not.
+ * @param __INTERRUPT__ CRYP interrupt source to check
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @retval State of interruption (TRUE or FALSE).
+ */
+#define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+
+/** @brief Check whether the specified CRYP interrupt is set or not.
+ * @param __INTERRUPT__ specifies the interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
+ * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+
+
+/** @brief Clear the CRYP pending interrupt.
+ * @param __INTERRUPT__ specifies the IT to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
+ * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+ * @retval None
+ */
+#define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
+
+
+/**
+ * @brief Enable the CRYP interrupt.
+ * @param __INTERRUPT__ CRYP Interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
+
+
+/**
+ * @brief Disable the CRYP interrupt.
+ * @param __INTERRUPT__ CRYP Interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @retval None
+ */
+#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Macros CRYP Private Macros
+ * @{
+ */
+
+/**
+ * @brief Verify the key size length.
+ * @param __KEYSIZE__ Ciphering/deciphering algorithm key size.
+ * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
+ */
+#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
+ ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
+
+/**
+ * @brief Verify the input data type.
+ * @param __DATATYPE__ Ciphering/deciphering algorithm input data type.
+ * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+ */
+#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_8B) || \
+ ((__DATATYPE__) == CRYP_DATATYPE_1B))
+
+/**
+ * @brief Verify the CRYP AES IP running mode.
+ * @param __MODE__ CRYP AES IP running mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
+ ((__MODE__) == CRYP_AES_ENABLE))
+
+/**
+ * @brief Verify the selected CRYP algorithm.
+ * @param __ALGOMODE__ Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
+ * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
+ */
+#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \
+ ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION) || \
+ ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT) || \
+ ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
+ ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))
+
+/**
+ * @brief Verify the selected CRYP chaining algorithm.
+ * @param __CHAINMODE__ Selected CRYP chaining algorithm.
+ * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
+ */
+#if defined(AES_CR_NPBLB)
+#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
+ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
+ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
+ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
+ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM_CMAC))
+#else
+#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
+ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
+ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
+ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
+ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))
+#endif
+
+/**
+ * @brief Verify the deciphering key write option.
+ * @param __WRITE__ deciphering key write option.
+ * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
+ */
+#define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \
+ ((__WRITE__) == CRYP_KEY_WRITE_DISABLE))
+
+/**
+ * @brief Verify the CRYP input data DMA mode.
+ * @param __MODE__ CRYP input data DMA mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
+ ((__MODE__) == CRYP_DMAIN_ENABLE))
+
+/**
+ * @brief Verify the CRYP output data DMA mode.
+ * @param __MODE__ CRYP output data DMA mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
+ ((__MODE__) == CRYP_DMAOUT_ENABLE))
+
+/**
+ * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
+ * @param __PHASE__ CRYP AES ciphering/deciphering/authentication algorithm phase.
+ * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
+ */
+#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \
+ ((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \
+ ((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE) || \
+ ((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))
+
+/**
+ * @}
+ */
+
+/* Include CRYP HAL Extended module */
+#include "stm32f4xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+
+/* MSP initialization/de-initialization functions ****************************/
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions
+ * @{
+ */
+
+/* AES encryption/decryption processing functions ****************************/
+
+/* AES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions
+ * @{
+ */
+/* CallBack functions ********************************************************/
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
+ * @{
+ */
+
+/* AES interrupt handling function *******************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions
+ * @{
+ */
+
+/* Peripheral State functions ************************************************/
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#endif /* AES */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRYP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,5988 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cryp_ex.c
+ * @author MCD Application Team
+ * @brief Extended CRYP HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities of CRYP extension peripheral:
+ * + Extended AES processing functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The CRYP Extension HAL driver can be used as follows:
+ (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
+ (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
+ (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
+ (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++) Configure and enable two DMA streams one for managing data transfer from
+ memory to peripheral (input stream) and another stream for managing data
+ transfer from peripheral to memory (output stream)
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the two DMA Streams. The output stream should have higher
+ priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+ (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
+ (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
+ (##) The encryption/decryption key. Its size depends on the algorithm
+ used for encryption/decryption
+ (##) The initialization vector (counter). It is not used ECB mode.
+ (#)Three processing (encryption/decryption) functions are available:
+ (##) Polling mode: encryption and decryption APIs are blocking functions
+ i.e. they process the data and wait till the processing is finished
+ e.g. HAL_CRYPEx_AESGCM_Encrypt()
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+ i.e. they process the data under interrupt
+ e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
+ (##) DMA mode: encryption and decryption APIs are not blocking functions
+ i.e. the data transfer is ensured by DMA
+ e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
+ (#)When the processing function is called at first time after HAL_CRYP_Init()
+ the CRYP peripheral is initialized and processes the buffer in input.
+ At second call, the processing function performs an append of the already
+ processed buffer.
+ When a new data block is to be processed, call HAL_CRYP_Init() then the
+ processing function.
+ (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
+ which provide authentication messages.
+ HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
+ authentication messages.
+ Call those functions after the processing ones (polling, interrupt or DMA).
+ e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
+ then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
+ -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
+ -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
+ (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
+ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRYPEx CRYPEx
+ * @brief CRYP Extension HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+#if defined(CRYP)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_define
+ * @{
+ */
+#define CRYPEx_TIMEOUT_VALUE 1U
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions_prototypes CRYP Private Functions Prototypes
+ * @{
+ */
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
+static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
+static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);
+static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);
+static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA CRYP Input Data process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+
+ /* Call input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP Output Data process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
+ in the DMACR register */
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hcryp->State= HAL_CRYP_STATE_READY;
+ HAL_CRYP_ErrorCallback(hcryp);
+}
+
+/**
+ * @brief Writes the Key in Key registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Key Pointer to Key buffer
+ * @param KeySize Size of Key
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
+{
+ uint32_t keyaddr = (uint32_t)Key;
+
+ switch(KeySize)
+ {
+ case CRYP_KEYSIZE_256B:
+ /* Key Initialisation */
+ hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Writes the InitVector/InitCounter in IV registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param InitVector Pointer to InitVector/InitCounter buffer
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
+{
+ uint32_t ivaddr = (uint32_t)InitVector;
+
+ hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
+}
+
+/**
+ * @brief Process Data: Writes Input data in polling mode and read the Output data.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input Pointer to the Input buffer.
+ * @param Ilength Length of the Input buffer, must be a multiple of 16
+ * @param Output Pointer to the returned buffer
+ * @param Timeout Timeout value
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ uint32_t i = 0U;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
+
+ for(i=0U; (i < Ilength); i+=16U)
+ {
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the Output block from the OUT FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the header phase
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input Pointer to the Input buffer.
+ * @param Ilength Length of the Input buffer, must be a multiple of 16
+ * @param Timeout Timeout value
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ uint32_t loopcounter = 0U;
+ uint32_t headeraddr = (uint32_t)Input;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Ilength);
+
+ /***************************** Header phase *********************************/
+ if(hcryp->Init.HeaderSize != 0U)
+ {
+ /* Select header phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ }
+
+ /* Wait until the complete message has been processed */
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the DMA configuration and start the DMA transfer.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr Address of the Input buffer
+ * @param Size Size of the Input buffer, must be a multiple of 16
+ * @param outputaddr Address of the Output buffer
+ * @retval None
+ */
+static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4U);
+
+ /* Enable In DMA request */
+ hcryp->Instance->DMACR = CRYP_DMACR_DIEN;
+
+ /* Enable the DMA Out DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4U);
+
+ /* Enable Out DMA request */
+ hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
+}
+
+/**
+ * @}
+ */
+
+/* Exported functions---------------------------------------------------------*/
+/** @addtogroup CRYPEx_Exported_Functions
+ * @{
+ */
+
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
+ * @brief Extended processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended AES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes
+ (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes
+ (+) Finish the processing. This function is available only for GCM and CCM
+ [..] Three processing methods are available:
+ (+) Polling mode
+ (+) Interrupt mode
+ (+) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CCM encryption mode then
+ * encrypt pPlainData. The cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ uint32_t headersize = hcryp->Init.HeaderSize;
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
+ uint32_t loopcounter = 0U;
+ uint32_t bufferidx = 0U;
+ uint8_t blockb0[16U] = {0};/* Block B0 */
+ uint8_t ctr[16U] = {0}; /* Counter */
+ uint32_t b0addr = (uint32_t)blockb0;
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /************************ Formatting the header block *********************/
+ if(headersize != 0U)
+ {
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+ if(headersize < 65280U)
+ {
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+ headersize += 2U;
+ }
+ else
+ {
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
+ headersize += 6U;
+ }
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+ for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
+ {
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+ }
+ /* Check if the header size is modulo 16 */
+ if ((headersize % 16U) != 0U)
+ {
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+ for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = 0U;
+ }
+ /* Set the header size to modulo 16 */
+ headersize = ((headersize/16U) + 1U) * 16U;
+ }
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */
+ headeraddr = (uint32_t)hcryp->Init.pScratch;
+ }
+ /*********************** Formatting the block B0 **************************/
+ if(headersize != 0U)
+ {
+ blockb0[0U] = 0x40U;
+ }
+ /* Flags byte */
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1U) & (uint8_t)0x07) << 3U);
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+
+ for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
+ }
+ for ( ; loopcounter < 13U; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = 0U;
+ }
+
+ blockb0[14U] = (Size >> 8U);
+ blockb0[15U] = (Size & 0xFFU);
+
+ /************************* Formatting the initial counter *****************/
+ /* Byte 0:
+ Bits 7 and 6 are reserved and shall be set to 0
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
+ are distinct from B0
+ Bits 0, 1, and 2 contain the same encoding of q as in B0
+ */
+ ctr[0U] = blockb0[0U] & 0x07U;
+ /* byte 1 to NonceSize is the IV (Nonce) */
+ for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
+ {
+ ctr[loopcounter] = blockb0[loopcounter];
+ }
+ /* Set the LSB to 1 */
+ ctr[15U] |= 0x01U;
+
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CCM mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
+
+ /* Select init phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ b0addr = (uint32_t)blockb0;
+ /* Write the blockb0 block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /***************************** Header phase *******************************/
+ if(headersize != 0U)
+ {
+ /* Select header phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+ {
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Write the header block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Save formatted counter into the scratch buffer pScratch */
+ for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+ }
+ /* Reset bit 0 */
+ hcryp->Init.pScratch[15U] &= 0xFEU;
+
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES GCM encryption mode then
+ * encrypt pPlainData. The cypher data are available in pCypherData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES GCM mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set the header phase */
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES GCM decryption mode then
+ * decrypted pCypherData. The cypher data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the cyphertext buffer, must be a multiple of 16
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES GCM decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set the header phase */
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Computes the authentication TAG.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Size Total length of the plain/cyphertext buffer
+ * @param AuthTag Pointer to the authentication buffer
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ uint64_t headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */
+ uint64_t inputlength = Size * 8U; /* input length in bits */
+ uint32_t tagaddr = (uint32_t)AuthTag;
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
+ {
+ /* Change the CRYP phase */
+ hcryp->Phase = HAL_CRYP_PHASE_FINAL;
+
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select final phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write the number of bits in header (64 bits) followed by the number of bits
+ in the payload */
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DR = __RBIT(headerlength >> 32U);
+ hcryp->Instance->DR = __RBIT(headerlength);
+ hcryp->Instance->DR = __RBIT(inputlength >> 32U);
+ hcryp->Instance->DR = __RBIT(inputlength);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DR = __REV(headerlength >> 32U);
+ hcryp->Instance->DR = __REV(headerlength);
+ hcryp->Instance->DR = __REV(inputlength >> 32U);
+ hcryp->Instance->DR = __REV(inputlength);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32U), 16U);
+ hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16U);
+ hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32U), 16U);
+ hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ {
+ hcryp->Instance->DR = (uint32_t)(headerlength >> 32U);
+ hcryp->Instance->DR = (uint32_t)(headerlength);
+ hcryp->Instance->DR = (uint32_t)(inputlength >> 32U);
+ hcryp->Instance->DR = (uint32_t)(inputlength);
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the Auth TAG in the IN FIFO */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ }
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Computes the authentication TAG for AES CCM mode.
+ * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param AuthTag Pointer to the authentication buffer
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tagaddr = (uint32_t)AuthTag;
+ uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;
+ uint32_t temptag[4U] = {0U}; /* Temporary TAG (MAC) */
+ uint32_t loopcounter;
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
+ {
+ /* Change the CRYP phase */
+ hcryp->Phase = HAL_CRYP_PHASE_FINAL;
+
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select final phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write the counter block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
+ ctraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
+ ctraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
+ ctraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)ctraddr;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the Auth TAG in the IN FIFO */
+ temptag[0U] = hcryp->Instance->DOUT;
+ temptag[1U] = hcryp->Instance->DOUT;
+ temptag[2U] = hcryp->Instance->DOUT;
+ temptag[3U] = hcryp->Instance->DOUT;
+ }
+
+ /* Copy temporary authentication TAG in user TAG buffer */
+ for(loopcounter = 0U; loopcounter < hcryp->Init.TagSize ; loopcounter++)
+ {
+ /* Set the authentication TAG buffer */
+ *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);
+ }
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CCM decryption mode then
+ * decrypted pCypherData. The cypher data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ uint32_t headersize = hcryp->Init.HeaderSize;
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
+ uint32_t loopcounter = 0U;
+ uint32_t bufferidx = 0U;
+ uint8_t blockb0[16U] = {0};/* Block B0 */
+ uint8_t ctr[16U] = {0}; /* Counter */
+ uint32_t b0addr = (uint32_t)blockb0;
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /************************ Formatting the header block *********************/
+ if(headersize != 0U)
+ {
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+ if(headersize < 65280U)
+ {
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+ headersize += 2U;
+ }
+ else
+ {
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
+ headersize += 6U;
+ }
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+ for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
+ {
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+ }
+ /* Check if the header size is modulo 16 */
+ if ((headersize % 16U) != 0U)
+ {
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+ for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = 0U;
+ }
+ /* Set the header size to modulo 16 */
+ headersize = ((headersize/16U) + 1U) * 16U;
+ }
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */
+ headeraddr = (uint32_t)hcryp->Init.pScratch;
+ }
+ /*********************** Formatting the block B0 **************************/
+ if(headersize != 0U)
+ {
+ blockb0[0U] = 0x40U;
+ }
+ /* Flags byte */
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2U))) >> 1U) & (uint8_t)0x07U) << 3U);
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15U) - hcryp->Init.IVSize) - (uint8_t)1U) & (uint8_t)0x07U);
+
+ for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
+ }
+ for ( ; loopcounter < 13U; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = 0U;
+ }
+
+ blockb0[14U] = (Size >> 8U);
+ blockb0[15U] = (Size & 0xFFU);
+
+ /************************* Formatting the initial counter *****************/
+ /* Byte 0:
+ Bits 7 and 6 are reserved and shall be set to 0
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
+ blocks are distinct from B0
+ Bits 0, 1, and 2 contain the same encoding of q as in B0
+ */
+ ctr[0U] = blockb0[0U] & 0x07U;
+ /* byte 1 to NonceSize is the IV (Nonce) */
+ for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
+ {
+ ctr[loopcounter] = blockb0[loopcounter];
+ }
+ /* Set the LSB to 1 */
+ ctr[15U] |= 0x01U;
+
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CCM mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
+
+ /* Select init phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ b0addr = (uint32_t)blockb0;
+ /* Write the blockb0 block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /***************************** Header phase *******************************/
+ if(headersize != 0U)
+ {
+ /* Select header phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable Crypto processor */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Write the header block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Save formatted counter into the scratch buffer pScratch */
+ for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+ }
+ /* Reset bit 0 */
+ hcryp->Init.pScratch[15U] &= 0xFEU;
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES GCM mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP to start the init phase */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+
+ }
+ }
+
+ /* Set the header phase */
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ if(Size != 0U)
+ {
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+ else
+ {
+ /* Process Locked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ uint32_t headersize = hcryp->Init.HeaderSize;
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
+ uint32_t loopcounter = 0U;
+ uint32_t bufferidx = 0U;
+ uint8_t blockb0[16U] = {0};/* Block B0 */
+ uint8_t ctr[16U] = {0}; /* Counter */
+ uint32_t b0addr = (uint32_t)blockb0;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /************************ Formatting the header block *******************/
+ if(headersize != 0U)
+ {
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+ if(headersize < 65280U)
+ {
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+ headersize += 2U;
+ }
+ else
+ {
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
+ headersize += 6U;
+ }
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+ for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
+ {
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+ }
+ /* Check if the header size is modulo 16 */
+ if ((headersize % 16U) != 0U)
+ {
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+ for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = 0U;
+ }
+ /* Set the header size to modulo 16 */
+ headersize = ((headersize/16U) + 1U) * 16U;
+ }
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */
+ headeraddr = (uint32_t)hcryp->Init.pScratch;
+ }
+ /*********************** Formatting the block B0 ************************/
+ if(headersize != 0U)
+ {
+ blockb0[0U] = 0x40U;
+ }
+ /* Flags byte */
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1U) & (uint8_t)0x07) << 3U);
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+
+ for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
+ }
+ for ( ; loopcounter < 13U; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = 0U;
+ }
+
+ blockb0[14U] = (Size >> 8U);
+ blockb0[15U] = (Size & 0xFFU);
+
+ /************************* Formatting the initial counter ***************/
+ /* Byte 0:
+ Bits 7 and 6 are reserved and shall be set to 0
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
+ blocks are distinct from B0
+ Bits 0, 1, and 2 contain the same encoding of q as in B0
+ */
+ ctr[0U] = blockb0[0U] & 0x07U;
+ /* byte 1 to NonceSize is the IV (Nonce) */
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
+ {
+ ctr[loopcounter] = blockb0[loopcounter];
+ }
+ /* Set the LSB to 1 */
+ ctr[15U] |= 0x01U;
+
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CCM mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
+
+ /* Select init phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ b0addr = (uint32_t)blockb0;
+ /* Write the blockb0 block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /***************************** Header phase *****************************/
+ if(headersize != 0U)
+ {
+ /* Select header phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable Crypto processor */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write the header block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Save formatted counter into the scratch buffer pScratch */
+ for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+ }
+ /* Reset bit 0 */
+ hcryp->Init.pScratch[15U] &= 0xFEU;
+
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ if(Size != 0U)
+ {
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+ else
+ {
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call Input transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the cyphertext buffer, must be a multiple of 16
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES GCM decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP to start the init phase */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the header phase */
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ if(Size != 0U)
+ {
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+ else
+ {
+ /* Process Locked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt
+ * then decrypted pCypherData. The cypher data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+ uint32_t tickstart = 0U;
+ uint32_t headersize = hcryp->Init.HeaderSize;
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
+ uint32_t loopcounter = 0U;
+ uint32_t bufferidx = 0U;
+ uint8_t blockb0[16U] = {0};/* Block B0 */
+ uint8_t ctr[16U] = {0}; /* Counter */
+ uint32_t b0addr = (uint32_t)blockb0;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /************************ Formatting the header block *******************/
+ if(headersize != 0U)
+ {
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+ if(headersize < 65280U)
+ {
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+ headersize += 2U;
+ }
+ else
+ {
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
+ headersize += 6U;
+ }
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+ for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
+ {
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+ }
+ /* Check if the header size is modulo 16 */
+ if ((headersize % 16U) != 0U)
+ {
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+ for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = 0U;
+ }
+ /* Set the header size to modulo 16 */
+ headersize = ((headersize/16U) + 1U) * 16U;
+ }
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */
+ headeraddr = (uint32_t)hcryp->Init.pScratch;
+ }
+ /*********************** Formatting the block B0 ************************/
+ if(headersize != 0U)
+ {
+ blockb0[0U] = 0x40U;
+ }
+ /* Flags byte */
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1U) & (uint8_t)0x07) << 3U);
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+
+ for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
+ }
+ for ( ; loopcounter < 13U; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = 0U;
+ }
+
+ blockb0[14U] = (Size >> 8U);
+ blockb0[15U] = (Size & 0xFFU);
+
+ /************************* Formatting the initial counter ***************/
+ /* Byte 0:
+ Bits 7 and 6 are reserved and shall be set to 0
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
+ blocks are distinct from B0
+ Bits 0, 1, and 2 contain the same encoding of q as in B0
+ */
+ ctr[0U] = blockb0[0U] & 0x07U;
+ /* byte 1 to NonceSize is the IV (Nonce) */
+ for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
+ {
+ ctr[loopcounter] = blockb0[loopcounter];
+ }
+ /* Set the LSB to 1 */
+ ctr[15U] |= 0x01U;
+
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CCM mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
+
+ /* Select init phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ b0addr = (uint32_t)blockb0;
+ /* Write the blockb0 block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /***************************** Header phase *****************************/
+ if(headersize != 0U)
+ {
+ /* Select header phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable Crypto processor */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write the header block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Save formatted counter into the scratch buffer pScratch */
+ for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+ }
+ /* Reset bit 0 */
+ hcryp->Init.pScratch[15U] &= 0xFEU;
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ {
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Write the Input block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ if(hcryp->CrypInCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the Input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+ }
+ }
+ else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ {
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ if(hcryp->CrypOutCount == 0U)
+ {
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call Input transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES GCM mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Enable CRYP to start the init phase */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the header phase */
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Unlock process */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData Pointer to the plaintext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+ uint32_t headersize;
+ uint32_t headeraddr;
+ uint32_t loopcounter = 0U;
+ uint32_t bufferidx = 0U;
+ uint8_t blockb0[16U] = {0};/* Block B0 */
+ uint8_t ctr[16U] = {0}; /* Counter */
+ uint32_t b0addr = (uint32_t)blockb0;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ headersize = hcryp->Init.HeaderSize;
+ headeraddr = (uint32_t)hcryp->Init.Header;
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /************************ Formatting the header block *******************/
+ if(headersize != 0U)
+ {
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+ if(headersize < 65280U)
+ {
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+ headersize += 2U;
+ }
+ else
+ {
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
+ headersize += 6U;
+ }
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+ for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
+ {
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+ }
+ /* Check if the header size is modulo 16 */
+ if ((headersize % 16U) != 0U)
+ {
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+ for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = 0U;
+ }
+ /* Set the header size to modulo 16 */
+ headersize = ((headersize/16U) + 1U) * 16U;
+ }
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */
+ headeraddr = (uint32_t)hcryp->Init.pScratch;
+ }
+ /*********************** Formatting the block B0 ************************/
+ if(headersize != 0U)
+ {
+ blockb0[0U] = 0x40U;
+ }
+ /* Flags byte */
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07) << 3);
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+
+ for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
+ }
+ for ( ; loopcounter < 13U; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = 0U;
+ }
+
+ blockb0[14U] = (Size >> 8U);
+ blockb0[15U] = (Size & 0xFFU);
+
+ /************************* Formatting the initial counter ***************/
+ /* Byte 0:
+ Bits 7 and 6 are reserved and shall be set to 0
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
+ blocks are distinct from B0
+ Bits 0, 1, and 2 contain the same encoding of q as in B0
+ */
+ ctr[0U] = blockb0[0U] & 0x07U;
+ /* byte 1 to NonceSize is the IV (Nonce) */
+ for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
+ {
+ ctr[loopcounter] = blockb0[loopcounter];
+ }
+ /* Set the LSB to 1 */
+ ctr[15U] |= 0x01U;
+
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CCM mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
+
+ /* Select init phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ b0addr = (uint32_t)blockb0;
+ /* Write the blockb0 block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /***************************** Header phase *****************************/
+ if(headersize != 0U)
+ {
+ /* Select header phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable Crypto processor */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write the header block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Save formatted counter into the scratch buffer pScratch */
+ for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+ }
+ /* Reset bit 0 */
+ hcryp->Init.pScratch[15U] &= 0xFEU;
+
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Unlock process */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer.
+ * @param Size Length of the cyphertext buffer, must be a multiple of 16
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES GCM decryption mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Enable CRYP to start the init phase */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the header phase */
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Unlock process */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA
+ * then decrypted pCypherData. The cypher data are available in pPlainData.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData Pointer to the cyphertext buffer
+ * @param Size Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t tickstart = 0U;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+ uint32_t headersize;
+ uint32_t headeraddr;
+ uint32_t loopcounter = 0U;
+ uint32_t bufferidx = 0U;
+ uint8_t blockb0[16U] = {0};/* Block B0 */
+ uint8_t ctr[16U] = {0}; /* Counter */
+ uint32_t b0addr = (uint32_t)blockb0;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ headersize = hcryp->Init.HeaderSize;
+ headeraddr = (uint32_t)hcryp->Init.Header;
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /************************ Formatting the header block *******************/
+ if(headersize != 0U)
+ {
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+ if(headersize < 65280U)
+ {
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+ headersize += 2U;
+ }
+ else
+ {
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+ hcryp->Init.pScratch[bufferidx++] = 0xFFU;
+ hcryp->Init.pScratch[bufferidx++] = 0xFEU;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
+ headersize += 6U;
+ }
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+ for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
+ {
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+ }
+ /* Check if the header size is modulo 16 */
+ if ((headersize % 16U) != 0U)
+ {
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+ for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = 0U;
+ }
+ /* Set the header size to modulo 16 */
+ headersize = ((headersize/16U) + 1U) * 16U;
+ }
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */
+ headeraddr = (uint32_t)hcryp->Init.pScratch;
+ }
+ /*********************** Formatting the block B0 ************************/
+ if(headersize != 0U)
+ {
+ blockb0[0U] = 0x40U;
+ }
+ /* Flags byte */
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07) << 3);
+ blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+
+ for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
+ }
+ for ( ; loopcounter < 13U; loopcounter++)
+ {
+ blockb0[loopcounter+1U] = 0U;
+ }
+
+ blockb0[14U] = (Size >> 8U);
+ blockb0[15U] = (Size & 0xFFU);
+
+ /************************* Formatting the initial counter ***************/
+ /* Byte 0:
+ Bits 7 and 6 are reserved and shall be set to 0
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
+ blocks are distinct from B0
+ Bits 0, 1, and 2 contain the same encoding of q as in B0
+ */
+ ctr[0U] = blockb0[0U] & 0x07U;
+ /* byte 1 to NonceSize is the IV (Nonce) */
+ for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
+ {
+ ctr[loopcounter] = blockb0[loopcounter];
+ }
+ /* Set the LSB to 1 */
+ ctr[15U] |= 0x01U;
+
+ /* Set the key */
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+
+ /* Set the CRYP peripheral in AES CCM mode */
+ __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
+
+ /* Select init phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ b0addr = (uint32_t)blockb0;
+ /* Write the blockb0 block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ b0addr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(b0addr);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+
+ }
+ }
+ /***************************** Header phase *****************************/
+ if(headersize != 0U)
+ {
+ /* Select header phase */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable Crypto processor */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write the header block in the IN FIFO */
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ hcryp->Instance->DR = *(uint32_t*)(headeraddr);
+ headeraddr+=4U;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Save formatted counter into the scratch buffer pScratch */
+ for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
+ {
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+ }
+ /* Reset bit 0 */
+ hcryp->Init.pScratch[15U] &= 0xFEU;
+ /* Select payload phase once the header phase is performed */
+ __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Flush FIFO */
+ __HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Set the input and output addresses and start DMA transfer */
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Unlock process */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management
+ * @brief CRYPEx IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### CRYPEx IRQ handler management #####
+ ==============================================================================
+[..] This section provides CRYPEx IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles CRYPEx interrupt request.
+ * @param hcryp pointer to a CRYPEx_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+
+void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+ switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
+ {
+ case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:
+ HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:
+ HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:
+ HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:
+ HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0U, NULL);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* CRYP */
+
+#if defined (AES)
+
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
+ * @{
+ */
+#define CRYP_CCF_TIMEOUTVALUE 22000U /*!< CCF flag raising time-out value */
+#define CRYP_BUSY_TIMEOUTVALUE 22000U /*!< BUSY flag reset time-out value */
+
+#define CRYP_POLLING_OFF 0x0U /*!< No polling when padding */
+#define CRYP_POLLING_ON 0x1U /*!< Polling when padding */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout);
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+ * @{
+ */
+
+
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function
+ * @brief Extended callback functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended callback functions #####
+ ===============================================================================
+ [..] This section provides callback function:
+ (+) Computation completed.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Computation completed callbacks.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYPEx_ComputationCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions
+ * @brief Extended processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### AES extended processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes.
+ Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated
+ based on the processing type. Three processing types are available:
+ (++) Polling mode
+ (++) Interrupt mode
+ (++) DMA mode
+ (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES
+ algorithm in different chaining modes.
+ Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase
+ so that steps can be skipped if so required. Functions are only differentiated based on the processing type.
+ Three processing types are available:
+ (++) Polling mode
+ (++) Interrupt mode
+ (++) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Carry out in polling mode the ciphering or deciphering operation according to
+ * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and
+ * chaining modes ECB, CBC and CTR are managed by this function in polling mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption
+ * or key derivation+decryption.
+ * Parameter is meaningless in case of key derivation.
+ * @param Size Length of the input data buffer in bytes, must be a multiple of 16.
+ * Parameter is meaningless in case of key derivation.
+ * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of
+ * decryption/key derivation+decryption, or pointer to the derivative keys in
+ * case of key derivation only.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout)
+{
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Check parameters setting */
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+ {
+ if (pOutputData == NULL)
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Call CRYP_ReadKey() API if the operating mode is set to
+ key derivation, CRYP_ProcessData() otherwise */
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+ {
+ if(CRYP_ReadKey(hcryp, pOutputData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ if(CRYP_ProcessData(hcryp, pInputData, Size, pOutputData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If the state has not been set to SUSPENDED, set it to
+ READY, otherwise keep it as it is */
+ if (hcryp->State != HAL_CRYP_STATE_SUSPENDED)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Carry out in interrupt mode the ciphering or deciphering operation according to
+ * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and
+ * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption
+ * or key derivation+decryption.
+ * Parameter is meaningless in case of key derivation.
+ * @param Size Length of the input data buffer in bytes, must be a multiple of 16.
+ * Parameter is meaningless in case of key derivation.
+ * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of
+ * decryption/key derivation+decryption, or pointer to the derivative keys in
+ * case of key derivation only.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
+{
+ uint32_t inputaddr = 0U;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Check parameters setting */
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+ {
+ if (pOutputData == NULL)
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* If operating mode is not limited to key derivation only,
+ get the buffers addresses and sizes */
+ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+ {
+
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pInputData;
+ hcryp->pCrypOutBuffPtr = pOutputData;
+ hcryp->CrypOutCount = Size;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Enable Computation Complete Flag and Error Interrupts */
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+
+ /* If operating mode is key derivation only, the input data have
+ already been entered during the initialization process. For
+ the other operating modes, they are fed to the CRYP hardware
+ block at this point. */
+ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+ {
+ /* Initiate the processing under interrupt in entering
+ the first input data */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ /* Increment/decrement instance pointer/counter */
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ /* Write the first input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Carry out in DMA mode the ciphering or deciphering operation according to
+ * hcryp->Init structure fields.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption
+ * or key derivation+decryption.
+ * @param Size Length of the input data buffer in bytes, must be a multiple of 16.
+ * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of
+ * decryption/key derivation+decryption.
+ * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode.
+ * @note Supported operating modes are encryption, decryption and key derivation with decryption.
+ * @note No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx
+ * registers must be done by software.
+ * @note This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx
+ * registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs.
+ * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
+{
+ uint32_t inputaddr = 0U;
+ uint32_t outputaddr = 0U;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Check parameters setting */
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
+ {
+ /* no DMA channel is provided for key derivation operating mode,
+ access to AES_KEYRx registers must be done by software */
+ return HAL_ERROR;
+ }
+ else
+ {
+ if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pInputData;
+ outputaddr = (uint32_t)pOutputData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering
+ * operation according to hcryp->Init structure fields.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInputData
+ * - pointer to payload data in GCM payload phase,
+ * - pointer to B0 block in CMAC header phase,
+ * - pointer to C block in CMAC final phase.
+ * - Parameter is meaningless in case of GCM/GMAC init, header and final phases.
+ * @param Size
+ * - length of the input payload data buffer in bytes,
+ * - length of B0 block (in bytes) in CMAC header phase,
+ * - length of C block (in bytes) in CMAC final phase.
+ * - Parameter is meaningless in case of GCM/GMAC init and header phases.
+ * @param pOutputData
+ * - pointer to plain or cipher text in GCM payload phase,
+ * - pointer to authentication tag in GCM/GMAC and CMAC final phases.
+ * - Parameter is meaningless in case of GCM/GMAC init and header phases
+ * and in case of CMAC header phase.
+ * @param Timeout Specify Timeout value
+ * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable.
+ * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
+ * can be skipped by the user if so required.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout)
+{
+ uint32_t index = 0U;
+ uint32_t inputaddr = 0U;
+ uint32_t outputaddr = 0U;
+ uint32_t tagaddr = 0U;
+ uint64_t headerlength = 0U;
+ uint64_t inputlength = 0U;
+ uint64_t payloadlength = 0U;
+ uint32_t difflength = 0U;
+ uint32_t addhoc_process = 0U;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* input/output parameters check */
+ if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+ {
+ if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U))
+ {
+ return HAL_ERROR;
+ }
+#if defined(AES_CR_NPBLB)
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
+#else
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif
+ {
+ /* In case of CMAC (or CCM) header phase resumption, we can have pInputData = NULL and Size = 0 */
+ if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U)))
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+ {
+ if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+ {
+ if (pOutputData == NULL)
+ {
+ return HAL_ERROR;
+ }
+#if defined(AES_CR_NPBLB)
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))
+#else
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
+#endif
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /*==============================================*/
+ /* GCM/GMAC (or CCM when applicable) init phase */
+ /*==============================================*/
+ /* In case of init phase, the input data (Key and Initialization Vector) have
+ already been entered during the initialization process. Therefore, the
+ API just waits for the CCF flag to be set. */
+ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
+ {
+ /* just wait for hash computation */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Mark that the initialization phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
+ }
+ /*=====================================*/
+ /* GCM/GMAC or (CCM/)CMAC header phase */
+ /*=====================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+ {
+ /* Set header phase; for GCM or GMAC, set data-byte at this point */
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);
+ }
+ else
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_CRYP_ENABLE();
+
+#if !defined(AES_CR_NPBLB)
+ /* in case of CMAC, enter B0 block in header phase, before the header itself. */
+ /* If Size = 0 (possible case of resumption after CMAC header phase suspension),
+ skip these steps and go directly to header buffer feeding to the HW */
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0U))
+ {
+ inputaddr = (uint32_t)pInputData;
+
+ for(index=0U; (index < Size); index += 16U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < Size))
+ {
+ /* reset SuspendRequest */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+
+ /* Save current reading and writing locations of Input and Output buffers */
+ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
+ /* Save the total number of bytes (B blocks + header) that remain to be
+ processed at this point */
+ hcryp->CrypInCount = hcryp->Init.HeaderSize + Size - (index+16U);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+ } /* for(index=0; (index < Size); index += 16) */
+ }
+#endif /* !defined(AES_CR_NPBLB) */
+
+ /* Enter header */
+ inputaddr = (uint32_t)hcryp->Init.Header;
+ /* Local variable headerlength is a number of bytes multiple of 128 bits,
+ remaining header data (if any) are handled after this loop */
+ headerlength = (((hcryp->Init.HeaderSize)/16U)*16U) ;
+ if ((hcryp->Init.HeaderSize % 16U) != 0U)
+ {
+ difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength);
+ }
+ for(index=0U; index < headerlength; index += 16U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < headerlength))
+ {
+ /* reset SuspendRequest */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+
+ /* Save current reading and writing locations of Input and Output buffers */
+ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
+ /* Save the total number of bytes that remain to be processed at this point */
+ hcryp->CrypInCount = hcryp->Init.HeaderSize - (index+16U);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+ }
+
+ /* Case header length is not a multiple of 16 bytes */
+ if (difflength != 0U)
+ {
+ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
+ CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
+ }
+
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
+ }
+ /*============================================*/
+ /* GCM (or CCM when applicable) payload phase */
+ /*============================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+ {
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);
+
+ /* if the header phase has been bypassed, AES must be enabled again */
+ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+ {
+ __HAL_CRYP_ENABLE();
+ }
+
+ inputaddr = (uint32_t)pInputData;
+ outputaddr = (uint32_t)pOutputData;
+
+ /* Enter payload */
+ /* Specific handling to manage payload last block size less than 128 bits */
+ if ((Size % 16U) != 0U)
+ {
+ payloadlength = (Size/16U) * 16U;
+ difflength = (uint32_t) (Size - payloadlength);
+ addhoc_process = 1U;
+ }
+ else
+ {
+ payloadlength = Size;
+ addhoc_process = 0U;
+ }
+
+ /* Feed payload */
+ for(index=0U; index < payloadlength; index += 16U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ /* Retrieve output data: read the output block
+ from the Data Output Register */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < payloadlength))
+ {
+ /* no flag waiting under IRQ handling */
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+ {
+ /* Ensure that Busy flag is reset */
+ if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+ }
+ /* reset SuspendRequest */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+
+ /* Save current reading and writing locations of Input and Output buffers */
+ hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
+ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hcryp->CrypInCount = Size - (index+16U);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+
+ }
+
+ /* Additional processing to manage GCM(/CCM) encryption and decryption cases when
+ payload last block size less than 128 bits */
+ if (addhoc_process == 1U)
+ {
+ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
+ hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
+ CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
+ } /* (addhoc_process == 1) */
+
+ /* Mark that the payload phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
+ }
+ /*====================================*/
+ /* GCM/GMAC or (CCM/)CMAC final phase */
+ /*====================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+ {
+ tagaddr = (uint32_t)pOutputData;
+
+#if defined(AES_CR_NPBLB)
+ /* By default, clear NPBLB field */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
+#endif
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
+
+ /* if the header and payload phases have been bypassed, AES must be enabled again */
+ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+ {
+ __HAL_CRYP_ENABLE();
+ }
+
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ {
+ headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */
+ inputlength = Size * 8U; /* input length in bits */
+
+
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DINR = __RBIT((headerlength)>>32U);
+ hcryp->Instance->DINR = __RBIT(headerlength);
+ hcryp->Instance->DINR = __RBIT((inputlength)>>32U);
+ hcryp->Instance->DINR = __RBIT(inputlength);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DINR = __REV((headerlength)>>32U);
+ hcryp->Instance->DINR = __REV(headerlength);
+ hcryp->Instance->DINR = __REV((inputlength)>>32U);
+ hcryp->Instance->DINR = __REV(inputlength);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DINR = __ROR((headerlength)>>32U, 16U);
+ hcryp->Instance->DINR = __ROR(headerlength, 16U);
+ hcryp->Instance->DINR = __ROR((inputlength)>>32U, 16U);
+ hcryp->Instance->DINR = __ROR(inputlength, 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ {
+ hcryp->Instance->DINR = (uint32_t)(headerlength>>32U);
+ hcryp->Instance->DINR = (uint32_t)(headerlength);
+ hcryp->Instance->DINR = (uint32_t)(inputlength>>32U);
+ hcryp->Instance->DINR = (uint32_t)(inputlength);
+ }
+ }
+#if !defined(AES_CR_NPBLB)
+ else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+ {
+ inputaddr = (uint32_t)pInputData;
+ /* Enter the last block made of a 128-bit value formatted
+ from the original B0 packet. */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ }
+#endif
+
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+
+ /* Read the Auth TAG in the Data Out register */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Mark that the final phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
+ /* Disable the Peripheral */
+ __HAL_CRYP_DISABLE();
+ }
+ /*=================================================*/
+ /* case incorrect hcryp->Init.GCMCMACPhase setting */
+ /*=================================================*/
+ else
+ {
+ hcryp->State = HAL_CRYP_STATE_ERROR;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+
+
+/**
+ * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering
+ * operation according to hcryp->Init structure fields.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInputData
+ * - pointer to payload data in GCM payload phase,
+ * - pointer to B0 block in CMAC header phase,
+ * - pointer to C block in CMAC final phase.
+ * Parameter is meaningless in case of GCM/GMAC init, header and final phases.
+ * @param Size
+ * - length of the input payload data buffer in bytes,
+ * - length of B0 block (in bytes) in CMAC header phase,
+ * - length of C block (in bytes) in CMAC final phase.
+ * - Parameter is meaningless in case of GCM/GMAC init and header phases.
+ * @param pOutputData
+ * - pointer to plain or cipher text in GCM payload phase,
+ * - pointer to authentication tag in GCM/GMAC and CMAC final phases.
+ * - Parameter is meaningless in case of GCM/GMAC init and header phases
+ * and in case of CMAC header phase.
+ * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
+ * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
+ * can be skipped by the user if so required.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
+{
+
+ uint32_t inputaddr = 0U;
+ uint64_t headerlength = 0U;
+ uint64_t inputlength = 0U;
+ uint32_t index = 0U;
+ uint32_t addhoc_process = 0U;
+ uint32_t difflength = 0U;
+ uint32_t difflengthmod4 = 0U;
+ uint32_t mask[3U] = {0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
+
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* input/output parameters check */
+ if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+ {
+ if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U))
+ {
+ return HAL_ERROR;
+ }
+#if defined(AES_CR_NPBLB)
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
+#else
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif
+ {
+ /* In case of CMAC header phase resumption, we can have pInputData = NULL and Size = 0 */
+ if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U)))
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+ {
+ if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+ {
+ if (pOutputData == NULL)
+ {
+ return HAL_ERROR;
+ }
+#if defined(AES_CR_NPBLB)
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))
+#else
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
+#endif
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Enable Computation Complete Flag and Error Interrupts */
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+
+ /*==============================================*/
+ /* GCM/GMAC (or CCM when applicable) init phase */
+ /*==============================================*/
+ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
+ {
+ /* In case of init phase, the input data (Key and Initialization Vector) have
+ already been entered during the initialization process. Therefore, the
+ software just waits for the CCF interrupt to be raised and which will
+ be handled by CRYP_AES_Auth_IT() API. */
+ }
+ /*=====================================*/
+ /* GCM/GMAC or (CCM/)CMAC header phase */
+ /*=====================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+ {
+
+#if defined(AES_CR_NPBLB)
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
+#else
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif
+ {
+ /* In case of CMAC, B blocks are first entered, before the header.
+ Therefore, B blocks and the header are entered back-to-back
+ as if it was only one single block.
+ However, in case of resumption after suspension, if all the
+ B blocks have been entered (in that case, Size = 0), only the
+ remainder of the non-processed header bytes are entered. */
+ if (Size != 0U)
+ {
+ hcryp->CrypInCount = Size + hcryp->Init.HeaderSize;
+ hcryp->pCrypInBuffPtr = pInputData;
+ }
+ else
+ {
+ hcryp->CrypInCount = hcryp->Init.HeaderSize;
+ hcryp->pCrypInBuffPtr = hcryp->Init.Header;
+ }
+ }
+ else
+ {
+ /* Get the header addresses and sizes */
+ hcryp->CrypInCount = hcryp->Init.HeaderSize;
+ hcryp->pCrypInBuffPtr = hcryp->Init.Header;
+ }
+
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Set header phase; for GCM or GMAC, set data-byte at this point */
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);
+ }
+ else
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_CRYP_ENABLE();
+
+ /* Increment/decrement instance pointer/counter */
+ if (hcryp->CrypInCount == 0U)
+ {
+ /* Case of no header */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ return HAL_OK;
+ }
+ else if (hcryp->CrypInCount < 16U)
+ {
+ hcryp->CrypInCount = 0U;
+ addhoc_process = 1U;
+ difflength = (uint32_t) (hcryp->Init.HeaderSize);
+ difflengthmod4 = difflength%4U;
+ }
+ else
+ {
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ }
+
+#if defined(AES_CR_NPBLB)
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
+#else
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif
+ {
+ if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
+ {
+ /* All B blocks will have been entered after the next
+ four DINR writing, so point at header buffer for
+ the next iteration */
+ hcryp->pCrypInBuffPtr = hcryp->Init.Header;
+ }
+ }
+
+ /* Enter header first block to initiate the process
+ in the Data Input register */
+ if (addhoc_process == 0U)
+ {
+ /* Header has size equal or larger than 128 bits */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ }
+ else
+ {
+ /* Header has size less than 128 bits */
+ /* Enter complete words when possible */
+ for(index=0U; index < (difflength/4U); index ++)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ }
+ /* Enter incomplete word padded with zeroes if applicable
+ (case of header length not a multiple of 32-bits) */
+ if (difflengthmod4 != 0U)
+ {
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1U]);
+ }
+ /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
+ for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
+ {
+ hcryp->Instance->DINR = 0U;
+ }
+
+ }
+ }
+ /*============================================*/
+ /* GCM (or CCM when applicable) payload phase */
+ /*============================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+ {
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pInputData;
+ hcryp->pCrypOutBuffPtr = pOutputData;
+ hcryp->CrypOutCount = Size;
+
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCM_PAYLOAD_PHASE);
+
+ /* if the header phase has been bypassed, AES must be enabled again */
+ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+ {
+ __HAL_CRYP_ENABLE();
+ }
+
+ /* Specific handling to manage payload size less than 128 bits */
+ if (Size < 16U)
+ {
+#if defined(AES_CR_NPBLB)
+ /* In case of GCM encryption or CCM decryption, specify the number of padding
+ bytes in last block of payload */
+ if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)
+ {
+ if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
+ && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))
+ || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)
+ && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
+ {
+ /* Set NPBLB field in writing the number of padding bytes
+ for the last block of payload */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16U - difflength);
+ }
+ }
+#else
+ /* Software workaround applied to GCM encryption only */
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+ {
+ /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
+ __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
+ }
+#endif
+
+ /* Set hcryp->CrypInCount to 0 (no more data to enter) */
+ hcryp->CrypInCount = 0U;
+
+ /* Insert the last block (which size is inferior to 128 bits) padded with zeroes,
+ to have a complete block of 128 bits */
+ difflength = (uint32_t) (Size);
+ difflengthmod4 = difflength%4U;
+ /* Insert the last block (which size is inferior to 128 bits) padded with zeroes
+ to have a complete block of 128 bits */
+ for(index=0U; index < (difflength/4U); index ++)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ }
+ /* If required, manage input data size not multiple of 32 bits */
+ if (difflengthmod4 != 0U)
+ {
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1U]);
+ }
+ /* Wrap-up in padding with zero-words if applicable */
+ for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
+ {
+ hcryp->Instance->DINR = 0U;
+ }
+ }
+ else
+ {
+ /* Increment/decrement instance pointer/counter */
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+
+ /* Enter payload first block to initiate the process
+ in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ }
+ }
+ /*====================================*/
+ /* GCM/GMAC or (CCM/)CMAC final phase */
+ /*====================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+ {
+ hcryp->pCrypOutBuffPtr = pOutputData;
+
+#if defined(AES_CR_NPBLB)
+ /* By default, clear NPBLB field */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
+#endif
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
+
+ /* if the header and payload phases have been bypassed, AES must be enabled again */
+ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+ {
+ __HAL_CRYP_ENABLE();
+ }
+
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ {
+ headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */
+ inputlength = Size * 8U; /* Input length in bits */
+ /* Write the number of bits in the header on 64 bits followed by the number
+ of bits in the payload on 64 bits as well */
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DINR = __RBIT((headerlength)>>32U);
+ hcryp->Instance->DINR = __RBIT(headerlength);
+ hcryp->Instance->DINR = __RBIT((inputlength)>>32U);
+ hcryp->Instance->DINR = __RBIT(inputlength);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DINR = __REV((headerlength)>>32U);
+ hcryp->Instance->DINR = __REV(headerlength);
+ hcryp->Instance->DINR = __REV((inputlength)>>32U);
+ hcryp->Instance->DINR = __REV(inputlength);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DINR = __ROR((headerlength)>>32U, 16U);
+ hcryp->Instance->DINR = __ROR(headerlength, 16U);
+ hcryp->Instance->DINR = __ROR((inputlength)>>32U, 16U);
+ hcryp->Instance->DINR = __ROR(inputlength, 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ {
+ hcryp->Instance->DINR = (uint32_t)(headerlength>>32U);
+ hcryp->Instance->DINR = (uint32_t)(headerlength);
+ hcryp->Instance->DINR = (uint32_t)(inputlength>>32U);
+ hcryp->Instance->DINR = (uint32_t)(inputlength);
+ }
+ }
+#if !defined(AES_CR_NPBLB)
+ else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+ {
+ inputaddr = (uint32_t)pInputData;
+ /* Enter the last block made of a 128-bit value formatted
+ from the original B0 packet. */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ }
+#endif
+ }
+ /*=================================================*/
+ /* case incorrect hcryp->Init.GCMCMACPhase setting */
+ /*=================================================*/
+ else
+ {
+ hcryp->State = HAL_CRYP_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+
+
+/**
+ * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering
+ * operation according to hcryp->Init structure fields.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pInputData
+ * - pointer to payload data in GCM payload phase,
+ * - pointer to B0 block in CMAC header phase,
+ * - pointer to C block in CMAC final phase.
+ * - Parameter is meaningless in case of GCM/GMAC init, header and final phases.
+ * @param Size
+ * - length of the input payload data buffer in bytes,
+ * - length of B block (in bytes) in CMAC header phase,
+ * - length of C block (in bytes) in CMAC final phase.
+ * - Parameter is meaningless in case of GCM/GMAC init and header phases.
+ * @param pOutputData
+ * - pointer to plain or cipher text in GCM payload phase,
+ * - pointer to authentication tag in GCM/GMAC and CMAC final phases.
+ * - Parameter is meaningless in case of GCM/GMAC init and header phases
+ * and in case of CMAC header phase.
+ * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
+ * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
+ * can be skipped by the user if so required.
+ * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
+{
+ uint32_t inputaddr = 0U;
+ uint32_t outputaddr = 0U;
+ uint32_t tagaddr = 0U;
+ uint64_t headerlength = 0U;
+ uint64_t inputlength = 0U;
+ uint64_t payloadlength = 0U;
+
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* input/output parameters check */
+ if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+ {
+ if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U))
+ {
+ return HAL_ERROR;
+ }
+#if defined(AES_CR_NPBLB)
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
+#else
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif
+ {
+ if ((pInputData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+ {
+ if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+ {
+ if (pOutputData == NULL)
+ {
+ return HAL_ERROR;
+ }
+#if defined(AES_CR_NPBLB)
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))
+#else
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
+#endif
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /*==============================================*/
+ /* GCM/GMAC (or CCM when applicable) init phase */
+ /*==============================================*/
+ /* In case of init phase, the input data (Key and Initialization Vector) have
+ already been entered during the initialization process. No DMA transfer is
+ required at that point therefore, the software just waits for the CCF flag
+ to be raised. */
+ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
+ {
+ /* just wait for hash computation */
+ if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Mark that the initialization phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+ /*===============================*/
+ /* GCM/GMAC or CMAC header phase */
+ /*===============================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
+ {
+ /* Set header phase; for GCM or GMAC, set data-byte at this point */
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_GCMCMAC_HEADER_PHASE|hcryp->Init.DataType);
+ }
+ else
+ {
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_HEADER_PHASE);
+ }
+
+#if !defined(AES_CR_NPBLB)
+ /* enter first B0 block in polling mode (no DMA transfer for B0) */
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+ {
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE();
+
+ inputaddr = (uint32_t)pInputData;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+
+ if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ }
+#endif
+
+ /* No header case */
+ if (hcryp->Init.Header == NULL)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+
+ inputaddr = (uint32_t)hcryp->Init.Header;
+ if ((hcryp->Init.HeaderSize % 16U) != 0U)
+ {
+
+ if (hcryp->Init.HeaderSize < 16U)
+ {
+ CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF);
+
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
+
+ /* CCF flag indicating header phase AES processing completion
+ will be checked at the start of the next phase:
+ - payload phase (GCM / CCM when applicable)
+ - final phase (GMAC or CMAC). */
+ }
+ else
+ {
+ /* Local variable headerlength is a number of bytes multiple of 128 bits,
+ remaining header data (if any) are handled after this loop */
+ headerlength = (((hcryp->Init.HeaderSize)/16U)*16U) ;
+ /* Store the ending transfer point */
+ hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength;
+ hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */
+
+ /* Set the input and output addresses and start DMA transfer */
+ /* (incomplete DMA transfer, will be wrapped up after completion of
+ the first one (initiated here) with data padding */
+ CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, headerlength, 0U);
+ }
+ }
+ else
+ {
+ hcryp->CrypInCount = 0U;
+ /* Set the input address and start DMA transfer */
+ CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0U);
+ }
+
+ }
+ /*============================================*/
+ /* GCM (or CCM when applicable) payload phase */
+ /*============================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+ {
+ /* Coming from header phase, wait for CCF flag to be raised
+ if header present and fed to the IP in the previous phase */
+ if (hcryp->Init.Header != NULL)
+ {
+ if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ /* Enable the Peripheral since wasn't in header phase (no header case) */
+ __HAL_CRYP_ENABLE();
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);
+
+ /* Specific handling to manage payload size less than 128 bits */
+ if ((Size % 16U) != 0U)
+ {
+ inputaddr = (uint32_t)pInputData;
+ outputaddr = (uint32_t)pOutputData;
+ if (Size < 16U)
+ {
+ /* Block is now entered in polling mode, no actual gain in resorting to DMA */
+ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
+ hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
+
+ CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON);
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Mark that the payload phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
+
+ /* Call output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+ }
+ else
+ {
+ payloadlength = (Size/16U) * 16U;
+
+ /* Store the ending transfer points */
+ hcryp->pCrypInBuffPtr = pInputData + payloadlength;
+ hcryp->pCrypOutBuffPtr = pOutputData + payloadlength;
+ hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */
+
+ /* Set the input and output addresses and start DMA transfer */
+ /* (incomplete DMA transfer, will be wrapped up with data padding
+ after completion of the one initiated here) */
+ CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr);
+ }
+ }
+ else
+ {
+ hcryp->CrypInCount = 0U;
+ inputaddr = (uint32_t)pInputData;
+ outputaddr = (uint32_t)pOutputData;
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ }
+ }
+ /*====================================*/
+ /* GCM/GMAC or (CCM/)CMAC final phase */
+ /*====================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+ {
+ /* If coming from header phase (GMAC or CMAC case),
+ wait for CCF flag to be raised */
+ if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_HEADER_PHASE)
+ {
+ if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ }
+
+ tagaddr = (uint32_t)pOutputData;
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
+
+ /* if the header and payload phases have been bypassed, AES must be enabled again */
+ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
+ {
+ __HAL_CRYP_ENABLE();
+ }
+
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ {
+ headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */
+ inputlength = Size * 8U; /* input length in bits */
+ /* Write the number of bits in the header on 64 bits followed by the number
+ of bits in the payload on 64 bits as well */
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DINR = __RBIT((headerlength)>>32U);
+ hcryp->Instance->DINR = __RBIT(headerlength);
+ hcryp->Instance->DINR = __RBIT((inputlength)>>32U);
+ hcryp->Instance->DINR = __RBIT(inputlength);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DINR = __REV((headerlength)>>32U);
+ hcryp->Instance->DINR = __REV(headerlength);
+ hcryp->Instance->DINR = __REV((inputlength)>>32U);
+ hcryp->Instance->DINR = __REV(inputlength);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DINR = __ROR((headerlength)>>32U, 16U);
+ hcryp->Instance->DINR = __ROR(headerlength, 16U);
+ hcryp->Instance->DINR = __ROR((inputlength)>>32U, 16U);
+ hcryp->Instance->DINR = __ROR(inputlength, 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ {
+ hcryp->Instance->DINR = (uint32_t)(headerlength>>32U);
+ hcryp->Instance->DINR = (uint32_t)(headerlength);
+ hcryp->Instance->DINR = (uint32_t)(inputlength>>32U);
+ hcryp->Instance->DINR = (uint32_t)(inputlength);
+ }
+ }
+#if !defined(AES_CR_NPBLB)
+ else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+ {
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ inputaddr = (uint32_t)pInputData;
+ /* Enter the last block made of a 128-bit value formatted
+ from the original B0 packet. */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ }
+#endif
+
+ /* No DMA transfer is required at that point therefore, the software
+ just waits for the CCF flag to be raised. */
+ if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Read the Auth TAG in the IN FIFO */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+
+ /* Mark that the final phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Disable the Peripheral */
+ __HAL_CRYP_DISABLE();
+ }
+ /*=================================================*/
+ /* case incorrect hcryp->Init.GCMCMACPhase setting */
+ /*=================================================*/
+ else
+ {
+ hcryp->State = HAL_CRYP_STATE_ERROR;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions
+ * @brief Extended processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### AES extended suspension and resumption functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) save in memory the Initialization Vector, the Key registers, the Control register or
+ the Suspend registers when a process is suspended by a higher priority message
+ (+) write back in CRYP hardware block the saved values listed above when the suspended
+ lower priority message processing is resumed.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief In case of message processing suspension, read the Initialization Vector.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Output Pointer to the buffer containing the saved Initialization Vector.
+ * @note This value has to be stored for reuse by writing the AES_IVRx registers
+ * as soon as the interrupted processing has to be resumed.
+ * Applicable to all chaining modes.
+ * @note AES must be disabled when reading or resetting the IV values.
+ * @retval None
+ */
+void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
+{
+ uint32_t outputaddr = (uint32_t)Output;
+
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR1);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR0);
+}
+
+/**
+ * @brief In case of message processing resumption, rewrite the Initialization
+ * Vector in the AES_IVRx registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Input Pointer to the buffer containing the saved Initialization Vector to
+ * write back in the CRYP hardware block.
+ * @note Applicable to all chaining modes.
+ * @note AES must be disabled when reading or resetting the IV values.
+ * @retval None
+ */
+void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
+{
+ uint32_t ivaddr = (uint32_t)Input;
+
+ hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
+}
+
+
+/**
+ * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Output Pointer to the buffer containing the saved Suspend Registers.
+ * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers
+ * as soon as the interrupted processing has to be resumed.
+ * @retval None
+ */
+void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
+{
+ uint32_t outputaddr = (uint32_t)Output;
+
+ /* In case of GCM payload phase encryption, check that suspension can be carried out */
+ if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_GCM_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT))
+ {
+ /* Ensure that Busy flag is reset */
+ if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_BUSY_ERROR;
+ hcryp->State = HAL_CRYP_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ HAL_CRYP_ErrorCallback(hcryp);
+ return ;
+ }
+ }
+
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP5R);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP4R);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP3R);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R);
+}
+
+/**
+ * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend
+ * Registers in the AES_SUSPxR registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Input Pointer to the buffer containing the saved suspend registers to
+ * write back in the CRYP hardware block.
+ * @retval None
+ */
+void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
+{
+ uint32_t ivaddr = (uint32_t)Input;
+
+ hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->SUSP5R = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->SUSP4R = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->SUSP3R = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->SUSP2R = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4U;
+ hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr));
+}
+
+
+/**
+ * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Output Pointer to the buffer containing the saved Key Registers.
+ * @param KeySize Indicates the key size (128 or 256 bits).
+ * @note These values have to be stored for reuse by writing back the AES_KEYRx registers
+ * as soon as the interrupted processing has to be resumed.
+ * @retval None
+ */
+void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize)
+{
+ uint32_t keyaddr = (uint32_t)Output;
+
+ if (KeySize == CRYP_KEYSIZE_256B)
+ {
+ *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7);
+ keyaddr+=4U;
+ *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR6);
+ keyaddr+=4U;
+ *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5);
+ keyaddr+=4U;
+ *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4);
+ keyaddr+=4U;
+ }
+
+ *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3);
+ keyaddr+=4U;
+ *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2);
+ keyaddr+=4U;
+ *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1);
+ keyaddr+=4U;
+ *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0);
+}
+
+/**
+ * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key
+ * Registers in the AES_KEYRx registers.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Input Pointer to the buffer containing the saved key registers to
+ * write back in the CRYP hardware block.
+ * @param KeySize Indicates the key size (128 or 256 bits)
+ * @retval None
+ */
+void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize)
+{
+ uint32_t keyaddr = (uint32_t)Input;
+
+ if (KeySize == CRYP_KEYSIZE_256B)
+ {
+ hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ }
+
+ hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4U;
+ hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
+}
+
+
+/**
+ * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Control Register.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Output Pointer to the buffer containing the saved Control Register.
+ * @note This values has to be stored for reuse by writing back the AES_CR register
+ * as soon as the interrupted processing has to be resumed.
+ * @retval None
+ */
+void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
+{
+ *(uint32_t*)(Output) = hcryp->Instance->CR;
+}
+
+/**
+ * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control
+ * Registers in the AES_CR register.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Input Pointer to the buffer containing the saved Control Register to
+ * write back in the CRYP hardware block.
+ * @retval None
+ */
+void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
+{
+ hcryp->Instance->CR = *(uint32_t*)(Input);
+ /* At the same time, set handle state back to READY to be able to resume the AES calculations
+ without the processing APIs returning HAL_BUSY when called. */
+ hcryp->State = HAL_CRYP_STATE_READY;
+}
+
+/**
+ * @brief Request CRYP processing suspension when in polling or interruption mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @note Set the handle field SuspendRequest to the appropriate value so that
+ * the on-going CRYP processing is suspended as soon as the required
+ * conditions are met.
+ * @note It is advised not to suspend the CRYP processing when the DMA controller
+ * is managing the data transfer
+ * @retval None
+ */
+void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
+{
+ /* Set Handle Suspend Request field */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRYPEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA CRYP Input Data process complete callback
+ * for GCM, GMAC or CMAC chainging modes.
+ * @note Specific setting of hcryp fields are required only
+ * in the case of header phase where no output data DMA
+ * transfer is on-going (only input data transfer is enabled
+ * in such a case).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ uint32_t difflength = 0U;
+
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for input request */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+ {
+
+ if (hcryp->CrypInCount != 0U)
+ {
+ /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
+ difflength = hcryp->CrypInCount;
+ hcryp->CrypInCount = 0U;
+
+ CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF);
+ }
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
+ }
+ /* CCF flag indicating header phase AES processing completion
+ will be checked at the start of the next phase:
+ - payload phase (GCM or CCM when applicable)
+ - final phase (GMAC or CMAC).
+ This allows to avoid the Wait on Flag within the IRQ handling. */
+
+ /* Call input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP Output Data process complete callback
+ * for GCM, GMAC or CMAC chainging modes.
+ * @note This callback is called only in the payload phase.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ uint32_t difflength = 0U;
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for output request */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ /* Initiate additional transfer to wrap-up data feeding to the IP */
+ if (hcryp->CrypInCount != 0U)
+ {
+ /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
+ difflength = hcryp->CrypInCount;
+ hcryp->CrypInCount = 0U;
+
+ CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
+ }
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Mark that the payload phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
+
+ /* Call output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP communication error callback
+ * for GCM, GMAC or CMAC chainging modes.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ hcryp->State= HAL_CRYP_STATE_ERROR;
+ hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
+ HAL_CRYP_ErrorCallback(hcryp);
+ /* Clear Error Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);
+}
+
+/**
+ * @brief Handle CRYP block input/output data handling under interruption
+ * for GCM, GMAC or CMAC chaining modes.
+ * @note The function is called under interruption only, once
+ * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT().
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
+{
+ uint32_t inputaddr = 0x0U;
+ uint32_t outputaddr = 0x0U;
+ uint32_t index = 0x0U;
+ uint32_t addhoc_process = 0U;
+ uint32_t difflength = 0U;
+ uint32_t difflengthmod4 = 0U;
+ uint32_t mask[3] = {0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
+ uint32_t intermediate_data[4U] = {0U};
+
+ if(hcryp->State == HAL_CRYP_STATE_BUSY)
+ {
+ /*===========================*/
+ /* GCM/GMAC(/CCM) init phase */
+ /*===========================*/
+ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
+ {
+ /* Clear Computation Complete Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Mark that the initialization phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Call computation complete callback */
+ HAL_CRYPEx_ComputationCpltCallback(hcryp);
+ return HAL_OK;
+ }
+ /*=====================================*/
+ /* GCM/GMAC or (CCM/)CMAC header phase */
+ /*=====================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
+ {
+ /* Check if all input header data have been entered */
+ if (hcryp->CrypInCount == 0U)
+ {
+ /* Clear Computation Complete Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Call computation complete callback */
+ HAL_CRYPEx_ComputationCpltCallback(hcryp);
+
+ return HAL_OK;
+ }
+ /* If suspension flag has been raised, suspend processing */
+ else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+ {
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ /* reset SuspendRequest */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+ else /* Carry on feeding input data to the CRYP hardware block */
+ {
+ /* Clear Computation Complete Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Get the last Input data address */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Increment/decrement instance pointer/counter */
+ if (hcryp->CrypInCount < 16U)
+ {
+ difflength = hcryp->CrypInCount;
+ hcryp->CrypInCount = 0U;
+ addhoc_process = 1U;
+ difflengthmod4 = difflength%4U;
+ }
+ else
+ {
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+ }
+
+#if defined(AES_CR_NPBLB)
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
+#else
+ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
+#endif
+ {
+ if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
+ {
+ /* All B blocks will have been entered after the next
+ four DINR writing, so point at header buffer for
+ the next iteration */
+ hcryp->pCrypInBuffPtr = hcryp->Init.Header;
+ }
+ }
+
+ /* Write the Input block in the Data Input register */
+ if (addhoc_process == 0U)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ }
+ else
+ {
+ /* Header remainder has size less than 128 bits */
+ /* Enter complete words when possible */
+ for(index=0U; index < (difflength/4U); index ++)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ }
+ /* Enter incomplete word padded with zeroes if applicable
+ (case of header length not a multiple of 32-bits) */
+ if (difflengthmod4 != 0U)
+ {
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+ }
+ /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
+ for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
+ {
+ hcryp->Instance->DINR = 0U;
+ }
+ }
+
+ return HAL_OK;
+ }
+ }
+ /*=======================*/
+ /* GCM/CCM payload phase */
+ /*=======================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+ {
+ /* Get the last output data address */
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+
+ /* Specific handling to manage payload size less than 128 bits
+ when GCM (or CCM when applicable) encryption or decryption is selected.
+ Check here if the last block output data are read */
+#if defined(AES_CR_NPBLB)
+ if ((hcryp->CrypOutCount < 16U) && \
+ (hcryp->CrypOutCount > 0U))
+#else
+ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \
+ (hcryp->CrypOutCount < 16U) && \
+ (hcryp->CrypOutCount > 0U))
+#endif
+ {
+ addhoc_process = 1U;
+ difflength = hcryp->CrypOutCount;
+ difflengthmod4 = difflength%4U;
+ hcryp->CrypOutCount = 0U; /* mark that no more output data will be needed */
+ /* Retrieve intermediate data */
+ for(index=0U; index < 4U; index ++)
+ {
+ intermediate_data[index] = hcryp->Instance->DOUTR;
+ }
+ /* Retrieve last words of cyphered data */
+ /* First, retrieve complete output words */
+ for(index=0U; index < (difflength/4U); index ++)
+ {
+ *(uint32_t*)(outputaddr) = intermediate_data[index];
+ outputaddr+=4U;
+ }
+ /* Next, retrieve partial output word if applicable;
+ at the same time, start masking intermediate data
+ with a mask of zeros of same size than the padding
+ applied to the last block of payload */
+ if (difflengthmod4 != 0U)
+ {
+ intermediate_data[difflength/4U] &= mask[difflengthmod4-1U];
+ *(uint32_t*)(outputaddr) = intermediate_data[difflength/4U];
+ }
+
+#if !defined(AES_CR_NPBLB)
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+ {
+ /* Change again CHMOD configuration to GCM mode */
+ __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC);
+
+ /* Select FINAL phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
+
+ /* Before inserting the intermediate data, carry on masking operation
+ with a mask of zeros of same size than the padding applied to the last block of payload */
+ for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
+ {
+ intermediate_data[(difflength+3U)/4U+index] = 0U;
+ }
+
+ /* Insert intermediate data to trigger an additional DOUTR reading round */
+ /* Clear Computation Complete Flag before entering new block */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ for(index=0U; index < 4U; index ++)
+ {
+ hcryp->Instance->DINR = intermediate_data[index];
+ }
+ }
+ else
+#endif
+ {
+ /* Payload phase is now over */
+ /* Clear Computation Complete Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Mark that the payload phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Call computation complete callback */
+ HAL_CRYPEx_ComputationCpltCallback(hcryp);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ if (hcryp->CrypOutCount != 0U)
+ {
+ /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */
+ /* Retrieve the last block available from the CRYP hardware block:
+ read the output block from the Data Output Register */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+
+ /* Increment/decrement instance pointer/counter */
+ hcryp->pCrypOutBuffPtr += 16U;
+ hcryp->CrypOutCount -= 16U;
+ }
+#if !defined(AES_CR_NPBLB)
+ else
+ {
+ /* Software work-around: additional DOUTR reading round to discard the data */
+ for(index=0U; index < 4U; index ++)
+ {
+ intermediate_data[index] = hcryp->Instance->DOUTR;
+ }
+ }
+#endif
+ }
+
+ /* Check if all output text has been retrieved */
+ if (hcryp->CrypOutCount == 0U)
+ {
+#if !defined(AES_CR_NPBLB)
+ /* Make sure that software-work around is not running before disabling
+ the interruptions (indeed, if software work-around is running, the
+ interruptions must not be disabled to allow the additional DOUTR
+ reading round */
+ if (addhoc_process == 0U)
+#endif
+ {
+ /* Clear Computation Complete Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Mark that the payload phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Call computation complete callback */
+ HAL_CRYPEx_ComputationCpltCallback(hcryp);
+ }
+
+ return HAL_OK;
+ }
+ /* If suspension flag has been raised, suspend processing */
+ else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+ {
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ /* reset SuspendRequest */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_OK;
+ }
+ else /* Output data are still expected, carry on feeding the CRYP
+ hardware block with input data */
+ {
+ /* Clear Computation Complete Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Get the last Input data address */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Usual input data feeding case */
+ if (hcryp->CrypInCount < 16U)
+ {
+ difflength = (uint32_t) (hcryp->CrypInCount);
+ difflengthmod4 = difflength%4U;
+ hcryp->CrypInCount = 0U;
+
+#if defined(AES_CR_NPBLB)
+ /* In case of GCM encryption or CCM decryption, specify the number of padding
+ bytes in last block of payload */
+ if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
+ && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))
+ || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)
+ && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
+ {
+ /* Set NPBLB field in writing the number of padding bytes
+ for the last block of payload */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16U - difflength);
+ }
+#else
+ /* Software workaround applied to GCM encryption only */
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+ {
+ /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
+ __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
+ }
+#endif
+
+ /* Insert the last block (which size is inferior to 128 bits) padded with zeroes
+ to have a complete block of 128 bits */
+ for(index=0U; index < (difflength/4U); index ++)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ }
+ /* If required, manage input data size not multiple of 32 bits */
+ if (difflengthmod4 != 0U)
+ {
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1U]);
+ }
+ /* Wrap-up in padding with zero-words if applicable */
+ for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
+ {
+ hcryp->Instance->DINR = 0U;
+ }
+ }
+ else
+ {
+ hcryp->pCrypInBuffPtr += 16U;
+ hcryp->CrypInCount -= 16U;
+
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ }
+
+ return HAL_OK;
+ }
+ }
+ /*====================================*/
+ /* GCM/GMAC or (CCM/)CMAC final phase */
+ /*====================================*/
+ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
+ {
+ /* Clear Computation Complete Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ /* Get the last output data address */
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+
+ /* Retrieve the last expected data from the CRYP hardware block:
+ read the output block from the Data Output Register */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+
+ /* Disable Computation Complete Flag and Errors Interrupts */
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Mark that the header phase is over */
+ hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
+
+ /* Disable the Peripheral */
+ __HAL_CRYP_DISABLE();
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Call computation complete callback */
+ HAL_CRYPEx_ComputationCpltCallback(hcryp);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear Computation Complete Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ hcryp->State = HAL_CRYP_STATE_ERROR;
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Set the DMA configuration and start the DMA transfer
+ * for GCM, GMAC or CMAC chainging modes.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param inputaddr Address of the Input buffer.
+ * @param Size Size of the Input buffer un bytes, must be a multiple of 16.
+ * @param outputaddr Address of the Output buffer, null pointer when no output DMA stream
+ * has to be configured.
+ * @retval None
+ */
+static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+
+ /* Set the input CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_GCMCMAC_DMAInCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_GCMCMAC_DMAError;
+
+ if (outputaddr != 0U)
+ {
+ /* Set the output CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYP_GCMCMAC_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYP_GCMCMAC_DMAError;
+ }
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE();
+
+ /* Enable the DMA input stream */
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4U);
+
+ /* Enable the DMA input request */
+ SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+
+ if (outputaddr != 0U)
+ {
+ /* Enable the DMA output stream */
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4U);
+
+ /* Enable the DMA output request */
+ SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
+ }
+}
+
+/**
+ * @brief Write/read input/output data in polling mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Input Pointer to the Input buffer.
+ * @param Ilength Length of the Input buffer in bytes, must be a multiple of 16.
+ * @param Output Pointer to the returned buffer.
+ * @param Timeout Specify Timeout value.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+ uint32_t index = 0U;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
+
+
+ for(index=0U; (index < Ilength); index += 16U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ /* Read the Output block from the Data Output Register */
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ outputaddr+=4U;
+
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < Ilength))
+ {
+ /* Reset SuspendRequest */
+ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+
+ /* Save current reading and writing locations of Input and Output buffers */
+ hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
+ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hcryp->CrypInCount = Ilength - (index+16U);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+
+ return HAL_OK;
+ }
+
+ }
+ /* Return function status */
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Read derivative key in polling mode when CRYP hardware block is set
+ * in key derivation operating mode (mode 2).
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Output Pointer to the returned buffer.
+ * @param Timeout Specify Timeout value.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout)
+{
+ uint32_t outputaddr = (uint32_t)Output;
+
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ return HAL_TIMEOUT;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG( CRYP_CCF_CLEAR);
+
+ /* Read the derivative key from the AES_KEYRx registers */
+ if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+ {
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
+ outputaddr+=4U;
+ }
+
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the DMA configuration and start the DMA transfer.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param inputaddr Address of the Input buffer.
+ * @param Size Size of the Input buffer in bytes, must be a multiple of 16.
+ * @param outputaddr Address of the Output buffer.
+ * @retval None
+ */
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+ /* Enable the DMA input stream */
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4U);
+
+ /* Enable the DMA output stream */
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4U);
+
+ /* Enable In and Out DMA requests */
+ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE();
+}
+
+/**
+ * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA CRYP Input Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for input request */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ /* Call input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP Output Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for output request */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE();
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ hcryp->State= HAL_CRYP_STATE_ERROR;
+ hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
+ HAL_CRYP_ErrorCallback(hcryp);
+ /* Clear Error Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);
+}
+
+/**
+ * @brief Last header or payload block padding when size is not a multiple of 128 bits.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param difflength size remainder after having fed all complete 128-bit blocks.
+ * @param polling specifies whether or not polling on CCF must be done after having
+ * entered a complete block.
+ * @retval None
+ */
+static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling)
+{
+ uint32_t index = 0U;
+ uint32_t difflengthmod4 = difflength%4U;
+ uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ uint32_t mask[3U] = {0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
+ uint32_t intermediate_data[4U] = {0U};
+
+#if defined(AES_CR_NPBLB)
+ /* In case of GCM encryption or CCM decryption, specify the number of padding
+ bytes in last block of payload */
+ if (READ_BIT(hcryp->Instance->CR,AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)
+ {
+ if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
+ && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))
+ || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)
+ && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
+ {
+ /* Set NPBLB field in writing the number of padding bytes
+ for the last block of payload */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16U - difflength);
+ }
+ }
+#else
+ /* Software workaround applied to GCM encryption only */
+ if ((hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) &&
+ (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT))
+ {
+ /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
+ __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
+ }
+#endif
+
+ /* Wrap-up entering header or payload data */
+ /* Enter complete words when possible */
+ for(index=0U; index < (difflength/4U); index ++)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4U;
+ }
+ /* Enter incomplete word padded with zeroes if applicable
+ (case of header length not a multiple of 32-bits) */
+ if (difflengthmod4 != 0U)
+ {
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+ }
+ /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
+ for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
+ {
+ hcryp->Instance->DINR = 0U;
+ }
+
+ if (polling == CRYP_POLLING_ON)
+ {
+ if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ HAL_CRYP_ErrorCallback(hcryp);
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ }
+
+ /* if payload */
+ if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
+ {
+
+ /* Retrieve intermediate data */
+ for(index=0U; index < 4U; index ++)
+ {
+ intermediate_data[index] = hcryp->Instance->DOUTR;
+ }
+ /* Retrieve last words of cyphered data */
+ /* First, retrieve complete output words */
+ for(index=0U; index < (difflength/4U); index ++)
+ {
+ *(uint32_t*)(outputaddr) = intermediate_data[index];
+ outputaddr+=4U;
+ }
+ /* Next, retrieve partial output word if applicable;
+ at the same time, start masking intermediate data
+ with a mask of zeros of same size than the padding
+ applied to the last block of payload */
+ if (difflengthmod4 != 0U)
+ {
+ intermediate_data[difflength/4U] &= mask[difflengthmod4-1U];
+ *(uint32_t*)(outputaddr) = intermediate_data[difflength/4U];
+ }
+
+#if !defined(AES_CR_NPBLB)
+ /* Software workaround applied to GCM encryption only,
+ applicable for AES IP v2 version (where NPBLB is not defined) */
+ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
+ {
+ /* Change again CHMOD configuration to GCM mode */
+ __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC);
+
+ /* Select FINAL phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
+
+ /* Before inserting the intermediate data, carry on masking operation
+ with a mask of zeros of same size than the padding applied to the last block of payload */
+ for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
+ {
+ intermediate_data[(difflength+3U)/4U+index] = 0U;
+ }
+ /* Insert intermediate data */
+ for(index=0U; index < 4U; index ++)
+ {
+ hcryp->Instance->DINR = intermediate_data[index];
+ }
+
+ /* Wait for completion, and read data on DOUT. This data is to discard. */
+ if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+ HAL_CRYP_ErrorCallback(hcryp);
+ }
+
+ /* Read data to discard */
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ for(index=0U; index < 4U; index ++)
+ {
+ intermediate_data[index] = hcryp->Instance->DOUTR;
+ }
+
+ } /* if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) */
+#endif /* !defined(AES_CR_NPBLB) */
+ } /* if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) */
+
+}
+
+/**
+ * @}
+ */
+
+#endif /* AES */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,293 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cryp_ex.h
+ * @author MCD Application Team
+ * @brief Header file of CRYP HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRYP_EX_H
+#define __STM32F4xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+#if defined(CRYP)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYPEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported Constants
+ * @{
+ */
+
+/** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection
+ * @{
+ */
+#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT 0x00080000U
+#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT 0x00080004U
+#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT 0x00080008U
+#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT 0x0008000CU
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig
+ * @brief The phases are relevant only to AES-GCM and AES-CCM
+ * @{
+ */
+#define CRYP_PHASE_INIT 0x00000000U
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Set the phase: Init, header, payload, final.
+ * This is relevant only for GCM and CCM modes.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __PHASE__ The phase.
+ * @retval None
+ */
+#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
+ (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
+ }while(0)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* AES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group2
+ * @{
+ */
+
+void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
+ /* Private types -------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
+ * @{
+ */
+
+ /**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* CRYP */
+
+#if defined (AES)
+
+/** @addtogroup CRYPEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* CallBack functions ********************************************************/
+void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group2
+ * @{
+ */
+
+/* AES encryption/decryption processing functions ****************************/
+HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
+HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
+
+/* AES encryption/decryption/authentication processing functions *************/
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
+HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* AES suspension/resumption functions ***************************************/
+void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
+void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
+void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
+void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
+void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
+ * @{
+ */
+HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
+
+/**
+ * @}
+ */
+
+#endif /* AES */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRYP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,964 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dac.c
+ * @author MCD Application Team
+ * @brief DAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### DAC Peripheral features #####
+ ==============================================================================
+ [..]
+ *** DAC Channels ***
+ ====================
+ [..]
+ The device integrates two 12-bit Digital Analog Converters that can
+ be used independently or simultaneously (dual mode):
+ (#) DAC channel1 with DAC_OUT1 (PA4) as output
+ (#) DAC channel2 with DAC_OUT2 (PA5) as output
+
+ *** DAC Triggers ***
+ ====================
+ [..]
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
+ [..]
+ Digital to Analog conversion can be triggered by:
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
+ The used pin (GPIOx_Pin9) must be configured in input mode.
+
+ (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
+ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
+
+ (#) Software using DAC_TRIGGER_SOFTWARE
+
+ *** DAC Buffer mode feature ***
+ ===============================
+ [..]
+ Each DAC channel integrates an output buffer that can be used to
+ reduce the output impedance, and to drive external loads directly
+ without having to add an external operational amplifier.
+ To enable, the output buffer use
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+ [..]
+ (@) Refer to the device datasheet for more details about output
+ impedance value with and without output buffer.
+
+ *** DAC wave generation feature ***
+ ===================================
+ [..]
+ Both DAC channels can be used to generate
+ (#) Noise wave
+ (#) Triangle wave
+
+ *** DAC data format ***
+ =======================
+ [..]
+ The DAC data format can be:
+ (#) 8-bit right alignment using DAC_ALIGN_8B_R
+ (#) 12-bit left alignment using DAC_ALIGN_12B_L
+ (#) 12-bit right alignment using DAC_ALIGN_12B_R
+
+ *** DAC data value to voltage correspondence ***
+ ================================================
+ [..]
+ The analog output voltage on each DAC channel pin is determined
+ by the following equation:
+ DAC_OUTx = VREF+ * DOR / 4095
+ with DOR is the Data Output Register
+ VEF+ is the input voltage reference (refer to the device datasheet)
+ e.g. To set DAC_OUT1 to 0.7V, use
+ Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+ *** DMA requests ***
+ =====================
+ [..]
+ A DMA1 request can be generated when an external trigger (but not
+ a software trigger) occurs if DMA1 requests are enabled using
+ HAL_DAC_Start_DMA()
+ [..]
+ DMA1 requests are mapped as following:
+ (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
+ already configured
+ (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
+ already configured
+
+ -@- For Dual mode and specific signal (Triangle and noise) generation please
+ refer to Extension Features Driver description
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) DAC APB clock must be enabled to get write access to DAC
+ registers using HAL_DAC_Init()
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+ (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start()
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
+ (+) Stop the DAC peripheral using HAL_DAC_Stop()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
+ (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+ (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+
+ *** DAC HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DAC HAL driver.
+
+ (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
+ (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
+ (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
+ (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+
+ [..]
+ (@) You can refer to the DAC HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DAC DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+/* Private function prototypes -----------------------------------------------*/
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DAC.
+ (+) De-initialize the DAC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified parameters
+ * in the DAC_InitStruct.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ if(hdac->State == HAL_DAC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdac->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_DAC_MspInit(hdac);
+ }
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_DAC_MspDeInit(hdac);
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DAC MSP.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the DAC MSP.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ uint32_t tmp1 = 0U, tmp2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
+ tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
+ /* Check if software trigger enabled */
+ if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
+ {
+ /* Enable the selected DAC software conversion */
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
+ }
+ }
+ else
+ {
+ tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
+ tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
+ /* Check if software trigger enabled */
+ if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
+ {
+ /* Enable the selected DAC software conversion*/
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
+ }
+ }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param pData The destination peripheral Buffer address.
+ * @param Length The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ hdac->Instance->CR |= DAC_CR_DMAEN1;
+
+ /* Case of use of channel 1 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+ /* Enable the selected DAC channel2 DMA request */
+ hdac->Instance->CR |= DAC_CR_DMAEN2;
+
+ /* Case of use of channel 2 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Enable the DMA Stream */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+ }
+ else
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Disable the selected DAC channel DMA request */
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Disable the DMA Channel */
+ /* Channel1 is used */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+ }
+ else /* Channel2 is used for */
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+ }
+
+ /* Check if DMA Channel effectively disabled */
+ if(status != HAL_OK)
+ {
+ /* Update DAC state machine to error */
+ hdac->State = HAL_DAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Returns the DAC channel data output register value */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ return hdac->Instance->DOR1;
+ }
+ else
+ {
+ return hdac->Instance->DOR2;
+ }
+}
+
+/**
+ * @brief Handles DAC interrupt request
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+ /* Check underrun channel 1 flag */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to channel1 DMA underrun error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ hdac->Instance->CR &= ~DAC_CR_DMAEN1;
+
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
+ /* Check underrun channel 2 flag */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to channel2 DMA underrun error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
+
+ /* Disable the selected DAC channel1 DMA request */
+ hdac->Instance->CR &= ~DAC_CR_DMAEN2;
+
+ /* Error callback */
+ HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+ }
+}
+
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel1
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel1.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for channel1.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels.
+ (+) Set the specified data holding register value for DAC channel.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig DAC configuration structure.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Get the DAC CR value */
+ tmpreg1 = hdac->Instance->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value */
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << Channel;
+ /* Write to DAC CR */
+ hdac->Instance->CR = tmpreg1;
+ /* Disable wave generation */
+ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param Alignment Specifies the data alignment.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data Data to be loaded in the selected data holding register.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+ __IO uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)hdac->Instance;
+ if(Channel == DAC_CHANNEL_1)
+ {
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
+ }
+ else
+ {
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
+ }
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DAC state.
+ (+) Check the DAC Errors.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the DAC state
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL state
+ */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+{
+ /* Return DAC state */
+ return hdac->State;
+}
+
+
+/**
+ * @brief Return the DAC error code
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval DAC Error Code
+ */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+ return hdac->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DAC_ConvCpltCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DAC_ErrorCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
+ STM32F413xx || STM32F423xx */
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,412 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dac.h
+ * @author MCD Application Team
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DAC_H
+#define __STM32F4xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DAC_Exported_Types DAC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
+}HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
+ */
+typedef struct
+{
+ DAC_TypeDef *Instance; /*!< Register base address */
+
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
+
+ HAL_LockTypeDef Lock; /*!< DAC locking object */
+
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+
+ __IO uint32_t ErrorCode; /*!< DAC Error code */
+
+}DAC_HandleTypeDef;
+
+/**
+ * @brief DAC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+}DAC_ChannelConfTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+ * @{
+ */
+#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
+#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_trigger_selection DAC Trigger Selection
+ * @{
+ */
+
+#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer DAC Output Buffer
+ * @{
+ */
+#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
+#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection DAC Channel Selection
+ * @{
+ */
+#define DAC_CHANNEL_1 0x00000000U
+#define DAC_CHANNEL_2 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignment DAC Data Alignment
+ * @{
+ */
+#define DAC_ALIGN_12B_R 0x00000000U
+#define DAC_ALIGN_12B_L 0x00000004U
+#define DAC_ALIGN_8B_R 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition DAC Flags Definition
+ * @{
+ */
+#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_IT_definition DAC IT Definition
+ * @{
+ */
+#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @brief Reset DAC handle state
+ * @param __HANDLE__ specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __DAC_Channel__ specifies the DAC channel
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Disable the DAC channel
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __DAC_Channel__ specifies the DAC channel.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Enable the DAC interrupt
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
+ * @param __HANDLE__ DAC handle
+ * @param __INTERRUPT__ DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected DAC's flag status.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
+ * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+ * @retval None
+ */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the DAC's flag.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
+ * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+ * @retval None
+ */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+/**
+ * @}
+ */
+
+/* Include DAC HAL Extension module */
+#include "stm32f4xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions *********************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
+
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
+
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DAC_Private_Functions DAC Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
+ STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,389 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dac_ex.c
+ * @author MCD Application Team
+ * @brief DAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of DAC extension peripheral:
+ * + Extended features functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
+ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+ HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
+ (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DACEx DACEx
+ * @brief DAC driver modules
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DACEx_Exported_Functions DAC Exported Functions
+ * @{
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended features functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+ (+) Get result of dual mode conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+ uint32_t tmp = 0U;
+
+ tmp |= hdac->Instance->DOR1;
+
+ tmp |= hdac->Instance->DOR2 << 16U;
+
+ /* Returns the DAC channel data output register value */
+ return tmp;
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * DAC_CHANNEL_1 / DAC_CHANNEL_2
+ * @param Amplitude Select max triangle amplitude.
+ * This parameter can be one of the following values:
+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * DAC_CHANNEL_1 / DAC_CHANNEL_2
+ * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
+ * This parameter can be one of the following values:
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specified data holding register value for dual DAC channel.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Alignment Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register.
+ * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register.
+ * @note In dual mode, a unique register access is required to write in both
+ * DAC channels at the same time.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+ uint32_t data = 0U, tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (Alignment == DAC_ALIGN_8B_R)
+ {
+ data = ((uint32_t)Data2 << 8U) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16U) | Data1;
+ }
+
+ tmp = (uint32_t)hdac->Instance;
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel2
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel2.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for channel2.
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DACEx_ConvCpltCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DACEx_ErrorCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
+ STM32F413xx || STM32F423xx */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dac.h
+ * @author MCD Application Team
+ * @brief Header file of DAC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DAC_EX_H
+#define __STM32F4xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DACEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DACEx_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
+ * @{
+ */
+#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group1
+ * @{
+ */
+/* Extension features functions ***********************************************/
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DACEx_Private_Macros DAC Private Macros
+ * @{
+ */
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DAC Private Functions
+ * @{
+ */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx ||\
+ STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,885 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi.c
+ * @author MCD Application Team
+ * @brief DCMI HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital Camera Interface (DCMI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The sequence below describes how to use this driver to capture image
+ from a camera module connected to the DCMI Interface.
+ This sequence does not take into account the configuration of the
+ camera module, which should be made before to configure and enable
+ the DCMI to capture images.
+
+ (#) Program the required configuration through following parameters:
+ horizontal and vertical polarity, pixel clock polarity, Capture Rate,
+ Synchronization Mode, code of the frame delimiter and data width
+ using HAL_DCMI_Init() function.
+
+ (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
+ register to the destination memory buffer.
+
+ (#) Program the required configuration through following parameters:
+ DCMI mode, destination memory Buffer address and the data length
+ and enable capture using HAL_DCMI_Start_DMA() function.
+
+ (#) Optionally, configure and Enable the CROP feature to select a rectangular
+ window from the received image using HAL_DCMI_ConfigCrop()
+ and HAL_DCMI_EnableCROP() functions
+
+ (#) The capture can be stopped using HAL_DCMI_Stop() function.
+
+ (#) To control DCMI state you can use the function HAL_DCMI_GetState().
+
+ *** DCMI HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DCMI HAL driver.
+
+ (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
+ (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
+ (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
+ (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
+ (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
+ (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
+ (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DCMI HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup DCMI DCMI
+ * @brief DCMI HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HAL_TIMEOUT_DCMI_STOP 14U /* Set timeout to 1s */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
+ * @{
+ */
+
+/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DCMI
+ (+) De-initialize the DCMI
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DCMI according to the specified
+ * parameters in the DCMI_InitTypeDef and create the associated handle.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Check the DCMI peripheral state */
+ if(hdcmi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
+ assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
+ assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
+ assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
+ assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
+ assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
+ assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
+ assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
+
+ if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdcmi->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_DCMI_MspInit(hdcmi);
+ }
+
+ /* Change the DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Set DCMI parameters */
+ /* Configures the HS, VS, DE and PC polarity */
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |
+ DCMI_CR_ESS);
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
+ hdcmi->Init.JPEGMode);
+
+ if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+ {
+ hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |
+ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
+ }
+
+ /* Enable the Line, Vsync, Error and Overrun interrupts */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
+
+ /* Update error code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the DCMI peripheral registers to their default reset
+ * values.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
+{
+ /* DeInit the low level hardware */
+ HAL_DCMI_MspDeInit(hdcmi);
+
+ /* Update error code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DCMI MSP.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the DCMI MSP.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure destination address and data length and
+ Enables DCMI DMA request and enables DCMI capture
+ (+) Stop the DCMI capture.
+ (+) Handles DCMI interrupt request.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DCMI DMA request and enables DCMI capture
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @param DCMI_Mode DCMI capture mode snapshot or continuous grab.
+ * @param pData The destination memory Buffer address (LCD Frame buffer).
+ * @param Length The length of capture to be transferred.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
+{
+ /* Initialize the second memory address */
+ uint32_t SecondMemAddress = 0U;
+
+ /* Check function parameters */
+ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
+
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Enable DCMI by setting DCMIEN bit */
+ __HAL_DCMI_ENABLE(hdcmi);
+
+ /* Configure the DCMI Mode */
+ hdcmi->Instance->CR &= ~(DCMI_CR_CM);
+ hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
+
+ /* Set the DMA memory0 conversion complete callback */
+ hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
+
+ /* Set the dma abort callback */
+ hdcmi->DMA_Handle->XferAbortCallback = NULL;
+
+ /* Reset transfer counters value */
+ hdcmi->XferCount = 0U;
+ hdcmi->XferTransferNumber = 0U;
+
+ if(Length <= 0xFFFFU)
+ {
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
+ }
+ else /* DCMI_DOUBLE_BUFFER Mode */
+ {
+ /* Set the DMA memory1 conversion complete callback */
+ hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
+
+ /* Initialize transfer parameters */
+ hdcmi->XferCount = 1U;
+ hdcmi->XferSize = Length;
+ hdcmi->pBuffPtr = pData;
+
+ /* Get the number of buffer */
+ while(hdcmi->XferSize > 0xFFFFU)
+ {
+ hdcmi->XferSize = (hdcmi->XferSize/2U);
+ hdcmi->XferCount = hdcmi->XferCount*2U;
+ }
+
+ /* Update DCMI counter and transfer number*/
+ hdcmi->XferCount = (hdcmi->XferCount - 2U);
+ hdcmi->XferTransferNumber = hdcmi->XferCount;
+
+ /* Update second memory address */
+ SecondMemAddress = (uint32_t)(pData + (4U*hdcmi->XferSize));
+
+ /* Start DMA multi buffer transfer */
+ HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
+ }
+
+ /* Enable Capture */
+ hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable DCMI DMA request and Disable DCMI capture
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
+{
+ __IO uint32_t count = SystemCoreClock / HAL_TIMEOUT_DCMI_STOP;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Disable Capture */
+ hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
+
+ /* Check if the DCMI capture effectively disabled */
+ do
+ {
+ if (count-- == 0U)
+ {
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+
+ status = HAL_TIMEOUT;
+ }
+ }
+ while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+
+ /* Disable the DCMI */
+ __HAL_DCMI_DISABLE(hdcmi);
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdcmi->DMA_Handle);
+
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
+
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Suspend DCMI capture
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
+{
+ __IO uint32_t count = SystemCoreClock / HAL_TIMEOUT_DCMI_STOP;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdcmi);
+
+ if(hdcmi->State == HAL_DCMI_STATE_BUSY)
+ {
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
+
+ /* Disable Capture */
+ hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
+
+ /* Check if the DCMI capture effectively disabled */
+ do
+ {
+ if (count-- == 0U)
+ {
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+ while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Resume DCMI capture
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdcmi);
+
+ if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
+ {
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Disable Capture */
+ hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles DCMI interrupt request.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for the DCMI.
+ * @retval None
+ */
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
+{
+ uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
+
+ /* Synchronization error interrupt management *******************************/
+ if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
+ {
+ /* Clear the Synchronization error flag */
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
+
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
+
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_ERROR;
+
+ /* Set the synchronization error callback */
+ hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
+
+ /* Abort the DMA Transfer */
+ HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
+ }
+ /* Overflow interrupt management ********************************************/
+ if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
+ {
+ /* Clear the Overflow flag */
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
+
+ /* Update error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
+
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_ERROR;
+
+ /* Set the overflow callback */
+ hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
+
+ /* Abort the DMA Transfer */
+ HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
+ }
+ /* Line Interrupt management ************************************************/
+ if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
+ {
+ /* Clear the Line interrupt flag */
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
+
+ /* Line interrupt Callback */
+ HAL_DCMI_LineEventCallback(hdcmi);
+ }
+ /* VSYNC interrupt management ***********************************************/
+ if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
+ {
+ /* Clear the VSYNC flag */
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
+
+ /* VSYNC Callback */
+ HAL_DCMI_VsyncEventCallback(hdcmi);
+ }
+ /* FRAME interrupt management ***********************************************/
+ if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
+ {
+ /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
+ if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+ {
+ /* Disable the Line, Vsync, Error and Overrun interrupts */
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
+ }
+
+ /* Disable the Frame interrupt */
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+ /* Frame Callback */
+ HAL_DCMI_FrameEventCallback(hdcmi);
+ }
+}
+
+/**
+ * @brief Error DCMI callback.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Line Event callback.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_LineEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief VSYNC Event callback.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_VsyncEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Frame Event callback.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval None
+ */
+__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DCMI_FrameEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+[..] This section provides functions allowing to:
+ (+) Configure the CROP feature.
+ (+) Enable/Disable the CROP feature.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the DCMI CROP coordinate.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @param X0 DCMI window X offset
+ * @param Y0 DCMI window Y offset
+ * @param XSize DCMI Pixel per line
+ * @param YSize DCMI Line number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
+ assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
+ assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
+ assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
+
+ /* Configure CROP */
+ hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));
+ hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));
+
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Crop feature.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Disable DCMI Crop feature */
+ hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
+
+ /* Change the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the Crop feature.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Enable DCMI Crop feature */
+ hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
+
+ /* Change the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DCMI state.
+ (+) Get the specific DCMI error flag.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the DCMI state
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL state
+ */
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
+{
+ return hdcmi->State;
+}
+
+/**
+ * @brief Return the DCMI error code
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval DCMI Error Code
+ */
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
+{
+ return hdcmi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmp = 0U;
+
+ DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if(hdcmi->XferCount != 0U)
+ {
+ /* Update memory 0 address location */
+ tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
+ if(((hdcmi->XferCount % 2U) == 0U) && (tmp != 0U))
+ {
+ tmp = hdcmi->DMA_Handle->Instance->M0AR;
+ HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY0);
+ hdcmi->XferCount--;
+ }
+ /* Update memory 1 address location */
+ else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0U)
+ {
+ tmp = hdcmi->DMA_Handle->Instance->M1AR;
+ HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY1);
+ hdcmi->XferCount--;
+ }
+ }
+ /* Update memory 0 address location */
+ else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0U)
+ {
+ hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
+ }
+ /* Update memory 1 address location */
+ else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0U)
+ {
+ tmp = hdcmi->pBuffPtr;
+ hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4U*hdcmi->XferSize));
+ hdcmi->XferCount = hdcmi->XferTransferNumber;
+ }
+
+ /* Check if the frame is transferred */
+ if(hdcmi->XferCount == hdcmi->XferTransferNumber)
+ {
+ /* Enable the Frame interrupt */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+ /* When snapshot mode, set dcmi state to ready */
+ if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+ {
+ hdcmi->State= HAL_DCMI_STATE_READY;
+ }
+ }
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
+ {
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ }
+
+ /* DCMI error Callback */
+ HAL_DCMI_ErrorCallback(hdcmi);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
+#endif /* HAL_DCMI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,535 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi.h
+ * @author MCD Application Team
+ * @brief Header file of DCMI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DCMI_H
+#define __STM32F4xx_HAL_DCMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/* Include DCMI HAL Extended module */
+/* (include on top of file since DCMI structures are defined in extended file) */
+#include "stm32f4xx_hal_dcmi_ex.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DCMI DCMI
+ * @brief DCMI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Types DCMI Exported Types
+ * @{
+ */
+/**
+ * @brief HAL DCMI State structures definition
+ */
+typedef enum
+{
+ HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
+ HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
+ HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
+ HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
+ HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
+ HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
+}HAL_DCMI_StateTypeDef;
+
+/**
+ * @brief DCMI handle Structure definition
+ */
+typedef struct
+{
+ DCMI_TypeDef *Instance; /*!< DCMI Register base address */
+
+ DCMI_InitTypeDef Init; /*!< DCMI parameters */
+
+ HAL_LockTypeDef Lock; /*!< DCMI locking object */
+
+ __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
+
+ __IO uint32_t XferCount; /*!< DMA transfer counter */
+
+ __IO uint32_t XferSize; /*!< DMA transfer size */
+
+ uint32_t XferTransferNumber; /*!< DMA transfer number */
+
+ uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
+
+ __IO uint32_t ErrorCode; /*!< DCMI Error code */
+
+}DCMI_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
+ * @{
+ */
+
+/** @defgroup DCMI_Error_Code DCMI Error Code
+ * @{
+ */
+#define HAL_DCMI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DCMI_ERROR_OVR 0x00000001U /*!< Overrun error */
+#define HAL_DCMI_ERROR_SYNC 0x00000002U /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
+#define HAL_DCMI_ERROR_DMA 0x00000040U /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
+ * @{
+ */
+#define DCMI_MODE_CONTINUOUS 0x00000000U /*!< The received data are transferred continuously
+ into the destination memory through the DMA */
+#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
+ frame and then transfers a single frame through the DMA */
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
+ * @{
+ */
+#define DCMI_SYNCHRO_HARDWARE 0x00000000U /*!< Hardware synchronization data capture (frame/line start/stop)
+ is synchronized with the HSYNC/VSYNC signals */
+#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
+ synchronization codes embedded in the data flow */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
+ * @{
+ */
+#define DCMI_PCKPOLARITY_FALLING 0x00000000U /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
+ * @{
+ */
+#define DCMI_VSPOLARITY_LOW 0x00000000U /*!< Vertical synchronization active Low */
+#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
+ * @{
+ */
+#define DCMI_HSPOLARITY_LOW 0x00000000U /*!< Horizontal synchronization active Low */
+#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
+ * @{
+ */
+#define DCMI_JPEG_DISABLE 0x00000000U /*!< Mode JPEG Disabled */
+#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
+ * @{
+ */
+#define DCMI_CR_ALL_FRAME 0x00000000U /*!< All frames are captured */
+#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
+#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
+ * @{
+ */
+#define DCMI_EXTEND_DATA_8B 0x00000000U /*!< Interface captures 8-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
+ * @{
+ */
+#define DCMI_WINDOW_COORDINATE 0x3FFFU /*!< Window coordinate */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Window_Height DCMI Window Height
+ * @{
+ */
+#define DCMI_WINDOW_HEIGHT 0x1FFFU /*!< Window Height */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Window_Vertical_Line DCMI Window Vertical Line
+ * @{
+ */
+#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)DCMI_CWSIZE_VLINE_Pos /*!< Required left shift to set crop window vertical line count */
+#define DCMI_POSITION_CWSTRT_VST (uint32_t)DCMI_CWSTRT_VST_Pos /*!< Required left shift to set crop window vertical start line count */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
+ * @{
+ */
+#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
+#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
+#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
+#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
+#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Flags DCMI Flags
+ * @{
+ */
+
+/**
+ * @brief DCMI SR register
+ */
+#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
+#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
+#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
+/**
+ * @brief DCMI RIS register
+ */
+#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS) /*!< Frame capture complete interrupt flag */
+#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RISR_OVR_RIS) /*!< Overrun interrupt flag */
+#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS) /*!< Synchronization error interrupt flag */
+#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS) /*!< VSYNC interrupt flag */
+#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS) /*!< Line interrupt flag */
+/**
+ * @brief DCMI MIS register
+ */
+#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
+#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
+#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
+#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
+#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
+ * @{
+ */
+
+/** @brief Reset DCMI handle state
+ * @param __HANDLE__ specifies the DCMI handle.
+ * @retval None
+ */
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+
+/**
+ * @brief Enable the DCMI.
+ * @param __HANDLE__ DCMI handle
+ * @retval None
+ */
+#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
+
+/**
+ * @brief Disable the DCMI.
+ * @param __HANDLE__ DCMI handle
+ * @retval None
+ */
+#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the DCMI pending flag.
+ * @param __HANDLE__ DCMI handle
+ * @param __FLAG__ Get the specified flag.
+ * This parameter can be one of the following values (no combination allowed)
+ * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
+ * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
+ * @arg DCMI_FLAG_FNE: FIFO empty flag
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+ * @arg DCMI_FLAG_OVRRI: Overrun flag mask
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+ * @arg DCMI_FLAG_LINERI: Line flag mask
+ * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
+ * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
+ * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
+ * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
+ * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
+ * @retval The state of FLAG.
+ */
+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
+((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0U)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
+ (((__FLAG__) & DCMI_SR_INDEX) == 0x0U)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
+
+/**
+ * @brief Clear the DCMI pending flags.
+ * @param __HANDLE__ DCMI handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+ * @arg DCMI_FLAG_OVRRI: Overrun flag mask
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+ * @arg DCMI_FLAG_LINERI: Line flag mask
+ * @retval None
+ */
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable the specified DCMI interrupts.
+ * @param __HANDLE__ DCMI handle
+ * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVR: Overrun interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval None
+ */
+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified DCMI interrupts.
+ * @param __HANDLE__ DCMI handle
+ * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVR: Overrun interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval None
+ */
+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified DCMI interrupt has occurred or not.
+ * @param __HANDLE__ DCMI handle
+ * @param __INTERRUPT__ specifies the DCMI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVR: Overrun interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval The state of INTERRUPT.
+ */
+#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
+ * @{
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
+void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
+void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
+HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Constants DCMI Private Constants
+ * @{
+ */
+#define DCMI_MIS_INDEX 0x1000U /*!< DCMI MIS register index */
+#define DCMI_SR_INDEX 0x2000U /*!< DCMI SR register index */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Macros DCMI Private Macros
+ * @{
+ */
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+ ((MODE) == DCMI_MODE_SNAPSHOT))
+
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+ ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+ ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+ ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
+ ((DATA) == DCMI_EXTEND_DATA_10B) || \
+ ((DATA) == DCMI_EXTEND_DATA_12B) || \
+ ((DATA) == DCMI_EXTEND_DATA_14B))
+
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DCMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,181 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi_ex.c
+ * @author MCD Application Team
+ * @brief DCMI Extension HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities of DCMI extension peripheral:
+ * + Extension features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### DCMI peripheral extension features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the DCMI interface for STM32F446xx
+ devices contains the following additional features :
+
+ (+) Support of Black and White cameras
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to manage the Black and White feature
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup DCMIEx DCMIEx
+ * @brief DCMI Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) ||\
+ defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DCMIEx_Exported_Functions DCMI Extended Exported Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the DCMI according to the specified
+ * parameters in the DCMI_InitTypeDef and create the associated handle.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+{
+ /* Check the DCMI peripheral state */
+ if(hdcmi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
+ assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
+ assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
+ assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
+ assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
+ assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
+ assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
+ assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
+ assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
+ assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
+ assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_DCMI_MspInit(hdcmi);
+ }
+
+ /* Change the DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+ /* Configures the HS, VS, DE and PC polarity */
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
+ DCMI_CR_ESS
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
+ DCMI_CR_LSM | DCMI_CR_OELS
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ );
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
+ hdcmi->Init.JPEGMode
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ | hdcmi->Init.ByteSelectMode |\
+ hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
+ hdcmi->Init.LineSelectStart
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ );
+ if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+ {
+ hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |
+ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
+
+ }
+
+ /* Enable the Line, Vsync, Error and Overrun interrupts */
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
+
+ /* Update error code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+ /* Initialize the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx ||\
+ STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* HAL_DCMI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,228 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi_ex.h
+ * @author MCD Application Team
+ * @brief Header file of DCMI Extension HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DCMI_EX_H
+#define __STM32F4xx_HAL_DCMI_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DCMIEx
+ * @brief DCMI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DCMIEx_Exported_Types DCMI Extended Exported Types
+ * @{
+ */
+/**
+ * @brief DCMIEx Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+ uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
+ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
+ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
+}DCMI_CodesInitTypeDef;
+
+/**
+ * @brief DCMI Init structure definition
+ */
+typedef struct
+{
+ uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+ This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+ uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
+ This parameter can be a value of @ref DCMI_PIXCK_Polarity */
+
+ uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_VSYNC_Polarity */
+
+ uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_HSYNC_Polarity */
+
+ uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+ This parameter can be a value of @ref DCMI_Capture_Rate */
+
+ uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+ This parameter can be a value of @ref DCMI_Extended_Data_Mode */
+
+ DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
+
+ uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode
+ This parameter can be a value of @ref DCMI_MODE_JPEG */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
+ This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */
+
+ uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
+ This parameter can be a value of @ref DCMIEx_Byte_Select_Start */
+
+ uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
+ This parameter can be a value of @ref DCMIEx_Line_Select_Mode */
+
+ uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
+ This parameter can be a value of @ref DCMIEx_Line_Select_Start */
+
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+}DCMI_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants
+ * @{
+ */
+
+/** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode
+ * @{
+ */
+#define DCMI_BSM_ALL 0x00000000U /*!< Interface captures all received data */
+#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
+#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
+#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start
+ * @{
+ */
+#define DCMI_OEBS_ODD 0x00000000U /*!< Interface captures first data from the frame/line start, second one being dropped */
+#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode
+ * @{
+ */
+#define DCMI_LSM_ALL 0x00000000U /*!< Interface captures all received lines */
+#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
+
+/**
+ * @}
+ */
+
+/** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start
+ * @{
+ */
+#define DCMI_OELS_ODD 0x00000000U /*!< Interface captures first line from the frame start, second one being dropped */
+#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+#define DCMI_POSITION_ESCR_LSC (uint32_t)DCMI_ESCR_LSC_Pos /*!< Required left shift to set line start delimiter */
+#define DCMI_POSITION_ESCR_LEC (uint32_t)DCMI_ESCR_LEC_Pos /*!< Required left shift to set line end delimiter */
+#define DCMI_POSITION_ESCR_FEC (uint32_t)DCMI_ESCR_FEC_Pos /*!< Required left shift to set frame end delimiter */
+
+/* Private macro -------------------------------------------------------------*/
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros
+ * @{
+ */
+#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
+ ((MODE) == DCMI_BSM_OTHER) || \
+ ((MODE) == DCMI_BSM_ALTERNATE_4) || \
+ ((MODE) == DCMI_BSM_ALTERNATE_2))
+
+#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
+ ((POLARITY) == DCMI_OEBS_EVEN))
+
+#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
+ ((MODE) == DCMI_LSM_ALTERNATE_2))
+
+#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
+ ((POLARITY) == DCMI_OELS_EVEN))
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DCMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,239 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_def.h
+ * @author MCD Application Team
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DEF
+#define __STM32F4xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+/* MBED */
+#include "stm32_hal_legacy.h"
+/* MBED */
+#include <stdio.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00U,
+ HAL_ERROR = 0x01U,
+ HAL_BUSY = 0x02U,
+ HAL_TIMEOUT = 0x03U
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00U,
+ HAL_LOCKED = 0x01U
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#define HAL_MAX_DELAY 0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
+ } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__ specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it as parameter
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to set to 0 the Handle's "State" field.
+ * Otherwise, "State" field may have any random value and the first time the function
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ * (i.e. HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware: instead of calling
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+ /* Reserved for future use */
+ #error "USE_RTOS should be 0 in the current HAL release"
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0U)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0U)
+
+/* MBED */
+#if defined (__CC_ARM)
+#pragma diag_suppress 3731
+#endif
+static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
+{
+ uint32_t newValue;
+ do {
+ newValue = (uint32_t)__LDREXW(ptr) | mask;
+
+ } while (__STREXW(newValue, ptr));
+}
+
+
+static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
+{
+ uint32_t newValue;
+ do {
+ newValue = (uint32_t)__LDREXW(ptr) &~mask;
+
+ } while (__STREXW(newValue, ptr));
+}
+/* MBED */
+
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+
+/**
+ * @brief __RAM_FUNC definition
+ */
+#if defined ( __CC_ARM )
+/* ARM Compiler
+ ------------
+ RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate source module.
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'
+ area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+ dialog.
+*/
+#define __RAM_FUNC HAL_StatusTypeDef
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+
+#elif defined ( __GNUC__ )
+/* GNU Compiler
+ ------------
+ RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F4xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,3839 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dfsdm.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Digital Filter for Sigma-Delta Modulators
+ * (DFSDM) peripherals:
+ * + Initialization and configuration of channels and filters
+ * + Regular channels configuration
+ * + Injected channels configuration
+ * + Regular/Injected Channels DMA Configuration
+ * + Interrupts and flags management
+ * + Analog watchdog feature
+ * + Short-circuit detector feature
+ * + Extremes detector feature
+ * + Clock absence detector feature
+ * + Break generation on analog watchdog or short-circuit event
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ *** Channel initialization ***
+ ==============================
+ [..]
+ (#) User has first to initialize channels (before filters initialization).
+ (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
+ (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
+ (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
+ (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (#) Configure the output clock, input, serial interface, analog watchdog,
+ offset and data right bit shift parameters for this channel using the
+ HAL_DFSDM_ChannelInit() function.
+
+ *** Channel clock absence detector ***
+ ======================================
+ [..]
+ (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
+ HAL_DFSDM_ChannelCkabStart_IT().
+ (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
+ absence.
+ (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
+ clock absence is detected.
+ (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
+ HAL_DFSDM_ChannelCkabStop_IT().
+ (#) Please note that the same mode (polling or interrupt) has to be used
+ for all channels because the channels are sharing the same interrupt.
+ (#) Please note also that in interrupt mode, if clock absence detector is
+ stopped for one channel, interrupt will be disabled for all channels.
+
+ *** Channel short circuit detector ***
+ ======================================
+ [..]
+ (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
+ or HAL_DFSDM_ChannelScdStart_IT().
+ (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
+ circuit.
+ (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
+ short circuit is detected.
+ (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
+ or HAL_DFSDM_ChannelScdStop_IT().
+ (#) Please note that the same mode (polling or interrupt) has to be used
+ for all channels because the channels are sharing the same interrupt.
+ (#) Please note also that in interrupt mode, if short circuit detector is
+ stopped for one channel, interrupt will be disabled for all channels.
+
+ *** Channel analog watchdog value ***
+ =====================================
+ [..]
+ (#) Get analog watchdog filter value of a channel using
+ HAL_DFSDM_ChannelGetAwdValue().
+
+ *** Channel offset value ***
+ =====================================
+ [..]
+ (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
+
+ *** Filter initialization ***
+ =============================
+ [..]
+ (#) After channel initialization, user has to init filters.
+ (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
+ (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ Please note that DFSDMz_FLT0 global interrupt could be already
+ enabled if interrupt is used for channel.
+ (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
+ with DFSDMz filter handle using __HAL_LINKDMA().
+ (#) Configure the regular conversion, injected conversion and filter
+ parameters for this filter using the HAL_DFSDM_FilterInit() function.
+
+ *** Filter regular channel conversion ***
+ =========================================
+ [..]
+ (#) Select regular channel and enable/disable continuous mode using
+ HAL_DFSDM_FilterConfigRegChannel().
+ (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
+ HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
+ HAL_DFSDM_FilterRegularMsbStart_DMA().
+ (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
+ the end of regular conversion.
+ (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
+ at the end of regular conversion.
+ (#) Get value of regular conversion and corresponding channel using
+ HAL_DFSDM_FilterGetRegularValue().
+ (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
+ HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
+ half transfer and at the transfer complete. Please note that
+ HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
+ circular mode.
+ (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
+ HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
+
+ *** Filter injected channels conversion ***
+ ===========================================
+ [..]
+ (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
+ (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
+ HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
+ HAL_DFSDM_FilterInjectedMsbStart_DMA().
+ (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
+ the end of injected conversion.
+ (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
+ at the end of injected conversion.
+ (#) Get value of injected conversion and corresponding channel using
+ HAL_DFSDM_FilterGetInjectedValue().
+ (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
+ HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
+ half transfer and at the transfer complete. Please note that
+ HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
+ circular mode.
+ (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
+ HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
+
+ *** Filter analog watchdog ***
+ ==============================
+ [..]
+ (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
+ (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
+ (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
+
+ *** Filter extreme detector ***
+ ===============================
+ [..]
+ (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
+ (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
+ (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
+ (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
+
+ *** Filter conversion time ***
+ ==============================
+ [..]
+ (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+#ifdef HAL_DFSDM_MODULE_ENABLED
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup DFSDM DFSDM
+ * @brief DFSDM HAL driver module
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Define DFSDM Private Define
+ * @{
+ */
+
+#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8U
+
+#define DFSDM_MSB_MASK 0xFFFF0000U
+#define DFSDM_LSB_MASK 0x0000FFFFU
+#define DFSDM_CKAB_TIMEOUT 5000U
+#define DFSDM1_CHANNEL_NUMBER 4U
+#if defined (DFSDM2_Channel0)
+#define DFSDM2_CHANNEL_NUMBER 8U
+#endif /* DFSDM2_Channel0 */
+
+/**
+ * @}
+ */
+/** @addtogroup DFSDM_Private_Macros
+* @{
+*/
+
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Variables DFSDM Private Variables
+ * @{
+ */
+__IO uint32_t v_dfsdm1ChannelCounter = 0U;
+DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
+
+#if defined (DFSDM2_Channel0)
+__IO uint32_t v_dfsdm2ChannelCounter = 0U;
+DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NULL};
+#endif /* DFSDM2_Channel0 */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DFSDM_Private_Functions DFSDM Private Functions
+ * @{
+ */
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
+static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
+static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
+static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
+static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
+static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
+static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
+static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
+ * @{
+ */
+
+/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
+ * @brief Channel initialization and de-initialization functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Channel initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the DFSDM channel.
+ (+) De-initialize the DFSDM channel.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DFSDM channel according to the specified parameters
+ * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+#if defined(DFSDM2_Channel0)
+ __IO uint32_t* channelCounterPtr;
+ DFSDM_Channel_HandleTypeDef **channelHandleTable;
+ DFSDM_Channel_TypeDef* channel0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check DFSDM Channel handle */
+ if(hdfsdm_channel == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
+ assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
+ assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
+ assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
+ assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
+ assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
+ assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
+ assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
+ assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
+ assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
+
+#if defined(DFSDM2_Channel0)
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ channelCounterPtr = &v_dfsdm1ChannelCounter;
+ channelHandleTable = a_dfsdm1ChannelHandle;
+ channel0Instance = DFSDM1_Channel0;
+ }
+ else
+ {
+ channelCounterPtr = &v_dfsdm2ChannelCounter;
+ channelHandleTable = a_dfsdm2ChannelHandle;
+ channel0Instance = DFSDM2_Channel0;
+ }
+
+ /* Check that channel has not been already initialized */
+ if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Call MSP init function */
+ HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
+
+ /* Update the channel counter */
+ (*channelCounterPtr)++;
+
+ /* Configure output serial clock and enable global DFSDM interface only for first channel */
+ if(*channelCounterPtr == 1U)
+ {
+ assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
+ /* Set the output serial clock source */
+ channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
+ channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
+
+ /* Reset clock divider */
+ channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
+ if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
+ {
+ assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
+ /* Set the output clock divider */
+ channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
+ DFSDM_CHCFGR1_CKOUTDIV_Pos);
+ }
+
+ /* enable the DFSDM global interface */
+ channel0Instance->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
+ }
+
+ /* Set channel input parameters */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
+ DFSDM_CHCFGR1_CHINSEL);
+ hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
+ hdfsdm_channel->Init.Input.DataPacking |
+ hdfsdm_channel->Init.Input.Pins);
+
+ /* Set serial interface parameters */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
+ hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
+ hdfsdm_channel->Init.SerialInterface.SpiClock);
+
+ /* Set analog watchdog parameters */
+ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
+ hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
+ ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
+
+ /* Set channel offset and right bit shift */
+ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
+ hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
+ (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
+
+ /* Enable DFSDM channel */
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
+
+ /* Set DFSDM Channel to ready state */
+ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
+
+ /* Store channel handle in DFSDM channel handle table */
+ channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
+
+#else
+ /* Check that channel has not been already initialized */
+ if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Call MSP init function */
+ HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
+
+ /* Update the channel counter */
+ v_dfsdm1ChannelCounter++;
+
+ /* Configure output serial clock and enable global DFSDM interface only for first channel */
+ if(v_dfsdm1ChannelCounter == 1U)
+ {
+ assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
+ /* Set the output serial clock source */
+ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
+ DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
+
+ /* Reset clock divider */
+ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
+ if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
+ {
+ assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
+ /* Set the output clock divider */
+ DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
+ DFSDM_CHCFGR1_CKOUTDIV_Pos);
+ }
+
+ /* enable the DFSDM global interface */
+ DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
+ }
+
+ /* Set channel input parameters */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
+ DFSDM_CHCFGR1_CHINSEL);
+ hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
+ hdfsdm_channel->Init.Input.DataPacking |
+ hdfsdm_channel->Init.Input.Pins);
+
+ /* Set serial interface parameters */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
+ hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
+ hdfsdm_channel->Init.SerialInterface.SpiClock);
+
+ /* Set analog watchdog parameters */
+ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
+ hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
+ ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
+
+ /* Set channel offset and right bit shift */
+ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
+ hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
+ (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
+
+ /* Enable DFSDM channel */
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
+
+ /* Set DFSDM Channel to ready state */
+ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
+
+ /* Store channel handle in DFSDM channel handle table */
+ a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
+#endif /* DFSDM2_Channel0 */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initialize the DFSDM channel.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+#if defined(DFSDM2_Channel0)
+ __IO uint32_t* channelCounterPtr;
+ DFSDM_Channel_HandleTypeDef **channelHandleTable;
+ DFSDM_Channel_TypeDef* channel0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check DFSDM Channel handle */
+ if(hdfsdm_channel == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+#if defined(DFSDM2_Channel0)
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ channelCounterPtr = &v_dfsdm1ChannelCounter;
+ channelHandleTable = a_dfsdm1ChannelHandle;
+ channel0Instance = DFSDM1_Channel0;
+ }
+ else
+ {
+ channelCounterPtr = &v_dfsdm2ChannelCounter;
+ channelHandleTable = a_dfsdm2ChannelHandle;
+ channel0Instance = DFSDM2_Channel0;
+ }
+
+ /* Check that channel has not been already deinitialized */
+ if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the DFSDM channel */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
+
+ /* Update the channel counter */
+ (*channelCounterPtr)--;
+
+ /* Disable global DFSDM at deinit of last channel */
+ if(*channelCounterPtr == 0U)
+ {
+ channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
+ }
+
+ /* Call MSP deinit function */
+ HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
+
+ /* Set DFSDM Channel in reset state */
+ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
+
+ /* Reset channel handle in DFSDM channel handle table */
+ channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = NULL;
+#else
+ /* Check that channel has not been already deinitialized */
+ if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the DFSDM channel */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
+
+ /* Update the channel counter */
+ v_dfsdm1ChannelCounter--;
+
+ /* Disable global DFSDM at deinit of last channel */
+ if(v_dfsdm1ChannelCounter == 0U)
+ {
+ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
+ }
+
+ /* Call MSP deinit function */
+ HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
+
+ /* Set DFSDM Channel in reset state */
+ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
+
+ /* Reset channel handle in DFSDM channel handle table */
+ a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
+#endif /* defined(DFSDM2_Channel0) */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the DFSDM channel MSP.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_channel);
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief De-initialize the DFSDM channel MSP.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_channel);
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
+ * @brief Channel operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Channel operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Manage clock absence detector feature.
+ (+) Manage short circuit detector feature.
+ (+) Get analog watchdog value.
+ (+) Modify offset value.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to start clock absence detection in polling mode.
+ * @note Same mode has to be used for all channels.
+ * @note If clock is not available on this channel during 5 seconds,
+ * clock absence detection will not be activated and function
+ * will return HAL_TIMEOUT error.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+ uint32_t channel;
+
+#if defined(DFSDM2_Channel0)
+ DFSDM_Filter_TypeDef* filter0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+#if defined (DFSDM2_Channel0)
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ filter0Instance = DFSDM1_Filter0;
+ }
+ else
+ {
+ filter0Instance = DFSDM2_Filter0;
+ }
+ /* Get channel number from channel instance */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Clear clock absence flag */
+ while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
+ {
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+
+ /* Check the Timeout */
+ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
+ {
+ /* Set timeout status */
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+#else
+ /* Get channel number from channel instance */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Clear clock absence flag */
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
+ {
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+
+ /* Check the Timeout */
+ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
+ {
+ /* Set timeout status */
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+#endif /* DFSDM2_Channel0 */
+
+ if(status == HAL_OK)
+ {
+ /* Start clock absence detection */
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the clock absence detection.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t channel;
+#if defined(DFSDM2_Channel0)
+ DFSDM_Filter_TypeDef* filter0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+#if defined(DFSDM2_Channel0)
+
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ filter0Instance = DFSDM1_Filter0;
+ }
+ else
+ {
+ filter0Instance = DFSDM2_Filter0;
+ }
+
+ /* Get channel number from channel instance */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait clock absence detection */
+ while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear clock absence detection flag */
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+#else
+ /* Get channel number from channel instance */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait clock absence detection */
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear clock absence detection flag */
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+#endif /* defined(DFSDM2_Channel0) */
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to stop clock absence detection in polling mode.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t channel;
+#if defined(DFSDM2_Channel0)
+ DFSDM_Filter_TypeDef* filter0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+#if defined(DFSDM2_Channel0)
+
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ filter0Instance = DFSDM1_Filter0;
+ }
+ else
+ {
+ filter0Instance = DFSDM2_Filter0;
+ }
+
+ /* Stop clock absence detection */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
+
+ /* Clear clock absence flag */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+
+#else
+ /* Stop clock absence detection */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
+
+ /* Clear clock absence flag */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+#endif /* DFSDM2_Channel0 */
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start clock absence detection in interrupt mode.
+ * @note Same mode has to be used for all channels.
+ * @note If clock is not available on this channel during 5 seconds,
+ * clock absence detection will not be activated and function
+ * will return HAL_TIMEOUT error.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t channel;
+ uint32_t tickstart;
+#if defined(DFSDM2_Channel0)
+ DFSDM_Filter_TypeDef* filter0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+#if defined(DFSDM2_Channel0)
+
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ filter0Instance = DFSDM1_Filter0;
+ }
+ else
+ {
+ filter0Instance = DFSDM2_Filter0;
+ }
+
+ /* Get channel number from channel instance */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Clear clock absence flag */
+ while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
+ {
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+
+ /* Check the Timeout */
+ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
+ {
+ /* Set timeout status */
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+
+ if(status == HAL_OK)
+ {
+ /* Activate clock absence detection interrupt */
+ filter0Instance->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
+
+ /* Start clock absence detection */
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
+ }
+#else
+ /* Get channel number from channel instance */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Clear clock absence flag */
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
+ {
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+
+ /* Check the Timeout */
+ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
+ {
+ /* Set timeout status */
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+
+ if(status == HAL_OK)
+ {
+ /* Activate clock absence detection interrupt */
+ DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
+
+ /* Start clock absence detection */
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
+ }
+
+#endif /* defined(DFSDM2_Channel0) */
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Clock absence detection callback.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_channel);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function allows to stop clock absence detection in interrupt mode.
+ * @note Interrupt will be disabled for all channels
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t channel;
+#if defined(DFSDM2_Channel0)
+ DFSDM_Filter_TypeDef* filter0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+#if defined(DFSDM2_Channel0)
+
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ filter0Instance = DFSDM1_Filter0;
+ }
+ else
+ {
+ filter0Instance = DFSDM2_Filter0;
+ }
+
+ /* Stop clock absence detection */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
+
+ /* Clear clock absence flag */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+
+ /* Disable clock absence detection interrupt */
+ filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
+#else
+
+ /* Stop clock absence detection */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
+
+ /* Clear clock absence flag */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+
+ /* Disable clock absence detection interrupt */
+ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
+#endif /* DFSDM2_Channel0 */
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start short circuit detection in polling mode.
+ * @note Same mode has to be used for all channels
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Threshold Short circuit detector threshold.
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
+ * @param BreakSignal Break signals assigned to short circuit event.
+ * This parameter can be a values combination of @ref DFSDM_BreakSignals.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ uint32_t Threshold,
+ uint32_t BreakSignal)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+ assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
+ assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Configure threshold and break signals */
+ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
+ hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
+ Threshold);
+
+ /* Start short circuit detection */
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the short circuit detection.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t channel;
+#if defined(DFSDM2_Channel0)
+ DFSDM_Filter_TypeDef* filter0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Get channel number from channel instance */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+#if defined(DFSDM2_Channel0)
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ filter0Instance = DFSDM1_Filter0;
+ }
+ else
+ {
+ filter0Instance = DFSDM2_Filter0;
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait short circuit detection */
+ while(((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear short circuit detection flag */
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+
+#else
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait short circuit detection */
+ while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear short circuit detection flag */
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+#endif /* DFSDM2_Channel0 */
+
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to stop short circuit detection in polling mode.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t channel;
+#if defined(DFSDM2_Channel0)
+ DFSDM_Filter_TypeDef* filter0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop short circuit detection */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
+
+ /* Clear short circuit detection flag */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+#if defined(DFSDM2_Channel0)
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ filter0Instance = DFSDM1_Filter0;
+ }
+ else
+ {
+ filter0Instance = DFSDM2_Filter0;
+ }
+
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+#else
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+#endif /* DFSDM2_Channel0*/
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start short circuit detection in interrupt mode.
+ * @note Same mode has to be used for all channels
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Threshold Short circuit detector threshold.
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
+ * @param BreakSignal Break signals assigned to short circuit event.
+ * This parameter can be a values combination of @ref DFSDM_BreakSignals.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ uint32_t Threshold,
+ uint32_t BreakSignal)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+#if defined(DFSDM2_Channel0)
+ DFSDM_Filter_TypeDef* filter0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+ assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
+ assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+#if defined(DFSDM2_Channel0)
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ filter0Instance = DFSDM1_Filter0;
+ }
+ else
+ {
+ filter0Instance = DFSDM2_Filter0;
+ }
+ /* Activate short circuit detection interrupt */
+ filter0Instance->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
+#else
+ /* Activate short circuit detection interrupt */
+ DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
+#endif /* DFSDM2_Channel0 */
+
+ /* Configure threshold and break signals */
+ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
+ hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
+ Threshold);
+
+ /* Start short circuit detection */
+ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Short circuit detection callback.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_channel);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function allows to stop short circuit detection in interrupt mode.
+ * @note Interrupt will be disabled for all channels
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t channel;
+#if defined(DFSDM2_Channel0)
+ DFSDM_Filter_TypeDef* filter0Instance;
+#endif /* defined(DFSDM2_Channel0) */
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop short circuit detection */
+ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
+
+ /* Clear short circuit detection flag */
+ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+#if defined(DFSDM2_Channel0)
+ /* Get channel counter, channel handle table and channel 0 instance */
+ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
+ {
+ filter0Instance = DFSDM1_Filter0;
+ }
+ else
+ {
+ filter0Instance = DFSDM2_Filter0;
+ }
+
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+
+ /* Disable short circuit detection interrupt */
+ filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
+#else
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+
+ /* Disable short circuit detection interrupt */
+ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
+#endif /* DFSDM2_Channel0 */
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get channel analog watchdog value.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval Channel analog watchdog value.
+ */
+int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
+}
+
+/**
+ * @brief This function allows to modify channel offset value.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Offset DFSDM channel offset.
+ * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ int32_t Offset)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+ assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
+
+ /* Check DFSDM channel state */
+ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Modify channel offset */
+ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
+ hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
+ * @brief Channel state function
+ *
+@verbatim
+ ==============================================================================
+ ##### Channel state function #####
+ ==============================================================================
+ [..] This section provides function allowing to:
+ (+) Get channel handle state.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to get the current DFSDM channel handle state.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @retval DFSDM channel state.
+ */
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+ /* Return DFSDM channel handle state */
+ return hdfsdm_channel->State;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
+ * @brief Filter initialization and de-initialization functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Filter initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the DFSDM filter.
+ (+) De-initialize the DFSDM filter.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DFSDM filter according to the specified parameters
+ * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Check DFSDM Channel handle */
+ if(hdfsdm_filter == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+ assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
+ assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
+ assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
+ assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
+ assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
+ assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
+
+ /* Check parameters compatibility */
+ if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
+ ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
+ (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
+ {
+ return HAL_ERROR;
+ }
+#if defined (DFSDM2_Channel0)
+ if((hdfsdm_filter->Instance == DFSDM2_Filter0) &&
+ ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
+ (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
+ {
+ return HAL_ERROR;
+ }
+#endif /* DFSDM2_Channel0 */
+
+ /* Initialize DFSDM filter variables with default values */
+ hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;
+ hdfsdm_filter->InjectedChannelsNbr = 1U;
+ hdfsdm_filter->InjConvRemaining = 1U;
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
+
+ /* Call MSP init function */
+ HAL_DFSDM_FilterMspInit(hdfsdm_filter);
+
+ /* Set regular parameters */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
+ if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
+ }
+ else
+ {
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
+ }
+
+ if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
+ }
+ else
+ {
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
+ }
+
+ /* Set injected parameters */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
+ if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
+ {
+ assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
+ assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
+ hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
+ }
+
+ if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
+ }
+ else
+ {
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
+ }
+
+ if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
+ }
+ else
+ {
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
+ }
+
+ /* Set filter parameters */
+ hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
+ hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
+ ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) |
+ (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));
+
+ /* Store regular and injected triggers and injected scan mode*/
+ hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger;
+ hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
+ hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
+ hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
+
+ /* Enable DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+
+ /* Set DFSDM filter to ready state */
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initializes the DFSDM filter.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Check DFSDM filter handle */
+ if(hdfsdm_filter == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Disable the DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+
+ /* Call MSP deinit function */
+ HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
+
+ /* Set DFSDM filter in reset state */
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DFSDM filter MSP.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_filter);
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_DFSDM_FilterMspInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief De-initializes the DFSDM filter MSP.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_filter);
+ /* NOTE : This function should not be modified, when the function is needed,
+ the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
+ * @brief Filter control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Filter control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Select channel and enable/disable continuous mode for regular conversion.
+ (+) Select channels for injected conversion.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to select channel and to enable/disable
+ * continuous mode for regular conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Channel for regular conversion.
+ * This parameter can be a value of @ref DFSDM_Channel_Selection.
+ * @param ContinuousMode Enable/disable continuous mode for regular conversion.
+ * This parameter can be a value of @ref DFSDM_ContinuousMode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Channel,
+ uint32_t ContinuousMode)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+ assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
+ assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
+ {
+ /* Configure channel and continuous mode for regular conversion */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
+ if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
+ DFSDM_FLTCR1_RCONT);
+ }
+ else
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
+ }
+ /* Store continuous mode information */
+ hdfsdm_filter->RegularContMode = ContinuousMode;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select channels for injected conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Channels for injected conversion.
+ * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+ assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
+ {
+ /* Configure channel for injected conversion */
+ hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
+ /* Store number of injected channels */
+ hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
+ /* Update number of injected channels remaining */
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
+ * @brief Filter operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Filter operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular/injected channel.
+ (+) Poll for the end of regular/injected conversion.
+ (+) Stop conversion of regular/injected channel.
+ (+) Start conversion of regular/injected channel and enable interrupt.
+ (+) Call the callback functions at the end of regular/injected conversions.
+ (+) Stop conversion of regular/injected channel and disable interrupt.
+ (+) Start conversion of regular/injected channel and enable DMA transfer.
+ (+) Stop conversion of regular/injected channel and disable DMA transfer.
+ (+) Start analog watchdog and enable interrupt.
+ (+) Call the callback function when analog watchdog occurs.
+ (+) Stop analog watchdog and disable interrupt.
+ (+) Start extreme detector.
+ (+) Stop extreme detector.
+ (+) Get result of regular channel conversion.
+ (+) Get result of injected channel conversion.
+ (+) Get extreme detector maximum and minimum values.
+ (+) Get conversion time.
+ (+) Handle DFSDM interrupt request.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to start regular conversion in polling mode.
+ * @note This function should be called only when DFSDM filter instance is
+ * in idle state or if injected conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+ {
+ /* Start regular conversion */
+ DFSDM_RegConvStart(hdfsdm_filter);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the end of regular conversion.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait end of regular conversion */
+ while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Check if overrun occurs */
+ if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
+ {
+ /* Update error code and call error callback */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+
+ /* Clear regular overrun flag */
+ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
+ }
+ /* Update DFSDM filter state only if not continuous conversion and SW trigger */
+ if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+ {
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+ }
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to stop regular conversion in polling mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop regular conversion */
+ DFSDM_RegConvStop(hdfsdm_filter);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start regular conversion in interrupt mode.
+ * @note This function should be called only when DFSDM filter instance is
+ * in idle state or if injected conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+ {
+ /* Enable interrupts for regular conversions */
+ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
+
+ /* Start regular conversion */
+ DFSDM_RegConvStart(hdfsdm_filter);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop regular conversion in interrupt mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Disable interrupts for regular conversions */
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
+
+ /* Stop regular conversion */
+ DFSDM_RegConvStop(hdfsdm_filter);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start regular conversion in DMA mode.
+ * @note This function should be called only when DFSDM filter instance is
+ * in idle state or if injected conversion is ongoing.
+ * Please note that data on buffer will contain signed regular conversion
+ * value on 24 most significant bits and corresponding channel on 3 least
+ * significant bits.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ int32_t *pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check destination address and length */
+ if((pData == NULL) || (Length == 0U))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check that DMA is enabled for regular conversion */
+ else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
+ (Length != 1U))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check DFSDM filter state */
+ else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+ {
+ /* Set callbacks on DMA handler */
+ hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
+ hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
+ hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
+ DFSDM_DMARegularHalfConvCplt : NULL;
+
+ /* Start DMA in interrupt mode */
+ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
+ (uint32_t) pData, Length) != HAL_OK)
+ {
+ /* Set DFSDM filter in error state */
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start regular conversion */
+ DFSDM_RegConvStart(hdfsdm_filter);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start regular conversion in DMA mode and to get
+ * only the 16 most significant bits of conversion.
+ * @note This function should be called only when DFSDM filter instance is
+ * in idle state or if injected conversion is ongoing.
+ * Please note that data on buffer will contain signed 16 most significant
+ * bits of regular conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ int16_t *pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check destination address and length */
+ if((pData == NULL) || (Length == 0U))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check that DMA is enabled for regular conversion */
+ else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
+ (Length != 1U))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check DFSDM filter state */
+ else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+ {
+ /* Set callbacks on DMA handler */
+ hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
+ hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
+ hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
+ DFSDM_DMARegularHalfConvCplt : NULL;
+
+ /* Start DMA in interrupt mode */
+ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
+ (uint32_t) pData, Length) != HAL_OK)
+ {
+ /* Set DFSDM filter in error state */
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start regular conversion */
+ DFSDM_RegConvStart(hdfsdm_filter);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop regular conversion in DMA mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
+ {
+ /* Set DFSDM filter in error state */
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop regular conversion */
+ DFSDM_RegConvStop(hdfsdm_filter);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get regular conversion value.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel of regular conversion.
+ * @retval Regular conversion value
+ */
+int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t *Channel)
+{
+ uint32_t reg = 0U;
+ int32_t value = 0;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+ assert_param(Channel != NULL);
+
+ /* Get value of data register for regular channel */
+ reg = hdfsdm_filter->Instance->FLTRDATAR;
+
+ /* Extract channel and regular conversion value */
+ *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
+ value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos);
+
+ /* return regular conversion value */
+ return value;
+}
+
+/**
+ * @brief This function allows to start injected conversion in polling mode.
+ * @note This function should be called only when DFSDM filter instance is
+ * in idle state or if regular conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+ {
+ /* Start injected conversion */
+ DFSDM_InjConvStart(hdfsdm_filter);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the end of injected conversion.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Timeout Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait end of injected conversions */
+ while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Check if overrun occurs */
+ if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
+ {
+ /* Update error code and call error callback */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+
+ /* Clear injected overrun flag */
+ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
+ }
+
+ /* Update remaining injected conversions */
+ hdfsdm_filter->InjConvRemaining--;
+ if(hdfsdm_filter->InjConvRemaining == 0U)
+ {
+ /* Update DFSDM filter state only if trigger is software */
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+ {
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+ }
+
+ /* end of injected sequence, reset the value */
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to stop injected conversion in polling mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop injected conversion */
+ DFSDM_InjConvStop(hdfsdm_filter);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start injected conversion in interrupt mode.
+ * @note This function should be called only when DFSDM filter instance is
+ * in idle state or if regular conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+ {
+ /* Enable interrupts for injected conversions */
+ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
+
+ /* Start injected conversion */
+ DFSDM_InjConvStart(hdfsdm_filter);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop injected conversion in interrupt mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Disable interrupts for injected conversions */
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
+
+ /* Stop injected conversion */
+ DFSDM_InjConvStop(hdfsdm_filter);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start injected conversion in DMA mode.
+ * @note This function should be called only when DFSDM filter instance is
+ * in idle state or if regular conversion is ongoing.
+ * Please note that data on buffer will contain signed injected conversion
+ * value on 24 most significant bits and corresponding channel on 3 least
+ * significant bits.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ int32_t *pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check destination address and length */
+ if((pData == NULL) || (Length == 0U))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check that DMA is enabled for injected conversion */
+ else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
+ (Length > hdfsdm_filter->InjConvRemaining))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check DFSDM filter state */
+ else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+ {
+ /* Set callbacks on DMA handler */
+ hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
+ hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
+ hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
+ DFSDM_DMAInjectedHalfConvCplt : NULL;
+
+ /* Start DMA in interrupt mode */
+ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
+ (uint32_t) pData, Length) != HAL_OK)
+ {
+ /* Set DFSDM filter in error state */
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start injected conversion */
+ DFSDM_InjConvStart(hdfsdm_filter);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start injected conversion in DMA mode and to get
+ * only the 16 most significant bits of conversion.
+ * @note This function should be called only when DFSDM filter instance is
+ * in idle state or if regular conversion is ongoing.
+ * Please note that data on buffer will contain signed 16 most significant
+ * bits of injected conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ int16_t *pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check destination address and length */
+ if((pData == NULL) || (Length == 0U))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check that DMA is enabled for injected conversion */
+ else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
+ (Length > hdfsdm_filter->InjConvRemaining))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check DFSDM filter state */
+ else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+ {
+ /* Set callbacks on DMA handler */
+ hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
+ hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
+ hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
+ DFSDM_DMAInjectedHalfConvCplt : NULL;
+
+ /* Start DMA in interrupt mode */
+ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
+ (uint32_t) pData, Length) != HAL_OK)
+ {
+ /* Set DFSDM filter in error state */
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start injected conversion */
+ DFSDM_InjConvStart(hdfsdm_filter);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop injected conversion in DMA mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
+ {
+ /* Set DFSDM filter in error state */
+ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop regular conversion */
+ DFSDM_InjConvStop(hdfsdm_filter);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get injected conversion value.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel of injected conversion.
+ * @retval Injected conversion value
+ */
+int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t *Channel)
+{
+ uint32_t reg = 0U;
+ int32_t value = 0;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+ assert_param(Channel != NULL);
+
+ /* Get value of data register for injected channel */
+ reg = hdfsdm_filter->Instance->FLTJDATAR;
+
+ /* Extract channel and injected conversion value */
+ *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
+ value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos);
+
+ /* return regular conversion value */
+ return value;
+}
+
+/**
+ * @brief This function allows to start filter analog watchdog in interrupt mode.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param awdParam DFSDM filter analog watchdog parameters.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ DFSDM_Filter_AwdParamTypeDef *awdParam)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+ assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
+ assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
+ assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
+ assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
+ assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
+ assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Set analog watchdog data source */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
+ hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
+
+ /* Set thresholds and break signals */
+ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
+ hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \
+ awdParam->HighBreakSignal);
+ hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
+ hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \
+ awdParam->LowBreakSignal);
+
+ /* Set channels and interrupt for analog watchdog */
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
+ hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \
+ DFSDM_FLTCR2_AWDIE);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop filter analog watchdog in interrupt mode.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset channels for analog watchdog and deactivate interrupt */
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
+
+ /* Clear all analog watchdog flags */
+ hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
+
+ /* Reset thresholds and break signals */
+ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
+ hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
+
+ /* Reset analog watchdog data source */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start extreme detector feature.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Channels where extreme detector is enabled.
+ * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+ assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Set channels for extreme detector */
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
+ hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop extreme detector feature.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ __IO uint32_t reg1;
+ __IO uint32_t reg2;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Check DFSDM filter state */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset channels for extreme detector */
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
+
+ /* Clear extreme detector values */
+ reg1 = hdfsdm_filter->Instance->FLTEXMAX;
+ reg2 = hdfsdm_filter->Instance->FLTEXMIN;
+ UNUSED(reg1); /* To avoid GCC warning */
+ UNUSED(reg2); /* To avoid GCC warning */
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get extreme detector maximum value.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel.
+ * @retval Extreme detector maximum value
+ * This value is between Min_Data = -8388608 and Max_Data = 8388607.
+ */
+int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t *Channel)
+{
+ uint32_t reg = 0U;
+ int32_t value = 0;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+ assert_param(Channel != NULL);
+
+ /* Get value of extreme detector maximum register */
+ reg = hdfsdm_filter->Instance->FLTEXMAX;
+
+ /* Extract channel and extreme detector maximum value */
+ *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
+ value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos);
+
+ /* return extreme detector maximum value */
+ return value;
+}
+
+/**
+ * @brief This function allows to get extreme detector minimum value.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel.
+ * @retval Extreme detector minimum value
+ * This value is between Min_Data = -8388608 and Max_Data = 8388607.
+ */
+int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t *Channel)
+{
+ uint32_t reg = 0U;
+ int32_t value = 0;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+ assert_param(Channel != NULL);
+
+ /* Get value of extreme detector minimum register */
+ reg = hdfsdm_filter->Instance->FLTEXMIN;
+
+ /* Extract channel and extreme detector minimum value */
+ *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
+ value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos);
+
+ /* return extreme detector minimum value */
+ return value;
+}
+
+/**
+ * @brief This function allows to get conversion time value.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval Conversion time value
+ * @note To get time in second, this value has to be divided by DFSDM clock frequency.
+ */
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ uint32_t reg = 0U;
+ uint32_t value = 0U;
+
+ /* Check parameters */
+ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+ /* Get value of conversion timer register */
+ reg = hdfsdm_filter->Instance->FLTCNVTIMR;
+
+ /* Extract conversion time value */
+ value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
+
+ /* return extreme detector minimum value */
+ return value;
+}
+
+/**
+ * @brief This function handles the DFSDM interrupts.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Check if overrun occurs during regular conversion */
+ if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0U) && \
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0U))
+ {
+ /* Clear regular overrun flag */
+ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
+
+ /* Update error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
+
+ /* Call error callback */
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+ }
+ /* Check if overrun occurs during injected conversion */
+ else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0U) && \
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0U))
+ {
+ /* Clear injected overrun flag */
+ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
+
+ /* Update error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
+
+ /* Call error callback */
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+ }
+ /* Check if end of regular conversion */
+ else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0U) && \
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0U))
+ {
+ /* Call regular conversion complete callback */
+ HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+
+ /* End of conversion if mode is not continuous and software trigger */
+ if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+ {
+ /* Disable interrupts for regular conversions */
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
+
+ /* Update DFSDM filter state */
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+ }
+ }
+ /* Check if end of injected conversion */
+ else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0U) && \
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0U))
+ {
+ /* Call injected conversion complete callback */
+ HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+
+ /* Update remaining injected conversions */
+ hdfsdm_filter->InjConvRemaining--;
+ if(hdfsdm_filter->InjConvRemaining == 0U)
+ {
+ /* End of conversion if trigger is software */
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+ {
+ /* Disable interrupts for injected conversions */
+ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
+
+ /* Update DFSDM filter state */
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+ }
+ /* end of injected sequence, reset the value */
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
+ }
+ }
+ /* Check if analog watchdog occurs */
+ else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0U) && \
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0U))
+ {
+ uint32_t reg = 0U;
+ uint32_t threshold = 0U;
+ uint32_t channel = 0U;
+
+ /* Get channel and threshold */
+ reg = hdfsdm_filter->Instance->FLTAWSR;
+ threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
+ if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
+ {
+ reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;
+ }
+ while((reg & 1U) == 0U)
+ {
+ channel++;
+ reg = reg >> 1U;
+ }
+ /* Clear analog watchdog flag */
+ hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
+ (1U << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \
+ (1U << channel);
+
+ /* Call analog watchdog callback */
+ HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
+ }
+ /* Check if clock absence occurs */
+ else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
+ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U))
+ {
+ uint32_t reg = 0U;
+ uint32_t channel = 0U;
+
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
+
+ while(channel < DFSDM1_CHANNEL_NUMBER)
+ {
+ /* Check if flag is set and corresponding channel is enabled */
+ if(((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL))
+ {
+ /* Check clock absence has been enabled for this channel */
+ if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
+ {
+ /* Clear clock absence flag */
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+
+ /* Call clock absence callback */
+ HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
+ }
+ }
+ channel++;
+ reg = reg >> 1U;
+ }
+ }
+#if defined (DFSDM2_Channel0)
+ /* Check if clock absence occurs */
+ else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
+ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U))
+ {
+ uint32_t reg = 0U;
+ uint32_t channel = 0U;
+
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
+
+ while(channel < DFSDM2_CHANNEL_NUMBER)
+ {
+ /* Check if flag is set and corresponding channel is enabled */
+ if(((reg & 1U) != 0U) && (a_dfsdm2ChannelHandle[channel] != NULL))
+ {
+ /* Check clock absence has been enabled for this channel */
+ if((a_dfsdm2ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
+ {
+ /* Clear clock absence flag */
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
+
+ /* Call clock absence callback */
+ HAL_DFSDM_ChannelCkabCallback(a_dfsdm2ChannelHandle[channel]);
+ }
+ }
+ channel++;
+ reg = reg >> 1U;
+ }
+ }
+#endif /* DFSDM2_Channel0 */
+ /* Check if short circuit detection occurs */
+ else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
+ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U))
+ {
+ uint32_t reg = 0U;
+ uint32_t channel = 0U;
+
+ /* Get channel */
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
+ while((reg & 1U) == 0U)
+ {
+ channel++;
+ reg = reg >> 1U;
+ }
+
+ /* Clear short circuit detection flag */
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+
+ /* Call short circuit detection callback */
+ HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
+ }
+#if defined (DFSDM2_Channel0)
+ /* Check if short circuit detection occurs */
+ else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
+ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
+ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U))
+ {
+ uint32_t reg = 0U;
+ uint32_t channel = 0U;
+
+ /* Get channel */
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
+ while((reg & 1U) == 0U)
+ {
+ channel++;
+ reg = reg >> 1U;
+ }
+
+ /* Clear short circuit detection flag */
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+
+ /* Call short circuit detection callback */
+ HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]);
+ }
+#endif /* DFSDM2_Channel0 */
+}
+
+/**
+ * @brief Regular conversion complete callback.
+ * @note In interrupt mode, user has to read conversion value in this function
+ * using HAL_DFSDM_FilterGetRegularValue.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_filter);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Half regular conversion complete callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_filter);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Injected conversion complete callback.
+ * @note In interrupt mode, user has to read conversion value in this function
+ * using HAL_DFSDM_FilterGetInjectedValue.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_filter);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Half injected conversion complete callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_filter);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Filter analog watchdog callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel.
+ * @param Threshold Low or high threshold has been reached.
+ * @retval None
+ */
+__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Channel, uint32_t Threshold)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_filter);
+ UNUSED(Channel);
+ UNUSED(Threshold);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Error callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdfsdm_filter);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
+ * @brief Filter state functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Filter state functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Get the DFSDM filter state.
+ (+) Get the DFSDM filter error.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to get the current DFSDM filter handle state.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval DFSDM filter state.
+ */
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ /* Return DFSDM filter handle state */
+ return hdfsdm_filter->State;
+}
+
+/**
+ * @brief This function allows to get the current DFSDM filter error.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval DFSDM filter error code.
+ */
+uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ return hdfsdm_filter->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions
+ * @brief Filter state functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Filter MultiChannel operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Control the DFSDM Multi channel delay block
+@endverbatim
+ * @{
+ */
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+/**
+ * @brief Select the DFSDM2 as clock source for the bitstream clock.
+ * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
+ * before HAL_DFSDM_BitstreamClock_Start()
+ */
+void HAL_DFSDM_BitstreamClock_Start(void)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+ tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
+
+ SYSCFG->MCHDLYCR = (tmp|SYSCFG_MCHDLYCR_BSCKSEL);
+}
+
+/**
+ * @brief Stop the DFSDM2 as clock source for the bitstream clock.
+ * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
+ * before HAL_DFSDM_BitstreamClock_Stop()
+ * @retval None
+ */
+void HAL_DFSDM_BitstreamClock_Stop(void)
+{
+ uint32_t tmp = 0U;
+
+ tmp = SYSCFG->MCHDLYCR;
+ tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
+
+ SYSCFG->MCHDLYCR = tmp;
+}
+
+/**
+ * @brief Disable Delay Clock for DFSDM1/2.
+ * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2.
+ * HAL_MCHDLY_CLOCK_DFSDM1.
+ * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
+ * before HAL_DFSDM_DisableDelayClock()
+ * @retval None
+ */
+void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY)
+{
+ uint32_t tmp = 0U;
+
+ assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
+
+ tmp = SYSCFG->MCHDLYCR;
+ if(MCHDLY == HAL_MCHDLY_CLOCK_DFSDM2)
+ {
+ tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY2EN);
+ }
+ else
+ {
+ tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY1EN);
+ }
+
+ SYSCFG->MCHDLYCR = tmp;
+}
+
+/**
+ * @brief Enable Delay Clock for DFSDM1/2.
+ * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2.
+ * HAL_MCHDLY_CLOCK_DFSDM1.
+ * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
+ * before HAL_DFSDM_EnableDelayClock()
+ * @retval None
+ */
+void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY)
+{
+ uint32_t tmp = 0U;
+
+ assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
+
+ tmp = SYSCFG->MCHDLYCR;
+ tmp = tmp & ~MCHDLY;
+
+ SYSCFG->MCHDLYCR = (tmp|MCHDLY);
+}
+
+/**
+ * @brief Select the source for CKin signals for DFSDM1/2.
+ * @param source DFSDM2_CKIN_PAD.
+ * DFSDM2_CKIN_DM.
+ * DFSDM1_CKIN_PAD.
+ * DFSDM1_CKIN_DM.
+ * @retval None
+ */
+void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0U;
+
+ assert_param(IS_DFSDM_CLOCKIN_SELECTION(source));
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if((source == HAL_DFSDM2_CKIN_PAD) || (source == HAL_DFSDM2_CKIN_DM))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG);
+
+ if(source == HAL_DFSDM2_CKIN_PAD)
+ {
+ source = 0x000000U;
+ }
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CFG);
+ }
+
+ SYSCFG->MCHDLYCR = (source|tmp);
+}
+
+/**
+ * @brief Select the source for CKOut signals for DFSDM1/2.
+ * @param source: DFSDM2_CKOUT_DFSDM2.
+ * DFSDM2_CKOUT_M27.
+ * DFSDM1_CKOUT_DFSDM1.
+ * DFSDM1_CKOUT_M27.
+ * @retval None
+ */
+void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0U;
+
+ assert_param(IS_DFSDM_CLOCKOUT_SELECTION(source));
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if((source == HAL_DFSDM2_CKOUT_DFSDM2) || (source == HAL_DFSDM2_CKOUT_M27))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL);
+
+ if(source == HAL_DFSDM2_CKOUT_DFSDM2)
+ {
+ source = 0x000U;
+ }
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CKOSEL);
+ }
+
+ SYSCFG->MCHDLYCR = (source|tmp);
+}
+
+/**
+ * @brief Select the source for DataIn0 signals for DFSDM1/2.
+ * @param source DATAIN0_DFSDM2_PAD.
+ * DATAIN0_DFSDM2_DATAIN1.
+ * DATAIN0_DFSDM1_PAD.
+ * DATAIN0_DFSDM1_DATAIN1.
+ * @retval None
+ */
+void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0U;
+
+ assert_param(IS_DFSDM_DATAIN0_SRC_SELECTION(source));
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if((source == HAL_DATAIN0_DFSDM2_PAD)|| (source == HAL_DATAIN0_DFSDM2_DATAIN1))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL);
+ if(source == HAL_DATAIN0_DFSDM2_PAD)
+ {
+ source = 0x00000U;
+ }
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D0SEL);
+ }
+ SYSCFG->MCHDLYCR = (source|tmp);
+}
+
+/**
+ * @brief Select the source for DataIn2 signals for DFSDM1/2.
+ * @param source DATAIN2_DFSDM2_PAD.
+ * DATAIN2_DFSDM2_DATAIN3.
+ * DATAIN2_DFSDM1_PAD.
+ * DATAIN2_DFSDM1_DATAIN3.
+ * @retval None
+ */
+void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0U;
+
+ assert_param(IS_DFSDM_DATAIN2_SRC_SELECTION(source));
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if((source == HAL_DATAIN2_DFSDM2_PAD)|| (source == HAL_DATAIN2_DFSDM2_DATAIN3))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL);
+ if (source == HAL_DATAIN2_DFSDM2_PAD)
+ {
+ source = 0x0000U;
+ }
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D2SEL);
+ }
+ SYSCFG->MCHDLYCR = (source|tmp);
+}
+
+/**
+ * @brief Select the source for DataIn4 signals for DFSDM2.
+ * @param source DATAIN4_DFSDM2_PAD.
+ * DATAIN4_DFSDM2_DATAIN5
+ * @retval None
+ */
+void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0U;
+
+ assert_param(IS_DFSDM_DATAIN4_SRC_SELECTION(source));
+
+ tmp = SYSCFG->MCHDLYCR;
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D4SEL);
+
+ SYSCFG->MCHDLYCR = (source|tmp);
+}
+
+/**
+ * @brief Select the source for DataIn6 signals for DFSDM2.
+ * @param source DATAIN6_DFSDM2_PAD.
+ * DATAIN6_DFSDM2_DATAIN7.
+ * @retval None
+ */
+void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0U;
+
+ assert_param(IS_DFSDM_DATAIN6_SRC_SELECTION(source));
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL);
+
+ SYSCFG->MCHDLYCR = (source|tmp);
+}
+
+/**
+ * @brief Configure the distribution of the bitstream clock gated from TIM4_OC
+ * for DFSDM1 or TIM3_OC for DFSDM2
+ * @param source DFSDM1_CLKIN0_TIM4OC2
+ * DFSDM1_CLKIN2_TIM4OC2
+ * DFSDM1_CLKIN1_TIM4OC1
+ * DFSDM1_CLKIN3_TIM4OC1
+ * DFSDM2_CLKIN0_TIM3OC4
+ * DFSDM2_CLKIN4_TIM3OC4
+ * DFSDM2_CLKIN1_TIM3OC3
+ * DFSDM2_CLKIN5_TIM3OC3
+ * DFSDM2_CLKIN2_TIM3OC2
+ * DFSDM2_CLKIN6_TIM3OC2
+ * DFSDM2_CLKIN3_TIM3OC1
+ * DFSDM2_CLKIN7_TIM3OC1
+ * @retval None
+ */
+void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
+{
+ uint32_t tmp = 0U;
+
+ assert_param(IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(source));
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if ((source == HAL_DFSDM1_CLKIN0_TIM4OC2) || (source == HAL_DFSDM1_CLKIN2_TIM4OC2))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK02SEL);
+ }
+ else if ((source == HAL_DFSDM1_CLKIN1_TIM4OC1) || (source == HAL_DFSDM1_CLKIN3_TIM4OC1))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK13SEL);
+ }
+ else if ((source == HAL_DFSDM2_CLKIN0_TIM3OC4) || (source == HAL_DFSDM2_CLKIN4_TIM3OC4))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK04SEL);
+ }
+ else if ((source == HAL_DFSDM2_CLKIN1_TIM3OC3) || (source == HAL_DFSDM2_CLKIN5_TIM3OC3))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL);
+
+ }else if ((source == HAL_DFSDM2_CLKIN2_TIM3OC2) || (source == HAL_DFSDM2_CLKIN6_TIM3OC2))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL);
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL);
+ }
+
+ if((source == HAL_DFSDM1_CLKIN0_TIM4OC2) ||(source == HAL_DFSDM1_CLKIN1_TIM4OC1)||
+ (source == HAL_DFSDM2_CLKIN0_TIM3OC4) ||(source == HAL_DFSDM2_CLKIN1_TIM3OC3)||
+ (source == HAL_DFSDM2_CLKIN2_TIM3OC2) ||(source == HAL_DFSDM2_CLKIN3_TIM3OC1))
+ {
+ source = 0x0000U;
+ }
+
+ SYSCFG->MCHDLYCR = (source|tmp);
+}
+
+/**
+ * @brief Configure multi channel delay block: Use DFSDM2 audio clock source as input
+ * clock for DFSDM1 and DFSDM2 filters to Synchronize DFSDMx filters.
+ * Set the path of the DFSDM2 clock output (dfsdm2_ckout) to the
+ * DFSDM1/2 CkInx and data inputs channels by configuring following MCHDLY muxes
+ * or demuxes: M1, M2, M3, M4, M5, M6, M7, M8, DM1, DM2, DM3, DM4, DM5, DM6,
+ * M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 based on the
+ * contains of the DFSDM_MultiChannelConfigTypeDef structure
+ * @param mchdlystruct Structure of multi channel configuration
+ * @retval None
+ * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
+ * before HAL_DFSDM_ConfigMultiChannelDelay()
+ * @note The HAL_DFSDM_ConfigMultiChannelDelay() function clears the SYSCFG-MCHDLYCR
+ * register before setting the new configuration.
+ */
+void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct)
+{
+ uint32_t mchdlyreg = 0U;
+
+ assert_param(IS_DFSDM_DFSDM1_CLKOUT(mchdlystruct->DFSDM1ClockOut));
+ assert_param(IS_DFSDM_DFSDM2_CLKOUT(mchdlystruct->DFSDM2ClockOut));
+ assert_param(IS_DFSDM_DFSDM1_CLKIN(mchdlystruct->DFSDM1ClockIn));
+ assert_param(IS_DFSDM_DFSDM2_CLKIN(mchdlystruct->DFSDM2ClockIn));
+ assert_param(IS_DFSDM_DFSDM1_BIT_CLK((mchdlystruct->DFSDM1BitClkDistribution)));
+ assert_param(IS_DFSDM_DFSDM2_BIT_CLK(mchdlystruct->DFSDM2BitClkDistribution));
+ assert_param(IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(mchdlystruct->DFSDM1DataDistribution));
+ assert_param(IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(mchdlystruct->DFSDM2DataDistribution));
+
+ mchdlyreg = (SYSCFG->MCHDLYCR & 0x80103U);
+
+ SYSCFG->MCHDLYCR = (mchdlyreg |(mchdlystruct->DFSDM1ClockOut)|(mchdlystruct->DFSDM2ClockOut)|
+ (mchdlystruct->DFSDM1ClockIn)|(mchdlystruct->DFSDM2ClockIn)|
+ (mchdlystruct->DFSDM1BitClkDistribution)| (mchdlystruct->DFSDM2BitClkDistribution)|
+ (mchdlystruct->DFSDM1DataDistribution)| (mchdlystruct->DFSDM2DataDistribution));
+
+}
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA half transfer complete callback for regular conversion.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get DFSDM filter handle */
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call regular half conversion complete callback */
+ HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
+}
+
+/**
+ * @brief DMA transfer complete callback for regular conversion.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get DFSDM filter handle */
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call regular conversion complete callback */
+ HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+}
+
+/**
+ * @brief DMA half transfer complete callback for injected conversion.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get DFSDM filter handle */
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call injected half conversion complete callback */
+ HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
+}
+
+/**
+ * @brief DMA transfer complete callback for injected conversion.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get DFSDM filter handle */
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call injected conversion complete callback */
+ HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+}
+
+/**
+ * @brief DMA error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Get DFSDM filter handle */
+ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Update error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
+
+ /* Call error callback */
+ HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+}
+
+/**
+ * @brief This function allows to get the number of injected channels.
+ * @param Channels bitfield of injected channels.
+ * @retval Number of injected channels.
+ */
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
+{
+ uint32_t nbChannels = 0U;
+ uint32_t tmp;
+
+ /* Get the number of channels from bitfield */
+ tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
+ while(tmp != 0U)
+ {
+ if((tmp & 1U) != 0U)
+ {
+ nbChannels++;
+ }
+ tmp = (uint32_t) (tmp >> 1U);
+ }
+ return nbChannels;
+}
+
+/**
+ * @brief This function allows to get the channel number from channel instance.
+ * @param Instance DFSDM channel instance.
+ * @retval Channel number.
+ */
+static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
+{
+ uint32_t channel = 0xFFU;
+
+ /* Get channel from instance */
+#if defined(DFSDM2_Channel0)
+ if((Instance == DFSDM1_Channel0) || (Instance == DFSDM2_Channel0))
+ {
+ channel = 0U;
+ }
+ else if((Instance == DFSDM1_Channel1) || (Instance == DFSDM2_Channel1))
+ {
+ channel = 1U;
+ }
+ else if((Instance == DFSDM1_Channel2) || (Instance == DFSDM2_Channel2))
+ {
+ channel = 2U;
+ }
+ else if((Instance == DFSDM1_Channel3) || (Instance == DFSDM2_Channel3))
+ {
+ channel = 3U;
+ }
+ else if(Instance == DFSDM2_Channel4)
+ {
+ channel = 4U;
+ }
+ else if(Instance == DFSDM2_Channel5)
+ {
+ channel = 5U;
+ }
+ else if(Instance == DFSDM2_Channel6)
+ {
+ channel = 6U;
+ }
+ else if(Instance == DFSDM2_Channel7)
+ {
+ channel = 7U;
+ }
+#else
+ if(Instance == DFSDM1_Channel0)
+ {
+ channel = 0U;
+ }
+ else if(Instance == DFSDM1_Channel1)
+ {
+ channel = 1U;
+ }
+ else if(Instance == DFSDM1_Channel2)
+ {
+ channel = 2U;
+ }
+ else if(Instance == DFSDM1_Channel3)
+ {
+ channel = 3U;
+ }
+#endif /* defined(DFSDM2_Channel0) */
+
+ return channel;
+}
+
+/**
+ * @brief This function allows to really start regular conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+ /* Check regular trigger */
+ if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
+ {
+ /* Software start of regular conversion */
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+ }
+ else /* synchronous trigger */
+ {
+ /* Disable DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+
+ /* Set RSYNC bit in DFSDM_FLTCR1 register */
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
+
+ /* Enable DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+
+ /* If injected conversion was in progress, restart it */
+ if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
+ {
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
+ }
+ /* Update remaining injected conversions */
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
+ }
+ }
+ /* Update DFSDM filter state */
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
+ HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
+}
+
+/**
+ * @brief This function allows to really stop regular conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+ /* Disable DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+
+ /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
+ if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
+ {
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
+ }
+
+ /* Enable DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+
+ /* If injected conversion was in progress, restart it */
+ if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
+ {
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
+ }
+ /* Update remaining injected conversions */
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
+ }
+
+ /* Update DFSDM filter state */
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+}
+
+/**
+ * @brief This function allows to really start injected conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+ /* Check injected trigger */
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+ {
+ /* Software start of injected conversion */
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
+ }
+ else /* external or synchronous trigger */
+ {
+ /* Disable DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
+ {
+ /* Set JSYNC bit in DFSDM_FLTCR1 register */
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
+ }
+ else /* external trigger */
+ {
+ /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
+ hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
+ }
+
+ /* Enable DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+
+ /* If regular conversion was in progress, restart it */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+ }
+ }
+ /* Update DFSDM filter state */
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
+ HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
+}
+
+/**
+ * @brief This function allows to really stop injected conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval None
+ */
+static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+ /* Disable DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+
+ /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
+ if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
+ {
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
+ }
+ else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
+ {
+ /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
+ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
+ }
+
+ /* Enable DFSDM filter */
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+
+ /* If regular conversion was in progress, restart it */
+ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+ {
+ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+ }
+
+ /* Update remaining injected conversions */
+ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
+
+ /* Update DFSDM filter state */
+ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+}
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1058 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dfsdm.h
+ * @author MCD Application Team
+ * @brief Header file of DFSDM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DFSDM_H
+#define __STM32F4xx_HAL_DFSDM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DFSDM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL DFSDM Channel states definition
+ */
+typedef enum
+{
+ HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
+ HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
+ HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
+}HAL_DFSDM_Channel_StateTypeDef;
+
+/**
+ * @brief DFSDM channel output clock structure definition
+ */
+typedef struct
+{
+ FunctionalState Activation; /*!< Output clock enable/disable */
+ uint32_t Selection; /*!< Output clock is system clock or audio clock.
+ This parameter can be a value of @ref DFSDM_Channel_OuputClock */
+ uint32_t Divider; /*!< Output clock divider.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
+}DFSDM_Channel_OutputClockTypeDef;
+
+/**
+ * @brief DFSDM channel input structure definition
+ */
+typedef struct
+{
+ uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
+ This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
+ uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
+ This parameter can be a value of @ref DFSDM_Channel_DataPacking */
+ uint32_t Pins; /*!< Input pins are taken from same or following channel.
+ This parameter can be a value of @ref DFSDM_Channel_InputPins */
+}DFSDM_Channel_InputTypeDef;
+
+/**
+ * @brief DFSDM channel serial interface structure definition
+ */
+typedef struct
+{
+ uint32_t Type; /*!< SPI or Manchester modes.
+ This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
+ uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
+ This parameter can be a value of @ref DFSDM_Channel_SpiClock */
+}DFSDM_Channel_SerialInterfaceTypeDef;
+
+/**
+ * @brief DFSDM channel analog watchdog structure definition
+ */
+typedef struct
+{
+ uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
+ This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
+ uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+}DFSDM_Channel_AwdTypeDef;
+
+/**
+ * @brief DFSDM channel init structure definition
+ */
+typedef struct
+{
+ DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
+ DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
+ DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
+ DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
+ int32_t Offset; /*!< DFSDM channel offset.
+ This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+ uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+}DFSDM_Channel_InitTypeDef;
+
+/**
+ * @brief DFSDM channel handle structure definition
+ */
+typedef struct
+{
+ DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
+ DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
+ HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
+}DFSDM_Channel_HandleTypeDef;
+
+/**
+ * @brief HAL DFSDM Filter states definition
+ */
+typedef enum
+{
+ HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
+ HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */
+ HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */
+ HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */
+ HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
+ HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
+}HAL_DFSDM_Filter_StateTypeDef;
+
+/**
+ * @brief DFSDM filter regular conversion parameters structure definition
+ */
+typedef struct
+{
+ uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
+ This parameter can be a value of @ref DFSDM_Filter_Trigger */
+ FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
+ FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
+}DFSDM_Filter_RegularParamTypeDef;
+
+/**
+ * @brief DFSDM filter injected conversion parameters structure definition
+ */
+typedef struct
+{
+ uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
+ This parameter can be a value of @ref DFSDM_Filter_Trigger */
+ FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
+ FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
+ uint32_t ExtTrigger; /*!< External trigger.
+ This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
+ uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
+ This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
+}DFSDM_Filter_InjectedParamTypeDef;
+
+/**
+ * @brief DFSDM filter parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SincOrder; /*!< Sinc filter order.
+ This parameter can be a value of @ref DFSDM_Filter_SincOrder */
+ uint32_t Oversampling; /*!< Filter oversampling ratio.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+ uint32_t IntOversampling; /*!< Integrator oversampling ratio.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
+}DFSDM_Filter_FilterParamTypeDef;
+
+/**
+ * @brief DFSDM filter init structure definition
+ */
+typedef struct
+{
+ DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
+ DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
+ DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
+}DFSDM_Filter_InitTypeDef;
+
+/**
+ * @brief DFSDM filter handle structure definition
+ */
+typedef struct
+{
+ DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
+ DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
+ DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
+ DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
+ uint32_t RegularContMode; /*!< Regular conversion continuous mode */
+ uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
+ uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
+ uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
+ FunctionalState InjectedScanMode; /*!< Injected scanning mode */
+ uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
+ uint32_t InjConvRemaining; /*!< Injected conversions remaining */
+ HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
+ uint32_t ErrorCode; /*!< DFSDM filter error code */
+}DFSDM_Filter_HandleTypeDef;
+
+/**
+ * @brief DFSDM filter analog watchdog parameters structure definition
+ */
+typedef struct
+{
+ uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
+ This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
+ uint32_t Channel; /*!< Analog watchdog channel selection.
+ This parameter can be a values combination of @ref DFSDM_Channel_Selection */
+ int32_t HighThreshold; /*!< High threshold for the analog watchdog.
+ This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+ int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
+ This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+ uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
+ This parameter can be a values combination of @ref DFSDM_BreakSignals */
+ uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
+ This parameter can be a values combination of @ref DFSDM_BreakSignals */
+}DFSDM_Filter_AwdParamTypeDef;
+
+/**
+ * @}
+ */
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+/**
+ * @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices
+ */
+typedef struct
+{
+ uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin.
+ This parameter can be a value of @ref DFSDM_1_CLOCKIN_SELECTION*/
+ uint32_t DFSDM2ClockIn; /*!< Source selection for DFSDM2_Ckin.
+ This parameter can be a value of @ref DFSDM_2_CLOCKIN_SELECTION*/
+ uint32_t DFSDM1ClockOut; /*!< Source selection for DFSDM1_Ckout.
+ This parameter can be a value of @ref DFSDM_1_CLOCKOUT_SELECTION*/
+ uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout.
+ This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/
+ uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2.
+ This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION
+ @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2
+ @note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */
+ uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4.
+ This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION
+ @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4
+ @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5
+ @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6
+ @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */
+ uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1.
+ This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */
+ uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2.
+ This parameter can be a value of @ref DFSDM_2_DATA_DISTRIBUTION */
+}DFSDM_MultiChannelConfigTypeDef;
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
+/**
+ * @}
+ */
+
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
+ * @{
+ */
+
+/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
+ * @{
+ */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
+ * @{
+ */
+#define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */
+#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
+ * @{
+ */
+#define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */
+#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
+#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
+ * @{
+ */
+#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */
+#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
+ * @{
+ */
+#define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */
+#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
+#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
+#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
+ * @{
+ */
+#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
+ * @{
+ */
+#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
+#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
+#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
+#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
+ * @{
+ */
+#define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */
+#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */
+#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
+ * @{
+ */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+/* Trigger for stm32f413xx and STM32f423xx devices */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For All DFSDM1/2 filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For All DFSDM1/2 filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For All DFSDM1/2 filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */
+#define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM2 filter 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */
+#define DFSDM_FILTER_EXT_TRIG_TIM11_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM2 filter 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0 and 1 */
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM2 filter 2 and 3*/
+#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For All DFSDM1/2 filters */
+#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For All DFSDM1/2 filters */
+#else
+/* Trigger for stm32f412xx devices */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM1 filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM1 filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM1 filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM1 filter 0 and 1*/
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
+ * @{
+ */
+#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
+#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
+#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
+ * @{
+ */
+#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
+#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
+#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
+#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
+#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
+#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
+ * @{
+ */
+#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */
+#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
+ * @{
+ */
+#define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */
+#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */
+#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
+#define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_BreakSignals DFSDM break signals
+ * @{
+ */
+#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */
+#define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */
+#define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */
+#define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */
+#define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
+ * @{
+ */
+/* DFSDM Channels ------------------------------------------------------------*/
+/* The DFSDM channels are defined as follows:
+ - in 16-bit LSB the channel mask is set
+ - in 16-bit MSB the channel number is set
+ e.g. for channel 3 definition:
+ - the channel mask is 0x00000008 (bit 3 is set)
+ - the channel number 3 is 0x00030000
+ --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */
+#define DFSDM_CHANNEL_0 0x00000001U
+#define DFSDM_CHANNEL_1 0x00010002U
+#define DFSDM_CHANNEL_2 0x00020004U
+#define DFSDM_CHANNEL_3 0x00030008U
+#define DFSDM_CHANNEL_4 0x00040010U /* only for stmm32f413xx and stm32f423xx devices */
+#define DFSDM_CHANNEL_5 0x00050020U /* only for stmm32f413xx and stm32f423xx devices */
+#define DFSDM_CHANNEL_6 0x00060040U /* only for stmm32f413xx and stm32f423xx devices */
+#define DFSDM_CHANNEL_7 0x00070080U /* only for stmm32f413xx and stm32f423xx devices */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
+ * @{
+ */
+#define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */
+#define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
+ * @{
+ */
+#define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */
+#define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+/** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection
+ * @{
+ */
+#define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U
+#define DFSDM1_CKOUT_DFSDM1 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection
+ * @{
+ */
+#define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U
+#define DFSDM2_CKOUT_DFSDM2 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection
+ * @{
+ */
+#define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U
+#define DFSDM1_CKIN_PAD 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection
+ * @{
+ */
+#define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U
+#define DFSDM2_CKIN_PAD 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution
+ * @{
+ */
+#define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */
+#define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */
+#define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */
+#define DFSDM1_T4_OC1_BITSTREAM_CKIN1 0x00000000U /* TIM4_OC1 to CLKIN1 */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution
+ * @{
+ */
+#define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */
+#define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */
+#define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */
+#define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */
+#define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */
+#define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */
+#define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */
+#define DFSDM2_T3_OC1_BITSTREAM_CKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution
+ * @{
+ */
+#define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U
+#define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL
+#define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U
+#define DFSDM1_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM1D2SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution
+ * @{
+ */
+#define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U
+#define DFSDM2_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM2D0SEL
+#define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U
+#define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL
+#define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U
+#define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL
+#define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U
+#define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL
+/**
+ * @}
+ */
+
+/** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable
+ * @{
+ */
+#define HAL_MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN
+#define HAL_MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection
+ * @{
+ */
+#define HAL_DFSDM2_CKIN_PAD 0x00040000U
+#define HAL_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
+#define HAL_DFSDM1_CKIN_PAD 0x00000000U
+#define HAL_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection
+ * @{
+ */
+#define HAL_DFSDM2_CKOUT_DFSDM2 0x10000000U
+#define HAL_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
+#define HAL_DFSDM1_CKOUT_DFSDM1 0x00000000U
+#define HAL_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0
+ * @{
+ */
+#define HAL_DATAIN0_DFSDM2_PAD 0x10000000U
+#define HAL_DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL
+#define HAL_DATAIN0_DFSDM1_PAD 0x00000000U
+#define HAL_DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2
+ * @{
+ */
+#define HAL_DATAIN2_DFSDM2_PAD 0x10000000U
+#define HAL_DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL
+#define HAL_DATAIN2_DFSDM1_PAD 0x00000000U
+#define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4
+ * @{
+ */
+#define HAL_DATAIN4_DFSDM2_PAD 0x00000000U
+#define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6
+ * @{
+ */
+#define HAL_DATAIN6_DFSDM2_PAD 0x00000000U
+#define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN
+ * @{
+ */
+#define HAL_DFSDM1_CLKIN0_TIM4OC2 0x01000000U
+#define HAL_DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
+#define HAL_DFSDM1_CLKIN1_TIM4OC1 0x02000000U
+#define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN
+ * @{
+ */
+#define HAL_DFSDM2_CLKIN0_TIM3OC4 0x04000000U
+#define HAL_DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
+#define HAL_DFSDM2_CLKIN1_TIM3OC3 0x08000000U
+#define HAL_DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
+#define HAL_DFSDM2_CLKIN2_TIM3OC2 0x10000000U
+#define HAL_DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
+#define HAL_DFSDM2_CLKIN3_TIM3OC1 0x00000000U
+#define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL*/
+/**
+ * @}
+ */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
+ * @{
+ */
+
+/** @brief Reset DFSDM channel handle state.
+ * @param __HANDLE__ DFSDM channel handle.
+ * @retval None
+ */
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
+
+/** @brief Reset DFSDM filter handle state.
+ * @param __HANDLE__ DFSDM filter handle.
+ * @retval None
+ */
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
+
+/**
+ * @}
+ */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
+ * @{
+ */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
+ * @{
+ */
+/* Channel initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+ * @}
+ */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
+ * @{
+ */
+/* Channel operation functions ************************************************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+
+void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
+ * @{
+ */
+/* Channel state function *****************************************************/
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+ * @}
+ */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
+ * @{
+ */
+/* Filter initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+ * @}
+ */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
+ * @{
+ */
+/* Filter control functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Channel,
+ uint32_t ContinuousMode);
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
+ * @{
+ */
+/* Filter operation functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ DFSDM_Filter_AwdParamTypeDef* awdParam);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+
+void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
+void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+ * @}
+ */
+
+/** @addtogroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
+ * @{
+ */
+/* Filter state functions *****************************************************/
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+ * @}
+ */
+/** @addtogroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions
+ * @{
+ */
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct);
+void HAL_DFSDM_BitstreamClock_Start(void);
+void HAL_DFSDM_BitstreamClock_Stop(void);
+void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY);
+void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY);
+void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source);
+void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source);
+void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source);
+void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source);
+void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source);
+void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source);
+void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
+* @{
+*/
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
+ ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
+#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
+ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
+#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
+ ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
+ ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
+#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
+ ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
+#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
+ ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
+ ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
+ ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
+#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
+ ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
+ ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
+ ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
+#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
+ ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
+ ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
+ ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
+#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
+#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
+#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
+#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+ ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
+#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+ ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
+#if defined (STM32F413xx) || defined (STM32F423xx)
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
+#define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \
+ ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1))
+#else
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
+#endif
+#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
+ ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
+ ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
+#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
+ ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
+ ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
+ ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
+ ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
+ ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
+#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
+#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
+#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
+ ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
+#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU)
+#if defined(DFSDM2_Channel0)
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
+ ((CHANNEL) == DFSDM_CHANNEL_1) || \
+ ((CHANNEL) == DFSDM_CHANNEL_2) || \
+ ((CHANNEL) == DFSDM_CHANNEL_3) || \
+ ((CHANNEL) == DFSDM_CHANNEL_4) || \
+ ((CHANNEL) == DFSDM_CHANNEL_5) || \
+ ((CHANNEL) == DFSDM_CHANNEL_6) || \
+ ((CHANNEL) == DFSDM_CHANNEL_7))
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
+#else
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
+ ((CHANNEL) == DFSDM_CHANNEL_1) || \
+ ((CHANNEL) == DFSDM_CHANNEL_2) || \
+ ((CHANNEL) == DFSDM_CHANNEL_3))
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
+#endif
+#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
+ ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
+#if defined(DFSDM2_Channel0)
+#define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3))
+#define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1))
+#endif /* DFSDM2_Channel0 */
+
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+#define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \
+ ((SELECTION) == HAL_DFSDM2_CKIN_DM) || \
+ ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \
+ ((SELECTION) == HAL_DFSDM1_CKIN_DM))
+#define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \
+ ((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \
+ ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \
+ ((SELECTION) == HAL_DFSDM1_CKOUT_M27))
+#define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \
+ ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \
+ ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \
+ ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1))
+#define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD) || \
+ ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \
+ ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD) || \
+ ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3))
+#define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD) || \
+ ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5))
+#define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD) || \
+ ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7))
+#define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \
+ ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \
+ ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \
+ ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \
+ ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \
+ ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \
+ ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \
+ ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \
+ ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \
+ ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \
+ ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \
+ ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1))
+#define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \
+ ((CLKOUT) == DFSDM1_CKOUT_DFSDM1))
+#define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \
+ ((CLKOUT) == DFSDM2_CKOUT_DFSDM2))
+#define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \
+ ((CLKIN) == DFSDM1_CKIN_PAD))
+#define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \
+ ((CLKIN) == DFSDM2_CKIN_PAD))
+#define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \
+ ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \
+ ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \
+ ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \
+ ((CLK) <= 0x30U))
+
+#define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \
+ ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \
+ ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5) || \
+ ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1) || \
+ ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6) || \
+ ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \
+ ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \
+ ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \
+ ((CLK) <= 0x1E000U))
+
+#define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \
+ ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \
+ ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \
+ ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \
+ ((DISTRIBUTION) <= 0xCU))
+
+#define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \
+ ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \
+ ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \
+ ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \
+ ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \
+ ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \
+ ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \
+ ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \
+ ((DISTRIBUTION) <= 0x1D00U))
+#endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DFSDM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1314 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma.c
+ * @author MCD Application Team
+ * @brief DMA HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Stream
+ (except for internal SRAM/FLASH memories: no initialization is
+ necessary) please refer to Reference manual for connection between peripherals
+ and DMA requests.
+
+ (#) For a given Stream, program the required configuration through the following parameters:
+ Transfer Direction, Source and Destination data formats,
+ Circular, Normal or peripheral flow control mode, Stream Priority level,
+ Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
+ Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+ -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
+ __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred.
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+ (+) Use HAL_DMA_Abort() function to abort the current transfer.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred. In this
+ case the DMA interrupt is configured
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
+ [..]
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+ -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+ possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+ Half-Word data size for the peripheral to access its data register and set Word data size
+ for the Memory to gain in access time. Each two half words will be packed and written in
+ a single access to a Word in the Memory).
+
+ -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+ and Destination. In this case the Peripheral Data Size will be applied to both Source
+ and Destination.
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register */
+ __IO uint32_t Reserved0;
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+ #define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize the DMA Stream source
+ and destination addresses, incrementation and data sizes, transfer direction,
+ circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+ [..]
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ reference manual.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and create the associated handle.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmp = 0U;
+ uint32_t tickstart = HAL_GetTick();
+ DMA_Base_Registers *regs;
+
+ /* Check the DMA peripheral state */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+ assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+ /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+ when FIFO mode is enabled */
+ if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+ {
+ assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+ assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+ assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+ }
+
+ /* Allocate lock resource */
+ __HAL_UNLOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Check if the DMA Stream is effectively disabled */
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get the CR register value */
+ tmp = hdma->Instance->CR;
+
+ /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
+ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
+ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
+
+ /* Prepare the DMA Stream configuration */
+ tmp |= hdma->Init.Channel | hdma->Init.Direction |
+ hdma->Init.PeriphInc | hdma->Init.MemInc |
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ hdma->Init.Mode | hdma->Init.Priority;
+
+ /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ {
+ /* Get memory burst and peripheral burst */
+ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+ }
+
+ /* Write to DMA Stream CR register */
+ hdma->Instance->CR = tmp;
+
+ /* Get the FCR register value */
+ tmp = hdma->Instance->FCR;
+
+ /* Clear Direct mode and FIFO threshold bits */
+ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+ /* Prepare the DMA Stream FIFO configuration */
+ tmp |= hdma->Init.FIFOMode;
+
+ /* The FIFO threshold is not used when the FIFO mode is disabled */
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ {
+ /* Get the FIFO threshold */
+ tmp |= hdma->Init.FIFOThreshold;
+
+ /* Check compatibility between FIFO threshold level and size of the memory burst */
+ /* for INCR4, INCR8, INCR16 bursts */
+ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+ {
+ if (DMA_CheckFifoParam(hdma) != HAL_OK)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Write to DMA Stream FCR */
+ hdma->Instance->FCR = tmp;
+
+ /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+ DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+ /* Clear all interrupt flags */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the DMA peripheral
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+ DMA_Base_Registers *regs;
+
+ /* Check the DMA peripheral state */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the DMA peripheral state */
+ if(hdma->State == HAL_DMA_STATE_BUSY)
+ {
+ /* Return error status */
+ return HAL_BUSY;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+
+ /* Disable the selected DMA Streamx */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Reset DMA Streamx control register */
+ hdma->Instance->CR = 0U;
+
+ /* Reset DMA Streamx number of data to transfer register */
+ hdma->Instance->NDTR = 0U;
+
+ /* Reset DMA Streamx peripheral address register */
+ hdma->Instance->PAR = 0U;
+
+ /* Reset DMA Streamx memory 0 address register */
+ hdma->Instance->M0AR = 0U;
+
+ /* Reset DMA Streamx memory 1 address register */
+ hdma->Instance->M1AR = 0U;
+
+ /* Reset DMA Streamx FIFO control register */
+ hdma->Instance->FCR = 0x00000021U;
+
+ /* Get DMA steam Base Address */
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the DMA Transfer.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Return error status */
+ status = HAL_BUSY;
+ }
+ return status;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+ /* Enable Common interrupts*/
+ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+ hdma->Instance->FCR |= DMA_IT_FE;
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ hdma->Instance->CR |= DMA_IT_HT;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Return error status */
+ status = HAL_BUSY;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Aborts the DMA Transfer.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ *
+ * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
+ * effectively disabled is added. If a Stream is disabled
+ * while a data transfer is ongoing, the current data will be transferred
+ * and the Stream will be effectively disabled only after the transfer of
+ * this single data is finished.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+ uint32_t tickstart = HAL_GetTick();
+
+ if(hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable all the transfer interrupts */
+ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+ hdma->Instance->FCR &= ~(DMA_IT_FE);
+
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ {
+ hdma->Instance->CR &= ~(DMA_IT_HT);
+ }
+
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Check if the DMA Stream is effectively disabled */
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the DMA Transfer in Interrupt mode.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+ if(hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set Abort State */
+ hdma->State = HAL_DMA_STATE_ABORT;
+
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CompleteLevel Specifies the DMA level complete.
+ * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+ * This model could be used for debug purpose.
+ * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t mask_cpltlevel;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t tmpisr;
+
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs;
+
+ if(HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* No transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ __HAL_UNLOCK(hdma);
+ return HAL_ERROR;
+ }
+
+ /* Polling mode not supported in circular mode and double buffering mode */
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
+
+ /* Get the level transfer complete flag */
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Transfer Complete flag */
+ mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+ }
+ else
+ {
+ /* Half Transfer Complete flag */
+ mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+ }
+
+ regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ tmpisr = regs->ISR;
+
+ while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
+ {
+ /* Check for the Timeout (Not applicable in circular mode)*/
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get the ISR register value */
+ tmpisr = regs->ISR;
+
+ if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+ /* Clear the transfer error flag */
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+ }
+
+ if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+
+ /* Clear the FIFO error flag */
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+ }
+
+ if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+
+ /* Clear the Direct Mode error flag */
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+ }
+ }
+
+ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ {
+ if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+ {
+ HAL_DMA_Abort(hdma);
+
+ /* Clear the half transfer and transfer complete flags */
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State= HAL_DMA_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get the level transfer complete flag */
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Clear the half transfer and transfer complete flags */
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ else
+ {
+ /* Clear the half transfer and transfer complete flags */
+ regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Handles DMA interrupt request.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmpisr;
+ __IO uint32_t count = 0U;
+ uint32_t timeout = SystemCoreClock / 9600U;
+
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+ tmpisr = regs->ISR;
+
+ /* Transfer Error Interrupt management ***************************************/
+ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+ {
+ /* Disable the transfer error interrupt */
+ hdma->Instance->CR &= ~(DMA_IT_TE);
+
+ /* Clear the transfer error flag */
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+ }
+ }
+ /* FIFO Error Interrupt management ******************************************/
+ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
+ {
+ /* Clear the FIFO error flag */
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+ }
+ }
+ /* Direct Mode Error Interrupt management ***********************************/
+ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
+ {
+ /* Clear the direct mode error flag */
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+ }
+ }
+ /* Half Transfer Complete Interrupt management ******************************/
+ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+ {
+ /* Clear the half transfer complete flag */
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+
+ /* Multi_Buffering mode enabled */
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+ {
+ /* Current memory buffer used is Memory 0 */
+ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+ {
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ /* Current memory buffer used is Memory 1 */
+ else
+ {
+ if(hdma->XferM1HalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferM1HalfCpltCallback(hdma);
+ }
+ }
+ }
+ else
+ {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+ {
+ /* Disable the half transfer interrupt */
+ hdma->Instance->CR &= ~(DMA_IT_HT);
+ }
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ }
+ }
+ /* Transfer Complete Interrupt management ***********************************/
+ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+ {
+ /* Clear the transfer complete flag */
+ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+
+ if(HAL_DMA_STATE_ABORT == hdma->State)
+ {
+ /* Disable all the transfer interrupts */
+ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+ hdma->Instance->FCR &= ~(DMA_IT_FE);
+
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ {
+ hdma->Instance->CR &= ~(DMA_IT_HT);
+ }
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ if(hdma->XferAbortCallback != NULL)
+ {
+ hdma->XferAbortCallback(hdma);
+ }
+ return;
+ }
+
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+ {
+ /* Current memory buffer used is Memory 0 */
+ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+ {
+ if(hdma->XferM1CpltCallback != NULL)
+ {
+ /* Transfer complete Callback for memory1 */
+ hdma->XferM1CpltCallback(hdma);
+ }
+ }
+ /* Current memory buffer used is Memory 1 */
+ else
+ {
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete Callback for memory0 */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+ /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+ else
+ {
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+ {
+ /* Disable the transfer complete interrupt */
+ hdma->Instance->CR &= ~(DMA_IT_TC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+ }
+
+ /* manage error case */
+ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ {
+ if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+ {
+ hdma->State = HAL_DMA_STATE_ABORT;
+
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
+
+ do
+ {
+ if (++count > timeout)
+ {
+ break;
+ }
+ }
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ if(hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+}
+
+/**
+ * @brief Register callbacks
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID User Callback identifer
+ * a DMA_HandleTypeDef structure as parameter.
+ * @param pCallback pointer to private callbacsk function which has pointer to
+ * a DMA_HandleTypeDef structure as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_M1CPLT_CB_ID:
+ hdma->XferM1CpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+ hdma->XferM1HalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID User Callback identifer
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_M1CPLT_CB_ID:
+ hdma->XferM1CpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+ hdma->XferM1HalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferM1CpltCallback = NULL;
+ hdma->XferM1HalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the DMA state.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+ return hdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Clear DBM bit */
+ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+ /* Configure DMA Stream data length */
+ hdma->Instance->NDTR = DataLength;
+
+ /* Memory to Peripheral */
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Stream destination address */
+ hdma->Instance->PAR = DstAddress;
+
+ /* Configure DMA Stream source address */
+ hdma->Instance->M0AR = SrcAddress;
+ }
+ /* Peripheral to Memory */
+ else
+ {
+ /* Configure DMA Stream source address */
+ hdma->Instance->PAR = SrcAddress;
+
+ /* Configure DMA Stream destination address */
+ hdma->Instance->M0AR = DstAddress;
+ }
+}
+
+/**
+ * @brief Returns the DMA Stream base address depending on stream number
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval Stream base address
+ */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+ uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
+
+ /* lookup table for necessary bitshift of flags within status registers */
+ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+ hdma->StreamIndex = flagBitshiftOffset[stream_number];
+
+ if (stream_number > 3U)
+ {
+ /* return pointer to HISR and HIFCR */
+ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
+ }
+ else
+ {
+ /* return pointer to LISR and LIFCR */
+ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
+ }
+
+ return hdma->StreamBaseAddress;
+}
+
+/**
+ * @brief Check compatibility between FIFO threshold level and size of the memory burst
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmp = hdma->Init.FIFOThreshold;
+
+ /* Memory Data size equal to Byte */
+ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+ {
+ switch (tmp)
+ {
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case DMA_FIFO_THRESHOLD_HALFFULL:
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case DMA_FIFO_THRESHOLD_FULL:
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Memory Data size equal to Half-Word */
+ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ switch (tmp)
+ {
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+ status = HAL_ERROR;
+ break;
+ case DMA_FIFO_THRESHOLD_HALFFULL:
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case DMA_FIFO_THRESHOLD_FULL:
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Memory Data size equal to Word */
+ else
+ {
+ switch (tmp)
+ {
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+ case DMA_FIFO_THRESHOLD_HALFFULL:
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+ status = HAL_ERROR;
+ break;
+ case DMA_FIFO_THRESHOLD_FULL:
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,820 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_H
+#define __STM32F4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @brief DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel used for the specified stream.
+ This parameter can be a value of @ref DMA_Channel_selection */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Stream */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
+ This parameter can be a value of @ref DMA_Priority_level */
+
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+ This parameter can be a value of @ref DMA_FIFO_direct_mode
+ @note The Direct mode (FIFO mode disabled) cannot be used if the
+ memory-to-memory data transfer is configured on the selected stream */
+
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
+ This parameter can be a value of @ref DMA_FIFO_threshold_level */
+
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptible
+ transaction.
+ This parameter can be a value of @ref DMA_Memory_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+ It specifies the amount of data to be transferred in a single non interruptible
+ transaction.
+ This parameter can be a value of @ref DMA_Peripheral_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
+ HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
+ HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
+}HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
+ HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
+ HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Stream_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
+
+ void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
+
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+ uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
+
+ uint32_t StreamIndex; /*!< DMA Stream Index */
+
+}DMA_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @brief DMA Exported constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @brief DMA Error Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
+#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
+#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
+#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
+#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
+#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
+#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Channel_selection DMA Channel selection
+ * @brief DMA channel selection
+ * @{
+ */
+#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
+#if defined (DMA_SxCR_CHSEL_3)
+#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
+#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
+#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */
+#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */
+#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */
+#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */
+#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */
+#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */
+#endif /* DMA_SxCR_CHSEL_3 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @brief DMA data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @brief DMA peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
+#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @brief DMA memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
+#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @brief DMA peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @brief DMA memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @brief DMA mode
+ * @{
+ */
+#define DMA_NORMAL 0x00000000U /*!< Normal mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
+#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @brief DMA priority levels
+ * @{
+ */
+#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+ * @brief DMA FIFO direct mode
+ * @{
+ */
+#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+ * @brief DMA FIFO level
+ * @{
+ */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
+#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_burst DMA Memory burst
+ * @brief DMA memory burst
+ * @{
+ */
+#define DMA_MBURST_SINGLE 0x00000000U
+#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
+#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
+#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+ * @brief DMA peripheral burst
+ * @{
+ */
+#define DMA_PBURST_SINGLE 0x00000000U
+#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @brief DMA interrupts definition
+ * @{
+ */
+#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE 0x00000080U
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @brief DMA flag definitions
+ * @{
+ */
+#define DMA_FLAG_FEIF0_4 0x00000001U
+#define DMA_FLAG_DMEIF0_4 0x00000004U
+#define DMA_FLAG_TEIF0_4 0x00000008U
+#define DMA_FLAG_HTIF0_4 0x00000010U
+#define DMA_FLAG_TCIF0_4 0x00000020U
+#define DMA_FLAG_FEIF1_5 0x00000040U
+#define DMA_FLAG_DMEIF1_5 0x00000100U
+#define DMA_FLAG_TEIF1_5 0x00000200U
+#define DMA_FLAG_HTIF1_5 0x00000400U
+#define DMA_FLAG_TCIF1_5 0x00000800U
+#define DMA_FLAG_FEIF2_6 0x00010000U
+#define DMA_FLAG_DMEIF2_6 0x00040000U
+#define DMA_FLAG_TEIF2_6 0x00080000U
+#define DMA_FLAG_HTIF2_6 0x00100000U
+#define DMA_FLAG_TCIF2_6 0x00200000U
+#define DMA_FLAG_FEIF3_7 0x00400000U
+#define DMA_FLAG_DMEIF3_7 0x01000000U
+#define DMA_FLAG_TEIF3_7 0x02000000U
+#define DMA_FLAG_HTIF3_7 0x04000000U
+#define DMA_FLAG_TCIF3_7 0x08000000U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__ specifies the DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Return the current DMA Stream FIFO filled level.
+ * @param __HANDLE__ DMA handle
+ * @retval The FIFO filling state.
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
+ * and not empty.
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+ * - DMA_FIFOStatus_Empty: when FIFO is empty
+ * - DMA_FIFOStatus_Full: when FIFO is full
+ */
+#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
+
+/**
+ * @brief Enable the specified DMA Stream.
+ * @param __HANDLE__ DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
+
+/**
+ * @brief Disable the specified DMA Stream.
+ * @param __HANDLE__ DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Return the current DMA Stream transfer complete flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ DMA_FLAG_TCIF3_7)
+
+/**
+ * @brief Return the current DMA Stream half transfer complete flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ DMA_FLAG_HTIF3_7)
+
+/**
+ * @brief Return the current DMA Stream transfer error flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ DMA_FLAG_TEIF3_7)
+
+/**
+ * @brief Return the current DMA Stream FIFO error flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified FIFO error flag index.
+ */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+ DMA_FLAG_FEIF3_7)
+
+/**
+ * @brief Return the current DMA Stream direct mode error flag.
+ * @param __HANDLE__ DMA handle
+ * @retval The specified direct mode error flag index.
+ */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ DMA_FLAG_DMEIF3_7)
+
+/**
+ * @brief Get the DMA Stream pending flags.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+
+/**
+ * @brief Clear the DMA Stream pending flags.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+
+/**
+ * @brief Enable the specified DMA Stream interrupts.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the specified DMA Stream interrupts.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval The state of DMA_IT.
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+ ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
+ ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
+
+/**
+ * @brief Writes the number of data units to be transferred on the DMA Stream.
+ * @param __HANDLE__ DMA handle
+ * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
+ * Number of data items depends only on the Peripheral data format.
+ *
+ * @note If Peripheral data format is Bytes: number of data units is equal
+ * to total number of bytes to be transferred.
+ *
+ * @note If Peripheral data format is Half-Word: number of data units is
+ * equal to total number of bytes to be transferred / 2.
+ *
+ * @note If Peripheral data format is Word: number of data units is equal
+ * to total number of bytes to be transferred / 4.
+ *
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.
+ */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
+
+/**
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
+ * @param __HANDLE__ DMA handle
+ *
+ * @retval The number of remaining data units in the current DMA Stream transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
+
+
+/* Include DMA HAL Extension module */
+#include "stm32f4xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @brief DMA Exported functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+ * @brief I/O operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @brief DMA private defines and constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @brief DMA private macros
+ * @{
+ */
+#if defined (DMA_SxCR_CHSEL_3)
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+ ((CHANNEL) == DMA_CHANNEL_1) || \
+ ((CHANNEL) == DMA_CHANNEL_2) || \
+ ((CHANNEL) == DMA_CHANNEL_3) || \
+ ((CHANNEL) == DMA_CHANNEL_4) || \
+ ((CHANNEL) == DMA_CHANNEL_5) || \
+ ((CHANNEL) == DMA_CHANNEL_6) || \
+ ((CHANNEL) == DMA_CHANNEL_7) || \
+ ((CHANNEL) == DMA_CHANNEL_8) || \
+ ((CHANNEL) == DMA_CHANNEL_9) || \
+ ((CHANNEL) == DMA_CHANNEL_10)|| \
+ ((CHANNEL) == DMA_CHANNEL_11)|| \
+ ((CHANNEL) == DMA_CHANNEL_12)|| \
+ ((CHANNEL) == DMA_CHANNEL_13)|| \
+ ((CHANNEL) == DMA_CHANNEL_14)|| \
+ ((CHANNEL) == DMA_CHANNEL_15))
+#else
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+ ((CHANNEL) == DMA_CHANNEL_1) || \
+ ((CHANNEL) == DMA_CHANNEL_2) || \
+ ((CHANNEL) == DMA_CHANNEL_3) || \
+ ((CHANNEL) == DMA_CHANNEL_4) || \
+ ((CHANNEL) == DMA_CHANNEL_5) || \
+ ((CHANNEL) == DMA_CHANNEL_6) || \
+ ((CHANNEL) == DMA_CHANNEL_7))
+#endif /* DMA_SxCR_CHSEL_3 */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR) || \
+ ((MODE) == DMA_PFCTRL))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+ ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+ ((BURST) == DMA_MBURST_INC4) || \
+ ((BURST) == DMA_MBURST_INC8) || \
+ ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+ ((BURST) == DMA_PBURST_INC4) || \
+ ((BURST) == DMA_PBURST_INC8) || \
+ ((BURST) == DMA_PBURST_INC16))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @brief DMA private functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1717 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma2d.c
+ * @author MCD Application Team
+ * @brief DMA2D HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the DMA2D peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Program the required configuration through the following parameters:
+ the transfer mode, the output color mode and the output offset using
+ HAL_DMA2D_Init() function.
+
+ (#) Program the required configuration through the following parameters:
+ the input color mode, the input color, the input alpha value, the alpha mode,
+ and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
+ or/and background layer.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (#) Configure pdata parameter (explained hereafter), destination and data length
+ and enable the transfer using HAL_DMA2D_Start().
+ (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
+ user can specify the value of timeout according to his end application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (#) Configure pdata parameter, destination and data length and enable
+ the transfer using HAL_DMA2D_Start_IT().
+ (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
+ (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback (member
+ of DMA2D handle structure).
+ (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
+ XferErrorCallback.
+
+ -@- In Register-to-Memory transfer mode, pdata parameter is the register
+ color, in Memory-to-memory or Memory-to-Memory with pixel format
+ conversion pdata is the source address.
+
+ -@- Configure the foreground source address, the background source address,
+ the destination and data length then Enable the transfer using
+ HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
+ in interrupt mode
+
+ -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
+ are used if the memory to memory with blending transfer mode is selected.
+
+ (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
+ mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
+
+ (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
+
+ (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
+ consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
+ and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
+ HAL_DMA2D_DisableDeadTime().
+
+ (#) The transfer can be suspended, resumed and aborted using the following
+ functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
+
+ (#) The CLUT loading can be suspended, resumed and aborted using the following
+ functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
+ HAL_DMA2D_CLUTLoading_Abort().
+
+ (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
+
+ (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
+
+ *** DMA2D HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA2D HAL driver :
+
+ (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
+ (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
+ (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
+ (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
+ (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
+ (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
+
+ [..]
+ (@) You can refer to the DMA2D HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA2D DMA2D
+ * @brief DMA2D HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Private types -------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_TimeOut DMA2D Time Out
+ * @{
+ */
+#define DMA2D_TIMEOUT_ABORT 1000U /*!< 1s */
+#define DMA2D_TIMEOUT_SUSPEND 1000U /*!< 1s */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Shifts DMA2D Shifts
+ * @{
+ */
+#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)DMA2D_FGPFCCR_CS_Pos /*!< Required left shift to set foreground CLUT size */
+#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)DMA2D_BGPFCCR_CS_Pos /*!< Required left shift to set background CLUT size */
+
+#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)DMA2D_FGPFCCR_CCM_Pos /*!< Required left shift to set foreground CLUT color mode */
+#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)DMA2D_BGPFCCR_CCM_Pos /*!< Required left shift to set background CLUT color mode */
+
+#define DMA2D_POSITION_AMTCR_DT (uint32_t)DMA2D_AMTCR_DT_Pos /*!< Required left shift to set deadtime value */
+
+#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)DMA2D_FGPFCCR_AM_Pos /*!< Required left shift to set foreground alpha mode */
+#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)DMA2D_BGPFCCR_AM_Pos /*!< Required left shift to set background alpha mode */
+
+#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)DMA2D_FGPFCCR_ALPHA_Pos /*!< Required left shift to set foreground alpha value */
+#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)DMA2D_BGPFCCR_ALPHA_Pos /*!< Required left shift to set background alpha value */
+
+#define DMA2D_POSITION_NLR_PL (uint32_t)DMA2D_NLR_PL_Pos /*!< Required left shift to set pixels per lines value */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup DMA2D_Private_Functions_Prototypes
+ * @{
+ */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DMA2D
+ (+) De-initialize the DMA2D
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA2D according to the specified
+ * parameters in the DMA2D_InitTypeDef and create the associated handle.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Check the DMA2D peripheral state */
+ if(hdma2d == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
+ assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
+ assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
+ assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
+
+ if(hdma2d->State == HAL_DMA2D_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdma2d->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_DMA2D_MspInit(hdma2d);
+ }
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* DMA2D CR register configuration -------------------------------------------*/
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
+
+ /* DMA2D OPFCCR register configuration ---------------------------------------*/
+ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
+
+ /* DMA2D OOR register configuration ------------------------------------------*/
+ MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
+
+ /* Update error code */
+ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+ /* Initialize the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the DMA2D peripheral registers to their default reset
+ * values.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Check the DMA2D peripheral state */
+ if(hdma2d == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Before aborting any DMA2D transfer or CLUT loading, check
+ first whether or not DMA2D clock is enabled */
+ if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
+ {
+ /* Abort DMA2D transfer if any */
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
+ {
+ if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
+ {
+ /* Issue when aborting DMA2D transfer */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Abort background CLUT loading if any */
+ if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+ {
+ if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
+ {
+ /* Issue when aborting background CLUT loading */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Abort foreground CLUT loading if any */
+ if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+ {
+ if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
+ {
+ /* Issue when aborting foreground CLUT loading */
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ }
+
+ /* Carry on with de-initialization of low level hardware */
+ HAL_DMA2D_MspDeInit(hdma2d);
+
+ /* Reset DMA2D control registers*/
+ hdma2d->Instance->CR = 0U;
+ hdma2d->Instance->FGOR = 0U;
+ hdma2d->Instance->BGOR = 0U;
+ hdma2d->Instance->FGPFCCR = 0U;
+ hdma2d->Instance->BGPFCCR = 0U;
+ hdma2d->Instance->OPFCCR = 0U;
+
+ /* Update error code */
+ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+ /* Initialize the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DMA2D MSP.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma2d);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_DMA2D_MspInit can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitializes the DMA2D MSP.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma2d);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_DMA2D_MspDeInit can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the pdata, destination address and data size then
+ start the DMA2D transfer.
+ (+) Configure the source for foreground and background, destination address
+ and data size then start a MultiBuffer DMA2D transfer.
+ (+) Configure the pdata, destination address and data size then
+ start the DMA2D transfer with interrupt.
+ (+) Configure the source for foreground and background, destination address
+ and data size then start a MultiBuffer DMA2D transfer with interrupt.
+ (+) Abort DMA2D transfer.
+ (+) Suspend DMA2D transfer.
+ (+) Resume DMA2D transfer.
+ (+) Enable CLUT transfer.
+ (+) Configure CLUT loading then start transfer in polling mode.
+ (+) Configure CLUT loading then start transfer in interrupt mode.
+ (+) Abort DMA2D CLUT loading.
+ (+) Suspend DMA2D CLUT loading.
+ (+) Resume DMA2D CLUT loading.
+ (+) Poll for transfer complete.
+ (+) handle DMA2D interrupt request.
+ (+) Transfer watermark callback.
+ (+) CLUT Transfer Complete callback.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the DMA2D Transfer.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param pdata Configure the source memory Buffer address if
+ * Memory-to-Memory or Memory-to-Memory with pixel format
+ * conversion mode is selected, or configure
+ * the color value if Register-to-Memory mode is selected.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LINE(Height));
+ assert_param(IS_DMA2D_PIXEL(Width));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+ /* Enable the Peripheral */
+ __HAL_DMA2D_ENABLE(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the DMA2D Transfer with interrupt enabled.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param pdata Configure the source memory Buffer address if
+ * the Memory-to-Memory or Memory-to-Memory with pixel format
+ * conversion mode is selected, or configure
+ * the color value if Register-to-Memory mode is selected.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LINE(Height));
+ assert_param(IS_DMA2D_PIXEL(Width));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+ /* Enable the transfer complete, transfer error and configuration error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+
+ /* Enable the Peripheral */
+ __HAL_DMA2D_ENABLE(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the multi-source DMA2D Transfer.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param SrcAddress1 The source memory Buffer address for the foreground layer.
+ * @param SrcAddress2 The source memory Buffer address for the background layer.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LINE(Height));
+ assert_param(IS_DMA2D_PIXEL(Width));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure DMA2D Stream source2 address */
+ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+
+ /* Enable the Peripheral */
+ __HAL_DMA2D_ENABLE(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param SrcAddress1 The source memory Buffer address for the foreground layer.
+ * @param SrcAddress2 The source memory Buffer address for the background layer.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LINE(Height));
+ assert_param(IS_DMA2D_PIXEL(Width));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure DMA2D Stream source2 address */
+ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+
+ /* Enable the transfer complete, transfer error and configuration error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+
+ /* Enable the Peripheral */
+ __HAL_DMA2D_ENABLE(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the DMA2D Transfer.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
+{
+ uint32_t tickstart = 0U;
+
+ /* Abort the DMA2D transfer */
+ /* START bit is reset to make sure not to set it again, in the event the HW clears it
+ between the register read and the register write by the CPU (writing 0 has no
+ effect on START bitvalue) */
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the DMA2D is effectively disabled */
+ while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+
+ /* Change the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Suspend the DMA2D Transfer.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
+{
+ uint32_t tickstart = 0U;
+
+ /* Suspend the DMA2D transfer */
+ /* START bit is reset to make sure not to set it again, in the event the HW clears it
+ between the register read and the register write by the CPU (writing 0 has no
+ effect on START bitvalue) */
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the DMA2D is effectively suspended */
+ while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
+ && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
+ {
+ if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+ {
+ hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+ }
+ else
+ {
+ /* Make sure SUSP bit is cleared since it is meaningless
+ when no tranfer is on-going */
+ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA2D Transfer.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Check the SUSP and START bits */
+ if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
+ {
+ /* Ongoing transfer is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
+
+ /* Resume the DMA2D transfer */
+ /* START bit is reset to make sure not to set it again, in the event the HW clears it
+ between the register read and the register write by the CPU (writing 0 has no
+ effect on START bitvalue) */
+ CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the DMA2D CLUT Transfer.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ if(LayerIdx == 0U)
+ {
+ /* Enable the background CLUT loading */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ else
+ {
+ /* Enable the foreground CLUT loading */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start DMA2D CLUT Loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if(LayerIdx == 0U)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+
+ /* Enable the CLUT loading for the background */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+
+ /* Enable the CLUT loading for the foreground */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start DMA2D CLUT Loading with interrupt enabled.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if(LayerIdx == 0U)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+
+ /* Enable the CLUT loading for the background */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+
+ /* Enable the CLUT loading for the foreground */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the DMA2D CLUT loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ uint32_t tickstart = 0U;
+ __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+
+ /* Abort the CLUT loading */
+ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
+
+ /* If foreground CLUT loading is considered, update local variables */
+ if(LayerIdx == 1)
+ {
+ reg = &(hdma2d->Instance->FGPFCCR);
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the CLUT loading is aborted */
+ while((*reg & DMA2D_BGPFCCR_START) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+
+ /* Change the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Suspend the DMA2D CLUT loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ uint32_t tickstart = 0U;
+ __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+
+ /* Suspend the CLUT loading */
+ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
+ /* If foreground CLUT loading is considered, update local variables */
+ if(LayerIdx == 1U)
+ {
+ reg = &(hdma2d->Instance->FGPFCCR);
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the CLUT loading is suspended */
+ while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
+ && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
+ {
+ if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+ if ((*reg & DMA2D_BGPFCCR_START) != RESET)
+ {
+ hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+ }
+ else
+ {
+ /* Make sure SUSP bit is cleared since it is meaningless
+ when no tranfer is on-going */
+ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA2D CLUT loading.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ /* Check the SUSP and START bits for background or foreground CLUT loading */
+ if(LayerIdx == 0U)
+ {
+ /* Background CLUT loading suspension check */
+ if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+ && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
+ {
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* Foreground CLUT loading suspension check */
+ if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+ && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
+ {
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
+ }
+
+ /* Resume the CLUT loading */
+ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer complete or CLUT loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ __IO uint32_t isrflags = 0x0U;
+
+ /* Polling for DMA2D transfer */
+ if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
+ {
+ isrflags = READ_REG(hdma2d->Instance->ISR);
+ if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
+ {
+ if ((isrflags & DMA2D_FLAG_CE) != RESET)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+ }
+ if ((isrflags & DMA2D_FLAG_TE) != RESET)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+ }
+ /* Clear the transfer and configuration error flags */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /* Polling for CLUT loading (foreground or background) */
+ if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
+ ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
+ {
+ isrflags = READ_REG(hdma2d->Instance->ISR);
+ if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
+ {
+ if ((isrflags & DMA2D_FLAG_CAE) != RESET)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+ }
+ if ((isrflags & DMA2D_FLAG_CE) != RESET)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+ }
+ if ((isrflags & DMA2D_FLAG_TE) != RESET)
+ {
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+ }
+ /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+ /* Change DMA2D state */
+ hdma2d->State= HAL_DMA2D_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+ /* Change the DMA2D state */
+ hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Clear the transfer complete and CLUT loading flags */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+/**
+ * @brief Handle DMA2D interrupt request.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL status
+ */
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
+{
+ uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
+ uint32_t crflags = READ_REG(hdma2d->Instance->CR);
+
+ /* Transfer Error Interrupt management ***************************************/
+ if ((isrflags & DMA2D_FLAG_TE) != RESET)
+ {
+ if ((crflags & DMA2D_IT_TE) != RESET)
+ {
+ /* Disable the transfer Error interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+
+ /* Clear the transfer error flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ if(hdma2d->XferErrorCallback != NULL)
+ {
+ /* Transfer error Callback */
+ hdma2d->XferErrorCallback(hdma2d);
+ }
+ }
+ }
+ /* Configuration Error Interrupt management **********************************/
+ if ((isrflags & DMA2D_FLAG_CE) != RESET)
+ {
+ if ((crflags & DMA2D_IT_CE) != RESET)
+ {
+ /* Disable the Configuration Error interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
+
+ /* Clear the Configuration error flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ if(hdma2d->XferErrorCallback != NULL)
+ {
+ /* Transfer error Callback */
+ hdma2d->XferErrorCallback(hdma2d);
+ }
+ }
+ }
+ /* CLUT access Error Interrupt management ***********************************/
+ if ((isrflags & DMA2D_FLAG_CAE) != RESET)
+ {
+ if ((crflags & DMA2D_IT_CAE) != RESET)
+ {
+ /* Disable the CLUT access error interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
+
+ /* Clear the CLUT access error flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ if(hdma2d->XferErrorCallback != NULL)
+ {
+ /* Transfer error Callback */
+ hdma2d->XferErrorCallback(hdma2d);
+ }
+ }
+ }
+ /* Transfer watermark Interrupt management **********************************/
+ if ((isrflags & DMA2D_FLAG_TW) != RESET)
+ {
+ if ((crflags & DMA2D_IT_TW) != RESET)
+ {
+ /* Disable the transfer watermark interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
+
+ /* Clear the transfer watermark flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
+
+ /* Transfer watermark Callback */
+ HAL_DMA2D_LineEventCallback(hdma2d);
+ }
+ }
+ /* Transfer Complete Interrupt management ************************************/
+ if ((isrflags & DMA2D_FLAG_TC) != RESET)
+ {
+ if ((crflags & DMA2D_IT_TC) != RESET)
+ {
+ /* Disable the transfer complete interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
+
+ /* Clear the transfer complete flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ if(hdma2d->XferCpltCallback != NULL)
+ {
+ /* Transfer complete Callback */
+ hdma2d->XferCpltCallback(hdma2d);
+ }
+ }
+ }
+ /* CLUT Transfer Complete Interrupt management ******************************/
+ if ((isrflags & DMA2D_FLAG_CTC) != RESET)
+ {
+ if ((crflags & DMA2D_IT_CTC) != RESET)
+ {
+ /* Disable the CLUT transfer complete interrupt */
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
+
+ /* Clear the CLUT transfer complete flag */
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
+
+ /* Update error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
+ /* Change DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ /* CLUT Transfer complete Callback */
+ HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
+ }
+ }
+}
+
+/**
+ * @brief Transfer watermark callback.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma2d);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_DMA2D_LineEventCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief CLUT Transfer Complete callback.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval None
+ */
+__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma2d);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the DMA2D foreground or background layer parameters.
+ (+) Configure the DMA2D CLUT transfer.
+ (+) Configure the line watermark
+ (+) Configure the dead time value.
+ (+) Enable or disable the dead time value functionality.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the DMA2D Layer according to the specified
+ * parameters in the DMA2D_InitTypeDef and create the associated handle.
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+ DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
+ uint32_t regValue = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
+ if(hdma2d->Init.Mode != DMA2D_R2M)
+ {
+ assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
+ if(hdma2d->Init.Mode != DMA2D_M2M)
+ {
+ assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
+ }
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* DMA2D BGPFCR register configuration -----------------------------------*/
+ /* Prepare the value to be written to the BGPFCCR register */
+
+ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+ {
+ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
+ }
+ else
+ {
+ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
+ }
+
+ /* Configure the background DMA2D layer */
+ if(LayerIdx == 0)
+ {
+ /* Write DMA2D BGPFCCR register */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
+
+ /* DMA2D BGOR register configuration -------------------------------------*/
+ WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
+
+ /* DMA2D BGCOLR register configuration -------------------------------------*/
+ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+ {
+ WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
+ }
+ }
+ /* Configure the foreground DMA2D layer */
+ else
+ {
+ /* Write DMA2D FGPFCCR register */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
+
+ /* DMA2D FGOR register configuration -------------------------------------*/
+ WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
+
+ /* DMA2D FGCOLR register configuration -------------------------------------*/
+ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+ {
+ WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
+ }
+ }
+ /* Initialize the DMA2D state*/
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMA2D CLUT Transfer.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if(LayerIdx == 0U)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+ }
+
+ /* Set the DMA2D state to Ready */
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the line watermark.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param Line Line Watermark configuration (maximum 16-bit long value expected).
+ * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
+ * @note The transfer watermark interrupt is disabled once it has occurred.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LINEWATERMARK(Line));
+
+ if (Line > DMA2D_LWR_LW)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Sets the Line watermark configuration */
+ WRITE_REG(hdma2d->Instance->LWR, Line);
+
+ /* Enable the Line interrupt */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
+
+ /* Initialize the DMA2D state */
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Enable DMA2D dead time feature.
+ * @param hdma2d DMA2D handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdma2d);
+
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Set DMA2D_AMTCR EN bit */
+ SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable DMA2D dead time feature.
+ * @param hdma2d DMA2D handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdma2d);
+
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Clear DMA2D_AMTCR EN bit */
+ CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure dead time.
+ * @note The dead time value represents the guaranteed minimum number of cycles between
+ * two consecutive transactions on the AHB bus.
+ * @param hdma2d DMA2D handle.
+ * @param DeadTime dead time value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdma2d);
+
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Set DMA2D_AMTCR DT field */
+ MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
+
+ hdma2d->State = HAL_DMA2D_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma2d);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Get the DMA2D state
+ (+) Get the DMA2D error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the DMA2D state
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @retval HAL state
+ */
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
+{
+ return hdma2d->State;
+}
+
+/**
+ * @brief Return the DMA2D error code
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for DMA2D.
+ * @retval DMA2D Error Code
+ */
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
+{
+ return hdma2d->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
+ * @{
+ */
+
+/**
+ * @brief Set the DMA2D transfer parameters.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA2D.
+ * @param pdata The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param Width The width of data to be transferred from source to destination.
+ * @param Height The height of data to be transferred from source to destination.
+ * @retval HAL status
+ */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+{
+ uint32_t tmp = 0U;
+ uint32_t tmp1 = 0U;
+ uint32_t tmp2 = 0U;
+ uint32_t tmp3 = 0U;
+ uint32_t tmp4 = 0U;
+
+ /* Configure DMA2D data size */
+ MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
+
+ /* Configure DMA2D destination address */
+ WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
+
+ /* Register to memory DMA2D mode selected */
+ if (hdma2d->Init.Mode == DMA2D_R2M)
+ {
+ tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
+ tmp2 = pdata & DMA2D_OCOLR_RED_1;
+ tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
+ tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
+
+ /* Prepare the value to be written to the OCOLR register according to the color mode */
+ if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
+ {
+ tmp = (tmp3 | tmp2 | tmp1| tmp4);
+ }
+ else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
+ {
+ tmp = (tmp3 | tmp2 | tmp4);
+ }
+ else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
+ {
+ tmp2 = (tmp2 >> 19U);
+ tmp3 = (tmp3 >> 10U);
+ tmp4 = (tmp4 >> 3U);
+ tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
+ }
+ else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
+ {
+ tmp1 = (tmp1 >> 31U);
+ tmp2 = (tmp2 >> 19U);
+ tmp3 = (tmp3 >> 11U);
+ tmp4 = (tmp4 >> 3U);
+ tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
+ }
+ else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
+ {
+ tmp1 = (tmp1 >> 28U);
+ tmp2 = (tmp2 >> 20U);
+ tmp3 = (tmp3 >> 12U);
+ tmp4 = (tmp4 >> 4U);
+ tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
+ }
+ /* Write to DMA2D OCOLR register */
+ WRITE_REG(hdma2d->Instance->OCOLR, tmp);
+ }
+ else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
+ {
+ /* Configure DMA2D source address */
+ WRITE_REG(hdma2d->Instance->FGMAR, pdata);
+ }
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,575 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma2d.h
+ * @author MCD Application Team
+ * @brief Header file of DMA2D HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA2D_H
+#define __STM32F4xx_HAL_DMA2D_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA2D DMA2D
+ * @brief DMA2D HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
+ * @{
+ */
+#define MAX_DMA2D_LAYER 2U
+
+/**
+ * @brief DMA2D color Structure definition
+ */
+typedef struct
+{
+ uint32_t Blue; /*!< Configures the blue value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t Green; /*!< Configures the green value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t Red; /*!< Configures the red value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+} DMA2D_ColorTypeDef;
+
+/**
+ * @brief DMA2D CLUT Structure definition
+ */
+typedef struct
+{
+ uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
+
+ uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
+ This parameter can be one value of @ref DMA2D_CLUT_CM. */
+
+ uint32_t Size; /*!< Configures the DMA2D CLUT size.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+} DMA2D_CLUTCfgTypeDef;
+
+/**
+ * @brief DMA2D Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the DMA2D transfer mode.
+ This parameter can be one value of @ref DMA2D_Mode. */
+
+ uint32_t ColorMode; /*!< Configures the color format of the output image.
+ This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
+
+ uint32_t OutputOffset; /*!< Specifies the Offset value.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+} DMA2D_InitTypeDef;
+
+/**
+ * @brief DMA2D Layer structure definition
+ */
+typedef struct
+{
+ uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+ uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
+ This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
+
+ uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
+ This parameter can be one value of @ref DMA2D_Alpha_Mode. */
+
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
+ @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
+ Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
+ - InputAlpha[24:31] is the alpha value ALPHA[0:7]
+ - InputAlpha[16:23] is the red value RED[0:7]
+ - InputAlpha[8:15] is the green value GREEN[0:7]
+ - InputAlpha[0:7] is the blue value BLUE[0:7]. */
+
+} DMA2D_LayerCfgTypeDef;
+
+/**
+ * @brief HAL DMA2D State structures definition
+ */
+typedef enum
+{
+ HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
+ HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
+ HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
+}HAL_DMA2D_StateTypeDef;
+
+/**
+ * @brief DMA2D handle Structure definition
+ */
+typedef struct __DMA2D_HandleTypeDef
+{
+ DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
+
+ DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
+
+ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
+
+ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
+
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA2D lock. */
+
+ __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
+
+ __IO uint32_t ErrorCode; /*!< DMA2D error code. */
+} DMA2D_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_Error_Code DMA2D Error Code
+ * @{
+ */
+#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */
+#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */
+#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */
+#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Mode DMA2D Mode
+ * @{
+ */
+#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
+ * @{
+ */
+#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
+#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
+ * @{
+ */
+#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */
+#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */
+#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */
+#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */
+#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */
+#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */
+#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */
+#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */
+#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */
+#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */
+#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
+ * @{
+ */
+#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
+ with original alpha channel value */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
+ * @{
+ */
+#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */
+#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Interrupts DMA2D Interrupts
+ * @{
+ */
+#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
+#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Flags DMA2D Flags
+ * @{
+ */
+#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+ * @{
+ */
+#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA2D handle state
+ * @param __HANDLE__ specifies the DMA2D handle.
+ * @retval None
+ */
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+
+/**
+ * @brief Enable the DMA2D.
+ * @param __HANDLE__ DMA2D handle
+ * @retval None.
+ */
+#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the DMA2D pending flags.
+ * @param __HANDLE__ DMA2D handle
+ * @param __FLAG__ flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_FLAG_CE: Configuration error flag
+ * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+ * @arg DMA2D_FLAG_CAE: CLUT access error flag
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag
+ * @arg DMA2D_FLAG_TC: Transfer complete flag
+ * @arg DMA2D_FLAG_TE: Transfer error flag
+ * @retval The state of FLAG.
+ */
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+ * @brief Clear the DMA2D pending flags.
+ * @param __HANDLE__ DMA2D handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_FLAG_CE: Configuration error flag
+ * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+ * @arg DMA2D_FLAG_CAE: CLUT access error flag
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag
+ * @arg DMA2D_FLAG_TC: Transfer complete flag
+ * @arg DMA2D_FLAG_TE: Transfer error flag
+ * @retval None
+ */
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
+
+/**
+ * @brief Enable the specified DMA2D interrupts.
+ * @param __HANDLE__ DMA2D handle
+ * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified DMA2D interrupts.
+ * @param __HANDLE__ DMA2D handle
+ * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified DMA2D interrupt source is enabled or not.
+ * @param __HANDLE__ DMA2D handle
+ * @param __INTERRUPT__ specifies the DMA2D interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval The state of INTERRUPT source.
+ */
+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
+ * @{
+ */
+
+/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State functions ***************************************************/
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
+ * @{
+ */
+#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Color_Value DMA2D Color Value
+ * @{
+ */
+#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
+ * @{
+ */
+#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Offset DMA2D Offset
+ * @{
+ */
+#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Size DMA2D Size
+ * @{
+ */
+#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */
+#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
+ * @{
+ */
+#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D CLUT size */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
+ * @{
+ */
+#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER)
+#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
+ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
+#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
+#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
+#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
+ ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
+ ((INPUT_CM) == DMA2D_INPUT_A4))
+#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
+ ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+
+#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
+#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA2D_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,331 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma_ex.c
+ * @author MCD Application Team
+ * @brief DMA Extension HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities of the DMA Extension peripheral:
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The DMA Extension HAL driver can be used as follows:
+ (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+ for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+
+ -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+ -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
+ -@- In Multi (Double) buffer mode, it is possible to update the base address for
+ the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMAEx DMAEx
+ * @brief DMA Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+ * @{
+ */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and
+ Start MultiBuffer DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start MultiBuffer DMA transfer with interrupt
+ (+) Change on the fly the memory0 or memory1 address.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Starts the multi_buffer DMA Transfer.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Memory-to-memory transfer not supported in double buffering mode */
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Process Locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Enable the double buffer mode */
+ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+
+ /* Configure DMA Stream destination address */
+ hdma->Instance->M1AR = SecondMemAddress;
+
+ /* Configure the source, destination address and the data length */
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_BUSY;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Memory-to-memory transfer not supported in double buffering mode */
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
+
+ /* Check callback functions */
+ if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Enable the Double buffer mode */
+ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+
+ /* Configure DMA Stream destination address */
+ hdma->Instance->M1AR = SecondMemAddress;
+
+ /* Configure the source, destination address and the data length */
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+
+ /* Enable Common interrupts*/
+ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+ hdma->Instance->FCR |= DMA_IT_FE;
+
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ {
+ hdma->Instance->CR |= DMA_IT_HT;
+ }
+
+ /* Enable the peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Return error status */
+ status = HAL_BUSY;
+ }
+ return status;
+}
+
+/**
+ * @brief Change the memory0 or memory1 address on the fly.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param Address The new address
+ * @param memory the memory to be changed, This parameter can be one of
+ * the following values:
+ * MEMORY0 /
+ * MEMORY1
+ * @note The MEMORY0 address can be changed only when the current transfer use
+ * MEMORY1 and the MEMORY1 address can be changed only when the current
+ * transfer use MEMORY0.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+ if(memory == MEMORY0)
+ {
+ /* change the memory0 address */
+ hdma->Instance->M0AR = Address;
+ }
+ else
+ {
+ /* change the memory1 address */
+ hdma->Instance->M1AR = Address;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMAEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Set the DMA Transfer parameter.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Configure DMA Stream data length */
+ hdma->Instance->NDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Stream destination address */
+ hdma->Instance->PAR = DstAddress;
+
+ /* Configure DMA Stream source address */
+ hdma->Instance->M0AR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Stream source address */
+ hdma->Instance->PAR = SrcAddress;
+
+ /* Configure DMA Stream destination address */
+ hdma->Instance->M0AR = DstAddress;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,120 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_EX_H
+#define __STM32F4xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+ * @brief DMAEx Exported types
+ * @{
+ */
+
+/**
+ * @brief HAL DMA Memory definition
+ */
+typedef enum
+{
+ MEMORY0 = 0x00U, /*!< Memory 0 */
+ MEMORY1 = 0x01U /*!< Memory 1 */
+}HAL_DMA_MemoryTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+ * @brief DMAEx Exported functions
+ * @{
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ * @{
+ */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+ * @brief DMAEx Private functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DMA_EX_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2379 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dsi.c
+ * @author MCD Application Team
+ * @brief DSI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the DSI peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+
+#if defined(DSI)
+
+/** @addtogroup DSI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @addtogroup DSI_Private_Constants
+ * @{
+ */
+#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
+
+#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
+ DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
+ DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
+ DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
+#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
+#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
+#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
+#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
+#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
+#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
+#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
+#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
+#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
+
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @brief Generic DSI packet header configuration
+ * @param DSIx Pointer to DSI register base
+ * @param ChannelID Virtual channel ID of the header packet
+ * @param DataType Packet data type of the header packet
+ * This parameter can be any value of :
+ * @ref DSI_SHORT_WRITE_PKT_Data_Type
+ * or @ref DSI_LONG_WRITE_PKT_Data_Type
+ * or @ref DSI_SHORT_READ_PKT_Data_Type
+ * or DSI_MAX_RETURN_PKT_SIZE
+ * @param Data0 Word count LSB
+ * @param Data1 Word count MSB
+ * @retval None
+ */
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
+ uint32_t ChannelID,
+ uint32_t DataType,
+ uint32_t Data0,
+ uint32_t Data1)
+{
+ /* Update the DSI packet header with new information */
+ DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U));
+}
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DSI_Exported_Functions
+ * @{
+ */
+
+/** @defgroup DSI_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DSI
+ (+) De-initialize the DSI
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DSI according to the specified
+ * parameters in the DSI_InitTypeDef and create the associated handle.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
+ * the PLL Clock structure definition for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
+{
+ uint32_t tickstart;
+ uint32_t unitIntervalx4;
+ uint32_t tempIDF;
+
+ /* Check the DSI handle allocation */
+ if(hdsi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
+ assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
+ assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
+ assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
+ assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
+
+ if(hdsi->State == HAL_DSI_STATE_RESET)
+ {
+ /* Initialize the low level hardware */
+ HAL_DSI_MspInit(hdsi);
+ }
+
+ /* Change DSI peripheral state */
+ hdsi->State = HAL_DSI_STATE_BUSY;
+
+ /**************** Turn on the regulator and enable the DSI PLL ****************/
+
+ /* Enable the regulator */
+ __HAL_DSI_REG_ENABLE(hdsi);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the regulator is ready */
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the PLL division factors */
+ hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
+ hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U));
+
+ /* Enable the DSI PLL */
+ __HAL_DSI_PLL_ENABLE(hdsi);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for the lock of the PLL */
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*************************** Set the PHY parameters ***************************/
+
+ /* D-PHY clock and digital enable*/
+ hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+
+ /* Clock lane configuration */
+ hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
+ hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
+
+ /* Configure the number of active data lanes */
+ hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
+ hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
+
+ /************************ Set the DSI clock parameters ************************/
+
+ /* Set the TX escape clock division factor */
+ hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
+ hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+
+ /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
+ /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
+ /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
+ tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
+ unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
+
+ /* Set the bit period in high-speed mode */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
+ hdsi->Instance->WPCR[0U] |= unitIntervalx4;
+
+ /****************************** Error management *****************************/
+
+ /* Disable all error interrupts and reset the Error Mask */
+ hdsi->Instance->IER[0U] = 0U;
+ hdsi->Instance->IER[1U] = 0U;
+ hdsi->ErrorMsk = 0U;
+
+ /* Initialise the error code */
+ hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
+
+ /* Initialize the DSI state*/
+ hdsi->State = HAL_DSI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initializes the DSI peripheral registers to their default reset
+ * values.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
+{
+ /* Check the DSI handle allocation */
+ if(hdsi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change DSI peripheral state */
+ hdsi->State = HAL_DSI_STATE_BUSY;
+
+ /* Disable the DSI wrapper */
+ __HAL_DSI_WRAPPER_DISABLE(hdsi);
+
+ /* Disable the DSI host */
+ __HAL_DSI_DISABLE(hdsi);
+
+ /* D-PHY clock and digital disable */
+ hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+
+ /* Turn off the DSI PLL */
+ __HAL_DSI_PLL_DISABLE(hdsi);
+
+ /* Disable the regulator */
+ __HAL_DSI_REG_DISABLE(hdsi);
+
+ /* DeInit the low level hardware */
+ HAL_DSI_MspDeInit(hdsi);
+
+ /* Initialise the error code */
+ hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
+
+ /* Initialize the DSI state*/
+ hdsi->State = HAL_DSI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the error monitor flags
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ActiveErrors indicates which error interrupts will be enabled.
+ * This parameter can be any combination of @ref DSI_Error_Data_Type.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ hdsi->Instance->IER[0U] = 0U;
+ hdsi->Instance->IER[1U] = 0U;
+
+ /* Store active errors to the handle */
+ hdsi->ErrorMsk = ActiveErrors;
+
+ if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
+ }
+
+ if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
+ }
+
+ if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
+ }
+
+ if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
+ }
+
+ if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
+ }
+
+ if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
+ }
+
+ if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
+ }
+
+ if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
+ }
+
+ if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
+ }
+
+ if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
+ {
+ /* Enable the interrupt generation on selected errors */
+ hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DSI MSP.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdsi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-initializes the DSI MSP.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdsi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides function allowing to:
+ (+) Handle DSI interrupt request
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Handles DSI interrupt request.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t ErrorStatus0, ErrorStatus1;
+
+ /* Tearing Effect Interrupt management ***************************************/
+ if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
+ {
+ if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
+ {
+ /* Clear the Tearing Effect Interrupt Flag */
+ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
+
+ /* Tearing Effect Callback */
+ HAL_DSI_TearingEffectCallback(hdsi);
+ }
+ }
+
+ /* End of Refresh Interrupt management ***************************************/
+ if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
+ {
+ if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
+ {
+ /* Clear the End of Refresh Interrupt Flag */
+ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
+
+ /* End of Refresh Callback */
+ HAL_DSI_EndOfRefreshCallback(hdsi);
+ }
+ }
+
+ /* Error Interrupts management ***********************************************/
+ if(hdsi->ErrorMsk != 0U)
+ {
+ ErrorStatus0 = hdsi->Instance->ISR[0U];
+ ErrorStatus0 &= hdsi->Instance->IER[0U];
+ ErrorStatus1 = hdsi->Instance->ISR[1U];
+ ErrorStatus1 &= hdsi->Instance->IER[1U];
+
+ if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
+ }
+
+ if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
+ }
+
+ if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
+ }
+
+ if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
+ }
+
+ if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
+ }
+
+ if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
+ }
+
+ if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
+ }
+
+ if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
+ }
+
+ if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
+ }
+
+ if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
+ {
+ hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
+ }
+
+ /* Check only selected errors */
+ if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
+ {
+ /* DSI error interrupt user callback */
+ HAL_DSI_ErrorCallback(hdsi);
+ }
+ }
+}
+
+/**
+ * @brief Tearing Effect DSI callback.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdsi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_TearingEffectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief End of Refresh DSI callback.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdsi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Operation Error DSI callback.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval None
+ */
+__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdsi);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DSI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the Generic interface read-back Virtual Channel ID
+ (+) Select video mode and configure the corresponding parameters
+ (+) Configure command transmission mode: High-speed or Low-power
+ (+) Configure the flow control
+ (+) Configure the DSI PHY timer
+ (+) Configure the DSI HOST timeout
+ (+) Configure the DSI HOST timeout
+ (+) Start/Stop the DSI module
+ (+) Refresh the display in command mode
+ (+) Controls the display color mode in Video mode
+ (+) Control the display shutdown in Video mode
+ (+) write short DCS or short Generic command
+ (+) write long DCS or long Generic command
+ (+) Read command (DCS or generic)
+ (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
+ (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
+ (+) Start/Stop test pattern generation
+ (+) Slew-Rate And Delay Tuning
+ (+) Low-Power Reception Filter Tuning
+ (+) Activate an additional current path on all lanes to meet the SDDTx parameter
+ (+) Custom lane pins configuration
+ (+) Set custom timing for the PHY
+ (+) Force the Clock/Data Lane in TX Stop Mode
+ (+) Force LP Receiver in Low-Power Mode
+ (+) Force Data Lanes in RX Mode after a BTA
+ (+) Enable a pull-down on the lanes to prevent from floating states when unused
+ (+) Switch off the contention detection on data lanes
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the Generic interface read-back Virtual Channel ID.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param VirtualChannelID Virtual channel ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Update the GVCID register */
+ hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
+ hdsi->Instance->GVCIDR |= VirtualChannelID;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Select video mode and configure the corresponding parameters
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
+ * the DSI video mode configuration parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
+ assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
+ assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
+ assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
+ assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
+ assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
+ assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
+ assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
+ assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
+ assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
+ assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
+ assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
+ assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
+ /* Check the LooselyPacked variant only in 18-bit mode */
+ if(VidCfg->ColorCoding == DSI_RGB666)
+ {
+ assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
+ }
+
+ /* Select video mode by resetting CMDM and DSIM bits */
+ hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
+
+ /* Configure the video mode transmission type */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
+ hdsi->Instance->VMCR |= VidCfg->Mode;
+
+ /* Configure the video packet size */
+ hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
+ hdsi->Instance->VPCR |= VidCfg->PacketSize;
+
+ /* Set the chunks number to be transmitted through the DSI link */
+ hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
+ hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
+
+ /* Set the size of the null packet */
+ hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
+ hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
+
+ /* Select the virtual channel for the LTDC interface traffic */
+ hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
+ hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
+
+ /* Configure the polarity of control signals */
+ hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
+ hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
+
+ /* Select the color coding for the host */
+ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
+ hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
+
+ /* Select the color coding for the wrapper */
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
+ hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U);
+
+ /* Enable/disable the loosely packed variant to 18-bit configuration */
+ if(VidCfg->ColorCoding == DSI_RGB666)
+ {
+ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
+ hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
+ }
+
+ /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
+ hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
+ hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
+
+ /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
+ hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
+ hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
+
+ /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
+ hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
+ hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
+
+ /* Set the Vertical Synchronization Active (VSA) */
+ hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
+ hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
+
+ /* Set the Vertical Back Porch (VBP)*/
+ hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
+ hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
+
+ /* Set the Vertical Front Porch (VFP)*/
+ hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
+ hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
+
+ /* Set the Vertical Active period*/
+ hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
+ hdsi->Instance->VVACR |= VidCfg->VerticalActive;
+
+ /* Configure the command transmission mode */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
+ hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
+
+ /* Low power largest packet size */
+ hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
+ hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U);
+
+ /* Low power VACT largest packet size */
+ hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
+ hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
+
+ /* Enable LP transition in HFP period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
+ hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
+
+ /* Enable LP transition in HBP period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
+ hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
+
+ /* Enable LP transition in VACT period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
+
+ /* Enable LP transition in VFP period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
+
+ /* Enable LP transition in VBP period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
+
+ /* Enable LP transition in vertical sync period */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
+ hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
+
+ /* Enable the request for an acknowledge response at the end of a frame */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
+ hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Select adapted command mode and configure the corresponding parameters
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
+ * the DSI command mode configuration parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
+ assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
+ assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
+ assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
+ assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
+ assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
+ assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
+ assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
+ assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
+
+ /* Select command mode by setting CMDM and DSIM bits */
+ hdsi->Instance->MCR |= DSI_MCR_CMDM;
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
+ hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
+
+ /* Select the virtual channel for the LTDC interface traffic */
+ hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
+ hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
+
+ /* Configure the polarity of control signals */
+ hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
+ hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
+
+ /* Select the color coding for the host */
+ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
+ hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
+
+ /* Select the color coding for the wrapper */
+ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
+ hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U);
+
+ /* Configure the maximum allowed size for write memory command */
+ hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
+ hdsi->Instance->LCCR |= CmdCfg->CommandSize;
+
+ /* Configure the tearing effect source and polarity and select the refresh mode */
+ hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
+ hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
+
+ /* Configure the tearing effect acknowledge request */
+ hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
+ hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
+
+ /* Enable the Tearing Effect interrupt */
+ __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
+
+ /* Enable the End of Refresh interrupt */
+ __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure command transmission mode: High-speed or Low-power
+ * and enable/disable acknowledge request after packet transmission
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains
+ * the DSI command transmission mode configuration parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
+ assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
+ assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
+ assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
+ assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
+ assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
+ assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
+ assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
+ assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
+ assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
+ assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
+ assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
+ assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
+
+ /* Select High-speed or Low-power for command transmission */
+ hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
+ DSI_CMCR_GSW1TX |\
+ DSI_CMCR_GSW2TX |\
+ DSI_CMCR_GSR0TX |\
+ DSI_CMCR_GSR1TX |\
+ DSI_CMCR_GSR2TX |\
+ DSI_CMCR_GLWTX |\
+ DSI_CMCR_DSW0TX |\
+ DSI_CMCR_DSW1TX |\
+ DSI_CMCR_DSR0TX |\
+ DSI_CMCR_DLWTX |\
+ DSI_CMCR_MRDPS);
+ hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
+ LPCmd->LPGenShortWriteOneP |\
+ LPCmd->LPGenShortWriteTwoP |\
+ LPCmd->LPGenShortReadNoP |\
+ LPCmd->LPGenShortReadOneP |\
+ LPCmd->LPGenShortReadTwoP |\
+ LPCmd->LPGenLongWrite |\
+ LPCmd->LPDcsShortWriteNoP |\
+ LPCmd->LPDcsShortWriteOneP |\
+ LPCmd->LPDcsShortReadNoP |\
+ LPCmd->LPDcsLongWrite |\
+ LPCmd->LPMaxReadPacket);
+
+ /* Configure the acknowledge request after each packet transmission */
+ hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
+ hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the flow control parameters
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param FlowControl flow control feature(s) to be enabled.
+ * This parameter can be any combination of @ref DSI_FlowControl.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
+
+ /* Set the DSI Host Protocol Configuration Register */
+ hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
+ hdsi->Instance->PCR |= FlowControl;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DSI PHY timer parameters
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains
+ * the DSI PHY timing parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
+{
+ uint32_t maxTime;
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
+
+ /* Clock lane timer configuration */
+
+ /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
+ High-Speed transmission.
+ To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
+ to Low-Power and from Low-Power to High-Speed.
+ This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
+ But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
+
+ Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
+ */
+ hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
+ hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U));
+
+ /* Data lane timer configuration */
+ hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
+ hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U));
+
+ /* Configure the wait period to request HS transmission after a stop state */
+ hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
+ hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DSI HOST timeout parameters
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains
+ * the DSI host timeout parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Set the timeout clock division factor */
+ hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
+ hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U);
+
+ /* High-speed transmission timeout */
+ hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
+ hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U);
+
+ /* Low-power reception timeout */
+ hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
+ hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
+
+ /* High-speed read timeout */
+ hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
+ hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
+
+ /* Low-power read timeout */
+ hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
+ hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
+
+ /* High-speed write timeout */
+ hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
+ hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
+
+ /* High-speed write presp mode */
+ hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
+ hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
+
+ /* Low-speed write timeout */
+ hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
+ hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
+
+ /* BTA timeout */
+ hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
+ hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the DSI module
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Enable the DSI host */
+ __HAL_DSI_ENABLE(hdsi);
+
+ /* Enable the DSI wrapper */
+ __HAL_DSI_WRAPPER_ENABLE(hdsi);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DSI module
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Disable the DSI host */
+ __HAL_DSI_DISABLE(hdsi);
+
+ /* Disable the DSI wrapper */
+ __HAL_DSI_WRAPPER_DISABLE(hdsi);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Refresh the display in command mode
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Update the display */
+ hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Controls the display color mode in Video mode
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ColorMode Color mode (full or 8-colors).
+ * This parameter can be any value of @ref DSI_Color_Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_COLOR_MODE(ColorMode));
+
+ /* Update the display color mode */
+ hdsi->Instance->WCR &= ~DSI_WCR_COLM;
+ hdsi->Instance->WCR |= ColorMode;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Control the display shutdown in Video mode
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Shutdown Shut-down (Display-ON or Display-OFF).
+ * This parameter can be any value of @ref DSI_ShutDown
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_SHUT_DOWN(Shutdown));
+
+ /* Update the display Shutdown */
+ hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
+ hdsi->Instance->WCR |= Shutdown;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief write short DCS or short Generic command
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ChannelID Virtual channel ID.
+ * @param Mode DSI short packet data type.
+ * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
+ * @param Param1 DSC command or first generic parameter.
+ * This parameter can be any value of @ref DSI_DCS_Command or a
+ * generic command code.
+ * @param Param2 DSC parameter or second generic parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2)
+{
+ uint32_t tickstart;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for Command FIFO Empty */
+ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the packet to send a short DCS command with 0 or 1 parameter */
+ DSI_ConfigPacketHeader(hdsi->Instance,
+ ChannelID,
+ Mode,
+ Param1,
+ Param2);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief write long DCS or long Generic command
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ChannelID Virtual channel ID.
+ * @param Mode DSI long packet data type.
+ * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
+ * @param NbParams Number of parameters.
+ * @param Param1 DSC command or first generic parameter.
+ * This parameter can be any value of @ref DSI_DCS_Command or a
+ * generic command code
+ * @param ParametersTable Pointer to parameter values table.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t NbParams,
+ uint32_t Param1,
+ uint8_t* ParametersTable)
+{
+ uint32_t uicounter, nbBytes, count;
+ uint32_t tickstart;
+ uint32_t fifoword;
+ uint8_t* pparams = ParametersTable;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for Command FIFO Empty */
+ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
+ fifoword = Param1;
+ nbBytes = (NbParams < 3U) ? NbParams : 3U;
+
+ for(count = 0U; count < nbBytes; count++)
+ {
+ fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count)));
+ }
+ hdsi->Instance->GPDR = fifoword;
+
+ uicounter = NbParams - nbBytes;
+ pparams += nbBytes;
+ /* Set the Next parameters on the write FIFO command*/
+ while(uicounter != 0U)
+ {
+ nbBytes = (uicounter < 4U) ? uicounter : 4U;
+ fifoword = 0U;
+ for(count = 0U; count < nbBytes; count++)
+ {
+ fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count));
+ }
+ hdsi->Instance->GPDR = fifoword;
+
+ uicounter -= nbBytes;
+ pparams += nbBytes;
+ }
+
+ /* Configure the packet to send a long DCS command */
+ DSI_ConfigPacketHeader(hdsi->Instance,
+ ChannelID,
+ Mode,
+ ((NbParams+1U)&0x00FFU),
+ (((NbParams+1U)&0xFF00U)>>8U));
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read command (DCS or generic)
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ChannelNbr Virtual channel ID
+ * @param Array pointer to a buffer to store the payload of a read back operation.
+ * @param Size Data size to be read (in byte).
+ * @param Mode DSI read packet data type.
+ * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
+ * @param DCSCmd DCS get/read command.
+ * @param ParametersTable Pointer to parameter values table.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelNbr,
+ uint8_t* Array,
+ uint32_t Size,
+ uint32_t Mode,
+ uint32_t DCSCmd,
+ uint8_t* ParametersTable)
+{
+ uint32_t tickstart;
+ uint8_t* pdata = Array;
+ uint32_t datasize = Size;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check the parameters */
+ assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
+
+ if(datasize > 2U)
+ {
+ /* set max return packet size */
+ if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Configure the packet to read command */
+ if (Mode == DSI_DCS_SHORT_PKT_READ)
+ {
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
+ }
+ else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
+ {
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
+ }
+ else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
+ {
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
+ }
+ else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
+ {
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check that the payload read FIFO is not empty */
+ while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get the first byte */
+ *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
+ if (datasize > 4U)
+ {
+ datasize -= 4U;
+ pdata += 4U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Get the remaining bytes if any */
+ while(((int)(datasize)) > 0)
+ {
+ if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
+ {
+ *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
+ datasize -= 4U;
+ pdata += 4U;
+ }
+
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
+ * (only data lanes are in ULPM)
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t tickstart;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* ULPS Request on Data Lanes */
+ hdsi->Instance->PUCR |= DSI_PUCR_URDL;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the D-PHY active lanes enter into ULPM */
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
+ * (only data lanes are in ULPM)
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t tickstart;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Exit ULPS on Data Lanes */
+ hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until all active lanes exit ULPM */
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
+ /* wait for 1 ms*/
+ HAL_Delay(1U);
+
+ /* De-assert the ULPM requests and the ULPM exit bits */
+ hdsi->Instance->PUCR = 0U;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
+ * (both data and clock lanes are in ULPM)
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t tickstart;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Clock lane configuration: no more HS request */
+ hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
+
+ /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
+ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
+
+ /* ULPS Request on Clock and Data Lanes */
+ hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until all active lanes exit ULPM */
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
+ /* Turn off the DSI PLL */
+ __HAL_DSI_PLL_DISABLE(hdsi);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
+ * (both data and clock lanes are in ULPM)
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
+{
+ uint32_t tickstart;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Turn on the DSI PLL */
+ __HAL_DSI_PLL_ENABLE(hdsi);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for the lock of the PLL */
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Exit ULPS on Clock and Data Lanes */
+ hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until all active lanes exit ULPM */
+ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+ {
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
+ /* wait for 1 ms */
+ HAL_Delay(1U);
+
+ /* De-assert the ULPM requests and the ULPM exit bits */
+ hdsi->Instance->PUCR = 0U;
+
+ /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
+ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
+
+ /* Restore clock lane configuration to HS */
+ hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start test pattern generation
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Mode Pattern generator mode
+ * This parameter can be one of the following values:
+ * 0 : Color bars (horizontal or vertical)
+ * 1 : BER pattern (vertical only)
+ * @param Orientation Pattern generator orientation
+ * This parameter can be one of the following values:
+ * 0 : Vertical color bars
+ * 1 : Horizontal color bars
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Configure pattern generator mode and orientation */
+ hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
+ hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U));
+
+ /* Enable pattern generator by setting PGE bit */
+ hdsi->Instance->VMCR |= DSI_VMCR_PGE;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop test pattern generation
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Disable pattern generator by clearing PGE bit */
+ hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Slew-Rate And Delay Tuning
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param CommDelay Communication delay to be adjusted.
+ * This parameter can be any value of @ref DSI_Communication_Delay
+ * @param Lane select between clock or data lanes.
+ * This parameter can be any value of @ref DSI_Lane_Group
+ * @param Value Custom value of the slew-rate or delay
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
+ assert_param(IS_DSI_LANE_GROUP(Lane));
+
+ switch(CommDelay)
+ {
+ case DSI_SLEW_RATE_HSTX:
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* High-Speed Transmission Slew Rate Control on Clock Lane */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
+ hdsi->Instance->WPCR[1U] |= Value<<16U;
+ }
+ else if(Lane == DSI_DATA_LANES)
+ {
+ /* High-Speed Transmission Slew Rate Control on Data Lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
+ hdsi->Instance->WPCR[1U] |= Value<<18U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ case DSI_SLEW_RATE_LPTX:
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* Low-Power transmission Slew Rate Compensation on Clock Lane */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
+ hdsi->Instance->WPCR[1U] |= Value<<6U;
+ }
+ else if(Lane == DSI_DATA_LANES)
+ {
+ /* Low-Power transmission Slew Rate Compensation on Data Lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
+ hdsi->Instance->WPCR[1U] |= Value<<8U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ case DSI_HS_DELAY:
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* High-Speed Transmission Delay on Clock Lane */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
+ hdsi->Instance->WPCR[1U] |= Value;
+ }
+ else if(Lane == DSI_DATA_LANES)
+ {
+ /* High-Speed Transmission Delay on Data Lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
+ hdsi->Instance->WPCR[1U] |= Value<<2U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Low-Power Reception Filter Tuning
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Frequency cutoff frequency of low-pass filter at the input of LPRX
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Low-Power RX low-pass Filtering Tuning */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
+ hdsi->Instance->WPCR[1U] |= Frequency<<25U;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
+ * defined in the MIPI D-PHY specification
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Activate/Disactivate additional current path on all lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
+ hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Custom lane pins configuration
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param CustomLane Function to be applyed on selected lane.
+ * This parameter can be any value of @ref DSI_CustomLane
+ * @param Lane select between clock or data lane 0 or data lane 1.
+ * This parameter can be any value of @ref DSI_Lane_Select
+ * @param State ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
+ assert_param(IS_DSI_LANE(Lane));
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ switch(CustomLane)
+ {
+ case DSI_SWAP_LANE_PINS:
+ if(Lane == DSI_CLK_LANE)
+ {
+ /* Swap pins on clock lane */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
+ }
+ else if(Lane == DSI_DATA_LANE0)
+ {
+ /* Swap pins on data lane 0 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
+ }
+ else if(Lane == DSI_DATA_LANE1)
+ {
+ /* Swap pins on data lane 1 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ case DSI_INVERT_HS_SIGNAL:
+ if(Lane == DSI_CLK_LANE)
+ {
+ /* Invert HS signal on clock lane */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
+ }
+ else if(Lane == DSI_DATA_LANE0)
+ {
+ /* Invert HS signal on data lane 0 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
+ }
+ else if(Lane == DSI_DATA_LANE1)
+ {
+ /* Invert HS signal on data lane 1 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set custom timing for the PHY
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Timing PHY timing to be adjusted.
+ * This parameter can be any value of @ref DSI_PHY_Timing
+ * @param State ENABLE or DISABLE
+ * @param Value Custom value of the timing
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_DSI_PHY_TIMING(Timing));
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ switch(Timing)
+ {
+ case DSI_TCLK_POST:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
+
+ if(State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
+ hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
+ }
+
+ break;
+ case DSI_TLPX_CLK:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
+
+ if(State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
+ hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
+ }
+
+ break;
+ case DSI_THS_EXIT:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
+
+ if(State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
+ hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
+ }
+
+ break;
+ case DSI_TLPX_DATA:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
+
+ if(State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
+ hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
+ }
+
+ break;
+ case DSI_THS_ZERO:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
+
+ if(State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
+ hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
+ }
+
+ break;
+ case DSI_THS_TRAIL:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
+
+ if(State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
+ hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
+ }
+
+ break;
+ case DSI_THS_PREPARE:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
+
+ if(State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
+ hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
+ }
+
+ break;
+ case DSI_TCLK_ZERO:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
+
+ if(State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
+ hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
+ }
+
+ break;
+ case DSI_TCLK_PREPARE:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
+
+ if(State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
+ hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Force the Clock/Data Lane in TX Stop Mode
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param Lane select between clock or data lanes.
+ * This parameter can be any value of @ref DSI_Lane_Group
+ * @param State ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_DSI_LANE_GROUP(Lane));
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ if(Lane == DSI_CLOCK_LANE)
+ {
+ /* Force/Unforce the Clock Lane in TX Stop Mode */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
+ }
+ else if(Lane == DSI_DATA_LANES)
+ {
+ /* Force/Unforce the Data Lanes in TX Stop Mode */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Force LP Receiver in Low-Power Mode
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Force/Unforce LP Receiver in Low-Power Mode */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
+ hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Force Data Lanes in RX Mode after a BTA
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Force Data Lanes in RX Mode */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable a pull-down on the lanes to prevent from floating states when unused
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Enable/Disable pull-down on lanes */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Switch off the contention detection on data lanes
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param State ENABLE or DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ /* Check function parameters */
+ assert_param(IS_FUNCTIONAL_STATE(State));
+
+ /* Contention Detection on Data Lanes OFF */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DSI state.
+ (+) Get error code.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the DSI state
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval HAL state
+ */
+HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
+{
+ return hdsi->State;
+}
+
+/**
+ * @brief Return the DSI error code
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval DSI Error Code
+ */
+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
+{
+ /* Get the error code */
+ return hdsi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DSI */
+
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1288 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dsi.h
+ * @author MCD Application Team
+ * @brief Header file of DSI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DSI_H
+#define __STM32F4xx_HAL_DSI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(DSI)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DSI DSI
+ * @brief DSI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief DSI Init Structure definition
+ */
+typedef struct
+{
+ uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
+ This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
+
+ uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
+ The values 0 and 1 stop the TX_ESC clock generation */
+
+ uint32_t NumberOfLanes; /*!< Number of lanes
+ This parameter can be any value of @ref DSI_Number_Of_Lanes */
+
+}DSI_InitTypeDef;
+
+/**
+ * @brief DSI PLL Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLNDIV; /*!< PLL Loop Division Factor
+ This parameter must be a value between 10 and 125 */
+
+ uint32_t PLLIDF; /*!< PLL Input Division Factor
+ This parameter can be any value of @ref DSI_PLL_IDF */
+
+ uint32_t PLLODF; /*!< PLL Output Division Factor
+ This parameter can be any value of @ref DSI_PLL_ODF */
+
+}DSI_PLLInitTypeDef;
+
+/**
+ * @brief DSI Video mode configuration
+ */
+typedef struct
+{
+ uint32_t VirtualChannelID; /*!< Virtual channel ID */
+
+ uint32_t ColorCoding; /*!< Color coding for LTDC interface
+ This parameter can be any value of @ref DSI_Color_Coding */
+
+ uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
+ 18-bit configuration).
+ This parameter can be any value of @ref DSI_LooselyPacked */
+
+ uint32_t Mode; /*!< Video mode type
+ This parameter can be any value of @ref DSI_Video_Mode_Type */
+
+ uint32_t PacketSize; /*!< Video packet size */
+
+ uint32_t NumberOfChunks; /*!< Number of chunks */
+
+ uint32_t NullPacketSize; /*!< Null packet size */
+
+ uint32_t HSPolarity; /*!< HSYNC pin polarity
+ This parameter can be any value of @ref DSI_HSYNC_Polarity */
+
+ uint32_t VSPolarity; /*!< VSYNC pin polarity
+ This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
+
+ uint32_t DEPolarity; /*!< Data Enable pin polarity
+ This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
+
+ uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
+
+ uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
+
+ uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
+
+ uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
+
+ uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
+
+ uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
+
+ uint32_t VerticalActive; /*!< Vertical active duration */
+
+ uint32_t LPCommandEnable; /*!< Low-power command enable
+ This parameter can be any value of @ref DSI_LP_Command */
+
+ uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
+ can fit in a line during VSA, VBP and VFP regions */
+
+ uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
+ can fit in a line during VACT region */
+
+ uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
+ This parameter can be any value of @ref DSI_LP_HFP */
+
+ uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
+ This parameter can be any value of @ref DSI_LP_HBP */
+
+ uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
+ This parameter can be any value of @ref DSI_LP_VACT */
+
+ uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
+ This parameter can be any value of @ref DSI_LP_VFP */
+
+ uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
+ This parameter can be any value of @ref DSI_LP_VBP */
+
+ uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
+ This parameter can be any value of @ref DSI_LP_VSYNC */
+
+ uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
+ This parameter can be any value of @ref DSI_FBTA_acknowledge */
+
+}DSI_VidCfgTypeDef;
+
+/**
+ * @brief DSI Adapted command mode configuration
+ */
+typedef struct
+{
+ uint32_t VirtualChannelID; /*!< Virtual channel ID */
+
+ uint32_t ColorCoding; /*!< Color coding for LTDC interface
+ This parameter can be any value of @ref DSI_Color_Coding */
+
+ uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
+ pixels. This parameter can be any value between 0x00 and 0xFFFFU */
+
+ uint32_t TearingEffectSource; /*!< Tearing effect source
+ This parameter can be any value of @ref DSI_TearingEffectSource */
+
+ uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
+ This parameter can be any value of @ref DSI_TearingEffectPolarity */
+
+ uint32_t HSPolarity; /*!< HSYNC pin polarity
+ This parameter can be any value of @ref DSI_HSYNC_Polarity */
+
+ uint32_t VSPolarity; /*!< VSYNC pin polarity
+ This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
+
+ uint32_t DEPolarity; /*!< Data Enable pin polarity
+ This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
+
+ uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
+ This parameter can be any value of @ref DSI_Vsync_Polarity */
+
+ uint32_t AutomaticRefresh; /*!< Automatic refresh mode
+ This parameter can be any value of @ref DSI_AutomaticRefresh */
+
+ uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
+ This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
+
+}DSI_CmdCfgTypeDef;
+
+/**
+ * @brief DSI command transmission mode configuration
+ */
+typedef struct
+{
+ uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
+
+ uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
+
+ uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
+
+ uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
+
+ uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
+
+ uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
+
+ uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
+
+ uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
+
+ uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
+
+ uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
+
+ uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
+
+ uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
+ This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
+
+ uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
+ This parameter can be any value of @ref DSI_AcknowledgeRequest */
+
+}DSI_LPCmdTypeDef;
+
+/**
+ * @brief DSI PHY Timings definition
+ */
+typedef struct
+{
+ uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
+ to low-power transmission */
+
+ uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
+ to high-speed transmission */
+
+ uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
+ to low-power transmission */
+
+ uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
+ to high-speed transmission */
+
+ uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
+
+ uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
+ Stop state */
+
+}DSI_PHY_TimerTypeDef;
+
+/**
+ * @brief DSI HOST Timeouts definition
+ */
+typedef struct
+{
+ uint32_t TimeoutCkdiv; /*!< Time-out clock division */
+
+ uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */
+
+ uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */
+
+ uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */
+
+ uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */
+
+ uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */
+
+ uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
+ This parameter can be any value of @ref DSI_HS_PrespMode */
+
+ uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */
+
+ uint32_t BTATimeout; /*!< BTA time-out */
+
+}DSI_HOST_TimeoutTypeDef;
+
+/**
+ * @brief DSI States Structure definition
+ */
+typedef enum
+{
+ HAL_DSI_STATE_RESET = 0x00U,
+ HAL_DSI_STATE_READY = 0x01U,
+ HAL_DSI_STATE_ERROR = 0x02U,
+ HAL_DSI_STATE_BUSY = 0x03U,
+ HAL_DSI_STATE_TIMEOUT = 0x04U
+}HAL_DSI_StateTypeDef;
+
+/**
+ * @brief DSI Handle Structure definition
+ */
+typedef struct
+{
+ DSI_TypeDef *Instance; /*!< Register base address */
+ DSI_InitTypeDef Init; /*!< DSI required parameters */
+ HAL_LockTypeDef Lock; /*!< DSI peripheral status */
+ __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
+ __IO uint32_t ErrorCode; /*!< DSI Error code */
+ uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
+}DSI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DSI_DCS_Command DSI DCS Command
+ * @{
+ */
+#define DSI_ENTER_IDLE_MODE 0x39U
+#define DSI_ENTER_INVERT_MODE 0x21U
+#define DSI_ENTER_NORMAL_MODE 0x13U
+#define DSI_ENTER_PARTIAL_MODE 0x12U
+#define DSI_ENTER_SLEEP_MODE 0x10U
+#define DSI_EXIT_IDLE_MODE 0x38U
+#define DSI_EXIT_INVERT_MODE 0x20U
+#define DSI_EXIT_SLEEP_MODE 0x11U
+#define DSI_GET_3D_CONTROL 0x3FU
+#define DSI_GET_ADDRESS_MODE 0x0BU
+#define DSI_GET_BLUE_CHANNEL 0x08U
+#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
+#define DSI_GET_DISPLAY_MODE 0x0DU
+#define DSI_GET_GREEN_CHANNEL 0x07U
+#define DSI_GET_PIXEL_FORMAT 0x0CU
+#define DSI_GET_POWER_MODE 0x0AU
+#define DSI_GET_RED_CHANNEL 0x06U
+#define DSI_GET_SCANLINE 0x45U
+#define DSI_GET_SIGNAL_MODE 0x0EU
+#define DSI_NOP 0x00U
+#define DSI_READ_DDB_CONTINUE 0xA8U
+#define DSI_READ_DDB_START 0xA1U
+#define DSI_READ_MEMORY_CONTINUE 0x3EU
+#define DSI_READ_MEMORY_START 0x2EU
+#define DSI_SET_3D_CONTROL 0x3DU
+#define DSI_SET_ADDRESS_MODE 0x36U
+#define DSI_SET_COLUMN_ADDRESS 0x2AU
+#define DSI_SET_DISPLAY_OFF 0x28U
+#define DSI_SET_DISPLAY_ON 0x29U
+#define DSI_SET_GAMMA_CURVE 0x26U
+#define DSI_SET_PAGE_ADDRESS 0x2BU
+#define DSI_SET_PARTIAL_COLUMNS 0x31U
+#define DSI_SET_PARTIAL_ROWS 0x30U
+#define DSI_SET_PIXEL_FORMAT 0x3AU
+#define DSI_SET_SCROLL_AREA 0x33U
+#define DSI_SET_SCROLL_START 0x37U
+#define DSI_SET_TEAR_OFF 0x34U
+#define DSI_SET_TEAR_ON 0x35U
+#define DSI_SET_TEAR_SCANLINE 0x44U
+#define DSI_SET_VSYNC_TIMING 0x40U
+#define DSI_SOFT_RESET 0x01U
+#define DSI_WRITE_LUT 0x2DU
+#define DSI_WRITE_MEMORY_CONTINUE 0x3CU
+#define DSI_WRITE_MEMORY_START 0x2CU
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
+ * @{
+ */
+#define DSI_VID_MODE_NB_PULSES 0U
+#define DSI_VID_MODE_NB_EVENTS 1U
+#define DSI_VID_MODE_BURST 2U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Color_Mode DSI Color Mode
+ * @{
+ */
+#define DSI_COLOR_MODE_FULL 0x00000000U
+#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
+/**
+ * @}
+ */
+
+/** @defgroup DSI_ShutDown DSI ShutDown
+ * @{
+ */
+#define DSI_DISPLAY_ON 0x00000000U
+#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_Command DSI LP Command
+ * @{
+ */
+#define DSI_LP_COMMAND_DISABLE 0x00000000U
+#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_HFP DSI LP HFP
+ * @{
+ */
+#define DSI_LP_HFP_DISABLE 0x00000000U
+#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_HBP DSI LP HBP
+ * @{
+ */
+#define DSI_LP_HBP_DISABLE 0x00000000U
+#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_VACT DSI LP VACT
+ * @{
+ */
+#define DSI_LP_VACT_DISABLE 0x00000000U
+#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_VFP DSI LP VFP
+ * @{
+ */
+#define DSI_LP_VFP_DISABLE 0x00000000U
+#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_VBP DSI LP VBP
+ * @{
+ */
+#define DSI_LP_VBP_DISABLE 0x00000000U
+#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_VSYNC DSI LP VSYNC
+ * @{
+ */
+#define DSI_LP_VSYNC_DISABLE 0x00000000U
+#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
+ * @{
+ */
+#define DSI_FBTAA_DISABLE 0x00000000U
+#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
+ * @{
+ */
+#define DSI_TE_DSILINK 0x00000000U
+#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
+/**
+ * @}
+ */
+
+/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
+ * @{
+ */
+#define DSI_TE_RISING_EDGE 0x00000000U
+#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
+ * @{
+ */
+#define DSI_VSYNC_FALLING 0x00000000U
+#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
+/**
+ * @}
+ */
+
+/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
+ * @{
+ */
+#define DSI_AR_DISABLE 0x00000000U
+#define DSI_AR_ENABLE DSI_WCFGR_AR
+/**
+ * @}
+ */
+
+/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
+ * @{
+ */
+#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
+#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
+ * @{
+ */
+#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
+#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
+ * @{
+ */
+#define DSI_LP_GSW0P_DISABLE 0x00000000U
+#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
+ * @{
+ */
+#define DSI_LP_GSW1P_DISABLE 0x00000000U
+#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
+ * @{
+ */
+#define DSI_LP_GSW2P_DISABLE 0x00000000U
+#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
+ * @{
+ */
+#define DSI_LP_GSR0P_DISABLE 0x00000000U
+#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
+ * @{
+ */
+#define DSI_LP_GSR1P_DISABLE 0x00000000U
+#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
+ * @{
+ */
+#define DSI_LP_GSR2P_DISABLE 0x00000000U
+#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
+ * @{
+ */
+#define DSI_LP_GLW_DISABLE 0x00000000U
+#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
+ * @{
+ */
+#define DSI_LP_DSW0P_DISABLE 0x00000000U
+#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
+ * @{
+ */
+#define DSI_LP_DSW1P_DISABLE 0x00000000U
+#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
+ * @{
+ */
+#define DSI_LP_DSR0P_DISABLE 0x00000000U
+#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
+ * @{
+ */
+#define DSI_LP_DLW_DISABLE 0x00000000U
+#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
+ * @{
+ */
+#define DSI_LP_MRDP_DISABLE 0x00000000U
+#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
+/**
+ * @}
+ */
+
+/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
+ * @{
+ */
+#define DSI_HS_PM_DISABLE 0x00000000U
+#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
+/**
+ * @}
+ */
+
+
+/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
+ * @{
+ */
+#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
+#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
+ * @{
+ */
+#define DSI_ONE_DATA_LANE 0U
+#define DSI_TWO_DATA_LANES 1U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_FlowControl DSI Flow Control
+ * @{
+ */
+#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
+#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
+#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
+#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
+#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
+#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
+ DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
+ DSI_FLOW_CONTROL_EOTP_TX)
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Color_Coding DSI Color Coding
+ * @{
+ */
+#define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
+#define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
+#define DSI_RGB888 0x00000005U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LooselyPacked DSI Loosely Packed
+ * @{
+ */
+#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
+#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
+ * @{
+ */
+#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
+#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
+/**
+ * @}
+ */
+
+/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
+ * @{
+ */
+#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
+#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
+/**
+ * @}
+ */
+
+/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
+ * @{
+ */
+#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
+#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
+/**
+ * @}
+ */
+
+/** @defgroup DSI_PLL_IDF DSI PLL IDF
+ * @{
+ */
+#define DSI_PLL_IN_DIV1 0x00000001U
+#define DSI_PLL_IN_DIV2 0x00000002U
+#define DSI_PLL_IN_DIV3 0x00000003U
+#define DSI_PLL_IN_DIV4 0x00000004U
+#define DSI_PLL_IN_DIV5 0x00000005U
+#define DSI_PLL_IN_DIV6 0x00000006U
+#define DSI_PLL_IN_DIV7 0x00000007U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_PLL_ODF DSI PLL ODF
+ * @{
+ */
+#define DSI_PLL_OUT_DIV1 0x00000000U
+#define DSI_PLL_OUT_DIV2 0x00000001U
+#define DSI_PLL_OUT_DIV4 0x00000002U
+#define DSI_PLL_OUT_DIV8 0x00000003U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Flags DSI Flags
+ * @{
+ */
+#define DSI_FLAG_TE DSI_WISR_TEIF
+#define DSI_FLAG_ER DSI_WISR_ERIF
+#define DSI_FLAG_BUSY DSI_WISR_BUSY
+#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
+#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
+#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
+#define DSI_FLAG_RRS DSI_WISR_RRS
+#define DSI_FLAG_RR DSI_WISR_RRIF
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Interrupts DSI Interrupts
+ * @{
+ */
+#define DSI_IT_TE DSI_WIER_TEIE
+#define DSI_IT_ER DSI_WIER_ERIE
+#define DSI_IT_PLLL DSI_WIER_PLLLIE
+#define DSI_IT_PLLU DSI_WIER_PLLUIE
+#define DSI_IT_RR DSI_WIER_RRIE
+/**
+ * @}
+ */
+
+/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
+ * @{
+ */
+#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */
+#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */
+#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */
+#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */
+#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */
+/**
+ * @}
+ */
+
+/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
+ * @{
+ */
+#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */
+#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */
+/**
+ * @}
+ */
+
+/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
+ * @{
+ */
+#define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */
+#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */
+#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */
+#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Error_Data_Type DSI Error Data Type
+ * @{
+ */
+#define HAL_DSI_ERROR_NONE 0U
+#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
+#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
+#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
+#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
+#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
+#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
+#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
+#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
+#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
+#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Lane_Group DSI Lane Group
+ * @{
+ */
+#define DSI_CLOCK_LANE 0x00000000U
+#define DSI_DATA_LANES 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Communication_Delay DSI Communication Delay
+ * @{
+ */
+#define DSI_SLEW_RATE_HSTX 0x00000000U
+#define DSI_SLEW_RATE_LPTX 0x00000001U
+#define DSI_HS_DELAY 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_CustomLane DSI CustomLane
+ * @{
+ */
+#define DSI_SWAP_LANE_PINS 0x00000000U
+#define DSI_INVERT_HS_SIGNAL 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Lane_Select DSI Lane Select
+ * @{
+ */
+#define DSI_CLK_LANE 0x00000000U
+#define DSI_DATA_LANE0 0x00000001U
+#define DSI_DATA_LANE1 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup DSI_PHY_Timing DSI PHY Timing
+ * @{
+ */
+#define DSI_TCLK_POST 0x00000000U
+#define DSI_TLPX_CLK 0x00000001U
+#define DSI_THS_EXIT 0x00000002U
+#define DSI_TLPX_DATA 0x00000003U
+#define DSI_THS_ZERO 0x00000004U
+#define DSI_THS_TRAIL 0x00000005U
+#define DSI_THS_PREPARE 0x00000006U
+#define DSI_TCLK_ZERO 0x00000007U
+#define DSI_TCLK_PREPARE 0x00000008U
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/**
+ * @brief Enables the DSI host.
+ * @param __HANDLE__ DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ /* Delay after an DSI Host enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ UNUSED(tmpreg); \
+ }while(0U)
+
+/**
+ * @brief Disables the DSI host.
+ * @param __HANDLE__ DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ /* Delay after an DSI Host disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ UNUSED(tmpreg); \
+ }while(0U)
+
+/**
+ * @brief Enables the DSI wrapper.
+ * @param __HANDLE__ DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
+
+/**
+ * @brief Disable the DSI wrapper.
+ * @param __HANDLE__ DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper disabling*/ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
+
+/**
+ * @brief Enables the DSI PLL.
+ * @param __HANDLE__ DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
+
+/**
+ * @brief Disables the DSI PLL.
+ * @param __HANDLE__ DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
+
+/**
+ * @brief Enables the DSI regulator.
+ * @param __HANDLE__ DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ /* Delay after an DSI regulator enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
+
+/**
+ * @brief Disables the DSI regulator.
+ * @param __HANDLE__ DSI handle
+ * @retval None.
+ */
+#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ /* Delay after an DSI regulator disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
+
+/**
+ * @brief Get the DSI pending flags.
+ * @param __HANDLE__ DSI handle.
+ * @param __FLAG__ Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
+ * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
+ * @arg DSI_FLAG_BUSY : Busy Flag
+ * @arg DSI_FLAG_PLLLS: PLL Lock Status
+ * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
+ * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
+ * @arg DSI_FLAG_RRS : Regulator Ready Flag
+ * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
+
+/**
+ * @brief Clears the DSI pending flags.
+ * @param __HANDLE__ DSI handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
+ * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
+ * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
+ * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
+ * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
+ * @retval None
+ */
+#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
+
+/**
+ * @brief Enables the specified DSI interrupts.
+ * @param __HANDLE__ DSI handle.
+ * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DSI_IT_TE : Tearing Effect Interrupt
+ * @arg DSI_IT_ER : End of Refresh Interrupt
+ * @arg DSI_IT_PLLL: PLL Lock Interrupt
+ * @arg DSI_IT_PLLU: PLL Unlock Interrupt
+ * @arg DSI_IT_RR : Regulator Ready Interrupt
+ * @retval None
+ */
+#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified DSI interrupts.
+ * @param __HANDLE__ DSI handle
+ * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DSI_IT_TE : Tearing Effect Interrupt
+ * @arg DSI_IT_ER : End of Refresh Interrupt
+ * @arg DSI_IT_PLLL: PLL Lock Interrupt
+ * @arg DSI_IT_PLLU: PLL Unlock Interrupt
+ * @arg DSI_IT_RR : Regulator Ready Interrupt
+ * @retval None
+ */
+#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified DSI interrupt source is enabled or not.
+ * @param __HANDLE__ DSI handle
+ * @param __INTERRUPT__ specifies the DSI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DSI_IT_TE : Tearing Effect Interrupt
+ * @arg DSI_IT_ER : End of Refresh Interrupt
+ * @arg DSI_IT_PLLL: PLL Lock Interrupt
+ * @arg DSI_IT_PLLU: PLL Unlock Interrupt
+ * @arg DSI_IT_RR : Regulator Ready Interrupt
+ * @retval The state of INTERRUPT (SET or RESET).
+ */
+#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DSI_Exported_Functions DSI Exported Functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
+HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
+
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
+
+HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
+HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
+HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
+HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
+HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
+HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
+HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
+HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
+HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
+HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2);
+HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t NbParams,
+ uint32_t Param1,
+ uint8_t* ParametersTable);
+HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelNbr,
+ uint8_t* Array,
+ uint32_t Size,
+ uint32_t Mode,
+ uint32_t DCSCmd,
+ uint8_t* ParametersTable);
+HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
+
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
+
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
+HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
+
+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
+HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup DSI_Private_Types DSI Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup DSI_Private_Defines DSI Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Variables DSI Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Constants DSI Private Constants
+ * @{
+ */
+#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DSI_Private_Macros DSI Private Macros
+ * @{
+ */
+#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
+#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
+ ((IDF) == DSI_PLL_IN_DIV2) || \
+ ((IDF) == DSI_PLL_IN_DIV3) || \
+ ((IDF) == DSI_PLL_IN_DIV4) || \
+ ((IDF) == DSI_PLL_IN_DIV5) || \
+ ((IDF) == DSI_PLL_IN_DIV6) || \
+ ((IDF) == DSI_PLL_IN_DIV7))
+#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
+ ((ODF) == DSI_PLL_OUT_DIV2) || \
+ ((ODF) == DSI_PLL_OUT_DIV4) || \
+ ((ODF) == DSI_PLL_OUT_DIV8))
+#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
+#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
+#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
+#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
+#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
+#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
+#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
+#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
+#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
+ ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
+ ((VideoModeType) == DSI_VID_MODE_BURST))
+#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
+#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
+#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
+#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
+#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
+#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
+#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
+#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
+#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
+#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
+#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
+#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
+#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
+#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
+#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
+#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
+#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
+#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
+#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
+#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
+#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
+#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
+#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
+#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
+#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
+#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
+#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
+ ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
+#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
+ ((MODE) == DSI_GEN_LONG_PKT_WRITE))
+#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
+ ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
+#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
+#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
+#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
+#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
+#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
+ ((Timing) == DSI_TLPX_CLK ) || \
+ ((Timing) == DSI_THS_EXIT ) || \
+ ((Timing) == DSI_TLPX_DATA ) || \
+ ((Timing) == DSI_THS_ZERO ) || \
+ ((Timing) == DSI_THS_TRAIL ) || \
+ ((Timing) == DSI_THS_PREPARE ) || \
+ ((Timing) == DSI_TCLK_ZERO ) || \
+ ((Timing) == DSI_TCLK_PREPARE))
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Functions DSI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* DSI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DSI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2032 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_eth.c
+ * @author MCD Application Team
+ * @brief ETH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Ethernet (ETH) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#)Declare a ETH_HandleTypeDef handle structure, for example:
+ ETH_HandleTypeDef heth;
+
+ (#)Fill parameters of Init structure in heth handle
+
+ (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
+
+ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
+ (##) Enable the Ethernet interface clock using
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure Ethernet pin-out
+ (##) Configure Ethernet NVIC interrupt (IT mode)
+
+ (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
+ (##) HAL_ETH_DMATxDescListInit(); for Transmission process
+ (##) HAL_ETH_DMARxDescListInit(); for Reception process
+
+ (#)Enable MAC and DMA transmission and reception:
+ (##) HAL_ETH_Start();
+
+ (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
+ the frame to MAC TX FIFO:
+ (##) HAL_ETH_TransmitFrame();
+
+ (#)Poll for a received frame in ETH RX DMA Descriptors and get received
+ frame parameters
+ (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
+
+ (#) Get a received frame when an ETH RX interrupt occurs:
+ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
+
+ (#) Communicate with external PHY device:
+ (##) Read a specific register from the PHY
+ HAL_ETH_ReadPHYRegister();
+ (##) Write data to a specific RHY register:
+ HAL_ETH_WritePHYRegister();
+
+ (#) Configure the Ethernet MAC after ETH peripheral initialization
+ HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
+
+ (#) Configure the Ethernet DMA after ETH peripheral initialization
+ HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
+
+ -@- The PTP protocol and the DMA descriptors ring mode are not supported
+ in this driver
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ETH ETH
+ * @brief ETH HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ETH_Private_Constants ETH Private Constants
+ * @{
+ */
+#define ETH_TIMEOUT_SWRESET 500U
+#define ETH_TIMEOUT_LINKED_STATE 5000U
+#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
+
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ETH_Private_Functions ETH Private Functions
+ * @{
+ */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
+static void ETH_Delay(uint32_t mdelay);
+
+/**
+ * @}
+ */
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ETH_Exported_Functions ETH Exported Functions
+ * @{
+ */
+
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the Ethernet peripheral
+ (+) De-initialize the Ethernet peripheral
+
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the Ethernet MAC and DMA according to default
+ * parameters.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
+{
+ uint32_t tmpreg1 = 0U, phyreg = 0U;
+ uint32_t hclk = 60000000U;
+ uint32_t tickstart = 0U;
+ uint32_t err = ETH_SUCCESS;
+
+ /* Check the ETH peripheral state */
+ if(heth == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
+ assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
+ assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
+ assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
+
+ if(heth->State == HAL_ETH_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ heth->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+ HAL_ETH_MspInit(heth);
+ }
+
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Select MII or RMII Mode*/
+ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
+ SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
+
+ /* Ethernet Software reset */
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+ /* After reset all the registers holds their respective reset values */
+ (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for software reset */
+ while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
+ {
+ heth->State= HAL_ETH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
+ not available, please check your external PHY or the IO configuration */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*-------------------------------- MAC Initialization ----------------------*/
+ /* Get the ETHERNET MACMIIAR value */
+ tmpreg1 = (heth->Instance)->MACMIIAR;
+ /* Clear CSR Clock Range CR[2:0] bits */
+ tmpreg1 &= ETH_MACMIIAR_CR_MASK;
+
+ /* Get hclk frequency value */
+ hclk = HAL_RCC_GetHCLKFreq();
+
+ /* Set CR bits depending on hclk value */
+ if((hclk >= 20000000U)&&(hclk < 35000000U))
+ {
+ /* CSR Clock Range between 20-35 MHz */
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
+ }
+ else if((hclk >= 35000000U)&&(hclk < 60000000U))
+ {
+ /* CSR Clock Range between 35-60 MHz */
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
+ }
+ else if((hclk >= 60000000U)&&(hclk < 100000000U))
+ {
+ /* CSR Clock Range between 60-100 MHz */
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
+ }
+ else if((hclk >= 100000000U)&&(hclk < 150000000U))
+ {
+ /* CSR Clock Range between 100-150 MHz */
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
+ }
+ else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */
+ {
+ /* CSR Clock Range between 150-183 MHz */
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
+ }
+
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
+ (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
+
+ /*-------------------- PHY initialization and configuration ----------------*/
+ /* Put the PHY in reset mode */
+ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set the ETH peripheral state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return HAL_ERROR */
+ return HAL_ERROR;
+ }
+
+ /* Delay to assure PHY reset */
+ HAL_Delay(PHY_RESET_DELAY);
+
+ if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* We wait for linked status */
+ do
+ {
+ HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
+
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+ } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
+
+
+ /* Enable Auto-Negotiation */
+ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set the ETH peripheral state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return HAL_ERROR */
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the auto-negotiation will be completed */
+ do
+ {
+ HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
+
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+
+ } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
+
+ /* Read the result of the auto-negotiation */
+ if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set the ETH peripheral state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return HAL_ERROR */
+ return HAL_ERROR;
+ }
+
+ /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
+ if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
+ {
+ /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
+ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
+ }
+ else
+ {
+ /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
+ (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
+ }
+ /* Configure the MAC with the speed fixed by the auto-negotiation process */
+ if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
+ {
+ /* Set Ethernet speed to 10M following the auto-negotiation */
+ (heth->Init).Speed = ETH_SPEED_10M;
+ }
+ else
+ {
+ /* Set Ethernet speed to 100M following the auto-negotiation */
+ (heth->Init).Speed = ETH_SPEED_100M;
+ }
+ }
+ else /* AutoNegotiation Disable */
+ {
+ /* Check parameters */
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
+
+ /* Set MAC Speed and Duplex Mode */
+ if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
+ (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set the ETH peripheral state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return HAL_ERROR */
+ return HAL_ERROR;
+ }
+
+ /* Delay to assure PHY configuration */
+ HAL_Delay(PHY_CONFIG_DELAY);
+ }
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set ETH HAL State to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initializes the ETH peripheral.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
+{
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
+ HAL_ETH_MspDeInit(heth);
+
+ /* Set ETH HAL state to Disabled */
+ heth->State= HAL_ETH_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DMA Tx descriptors in chain mode.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param DMATxDescTab Pointer to the first Tx desc list
+ * @param TxBuff Pointer to the first TxBuffer list
+ * @param TxBuffCount Number of the used Tx desc in the list
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
+{
+ uint32_t i = 0U;
+ ETH_DMADescTypeDef *dmatxdesc;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+ heth->TxDesc = DMATxDescTab;
+
+ /* Fill each DMATxDesc descriptor with the right values */
+ for(i=0U; i < TxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Tx Desc list */
+ dmatxdesc = DMATxDescTab + i;
+
+ /* Set Second Address Chained bit */
+ dmatxdesc->Status = ETH_DMATXDESC_TCH;
+
+ /* Set Buffer1 address pointer */
+ dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
+
+ if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
+ {
+ /* Set the DMA Tx descriptors checksum insertion */
+ dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
+ }
+
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+ if(i < (TxBuffCount-1U))
+ {
+ /* Set next descriptor address register with next descriptor base address */
+ dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
+ }
+ else
+ {
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+ dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
+ }
+ }
+
+ /* Set Transmit Descriptor List Address Register */
+ (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
+
+ /* Set ETH HAL State to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DMA Rx descriptors in chain mode.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param DMARxDescTab Pointer to the first Rx desc list
+ * @param RxBuff Pointer to the first RxBuffer list
+ * @param RxBuffCount Number of the used Rx desc in the list
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+ uint32_t i = 0U;
+ ETH_DMADescTypeDef *DMARxDesc;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
+ heth->RxDesc = DMARxDescTab;
+
+ /* Fill each DMARxDesc descriptor with the right values */
+ for(i=0U; i < RxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Rx Desc list */
+ DMARxDesc = DMARxDescTab+i;
+
+ /* Set Own bit of the Rx descriptor Status */
+ DMARxDesc->Status = ETH_DMARXDESC_OWN;
+
+ /* Set Buffer1 size and Second Address Chained bit */
+ DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
+
+ /* Set Buffer1 address pointer */
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
+
+ if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
+ {
+ /* Enable Ethernet DMA Rx Descriptor interrupt */
+ DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
+ }
+
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+ if(i < (RxBuffCount-1U))
+ {
+ /* Set next descriptor address register with next descriptor base address */
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
+ }
+ else
+ {
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+ }
+ }
+
+ /* Set Receive Descriptor List Address Register */
+ (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
+
+ /* Set ETH HAL State to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the ETH MSP.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes ETH MSP.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a frame
+ HAL_ETH_TransmitFrame();
+ (+) Receive a frame
+ HAL_ETH_GetReceivedFrame();
+ HAL_ETH_GetReceivedFrame_IT();
+ (+) Read from an External PHY register
+ HAL_ETH_ReadPHYRegister();
+ (+) Write to an External PHY register
+ HAL_ETH_WritePHYRegister();
+
+ @endverbatim
+
+ * @{
+ */
+
+/**
+ * @brief Sends an Ethernet frame.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param FrameLength Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
+{
+ uint32_t bufcount = 0U, size = 0U, i = 0U;
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ if (FrameLength == 0U)
+ {
+ /* Set ETH HAL state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ return HAL_ERROR;
+ }
+
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+ if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
+ {
+ /* OWN bit set */
+ heth->State = HAL_ETH_STATE_BUSY_TX;
+
+ return HAL_ERROR;
+ }
+
+ /* Get the number of needed Tx buffers for the current frame */
+ if (FrameLength > ETH_TX_BUF_SIZE)
+ {
+ bufcount = FrameLength/ETH_TX_BUF_SIZE;
+ if (FrameLength % ETH_TX_BUF_SIZE)
+ {
+ bufcount++;
+ }
+ }
+ else
+ {
+ bufcount = 1U;
+ }
+ if (bufcount == 1U)
+ {
+ /* Set LAST and FIRST segment */
+ heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
+ /* Set frame size */
+ heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
+ /* Point to next descriptor */
+ heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
+ }
+ else
+ {
+ for (i=0U; i< bufcount; i++)
+ {
+ /* Clear FIRST and LAST segment bits */
+ heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
+
+ if (i == 0U)
+ {
+ /* Setting the first segment bit */
+ heth->TxDesc->Status |= ETH_DMATXDESC_FS;
+ }
+
+ /* Program size */
+ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
+
+ if (i == (bufcount-1U))
+ {
+ /* Setting the last segment bit */
+ heth->TxDesc->Status |= ETH_DMATXDESC_LS;
+ size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
+ heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
+ }
+
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
+ /* point to next descriptor */
+ heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
+ }
+ }
+
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+ if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+ {
+ /* Clear TBUS ETHERNET DMA flag */
+ (heth->Instance)->DMASR = ETH_DMASR_TBUS;
+ /* Resume DMA transmission*/
+ (heth->Instance)->DMATPDR = 0U;
+ }
+
+ /* Set ETH HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Checks for received frames.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
+{
+ uint32_t framelength = 0U;
+
+ /* Check the ETH state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Check if segment is not owned by DMA */
+ /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
+ if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
+ {
+ /* Check if last segment */
+ if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
+ {
+ /* increment segment count */
+ (heth->RxFrameInfos).SegCount++;
+
+ /* Check if last segment is first segment: one segment contains the frame */
+ if ((heth->RxFrameInfos).SegCount == 1U)
+ {
+ (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
+ }
+
+ heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
+
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+ framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
+ heth->RxFrameInfos.length = framelength;
+
+ /* Get the address of the buffer start address */
+ heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
+ /* point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ /* Check if first segment */
+ else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
+ {
+ (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
+ (heth->RxFrameInfos).LSRxDesc = NULL;
+ (heth->RxFrameInfos).SegCount = 1U;
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+ }
+ /* Check if intermediate segment */
+ else
+ {
+ (heth->RxFrameInfos).SegCount++;
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+ }
+ }
+
+ /* Set ETH HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Gets the Received frame in interrupt mode.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
+{
+ uint32_t descriptorscancounter = 0U;
+
+ /* Set ETH HAL State to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Scan descriptors owned by CPU */
+ while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
+ {
+ /* Just for security */
+ descriptorscancounter++;
+
+ /* Check if first segment in frame */
+ /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
+ if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
+ {
+ heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
+ heth->RxFrameInfos.SegCount = 1U;
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+ }
+ /* Check if intermediate segment */
+ /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
+ else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
+ {
+ /* Increment segment count */
+ (heth->RxFrameInfos.SegCount)++;
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
+ }
+ /* Should be last segment */
+ else
+ {
+ /* Last segment */
+ heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
+
+ /* Increment segment count */
+ (heth->RxFrameInfos.SegCount)++;
+
+ /* Check if last segment is first segment: one segment contains the frame */
+ if ((heth->RxFrameInfos.SegCount) == 1U)
+ {
+ heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
+ }
+
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+ heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
+
+ /* Get the address of the buffer start address */
+ heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
+
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ }
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief This function handles ETH interrupt request.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
+{
+ /* Frame received */
+ if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
+ {
+ /* Receive complete callback */
+ HAL_ETH_RxCpltCallback(heth);
+
+ /* Clear the Eth DMA Rx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ }
+ /* Frame transmitted */
+ else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
+ {
+ /* Transfer complete callback */
+ HAL_ETH_TxCpltCallback(heth);
+
+ /* Clear the Eth DMA Tx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+ }
+
+ /* Clear the interrupt flags */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
+
+ /* ETH DMA Error */
+ if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
+ {
+ /* Ethernet Error callback */
+ HAL_ETH_ErrorCallback(heth);
+
+ /* Clear the interrupt flags */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Ethernet transfer error callbacks
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Reads a PHY register
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
+ * This parameter can be one of the following values:
+ * PHY_BCR: Transceiver Basic Control Register,
+ * PHY_BSR: Transceiver Basic Status Register.
+ * More PHY register could be read depending on the used PHY
+ * @param RegValue PHY register value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
+{
+ uint32_t tmpreg1 = 0U;
+ uint32_t tickstart = 0U;
+
+ /* Check parameters */
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
+
+ /* Check the ETH peripheral state */
+ if(heth->State == HAL_ETH_STATE_BUSY_RD)
+ {
+ return HAL_BUSY;
+ }
+ /* Set ETH HAL State to BUSY_RD */
+ heth->State = HAL_ETH_STATE_BUSY_RD;
+
+ /* Get the ETHERNET MACMIIAR value */
+ tmpreg1 = heth->Instance->MACMIIAR;
+
+ /* Keep only the CSR Clock Range CR[2:0] bits value */
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
+
+ /* Prepare the MII address register value */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+
+ /* Write the result value into the MII Address register */
+ heth->Instance->MACMIIAR = tmpreg1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check for the Busy flag */
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
+ {
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+
+ tmpreg1 = heth->Instance->MACMIIAR;
+ }
+
+ /* Get MACMIIDR value */
+ *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
+
+ /* Set ETH HAL State to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes to a PHY register.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
+ * This parameter can be one of the following values:
+ * PHY_BCR: Transceiver Control Register.
+ * More PHY register could be written depending on the used PHY
+ * @param RegValue the value to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
+{
+ uint32_t tmpreg1 = 0U;
+ uint32_t tickstart = 0U;
+
+ /* Check parameters */
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
+
+ /* Check the ETH peripheral state */
+ if(heth->State == HAL_ETH_STATE_BUSY_WR)
+ {
+ return HAL_BUSY;
+ }
+ /* Set ETH HAL State to BUSY_WR */
+ heth->State = HAL_ETH_STATE_BUSY_WR;
+
+ /* Get the ETHERNET MACMIIAR value */
+ tmpreg1 = heth->Instance->MACMIIAR;
+
+ /* Keep only the CSR Clock Range CR[2:0] bits value */
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
+
+ /* Prepare the MII register address value */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+
+ /* Give the value to the MII data register */
+ heth->Instance->MACMIIDR = (uint16_t)RegValue;
+
+ /* Write the result value into the MII Address register */
+ heth->Instance->MACMIIAR = tmpreg1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check for the Busy flag */
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
+ {
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+
+ tmpreg1 = heth->Instance->MACMIIAR;
+ }
+
+ /* Set ETH HAL State to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Enable MAC and DMA transmission and reception.
+ HAL_ETH_Start();
+ (+) Disable MAC and DMA transmission and reception.
+ HAL_ETH_Stop();
+ (+) Set the MAC configuration in runtime mode
+ HAL_ETH_ConfigMAC();
+ (+) Set the DMA configuration in runtime mode
+ HAL_ETH_ConfigDMA();
+
+@endverbatim
+ * @{
+ */
+
+ /**
+ * @brief Enables Ethernet MAC and DMA reception/transmission
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
+{
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Enable transmit state machine of the MAC for transmission on the MII */
+ ETH_MACTransmissionEnable(heth);
+
+ /* Enable receive state machine of the MAC for reception from the MII */
+ ETH_MACReceptionEnable(heth);
+
+ /* Flush Transmit FIFO */
+ ETH_FlushTransmitFIFO(heth);
+
+ /* Start DMA transmission */
+ ETH_DMATransmissionEnable(heth);
+
+ /* Start DMA reception */
+ ETH_DMAReceptionEnable(heth);
+
+ /* Set the ETH state to READY*/
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop Ethernet MAC and DMA reception/transmission
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
+{
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Stop DMA transmission */
+ ETH_DMATransmissionDisable(heth);
+
+ /* Stop DMA reception */
+ ETH_DMAReceptionDisable(heth);
+
+ /* Disable receive state machine of the MAC for reception from the MII */
+ ETH_MACReceptionDisable(heth);
+
+ /* Flush Transmit FIFO */
+ ETH_FlushTransmitFIFO(heth);
+
+ /* Disable transmit state machine of the MAC for transmission on the MII */
+ ETH_MACTransmissionDisable(heth);
+
+ /* Set the ETH state*/
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set ETH MAC Configuration.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param macconf MAC Configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
+{
+ uint32_t tmpreg1 = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State= HAL_ETH_STATE_BUSY;
+
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
+
+ if (macconf != NULL)
+ {
+ /* Check the parameters */
+ assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
+ assert_param(IS_ETH_JABBER(macconf->Jabber));
+ assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
+ assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
+ assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
+ assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
+ assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
+ assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
+ assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
+ assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
+ assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
+ assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
+
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/
+ /* Get the ETHERNET MACCR value */
+ tmpreg1 = (heth->Instance)->MACCR;
+ /* Clear WD, PCE, PS, TE and RE bits */
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
+
+ tmpreg1 |= (uint32_t)(macconf->Watchdog |
+ macconf->Jabber |
+ macconf->InterFrameGap |
+ macconf->CarrierSense |
+ (heth->Init).Speed |
+ macconf->ReceiveOwn |
+ macconf->LoopbackMode |
+ (heth->Init).DuplexMode |
+ macconf->ChecksumOffload |
+ macconf->RetryTransmission |
+ macconf->AutomaticPadCRCStrip |
+ macconf->BackOffLimit |
+ macconf->DeferralCheck);
+
+ /* Write to ETHERNET MACCR */
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
+
+ /* Wait until the write operation will be taken into account :
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
+
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/
+ /* Write to ETHERNET MACFFR */
+ (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
+ macconf->SourceAddrFilter |
+ macconf->PassControlFrames |
+ macconf->BroadcastFramesReception |
+ macconf->DestinationAddrFilter |
+ macconf->PromiscuousMode |
+ macconf->MulticastFramesFilter |
+ macconf->UnicastFramesFilter);
+
+ /* Wait until the write operation will be taken into account :
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACFFR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACFFR = tmpreg1;
+
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
+ /* Write to ETHERNET MACHTHR */
+ (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
+
+ /* Write to ETHERNET MACHTLR */
+ (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/
+
+ /* Get the ETHERNET MACFCR value */
+ tmpreg1 = (heth->Instance)->MACFCR;
+ /* Clear xx bits */
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
+
+ tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
+ macconf->ZeroQuantaPause |
+ macconf->PauseLowThreshold |
+ macconf->UnicastPauseFrameDetect |
+ macconf->ReceiveFlowControl |
+ macconf->TransmitFlowControl);
+
+ /* Write to ETHERNET MACFCR */
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
+
+ /* Wait until the write operation will be taken into account :
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACFCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACFCR = tmpreg1;
+
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
+ (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
+ macconf->VLANTagIdentifier);
+
+ /* Wait until the write operation will be taken into account :
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACVLANTR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACVLANTR = tmpreg1;
+ }
+ else /* macconf == NULL : here we just configure Speed and Duplex mode */
+ {
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/
+ /* Get the ETHERNET MACCR value */
+ tmpreg1 = (heth->Instance)->MACCR;
+
+ /* Clear FES and DM bits */
+ tmpreg1 &= ~(0x00004800U);
+
+ tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
+
+ /* Write to ETHERNET MACCR */
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
+ }
+
+ /* Set the ETH state to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets ETH DMA Configuration.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param dmaconf DMA Configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
+{
+ uint32_t tmpreg1 = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State= HAL_ETH_STATE_BUSY;
+
+ /* Check parameters */
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
+ assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
+ assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
+
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
+ /* Get the ETHERNET DMAOMR value */
+ tmpreg1 = (heth->Instance)->DMAOMR;
+ /* Clear xx bits */
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
+
+ tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
+ dmaconf->ReceiveStoreForward |
+ dmaconf->FlushReceivedFrame |
+ dmaconf->TransmitStoreForward |
+ dmaconf->TransmitThresholdControl |
+ dmaconf->ForwardErrorFrames |
+ dmaconf->ForwardUndersizedGoodFrames |
+ dmaconf->ReceiveThresholdControl |
+ dmaconf->SecondFrameOperate);
+
+ /* Write to ETHERNET DMAOMR */
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->DMAOMR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMAOMR = tmpreg1;
+
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/
+ (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
+ dmaconf->FixedBurst |
+ dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+ dmaconf->TxDMABurstLength |
+ dmaconf->EnhancedDescriptorFormat |
+ (dmaconf->DescriptorSkipLength << 2U) |
+ dmaconf->DMAArbitration |
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->DMABMR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMABMR = tmpreg1;
+
+ /* Set the ETH state to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+ (+) Get the ETH handle state:
+ HAL_ETH_GetState();
+
+
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the ETH HAL state
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL state
+ */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
+{
+ /* Return ETH state */
+ return heth->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures Ethernet MAC and DMA with default parameters.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param err Ethernet Init error
+ * @retval HAL status
+ */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
+{
+ ETH_MACInitTypeDef macinit;
+ ETH_DMAInitTypeDef dmainit;
+ uint32_t tmpreg1 = 0U;
+
+ if (err != ETH_SUCCESS) /* Auto-negotiation failed */
+ {
+ /* Set Ethernet duplex mode to Full-duplex */
+ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
+
+ /* Set Ethernet speed to 100M */
+ (heth->Init).Speed = ETH_SPEED_100M;
+ }
+
+ /* Ethernet MAC default initialization **************************************/
+ macinit.Watchdog = ETH_WATCHDOG_ENABLE;
+ macinit.Jabber = ETH_JABBER_ENABLE;
+ macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
+ macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
+ macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
+ macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
+ if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
+ {
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
+ }
+ else
+ {
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
+ }
+ macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
+ macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
+ macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
+ macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
+ macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
+ macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
+ macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
+ macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
+ macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
+ macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
+ macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
+ macinit.HashTableHigh = 0x0U;
+ macinit.HashTableLow = 0x0U;
+ macinit.PauseTime = 0x0U;
+ macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
+ macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
+ macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
+ macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
+ macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
+ macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
+ macinit.VLANTagIdentifier = 0x0U;
+
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/
+ /* Get the ETHERNET MACCR value */
+ tmpreg1 = (heth->Instance)->MACCR;
+ /* Clear WD, PCE, PS, TE and RE bits */
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
+ /* Set the WD bit according to ETH Watchdog value */
+ /* Set the JD: bit according to ETH Jabber value */
+ /* Set the IFG bit according to ETH InterFrameGap value */
+ /* Set the DCRS bit according to ETH CarrierSense value */
+ /* Set the FES bit according to ETH Speed value */
+ /* Set the DO bit according to ETH ReceiveOwn value */
+ /* Set the LM bit according to ETH LoopbackMode value */
+ /* Set the DM bit according to ETH Mode value */
+ /* Set the IPCO bit according to ETH ChecksumOffload value */
+ /* Set the DR bit according to ETH RetryTransmission value */
+ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
+ /* Set the BL bit according to ETH BackOffLimit value */
+ /* Set the DC bit according to ETH DeferralCheck value */
+ tmpreg1 |= (uint32_t)(macinit.Watchdog |
+ macinit.Jabber |
+ macinit.InterFrameGap |
+ macinit.CarrierSense |
+ (heth->Init).Speed |
+ macinit.ReceiveOwn |
+ macinit.LoopbackMode |
+ (heth->Init).DuplexMode |
+ macinit.ChecksumOffload |
+ macinit.RetryTransmission |
+ macinit.AutomaticPadCRCStrip |
+ macinit.BackOffLimit |
+ macinit.DeferralCheck);
+
+ /* Write to ETHERNET MACCR */
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
+
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/
+ /* Set the RA bit according to ETH ReceiveAll value */
+ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
+ /* Set the PCF bit according to ETH PassControlFrames value */
+ /* Set the DBF bit according to ETH BroadcastFramesReception value */
+ /* Set the DAIF bit according to ETH DestinationAddrFilter value */
+ /* Set the PR bit according to ETH PromiscuousMode value */
+ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
+ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
+ /* Write to ETHERNET MACFFR */
+ (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
+ macinit.SourceAddrFilter |
+ macinit.PassControlFrames |
+ macinit.BroadcastFramesReception |
+ macinit.DestinationAddrFilter |
+ macinit.PromiscuousMode |
+ macinit.MulticastFramesFilter |
+ macinit.UnicastFramesFilter);
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACFFR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACFFR = tmpreg1;
+
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
+ /* Write to ETHERNET MACHTHR */
+ (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
+
+ /* Write to ETHERNET MACHTLR */
+ (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
+ /*----------------------- ETHERNET MACFCR Configuration -------------------*/
+
+ /* Get the ETHERNET MACFCR value */
+ tmpreg1 = (heth->Instance)->MACFCR;
+ /* Clear xx bits */
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
+
+ /* Set the PT bit according to ETH PauseTime value */
+ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
+ /* Set the PLT bit according to ETH PauseLowThreshold value */
+ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
+ /* Set the RFE bit according to ETH ReceiveFlowControl value */
+ /* Set the TFE bit according to ETH TransmitFlowControl value */
+ tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
+ macinit.ZeroQuantaPause |
+ macinit.PauseLowThreshold |
+ macinit.UnicastPauseFrameDetect |
+ macinit.ReceiveFlowControl |
+ macinit.TransmitFlowControl);
+
+ /* Write to ETHERNET MACFCR */
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACFCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACFCR = tmpreg1;
+
+ /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
+ /* Set the ETV bit according to ETH VLANTagComparison value */
+ /* Set the VL bit according to ETH VLANTagIdentifier value */
+ (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
+ macinit.VLANTagIdentifier);
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACVLANTR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACVLANTR = tmpreg1;
+
+ /* Ethernet DMA default initialization ************************************/
+ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
+ dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
+ dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
+ dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
+ dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
+ dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
+ dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
+ dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
+ dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
+ dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
+ dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
+ dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+ dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+ dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
+ dmainit.DescriptorSkipLength = 0x0U;
+ dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
+
+ /* Get the ETHERNET DMAOMR value */
+ tmpreg1 = (heth->Instance)->DMAOMR;
+ /* Clear xx bits */
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
+
+ /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
+ /* Set the RSF bit according to ETH ReceiveStoreForward value */
+ /* Set the DFF bit according to ETH FlushReceivedFrame value */
+ /* Set the TSF bit according to ETH TransmitStoreForward value */
+ /* Set the TTC bit according to ETH TransmitThresholdControl value */
+ /* Set the FEF bit according to ETH ForwardErrorFrames value */
+ /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
+ /* Set the RTC bit according to ETH ReceiveThresholdControl value */
+ /* Set the OSF bit according to ETH SecondFrameOperate value */
+ tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
+ dmainit.ReceiveStoreForward |
+ dmainit.FlushReceivedFrame |
+ dmainit.TransmitStoreForward |
+ dmainit.TransmitThresholdControl |
+ dmainit.ForwardErrorFrames |
+ dmainit.ForwardUndersizedGoodFrames |
+ dmainit.ReceiveThresholdControl |
+ dmainit.SecondFrameOperate);
+
+ /* Write to ETHERNET DMAOMR */
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->DMAOMR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMAOMR = tmpreg1;
+
+ /*----------------------- ETHERNET DMABMR Configuration ------------------*/
+ /* Set the AAL bit according to ETH AddressAlignedBeats value */
+ /* Set the FB bit according to ETH FixedBurst value */
+ /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
+ /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
+ /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
+ /* Set the DSL bit according to ETH DesciptorSkipLength value */
+ /* Set the PR and DA bits according to ETH DMAArbitration value */
+ (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
+ dmainit.FixedBurst |
+ dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+ dmainit.TxDMABurstLength |
+ dmainit.EnhancedDescriptorFormat |
+ (dmainit.DescriptorSkipLength << 2U) |
+ dmainit.DMAArbitration |
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->DMABMR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMABMR = tmpreg1;
+
+ if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
+ {
+ /* Enable the Ethernet Rx Interrupt */
+ __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
+ }
+
+ /* Initialize MAC address in ethernet MAC */
+ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
+}
+
+/**
+ * @brief Configures the selected MAC address.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param MacAddr The MAC address to configure
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_Address0: MAC Address0
+ * @arg ETH_MAC_Address1: MAC Address1
+ * @arg ETH_MAC_Address2: MAC Address2
+ * @arg ETH_MAC_Address3: MAC Address3
+ * @param Addr Pointer to MAC address buffer data (6 bytes)
+ * @retval HAL status
+ */
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
+{
+ uint32_t tmpreg1;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+
+ /* Calculate the selected MAC address high register */
+ tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
+ /* Load the selected MAC address high register */
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
+ /* Calculate the selected MAC address low register */
+ tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
+
+ /* Load the selected MAC address low register */
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
+}
+
+/**
+ * @brief Enables the MAC transmission.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg1 = 0U;
+
+ /* Enable the MAC transmission */
+ (heth->Instance)->MACCR |= ETH_MACCR_TE;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACCR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
+}
+
+/**
+ * @brief Disables the MAC transmission.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg1 = 0U;
+
+ /* Disable the MAC transmission */
+ (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACCR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
+}
+
+/**
+ * @brief Enables the MAC reception.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg1 = 0U;
+
+ /* Enable the MAC reception */
+ (heth->Instance)->MACCR |= ETH_MACCR_RE;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACCR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
+}
+
+/**
+ * @brief Disables the MAC reception.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg1 = 0U;
+
+ /* Disable the MAC reception */
+ (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->MACCR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
+}
+
+/**
+ * @brief Enables the DMA transmission.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
+{
+ /* Enable the DMA transmission */
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
+}
+
+/**
+ * @brief Disables the DMA transmission.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
+{
+ /* Disable the DMA transmission */
+ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
+}
+
+/**
+ * @brief Enables the DMA reception.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
+{
+ /* Enable the DMA reception */
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
+}
+
+/**
+ * @brief Disables the DMA reception.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
+{
+ /* Disable the DMA reception */
+ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
+}
+
+/**
+ * @brief Clears the ETHERNET transmit FIFO.
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg1 = 0U;
+
+ /* Set the Flush Transmit FIFO bit */
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg1 = (heth->Instance)->DMAOMR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMAOMR = tmpreg1;
+}
+
+/**
+ * @brief This function provides delay (in milliseconds) based on CPU cycles method.
+ * @param mdelay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+static void ETH_Delay(uint32_t mdelay)
+{
+ __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
+ do
+ {
+ __NOP();
+ }
+ while (Delay --);
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
+ STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#endif /* HAL_ETH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2181 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_eth.h
+ * @author MCD Application Team
+ * @brief Header file of ETH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_ETH_H
+#define __STM32F4xx_HAL_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ETH
+ * @{
+ */
+
+/** @addtogroup ETH_Private_Macros
+ * @{
+ */
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
+ ((SPEED) == ETH_SPEED_100M))
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
+ ((MODE) == ETH_MODE_HALFDUPLEX))
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
+ ((CMD) == ETH_WATCHDOG_DISABLE))
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
+ ((CMD) == ETH_JABBER_DISABLE))
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEAll_DISABLE))
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
+ ((CMD) == ETH_FIXEDBURST_DISABLE))
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
+ ((FLAG) == ETH_DMATXDESC_IC) || \
+ ((FLAG) == ETH_DMATXDESC_LS) || \
+ ((FLAG) == ETH_DMATXDESC_FS) || \
+ ((FLAG) == ETH_DMATXDESC_DC) || \
+ ((FLAG) == ETH_DMATXDESC_DP) || \
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \
+ ((FLAG) == ETH_DMATXDESC_TER) || \
+ ((FLAG) == ETH_DMATXDESC_TCH) || \
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \
+ ((FLAG) == ETH_DMATXDESC_IHE) || \
+ ((FLAG) == ETH_DMATXDESC_ES) || \
+ ((FLAG) == ETH_DMATXDESC_JT) || \
+ ((FLAG) == ETH_DMATXDESC_FF) || \
+ ((FLAG) == ETH_DMATXDESC_PCE) || \
+ ((FLAG) == ETH_DMATXDESC_LCA) || \
+ ((FLAG) == ETH_DMATXDESC_NC) || \
+ ((FLAG) == ETH_DMATXDESC_LCO) || \
+ ((FLAG) == ETH_DMATXDESC_EC) || \
+ ((FLAG) == ETH_DMATXDESC_VF) || \
+ ((FLAG) == ETH_DMATXDESC_CC) || \
+ ((FLAG) == ETH_DMATXDESC_ED) || \
+ ((FLAG) == ETH_DMATXDESC_UF) || \
+ ((FLAG) == ETH_DMATXDESC_DB))
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
+ ((FLAG) == ETH_DMARXDESC_AFM) || \
+ ((FLAG) == ETH_DMARXDESC_ES) || \
+ ((FLAG) == ETH_DMARXDESC_DE) || \
+ ((FLAG) == ETH_DMARXDESC_SAF) || \
+ ((FLAG) == ETH_DMARXDESC_LE) || \
+ ((FLAG) == ETH_DMARXDESC_OE) || \
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \
+ ((FLAG) == ETH_DMARXDESC_FS) || \
+ ((FLAG) == ETH_DMARXDESC_LS) || \
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
+ ((FLAG) == ETH_DMARXDESC_LC) || \
+ ((FLAG) == ETH_DMARXDESC_FT) || \
+ ((FLAG) == ETH_DMARXDESC_RWT) || \
+ ((FLAG) == ETH_DMARXDESC_RE) || \
+ ((FLAG) == ETH_DMARXDESC_DBE) || \
+ ((FLAG) == ETH_DMARXDESC_CE) || \
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+ ((FLAG) == ETH_PMT_FLAG_MPR))
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+ ((FLAG) == ETH_DMA_FLAG_T))
+#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+ ((IT) == ETH_MAC_IT_PMT))
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+ ((FLAG) == ETH_MAC_FLAG_PMT))
+#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
+ ((IT) != 0x00U))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Private_Defines
+ * @{
+ */
+/* Delay to wait when writing to some Ethernet registers */
+#define ETH_REG_WRITE_DELAY 0x00000001U
+
+/* ETHERNET Errors */
+#define ETH_SUCCESS 0U
+#define ETH_ERROR 1U
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
+
+/* ETHERNET DMA Rx descriptors Frame length Shift */
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
+
+/* ETHERNET MACCR register Mask */
+#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
+
+/* ETHERNET MACFCR register Mask */
+#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
+
+/* ETHERNET DMAOMR register Mask */
+#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH 8U
+
+/* ETHERNET Missed frames counter Shift */
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
+ /**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Types ETH Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
+ HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
+ HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
+ HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
+}HAL_ETH_StateTypeDef;
+
+/**
+ * @brief ETH Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+ and the mode (half/full-duplex).
+ This parameter can be a value of @ref ETH_AutoNegotiation */
+
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
+ This parameter can be a value of @ref ETH_Speed */
+
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+ This parameter can be a value of @ref ETH_Duplex_Mode */
+
+ uint16_t PhyAddress; /*!< Ethernet PHY address.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
+ This parameter can be a value of @ref ETH_Rx_Mode */
+
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
+ This parameter can be a value of @ref ETH_Checksum_Mode */
+
+ uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
+ This parameter can be a value of @ref ETH_Media_Interface */
+
+} ETH_InitTypeDef;
+
+
+ /**
+ * @brief ETH MAC Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer
+ When enabled, the MAC allows no more then 2048 bytes to be received.
+ When disabled, the MAC can receive up to 16384 bytes.
+ This parameter can be a value of @ref ETH_Watchdog */
+
+ uint32_t Jabber; /*!< Selects or not Jabber timer
+ When enabled, the MAC allows no more then 2048 bytes to be sent.
+ When disabled, the MAC can send up to 16384 bytes.
+ This parameter can be a value of @ref ETH_Jabber */
+
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */
+
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
+ This parameter can be a value of @ref ETH_Carrier_Sense */
+
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+ in Half-Duplex mode.
+ This parameter can be a value of @ref ETH_Receive_Own */
+
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */
+
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+ This parameter can be a value of @ref ETH_Checksum_Offload */
+
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+ when a collision occurs (Half-Duplex mode).
+ This parameter can be a value of @ref ETH_Retry_Transmission */
+
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
+
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
+ This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
+ This parameter can be a value of @ref ETH_Deferral_Check */
+
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
+ This parameter can be a value of @ref ETH_Receive_All */
+
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */
+
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */
+
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */
+
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
+
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
+
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
+
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
+
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
+
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
+
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
+ automatic retransmission of PAUSE Frame.
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+ unicast address and unique multicast address).
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
+
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
+ disable its transmitter for a specified time (Pause Time)
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+ or the MAC back-pressure operation (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */
+
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+ comparison and filtering.
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
+
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
+
+} ETH_MACInitTypeDef;
+
+/**
+ * @brief ETH DMA Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
+
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */
+
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */
+
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */
+
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+ and length less than 64 bytes) including pad-bytes and CRC)
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+ frame of Transmit data even before obtaining the status for the first frame.
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
+ This parameter can be a value of @ref ETH_Fixed_Burst */
+
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
+ This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
+
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
+ This parameter can be a value of @ref ETH_DMA_Arbitration */
+} ETH_DMAInitTypeDef;
+
+
+/**
+ * @brief ETH DMA Descriptors data structure definition
+ */
+
+typedef struct
+{
+ __IO uint32_t Status; /*!< Status */
+
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
+
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
+
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
+
+ /*!< Enhanced ETHERNET DMA PTP Descriptors */
+ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
+
+ uint32_t Reserved1; /*!< Reserved */
+
+ uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
+
+ uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
+
+} ETH_DMADescTypeDef;
+
+/**
+ * @brief Received Frame Informations structure definition
+ */
+typedef struct
+{
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
+
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
+
+ uint32_t SegCount; /*!< Segment count */
+
+ uint32_t length; /*!< Frame length */
+
+ uint32_t buffer; /*!< Frame buffer */
+
+} ETH_DMARxFrameInfos;
+
+/**
+ * @brief ETH Handle Structure definition
+ */
+
+typedef struct
+{
+ ETH_TypeDef *Instance; /*!< Register base address */
+
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
+
+ uint32_t LinkStatus; /*!< Ethernet link status */
+
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
+
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
+
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
+
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
+
+ HAL_LockTypeDef Lock; /*!< ETH Lock */
+
+} ETH_HandleTypeDef;
+
+ /**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETH_Exported_Constants ETH Exported Constants
+ * @{
+ */
+
+/** @defgroup ETH_Buffers_setting ETH Buffers setting
+ * @{
+ */
+#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC 4U /*!< Ethernet CRC */
+#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
+
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when
+ an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
+ to the driver receive buffers memory.
+
+ Depending on the size of the received ethernet packet and the size of
+ each ethernet driver receive buffer, the received packet can take one or more
+ ethernet driver receive buffer.
+
+ In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
+ and the total count of the driver receive buffers ETH_RXBUFNB.
+
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_RX_BUF_SIZE
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
+#ifndef ETH_RXBUFNB
+ #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
+#endif
+
+
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when
+ an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
+ driver transmit buffers memory to the TxFIFO.
+
+ Depending on the size of the Ethernet packet to be transmitted and the size of
+ each ethernet driver transmit buffer, the packet to be transmitted can take
+ one or more ethernet driver transmit buffer.
+
+ In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
+ and the total count of the driver transmit buffers ETH_TXBUFNB.
+
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_TX_BUF_SIZE
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
+#ifndef ETH_TXBUFNB
+ #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
+#endif
+
+ /**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
+ * @{
+ */
+
+/*
+ DMA Tx Descriptor
+ -----------------------------------------------------------------------------------------------
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES2 | Buffer1 Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
+ */
+#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
+#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
+#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
+#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
+#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
+#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
+
+/**
+ * @brief Bit definition of TDES1 register
+ */
+#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
+
+/**
+ * @brief Bit definition of TDES2 register
+ */
+#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of TDES3 register
+ */
+#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
+
+ /*---------------------------------------------------------------------------------------------
+ TDES6 | Transmit Time Stamp Low [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES7 | Transmit Time Stamp High [31:0] |
+ ----------------------------------------------------------------------------------------------*/
+
+/* Bit definition of TDES6 register */
+ #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
+
+/* Bit definition of TDES7 register */
+ #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
+
+/**
+ * @}
+ */
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
+ * @{
+ */
+
+/*
+ DMA Rx Descriptor
+ --------------------------------------------------------------------------------------------------------------------
+ RDES0 | OWN(31) | Status [30:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES2 | Buffer1 Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
+ */
+#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/**
+ * @brief Bit definition of RDES1 register
+ */
+#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
+
+/**
+ * @brief Bit definition of RDES2 register
+ */
+#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of RDES3 register
+ */
+#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
+
+/*---------------------------------------------------------------------------------------------------------------------
+ RDES4 | Reserved[31:15] | Extended Status [14:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES5 | Reserved[31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES6 | Receive Time Stamp Low [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES7 | Receive Time Stamp High [31:0] |
+ --------------------------------------------------------------------------------------------------------------------*/
+
+/* Bit definition of RDES4 register */
+#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
+#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
+#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
+ #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
+#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
+#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
+#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
+#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
+#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
+#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
+ #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
+ #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
+ #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
+
+/* Bit definition of RDES6 register */
+#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
+
+/* Bit definition of RDES7 register */
+#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
+/**
+ * @}
+ */
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
+ * @{
+ */
+#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
+#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
+
+/**
+ * @}
+ */
+/** @defgroup ETH_Speed ETH Speed
+ * @{
+ */
+#define ETH_SPEED_10M 0x00000000U
+#define ETH_SPEED_100M 0x00004000U
+
+/**
+ * @}
+ */
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+ * @{
+ */
+#define ETH_MODE_FULLDUPLEX 0x00000800U
+#define ETH_MODE_HALFDUPLEX 0x00000000U
+/**
+ * @}
+ */
+/** @defgroup ETH_Rx_Mode ETH Rx Mode
+ * @{
+ */
+#define ETH_RXPOLLING_MODE 0x00000000U
+#define ETH_RXINTERRUPT_MODE 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
+ * @{
+ */
+#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
+#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Media_Interface ETH Media Interface
+ * @{
+ */
+#define ETH_MEDIA_INTERFACE_MII 0x00000000U
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Watchdog ETH Watchdog
+ * @{
+ */
+#define ETH_WATCHDOG_ENABLE 0x00000000U
+#define ETH_WATCHDOG_DISABLE 0x00800000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Jabber ETH Jabber
+ * @{
+ */
+#define ETH_JABBER_ENABLE 0x00000000U
+#define ETH_JABBER_DISABLE 0x00400000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
+ * @{
+ */
+#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
+ * @{
+ */
+#define ETH_CARRIERSENCE_ENABLE 0x00000000U
+#define ETH_CARRIERSENCE_DISABLE 0x00010000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Own ETH Receive Own
+ * @{
+ */
+#define ETH_RECEIVEOWN_ENABLE 0x00000000U
+#define ETH_RECEIVEOWN_DISABLE 0x00002000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
+ * @{
+ */
+#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
+#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
+ * @{
+ */
+#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
+#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
+ * @{
+ */
+#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
+#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
+ * @{
+ */
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
+ * @{
+ */
+#define ETH_BACKOFFLIMIT_10 0x00000000U
+#define ETH_BACKOFFLIMIT_8 0x00000020U
+#define ETH_BACKOFFLIMIT_4 0x00000040U
+#define ETH_BACKOFFLIMIT_1 0x00000060U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Deferral_Check ETH Deferral Check
+ * @{
+ */
+#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
+#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_All ETH Receive All
+ * @{
+ */
+#define ETH_RECEIVEALL_ENABLE 0x80000000U
+#define ETH_RECEIVEAll_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
+ * @{
+ */
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
+#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
+ * @{
+ */
+#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
+ * @{
+ */
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
+ * @{
+ */
+#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
+#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
+ * @{
+ */
+#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
+#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
+ * @{
+ */
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
+#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
+#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
+ * @{
+ */
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
+#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
+ * @{
+ */
+#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
+#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
+ * @{
+ */
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
+ * @{
+ */
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
+ * @{
+ */
+#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
+#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
+ * @{
+ */
+#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
+#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
+ * @{
+ */
+#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
+#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses ETH MAC addresses
+ * @{
+ */
+#define ETH_MAC_ADDRESS0 0x00000000U
+#define ETH_MAC_ADDRESS1 0x00000008U
+#define ETH_MAC_ADDRESS2 0x00000010U
+#define ETH_MAC_ADDRESS3 0x00000018U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
+ * @{
+ */
+#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
+#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
+ * @{
+ */
+#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
+ * @{
+ */
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
+ * @{
+ */
+#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
+#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
+ * @{
+ */
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
+ * @{
+ */
+#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
+#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
+ * @{
+ */
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
+ * @{
+ */
+#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
+#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
+ * @{
+ */
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
+ * @{
+ */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
+ * @{
+ */
+#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
+#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
+ * @{
+ */
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
+ * @{
+ */
+#define ETH_FIXEDBURST_ENABLE 0x00010000U
+#define ETH_FIXEDBURST_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
+ * @{
+ */
+#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
+ * @{
+ */
+#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
+ * @{
+ */
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
+ * @{
+ */
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
+#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
+ * @{
+ */
+#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
+ * @{
+ */
+#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
+ * @{
+ */
+#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_PMT_Flags ETH PMT Flags
+ * @{
+ */
+#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Flags ETH MAC Flags
+ * @{
+ */
+#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
+#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Flags ETH DMA Flags
+ * @{
+ */
+#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
+#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
+#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+ * @{
+ */
+#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+ * @{
+ */
+#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
+#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
+ * @{
+ */
+#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
+#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
+#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
+ * @{
+ */
+#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
+#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_overflow ETH DMA overflow
+ * @{
+ */
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
+ * @{
+ */
+#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Macros ETH Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/** @brief Reset ETH handle state
+ * @param __HANDLE__ specifies the ETH handle.
+ * @retval None
+ */
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag of TDES0 to check.
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag of RDES0 to check.
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Enables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
+
+/**
+ * @brief Disables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
+
+/**
+ * @brief Set the specified DMA Rx Desc Own bit.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
+
+/**
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
+ * @param __HANDLE__ ETH Handle
+ * @retval The Transmit descriptor collision counter value.
+ */
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
+
+/**
+ * @brief Set the specified DMA Tx Desc Own bit.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
+
+/**
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
+
+/**
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
+
+/**
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+ * @param __HANDLE__ ETH Handle
+ * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
+
+/**
+ * @brief Enables the DMA Tx Desc CRC.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
+
+/**
+ * @brief Disables the DMA Tx Desc CRC.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
+
+/**
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
+
+/**
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
+
+/**
+ * @brief Enables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Initiate a Pause Control Frame (Full-duplex only).
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @retval The new state of flow control busy status bit (SET or RESET).
+ */
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ * @arg ETH_MAC_FLAG_MMC : MMC flag
+ * @arg ETH_MAC_FLAG_PMT : PMT flag
+ * @retval The state of ETHERNET MAC flag.
+ */
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Enables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
+ * enabled @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
+ * disabled. @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Clears the ETHERNET DMA IT pending bit.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+* @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __OVERFLOW__ specifies the DMA overflow flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
+ * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
+
+/**
+ * @brief Set the DMA Receive status watchdog timer register value
+ * @param __HANDLE__ ETH Handle
+ * @param __VALUE__ DMA Receive status watchdog timer register value
+ * @retval None
+ */
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
+
+/**
+ * @brief Enables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Disables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Enables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Disables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Magic Packet Detection.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
+
+/**
+ * @brief Disables the MAC Magic Packet Detection.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Power Down.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Disables the MAC Power Down.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.
+ * @param __HANDLE__ ETH Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
+
+/**
+ * @brief Enables the MMC Counter Freeze.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
+
+/**
+ * @brief Disables the MMC Counter Freeze.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
+
+/**
+ * @brief Enables the MMC Reset On Read.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
+
+/**
+ * @brief Disables the MMC Reset On Read.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
+
+/**
+ * @brief Enables the MMC Counter Stop Rollover.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
+
+/**
+ * @brief Disables the MMC Counter Stop Rollover.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
+
+/**
+ * @brief Resets the MMC Counters.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
+
+/**
+ * @brief Enables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
+/**
+ * @brief Disables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
+/**
+ * @brief Enables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Enables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enable event on ETH External event line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disable event on ETH External event line
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Get flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Clear flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
+ }while(0U)
+
+/**
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ }while(0U)
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup ETH_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+
+/** @addtogroup ETH_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+
+/**
+ * @}
+ */
+/* IO operation functions ****************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
+/* Communication with PHY functions*/
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+/* Callback in non blocking modes (Interrupt) */
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group3
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group4
+ * @{
+ */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
+ STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_ETH_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,788 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash.c
+ * @author MCD Application Team
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Memory Control functions
+ * + Peripheral Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+ to the Flash memory. It implements the erase and program Flash memory operations
+ and the read and write protection mechanisms.
+
+ [..] The Flash memory interface accelerates code execution with a system of instruction
+ prefetch and cache lines.
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Prefetch on I-Code
+ (+) 64 cache lines of 128 bits on I-Code
+ (+) 8 cache lines of 128 bits on D-Code
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the FLASH
+ memory of all STM32F4xx devices.
+
+ (#) FLASH Memory IO Programming functions:
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+ HAL_FLASH_Lock() functions
+ (++) Program functions: byte, half word, word and double word
+ (++) There Two modes of programming :
+ (+++) Polling mode using HAL_FLASH_Program() function
+ (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+ (#) Interrupts and flags management functions :
+ (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+ (++) Wait for last FLASH operation according to its status
+ (++) Get error flag status by calling HAL_SetErrorCode()
+
+ [..]
+ In addition to these functions, this driver includes a set of macros allowing
+ to handle the following operations:
+ (+) Set the latency
+ (+) Enable/Disable the prefetch buffer
+ (+) Enable/Disable the Instruction cache and the Data cache
+ (+) Reset the Instruction cache and the Data cache
+ (+) Enable/Disable the FLASH interrupts
+ (+) Monitor the FLASH flags status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH FLASH
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+/* Variable used for Erase sectors under interruption */
+FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+/* Program operations */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);
+static void FLASH_SetErrorCode(void);
+
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ * @brief Programming operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Programming operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FLASH
+ program operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program byte, halfword, word or double word at a specified address
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
+ {
+ /*Program byte (8-bit) at a specified address.*/
+ FLASH_Program_Byte(Address, (uint8_t) Data);
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(Address, (uint16_t) Data);
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ /*Program word (32-bit) at a specified address.*/
+ FLASH_Program_Word(Address, (uint32_t) Data);
+ }
+ else
+ {
+ /*Program double word (64-bit) at a specified address.*/
+ FLASH_Program_DoubleWord(Address, Data);
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG Bit */
+ FLASH->CR &= (~FLASH_CR_PG);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.
+ * @param TypeProgram Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+ /* Enable End of FLASH Operation interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+ /* Enable Error source interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+ pFlash.Address = Address;
+
+ if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
+ {
+ /*Program byte (8-bit) at a specified address.*/
+ FLASH_Program_Byte(Address, (uint8_t) Data);
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(Address, (uint16_t) Data);
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ /*Program word (32-bit) at a specified address.*/
+ FLASH_Program_Word(Address, (uint32_t) Data);
+ }
+ else
+ {
+ /*Program double word (64-bit) at a specified address.*/
+ FLASH_Program_DoubleWord(Address, Data);
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function handles FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t addresstmp = 0U;
+
+ /* Check FLASH operation error flags */
+#if defined(FLASH_SR_RDERR)
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+ FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+#else
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+ FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
+#endif /* FLASH_SR_RDERR */
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+ {
+ /*return the faulty sector*/
+ addresstmp = pFlash.Sector;
+ pFlash.Sector = 0xFFFFFFFFU;
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /*return the faulty bank*/
+ addresstmp = pFlash.Bank;
+ }
+ else
+ {
+ /*return the faulty address*/
+ addresstmp = pFlash.Address;
+ }
+
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(addresstmp);
+
+ /*Stop the procedure ongoing*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+
+ /* Check FLASH End of Operation flag */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+ {
+ /*Nb of sector to erased can be decreased*/
+ pFlash.NbSectorsToErase--;
+
+ /* Check if there are still sectors to erase*/
+ if(pFlash.NbSectorsToErase != 0U)
+ {
+ addresstmp = pFlash.Sector;
+ /*Indicate user which sector has been erased*/
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+
+ /*Increment sector number*/
+ pFlash.Sector++;
+ addresstmp = pFlash.Sector;
+ FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);
+ }
+ else
+ {
+ /*No more sectors to Erase, user callback can be called.*/
+ /*Reset Sector and stop Erase sectors procedure*/
+ pFlash.Sector = addresstmp = 0xFFFFFFFFU;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches() ;
+
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+ }
+ }
+ else
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /* MassErase ended. Return the selected bank */
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches() ;
+
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+ }
+ else
+ {
+ /*Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ {
+ /* Operation is completed, disable the PG, SER, SNB and MER Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
+
+ /* Disable End of FLASH Operation interrupt */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
+
+ /* Disable Error source interrupt */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+
+/**
+ * @brief FLASH end of operation interrupt callback
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
+ * Mass Erase: Bank number which has been requested to erase
+ * Sectors Erase: Sector which has been erased
+ * (if 0xFFFFFFFFU, it means that all the selected sectors have been erased)
+ * Program: Address which was selected for data program
+ * @retval None
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
+ * Mass Erase: Bank number which has been requested to erase
+ * Sectors Erase: Sector number which returned an error
+ * Program: Address which was selected for data program
+ * @retval None
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+ /* Verify Flash is unlocked */
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ FLASH->CR |= FLASH_CR_LOCK;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Unlock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+ if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
+ {
+ /* Authorizes the Option Byte register programming */
+ FLASH->OPTKEYR = FLASH_OPT_KEY1;
+ FLASH->OPTKEYR = FLASH_OPT_KEY2;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+ /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+ FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+ /* Set the OPTSTRT bit in OPTCR register */
+ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
+
+ /* Wait for last operation to be completed */
+ return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode: The returned value can be a combination of:
+ * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+ * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
+ * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
+ * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+ * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+ * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
+ */
+uint32_t HAL_FLASH_GetError(void)
+{
+ return pFlash.ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout maximum flash operationtimeout
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Clear Error Code */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+#if defined(FLASH_SR_RDERR)
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+ FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+#else
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+ FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
+#endif /* FLASH_SR_RDERR */
+ {
+ /*Save the error code*/
+ FLASH_SetErrorCode();
+ return HAL_ERROR;
+ }
+
+ /* If there is no error flag set */
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Program a double word (64-bit) at a specified address.
+ * @note This function must be used when the device voltage range is from
+ * 2.7V to 3.6V and Vpp in the range 7V to 9V.
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+ /* If the previous operation is completed, proceed to program the new data */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+ FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
+ FLASH->CR |= FLASH_CR_PG;
+
+ /* Program the double-word */
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+ *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+}
+
+
+/**
+ * @brief Program word (32-bit) at a specified address.
+ * @note This function must be used when the device voltage range is from
+ * 2.7V to 3.6V.
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+ /* If the previous operation is completed, proceed to program the new data */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+ FLASH->CR |= FLASH_PSIZE_WORD;
+ FLASH->CR |= FLASH_CR_PG;
+
+ *(__IO uint32_t*)Address = Data;
+}
+
+/**
+ * @brief Program a half-word (16-bit) at a specified address.
+ * @note This function must be used when the device voltage range is from
+ * 2.1V to 3.6V.
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+ /* If the previous operation is completed, proceed to program the new data */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+ FLASH->CR |= FLASH_PSIZE_HALF_WORD;
+ FLASH->CR |= FLASH_CR_PG;
+
+ *(__IO uint16_t*)Address = Data;
+}
+
+/**
+ * @brief Program byte (8-bit) at a specified address.
+ * @note This function must be used when the device voltage range is from
+ * 1.8V to 3.6V.
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+ /* If the previous operation is completed, proceed to program the new data */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+ FLASH->CR |= FLASH_PSIZE_BYTE;
+ FLASH->CR |= FLASH_CR_PG;
+
+ *(__IO uint8_t*)Address = Data;
+}
+
+/**
+ * @brief Set the specific FLASH error flag.
+ * @retval None
+ */
+static void FLASH_SetErrorCode(void)
+{
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+
+ /* Clear FLASH write protection error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
+
+ /* Clear FLASH Programming alignment error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
+
+ /* Clear FLASH Programming parallelism error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
+
+ /* Clear FLASH Programming sequence error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
+ }
+#if defined(FLASH_SR_RDERR)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
+
+ /* Clear FLASH Proprietary readout protection error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
+ }
+#endif /* FLASH_SR_RDERR */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
+
+ /* Clear FLASH Operation error pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,444 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash.h
+ * @author MCD Application Team
+ * @brief Header file of FLASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_H
+#define __STM32F4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum
+{
+ FLASH_PROC_NONE = 0U,
+ FLASH_PROC_SECTERASE,
+ FLASH_PROC_MASSERASE,
+ FLASH_PROC_PROGRAM
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/
+
+ __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
+
+ __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/
+
+ __IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/
+
+ __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/
+
+ __IO uint32_t Address; /*Internal variable to save address selected for program*/
+
+ HAL_LockTypeDef Lock; /* FLASH locking object */
+
+ __IO uint32_t ErrorCode; /* FLASH error code */
+
+}FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+/** @defgroup FLASH_Error_Code FLASH Error Code
+ * @brief FLASH Error Code
+ * @{
+ */
+#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */
+#define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */
+#define HAL_FLASH_ERROR_PGP 0x00000004U /*!< Programming Parallelism error */
+#define HAL_FLASH_ERROR_PGA 0x00000008U /*!< Programming Alignment error */
+#define HAL_FLASH_ERROR_WRP 0x00000010U /*!< Write protection error */
+#define HAL_FLASH_ERROR_OPERATION 0x00000020U /*!< Operation Error */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+ * @{
+ */
+#define FLASH_TYPEPROGRAM_BYTE 0x00000000U /*!< Program byte (8-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_HALFWORD 0x00000001U /*!< Program a half-word (16-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_WORD 0x00000002U /*!< Program a word (32-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003U /*!< Program a double word (64-bit) at a specified address */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+ * @brief Flag definition
+ * @{
+ */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
+#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
+#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */
+#if defined(FLASH_SR_RDERR)
+#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */
+#endif /* FLASH_SR_RDERR */
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+ * @brief FLASH Interrupt definition
+ * @{
+ */
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+ * @{
+ */
+#define FLASH_PSIZE_BYTE 0x00000000U
+#define FLASH_PSIZE_HALF_WORD 0x00000100U
+#define FLASH_PSIZE_WORD 0x00000200U
+#define FLASH_PSIZE_DOUBLE_WORD 0x00000300U
+#define CR_PSIZE_MASK 0xFFFFFCFFU
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Keys FLASH Keys
+ * @{
+ */
+#define RDP_KEY ((uint16_t)0x00A5)
+#define FLASH_KEY1 0x45670123U
+#define FLASH_KEY2 0xCDEF89ABU
+#define FLASH_OPT_KEY1 0x08192A3BU
+#define FLASH_OPT_KEY2 0x4C5D6E7FU
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ * @{
+ */
+/**
+ * @brief Set the FLASH Latency.
+ * @param __LATENCY__ FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ * @retval none
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
+
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval none
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval none
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
+
+/**
+ * @brief Enable the FLASH instruction cache.
+ * @retval none
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
+
+/**
+ * @brief Disable the FLASH instruction cache.
+ * @retval none
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
+
+/**
+ * @brief Enable the FLASH data cache.
+ * @retval none
+ */
+#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
+
+/**
+ * @brief Disable the FLASH data cache.
+ * @retval none
+ */
+#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
+
+/**
+ * @brief Resets the FLASH instruction Cache.
+ * @note This function must be used only when the Instruction Cache is disabled.
+ * @retval None
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
+ FLASH->ACR &= ~FLASH_ACR_ICRST; \
+ }while(0U)
+
+/**
+ * @brief Resets the FLASH data Cache.
+ * @note This function must be used only when the data Cache is disabled.
+ * @retval None
+ */
+#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
+ FLASH->ACR &= ~FLASH_ACR_DCRST; \
+ }while(0U)
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__ specifies the FLASH flags to check.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+ * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag
+ * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
+
+/**
+ * @brief Clear the specified FLASH flags.
+ * @param __FLAG__ specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+ * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
+ * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extension module */
+#include "stm32f4xx_hal_flash_ex.h"
+#include "stm32f4xx_hal_flash_ramfunc.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+/* Program operation functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+uint32_t HAL_FLASH_GetError(void);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+
+/**
+ * @brief ACR register byte 0 (Bits[7:0]) base address
+ */
+#define ACR_BYTE0_ADDRESS 0x40023C00U
+/**
+ * @brief OPTCR register byte 0 (Bits[7:0]) base address
+ */
+#define OPTCR_BYTE0_ADDRESS 0x40023C14U
+/**
+ * @brief OPTCR register byte 1 (Bits[15:8]) base address
+ */
+#define OPTCR_BYTE1_ADDRESS 0x40023C15U
+/**
+ * @brief OPTCR register byte 2 (Bits[23:16]) base address
+ */
+#define OPTCR_BYTE2_ADDRESS 0x40023C16U
+/**
+ * @brief OPTCR register byte 3 (Bits[31:24]) base address
+ */
+#define OPTCR_BYTE3_ADDRESS 0x40023C17U
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
+ * @{
+ */
+#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1366 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @brief Extended FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the FLASH extension peripheral:
+ * + Extended programming operations functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Flash Extension features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and
+ STM32F429xx/439xx devices contains the following additional features
+
+ (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+ capability (RWW)
+ (+) Dual bank memory organization
+ (+) PCROP protection for all banks
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx
+ devices. It includes
+ (#) FLASH Memory Erase functions:
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+ HAL_FLASH_Lock() functions
+ (++) Erase function: Erase sector, erase all sectors
+ (++) There are two modes of erase :
+ (+++) Polling Mode using HAL_FLASHEx_Erase()
+ (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+ (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
+ (++) Set/Reset the write protection
+ (++) Set the Read protection Level
+ (++) Set the BOR level
+ (++) Program the user Option Bytes
+ (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
+ (++) Extended space (bank 2) erase function
+ (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
+ (++) Dual Boot activation
+ (++) Write protection configuration for bank 2
+ (++) PCROP protection configuration and control for both banks
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASHEx FLASHEx
+ * @brief FLASH HAL Extension module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Variables
+ * @{
+ */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
+/* Option bytes control */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
+static uint8_t FLASH_OB_GetUser(void);
+static uint16_t FLASH_OB_GetWRP(void);
+static uint8_t FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetBOR(void);
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+ defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector);
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector);
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+ STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended programming operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the Extension FLASH
+ programming operations.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors
+ * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @param[out] SectorError pointer to variable that
+ * contains the configuration information on faulty sector in case of error
+ * (0xFFFFFFFFU means that all the sectors have been correctly erased)
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t index = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /*Initialization of SectorError variable*/
+ *SectorError = 0xFFFFFFFFU;
+
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* if the erase operation is completed, disable the MER Bit */
+ FLASH->CR &= (~FLASH_MER_BIT);
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+ /* Erase by sector by sector to be done*/
+ for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
+ {
+ FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the SER and SNB Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
+
+ if(status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty sector*/
+ *SectorError = index;
+ break;
+ }
+ }
+ }
+ /* Flush the caches to be sure of the data consistency */
+ FLASH_FlushCaches();
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
+ * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Enable End of FLASH Operation interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+ /* Enable Error source interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+ /* Clear pending flags (if any) */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
+ FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
+
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+ /*Mass erase to be done*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+ pFlash.Bank = pEraseInit->Banks;
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+ }
+ else
+ {
+ /* Erase by sector to be done*/
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
+ pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+ pFlash.Sector = pEraseInit->Sector;
+ pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
+
+ /*Erase 1st sector and wait for IT*/
+ FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program option bytes
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /*Write protection configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+ {
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));
+ if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+ {
+ /*Enable of Write protection on the selected Sector*/
+ status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
+ }
+ else
+ {
+ /*Disable of Write protection on the selected Sector*/
+ status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
+ }
+ }
+
+ /*Read protection configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+ {
+ status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+ }
+
+ /*USER configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+ {
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW,
+ pOBInit->USERConfig&OB_STOP_NO_RST,
+ pOBInit->USERConfig&OB_STDBY_NO_RST);
+ }
+
+ /*BOR Level configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+ {
+ status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Get the Option byte configuration
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
+
+ /*Get WRP*/
+ pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
+
+ /*Get RDP Level*/
+ pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
+
+ /*Get USER*/
+ pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
+
+ /*Get BOR Level*/
+ pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
+}
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief Program option bytes
+ * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_OBEX(pAdvOBInit->OptionType));
+
+ /*Program PCROP option byte*/
+ if(((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
+ {
+ /* Check the parameters */
+ assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
+ if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)
+ {
+ /*Enable of Write protection on the selected Sector*/
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
+#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+ status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+ STM32F413xx || STM32F423xx */
+ }
+ else
+ {
+ /*Disable of Write protection on the selected Sector*/
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
+#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+ status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+ STM32F413xx || STM32F423xx */
+ }
+ }
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ /*Program BOOT config option byte*/
+ if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
+ {
+ status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
+ }
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+ return status;
+}
+
+/**
+ * @brief Get the OBEX byte configuration
+ * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ /*Get Sector*/
+ pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+ /*Get Sector for Bank1*/
+ pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+
+ /*Get Sector for Bank2*/
+ pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
+
+ /*Get Boot config OB*/
+ pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+ STM32F413xx || STM32F423xx */
+}
+
+/**
+ * @brief Select the Protection Mode
+ *
+ * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted
+ * Global Read Out Protection modification (from level1 to level0)
+ * @note Once SPRMOD bit is active unprotection of a protected sector is not possible
+ * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+ * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
+ * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
+{
+ uint8_t optiontmp = 0xFF;
+
+ /* Mask SPRMOD bit */
+ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
+
+ /* Update Option Byte */
+ *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deselect the Protection Mode
+ *
+ * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted
+ * Global Read Out Protection modification (from level1 to level0)
+ * @note Once SPRMOD bit is active unprotection of a protected sector is not possible
+ * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+ * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
+ * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.
+ *
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
+{
+ uint8_t optiontmp = 0xFF;
+
+ /* Mask SPRMOD bit */
+ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
+
+ /* Update Option Byte */
+ *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);
+
+ return HAL_OK;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\
+ STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+ STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes value for Bank 2
+ * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices.
+ * @retval The FLASH Write Protection Option Bytes value
+ */
+uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Full erase of FLASH memory sectors
+ * @param VoltageRange The device voltage range which defines the erase parallelism.
+ * This parameter can be one of the following values:
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * the operation will be done by byte (8-bit)
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * the operation will be done by half word (16-bit)
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * the operation will be done by word (32-bit)
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * the operation will be done by double word (64-bit)
+ *
+ * @param Banks Banks to be erased
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be erased
+ * @arg FLASH_BANK_2: Bank2 to be erased
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+ *
+ * @retval HAL Status
+ */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+ /* Check the parameters */
+ assert_param(IS_VOLTAGERANGE(VoltageRange));
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* if the previous operation is completed, proceed to erase all sectors */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+
+ if(Banks == FLASH_BANK_BOTH)
+ {
+ /* bank1 & bank2 will be erased*/
+ FLASH->CR |= FLASH_MER_BIT;
+ }
+ else if(Banks == FLASH_BANK_1)
+ {
+ /*Only bank1 will be erased*/
+ FLASH->CR |= FLASH_CR_MER1;
+ }
+ else
+ {
+ /*Only bank2 will be erased*/
+ FLASH->CR |= FLASH_CR_MER2;
+ }
+ FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
+}
+
+/**
+ * @brief Erase the specified FLASH memory sector
+ * @param Sector FLASH sector to erase
+ * The value of this parameter depend on device used within the same series
+ * @param VoltageRange The device voltage range which defines the erase parallelism.
+ * This parameter can be one of the following values:
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * the operation will be done by byte (8-bit)
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * the operation will be done by half word (16-bit)
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * the operation will be done by word (32-bit)
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * the operation will be done by double word (64-bit)
+ *
+ * @retval None
+ */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+ uint32_t tmp_psize = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_SECTOR(Sector));
+ assert_param(IS_VOLTAGERANGE(VoltageRange));
+
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
+ {
+ tmp_psize = FLASH_PSIZE_BYTE;
+ }
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
+ {
+ tmp_psize = FLASH_PSIZE_HALF_WORD;
+ }
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
+ {
+ tmp_psize = FLASH_PSIZE_WORD;
+ }
+ else
+ {
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+ }
+
+ /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
+ if(Sector > FLASH_SECTOR_11)
+ {
+ Sector += 4U;
+ }
+ /* If the previous operation is completed, proceed to erase the sector */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+ FLASH->CR |= tmp_psize;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+ FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+ FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+ * @brief Enable the write protection of the desired bank1 or bank 2 sectors
+ *
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash sector i if CortexM4
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+ *
+ * @param WRPSector specifies the sector(s) to be write protected.
+ * This parameter can be one of the following values:
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
+ * @arg OB_WRP_SECTOR_All
+ * @note BANK2 starts from OB_WRP_SECTOR_12
+ *
+ * @param Banks Enable write protection on all the sectors for the specific bank
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: WRP on all sectors of bank1
+ * @arg FLASH_BANK_2: WRP on all sectors of bank2
+ * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+ *
+ * @retval HAL FLASH State
+ */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+ (WRPSector < OB_WRP_SECTOR_12))
+ {
+ if(WRPSector == OB_WRP_SECTOR_All)
+ {
+ /*Write protection on all sector of BANK1*/
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12));
+ }
+ else
+ {
+ /*Write protection done on sectors of BANK1*/
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
+ }
+ }
+ else
+ {
+ /*Write protection done on sectors of BANK2*/
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12));
+ }
+
+ /*Write protection on all sector of BANK2*/
+ if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12));
+ }
+ }
+
+ }
+ return status;
+}
+
+/**
+ * @brief Disable the write protection of the desired bank1 or bank 2 sectors
+ *
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash sector i if CortexM4
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+ *
+ * @param WRPSector specifies the sector(s) to be write protected.
+ * This parameter can be one of the following values:
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
+ * @arg OB_WRP_Sector_All
+ * @note BANK2 starts from OB_WRP_SECTOR_12
+ *
+ * @param Banks Disable write protection on all the sectors for the specific bank
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be erased
+ * @arg FLASH_BANK_2: Bank2 to be erased
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+ *
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+ (WRPSector < OB_WRP_SECTOR_12))
+ {
+ if(WRPSector == OB_WRP_SECTOR_All)
+ {
+ /*Write protection on all sector of BANK1*/
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12);
+ }
+ else
+ {
+ /*Write protection done on sectors of BANK1*/
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
+ }
+ }
+ else
+ {
+ /*Write protection done on sectors of BANK2*/
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12);
+ }
+
+ /*Write protection on all sector of BANK2*/
+ if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12);
+ }
+ }
+
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the Dual Bank Boot.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
+ * @param BootConfig specifies the Dual Bank Boot Option byte.
+ * This parameter can be one of the following values:
+ * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
+ * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
+ * @retval None
+ */
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_BOOT(BootConfig));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Set Dual Bank Boot */
+ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
+ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enable the read/write protection (PCROP) of the desired
+ * sectors of Bank 1 and/or Bank 2.
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ * @param SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1.
+ * This parameter can be one of the following values:
+ * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
+ * @arg OB_PCROP_SECTOR__All
+ * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
+ * This parameter can be one of the following values:
+ * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
+ * @arg OB_PCROP_SECTOR__All
+ * @param Banks Enable PCROP protection on all the sectors for the specific bank
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: WRP on all sectors of bank1
+ * @arg FLASH_BANK_2: WRP on all sectors of bank2
+ * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+ *
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+ {
+ assert_param(IS_OB_PCROP(SectorBank1));
+ /*Write protection done on sectors of BANK1*/
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1;
+ }
+ else
+ {
+ assert_param(IS_OB_PCROP(SectorBank2));
+ /*Write protection done on sectors of BANK2*/
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
+ }
+
+ /*Write protection on all sector of BANK2*/
+ if(Banks == FLASH_BANK_BOTH)
+ {
+ assert_param(IS_OB_PCROP(SectorBank2));
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /*Write protection done on sectors of BANK2*/
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
+ }
+ }
+
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Disable the read/write protection (PCROP) of the desired
+ * sectors of Bank 1 and/or Bank 2.
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ * @param SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1.
+ * This parameter can be one of the following values:
+ * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
+ * @arg OB_PCROP_SECTOR__All
+ * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
+ * This parameter can be one of the following values:
+ * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
+ * @arg OB_PCROP_SECTOR__All
+ * @param Banks Disable PCROP protection on all the sectors for the specific bank
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: WRP on all sectors of bank1
+ * @arg FLASH_BANK_2: WRP on all sectors of bank2
+ * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+ *
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+ {
+ assert_param(IS_OB_PCROP(SectorBank1));
+ /*Write protection done on sectors of BANK1*/
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~SectorBank1);
+ }
+ else
+ {
+ /*Write protection done on sectors of BANK2*/
+ assert_param(IS_OB_PCROP(SectorBank2));
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
+ }
+
+ /*Write protection on all sector of BANK2*/
+ if(Banks == FLASH_BANK_BOTH)
+ {
+ assert_param(IS_OB_PCROP(SectorBank2));
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /*Write protection done on sectors of BANK2*/
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
+ }
+ }
+
+ }
+
+ return status;
+
+}
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+/**
+ * @brief Mass erase of FLASH memory
+ * @param VoltageRange The device voltage range which defines the erase parallelism.
+ * This parameter can be one of the following values:
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * the operation will be done by byte (8-bit)
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * the operation will be done by half word (16-bit)
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * the operation will be done by word (32-bit)
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * the operation will be done by double word (64-bit)
+ *
+ * @param Banks Banks to be erased
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be erased
+ *
+ * @retval None
+ */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+ /* Check the parameters */
+ assert_param(IS_VOLTAGERANGE(VoltageRange));
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* If the previous operation is completed, proceed to erase all sectors */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+ FLASH->CR |= FLASH_CR_MER;
+ FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
+}
+
+/**
+ * @brief Erase the specified FLASH memory sector
+ * @param Sector FLASH sector to erase
+ * The value of this parameter depend on device used within the same series
+ * @param VoltageRange The device voltage range which defines the erase parallelism.
+ * This parameter can be one of the following values:
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * the operation will be done by byte (8-bit)
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * the operation will be done by half word (16-bit)
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * the operation will be done by word (32-bit)
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * the operation will be done by double word (64-bit)
+ *
+ * @retval None
+ */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+ uint32_t tmp_psize = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_SECTOR(Sector));
+ assert_param(IS_VOLTAGERANGE(VoltageRange));
+
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
+ {
+ tmp_psize = FLASH_PSIZE_BYTE;
+ }
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
+ {
+ tmp_psize = FLASH_PSIZE_HALF_WORD;
+ }
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
+ {
+ tmp_psize = FLASH_PSIZE_WORD;
+ }
+ else
+ {
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+ }
+
+ /* If the previous operation is completed, proceed to erase the sector */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+ FLASH->CR |= tmp_psize;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+ FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+ FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+ * @brief Enable the write protection of the desired bank 1 sectors
+ *
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash sector i if CortexM4
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+ *
+ * @param WRPSector specifies the sector(s) to be write protected.
+ * The value of this parameter depend on device used within the same series
+ *
+ * @param Banks Enable write protection on all the sectors for the specific bank
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: WRP on all sectors of bank1
+ *
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the write protection of the desired bank 1 sectors
+ *
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash sector i if CortexM4
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+ *
+ * @param WRPSector specifies the sector(s) to be write protected.
+ * The value of this parameter depend on device used within the same series
+ *
+ * @param Banks Enable write protection on all the sectors for the specific bank
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: WRP on all sectors of bank1
+ *
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
+ }
+
+ return status;
+}
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+ STM32F413xx || STM32F423xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief Enable the read/write protection (PCROP) of the desired sectors.
+ * @note This function can be used only for STM32F401xx devices.
+ * @param Sector specifies the sector(s) to be read/write protected or unprotected.
+ * This parameter can be one of the following values:
+ * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
+ * @arg OB_PCROP_Sector_All
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_PCROP(Sector));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector;
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Disable the read/write protection (PCROP) of the desired sectors.
+ * @note This function can be used only for STM32F401xx devices.
+ * @param Sector specifies the sector(s) to be read/write protected or unprotected.
+ * This parameter can be one of the following values:
+ * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
+ * @arg OB_PCROP_Sector_All
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_PCROP(Sector));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~Sector);
+ }
+
+ return status;
+
+}
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+ STM32F413xx || STM32F423xx */
+
+/**
+ * @brief Set the read protection level.
+ * @param Level specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
+ *
+ * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+ *
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_LEVEL(Level));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @param Iwdg Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW: Software IWDG selected
+ * @arg OB_IWDG_HW: Hardware IWDG selected
+ * @param Stop Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
+ * @arg OB_STOP_RST: Reset generated when entering in STOP
+ * @param Stdby Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
+{
+ uint8_t optiontmp = 0xFF;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+ assert_param(IS_OB_STOP_SOURCE(Stop));
+ assert_param(IS_OB_STDBY_SOURCE(Stdby));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
+ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
+
+ /* Update User Option Byte */
+ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp)));
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set the BOR Level.
+ * @param Level specifies the Option Bytes BOR Reset Level.
+ * This parameter can be one of the following values:
+ * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+ * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+ * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+ * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_BOR_LEVEL(Level));
+
+ /* Set the BOR Level */
+ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
+ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
+ * and RST_STDBY(Bit2).
+ */
+static uint8_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return ((uint8_t)(FLASH->OPTCR & 0xE0));
+}
+
+/**
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ * @retval uint16_t FLASH Write Protection Option Bytes value
+ */
+static uint16_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+}
+
+/**
+ * @brief Returns the FLASH Read Protection level.
+ * @retval FLASH ReadOut Protection Status:
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
+ */
+static uint8_t FLASH_OB_GetRDP(void)
+{
+ uint8_t readstatus = OB_RDP_LEVEL_0;
+
+ if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2))
+ {
+ readstatus = OB_RDP_LEVEL_2;
+ }
+ else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
+ {
+ readstatus = OB_RDP_LEVEL_1;
+ }
+ else
+ {
+ readstatus = OB_RDP_LEVEL_0;
+ }
+
+ return readstatus;
+}
+
+/**
+ * @brief Returns the FLASH BOR level.
+ * @retval uint8_t The FLASH BOR level:
+ * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+ * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+ * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+ * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
+ */
+static uint8_t FLASH_OB_GetBOR(void)
+{
+ /* Return the FLASH BOR level */
+ return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
+}
+
+/**
+ * @brief Flush the instruction and data caches
+ * @retval None
+ */
+void FLASH_FlushCaches(void)
+{
+ /* Flush instruction cache */
+ if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)!= RESET)
+ {
+ /* Disable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+ /* Reset instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+ /* Enable instruction cache */
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ }
+
+ /* Flush data cache */
+ if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+ {
+ /* Disable data cache */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ /* Reset data cache */
+ __HAL_FLASH_DATA_CACHE_RESET();
+ /* Enable data cache */
+ __HAL_FLASH_DATA_CACHE_ENABLE();
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1082 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @brief Header file of FLASH HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_EX_H
+#define __STM32F4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< Mass erase or sector Erase.
+ This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
+ This parameter must be a value of @ref FLASHEx_Sectors */
+
+ uint32_t NbSectors; /*!< Number of sectors to be erased.
+ This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+ uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+ This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Option Bytes Program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< Option byte to be configured.
+ This parameter can be a value of @ref FLASHEx_Option_Type */
+
+ uint32_t WRPState; /*!< Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_WRP_State */
+
+ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
+ The value of this parameter depend on device used within the same series */
+
+ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t RDPLevel; /*!< Set the read protection level.
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+ uint32_t BORLevel; /*!< Set the BOR Level.
+ This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+ uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @brief FLASH Advanced Option Bytes Program structure definition
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+typedef struct
+{
+ uint32_t OptionType; /*!< Option byte to be configured for extension.
+ This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
+
+ uint32_t PCROPState; /*!< PCROP activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_PCROP_State */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ uint16_t Sectors; /*!< specifies the sector(s) set for PCROP.
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
+ STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1.
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+ uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2.
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+ uint8_t BootConfig; /*!< Specifies Option bytes for boot config.
+ This parameter can be a value of @ref FLASHEx_Dual_Boot */
+
+#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+}FLASH_AdvOBProgramInitTypeDef;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx ||
+ STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+ * @{
+ */
+#define FLASH_TYPEERASE_SECTORS 0x00000000U /*!< Sectors erase only */
+#define FLASH_TYPEERASE_MASSERASE 0x00000001U /*!< Flash Mass erase activation */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+ * @{
+ */
+#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Device operating range: 1.8V to 2.1V */
+#define FLASH_VOLTAGE_RANGE_2 0x00000001U /*!< Device operating range: 2.1V to 2.7V */
+#define FLASH_VOLTAGE_RANGE_3 0x00000002U /*!< Device operating range: 2.7V to 3.6V */
+#define FLASH_VOLTAGE_RANGE_4 0x00000003U /*!< Device operating range: 2.7V to 3.6V + External Vpp */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+ * @{
+ */
+#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+ * @{
+ */
+#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */
+#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */
+#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */
+#define OPTIONBYTE_BOR 0x00000008U /*!< BOR option byte configuration */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
+ it s no more possible to go back to level 1 or 0 */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+ * @{
+ */
+#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
+#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
+#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
+#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
+/**
+ * @}
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
+ * @{
+ */
+#define OB_PCROP_STATE_DISABLE 0x00000000U /*!< Disable PCROP */
+#define OB_PCROP_STATE_ENABLE 0x00000001U /*!< Enable PCROP */
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define OPTIONBYTE_PCROP 0x00000001U /*!< PCROP option byte configuration */
+#define OPTIONBYTE_BOOTCONFIG 0x00000002U /*!< BOOTConfig option byte configuration */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+#define OPTIONBYTE_PCROP 0x00000001U /*!<PCROP option byte configuration */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+ STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+/*------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
+#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */
+#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */
+#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
+#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
+#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
+#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/*--------------------------------------------------------------------------------------------------------------*/
+
+/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx/STM32F423xx -----------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+ STM32F413xx || STM32F423xx */
+/*--------------------------------------------------------------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_BANK_1 1U /*!< Bank 1 */
+#define FLASH_BANK_2 2U /*!< Bank 2 */
+#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+#define FLASH_BANK_1 1U /*!< Bank 1 */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+ STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+ STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Sectors FLASH Sectors
+ * @{
+ */
+/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
+#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
+#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
+#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
+#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */
+#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */
+#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */
+#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */
+#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */
+#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */
+#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */
+#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */
+#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */
+#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */
+#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */
+#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */
+#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*-------------------------------------- STM32F413xx/STM32F423xx --------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
+#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
+#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
+#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
+#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */
+#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */
+#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */
+#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */
+#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */
+#endif /* STM32F413xx || STM32F423xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
+#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
+#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
+#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
+#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
+#endif /* STM32F401xC */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+ * @{
+ */
+/*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_8 0x00000100U /*!< Write protection of Sector8 */
+#define OB_WRP_SECTOR_9 0x00000200U /*!< Write protection of Sector9 */
+#define OB_WRP_SECTOR_10 0x00000400U /*!< Write protection of Sector10 */
+#define OB_WRP_SECTOR_11 0x00000800U /*!< Write protection of Sector11 */
+#define OB_WRP_SECTOR_12 0x00000001U << 12U /*!< Write protection of Sector12 */
+#define OB_WRP_SECTOR_13 0x00000002U << 12U /*!< Write protection of Sector13 */
+#define OB_WRP_SECTOR_14 0x00000004U << 12U /*!< Write protection of Sector14 */
+#define OB_WRP_SECTOR_15 0x00000008U << 12U /*!< Write protection of Sector15 */
+#define OB_WRP_SECTOR_16 0x00000010U << 12U /*!< Write protection of Sector16 */
+#define OB_WRP_SECTOR_17 0x00000020U << 12U /*!< Write protection of Sector17 */
+#define OB_WRP_SECTOR_18 0x00000040U << 12U /*!< Write protection of Sector18 */
+#define OB_WRP_SECTOR_19 0x00000080U << 12U /*!< Write protection of Sector19 */
+#define OB_WRP_SECTOR_20 0x00000100U << 12U /*!< Write protection of Sector20 */
+#define OB_WRP_SECTOR_21 0x00000200U << 12U /*!< Write protection of Sector21 */
+#define OB_WRP_SECTOR_22 0x00000400U << 12U /*!< Write protection of Sector22 */
+#define OB_WRP_SECTOR_23 0x00000800U << 12U /*!< Write protection of Sector23 */
+#define OB_WRP_SECTOR_All 0x00000FFFU << 12U /*!< Write protection of all Sectors */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------- STM32F413xx/STM32F423xx -------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_8 0x00000100U /*!< Write protection of Sector8 */
+#define OB_WRP_SECTOR_9 0x00000200U /*!< Write protection of Sector9 */
+#define OB_WRP_SECTOR_10 0x00000400U /*!< Write protection of Sector10 */
+#define OB_WRP_SECTOR_11 0x00000800U /*!< Write protection of Sector11 */
+#define OB_WRP_SECTOR_12 0x00001000U /*!< Write protection of Sector12 */
+#define OB_WRP_SECTOR_13 0x00002000U /*!< Write protection of Sector13 */
+#define OB_WRP_SECTOR_14 0x00004000U /*!< Write protection of Sector14 */
+#define OB_WRP_SECTOR_15 0x00004000U /*!< Write protection of Sector15 */
+#define OB_WRP_SECTOR_All 0x00007FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F413xx || STM32F423xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_8 0x00000100U /*!< Write protection of Sector8 */
+#define OB_WRP_SECTOR_9 0x00000200U /*!< Write protection of Sector9 */
+#define OB_WRP_SECTOR_10 0x00000400U /*!< Write protection of Sector10 */
+#define OB_WRP_SECTOR_11 0x00000800U /*!< Write protection of Sector11 */
+#define OB_WRP_SECTOR_All 0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/
+#if defined(STM32F401xC)
+#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_All 0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F401xC */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_All 0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_All 0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+/*-----------------------------------------------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
+ * @{
+ */
+/*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define OB_PCROP_SECTOR_0 0x00000001U /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 0x00000002U /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 0x00000004U /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 0x00000008U /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 0x00000010U /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 0x00000020U /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_6 0x00000040U /*!< PC Read/Write protection of Sector6 */
+#define OB_PCROP_SECTOR_7 0x00000080U /*!< PC Read/Write protection of Sector7 */
+#define OB_PCROP_SECTOR_8 0x00000100U /*!< PC Read/Write protection of Sector8 */
+#define OB_PCROP_SECTOR_9 0x00000200U /*!< PC Read/Write protection of Sector9 */
+#define OB_PCROP_SECTOR_10 0x00000400U /*!< PC Read/Write protection of Sector10 */
+#define OB_PCROP_SECTOR_11 0x00000800U /*!< PC Read/Write protection of Sector11 */
+#define OB_PCROP_SECTOR_12 0x00000001U /*!< PC Read/Write protection of Sector12 */
+#define OB_PCROP_SECTOR_13 0x00000002U /*!< PC Read/Write protection of Sector13 */
+#define OB_PCROP_SECTOR_14 0x00000004U /*!< PC Read/Write protection of Sector14 */
+#define OB_PCROP_SECTOR_15 0x00000008U /*!< PC Read/Write protection of Sector15 */
+#define OB_PCROP_SECTOR_16 0x00000010U /*!< PC Read/Write protection of Sector16 */
+#define OB_PCROP_SECTOR_17 0x00000020U /*!< PC Read/Write protection of Sector17 */
+#define OB_PCROP_SECTOR_18 0x00000040U /*!< PC Read/Write protection of Sector18 */
+#define OB_PCROP_SECTOR_19 0x00000080U /*!< PC Read/Write protection of Sector19 */
+#define OB_PCROP_SECTOR_20 0x00000100U /*!< PC Read/Write protection of Sector20 */
+#define OB_PCROP_SECTOR_21 0x00000200U /*!< PC Read/Write protection of Sector21 */
+#define OB_PCROP_SECTOR_22 0x00000400U /*!< PC Read/Write protection of Sector22 */
+#define OB_PCROP_SECTOR_23 0x00000800U /*!< PC Read/Write protection of Sector23 */
+#define OB_PCROP_SECTOR_All 0x00000FFFU /*!< PC Read/Write protection of all Sectors */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define OB_PCROP_SECTOR_0 0x00000001U /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 0x00000002U /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 0x00000004U /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 0x00000008U /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 0x00000010U /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 0x00000020U /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_6 0x00000040U /*!< PC Read/Write protection of Sector6 */
+#define OB_PCROP_SECTOR_7 0x00000080U /*!< PC Read/Write protection of Sector7 */
+#define OB_PCROP_SECTOR_8 0x00000100U /*!< PC Read/Write protection of Sector8 */
+#define OB_PCROP_SECTOR_9 0x00000200U /*!< PC Read/Write protection of Sector9 */
+#define OB_PCROP_SECTOR_10 0x00000400U /*!< PC Read/Write protection of Sector10 */
+#define OB_PCROP_SECTOR_11 0x00000800U /*!< PC Read/Write protection of Sector11 */
+#define OB_PCROP_SECTOR_12 0x00001000U /*!< PC Read/Write protection of Sector12 */
+#define OB_PCROP_SECTOR_13 0x00002000U /*!< PC Read/Write protection of Sector13 */
+#define OB_PCROP_SECTOR_14 0x00004000U /*!< PC Read/Write protection of Sector14 */
+#define OB_PCROP_SECTOR_15 0x00004000U /*!< PC Read/Write protection of Sector15 */
+#define OB_PCROP_SECTOR_All 0x00007FFFU /*!< PC Read/Write protection of all Sectors */
+#endif /* STM32F413xx || STM32F423xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/
+#if defined(STM32F401xC)
+#define OB_PCROP_SECTOR_0 0x00000001U /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 0x00000002U /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 0x00000004U /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 0x00000008U /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 0x00000010U /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 0x00000020U /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_All 0x00000FFFU /*!< PC Read/Write protection of all Sectors */
+#endif /* STM32F401xC */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define OB_PCROP_SECTOR_0 0x00000001U /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 0x00000002U /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 0x00000004U /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 0x00000008U /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 0x00000010U /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_All 0x00000FFFU /*!< PC Read/Write protection of all Sectors */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*-------------- STM32F401xE/STM32F411xE/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F446xx --*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define OB_PCROP_SECTOR_0 0x00000001U /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 0x00000002U /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 0x00000004U /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 0x00000008U /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 0x00000010U /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 0x00000020U /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_6 0x00000040U /*!< PC Read/Write protection of Sector6 */
+#define OB_PCROP_SECTOR_7 0x00000080U /*!< PC Read/Write protection of Sector7 */
+#define OB_PCROP_SECTOR_All 0x00000FFFU /*!< PC Read/Write protection of all Sectors */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
+#define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define OB_PCROP_DESELECTED ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
+#define OB_PCROP_SELECTED ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
+/* Extension Program operation functions *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
+ * @{
+ */
+/*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_SECTOR_TOTAL 24U
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/*-------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define FLASH_SECTOR_TOTAL 16U
+#endif /* STM32F413xx || STM32F423xx */
+
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define FLASH_SECTOR_TOTAL 12U
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_TOTAL 6U
+#endif /* STM32F401xC */
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define FLASH_SECTOR_TOTAL 5U
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*--------------------------------- STM32F401xE/STM32F411xE/STM32F412xG/STM32F446xx -------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define FLASH_SECTOR_TOTAL 8U
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+/**
+ * @brief OPTCR1 register byte 2 (Bits[23:16]) base address
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define OPTCR1_BYTE2_ADDRESS 0x40023C1AU
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
+ * @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+ ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+ ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+ ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+
+#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
+ ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1) ||\
+ ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
+ ((VALUE) == OB_PCROP_STATE_ENABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \
+ ((VALUE) == OPTIONBYTE_BOOTCONFIG))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || \
+ ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || \
+ ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || \
+ ((LATENCY) == FLASH_LATENCY_7) || \
+ ((LATENCY) == FLASH_LATENCY_8) || \
+ ((LATENCY) == FLASH_LATENCY_9) || \
+ ((LATENCY) == FLASH_LATENCY_10) || \
+ ((LATENCY) == FLASH_LATENCY_11) || \
+ ((LATENCY) == FLASH_LATENCY_12) || \
+ ((LATENCY) == FLASH_LATENCY_13) || \
+ ((LATENCY) == FLASH_LATENCY_14) || \
+ ((LATENCY) == FLASH_LATENCY_15))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || \
+ ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || \
+ ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || \
+ ((LATENCY) == FLASH_LATENCY_7))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2) || \
+ ((BANK) == FLASH_BANK_BOTH))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx ||\
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
+ ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
+ ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
+ ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
+ ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
+ ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
+ ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
+ ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
+ ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15))
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F401xC)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5))
+#endif /* STM32F401xC */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
+ (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
+
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xC */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+ defined(STM32F412Rx) || defined(STM32F412Cx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F401xC)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xC */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+ defined(STM32F412Rx) || defined(STM32F412Cx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
+ * @{
+ */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+void FLASH_FlushCaches(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,191 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash_ramfunc.c
+ * @author MCD Application Team
+ * @brief FLASH RAMFUNC module driver.
+ * This file provides a FLASH firmware functions which should be
+ * executed from internal SRAM
+ * + Stop/Start the flash interface while System Run
+ * + Enable/Disable the flash sleep while System Run
+ @verbatim
+ ==============================================================================
+ ##### APIs executed from Internal RAM #####
+ ==============================================================================
+ [..]
+ *** ARM Compiler ***
+ --------------------
+ [..] RAM functions are defined using the toolchain options.
+ Functions that are be executed in RAM should reside in a separate
+ source module. Using the 'Options for File' dialog you can simply change
+ the 'Code / Const' area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the
+ Options for Target' dialog.
+
+ *** ICCARM Compiler ***
+ -----------------------
+ [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
+
+ *** GNU Compiler ***
+ --------------------
+ [..] RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".RamFunc")))".
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
+ * @brief FLASH functions executed from RAM
+ * @{
+ */
+#ifdef HAL_FLASH_MODULE_ENABLED
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
+ * @brief Peripheral Extended features functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### ramfunc functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions that should be executed from RAM
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Stop the flash interface while System Run
+ * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
+ * @note This mode couldn't be set while executing with the flash itself.
+ * It should be done with specific routine executed from RAM.
+ * @retval None
+ */
+__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void)
+{
+ /* Enable Power ctrl clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ /* Stop the flash interface while System Run */
+ SET_BIT(PWR->CR, PWR_CR_FISSR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the flash interface while System Run
+ * @note This mode is only available for STM32F411xx/STM32F446xx devices.
+ * @note This mode couldn't be set while executing with the flash itself.
+ * It should be done with specific routine executed from RAM.
+ * @retval None
+ */
+__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void)
+{
+ /* Enable Power ctrl clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ /* Start the flash interface while System Run */
+ CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the flash sleep while System Run
+ * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
+ * @note This mode could n't be set while executing with the flash itself.
+ * It should be done with specific routine executed from RAM.
+ * @retval None
+ */
+__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void)
+{
+ /* Enable Power ctrl clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ /* Enable the flash sleep while System Run */
+ SET_BIT(PWR->CR, PWR_CR_FMSSR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the flash sleep while System Run
+ * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
+ * @note This mode couldn't be set while executing with the flash itself.
+ * It should be done with specific routine executed from RAM.
+ * @retval None
+ */
+__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void)
+{
+ /* Enable Power ctrl clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ /* Disable the flash sleep while System Run */
+ CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+#endif /* HAL_FLASH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,95 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash_ramfunc.h
+ * @author MCD Application Team
+ * @brief Header file of FLASH RAMFUNC driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FLASH_RAMFUNC_H
+#define __STM32F4xx_FLASH_RAMFUNC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH_RAMFUNC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+ * @{
+ */
+__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void);
+__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void);
+__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void);
+__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,4881 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c.c
+ * @author MCD Application Team
+ * @brief FMPI2C HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (FMPI2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The FMPI2C HAL driver can be used as follows:
+
+ (#) Declare a FMPI2C_HandleTypeDef handle structure, for example:
+ FMPI2C_HandleTypeDef hfmpi2c;
+
+ (#)Initialize the FMPI2C low level resources by implementing the HAL_FMPI2C_MspInit() API:
+ (##) Enable the FMPI2Cx interface clock
+ (##) FMPI2C pins configuration
+ (+++) Enable the clock for the FMPI2C GPIOs
+ (+++) Configure FMPI2C pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the FMPI2Cx interrupt priority
+ (+++) Enable the NVIC FMPI2C IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx stream
+ (+++) Associate the initialized DMA handle to the hfmpi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx stream
+
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure.
+
+ (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_FMPI2C_MspInit(&hfmpi2c) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_FMPI2C_IsDeviceReady()
+
+ (#) For FMPI2C IO and IO MEM operations, three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_FMPI2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_FMPI2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Receive_IT()
+ (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Receive_IT()
+ (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
+ (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
+ (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
+ (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+
+ *** Interrupt mode IO sequential operation ***
+ ==============================================
+ [..]
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ when a direction change during transfer
+ [..]
+ (+) A specific option field manage the different steps of a sequential transfer
+ (+) Option field values are defined through @ref FMPI2C_XFEROPTIONS and are listed below:
+ (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition
+ (++) FMPI2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+ several times (like HAL_FMPI2C_Master_Sequential_Transmit_IT() then HAL_FMPI2C_Master_Sequential_Transmit_IT())
+ (++) FMPI2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and without a final stop condition in both cases
+ (++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and with a final stop condition in both cases
+ (++) FMPI2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+ interface several times (link with option FMPI2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using HAL_FMPI2C_Master_Sequential_Transmit_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME)
+ or HAL_FMPI2C_Master_Sequential_Receive_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME).
+ Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ without stopping the communication and so generate a restart condition.
+
+ (+) Differents sequential FMPI2C interfaces are listed below:
+ (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
+ (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
+ (++) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
+ (+++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave FMPI2C mode using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT()
+ (+++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+ (+++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ListenCpltCallback()
+ (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
+ (++) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
+ (++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
+ (++) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+ HAL_FMPI2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+ HAL_FMPI2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+ HAL_FMPI2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+ HAL_FMPI2C_Master_Receive_DMA()
+ (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+ HAL_FMPI2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+ HAL_FMPI2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
+ (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
+ (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
+ (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+ HAL_FMPI2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+ HAL_FMPI2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
+
+
+ *** FMPI2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in FMPI2C HAL driver.
+
+ (+) __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral
+ (+) __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral
+ (+) __HAL_FMPI2C_GENERATE_NACK: Generate a Non-Acknowledge FMPI2C peripheral in Slave mode
+ (+) __HAL_FMPI2C_GET_FLAG: Check whether the specified FMPI2C flag is set or not
+ (+) __HAL_FMPI2C_CLEAR_FLAG: Clear the specified FMPI2C pending flag
+ (+) __HAL_FMPI2C_ENABLE_IT: Enable the specified FMPI2C interrupt
+ (+) __HAL_FMPI2C_DISABLE_IT: Disable the specified FMPI2C interrupt
+
+ [..]
+ (@) You can refer to the FMPI2C HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMPI2C FMPI2C
+ * @brief FMPI2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup FMPI2C_Private_Define FMPI2C Private Define
+ * @{
+ */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< FMPI2C TIMING clear register Mask */
+#define FMPI2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define FMPI2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_TC (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE 255U
+#define SlaveAddr_SHIFT 7U
+#define SlaveAddr_MSK 0x06U
+
+/* Private define for @ref PreviousState usage */
+#define FMPI2C_STATE_MSK ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX | HAL_FMPI2C_STATE_BUSY_RX) & (~((uint32_t)HAL_FMPI2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
+#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */
+#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define FMPI2C_XFER_TX_IT (0x00000001U)
+#define FMPI2C_XFER_RX_IT (0x00000002U)
+#define FMPI2C_XFER_LISTEN_IT (0x00000004U)
+
+#define FMPI2C_XFER_ERROR_IT (0x00000011U)
+#define FMPI2C_XFER_CPLT_IT (0x00000012U)
+#define FMPI2C_XFER_RELOAD_IT (0x00000012U)
+
+/* Private define Sequential Transfer Options default/reset value */
+#define FMPI2C_NO_OPTION_FRAME (0xFFFF0000U)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+#define FMPI2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_FMPI2C_STATE_BUSY_TX) ? \
+ ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) : \
+ ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR)))
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
+ * @{
+ */
+/* Private functions to handle DMA transfer */
+static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c);
+static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c);
+static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions for FMPI2C transfer IRQ handler */
+static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+
+/* Private functions to flush TXDR register */
+static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c);
+
+/* Private functions to handle start, restart or stop a transfer */
+static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMPI2C_Exported_Functions FMPI2C Exported Functions
+ * @{
+ */
+
+/** @defgroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the FMPI2Cx peripheral:
+
+ (+) User must Implement HAL_FMPI2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_FMPI2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_FMPI2C_DeInit() to restore the default configuration
+ of the selected FMPI2Cx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMPI2C according to the specified parameters
+ * in the FMPI2C_InitTypeDef and initialize the associated handle.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the FMPI2C handle allocation */
+ if (hfmpi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_FMPI2C_OWN_ADDRESS1(hfmpi2c->Init.OwnAddress1));
+ assert_param(IS_FMPI2C_ADDRESSING_MODE(hfmpi2c->Init.AddressingMode));
+ assert_param(IS_FMPI2C_DUAL_ADDRESS(hfmpi2c->Init.DualAddressMode));
+ assert_param(IS_FMPI2C_OWN_ADDRESS2(hfmpi2c->Init.OwnAddress2));
+ assert_param(IS_FMPI2C_OWN_ADDRESS2_MASK(hfmpi2c->Init.OwnAddress2Masks));
+ assert_param(IS_FMPI2C_GENERAL_CALL(hfmpi2c->Init.GeneralCallMode));
+ assert_param(IS_FMPI2C_NO_STRETCH(hfmpi2c->Init.NoStretchMode));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hfmpi2c->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_FMPI2C_MspInit(hfmpi2c);
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /*---------------------------- FMPI2Cx TIMINGR Configuration ------------------*/
+ /* Configure FMPI2Cx: Frequency range */
+ hfmpi2c->Instance->TIMINGR = hfmpi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- FMPI2Cx OAR1 Configuration ---------------------*/
+ /* Disable Own Address1 before set the Own Address1 configuration */
+ hfmpi2c->Instance->OAR1 &= ~FMPI2C_OAR1_OA1EN;
+
+ /* Configure FMPI2Cx: Own Address1 and ack own address1 mode */
+ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT)
+ {
+ hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpi2c->Init.OwnAddress1);
+ }
+ else /* FMPI2C_ADDRESSINGMODE_10BIT */
+ {
+ hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpi2c->Init.OwnAddress1);
+ }
+
+ /*---------------------------- FMPI2Cx CR2 Configuration ----------------------*/
+ /* Configure FMPI2Cx: Addressing Master mode */
+ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ {
+ hfmpi2c->Instance->CR2 = (FMPI2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ hfmpi2c->Instance->CR2 |= (FMPI2C_CR2_AUTOEND | FMPI2C_CR2_NACK);
+
+ /*---------------------------- FMPI2Cx OAR2 Configuration ---------------------*/
+ /* Disable Own Address2 before set the Own Address2 configuration */
+ hfmpi2c->Instance->OAR2 &= ~FMPI2C_DUALADDRESS_ENABLE;
+
+ /* Configure FMPI2Cx: Dual mode and Own Address2 */
+ hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | (hfmpi2c->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/
+ /* Configure FMPI2Cx: Generalcall and NoStretch mode */
+ hfmpi2c->Instance->CR1 = (hfmpi2c->Init.GeneralCallMode | hfmpi2c->Init.NoStretchMode);
+
+ /* Enable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the FMPI2C peripheral.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Check the FMPI2C handle allocation */
+ if (hfmpi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the FMPI2C Peripheral Clock */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_FMPI2C_MspDeInit(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State = HAL_FMPI2C_STATE_RESET;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMPI2C MSP.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the FMPI2C MSP.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FMPI2C data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated FMPI2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_FMPI2C_Master_Transmit()
+ (++) HAL_FMPI2C_Master_Receive()
+ (++) HAL_FMPI2C_Slave_Transmit()
+ (++) HAL_FMPI2C_Slave_Receive()
+ (++) HAL_FMPI2C_Mem_Write()
+ (++) HAL_FMPI2C_Mem_Read()
+ (++) HAL_FMPI2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_FMPI2C_Master_Transmit_IT()
+ (++) HAL_FMPI2C_Master_Receive_IT()
+ (++) HAL_FMPI2C_Slave_Transmit_IT()
+ (++) HAL_FMPI2C_Slave_Receive_IT()
+ (++) HAL_FMPI2C_Master_Sequential_Transmit_IT()
+ (++) HAL_FMPI2C_Master_Sequential_Receive_IT()
+ (++) HAL_FMPI2C_Slave_Sequential_Transmit_IT()
+ (++) HAL_FMPI2C_Slave_Sequential_Receive_IT()
+ (++) HAL_FMPI2C_Mem_Write_IT()
+ (++) HAL_FMPI2C_Mem_Read_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_FMPI2C_Master_Transmit_DMA()
+ (++) HAL_FMPI2C_Master_Receive_DMA()
+ (++) HAL_FMPI2C_Slave_Transmit_DMA()
+ (++) HAL_FMPI2C_Slave_Receive_DMA()
+ (++) HAL_FMPI2C_Mem_Write_DMA()
+ (++) HAL_FMPI2C_Mem_Read_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_FMPI2C_MemTxCpltCallback()
+ (++) HAL_FMPI2C_MemRxCpltCallback()
+ (++) HAL_FMPI2C_MasterTxCpltCallback()
+ (++) HAL_FMPI2C_MasterRxCpltCallback()
+ (++) HAL_FMPI2C_SlaveTxCpltCallback()
+ (++) HAL_FMPI2C_SlaveRxCpltCallback()
+ (++) HAL_FMPI2C_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferISR = NULL;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ }
+
+ while (hfmpi2c->XferCount > 0U)
+ {
+ /* Wait until TXIS flag is set */
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->XferCount--;
+ hfmpi2c->XferSize--;
+
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ }
+ }
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferISR = NULL;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ while (hfmpi2c->XferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ }
+ }
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferISR = NULL;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+
+ /* If 10bit addressing mode is selected */
+ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ while (hfmpi2c->XferCount > 0U)
+ {
+ /* Wait until TXIS flag is set */
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->XferCount--;
+ }
+
+ /* Wait until STOP flag is set */
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferISR = NULL;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is reset Receiver mode */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ while (hfmpi2c->XferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Store Last receive data if any */
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferCount--;
+ }
+
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferCount--;
+ }
+
+ /* Wait until STOP flag is set */
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ uint32_t xfermode = 0U;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ uint32_t xfermode = 0U;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ uint32_t xfermode = 0U;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
+
+ if (hfmpi2c->XferSize > 0U)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
+
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ uint32_t xfermode = 0U;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
+
+ if (hfmpi2c->XferSize > 0U)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_DMA;
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
+{
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_DMA;
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferISR = NULL;
+
+ /* Send Slave Address and Memory Address */
+ if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->XferCount--;
+ hfmpi2c->XferSize--;
+
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ }
+
+ }
+ while (hfmpi2c->XferCount > 0U);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferISR = NULL;
+
+ /* Send Slave Address and Memory Address */
+ if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ {
+ /* Wait until TCR flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ }
+ }
+ while (hfmpi2c->XferCount > 0U);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ __IO uint32_t FMPI2C_Trials = 0U;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hfmpi2c->Instance->CR2 = FMPI2C_GENERATE_START(hfmpi2c->Init.AddressingMode, DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+ while ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Device is ready */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Device is ready */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (FMPI2C_Trials++ == Trials)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+ }
+ }
+ while (FMPI2C_Trials < Trials);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode with Interrupt.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode = 0U;
+ uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = XferOptions;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ /* If size > MAX_NBYTE_SIZE, use reload mode */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = hfmpi2c->XferOptions;
+ }
+
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if (hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX)
+ {
+ xferrequest = FMPI2C_NO_STARTSTOP;
+ }
+
+ /* Send Slave Address and set NBYTES to write */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master FMPI2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode = 0U;
+ uint32_t xferrequest = FMPI2C_GENERATE_START_READ;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = XferOptions;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ /* If hfmpi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = hfmpi2c->XferOptions;
+ }
+
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if (hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX)
+ {
+ xferrequest = FMPI2C_NO_STARTSTOP;
+ }
+
+ /* Send Slave Address and set NBYTES to read */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in slave/device FMPI2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* FMPI2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ hfmpi2c->XferOptions = XferOptions;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
+
+ if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sequential receive in slave/device FMPI2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* FMPI2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave TX state to RX state */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ hfmpi2c->XferOptions = XferOptions;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
+
+ if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
+
+ /* Enable the Address Match interrupt */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp;
+
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
+ {
+ tmp = (uint32_t)(hfmpi2c->State) & FMPI2C_STATE_MSK;
+ hfmpi2c->PreviousState = tmp | (uint32_t)(hfmpi2c->Mode);
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+ hfmpi2c->XferISR = NULL;
+
+ /* Disable the Address Match interrupt */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master FMPI2C IT or DMA process communication with Interrupt.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress)
+{
+ if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* Disable Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+ /* Set State at HAL_FMPI2C_STATE_ABORT */
+ hfmpi2c->State = HAL_FMPI2C_STATE_ABORT;
+
+ /* Set NBYTES to 1 to generate a dummy read on FMPI2C peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, 1, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_STOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief This function handles FMPI2C event interrupt request.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Get current IT Flags and IT sources value */
+ uint32_t itflags = READ_REG(hfmpi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hfmpi2c->Instance->CR1);
+
+ /* FMPI2C events treatment -------------------------------------*/
+ if (hfmpi2c->XferISR != NULL)
+ {
+ hfmpi2c->XferISR(hfmpi2c, itflags, itsources);
+ }
+}
+
+/**
+ * @brief This function handles FMPI2C error interrupt request.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ uint32_t itflags = READ_REG(hfmpi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hfmpi2c->Instance->CR1);
+
+ /* FMPI2C Bus error interrupt occurred ------------------------------------*/
+ if (((itflags & FMPI2C_FLAG_BERR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_BERR);
+ }
+
+ /* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if (((itflags & FMPI2C_FLAG_OVR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_OVR);
+ }
+
+ /* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/
+ if (((itflags & FMPI2C_FLAG_ARLO) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if ((hfmpi2c->ErrorCode & (HAL_FMPI2C_ERROR_BERR | HAL_FMPI2C_ERROR_OVR | HAL_FMPI2C_ERROR_ARLO)) != HAL_FMPI2C_ERROR_NONE)
+ {
+ FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MasterTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MasterRxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_SlaveTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_SlaveRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref FMPI2C_XFERDIRECTION
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_ListenCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MemTxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_MemRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FMPI2C error callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FMPI2C abort callback.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval None
+ */
+__weak void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPI2C_AbortCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @brief Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the FMPI2C handle state.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL state
+ */
+HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Return FMPI2C handle state */
+ return hfmpi2c->State;
+}
+
+/**
+ * @brief Returns the FMPI2C Master, Slave, Memory or no mode.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for FMPI2C module
+ * @retval HAL mode
+ */
+HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ return hfmpi2c->Mode;
+}
+
+/**
+* @brief Return the FMPI2C error code.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+* @retval FMPI2C Error Code
+*/
+uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ return hfmpi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ uint16_t devaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ /* Error callback will be send during stop flag treatment */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+
+ /* Flush TX register */
+ FMPI2C_Flush_TXDR(hfmpi2c);
+ }
+ else if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
+ {
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+ }
+ else if (((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+ }
+ else if (((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+ {
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ {
+ devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
+ {
+ FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ }
+ }
+ }
+ else
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
+ {
+ /* Call FMPI2C Master Sequential complete process */
+ FMPI2C_ITMasterSequentialCplt(hfmpi2c);
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
+ }
+ }
+ }
+ else if (((ITFlags & FMPI2C_FLAG_TC) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+ {
+ if (hfmpi2c->XferCount == 0U)
+ {
+ if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
+ {
+ /* Generate a stop condition in case of no transfer option */
+ if (hfmpi2c->XferOptions == FMPI2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call FMPI2C Master Sequential complete process */
+ FMPI2C_ITMasterSequentialCplt(hfmpi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TC flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
+ }
+ }
+
+ if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ {
+ /* Call FMPI2C Master complete process */
+ FMPI2C_ITMasterCplt(hfmpi2c, ITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ /* Process locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ {
+ /* Check that FMPI2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hfmpi2c->XferCount == 0U)
+ {
+ if (((hfmpi2c->XferOptions == FMPI2C_FIRST_AND_LAST_FRAME) || (hfmpi2c->XferOptions == FMPI2C_LAST_FRAME)) && \
+ (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN))
+ {
+ /* Call FMPI2C Listen complete process */
+ FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
+ }
+ else if ((hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Flush TX register */
+ FMPI2C_Flush_TXDR(hfmpi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call FMPI2C Slave Sequential complete process */
+ FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ }
+ else if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
+ {
+ if (hfmpi2c->XferCount > 0U)
+ {
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+ }
+
+ if ((hfmpi2c->XferCount == 0U) && \
+ (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME))
+ {
+ /* Call FMPI2C Slave Sequential complete process */
+ FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
+ }
+ }
+ else if (((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
+ {
+ FMPI2C_ITAddrCplt(hfmpi2c, ITFlags);
+ }
+ else if (((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Datas have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if (hfmpi2c->XferCount > 0U)
+ {
+ /* Write data to TXDR */
+ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->XferCount--;
+ hfmpi2c->XferSize--;
+ }
+ else
+ {
+ if ((hfmpi2c->XferOptions == FMPI2C_NEXT_FRAME) || (hfmpi2c->XferOptions == FMPI2C_FIRST_FRAME))
+ {
+ /* Last Byte is Transmitted */
+ /* Call FMPI2C Slave Sequential complete process */
+ FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
+ }
+ }
+ }
+
+ /* Check if STOPF is set */
+ if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ {
+ /* Call FMPI2C Slave complete process */
+ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ uint16_t devaddress = 0U;
+ uint32_t xfermode = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+
+ /* No need to generate STOP, it is automatically done */
+ /* But enable STOP interrupt, to treat it */
+ /* Error callback will be send during stop flag treatment */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
+
+ /* Flush TX register */
+ FMPI2C_Flush_TXDR(hfmpi2c);
+ }
+ else if (((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+ {
+ /* Disable TC interrupt */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_TCI);
+
+ if (hfmpi2c->XferCount != 0U)
+ {
+ /* Recover Slave address */
+ devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ /* Prepare the new XferSize to transfer */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
+
+ /* Set the new XferSize in Nbytes register */
+ FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+ {
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
+ }
+ }
+ else if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ {
+ /* Call FMPI2C Master complete process */
+ FMPI2C_ITMasterCplt(hfmpi2c, ITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+ /* Process locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ {
+ /* Check that FMPI2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+ /* So clear Flag NACKF only */
+ if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c) == 0U)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ }
+ else if (((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
+ {
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ }
+ else if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ {
+ /* Call FMPI2C Slave complete process */
+ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TCR flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TC flag is set */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief FMPI2C Address complete process callback.
+ * @param hfmpi2c FMPI2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
+{
+ uint8_t transferdirection = 0;
+ uint16_t slaveaddrcode = 0;
+ uint16_t ownadd1code = 0;
+ uint16_t ownadd2code = 0;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ITFlags);
+
+ /* In case of Listen state, need to inform upper layer of address match code event */
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+ {
+ transferdirection = FMPI2C_GET_DIR(hfmpi2c);
+ slaveaddrcode = FMPI2C_GET_ADDR_MATCH(hfmpi2c);
+ ownadd1code = FMPI2C_GET_OWN_ADDRESS1(hfmpi2c);
+ ownadd2code = FMPI2C_GET_OWN_ADDRESS2(hfmpi2c);
+
+ /* If 10bits addressing mode is selected */
+ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ {
+ if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+ {
+ slaveaddrcode = ownadd1code;
+ hfmpi2c->AddrEventCount++;
+ if (hfmpi2c->AddrEventCount == 2U)
+ {
+ /* Reset Address Event counter */
+ hfmpi2c->AddrEventCount = 0U;
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call Slave Addr callback */
+ HAL_FMPI2C_AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+ }
+ }
+ else
+ {
+ slaveaddrcode = ownadd2code;
+
+ /* Disable ADDR Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call Slave Addr callback */
+ HAL_FMPI2C_AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+ }
+ }
+ /* else 7 bits addressing mode is selected */
+ else
+ {
+ /* Disable ADDR Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call Slave Addr callback */
+ HAL_FMPI2C_AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+ }
+ }
+ /* Else clear address flag only */
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ }
+}
+
+/**
+ * @brief FMPI2C Master sequential complete process.
+ * @param hfmpi2c FMPI2C handle.
+ * @retval None
+ */
+static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Reset FMPI2C handle mode */
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when FMPI2C_AUTOEND_MODE enable */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_TX;
+ hfmpi2c->XferISR = NULL;
+
+ /* Disable Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+ }
+ /* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX */
+ else
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_RX;
+ hfmpi2c->XferISR = NULL;
+
+ /* Disable Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief FMPI2C Slave sequential complete process.
+ * @param hfmpi2c FMPI2C handle.
+ * @retval None
+ */
+static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* Reset FMPI2C handle mode */
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_TX;
+
+ /* Disable Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+ }
+
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_RX, keep only HAL_FMPI2C_STATE_LISTEN */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_RX;
+
+ /* Disable Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief FMPI2C Master complete process.
+ * @param hfmpi2c FMPI2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
+{
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Reset handle parameters */
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+ hfmpi2c->XferISR = NULL;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+
+ if ((ITFlags & FMPI2C_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Set acknowledge error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+
+ /* Flush TX register */
+ FMPI2C_Flush_TXDR(hfmpi2c);
+
+ /* Disable Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if ((hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) || (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
+ }
+ /* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX */
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
+ {
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+ }
+ }
+ /* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX */
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
+ {
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+ }
+ }
+}
+
+/**
+ * @brief FMPI2C Slave complete process.
+ * @param hfmpi2c FMPI2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
+{
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear ADDR flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+
+ /* Disable all interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
+
+ /* Disable Address Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ FMPI2C_RESET_CR2(hfmpi2c);
+
+ /* Flush TX register */
+ FMPI2C_Flush_TXDR(hfmpi2c);
+
+ /* If a DMA is ongoing, Update handle size context */
+ if (((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) ||
+ ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN))
+ {
+ hfmpi2c->XferCount = FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c);
+ }
+
+ /* All data are not transferred, so set error code accordingly */
+ if (hfmpi2c->XferCount != 0U)
+ {
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+
+ /* Store Last receive data if any */
+ if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+
+ if ((hfmpi2c->XferSize > 0U))
+ {
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ }
+
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+ hfmpi2c->XferISR = NULL;
+
+ if (hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
+ {
+ /* Call FMPI2C Listen complete process */
+ FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
+ }
+ }
+ else if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
+ {
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
+ }
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the Slave Rx Complete callback */
+ HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+ }
+ else
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the Slave Tx Complete callback */
+ HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief FMPI2C Listen complete process.
+ * @param hfmpi2c FMPI2C handle.
+ * @param ITFlags Interrupt flags to handle.
+ * @retval None
+ */
+static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
+{
+ /* Reset handle parameters */
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+ hfmpi2c->XferISR = NULL;
+
+ /* Store Last receive data if any */
+ if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+
+ if ((hfmpi2c->XferSize > 0U))
+ {
+ hfmpi2c->XferSize--;
+ hfmpi2c->XferCount--;
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+ }
+
+ /* Disable all Interrupts*/
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
+
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
+}
+
+/**
+ * @brief FMPI2C interrupts error process.
+ * @param hfmpi2c FMPI2C handle.
+ * @param ErrorCode Error code to handle.
+ * @retval None
+ */
+static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
+{
+ /* Reset handle parameters */
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+ hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+ hfmpi2c->XferCount = 0U;
+
+ /* Set new error code */
+ hfmpi2c->ErrorCode |= ErrorCode;
+
+ /* Disable Interrupts */
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) ||
+ (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) ||
+ (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
+ {
+ /* Disable all interrupts, except interrupts related to LISTEN state */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
+
+ /* keep HAL_FMPI2C_STATE_LISTEN if set */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
+ }
+ else
+ {
+ /* Disable all interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
+
+ /* If state is an abort treatment on goind, don't change state */
+ /* This change will be do later */
+ if (hfmpi2c->State != HAL_FMPI2C_STATE_ABORT)
+ {
+ /* Set HAL_FMPI2C_STATE_READY */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ }
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+ hfmpi2c->XferISR = NULL;
+ }
+
+ /* Abort DMA TX transfer if any */
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ /* Set the FMPI2C DMA Abort callback :
+ will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+ hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx);
+ }
+ }
+ /* Abort DMA RX transfer if any */
+ else if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* Set the FMPI2C DMA Abort callback :
+ will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+ hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hfmpi2c->hdmarx->XferAbortCallback function in case of error */
+ hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx);
+ }
+ }
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_FMPI2C_AbortCpltCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief FMPI2C Tx data register flush process.
+ * @param hfmpi2c FMPI2C handle.
+ * @retval None
+ */
+static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* If a pending TXIS flag is set */
+ /* Write a dummy data in TXDR to clear it */
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
+ {
+ hfmpi2c->Instance->TXDR = 0x00U;
+ }
+
+ /* Flush TX register if not empty */
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET)
+ {
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_TXE);
+ }
+}
+
+/**
+ * @brief DMA FMPI2C master transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ /* If last transfer, enable STOP interrupt */
+ if (hfmpi2c->XferCount == 0U)
+ {
+ /* Enable STOP interrupt */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
+ }
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
+ else
+ {
+ /* Update Buffer pointer */
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+
+ /* Set the XferSize to transfer */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ /* Enable the DMA stream */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Enable TC interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RELOAD_IT);
+ }
+}
+
+/**
+ * @brief DMA FMPI2C slave transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+}
+
+/**
+ * @brief DMA FMPI2C master receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* If last transfer, enable STOP interrupt */
+ if (hfmpi2c->XferCount == 0U)
+ {
+ /* Enable STOP interrupt */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
+ }
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
+ else
+ {
+ /* Update Buffer pointer */
+ hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+
+ /* Set the XferSize to transfer */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ }
+
+ /* Enable the DMA stream */
+ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
+
+ /* Enable TC interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RELOAD_IT);
+ }
+}
+
+/**
+ * @brief DMA FMPI2C slave receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+}
+
+/**
+ * @brief DMA FMPI2C communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA);
+}
+
+/**
+ * @brief DMA FMPI2C communication abort callback
+ * (To be called at end of DMA Abort procedure).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Reset AbortCpltCallback */
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
+ hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if come from abort from user */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_FMPI2C_AbortCpltCallback(hfmpi2c);
+ }
+ else
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_FMPI2C_ErrorCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Flag Specifies the FMPI2C flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout for specific usage of TXIS flag.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout for specific usage of STOP flag.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles FMPI2C Communication Timeout for specific usage of RXNE flag.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check if a STOPF is detected */
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ {
+ /* Check if an RXNE is pending */
+ /* Store Last receive data if any */
+ if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET) && (hfmpi2c->XferSize > 0U))
+ {
+ /* Return HAL_OK */
+ /* The Reading of data from RXDR will be done in caller function */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check for the Timeout */
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Acknowledge failed detection during an FMPI2C Communication.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
+ {
+ /* Wait until STOP Flag is reset */
+ /* AutoEnd should be initiate after AF */
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear NACKF Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Flush TX register */
+ FMPI2C_Flush_TXDR(hfmpi2c);
+
+ /* Clear Configuration Register 2 */
+ FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hfmpi2c FMPI2C handle.
+ * @param DevAddress Specifies the slave address to be programmed.
+ * @param Size Specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the FMPI2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPI2C_RELOAD_MODE Enable Reload mode .
+ * @arg @ref FMPI2C_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref FMPI2C_SOFTEND_MODE Enable Software end mode.
+ * @param Request New state of the FMPI2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPI2C_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref FMPI2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref FMPI2C_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref FMPI2C_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_TRANSFER_MODE(Mode));
+ assert_param(IS_TRANSFER_REQUEST(Request));
+
+ /* update CR2 register */
+ MODIFY_REG(hfmpi2c->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP)), \
+ (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+ * @brief Manage the enabling of Interrupts.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param InterruptRequest Value of @ref FMPI2C_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if ((hfmpi2c->XferISR == FMPI2C_Master_ISR_DMA) || \
+ (hfmpi2c->XferISR == FMPI2C_Slave_ISR_DMA))
+ {
+ if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
+ tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI;
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= FMPI2C_IT_STOPI;
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= FMPI2C_IT_TCI;
+ }
+ }
+ else
+ {
+ if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK, and ADDR interrupts */
+ tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI;
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI;
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= FMPI2C_IT_STOPI;
+ }
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of FMPI2C interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_FMPI2C_ENABLE_IT(hfmpi2c, tmpisr);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param InterruptRequest Value of @ref FMPI2C_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0U;
+
+ if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
+ {
+ /* Disable TC and TXI interrupts */
+ tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_TXI;
+
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
+ }
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
+ {
+ /* Disable TC and RXI interrupts */
+ tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_RXI;
+
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
+ }
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
+ {
+ /* Disable ADDR, NACK and STOP interrupts */
+ tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI;
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= FMPI2C_IT_STOPI;
+ }
+
+ if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= FMPI2C_IT_TCI;
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_FMPI2C_DISABLE_IT(hfmpi2c, tmpisr);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,713 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c.h
+ * @author MCD Application Team
+ * @brief Header file of FMPI2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FMPI2C_H
+#define __STM32F4xx_HAL_FMPI2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPI2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types
+ * @{
+ */
+
+/** @defgroup FMPI2C_Configuration_Structure_definition FMPI2C Configuration Structure definition
+ * @brief FMPI2C Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value.
+ This parameter calculated by referring to FMPI2C initialization
+ section in Reference manual */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref FMPI2C_ADDRESSING_MODE */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref FMPI2C_DUAL_ADDRESSING_MODE */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref FMPI2C_OWN_ADDRESS2_MASKS */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref FMPI2C_GENERAL_CALL_ADDRESSING_MODE */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */
+
+} FMPI2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+ * @brief HAL State structure definition
+ * @note HAL FMPI2C State value coding follow below described bitmap :\n
+ * b7-b6 Error information\n
+ * 00 : No Error\n
+ * 01 : Abort (Abort user request on going)\n
+ * 10 : Timeout\n
+ * 11 : Error\n
+ * b5 IP initilisation status\n
+ * 0 : Reset (IP not initialized)\n
+ * 1 : Init done (IP initialized and ready to use. HAL FMPI2C Init function called)\n
+ * b4 (not used)\n
+ * x : Should be set to 0\n
+ * b3\n
+ * 0 : Ready or Busy (No Listen mode ongoing)\n
+ * 1 : Listen (IP in Address Listen Mode)\n
+ * b2 Intrinsic process state\n
+ * 0 : Ready\n
+ * 1 : Busy (IP busy with some configuration or internal operations)\n
+ * b1 Rx state\n
+ * 0 : Ready (no Rx operation ongoing)\n
+ * 1 : Busy (Rx operation ongoing)\n
+ * b0 Tx state\n
+ * 0 : Ready (no Tx operation ongoing)\n
+ * 1 : Busy (Tx operation ongoing)
+ * @{
+ */
+typedef enum
+{
+ HAL_FMPI2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
+ HAL_FMPI2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
+ HAL_FMPI2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
+ HAL_FMPI2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
+ HAL_FMPI2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_FMPI2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
+ HAL_FMPI2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
+ process is ongoing */
+ HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
+ process is ongoing */
+ HAL_FMPI2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
+ HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
+ HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */
+
+} HAL_FMPI2C_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+ * @brief HAL Mode structure definition
+ * @note HAL FMPI2C Mode value coding follow below described bitmap :\n
+ * b7 (not used)\n
+ * x : Should be set to 0\n
+ * b6\n
+ * 0 : None\n
+ * 1 : Memory (HAL FMPI2C communication is in Memory Mode)\n
+ * b5\n
+ * 0 : None\n
+ * 1 : Slave (HAL FMPI2C communication is in Slave Mode)\n
+ * b4\n
+ * 0 : None\n
+ * 1 : Master (HAL FMPI2C communication is in Master Mode)\n
+ * b3-b2-b1-b0 (not used)\n
+ * xxxx : Should be set to 0000
+ * @{
+ */
+typedef enum
+{
+ HAL_FMPI2C_MODE_NONE = 0x00U, /*!< No FMPI2C communication on going */
+ HAL_FMPI2C_MODE_MASTER = 0x10U, /*!< FMPI2C communication is in Master Mode */
+ HAL_FMPI2C_MODE_SLAVE = 0x20U, /*!< FMPI2C communication is in Slave Mode */
+ HAL_FMPI2C_MODE_MEM = 0x40U /*!< FMPI2C communication is in Memory Mode */
+
+} HAL_FMPI2C_ModeTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Error_Code_definition FMPI2C Error Code definition
+ * @brief FMPI2C Error Code definition
+ * @{
+ */
+#define HAL_FMPI2C_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_FMPI2C_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_FMPI2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_FMPI2C_ERROR_AF (0x00000004U) /*!< ACKF error */
+#define HAL_FMPI2C_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_FMPI2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_FMPI2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
+#define HAL_FMPI2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_handle_Structure_definition FMPI2C handle Structure definition
+ * @brief FMPI2C handle Structure definition
+ * @{
+ */
+typedef struct __FMPI2C_HandleTypeDef
+{
+ FMPI2C_TypeDef *Instance; /*!< FMPI2C registers base address */
+
+ FMPI2C_InitTypeDef Init; /*!< FMPI2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */
+
+ uint16_t XferSize; /*!< FMPI2C transfer size */
+
+ __IO uint16_t XferCount; /*!< FMPI2C transfer counter */
+
+ __IO uint32_t XferOptions; /*!< FMPI2C sequantial transfer options, this parameter can
+ be a value of @ref FMPI2C_XFEROPTIONS */
+
+ __IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */
+
+ HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /*!< FMPI2C transfer IRQ handler function pointer */
+
+ DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< FMPI2C locking object */
+
+ __IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */
+
+ __IO HAL_FMPI2C_ModeTypeDef Mode; /*!< FMPI2C communication mode */
+
+ __IO uint32_t ErrorCode; /*!< FMPI2C Error code */
+
+ __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */
+} FMPI2C_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMPI2C_Exported_Constants FMPI2C Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPI2C_XFEROPTIONS FMPI2C Sequential Transfer Options
+ * @{
+ */
+#define FMPI2C_FIRST_FRAME ((uint32_t)FMPI2C_SOFTEND_MODE)
+#define FMPI2C_FIRST_AND_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
+#define FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
+#define FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
+#define FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
+#define FMPI2C_LAST_FRAME_NO_STOP ((uint32_t)FMPI2C_SOFTEND_MODE)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_ADDRESSING_MODE FMPI2C Addressing Mode
+ * @{
+ */
+#define FMPI2C_ADDRESSINGMODE_7BIT (0x00000001U)
+#define FMPI2C_ADDRESSINGMODE_10BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_DUAL_ADDRESSING_MODE FMPI2C Dual Addressing Mode
+ * @{
+ */
+#define FMPI2C_DUALADDRESS_DISABLE (0x00000000U)
+#define FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_OWN_ADDRESS2_MASKS FMPI2C Own Address2 Masks
+ * @{
+ */
+#define FMPI2C_OA2_NOMASK ((uint8_t)0x00)
+#define FMPI2C_OA2_MASK01 ((uint8_t)0x01)
+#define FMPI2C_OA2_MASK02 ((uint8_t)0x02)
+#define FMPI2C_OA2_MASK03 ((uint8_t)0x03)
+#define FMPI2C_OA2_MASK04 ((uint8_t)0x04)
+#define FMPI2C_OA2_MASK05 ((uint8_t)0x05)
+#define FMPI2C_OA2_MASK06 ((uint8_t)0x06)
+#define FMPI2C_OA2_MASK07 ((uint8_t)0x07)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_GENERAL_CALL_ADDRESSING_MODE FMPI2C General Call Addressing Mode
+ * @{
+ */
+#define FMPI2C_GENERALCALL_DISABLE (0x00000000U)
+#define FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_NOSTRETCH_MODE FMPI2C No-Stretch Mode
+ * @{
+ */
+#define FMPI2C_NOSTRETCH_DISABLE (0x00000000U)
+#define FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_MEMORY_ADDRESS_SIZE FMPI2C Memory Address Size
+ * @{
+ */
+#define FMPI2C_MEMADD_SIZE_8BIT (0x00000001U)
+#define FMPI2C_MEMADD_SIZE_16BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_XFERDIRECTION FMPI2C Transfer Direction Master Point of View
+ * @{
+ */
+#define FMPI2C_DIRECTION_TRANSMIT (0x00000000U)
+#define FMPI2C_DIRECTION_RECEIVE (0x00000001U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_RELOAD_END_MODE FMPI2C Reload End Mode
+ * @{
+ */
+#define FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD
+#define FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND
+#define FMPI2C_SOFTEND_MODE (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_START_STOP_MODE FMPI2C Start or Stop Mode
+ * @{
+ */
+#define FMPI2C_NO_STARTSTOP (0x00000000U)
+#define FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP)
+#define FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
+#define FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Interrupt_configuration_definition FMPI2C Interrupt configuration definition
+ * @brief FMPI2C Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE
+#define FMPI2C_IT_TCI FMPI2C_CR1_TCIE
+#define FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE
+#define FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE
+#define FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE
+#define FMPI2C_IT_RXI FMPI2C_CR1_RXIE
+#define FMPI2C_IT_TXI FMPI2C_CR1_TXIE
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition
+ * @{
+ */
+#define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE
+#define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS
+#define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE
+#define FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR
+#define FMPI2C_FLAG_AF FMPI2C_ISR_NACKF
+#define FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF
+#define FMPI2C_FLAG_TC FMPI2C_ISR_TC
+#define FMPI2C_FLAG_TCR FMPI2C_ISR_TCR
+#define FMPI2C_FLAG_BERR FMPI2C_ISR_BERR
+#define FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO
+#define FMPI2C_FLAG_OVR FMPI2C_ISR_OVR
+#define FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR
+#define FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
+#define FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT
+#define FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY
+#define FMPI2C_FLAG_DIR FMPI2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset FMPI2C handle state.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
+ * @retval None
+ */
+#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
+
+/** @brief Enable the specified FMPI2C interrupt.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPI2C_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPI2C_IT_RXI RX interrupt enable
+ * @arg @ref FMPI2C_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified FMPI2C interrupt.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPI2C_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPI2C_IT_RXI RX interrupt enable
+ * @arg @ref FMPI2C_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified FMPI2C interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
+ * @param __INTERRUPT__ specifies the FMPI2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPI2C_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPI2C_IT_RXI RX interrupt enable
+ * @arg @ref FMPI2C_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified FMPI2C flag is set or not.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPI2C_FLAG_TXE Transmit data register empty
+ * @arg @ref FMPI2C_FLAG_TXIS Transmit interrupt status
+ * @arg @ref FMPI2C_FLAG_RXNE Receive data register not empty
+ * @arg @ref FMPI2C_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref FMPI2C_FLAG_AF Acknowledge failure received flag
+ * @arg @ref FMPI2C_FLAG_STOPF STOP detection flag
+ * @arg @ref FMPI2C_FLAG_TC Transfer complete (master mode)
+ * @arg @ref FMPI2C_FLAG_TCR Transfer complete reload
+ * @arg @ref FMPI2C_FLAG_BERR Bus error
+ * @arg @ref FMPI2C_FLAG_ARLO Arbitration lost
+ * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun
+ * @arg @ref FMPI2C_FLAG_PECERR PEC error in reception
+ * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref FMPI2C_FLAG_ALERT SMBus alert
+ * @arg @ref FMPI2C_FLAG_BUSY Bus busy
+ * @arg @ref FMPI2C_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FMPI2C_FLAG_TXE Transmit data register empty
+ * @arg @ref FMPI2C_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref FMPI2C_FLAG_AF Acknowledge failure received flag
+ * @arg @ref FMPI2C_FLAG_STOPF STOP detection flag
+ * @arg @ref FMPI2C_FLAG_BERR Bus error
+ * @arg @ref FMPI2C_FLAG_ARLO Arbitration lost
+ * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun
+ * @arg @ref FMPI2C_FLAG_PECERR PEC error in reception
+ * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref FMPI2C_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief Enable the specified FMPI2C peripheral.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
+ * @retval None
+ */
+#define __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
+
+/** @brief Disable the specified FMPI2C peripheral.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
+ * @retval None
+ */
+#define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge FMPI2C peripheral in Slave mode.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
+ * @retval None
+ */
+#define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK))
+/**
+ * @}
+ */
+
+/* Include FMPI2C HAL Extended module */
+#include "stm32f4xx_hal_fmpi2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPI2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c);
+HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
+HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @{
+ */
+/* Peripheral State, Mode and Error functions *********************************/
+HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c);
+HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c);
+uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMPI2C_Private_Macro FMPI2C Private Macros
+ * @{
+ */
+
+#define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))
+
+#define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))
+
+#define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \
+ ((MASK) == FMPI2C_OA2_MASK01) || \
+ ((MASK) == FMPI2C_OA2_MASK02) || \
+ ((MASK) == FMPI2C_OA2_MASK03) || \
+ ((MASK) == FMPI2C_OA2_MASK04) || \
+ ((MASK) == FMPI2C_OA2_MASK05) || \
+ ((MASK) == FMPI2C_OA2_MASK06) || \
+ ((MASK) == FMPI2C_OA2_MASK07))
+
+#define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \
+ ((CALL) == FMPI2C_GENERALCALL_ENABLE))
+
+#define IS_FMPI2C_NO_STRETCH(STRETCH) (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))
+
+#define IS_FMPI2C_MEMADD_SIZE(SIZE) (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE) (((MODE) == FMPI2C_RELOAD_MODE) || \
+ ((MODE) == FMPI2C_AUTOEND_MODE) || \
+ ((MODE) == FMPI2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPI2C_GENERATE_STOP) || \
+ ((REQUEST) == FMPI2C_GENERATE_START_READ) || \
+ ((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \
+ ((REQUEST) == FMPI2C_NO_STARTSTOP))
+
+#define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_FIRST_FRAME) || \
+ ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \
+ ((REQUEST) == FMPI2C_NEXT_FRAME) || \
+ ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \
+ ((REQUEST) == FMPI2C_LAST_FRAME) || \
+ ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP))
+
+#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
+
+#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16)
+#define FMPI2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16)
+#define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
+#define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)
+#define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)
+
+#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
+#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8U)))
+#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f4xx_hal_fmpi2c.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_FMPI2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,254 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c_ex.c
+ * @author MCD Application Team
+ * @brief FMPI2C Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of FMPI2C Extended peripheral:
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FMPI2C peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the FMPI2C interface for STM32F4xx
+ devices contains the following additional features
+
+ (+) Possibility to disable or enable Analog Noise Filter
+ (+) Use of a configured Digital Noise Filter
+ (+) Disable or enable Fast Mode Plus
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+ (#) Configure FMPI2C Analog noise filter using the function HAL_FMPI2CEx_ConfigAnalogFilter()
+ (#) Configure FMPI2C Digital noise filter using the function HAL_FMPI2CEx_ConfigDigitalFilter()
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_FMPI2CEx_EnableFastModePlus()
+ (++) HAL_FMPI2CEx_DisableFastModePlus()
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMPI2CEx FMPI2CEx
+ * @brief FMPI2C Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup FMPI2CEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Noise Filters
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure FMPI2C Analog noise filter.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @param AnalogFilter New state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_FMPI2C_ANALOG_FILTER(AnalogFilter));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Reset FMPI2Cx ANOFF bit */
+ hfmpi2c->Instance->CR1 &= ~(FMPI2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hfmpi2c->Instance->CR1 |= AnalogFilter;
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure FMPI2C Digital noise filter.
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2Cx peripheral.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
+ assert_param(IS_FMPI2C_DIGITAL_FILTER(DigitalFilter));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
+
+ /* Disable the selected FMPI2C peripheral */
+ __HAL_FMPI2C_DISABLE(hfmpi2c);
+
+ /* Get the old register value */
+ tmpreg = hfmpi2c->Instance->CR1;
+
+ /* Reset FMPI2Cx DNF bits [11:8] */
+ tmpreg &= ~(FMPI2C_CR1_DFN);
+
+ /* Set FMPI2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << 8U;
+
+ /* Store the new register value */
+ hfmpi2c->Instance->CR1 = tmpreg;
+
+ __HAL_FMPI2C_ENABLE(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the FMPI2C fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref FMPI2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_FMPI2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the FMPI2C fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref FMPI2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_FMPI2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||\
+ STM32F413xx || STM32F423xx */
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,160 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpi2c_ex.h
+ * @author MCD Application Team
+ * @brief Header file of FMPI2C HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FMPI2C_EX_H
+#define __STM32F4xx_HAL_FMPI2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPI2CEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMPI2CEx_Exported_Constants FMPI2C Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPI2CEx_Analog_Filter FMPI2C Extended Analog Filter
+ * @{
+ */
+#define FMPI2C_ANALOGFILTER_ENABLE 0x00000000U
+#define FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2CEx_FastModePlus FMPI2C Extended Fast Mode Plus
+ * @{
+ */
+#define FMPI2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C1 SCL pins */
+#define FMPI2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C1 SDA pins */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup FMPI2CEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter);
+void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPI2CEx_Private_Constants FMPI2C Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMPI2CEx_Private_Macro FMPI2C Extended Private Macros
+ * @{
+ */
+#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
+
+#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+
+#define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
+ (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup FMPI2CEx_Private_Functions FMPI2C Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f4xx_hal_fmpi2c_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FMPI2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,545 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+ port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+ in several modes:
+ (+) Input mode
+ (+) Analog mode
+ (+) Output mode
+ (+) Alternate function mode
+ (+) External interrupt/event lines
+
+ [..]
+ During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ [..]
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ [..]
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ [..]
+ All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ [..]
+ The external interrupt/event controller consists of up to 23 edge detectors
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each
+ input line can be independently configured to select the type (interrupt or event)
+ and the corresponding trigger event (rising or falling or both). Each line can
+ also be masked independently.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+ structure.
+ (++) In case of Output or alternate function mode selection: the speed is
+ configured through "Speed" member from GPIO_InitTypeDef structure.
+ (++) In alternate mode is selection, the alternate function connected to the IO
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member from
+ GPIO_InitTypeDef structure select the type (interrupt or event) and
+ the corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+ HAL_NVIC_EnableIRQ().
+
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+#define GPIO_MODE 0x00000003U
+#define EXTI_MODE 0x10000000U
+#define GPIO_MODE_IT 0x00010000U
+#define GPIO_MODE_EVT 0x00020000U
+#define RISING_EDGE 0x00100000U
+#define FALLING_EDGE 0x00200000U
+#define GPIO_OUTPUT_TYPE 0x00000010U
+
+#define GPIO_NUMBER 16U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the GPIOs
+ to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+ * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ uint32_t position;
+ uint32_t ioposition = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t temp = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Configure the port pins */
+ for(position = 0U; position < GPIO_NUMBER; position++)
+ {
+ /* Get the IO position */
+ ioposition = 0x01U << position;
+ /* Get the current IO position */
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+
+ if(iocurrent == ioposition)
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameter */
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3U];
+ temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ GPIOx->AFR[position >> 3U] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ GPIOx->MODER = temp;
+
+ /* In case of Output or Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ temp |= (GPIO_Init->Speed << (position * 2U));
+ GPIOx->OSPEEDR = temp;
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ GPIOx->OTYPER = temp;
+ }
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ temp |= ((GPIO_Init->Pull) << (position * 2U));
+ GPIOx->PUPDR = temp;
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ {
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ temp = SYSCFG->EXTICR[position >> 2U];
+ temp &= ~(0x0FU << (4U * (position & 0x03U)));
+ temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
+ SYSCFG->EXTICR[position >> 2U] = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->IMR = temp;
+
+ temp = EXTI->EMR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->EMR = temp;
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->RTSR = temp;
+
+ temp = EXTI->FTSR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->FTSR = temp;
+ }
+ }
+ }
+}
+
+/**
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+ * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+ * @param GPIO_Pin specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t position;
+ uint32_t ioposition = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t tmp = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Configure the port pins */
+ for(position = 0U; position < GPIO_NUMBER; position++)
+ {
+ /* Get the IO position */
+ ioposition = 0x01U << position;
+ /* Get the current IO position */
+ iocurrent = (GPIO_Pin) & ioposition;
+
+ if(iocurrent == ioposition)
+ {
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floating Mode */
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ tmp = SYSCFG->EXTICR[position >> 2U];
+ tmp &= (0x0FU << (4U * (position & 0x03U)));
+ if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
+ {
+ /* Configure the External Interrupt or event for the current IO */
+ tmp = 0x0FU << (4U * (position & 0x03U));
+ SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~((uint32_t)iocurrent);
+ EXTI->EMR &= ~((uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
+ EXTI->FTSR &= ~((uint32_t)iocurrent);
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @brief GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+ * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+ * @param GPIO_Pin specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+ {
+ bitstatus = GPIO_PIN_SET;
+ }
+ else
+ {
+ bitstatus = GPIO_PIN_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ *
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ *
+ * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+ * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+ * @param GPIO_Pin specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @param PinState specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if(PinState != GPIO_PIN_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
+ }
+}
+
+/**
+ * @brief Toggles the specified GPIO pins.
+ * @param GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+ * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+ * @param GPIO_Pin Specifies the pins to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family
+ * @param GPIO_Pin specifies the port bit to be locked.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ tmp |= GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief This function handles EXTI interrupt request.
+ * @param GPIO_Pin Specifies the pins connected EXTI line
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ /* EXTI line interrupt detected */
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ {
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line detection callbacks.
+ * @param GPIO_Pin Specifies the pins connected EXTI line
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,325 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_H
+#define __STM32F4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode_define */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull_define */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed_define */
+
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
+ This parameter can be a value of @ref GPIO_Alternate_function_selection */
+}GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0,
+ GPIO_PIN_SET
+}GPIO_PinState;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define GPIO pins define
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode_define GPIO mode define
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
+
+#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed_define GPIO speed define
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
+/**
+ * @}
+ */
+
+ /** @defgroup GPIO_pull_define GPIO pull define
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
+#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__ specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__ specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param __EXTI_LINE__ specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__ specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extension module */
+#include "stm32f4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+ ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1591 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_EX_H
+#define __STM32F4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+ * @{
+ */
+
+/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/
+#if defined(STM32F429xx) || defined(STM32F439xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+/** @brief GPIO_Legacy
+ */
+#define GPIO_AF5_I2S3ext GPIO_AF5_SPI3 /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F427xx || STM32F437xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
+#if defined(STM32F407xx) || defined(STM32F417xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F407xx || STM32F417xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F405xx || STM32F415xx */
+
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
+#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
+
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F401xC || STM32F401xE */
+/*----------------------------------------------------------------------------*/
+
+/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */
+#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
+#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
+#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
+#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */
+#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */
+#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
+#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
+#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF10_DFSDM2 ((uint8_t)0x0A) /* DFSDM2 Alternate Function mapping */
+#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */
+#define GPIO_AF10_FSMC ((uint8_t)0x0A) /* FSMC Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */
+#define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */
+#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
+#define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */
+#define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F413xx || STM32F423xx */
+
+/*---------------------------------------- STM32F411xx------------------------*/
+#if defined(STM32F411xE)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */
+#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
+#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F411xE */
+
+/*---------------------------------------- STM32F410xx------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#if defined(STM32F410Cx) || defined(STM32F410Rx)
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#endif /* STM32F410Cx || STM32F410Rx */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */
+#if defined(STM32F410Cx) || defined(STM32F410Rx)
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */
+#endif /* STM32F410Cx || STM32F410Rx */
+#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
+#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*---------------------------------------- STM32F446xx -----------------------*/
+#if defined(STM32F446xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
+#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */
+#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
+#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */
+#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+ * @{
+ */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U :\
+ ((__GPIOx__) == (GPIOH))? 7U : 8U)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U :\
+ ((__GPIOx__) == (GPIOH))? 7U :\
+ ((__GPIOx__) == (GPIOI))? 8U :\
+ ((__GPIOx__) == (GPIOJ))? 9U : 10U)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U : 7U)
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U : 7U)
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F446xx) || defined(STM32F412Zx) ||defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U : 7U)
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+ * @{
+ */
+/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
+#if defined(STM32F429xx) || defined(STM32F439xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
+ ((AF) == GPIO_AF14_LTDC))
+
+#endif /* STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1))
+
+#endif /* STM32F427xx || STM32F437xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
+#if defined(STM32F407xx) || defined(STM32F417xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F407xx || STM32F417xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \
+ ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F405xx || STM32F415xx */
+
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \
+ ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
+ ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F401xC || STM32F401xE */
+/*----------------------------------------------------------------------------*/
+/*---------------------------------------- STM32F410xx------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_GPIO_AF(AF) (((AF) < 10U) || ((AF) == 15U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*---------------------------------------- STM32F411xx------------------------*/
+#if defined(STM32F411xE)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \
+ ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI4) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF6_SPI5) || ((AF) == GPIO_AF7_SPI3) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
+ ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F411xE */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------- STM32F446xx ----------------*/
+#if defined(STM32F446xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI2) || \
+ ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF7_UART5) || \
+ ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_SPI3) || \
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF9_QSPI) || \
+ ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QSPI))
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------------------- STM32F469xx/STM32F479xx --------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
+ ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI) || \
+ ((AF) == GPIO_AF9_QSPI) || ((AF) == GPIO_AF10_QSPI))
+
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------STM32F413xx/STM32F423xx-----------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 13U))
+#endif /* STM32F413xx || STM32F423xx */
+/*----------------------------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1868 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hash.c
+ * @author MCD Application Team
+ * @brief HASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the HASH peripheral:
+ * + Initialization and de-initialization functions
+ * + HASH/HMAC Processing functions by algorithm using polling mode
+ * + HASH/HMAC functions by algorithm using interrupt mode
+ * + HASH/HMAC functions by algorithm using DMA mode
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The HASH HAL driver can be used as follows:
+ (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
+ (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
+ (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
+ (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
+ (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++) Configure and enable one DMA stream one for managing data transfer from
+ memory to peripheral (input stream). Managing data transfer from
+ peripheral to memory can be performed only using CPU
+ (+++) Associate the initialized DMA handle to the HASH DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+ (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
+ (##) For HMAC, the encryption key.
+ (##) For HMAC, the key size used for encryption.
+ (#)Three processing functions are available:
+ (##) Polling mode: processing APIs are blocking functions
+ i.e. they process the data and wait till the digest computation is finished
+ e.g. HAL_HASH_SHA1_Start()
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+ i.e. they process the data under interrupt
+ e.g. HAL_HASH_SHA1_Start_IT()
+ (##) DMA mode: processing APIs are not blocking functions and the CPU is
+ not used for data transfer i.e. the data transfer is ensured by DMA
+ e.g. HAL_HASH_SHA1_Start_DMA()
+ (#)When the processing function is called at first time after HAL_HASH_Init()
+ the HASH peripheral is initialized and processes the buffer in input.
+ After that, the digest computation is started.
+ When processing multi-buffer use the accumulate function to write the
+ data in the peripheral without starting the digest computation. In last
+ buffer use the start function to input the last buffer ans start the digest
+ computation.
+ (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
+ (##) write (n-1)th data buffer in the peripheral without starting the digest computation
+ (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
+ (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
+ (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
+ After that, call the finish function in order to get the digest value
+ e.g. HAL_HASH_SHA1_Finish()
+ (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HASH HASH
+ * @brief HASH HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup HASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA HASH Input Data complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t inputaddr = 0U;
+ uint32_t buffersize = 0U;
+
+ if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
+ {
+ /* Disable the DMA transfer */
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ else
+ {
+ /* Increment Interrupt counter */
+ hhash->HashInCount++;
+ /* Disable the DMA transfer before starting the next transfer */
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+
+ if(hhash->HashInCount <= 2U)
+ {
+ /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
+ if(hhash->HashInCount == 1U)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ buffersize = hhash->HashBuffSize;
+ }
+ /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
+ else if(hhash->HashInCount == 2U)
+ {
+ inputaddr = (uint32_t)hhash->Init.pKey;
+ buffersize = hhash->Init.KeySize;
+ }
+ /* Configure the number of valid bits in last word of the message */
+ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * (buffersize % 4U));
+
+ /* Set the HASH DMA transfer complete */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4U ? (buffersize+3U)/4U:buffersize/4U));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+ }
+ else
+ {
+ /* Disable the DMA transfer */
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+
+ /* Reset the InCount */
+ hhash->HashInCount = 0U;
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ }
+}
+
+/**
+ * @brief DMA HASH communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hhash->State= HAL_HASH_STATE_READY;
+ HAL_HASH_ErrorCallback(hhash);
+}
+
+/**
+ * @brief Writes the input buffer in data register.
+ * @param pInBuffer Pointer to input buffer
+ * @param Size The size of input buffer
+ * @retval None
+ */
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t buffercounter;
+
+ for(buffercounter = 0U; buffercounter < Size; buffercounter+=4)
+ {
+ uint32_t data = (uint32_t) *pInBuffer++;
+ data |= (uint32_t) *pInBuffer++ << 8;
+ data |= (uint32_t) *pInBuffer++ << 16;
+ data |= (uint32_t) *pInBuffer++ << 24;
+ HASH->DIN = data;
+ }
+}
+
+/**
+ * @brief Provides the message digest result.
+ * @param pMsgDigest Pointer to the message digest
+ * @param Size The size of the message digest in bytes
+ * @retval None
+ */
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+ uint32_t msgdigest = (uint32_t)pMsgDigest;
+
+ switch(Size)
+ {
+ case 16U:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
+ break;
+ case 20U:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
+ break;
+ case 28U:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
+ break;
+ case 32U:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7U]);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HASH_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the HASH according to the specified parameters
+ in the HASH_InitTypeDef and creates the associated handle.
+ (+) DeInitialize the HASH peripheral.
+ (+) Initialize the HASH MSP.
+ (+) DeInitialize HASH MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH according to the specified parameters in the
+ HASH_HandleTypeDef and creates the associated handle.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
+{
+ /* Check the hash handle allocation */
+ if(hhash == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+
+ if(hhash->State == HAL_HASH_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hhash->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_HASH_MspInit(hhash);
+ }
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Reset HashInCount, HashBuffSize and HashITCounter */
+ hhash->HashInCount = 0U;
+ hhash->HashBuffSize = 0U;
+ hhash->HashITCounter = 0U;
+
+ /* Set the data type */
+ HASH->CR |= (uint32_t) (hhash->Init.DataType);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Set the default HASH phase */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the HASH peripheral.
+ * @note This API must be called before starting a new processing.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
+{
+ /* Check the HASH handle allocation */
+ if(hhash == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Set the default HASH phase */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
+ /* Reset HashInCount, HashBuffSize and HashITCounter */
+ hhash->HashInCount = 0U;
+ hhash->HashBuffSize = 0U;
+ hhash->HashITCounter = 0U;
+
+ /* DeInit the low level hardware */
+ HAL_HASH_MspDeInit(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH MSP.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes HASH MSP.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input data transfer complete callback.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_InCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Data transfer Error callback.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Digest computation complete callback. It is used only with interrupt.
+ * @note This callback is not relevant with DMA.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_HASH_DgstCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
+ * @brief processing functions using polling mode
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using polling mode functions#####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
+ The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is multiple of 64 bytes, appending the input buffer is possible.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware
+ * and appending the input buffer is no more possible.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 16U);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is multiple of 64 bytes, appending the input buffer is possible.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware
+ * and appending the input buffer is no more possible.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+ The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 20U);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
+ * @brief processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using interrupt mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
+ * The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+ uint32_t buffercounter;
+ uint32_t inputcounter;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ if(hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ hhash->HashInCount = Size;
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->pHashOutBuffPtr = pOutBuffer;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode */
+ HASH->CR |= HASH_ALGOSELECTION_MD5;
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0U;
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
+
+ if(hhash->HashInCount == 0U)
+ {
+ /* Disable Interrupts */
+ HASH->IMR = 0U;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete callback */
+ HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ if(hhash->HashInCount >= 68U)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ if(hhash->HashITCounter == 0U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+
+ if(hhash->HashInCount >= 68U)
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 68U;
+ hhash->pHashInBuffPtr+= 68U;
+ }
+ else
+ {
+ hhash->HashInCount = 0U;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
+ }
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1U;
+ }
+ else
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 64U;
+ hhash->pHashInBuffPtr+= 64U;
+ }
+ }
+ else
+ {
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ HASH->IMR &= ~(HASH_IT_DINI);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+
+ if((inputcounter > 4U) && (inputcounter%4U))
+ {
+ inputcounter = (inputcounter+4U-inputcounter%4U);
+ }
+ else if ((inputcounter < 4U) && (inputcounter != 0U))
+ {
+ inputcounter = 4U;
+ }
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Reset buffer counter */
+ hhash->HashInCount = 0U;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+ * The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+ uint32_t buffercounter;
+ uint32_t inputcounter;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ if(hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ hhash->HashInCount = Size;
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->pHashOutBuffPtr = pOutBuffer;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode */
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0U;
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
+ /* Read the Output block from the Output FIFO */
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
+ outputaddr+=4U;
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[4U]);
+ if(hhash->HashInCount == 0U)
+ {
+ /* Disable Interrupts */
+ HASH->IMR = 0U;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete callback */
+ HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ if(hhash->HashInCount >= 68U)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ if(hhash->HashITCounter == 0U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ if(hhash->HashInCount >= 68U)
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 68U;
+ hhash->pHashInBuffPtr+= 68U;
+ }
+ else
+ {
+ hhash->HashInCount = 0U;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
+ }
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1U;
+ }
+ else
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 64U;
+ hhash->pHashInBuffPtr+= 64U;
+ }
+ }
+ else
+ {
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ HASH->IMR &= ~(HASH_IT_DINI);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+
+ if((inputcounter > 4U) && (inputcounter%4U))
+ {
+ inputcounter = (inputcounter+4U-inputcounter%4U);
+ }
+ else if ((inputcounter < 4U) && (inputcounter != 0U))
+ {
+ inputcounter = 4U;
+ }
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Reset buffer counter */
+ hhash->HashInCount = 0U;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles HASH interrupt request.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+ switch(HASH->CR & HASH_CR_ALGO)
+ {
+ case HASH_ALGOSELECTION_MD5:
+ HAL_HASH_MD5_Start_IT(hhash, NULL, 0U, NULL);
+ break;
+
+ case HASH_ALGOSELECTION_SHA1:
+ HAL_HASH_SHA1_Start_IT(hhash, NULL, 0U, NULL);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
+ * @brief processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using DMA mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
+ control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = (uint32_t)pInBuffer;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ }
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the computed digest in MD5 mode
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 16U);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
+ control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = (uint32_t)pInBuffer;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the computed digest in SHA1 mode.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 20U);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process UnLock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
+ * @brief HMAC processing functions using polling mode .
+ *
+@verbatim
+ ===============================================================================
+ ##### HMAC processing using polling mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC MD5 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64U)
+ {
+ /* Select the HMAC MD5 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC MD5 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /************************** STEP 1 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 2 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 3 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 16U);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA1 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64U)
+ {
+ /* Select the HMAC SHA1 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC SHA1 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /************************** STEP 1 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 2 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 3 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, 20U);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
+ * @brief HMAC processing functions using DMA mode .
+ *
+@verbatim
+ ===============================================================================
+ ##### HMAC processing using DMA mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (+) SHA1
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC MD5 mode
+ * then enables DMA to control data transfer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Save buffer pointer and size in handle */
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->HashBuffSize = Size;
+ hhash->HashInCount = 0U;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64U)
+ {
+ /* Select the HMAC MD5 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC MD5 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Get the key address */
+ inputaddr = (uint32_t)(hhash->Init.pKey);
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA1 mode
+ * then enables DMA to control data transfer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Save buffer pointer and size in handle */
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->HashBuffSize = Size;
+ hhash->HashInCount = 0U;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64U)
+ {
+ /* Select the HMAC SHA1 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC SHA1 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Get the key address */
+ inputaddr = (uint32_t)(hhash->Init.pKey);
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the HASH state
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval HAL state
+ */
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+{
+ return hhash->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
+#endif /* HAL_HASH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,449 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hash.h
+ * @author MCD Application Team
+ * @brief Header file of HASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HASH_H
+#define __STM32F4xx_HAL_HASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HASH
+ * @brief HASH HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HASH_Exported_Types HASH Exported Types
+ * @{
+ */
+
+/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref HASH_Data_Type */
+
+ uint32_t KeySize; /*!< The key size is used only in HMAC operation */
+
+ uint8_t* pKey; /*!< The key is used only in HMAC operation */
+}HASH_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
+ * @{
+ */
+
+typedef enum
+{
+ HAL_HASH_STATE_RESET = 0x00U, /*!< HASH not yet initialized or disabled */
+ HAL_HASH_STATE_READY = 0x01U, /*!< HASH initialized and ready for use */
+ HAL_HASH_STATE_BUSY = 0x02U, /*!< HASH internal process is ongoing */
+ HAL_HASH_STATE_TIMEOUT = 0x03U, /*!< HASH timeout state */
+ HAL_HASH_STATE_ERROR = 0x04U /*!< HASH error state */
+}HAL_HASH_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
+ * @{
+ */
+
+typedef enum
+{
+ HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready for initialization */
+ HAL_HASH_PHASE_PROCESS = 0x02U /*!< HASH peripheral is in processing phase */
+}HAL_HASH_PhaseTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
+ * @{
+ */
+
+typedef struct
+{
+ HASH_InitTypeDef Init; /*!< HASH required parameters */
+
+ uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
+
+ uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
+
+ __IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
+
+ __IO uint32_t HashInCount; /*!< Counter of inputed data */
+
+ __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
+
+ HAL_StatusTypeDef Status; /*!< HASH peripheral status */
+
+ HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< HASH locking object */
+
+ __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
+} HASH_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HASH_Exported_Constants HASH Exported Constants
+ * @{
+ */
+
+/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
+ * @{
+ */
+#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
+#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
+#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
+#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
+ * @{
+ */
+#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */
+#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Data_Type HASH Data Type
+ * @{
+ */
+#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */
+#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
+#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
+#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
+ * @brief HASH HMAC Long key used only for HMAC mode
+ * @{
+ */
+#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
+ * @{
+ */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
+ * @{
+ */
+#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HASH_Exported_Macros HASH Exported Macros
+ * @{
+ */
+
+/** @brief Reset HASH handle state
+ * @param __HANDLE__ specifies the HASH handle.
+ * @retval None
+ */
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+
+/** @brief Check whether the specified HASH flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
+ * @arg HASH_FLAG_DCIS: Digest calculation complete
+ * @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
+ * @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
+ * @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)))
+
+/**
+ * @brief Enable the multiple DMA mode.
+ * This feature is available only in STM32F429x and STM32F439x devices.
+ * @retval None
+ */
+#define __HAL_HASH_SET_MDMAT() HASH->CR |= HASH_CR_MDMAT
+
+/**
+ * @brief Disable the multiple DMA mode.
+ * @retval None
+ */
+#define __HAL_HASH_RESET_MDMAT() HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
+
+/**
+ * @brief Start the digest computation
+ * @retval None
+ */
+#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
+
+/**
+ * @brief Set the number of valid bits in last word written in Data register
+ * @param SIZE size in byte of last data written in Data register.
+ * @retval None
+*/
+#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
+ HASH->STR |= 8U * ((SIZE) % 4U);\
+ }while(0)
+
+/**
+ * @}
+ */
+
+/* Include HASH HAL Extension module */
+#include "stm32f4xx_hal_hash_ex.h"
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
+ * @{
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group4
+ * @{
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group5
+ * @{
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group6
+ * @{
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group7
+ * @{
+ */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
+
+/** @addtogroup HASH_Exported_Functions_Group8
+ * @{
+ */
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+ /* Private types -------------------------------------------------------------*/
+/** @defgroup HASH_Private_Types HASH Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Variables HASH Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Constants HASH Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros HASH Private Macros
+ * @{
+ */
+#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1) || \
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
+
+
+#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
+ ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
+
+
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+ ((__DATATYPE__) == HASH_DATATYPE_1B))
+
+
+#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
+ ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
+
+#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4U) != 0U)? 0U: 1U)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_HASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1638 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hash_ex.c
+ * @author MCD Application Team
+ * @brief HASH HAL Extension module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of HASH peripheral:
+ * + Extended HASH processing functions based on SHA224 Algorithm
+ * + Extended HASH processing functions based on SHA256 Algorithm
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The HASH HAL driver can be used as follows:
+ (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
+ (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
+ (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
+ (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
+ (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++) Configure and enable one DMA stream one for managing data transfer from
+ memory to peripheral (input stream). Managing data transfer from
+ peripheral to memory can be performed only using CPU
+ (+++) Associate the initialized DMA handle to the HASH DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+ (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
+ (##) For HMAC, the encryption key.
+ (##) For HMAC, the key size used for encryption.
+ (#)Three processing functions are available:
+ (##) Polling mode: processing APIs are blocking functions
+ i.e. they process the data and wait till the digest computation is finished
+ e.g. HAL_HASHEx_SHA224_Start()
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+ i.e. they process the data under interrupt
+ e.g. HAL_HASHEx_SHA224_Start_IT()
+ (##) DMA mode: processing APIs are not blocking functions and the CPU is
+ not used for data transfer i.e. the data transfer is ensured by DMA
+ e.g. HAL_HASHEx_SHA224_Start_DMA()
+ (#)When the processing function is called at first time after HAL_HASH_Init()
+ the HASH peripheral is initialized and processes the buffer in input.
+ After that, the digest computation is started.
+ When processing multi-buffer use the accumulate function to write the
+ data in the peripheral without starting the digest computation. In last
+ buffer use the start function to input the last buffer ans start the digest
+ computation.
+ (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
+ (##) write (n-1)th data buffer in the peripheral without starting the digest computation
+ (##) HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation
+ (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
+ (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().
+ After that, call the finish function in order to get the digest value
+ e.g. HAL_HASHEx_SHA224_Finish()
+ (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HASHEx HASHEx
+ * @brief HASH Extension HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+
+#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup HASHEx_Private_Functions
+ * @{
+ */
+static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);
+static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup HASHEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Writes the input buffer in data register.
+ * @param pInBuffer Pointer to input buffer
+ * @param Size The size of input buffer
+ * @retval None
+ */
+static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t buffercounter;
+
+ for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
+ {
+ uint32_t data = (uint32_t) *pInBuffer++;
+ data |= (uint32_t) *pInBuffer++ << 8;
+ data |= (uint32_t) *pInBuffer++ << 16;
+ data |= (uint32_t) *pInBuffer++ << 24;
+ HASH->DIN = data;
+ }
+}
+
+/**
+ * @brief Provides the message digest result.
+ * @param pMsgDigest Pointer to the message digest
+ * @param Size The size of the message digest in bytes
+ * @retval None
+ */
+static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+ uint32_t msgdigest = (uint32_t)pMsgDigest;
+
+ switch(Size)
+ {
+ case 16U:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
+ break;
+ case 20U:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
+ break;
+ case 28U:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
+ break;
+ case 32U:
+ /* Read the message digest */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7U]);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief DMA HASH Input Data complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t inputaddr = 0U;
+ uint32_t buffersize = 0U;
+
+ if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
+ {
+ /* Disable the DMA transfer */
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ else
+ {
+ /* Increment Interrupt counter */
+ hhash->HashInCount++;
+ /* Disable the DMA transfer before starting the next transfer */
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+
+ if(hhash->HashInCount <= 2U)
+ {
+ /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
+ if(hhash->HashInCount == 1U)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ buffersize = hhash->HashBuffSize;
+ }
+ /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
+ else if(hhash->HashInCount == 2U)
+ {
+ inputaddr = (uint32_t)hhash->Init.pKey;
+ buffersize = hhash->Init.KeySize;
+ }
+ /* Configure the number of valid bits in last word of the message */
+ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * (buffersize % 4U));
+
+ /* Set the HASH DMA transfer complete */
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4U ? (buffersize+3U)/4U:buffersize/4U));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+ }
+ else
+ {
+ /* Disable the DMA transfer */
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+
+ /* Reset the InCount */
+ hhash->HashInCount = 0U;
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ }
+}
+
+/**
+ * @brief DMA HASH communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hhash->State= HAL_HASH_STATE_READY;
+ HAL_HASH_ErrorCallback(hhash);
+}
+
+ /**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HASHEx_Exported_Functions
+ * @{
+ */
+
+/** @defgroup HASHEx_Group1 HASH processing functions
+ * @brief processing functions using polling mode
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using polling mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in SHA224 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 28U);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
+ The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 32U);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the HASH peripheral in SHA224 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
+ The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode
+ * @brief HMAC processing functions using polling mode .
+ *
+@verbatim
+ ===============================================================================
+ ##### HMAC processing using polling mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the HMAC value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA224 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64U)
+ {
+ /* Select the HMAC SHA224 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC SHA224 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /************************** STEP 1 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 2 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 3 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 28U);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA256 mode
+ * then processes pInBuffer. The digest is available in pOutBuffer
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64U)
+ {
+ /* Select the HMAC SHA256 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
+ }
+ else
+ {
+ /* Select the HMAC SHA256 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
+ }
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /************************** STEP 1 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 2 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(pInBuffer, Size);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /************************** STEP 3 ******************************************/
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in data register */
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 32U);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode
+ * @brief processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using interrupt functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
+ * The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ uint32_t inputaddr;
+ uint32_t buffercounter;
+ uint32_t inputcounter;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ if(hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ hhash->HashInCount = Size;
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->pHashOutBuffPtr = pOutBuffer;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA224 mode */
+ HASH->CR |= HASH_ALGOSELECTION_SHA224;
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0U;
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ /* Read the message digest */
+ HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28U);
+ if(hhash->HashInCount == 0U)
+ {
+ /* Disable Interrupts */
+ HASH->IMR = 0U;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete callback */
+ HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ if(hhash->HashInCount >= 68U)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ if(hhash->HashITCounter == 0U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+
+ if(hhash->HashInCount >= 68U)
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 68U;
+ hhash->pHashInBuffPtr+= 68U;
+ }
+ else
+ {
+ hhash->HashInCount = 0U;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
+ }
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1U;
+ }
+ else
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 64U;
+ hhash->pHashInBuffPtr+= 64U;
+ }
+ }
+ else
+ {
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ HASH->IMR &= ~(HASH_IT_DINI);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+
+ if((inputcounter > 4U) && (inputcounter%4U))
+ {
+ inputcounter = (inputcounter+4U-inputcounter%4U);
+ }
+ else if ((inputcounter < 4U) && (inputcounter != 0U))
+ {
+ inputcounter = 4U;
+ }
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Reset buffer counter */
+ hhash->HashInCount = 0U;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
+ * The digest is available in pOutBuffer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ uint32_t inputaddr;
+ uint32_t buffercounter;
+ uint32_t inputcounter;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ if(hhash->State == HAL_HASH_STATE_READY)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ hhash->HashInCount = Size;
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->pHashOutBuffPtr = pOutBuffer;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA256 mode */
+ HASH->CR |= HASH_ALGOSELECTION_SHA256;
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0U;
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ /* Read the message digest */
+ HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32U);
+ if(hhash->HashInCount == 0U)
+ {
+ /* Disable Interrupts */
+ HASH->IMR = 0U;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete callback */
+ HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ }
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ if(hhash->HashInCount >= 68U)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ if(hhash->HashITCounter == 0U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+
+ if(hhash->HashInCount >= 68U)
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 68U;
+ hhash->pHashInBuffPtr+= 68U;
+ }
+ else
+ {
+ hhash->HashInCount = 0U;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
+ }
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1U;
+ }
+ else
+ {
+ /* Decrement buffer counter */
+ hhash->HashInCount -= 64U;
+ hhash->pHashInBuffPtr+= 64U;
+ }
+ }
+ else
+ {
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ HASH->IMR &= ~(HASH_IT_DINI);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+
+ if((inputcounter > 4U) && (inputcounter%4U))
+ {
+ inputcounter = (inputcounter+4U-inputcounter%4U);
+ }
+ else if ((inputcounter < 4U) && (inputcounter != 0U))
+ {
+ inputcounter = 4U;
+ }
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ /* Start the digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Reset buffer counter */
+ hhash->HashInCount = 0U;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles HASH interrupt request.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @retval None
+ */
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+ switch(HASH->CR & HASH_CR_ALGO)
+ {
+
+ case HASH_ALGOSELECTION_SHA224:
+ HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0U, NULL);
+ break;
+
+ case HASH_ALGOSELECTION_SHA256:
+ HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0U, NULL);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode
+ * @brief processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### HASH processing using DMA functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
+ control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = (uint32_t)pInBuffer;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
+ }
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the computed digest in SHA224
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 28U);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
+ control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr = (uint32_t)pInBuffer;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
+ }
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
+
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process UnLock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the computed digest in SHA256.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Change state */
+ hhash->State = HAL_HASH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Read the message digest */
+ HASHEx_GetDigest(pOutBuffer, 32U);
+
+ /* Change HASH peripheral state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode
+ * @brief HMAC processing functions using DMA mode .
+ *
+@verbatim
+ ===============================================================================
+ ##### HMAC processing using DMA functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the HMAC value using one of the following algorithms:
+ (+) SHA224
+ (+) SHA256
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA224 mode
+ * then enables DMA to control data transfer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Save buffer pointer and size in handle */
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->HashBuffSize = Size;
+ hhash->HashInCount = 0U;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64U)
+ {
+ /* Select the HMAC SHA224 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ /* Select the HMAC SHA224 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Get the key address */
+ inputaddr = (uint32_t)(hhash->Init.pKey);
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HASH peripheral in HMAC SHA256 mode
+ * then enables DMA to control data transfer.
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t inputaddr;
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Save buffer pointer and size in handle */
+ hhash->pHashInBuffPtr = pInBuffer;
+ hhash->HashBuffSize = Size;
+ hhash->HashInCount = 0U;
+
+ /* Check if initialization phase has already been performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is greater than 64 bytes */
+ if(hhash->Init.KeySize > 64U)
+ {
+ /* Select the HMAC SHA256 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
+ }
+ else
+ {
+ /* Select the HMAC SHA256 mode */
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
+ }
+ /* Reset the HASH processor core, so that the HASH will be ready to compute
+ the message digest of a new message */
+ HASH->CR |= HASH_CR_INIT;
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Get the key address */
+ inputaddr = (uint32_t)(hhash->Init.pKey);
+
+ /* Set the HASH DMA transfer complete callback */
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
+ /* Enable DMA requests */
+ HASH->CR |= (HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+
+#endif /* HAL_HASH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,198 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hash_ex.h
+ * @author MCD Application Team
+ * @brief Header file of HASH HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HASH_EX_H
+#define __STM32F4xx_HAL_HASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HASHEx
+ * @brief HASHEx HAL Extension module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+/**
+ * @}
+ */
+
+/** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions
+ * @{
+ */
+
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+ /* Private types -------------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Types HASHEx Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Variables HASHEx Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Constants HASHEx Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Macros HASHEx Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup HASHEx_Private_Functions HASHEx Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_HASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1271 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hcd.c
+ * @author MCD Application Team
+ * @brief HCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#)Declare a HCD_HandleTypeDef handle structure, for example:
+ HCD_HandleTypeDef hhcd;
+
+ (#)Fill parameters of Init structure in HCD handle
+
+ (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
+
+ (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
+ (##) Enable the HCD/USB Low Level interface clock using the following macros
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+ (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure HCD pin-out
+ (##) Configure HCD NVIC interrupt
+
+ (#)Associate the Upper USB Host stack to the HAL HCD Driver:
+ (##) hhcd.pData = phost;
+
+ (#)Enable HCD transmission and reception:
+ (##) HAL_HCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HCD HCD
+ * @brief HCD HAL module driver
+ * @{
+ */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+ * @{
+ */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
+ * @{
+ */
+
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the host driver.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
+{
+ /* Check the HCD handle allocation */
+ if(hhcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+
+ hhcd->State = HAL_HCD_STATE_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_HCD_MspInit(hhcd);
+
+ /* Disable the Interrupts */
+ __HAL_HCD_DISABLE(hhcd);
+
+ /* Init the Core (common init.) */
+ USB_CoreInit(hhcd->Instance, hhcd->Init);
+
+ /* Force Host Mode*/
+ USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
+
+ /* Init Host */
+ USB_HostInit(hhcd->Instance, hhcd->Init);
+
+ hhcd->State= HAL_HCD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize a host channel.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param epnum Endpoint number.
+ * This parameter can be a value from 1 to 15
+ * @param dev_address Current device address
+ * This parameter can be a value from 0 to 255
+ * @param speed Current device speed.
+ * This parameter can be one of these values:
+ * HCD_SPEED_HIGH: High speed mode,
+ * HCD_SPEED_FULL: Full speed mode,
+ * HCD_SPEED_LOW: Low speed mode
+ * @param ep_type Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type,
+ * EP_TYPE_ISOC: Isochronous type,
+ * EP_TYPE_BULK: Bulk type,
+ * EP_TYPE_INTR: Interrupt type
+ * @param mps Max Packet Size.
+ * This parameter can be a value from 0 to32K
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_LOCK(hhcd);
+
+ hhcd->hc[ch_num].dev_addr = dev_address;
+ hhcd->hc[ch_num].max_packet = mps;
+ hhcd->hc[ch_num].ch_num = ch_num;
+ hhcd->hc[ch_num].ep_type = ep_type;
+ hhcd->hc[ch_num].ep_num = epnum & 0x7F;
+ hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
+ hhcd->hc[ch_num].speed = speed;
+/* MBED */
+ /* reset to 0 */
+ hhcd->hc[ch_num].toggle_out = 0;
+ hhcd->hc[ch_num].toggle_in = 0;
+/* MBED */
+
+ status = USB_HC_Init(hhcd->Instance,
+ ch_num,
+ epnum,
+ dev_address,
+ speed,
+ ep_type,
+ mps);
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+
+/**
+ * @brief Halt a host channel.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_LOCK(hhcd);
+ USB_HC_Halt(hhcd->Instance, ch_num);
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the host driver.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
+{
+ /* Check the HCD handle allocation */
+ if(hhcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hhcd->State = HAL_HCD_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_HCD_MspDeInit(hhcd);
+
+ __HAL_HCD_DISABLE(hhcd);
+
+ hhcd->State = HAL_HCD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the HCD MSP.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the HCD MSP.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
+ * @brief HCD IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data
+ Transfer
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Submit a new URB for processing.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param direction Channel number.
+ * This parameter can be one of these values:
+ * 0 : Output / 1 : Input
+ * @param ep_type Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type/
+ * EP_TYPE_ISOC: Isochronous type/
+ * EP_TYPE_BULK: Bulk type/
+ * EP_TYPE_INTR: Interrupt type/
+ * @param token Endpoint Type.
+ * This parameter can be one of these values:
+ * 0: HC_PID_SETUP / 1: HC_PID_DATA1
+ * @param pbuff pointer to URB data
+ * @param length Length of URB data
+ * @param do_ping activate do ping protocol (for high speed only).
+ * This parameter can be one of these values:
+ * 0 : do ping inactive / 1 : do ping active
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t direction,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping)
+{
+/* MBED */
+ if ((hhcd->hc[ch_num].ep_is_in != direction)) {
+ if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)){
+ /* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ if (direction)
+ {
+ USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+ USBx_HC(ch_num)->HCCHAR |= 1 << 15;
+ }
+ else
+ {
+ USBx_HC(ch_num)->HCINTMSK &= ~USB_OTG_HCINTMSK_BBERRM;
+ USBx_HC(ch_num)->HCCHAR &= ~(1 << 15);
+ }
+ hhcd->hc[ch_num].ep_is_in = direction;
+ /* if reception put toggle_in to 1 */
+ if (direction == 1) hhcd->hc[ch_num].toggle_in=1;
+ }
+ }
+/* MBED */
+ hhcd->hc[ch_num].ep_type = ep_type;
+
+ if(token == 0)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+
+ /* Manage Data Toggle */
+ switch(ep_type)
+ {
+ case EP_TYPE_CTRL:
+ if((token == 1) && (direction == 0)) /*send data */
+ {
+ if (length == 0)
+ { /* For Status OUT stage, Length==0, Status Out PID = 1 */
+ hhcd->hc[ch_num].toggle_out = 1;
+ }
+
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0)
+ { /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ { /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
+ {
+ hhcd->hc[ch_num].do_ping = do_ping;
+ }
+ }
+/* MBED */
+ else if ((token == 1) && (direction == 1))
+ {
+ if( hhcd->hc[ch_num].toggle_in == 0)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+/* MBED */
+ break;
+
+ case EP_TYPE_BULK:
+ if(direction == 0)
+ {
+ /* Set the Data Toggle bit as per the Flag */
+ if ( hhcd->hc[ch_num].toggle_out == 0)
+ { /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ { /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
+ {
+ hhcd->hc[ch_num].do_ping = do_ping;
+ }
+ }
+ else
+ {
+ if( hhcd->hc[ch_num].toggle_in == 0)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+
+ break;
+ case EP_TYPE_INTR:
+ if(direction == 0)
+ {
+ /* Set the Data Toggle bit as per the Flag */
+ if ( hhcd->hc[ch_num].toggle_out == 0)
+ { /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ { /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+ else
+ {
+ if( hhcd->hc[ch_num].toggle_in == 0)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+ break;
+
+ case EP_TYPE_ISOC:
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ break;
+ }
+
+ hhcd->hc[ch_num].xfer_buff = pbuff;
+ hhcd->hc[ch_num].xfer_len = length;
+ hhcd->hc[ch_num].urb_state = URB_IDLE;
+ hhcd->hc[ch_num].xfer_count = 0;
+ hhcd->hc[ch_num].ch_num = ch_num;
+ hhcd->hc[ch_num].state = HC_IDLE;
+
+ return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
+}
+
+/**
+ * @brief Handle HCD interrupt request.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t i = 0U , interrupt = 0U;
+
+ /* Ensure that we are in device mode */
+ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
+ {
+ /* Avoid spurious interrupt */
+ if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
+ {
+ return;
+ }
+
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ {
+ /* Incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+ }
+
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+ {
+ /* Incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
+ }
+
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+ {
+ /* Incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
+ }
+
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+ {
+ /* Incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
+ }
+
+ /* Handle Host Disconnect Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+ {
+
+ /* Cleanup HPRT */
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+
+ /* Handle Host Port Interrupts */
+ HAL_HCD_Disconnect_Callback(hhcd);
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+ }
+
+ /* Handle Host Port Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+ {
+ HCD_Port_IRQHandler (hhcd);
+ }
+
+ /* Handle Host SOF Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+ {
+ HAL_HCD_SOF_Callback(hhcd);
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
+ }
+
+ /* Handle Host channel Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+ {
+ interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
+ for (i = 0U; i < hhcd->Init.Host_channels; i++)
+ {
+ if (interrupt & (1U << i))
+ {
+ if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR)
+ {
+ HCD_HC_IN_IRQHandler(hhcd, i);
+ }
+ else
+ {
+ HCD_HC_OUT_IRQHandler (hhcd, i);
+ }
+ }
+ }
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
+ }
+
+ /* Handle Rx Queue Level Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
+ {
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+ HCD_RXQLVL_IRQHandler (hhcd);
+
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
+ }
+}
+
+/**
+ * @brief SOF callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_SOF_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Connection Event callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_Connect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disconnection Event callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Notify URB state change callback.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param urb_state:
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL/
+ * @retval None
+ */
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+ UNUSED(chnum);
+ UNUSED(urb_state);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the HCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the host driver.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
+{
+ __HAL_LOCK(hhcd);
+ __HAL_HCD_ENABLE(hhcd);
+ USB_DriveVbus(hhcd->Instance, 1U);
+ __HAL_UNLOCK(hhcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the host driver.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
+{
+ __HAL_LOCK(hhcd);
+ USB_StopHost(hhcd->Instance);
+ __HAL_UNLOCK(hhcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the host port.
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
+{
+ return (USB_ResetPort(hhcd->Instance));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the HCD handle state.
+ * @param hhcd HCD handle
+ * @retval HAL state
+ */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
+{
+ return hhcd->State;
+}
+
+/**
+ * @brief Return URB state for a channel.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval URB state.
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL
+ */
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ return hhcd->hc[chnum].urb_state;
+}
+
+
+/**
+ * @brief Return the last host transfer size.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval last transfer size in byte
+ */
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ return hhcd->hc[chnum].xfer_count;
+}
+
+/**
+ * @brief Return the Host Channel state.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval Host channel state
+ * This parameter can be one of these values:
+ * HC_IDLE/
+ * HC_XFRC/
+ * HC_HALTED/
+ * HC_NYET/
+ * HC_NAK/
+ * HC_STALL/
+ * HC_XACTERR/
+ * HC_BBLERR/
+ * HC_DATATGLERR
+ */
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ return hhcd->hc[chnum].state;
+}
+
+/**
+ * @brief Return the current Host frame number.
+ * @param hhcd HCD handle
+ * @retval Current Host frame number
+ */
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
+{
+ return (USB_GetCurrentFrame(hhcd->Instance));
+}
+
+/**
+ * @brief Return the Host enumeration speed.
+ * @param hhcd HCD handle
+ * @retval Enumeration speed
+ */
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
+{
+ return (USB_GetHostSpeed(hhcd->Instance));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup HCD_Private_Functions
+ * @{
+ */
+/**
+ * @brief Handle Host Channel IN interrupt requests.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval None
+ */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t tmpreg = 0U;
+
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ hhcd->hc[chnum].state = HC_STALL;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ hhcd->hc[chnum].state = HC_DATATGLERR;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+ }
+
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
+ {
+
+ if (hhcd->Init.dma_enable)
+ {
+ hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
+ (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+ }
+
+ hhcd->hc[chnum].state = HC_XFRC;
+ hhcd->hc[chnum].ErrCnt = 0U;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+
+
+ if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+
+ }
+ else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+ {
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+ hhcd->hc[chnum].urb_state = URB_DONE;
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ }
+ hhcd->hc[chnum].toggle_in ^= 1U;
+
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
+ {
+/* MBED */
+ int reactivate=0;
+/* MBED */
+ __HAL_HCD_MASK_HALT_HC_INT(chnum);
+
+ if(hhcd->hc[chnum].state == HC_XFRC)
+ {
+ hhcd->hc[chnum].urb_state = URB_DONE;
+ }
+
+ else if (hhcd->hc[chnum].state == HC_STALL)
+ {
+ hhcd->hc[chnum].urb_state = URB_STALL;
+ }
+
+ else if((hhcd->hc[chnum].state == HC_XACTERR) ||
+ (hhcd->hc[chnum].state == HC_DATATGLERR))
+ {
+ if(hhcd->hc[chnum].ErrCnt++ > 3U)
+ {
+ hhcd->hc[chnum].ErrCnt = 0U;
+ hhcd->hc[chnum].urb_state = URB_ERROR;
+ }
+ else
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+
+ /* re-activate the channel */
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+/* MBED */
+ if ( hhcd->hc[chnum].urb_state != URB_ERROR) {
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ reactivate = 1;
+ }
+/* MBED */
+ USBx_HC(chnum)->HCCHAR = tmpreg;
+
+ }
+/* MBED */
+ if (hhcd->hc[chnum].state == 0) reactivate = 1;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+ if (reactivate == 0) HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+/* MBED */
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ hhcd->hc[chnum].ErrCnt++;
+ hhcd->hc[chnum].state = HC_XACTERR;
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
+ {
+ if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ }
+
+ /* Clear the NAK flag before re-enabling the channel for new IN request */
+ hhcd->hc[chnum].state = HC_NAK;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+
+ if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ {
+ /* re-activate the channel */
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
+ }
+ }
+}
+
+/**
+ * @brief Handle Host Channel OUT interrupt requests.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval None
+ */
+static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+
+ if( hhcd->hc[chnum].do_ping == 1U)
+ {
+ hhcd->hc[chnum].state = HC_NYET;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET)
+ {
+ hhcd->hc[chnum].state = HC_NYET;
+ hhcd->hc[chnum].ErrCnt= 0U;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
+
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
+ {
+ hhcd->hc[chnum].ErrCnt = 0U;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+ hhcd->hc[chnum].state = HC_XFRC;
+
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].state = HC_STALL;
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
+ {
+ hhcd->hc[chnum].ErrCnt = 0U;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].state = HC_NAK;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].state = HC_XACTERR;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+ hhcd->hc[chnum].state = HC_DATATGLERR;
+ }
+
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
+ {
+ __HAL_HCD_MASK_HALT_HC_INT(chnum);
+
+ if(hhcd->hc[chnum].state == HC_XFRC)
+ {
+ hhcd->hc[chnum].urb_state = URB_DONE;
+ if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
+ {
+ hhcd->hc[chnum].toggle_out ^= 1U;
+ }
+ }
+ else if (hhcd->hc[chnum].state == HC_NAK)
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+
+ else if (hhcd->hc[chnum].state == HC_NYET)
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ hhcd->hc[chnum].do_ping = 0U;
+ }
+
+ else if (hhcd->hc[chnum].state == HC_STALL)
+ {
+ hhcd->hc[chnum].urb_state = URB_STALL;
+ }
+
+ else if((hhcd->hc[chnum].state == HC_XACTERR) ||
+ (hhcd->hc[chnum].state == HC_DATATGLERR))
+ {
+ if(hhcd->hc[chnum].ErrCnt++ > 3U)
+ {
+ hhcd->hc[chnum].ErrCnt = 0U;
+ hhcd->hc[chnum].urb_state = URB_ERROR;
+ }
+ else
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+ }
+
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ }
+}
+
+/**
+ * @brief Handle Rx Queue Level interrupt requests.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint8_t channelnum = 0;
+ uint32_t pktsts;
+ uint32_t pktcnt;
+ uint32_t temp = 0U;
+ uint32_t tmpreg = 0U;
+
+ temp = hhcd->Instance->GRXSTSP;
+ channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
+ pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U;
+ pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
+
+ switch (pktsts)
+ {
+ case GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+ if ((pktcnt > 0U) && (hhcd->hc[channelnum].xfer_buff != (void *)0))
+ {
+
+ USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
+
+ /*manage multiple Xfer */
+ hhcd->hc[channelnum].xfer_buff += pktcnt;
+ hhcd->hc[channelnum].xfer_count += pktcnt;
+
+ if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
+ {
+ /* re-activate the channel when more packets are expected */
+ tmpreg = USBx_HC(channelnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(channelnum)->HCCHAR = tmpreg;
+ hhcd->hc[channelnum].toggle_in ^= 1;
+ }
+ }
+ break;
+
+ case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+ break;
+ case GRXSTS_PKTSTS_IN_XFER_COMP:
+ case GRXSTS_PKTSTS_CH_HALTED:
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Handle Host Port interrupt requests.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ __IO uint32_t hprt0, hprt0_dup;
+
+ /* Handle Host Port Interrupts */
+ hprt0 = USBx_HPRT0;
+ hprt0_dup = USBx_HPRT0;
+
+ hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+
+ /* Check whether Port Connect Detected */
+ if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+ {
+ if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+ {
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+ HAL_HCD_Connect_Callback(hhcd);
+ }
+ hprt0_dup |= USB_OTG_HPRT_PCDET;
+
+ }
+
+ /* Check whether Port Enable Changed */
+ if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+ {
+ hprt0_dup |= USB_OTG_HPRT_PENCHNG;
+
+ if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+ {
+ if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
+ {
+ if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17U))
+ {
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
+ }
+ else
+ {
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+ }
+ }
+ else
+ {
+ if(hhcd->Init.speed == HCD_SPEED_FULL)
+ {
+ USBx_HOST->HFIR = 60000U;
+ }
+ }
+
+ HAL_HCD_Connect_Callback(hhcd);
+ }
+ else
+ {
+ /* Clean up HPRT */
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+ }
+ }
+
+ /* Check for an over current */
+ if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+ {
+ hprt0_dup |= USB_OTG_HPRT_POCCHNG;
+ }
+
+ /* Clear Port Interrupts */
+ USBx_HPRT0 = hprt0_dup;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+ STM32F412Vx || STM32F412Cx || defined(STM32F413xx) || defined(STM32F423xx) */
+#endif /* HAL_HCD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,260 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hcd.h
+ * @author MCD Application Team
+ * @brief Header file of HCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HCD_H
+#define __STM32F4xx_HAL_HCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usb.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Types HCD Exported Types
+ * @{
+ */
+
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
+ * @{
+ */
+typedef enum
+{
+ HAL_HCD_STATE_RESET = 0x00U,
+ HAL_HCD_STATE_READY = 0x01U,
+ HAL_HCD_STATE_ERROR = 0x02U,
+ HAL_HCD_STATE_BUSY = 0x03U,
+ HAL_HCD_STATE_TIMEOUT = 0x04U
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
+typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
+ * @{
+ */
+typedef struct
+{
+ HCD_TypeDef *Instance; /*!< Register base address */
+ HCD_InitTypeDef Init; /*!< HCD required parameters */
+ HCD_HCTypeDef hc[15U]; /*!< Host channels parameters */
+ HAL_LockTypeDef Lock; /*!< HCD peripheral status */
+ __IO HCD_StateTypeDef State; /*!< HCD communication state */
+ void *pData; /*!< Pointer Stack Handler */
+} HCD_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants HCD Exported Constants
+ * @{
+ */
+
+/** @defgroup HCD_Speed HCD Speed
+ * @{
+ */
+#define HCD_SPEED_HIGH 0U
+#define HCD_SPEED_LOW 2U
+#define HCD_SPEED_FULL 3U
+/**
+ * @}
+ */
+
+/** @defgroup HCD_PHY_Module HCD PHY Module
+ * @{
+ */
+#define HCD_PHY_ULPI 1U
+#define HCD_PHY_EMBEDDED 2U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Macros HCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
+
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t direction,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping);
+
+/* Non-Blocking mode: Interrupt */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+ uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HCD_Private_Macros HCD Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+ STM32F412Vx || STM32F412Cx || defined(STM32F413xx) || defined(STM32F423xx) */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_HCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,5502 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2c.c
+ * @author MCD Application Team
+ * @brief I2C HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State, Mode and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The I2C HAL driver can be used as follows:
+
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:
+ I2C_HandleTypeDef hi2c;
+
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+ (##) Enable the I2Cx interface clock
+ (##) I2C pins configuration
+ (+++) Enable the clock for the I2C GPIOs
+ (+++) Configure I2C pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the I2Cx interrupt priority
+ (+++) Enable the NVIC I2C IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx Stream
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx Stream
+
+ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
+ Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
+
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+
+ *** Interrupt mode IO sequential operation ***
+ ==============================================
+ [..]
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ when a direction change during transfer
+ [..]
+ (+) A specific option field manage the different steps of a sequential transfer
+ (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition
+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and without a final stop condition in both cases
+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and with a final stop condition in both cases
+
+ (+) Differents sequential I2C interfaces are listed below:
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
+ HAL_I2C_Mem_Write_IT()
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
+ HAL_I2C_Mem_Read_IT()
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
+ HAL_I2C_Mem_Write_DMA()
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
+ HAL_I2C_Mem_Read_DMA()
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+
+ *** I2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in I2C HAL driver.
+
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+ [..]
+ (@) You can refer to the I2C HAL driver header file for more useful macros
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2C I2C
+ * @brief I2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Define
+ * @{
+ */
+#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
+#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
+#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+static void I2C_ITError(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the I2Cx peripheral:
+
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
+
+ (+) Call the function HAL_I2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Communication Speed
+ (++) Duty cycle
+ (++) Addressing mode
+ (++) Own Address 1
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ of the selected I2Cx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2C according to the specified parameters
+ * in the I2C_InitTypeDef and create the associated handle.
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t freqrange = 0U;
+ uint32_t pclk1 = 0U;
+
+ /* Check the I2C handle allocation */
+ if(hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
+ assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+ if(hi2c->State == HAL_I2C_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_I2C_MspInit(hi2c);
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Get PCLK1 frequency */
+ pclk1 = HAL_RCC_GetPCLK1Freq();
+
+ /* Calculate frequency range */
+ freqrange = I2C_FREQRANGE(pclk1);
+
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ /* Configure I2Cx: Frequency range */
+ hi2c->Instance->CR2 = freqrange;
+
+ /*---------------------------- I2Cx TRISE Configuration --------------------*/
+ /* Configure I2Cx: Rise Time */
+ hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
+
+ /*---------------------------- I2Cx CCR Configuration ----------------------*/
+ /* Configure I2Cx: Speed */
+ hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
+
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+ /* Configure I2Cx: Generalcall and NoStretch mode */
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Configure I2Cx: Own Address1 and addressing mode */
+ hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
+
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Configure I2Cx: Dual mode and Own Address2 */
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
+
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the I2C peripheral.
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if(hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the I2C Peripheral Clock */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_I2C_MspDeInit(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_RESET;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2C MSP Init.
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval None
+ */
+ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C MSP DeInit
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval None
+ */
+ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2C data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2C_Master_Transmit()
+ (++) HAL_I2C_Master_Receive()
+ (++) HAL_I2C_Slave_Transmit()
+ (++) HAL_I2C_Slave_Receive()
+ (++) HAL_I2C_Mem_Write()
+ (++) HAL_I2C_Mem_Read()
+ (++) HAL_I2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2C_Master_Transmit_IT()
+ (++) HAL_I2C_Master_Receive_IT()
+ (++) HAL_I2C_Slave_Transmit_IT()
+ (++) HAL_I2C_Slave_Receive_IT()
+ (++) HAL_I2C_Master_Sequential_Transmit_IT()
+ (++) HAL_I2C_Master_Sequential_Receive_IT()
+ (++) HAL_I2C_Slave_Sequential_Transmit_IT()
+ (++) HAL_I2C_Slave_Sequential_Receive_IT()
+ (++) HAL_I2C_Mem_Write_IT()
+ (++) HAL_I2C_Mem_Read_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2C_Master_Transmit_DMA()
+ (++) HAL_I2C_Master_Receive_DMA()
+ (++) HAL_I2C_Slave_Transmit_DMA()
+ (++) HAL_I2C_Slave_Receive_DMA()
+ (++) HAL_I2C_Mem_Write_DMA()
+ (++) HAL_I2C_Mem_Read_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_MasterTxCpltCallback()
+ (++) HAL_I2C_MasterRxCpltCallback()
+ (++) HAL_I2C_SlaveTxCpltCallback()
+ (++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_ErrorCallback()
+ (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Send Slave Address */
+ if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ while(hi2c->XferSize > 0U)
+ {
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Send Slave Address */
+ if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(hi2c->XferSize == 0U)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ else if(hi2c->XferSize == 1U)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ else if(hi2c->XferSize == 2U)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Enable Pos */
+ hi2c->Instance->CR1 |= I2C_CR1_POS;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ while(hi2c->XferSize > 0U)
+ {
+ if(hi2c->XferSize <= 3U)
+ {
+ /* One byte */
+ if(hi2c->XferSize == 1U)
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ /* Two bytes */
+ else if(hi2c->XferSize == 2U)
+ {
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ /* 3 Last bytes */
+ else
+ {
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+ else
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* If 10bit addressing mode is selected */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ while(hi2c->XferSize > 0U)
+ {
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+ }
+
+ /* Wait until AF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ while(hi2c->XferSize > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+
+ /* Wait until STOP flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ __IO uint32_t Prev_State = 0x00U;
+ __IO uint32_t count = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ Prev_State = hi2c->PreviousState;
+
+ /* Generate Start */
+ if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
+ {
+ /* Generate Start condition if first transfer */
+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+ {
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED
+ {
+ /* Generate ReStart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ __IO uint32_t count = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
+ {
+ /* Generate Start condition if first transfer */
+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME))
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate ReStart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp;
+
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Disable EVT and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ if(hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferM1CpltCallback = NULL;
+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ if(hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferM1CpltCallback = NULL;
+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master I2C process communication with Interrupt.
+ * @note This abort can be called only if state is ready
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(DevAddress);
+
+ /* Abort Master transfer during Receive or Transmit process */
+ if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_ABORT;
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->XferCount = 0U;
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferM1CpltCallback = NULL;
+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferM1CpltCallback = NULL;
+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ while(hi2c->XferSize > 0U)
+ {
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(hi2c->XferSize == 0U)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ else if(hi2c->XferSize == 1U)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ else if(hi2c->XferSize == 2U)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Enable Pos */
+ hi2c->Instance->CR1 |= I2C_CR1_POS;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ while(hi2c->XferSize > 0U)
+ {
+ if(hi2c->XferSize <= 3U)
+ {
+ /* One byte */
+ if(hi2c->XferSize== 1U)
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ /* Two bytes */
+ else if(hi2c->XferSize == 2U)
+ {
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ /* 3 Last bytes */
+ else
+ {
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+ else
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->Devaddress = DevAddress;
+ hi2c->Memaddress = MemAddress;
+ hi2c->MemaddSize = MemAddSize;
+ hi2c->EventCount = 0U;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->Devaddress = DevAddress;
+ hi2c->Memaddress = MemAddress;
+ hi2c->MemaddSize = MemAddSize;
+ hi2c->EventCount = 0U;
+
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ if(hi2c->XferSize > 0U)
+ {
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ if(hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferM1CpltCallback = NULL;
+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tickstart = 0x00U;
+ __IO uint32_t count = 0U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
+ if(hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferM1CpltCallback = NULL;
+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(Size == 1U)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ }
+ else
+ {
+ /* Enable Last DMA bit */
+ hi2c->Instance->CR2 |= I2C_CR2_LAST;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ }
+ else
+ {
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ do
+ {
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+
+ /* Wait until ADDR or AF flag are set */
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ tmp3 = hi2c->State;
+ while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hi2c->State = HAL_I2C_STATE_TIMEOUT;
+ }
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ tmp3 = hi2c->State;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if the ADDR flag has been set */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ /* Clear ADDR Flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ /* Clear AF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }while(I2C_Trials++ < Trials);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles I2C event interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR2);
+
+ uint32_t CurrentMode = hi2c->Mode;
+
+ /* Master or Memory mode selected */
+ if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
+ {
+ /* SB Set ----------------------------------------------------------------*/
+ if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_Master_SB(hi2c);
+ }
+ /* ADD10 Set -------------------------------------------------------------*/
+ else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_Master_ADD10(hi2c);
+ }
+ /* ADDR Set --------------------------------------------------------------*/
+ else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_Master_ADDR(hi2c);
+ }
+
+ /* I2C in mode Transmitter -----------------------------------------------*/
+ if((sr2itflags & I2C_FLAG_TRA) != RESET)
+ {
+ /* TXE set and BTF reset -----------------------------------------------*/
+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
+ {
+ I2C_MasterTransmit_TXE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_MasterTransmit_BTF(hi2c);
+ }
+ }
+ /* I2C in mode Receiver --------------------------------------------------*/
+ else
+ {
+ /* RXNE set and BTF reset -----------------------------------------------*/
+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
+ {
+ I2C_MasterReceive_RXNE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_MasterReceive_BTF(hi2c);
+ }
+ }
+ }
+ /* Slave mode selected */
+ else
+ {
+ /* ADDR set --------------------------------------------------------------*/
+ if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_Slave_ADDR(hi2c);
+ }
+ /* STOPF set --------------------------------------------------------------*/
+ else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_Slave_STOPF(hi2c);
+ }
+ /* I2C in mode Transmitter -----------------------------------------------*/
+ else if((sr2itflags & I2C_FLAG_TRA) != RESET)
+ {
+ /* TXE set and BTF reset -----------------------------------------------*/
+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
+ {
+ I2C_SlaveTransmit_TXE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_SlaveTransmit_BTF(hi2c);
+ }
+ }
+ /* I2C in mode Receiver --------------------------------------------------*/
+ else
+ {
+ /* RXNE set and BTF reset ----------------------------------------------*/
+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
+ {
+ I2C_SlaveReceive_RXNE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_SlaveReceive_BTF(hi2c);
+ }
+ }
+ }
+}
+
+/**
+ * @brief This function handles I2C error interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR2);
+
+ /* I2C Bus error interrupt occurred ----------------------------------------*/
+ if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+ }
+
+ /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
+ if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ }
+
+ /* I2C Acknowledge failure error interrupt occurred ------------------------*/
+ if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
+ {
+ tmp1 = hi2c->Mode;
+ tmp2 = hi2c->XferCount;
+ tmp3 = hi2c->State;
+ tmp4 = hi2c->PreviousState;
+ if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
+ ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
+ ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
+ {
+ I2C_Slave_AF(hi2c);
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
+ if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ }
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+
+ /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
+ if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+ }
+
+ /* Call the Error Callback in case of Error detected -----------------------*/
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ I2C_ITError(hi2c);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AddrCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ListenCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemTxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C error callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C abort callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AbortCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2C handle state.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL state
+ */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+ /* Return I2C handle state */
+ return hi2c->State;
+}
+
+/**
+ * @brief Return the I2C Master, Slave, Memory or no mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL mode
+ */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->Mode;
+}
+
+/**
+ * @brief Return the I2C error code
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval I2C Error Code
+ */
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Handle TXE flag for Master
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+ uint32_t CurrentMode = hi2c->Mode;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+ if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
+ {
+ /* Call TxCpltCallback() directly if no stop mode is set */
+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+ {
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ else /* Generate Stop condition then Call TxCpltCallback() */
+ {
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+ }
+ else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
+ ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
+ {
+ if(hi2c->XferCount == 0U)
+ {
+ /* Disable BUF interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+ }
+ else
+ {
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ if(hi2c->EventCount == 0)
+ {
+ /* If Memory address size is 8Bit */
+ if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+ hi2c->EventCount += 2;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
+
+ hi2c->EventCount++;
+ }
+ }
+ else if(hi2c->EventCount == 1)
+ {
+ /* Send LSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+ hi2c->EventCount++;
+ }
+ else if(hi2c->EventCount == 2)
+ {
+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ /* Generate Restart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ }
+ }
+ else
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Master transmitter
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ if(hi2c->XferCount != 0U)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ else
+ {
+ /* Call TxCpltCallback() directly if no stop mode is set */
+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+ {
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ else /* Generate Stop condition then Call TxCpltCallback() */
+ {
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle RXNE flag for Master
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
+{
+
+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ uint32_t tmp = 0U;
+
+ tmp = hi2c->XferCount;
+ if(tmp > 3U)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+/* MBED */
+ }
+ else if((tmp == 2U) || (tmp == 3U))
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Enable Pos */
+ hi2c->Instance->CR1 |= I2C_CR1_POS;
+
+ /* Disable BUF interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+ }
+ else
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ if(hi2c->XferOptions == I2C_NEXT_FRAME)
+ {
+ /* Enable Pos */
+ hi2c->Instance->CR1 |= I2C_CR1_POS;
+ }
+/* MBED */
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Master receiver
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+/* MBED */
+ if(hi2c->XferCount == 3U)
+ {
+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ }
+/* MBED */
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ else if(hi2c->XferCount == 2U)
+ {
+ /* Prepare next transfer or stop current transfer */
+/* MBED */
+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME))
+ {
+ /* Generate ReStart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+/* MBED */
+ }
+ else
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+
+ /* Disable EVT and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+ else
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SB flag for Master
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ if(hi2c->EventCount == 0U)
+ {
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+ }
+ else
+ {
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+ }
+ }
+ else
+ {
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ /* Send slave 7 Bits address */
+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+ }
+ else
+ {
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+ }
+ }
+ else
+ {
+ if(hi2c->EventCount == 0U)
+ {
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
+ }
+ else if(hi2c->EventCount == 1U)
+ {
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADD10 flag for Master
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
+{
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADDR flag for Master
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentMode = hi2c->Mode;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+ uint32_t Prev_State = hi2c->PreviousState;
+
+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Restart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ hi2c->EventCount++;
+ }
+ else
+ {
+ if(hi2c->XferCount == 0U)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ else if(hi2c->XferCount == 1U)
+ {
+ if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ }
+ /* Prepare next transfer or stop current transfer */
+ else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
+ && (Prev_State != I2C_STATE_MASTER_BUSY_RX))
+ {
+ if(hi2c->XferOptions != I2C_NEXT_FRAME)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ }
+ else if(hi2c->XferCount == 2U)
+ {
+ if(hi2c->XferOptions != I2C_NEXT_FRAME)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Enable Pos */
+ hi2c->Instance->CR1 |= I2C_CR1_POS;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ }
+
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ /* Enable Last DMA bit */
+ hi2c->Instance->CR2 |= I2C_CR2_LAST;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ /* Enable Last DMA bit */
+ hi2c->Instance->CR2 |= I2C_CR2_LAST;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ /* Reset Event counter */
+ hi2c->EventCount = 0U;
+ }
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle TXE flag for Slave
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+
+ if(hi2c->XferCount != 0U)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+
+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ /* Last Byte is received, disable Interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+ /* Set state at HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+
+ /* Call the Tx complete callback to inform upper layer of the end of receive process */
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Slave transmitter
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->XferCount != 0U)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle RXNE flag for Slave
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+
+ if(hi2c->XferCount != 0U)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+
+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ /* Last Byte is received, disable Interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+ /* Set state at HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+
+ /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Slave receiver
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->XferCount != 0U)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADD flag for Slave
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
+{
+ uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
+ uint16_t SlaveAddrCode = 0U;
+
+ /* Transfer Direction requested by Master */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
+ {
+ TransferDirection = I2C_DIRECTION_TRANSMIT;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
+ {
+ SlaveAddrCode = hi2c->Init.OwnAddress1;
+ }
+ else
+ {
+ SlaveAddrCode = hi2c->Init.OwnAddress2;
+ }
+
+ /* Call Slave Addr callback */
+ HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle STOPF flag for Slave
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Clear STOPF flag */
+ __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* If a DMA is ongoing, Update handle size context */
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ }
+ else
+ {
+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ }
+ }
+
+ /* All data are not transferred, so set error code accordingly */
+ if(hi2c->XferCount != 0U)
+ {
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c);
+ }
+ else
+ {
+ if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
+ (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+ }
+ else
+ {
+ if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+ if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
+ (CurrentState == HAL_I2C_STATE_LISTEN))
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+ }
+ else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+ else
+ {
+ /* Clear AF flag only */
+ /* State Listen, but XferOptions == FIRST or NEXT */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2C interrupts error process
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+
+ if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ /* keep HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ }
+ else
+ {
+ /* If state is an abort treatment on going, don't change state */
+ /* This change will be do later */
+ if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ }
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ }
+
+ /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ /* Abort DMA transfer */
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+ if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
+ {
+ /* Set the DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ else
+ {
+ /* Set the DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ }
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ else if(hi2c->State == HAL_I2C_STATE_ABORT)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ }
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_AbortCpltCallback(hi2c);
+ }
+ else
+ {
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ }
+
+ /* Call user error callback */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ /* STOP Flag is not set after a NACK reception */
+ /* So may inform upper layer that listen phase is stopped */
+ /* during NACK error treatment */
+ if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+ /* Generate Start condition if first transfer */
+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+ {
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+ {
+ /* Generate ReStart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+ }
+ else
+ {
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
+
+ /* Wait until ADD10 flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
+ }
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address for read request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start condition if first transfer */
+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+ {
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ {
+ /* Generate ReStart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
+ }
+ else
+ {
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
+
+ /* Wait until ADD10 flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Restart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
+ }
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Generate Restart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA I2C process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+ uint32_t CurrentMode = hi2c->Mode;
+
+ if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+ hi2c->XferCount = 0U;
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ }
+ else
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ /* Disable Last DMA */
+ hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+ hi2c->XferCount = 0U;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Ignore DMA FIFO error */
+ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ hi2c->XferCount = 0U;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C communication abort callback
+ * (To be called at end of DMA Abort procedure).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ hi2c->XferCount = 0U;
+
+ /* Reset XferAbortCallback */
+ hi2c->hdmatx->XferAbortCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if come from abort from user */
+ if(hi2c->State == HAL_I2C_STATE_ABORT)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_AbortCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @param Flag specifies the I2C flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Wait until flag is set */
+ while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for Master addressing phase.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @param Flag specifies the I2C flag to check.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
+{
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+ {
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ /* Clear AF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ {
+ /* Check if a STOPF is detected */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Acknowledge failed detection during an I2C Communication.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
+{
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,649 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2c.h
+ * @author MCD Application Team
+ * @brief Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_H
+#define __STM32F4xx_HAL_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
+/**
+ * @brief I2C Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref I2C_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref I2C_nostretch_mode */
+
+}I2C_InitTypeDef;
+
+/**
+ * @brief HAL State structure definition
+ * @note HAL I2C State value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : Abort (Abort user request on going)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
+ * b4 (not used)
+ * x : Should be set to 0
+ * b3
+ * 0 : Ready or Busy (No Listen mode ongoing)
+ * 1 : Listen (IP in Address Listen Mode)
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ */
+typedef enum
+{
+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
+ process is ongoing */
+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
+ process is ongoing */
+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
+
+}HAL_I2C_StateTypeDef;
+
+/**
+ * @brief HAL Mode structure definition
+ * @note HAL I2C Mode value coding follow below described bitmap :
+ * b7 (not used)
+ * x : Should be set to 0
+ * b6
+ * 0 : None
+ * 1 : Memory (HAL I2C communication is in Memory Mode)
+ * b5
+ * 0 : None
+ * 1 : Slave (HAL I2C communication is in Slave Mode)
+ * b4
+ * 0 : None
+ * 1 : Master (HAL I2C communication is in Master Mode)
+ * b3-b2-b1-b0 (not used)
+ * xxxx : Should be set to 0000
+ */
+typedef enum
+{
+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
+
+}HAL_I2C_ModeTypeDef;
+
+/**
+ * @brief I2C handle Structure definition
+ */
+typedef struct
+{
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ __IO uint32_t XferOptions; /*!< I2C transfer options */
+
+ __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
+ context for internal usage */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
+
+ __IO uint32_t ErrorCode; /*!< I2C Error code */
+
+ __IO uint32_t Devaddress; /*!< I2C Target device address */
+
+ __IO uint32_t Memaddress; /*!< I2C Target memory address */
+
+ __IO uint32_t MemaddSize; /*!< I2C Target memory address size */
+
+ __IO uint32_t EventCount; /*!< I2C Event counter */
+
+}I2C_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_Error_Code I2C Error Code
+ * @brief I2C Error Code
+ * @{
+ */
+#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
+#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
+#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
+#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
+ * @{
+ */
+#define I2C_DUTYCYCLE_2 0x00000000U
+#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
+/**
+ * @}
+ */
+
+/** @defgroup I2C_addressing_mode I2C addressing mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLE 0x00000000U
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
+/**
+ * @}
+ */
+
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLE 0x00000000U
+#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
+/**
+ * @}
+ */
+
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLE 0x00000000U
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT 0x00000001U
+#define I2C_MEMADD_SIZE_16BIT 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+ * @{
+ */
+#define I2C_DIRECTION_RECEIVE 0x00000000U
+#define I2C_DIRECTION_TRANSMIT 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
+ * @{
+ */
+#define I2C_FIRST_FRAME 0x00000001U
+#define I2C_NEXT_FRAME 0x00000002U
+#define I2C_FIRST_AND_LAST_FRAME 0x00000004U
+#define I2C_LAST_FRAME 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+ * @{
+ */
+#define I2C_IT_BUF I2C_CR2_ITBUFEN
+#define I2C_IT_EVT I2C_CR2_ITEVTEN
+#define I2C_IT_ERR I2C_CR2_ITERREN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+ * @{
+ */
+#define I2C_FLAG_SMBALERT 0x00018000U
+#define I2C_FLAG_TIMEOUT 0x00014000U
+#define I2C_FLAG_PECERR 0x00011000U
+#define I2C_FLAG_OVR 0x00010800U
+#define I2C_FLAG_AF 0x00010400U
+#define I2C_FLAG_ARLO 0x00010200U
+#define I2C_FLAG_BERR 0x00010100U
+#define I2C_FLAG_TXE 0x00010080U
+#define I2C_FLAG_RXNE 0x00010040U
+#define I2C_FLAG_STOPF 0x00010010U
+#define I2C_FLAG_ADD10 0x00010008U
+#define I2C_FLAG_BTF 0x00010004U
+#define I2C_FLAG_ADDR 0x00010002U
+#define I2C_FLAG_SB 0x00010001U
+#define I2C_FLAG_DUALF 0x00100080U
+#define I2C_FLAG_SMBHOST 0x00100040U
+#define I2C_FLAG_SMBDEFAULT 0x00100020U
+#define I2C_FLAG_GENCALL 0x00100010U
+#define I2C_FLAG_TRA 0x00100004U
+#define I2C_FLAG_BUSY 0x00100002U
+#define I2C_FLAG_MSL 0x00100001U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2C handle state
+ * @param __HANDLE__ specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief Enable or disable the specified I2C interrupts.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __INTERRUPT__ specifies the I2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2C flag is set or not.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @arg I2C_FLAG_TXE: Data register empty flag
+ * @arg I2C_FLAG_RXNE: Data register not empty flag
+ * @arg I2C_FLAG_STOPF: Stop detection flag
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag
+ * @arg I2C_FLAG_ADDR: Address sent flag
+ * Address matched flag
+ * @arg I2C_FLAG_SB: Start bit flag
+ * @arg I2C_FLAG_DUALF: Dual flag
+ * @arg I2C_FLAG_SMBHOST: SMBus host header
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
+ * @arg I2C_FLAG_GENCALL: General call header flag
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY: Bus busy flag
+ * @arg I2C_FLAG_MSL: Master/Slave flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
+
+/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
+
+/** @brief Clears the I2C ADDR pending flag.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ tmpreg = (__HANDLE__)->Instance->SR2; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clears the I2C STOPF pending flag.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Enable the I2C peripheral.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
+
+/** @brief Disable the I2C peripheral.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
+
+/**
+ * @}
+ */
+
+/* Include I2C HAL Extension module */
+#include "stm32f4xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions *****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State, Mode and Errors functions *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+#define I2C_FLAG_MASK 0x0000FFFFU
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+ * @{
+ */
+
+#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+
+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
+ * @{
+ */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+ ((CYCLE) == I2C_DUTYCYCLE_16_9))
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
+ ((REQUEST) == I2C_NEXT_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,204 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2c_ex.c
+ * @author MCD Application Team
+ * @brief I2C Extension HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of I2C extension peripheral:
+ * + Extension features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### I2C peripheral extension features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/
+ 429xx/439xx devices contains the following additional features :
+
+ (+) Possibility to disable or enable Analog Noise Filter
+ (+) Use of a configured Digital Noise Filter
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure Noise Filter
+ (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config()
+ (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2CEx I2CEx
+ * @brief I2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions
+ * @brief Extension features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Noise Filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures I2C Analog noise filter.
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param AnalogFilter new state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Reset I2Cx ANOFF bit */
+ hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);
+
+ /* Disable the analog filter */
+ hi2c->Instance->FLTR |= AnalogFilter;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configures I2C Digital noise filter.
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+ uint16_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Get the old register value */
+ tmpreg = hi2c->Instance->FLTR;
+
+ /* Reset I2Cx DNF bit [3:0] */
+ tmpreg &= ~(I2C_FLTR_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter;
+
+ /* Store the new register value */
+ hi2c->Instance->FLTR = tmpreg;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\
+ STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx ||\
+ STM32F423xx */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,137 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2c_ex.h
+ * @author MCD Application Team
+ * @brief Header file of I2C HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_EX_H
+#define __STM32F4xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2CEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2CEx_Analog_Filter I2C Analog Filter
+ * @{
+ */
+#define I2C_ANALOGFILTER_ENABLE 0x00000000U
+#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2CEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macros I2C Private Macros
+ * @{
+ */
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\
+ STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx ||\
+ STM32F413xx || STM32F423xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_I2C_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1539 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2s.c
+ * @author MCD Application Team
+ * @brief I2S HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Integrated Interchip Sound (I2S) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The I2S HAL driver can be used as follow:
+
+ (#) Declare a I2S_HandleTypeDef handle structure.
+ (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+ (##) Enable the SPIx interface clock.
+ (##) I2S pins configuration:
+ (+++) Enable the clock for the I2S GPIOs.
+ (+++) Configure these I2S pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+ and HAL_I2S_Receive_IT() APIs).
+ (+++) Configure the I2Sx interrupt priority.
+ (+++) Enable the NVIC I2S IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+ and HAL_I2S_Receive_DMA() APIs:
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Stream.
+
+ (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+ using HAL_I2S_Init() function.
+
+ -@- The specific I2S interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
+ -@- Make sure that either:
+ (+@) I2S PLL is configured or
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+ *** I2S HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in I2S HAL driver.
+
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+ (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+
+ [..]
+ (@) You can refer to the I2S HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+/** @defgroup I2S I2S
+ * @brief I2S HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @addtogroup I2S_Private_Functions
+ * @{
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
+ uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the I2Sx peripheral in simplex mode:
+
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Standard
+ (++) Data Format
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) Polarity
+ (++) Full duplex mode
+
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx peripheral.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U;
+ uint32_t tmp = 0U, i2sclk = 0U;
+
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+ assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* Initialize Default I2S IrqHandler ISR */
+ hi2s->IrqHandlerISR = I2S_IRQHandler;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2S_MspInit(hi2s);
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ hi2s->Instance->I2SPR = 0x0002U;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = hi2s->Instance->I2SCFGR;
+
+ /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing) *******************/
+ /* Set I2S Packet Length value*/
+ if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 32U;
+ }
+ else
+ {
+ /* Packet length is 16 bits */
+ packetlength = 16U;
+ }
+
+ /* I2S standard */
+ if(hi2s->Init.Standard <= I2S_STANDARD_LSB)
+ {
+ /* In I2S standard packet lenght is multiplied by 2 */
+ packetlength = packetlength * 2U;
+ }
+
+ /* Get I2S source Clock frequency from RCC ********************************/
+#if defined(I2S_APB1_APB2_FEATURE)
+ if(IS_I2S_APB1_INSTANCE(hi2s->Instance))
+ {
+ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB1);
+ }
+ else
+ {
+ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB2);
+ }
+#else
+ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S);
+#endif
+
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */
+ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5);
+ }
+ else
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5);
+ }
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ }
+
+ /* Remove the flatting point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)1U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint32_t) (i2sodd << 8U);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+
+ /* Configure the I2S with the I2S_InitStruct values */
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
+ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
+ (uint16_t)hi2s->Init.CPOL))));
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||(hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))
+ {
+ /* Write to SPIx I2SCFGR */
+ WRITE_REG(hi2s->Instance->I2SCFGR,(tmpreg | SPI_I2SCFGR_ASTRTEN));
+ }
+ else
+ {
+ /* Write to SPIx I2SCFGR */
+ WRITE_REG(hi2s->Instance->I2SCFGR,tmpreg);
+ }
+#else
+ /* Write to SPIx I2SCFGR */
+ WRITE_REG(hi2s->Instance->I2SCFGR, tmpreg);
+#endif
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+
+ /* Configure the I2S extended if the full duplex mode is enabled */
+ assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
+
+ if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */
+ hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler;
+
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ I2SxEXT(hi2s->Instance)->I2SPR = 2U;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
+
+ /* Get the mode to be configured for the extended I2S */
+ if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
+ {
+ tmp = I2S_MODE_SLAVE_RX;
+ }
+ else /* I2S_MODE_MASTER_RX || I2S_MODE_SLAVE_RX */
+ {
+ tmp = I2S_MODE_SLAVE_TX;
+ }
+
+ /* Configure the I2S Slave with the I2S Master parameter values */
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
+ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
+ (uint16_t)hi2s->Init.CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR,tmpreg);
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the I2S peripheral
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_I2S_MspDeInit(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2S MSP Init
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S MSP DeInit
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspDeInit could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group2
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2S_Transmit()
+ (++) HAL_I2S_Receive()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2S_Transmit_IT()
+ (++) HAL_I2S_Receive_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2S_Transmit_DMA()
+ (++) HAL_I2S_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2S_TxCpltCallback()
+ (++) HAL_I2S_RxCpltCallback()
+ (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmp1 = 0U;
+
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ while(hi2s->TxXferCount > 0U)
+ {
+ hi2s->Instance->DR = (*pData++);
+ hi2s->TxXferCount--;
+
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an underrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Clear underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+ }
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming)
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmp1 = 0U;
+
+ if((pData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Receive data */
+ while(hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ (*pData++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmp1 = 0U;
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->pTxBuffPtr = pData;
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
+ * between Master and Slave otherwise the I2S interrupt should be optimized.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmp1 = 0U;
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->pRxBuffPtr = pData;
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Transmit data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t *tmp = NULL;
+ uint32_t tmp1 = 0U;
+
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pData;
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+ /* Enable the Tx DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Tx request is already enabled */
+ if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
+ {
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t *tmp = NULL;
+ uint32_t tmp1 = 0U;
+
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pRxBuffPtr = pData;
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Rx DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Rx request is already enabled */
+ if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
+ {
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the audio stream playing from the Media.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA Tx request */
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA Rx request */
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ }
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_TXDMAEN|SPI_CR2_RXDMAEN));
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_TXDMAEN|SPI_CR2_RXDMAEN));
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA Tx request */
+ SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA Rx request */
+ SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ }
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ SET_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ SET_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+
+ /* If the I2Sext peripheral is still not enabled, enable it */
+ if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
+ {
+ /* Enable I2Sext peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+ }
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+
+ /* Disable the I2S DMA Channel */
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+
+ /* Disable the I2S DMA Channel */
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Disable the I2S DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+
+ /* Disable the I2S DMA Channels */
+ HAL_DMA_Abort(hi2s->hdmatx);
+ HAL_DMA_Abort(hi2s->hdmarx);
+
+ /* Disable I2Sext peripheral */
+ __HAL_I2SEXT_DISABLE(hi2s);
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ /* Call the IrqHandler ISR set during HAL_I2S_INIT */
+ hi2s->IrqHandlerISR(hi2s);
+}
+
+/**
+ * @brief Tx Transfer Half completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer half completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S error callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group3
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2S state
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL state
+ */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->State;
+}
+
+/**
+ * @brief Return the I2S error code
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval I2S Error Code
+ */
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+/**
+ * @brief DMA I2S transmit process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+
+ hi2s->TxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_TxCpltCallback(hi2s);
+}
+/**
+ * @brief DMA I2S transmit process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_TxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_RxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_RxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable Rx and Tx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
+
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
+ HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Transmit data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxCpltCallback(hi2s);
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Receive data */
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_RxCpltCallback(hi2s);
+ }
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ __IO uint32_t i2ssr = hi2s->Instance->SR;
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ }
+
+ /* I2S Overrun error interrupt occured -------------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Clear Overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* I2S in mode Transmitter -----------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ }
+
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Clear Underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+}
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
+ uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set to status*/
+ while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2S_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,541 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2s.h
+ * @author MCD Application Team
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2S_H
+#define __STM32F4xx_HAL_I2S_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2S I2S
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+
+ uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
+ This parameter can be a value of @ref I2S_Clock_Source */
+
+ uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
+ This parameter can be a value of @ref I2S_FullDuplex_Mode */
+
+}I2S_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
+
+}HAL_I2S_StateTypeDef;
+
+/**
+ * @brief I2S handle Structure definition
+ */
+typedef struct __I2S_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /*!< I2S registers base address */
+
+ I2S_InitTypeDef Init; /*!< I2S communication parameters */
+
+ uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ void (*IrqHandlerISR) (struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
+
+ __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
+
+ __IO uint32_t ErrorCode; /*!< I2S Error code
+ This parameter can be a value of @ref I2S_ErrorCode */
+
+}I2S_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+ * @{
+ */
+/**
+ * @defgroup I2S_ErrorCode I2S Error Code
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
+#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
+#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode I2S Mode
+ * @{
+ */
+#define I2S_MODE_SLAVE_TX (0x00000000U)
+#define I2S_MODE_SLAVE_RX (0x00000100U)
+#define I2S_MODE_MASTER_TX (0x00000200U)
+#define I2S_MODE_MASTER_RX (0x00000300U)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard I2S Standard
+ * @{
+ */
+#define I2S_STANDARD_PHILIPS (0x00000000U)
+#define I2S_STANDARD_MSB (0x00000010U)
+#define I2S_STANDARD_LSB (0x00000020U)
+#define I2S_STANDARD_PCM_SHORT (0x00000030U)
+#define I2S_STANDARD_PCM_LONG (0x000000B0U)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format I2S Data Format
+ * @{
+ */
+#define I2S_DATAFORMAT_16B (0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
+#define I2S_DATAFORMAT_24B (0x00000003U)
+#define I2S_DATAFORMAT_32B (0x00000005U)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output I2S Mclk Output
+ * @{
+ */
+#define I2S_MCLKOUTPUT_ENABLE SPI_I2SPR_MCKOE
+#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
+ * @{
+ */
+#define I2S_AUDIOFREQ_192K (192000U)
+#define I2S_AUDIOFREQ_96K (96000U)
+#define I2S_AUDIOFREQ_48K (48000U)
+#define I2S_AUDIOFREQ_44K (44100U)
+#define I2S_AUDIOFREQ_32K (32000U)
+#define I2S_AUDIOFREQ_22K (22050U)
+#define I2S_AUDIOFREQ_16K (16000U)
+#define I2S_AUDIOFREQ_11K (11025U)
+#define I2S_AUDIOFREQ_8K (8000U)
+#define I2S_AUDIOFREQ_DEFAULT (2U)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
+ * @{
+ */
+#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
+#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+ * @{
+ */
+#define I2S_CPOL_LOW (0x00000000U)
+#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
+ * @{
+ */
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Flags_Definition I2S Flags Definition
+ * @{
+ */
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
+
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+/**
+ * @}
+ */
+/** @defgroup I2S_Clock_Source I2S Clock Source Definition
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
+ defined(STM32F479xx)
+#define I2S_CLOCK_PLL (0x00000000U)
+#define I2S_CLOCK_EXTERNAL (0x00000001U)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+#define I2S_CLOCK_PLL (0x00000000U)
+#define I2S_CLOCK_EXTERNAL (0x00000001U)
+#define I2S_CLOCK_PLLR (0x00000002U)
+#define I2S_CLOCK_PLLSRC (0x00000003U)
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define I2S_CLOCK_PLLSRC (0x00000000U)
+#define I2S_CLOCK_EXTERNAL (0x00000001U)
+#define I2S_CLOCK_PLLR (0x00000002U)
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2S handle state
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+
+/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &=(uint16_t)(~SPI_I2SCFGR_I2SE))
+
+/** @brief Enable or disable the specified I2S interrupts.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &=(uint16_t)(~(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__ specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2S flag is set or not.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clears the I2S UDR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+/**
+ * @}
+ */
+
+/* Include I2S Extension module */
+#include "stm32f4xx_hal_i2s_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_Exported_Functions_Group1 I2S Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group2 I2S IO operation functions
+ * @{
+ */
+/* I/O operation functions *****************************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group3 I2S Peripheral Control and State functions
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Constants I2S Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
+ ((MODE) == I2S_MODE_SLAVE_RX) || \
+ ((MODE) == I2S_MODE_MASTER_TX) || \
+ ((MODE) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
+ ((STANDARD) == I2S_STANDARD_MSB) || \
+ ((STANDARD) == I2S_STANDARD_LSB) || \
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \
+ ((FORMAT) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
+ ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+ ((CPOL) == I2S_CPOL_HIGH))
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
+ defined(STM32F479xx)
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
+ ((CLOCK) == I2S_CLOCK_PLL))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined (STM32F413xx) ||\
+ defined(STM32F423xx)
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
+ ((CLOCK) == I2S_CLOCK_PLL) ||\
+ ((CLOCK) == I2S_CLOCK_PLLSRC) ||\
+ ((CLOCK) == I2S_CLOCK_PLLR))
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
+ ((CLOCK) == I2S_CLOCK_PLLSRC) ||\
+ ((CLOCK) == I2S_CLOCK_PLLR))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1184 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2s_ex.c
+ * @author MCD Application Team
+ * @brief I2S HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of I2S extension peripheral:
+ * + Extension features Functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### I2S Extension features #####
+ ==============================================================================
+ [..]
+ (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
+ data simultaneously using two data lines. Each SPI peripheral has an extended block
+ called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
+ (#) The extension block is not a full SPI IP, it is used only as I2S slave to
+ implement full duplex mode. The extension block uses the same clock sources
+ as its master.
+
+ (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
+
+ [..]
+ (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
+ I2Sx can be I2S2 or I2S3.
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT()
+ (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA()
+ (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ @endverbatim
+
+ Additional Figure: The Extended block uses the same clock sources as its master.
+
+ +-----------------------+
+ I2Sx_SCK | |
+ ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
+ +--|-->| |
+ | | +-----------------------+
+ | |
+ I2S_WS | |
+ ------>| |
+ | | +-----------------------+
+ | +-->| |
+ | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
+ +----->| |
+ +-----------------------+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+/** @defgroup I2SEx I2SEx
+ * @brief I2S Extended HAL module driver
+ * @{
+ */
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
+ * @{
+ */
+typedef enum
+{
+ I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */
+ I2S_USE_I2SEXT = 0x01U, /*!< I2Sx_ext should be used */
+}I2S_UseTypeDef;
+/**
+ * @}
+ */
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
+ * @{
+ */
+static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma);
+static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma);
+static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
+static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
+static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2SEx I2SEx
+ * @{
+ */
+
+/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
+ * @brief I2SEx IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions#####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2SEx_TransmitReceive()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2SEx_TransmitReceive_IT()
+ (++) HAL_I2SEx_FullDuplex_IRQHandler()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2SEx_TransmitReceive_DMA()
+
+ (#) A set of Transfer Complete Callback are provided in non Blocking mode:
+ (++) HAL_I2SEx_TxRxCpltCallback()
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Full-Duplex Transmit/Receive data in blocking mode.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmp1 = 0U;
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S State */
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ /* Set the I2S State busy TX/RX */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
+ {
+ /* Prepare the First Data before enabling the I2S */
+ hi2s->Instance->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2Sx peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
+ }
+
+ while((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
+ {
+ if(hi2s->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set */
+ if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+ /* Write Data on DR register */
+ hi2s->Instance->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+
+ /* Check if an underrun occurs */
+ if((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_TX))
+ {
+ /* Clear Underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+ }
+ if(hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+ /* Read Data from DR register */
+ (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
+ hi2s->RxXferCount--;
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear Overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* Prepare the First Data before enabling the I2S */
+ I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+
+ /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral before the I2Sext*/
+ __HAL_I2S_ENABLE(hi2s);
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ while((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
+ {
+ if(hi2s->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set */
+ if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+ /* Write Data on DR register */
+ I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+
+ /* Check if an underrun occurs */
+ if((__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_RX))
+ {
+ /* Clear Underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+ }
+ if(hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+ /* Read Data from DR register */
+ (*pRxData++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear Overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size)
+{
+ uint32_t tmp1 = 0U;
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
+
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
+ {
+ /* Enable I2Sext RXNE and ERR interrupts */
+ __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Enable I2Sx TXE and ERR interrupts */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+ {
+ /* Prepare the First Data before enabling the I2S */
+ if(hi2s->TxXferCount != 0U)
+ {
+ /* Transmit First data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable I2Sext RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ }
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2Sx peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* Enable I2Sext TXE and ERR interrupts */
+ __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Enable I2Sext RXNE and ERR interrupts */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Check if the I2S_MODE_MASTER_RX is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Prepare the First Data before enabling the I2S */
+ if(hi2s->TxXferCount != 0U)
+ {
+ /* Transmit First data */
+ I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable I2Sext TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ }
+ /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size)
+{
+ uint32_t *tmp = NULL;
+ uint32_t tmp1 = 0U;
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
+
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt;
+
+ /* Set the I2S Rx DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
+
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
+
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt;
+
+ /* Set the I2S Tx DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError;
+
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
+ {
+ /* Enable the Rx DMA Stream */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_RXDMAEN);
+
+ /* Enable the Tx DMA Stream */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral after the I2Sext */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+ else
+ {
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+ /* Enable the Tx DMA Stream */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
+
+ /* Enable Tx DMA Request */
+ SET_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_TXDMAEN);
+
+ /* Enable the Rx DMA Stream */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+ /* Enable I2S peripheral before the I2Sext */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
+ * @param hi2s I2S handle
+ * @retval HAL status
+ */
+void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ __IO uint32_t i2ssr = hi2s->Instance->SR ;
+ __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
+
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
+ || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ /* I2S in mode Transmitter -------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ I2SEx_FullDuplexTx_IT(hi2s, I2S_USE_I2S);
+ }
+
+ /* I2Sext in mode Receiver -----------------------------------------------*/
+ if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT);
+ }
+
+ /* I2Sext Overrun error interrupt occured --------------------------------*/
+ if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Clear Overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+
+ /* I2S Underrun error interrupt occured ----------------------------------*/
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Clear underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* I2Sext in mode Transmitter ----------------------------------------------*/
+ if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ I2SEx_FullDuplexTx_IT(hi2s, I2S_USE_I2SEXT);
+ }
+
+ /* I2S in mode Receiver --------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2S);
+ }
+
+ /* I2S Overrun error interrupt occured -------------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+
+ /* I2Sext Underrun error interrupt occured -------------------------------*/
+ if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+}
+
+/**
+ * @brief Tx and Rx Transfer half completed callback
+ * @param hi2s I2S handle
+ * @retval None
+ */
+__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2SEx_TxRxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callback
+ * @param hi2s I2S handle
+ * @retval None
+ */
+__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA I2S transmit receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S transmit receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* if DMA is not configured in DMA_CIRCULAR mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ if (hi2s->hdmarx == hdma)
+ {
+ /* Disable Rx DMA Request */
+ if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) ||\
+ ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ }
+
+ hi2s->RxXferCount = 0U;
+
+ if (hi2s->TxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ }
+
+ if (hi2s->hdmatx == hdma)
+ {
+ /* Disable Tx DMA Request */
+ if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) ||\
+ ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+ }
+ else
+ {
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_TXDMAEN);
+ }
+
+ hi2s->TxXferCount = 0U;
+
+ if (hi2s->RxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx and Tx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
+
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
+ HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+ * @brief Full-Duplex IT handler transmit function
+ * @param hi2s I2S handle
+ * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned
+ * @retval None
+ */
+static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
+{
+ if(i2sUsed == I2S_USE_I2S)
+ {
+ /* Write Data on DR register */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ else
+ {
+ /* Write Data on DR register */
+ I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ /* Disable I2Sext TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+}
+
+/**
+ * @brief Full-Duplex IT handler receive function
+ * @param hi2s I2S handle
+ * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned
+ * @retval None
+ */
+static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
+{
+ if(i2sUsed == I2S_USE_I2S)
+ {
+ /* Read Data from DR register */
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ else
+ {
+ /* Read Data from DR register */
+ (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0U)
+ {
+ /* Disable I2Sext RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ if(hi2s->TxXferCount == 0U)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+}
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s I2S handle
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
+ * @param i2sUsed I2S instance reference
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ if(i2sUsed == I2S_USE_I2S)
+ {
+ /* Wait until flag is reset */
+ while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else /* i2sUsed == I2S_USE_I2SEXT */
+ {
+ /* Wait until flag is reset */
+ while(((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/**
+ * @}
+ */
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,190 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2s_ex.h
+ * @author MCD Application Team
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2S_EX_H
+#define __STM32F4xx_HAL_I2S_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
+/** @addtogroup I2SEx I2SEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
+ * @{
+ */
+
+#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
+
+/** @brief Enable or disable the specified I2SExt peripheral.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
+
+/** @brief Enable or disable the specified I2SExt interrupts.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
+#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__ specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2SExt flag is set or not.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2SExt OVR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
+ tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
+ UNUSED(tmpreg_ovr); \
+ }while(0U)
+/** @brief Clears the I2SExt UDR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg_udr = 0x00U; \
+ tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
+ UNUSED(tmpreg_udr); \
+ }while(0U)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
+ * @{
+ */
+
+/* Extended features functions *************************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size, uint32_t Timeout);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size);
+/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
+void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2S_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2106 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_irda.c
+ * @author MCD Application Team
+ * @brief IRDA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the IrDA SIR ENDEC block (IrDA):
+ * + Initialization and de-initialization methods
+ * + IO operation methods
+ * + Peripheral Control methods
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The IRDA HAL driver can be used as follows:
+
+ (#) Declare a IRDA_HandleTypeDef handle structure.
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
+ (##) Enable the USARTx interface clock.
+ (##) IRDA pins configuration:
+ (+++) Enable the clock for the IRDA GPIOs.
+ (+++) Configure these IRDA pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+ and HAL_IRDA_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+ and HAL_IRDA_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+
+ (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
+ and Mode(Receiver/Transmitter) in the hirda Init structure.
+
+ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_IRDA_MspInit() API.
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+
+ *** DMA mode IO operation ***
+ =============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+
+ *** IRDA HAL driver macros list ***
+ ===================================
+ [..]
+ Below the list of most used macros in IRDA HAL driver.
+
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
+ (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
+ (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
+ (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
+
+ [..]
+ (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IRDA IRDA
+ * @brief HAL IRDA module driver
+ * @{
+ */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup IRDA_Private_Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions
+ * @{
+ */
+static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Functions IrDA Exported Functions
+ * @{
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in IrDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) BaudRate
+ (++) WordLength
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ please refer to Reference manual for possible IRDA frame formats.
+ (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
+ not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
+ specification specifies a minimum of 10 ms delay between transmission and
+ reception (IrDA is a half duplex protocol).
+ (++) Mode: Receiver/transmitter modes
+ (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
+ [..]
+ The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
+ are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and create the associated handle.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the IRDA instance parameters */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+ /* Check the IRDA mode parameter in the IRDA handle */
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
+
+ if(hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_IRDA_MspInit(hirda);
+ }
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
+
+ /* Disable the IRDA peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
+ /* Set the IRDA communication parameters */
+ IRDA_SetConfig(hirda);
+
+ /* In IrDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(hirda->Instance->CR2, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL);
+
+ /* Enable the IRDA peripheral */
+ __HAL_IRDA_ENABLE(hirda);
+
+ /* Set the prescaler */
+ MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+
+ /* Configure the IrDA mode */
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
+
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
+
+ /* Initialize the IRDA state*/
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState= HAL_IRDA_STATE_READY;
+ hirda->RxState= HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the IRDA peripheral
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
+ /* DeInit the low level hardware */
+ HAL_IRDA_MspDeInit(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ hirda->gState = HAL_IRDA_STATE_RESET;
+ hirda->RxState = HAL_IRDA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief IRDA MSP Init.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief IRDA MSP DeInit.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @brief IRDA Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.
+ [..]
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+ While receiving data, transmission should be avoided as the data to be transmitted
+ could be corrupted.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API's are :
+ (++) HAL_IRDA_Transmit()
+ (++) HAL_IRDA_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_IRDA_Transmit_IT()
+ (++) HAL_IRDA_Receive_IT()
+ (++) HAL_IRDA_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_IRDA_Transmit_DMA()
+ (++) HAL_IRDA_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxCpltCallback()
+ (++) HAL_IRDA_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sends an amount of data in blocking mode.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+ while(hirda->TxXferCount > 0U)
+ {
+ hirda->TxXferCount--;
+ if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pData;
+ hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ pData +=2;
+ }
+ else
+ {
+ pData +=1;
+ }
+ }
+ else
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
+ }
+ }
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+ /* Check the remain data to be received */
+ while(hirda->RxXferCount > 0U)
+ {
+ hirda->RxXferCount--;
+ if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pData ;
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
+ pData +=2;
+ }
+ else
+ {
+ *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
+ pData +=1;
+ }
+ }
+ else
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
+ }
+ }
+ }
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in non blocking mode.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the IRDA transmit DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t dmarequest = 0x00U;
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+ if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+ if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Enable the IRDA DMA Tx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer */
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the IRDA DMA Rx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t dmarequest = 0x00U;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
+ */
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+ if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel */
+ if(hirda->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ IRDA_EndTxTransfer(hirda);
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+ if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ IRDA_EndRxTransfer(hirda);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->RxState and hirda->gState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0x00U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0x00U;
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t AbortCplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at IRDA level */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* IRDA Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* IRDA Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ AbortCplt = 0x01U;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if(AbortCplt == 0x01U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+ hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0x00U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0x00U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0x00U;
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0x00U;
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles IRDA interrupt request.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t isrflags = READ_REG(hirda->Instance->SR);
+ uint32_t cr1its = READ_REG(hirda->Instance->CR1);
+ uint32_t cr3its = READ_REG(hirda->Instance->CR3);
+ uint32_t errorflags = 0x00U;
+ uint32_t dmarequest = 0x00U;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+ if(errorflags == RESET)
+ {
+ /* IRDA in mode Receiver -----------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ {
+ /* IRDA parity error interrupt occurred -------------------------------*/
+ if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ }
+
+ /* IRDA noise error interrupt occurred --------------------------------*/
+ if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ }
+
+ /* IRDA frame error interrupt occurred --------------------------------*/
+ if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ }
+
+ /* IRDA Over-Run interrupt occurred -----------------------------------*/
+ if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ }
+ /* Call IRDA Error Call back function if need be -----------------------*/
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ }
+
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ if(((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
+ {
+ /* Blocking error : transfer is aborted
+ Set the IRDA state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ IRDA_EndRxTransfer(hirda);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ }
+ }
+ return;
+ } /* End if some error occurs */
+
+ /* IRDA in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ IRDA_Transmit_IT(hirda);
+ return;
+ }
+
+ /* IRDA in mode Transmitter end --------------------------------------------*/
+ if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ return;
+ }
+}
+
+/**
+ * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+/**
+ * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+/**
+ * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hirda->RxXferCount = 0x00U;
+ hirda->TxXferCount = 0x00U;
+
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmarx != NULL)
+ {
+ if(hirda->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmatx != NULL)
+ {
+ if(hirda->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->TxXferCount = 0x00U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->RxXferCount = 0x00U;
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+}
+
+/**
+ * @brief Tx Transfer complete callbacks.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer complete callbacks.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer complete callbacks.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief IRDA error callbacks.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Transmit Complete callback.
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort ReceiveComplete callback.
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief IRDA State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of IrDA
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
+ (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the IRDA state.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL state
+ */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t temp1 = 0x00U, temp2 = 0x00U;
+ temp1 = hirda->gState;
+ temp2 = hirda->RxState;
+
+ return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the IARDA error code
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA.
+ * @retval IRDA Error Code
+ */
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+ return hirda->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA IRDA transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ hirda->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_IRDA_TxCpltCallback(hirda);
+ }
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_IRDA_TxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ hirda->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ HAL_IRDA_RxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+ uint32_t dmarequest = 0x00U;
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+ if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+ {
+ hirda->TxXferCount = 0U;
+ IRDA_EndTxTransfer(hirda);
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+ if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+ {
+ hirda->RxXferCount = 0U;
+ IRDA_EndRxTransfer(hirda);
+ }
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+ * @brief This function handles IRDA Communication Timeout.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param Flag specifies the IRDA flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+ /**
+ * @brief Send an amount of data in non blocking mode.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+
+ /* Check that a Tx process is ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) hirda->pTxBuffPtr;
+ hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ hirda->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ hirda->pTxBuffPtr += 1U;
+ }
+ }
+ else
+ {
+ hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
+ }
+
+ if(--hirda->TxXferCount == 0U)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Tx process is ended, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ HAL_IRDA_TxCpltCallback(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
+ if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) hirda->pRxBuffPtr;
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
+ hirda->pRxBuffPtr += 2U;
+ }
+ else
+ {
+ *tmp = (uint16_t)(uhdata & (uint16_t)0x00FF);
+ hirda->pRxBuffPtr += 1U;
+ }
+ }
+ else
+ {
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F);
+ }
+ }
+
+ if(--hirda->RxXferCount == 0U)
+ {
+ /* Disable the IRDA Data Register not empty Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
+
+ /* Disable the IRDA Parity Error Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ HAL_IRDA_RxCpltCallback(hirda);
+
+ return HAL_OK;
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configures the IRDA peripheral.
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the parameters */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+ assert_param(IS_IRDA_MODE(hirda->Init.Mode));
+
+ /*-------------------------- IRDA CR2 Configuration ------------------------*/
+ /* Clear STOP[13:12] bits */
+ CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE and RE bits */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE);
+
+ /* Configure the USART Word Length, Parity and mode:
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
+ /* Write to USART CR1 */
+ SET_BIT(hirda->Instance->CR1, (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Clear CTSE and RTSE bits */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_RTSE | USART_CR3_CTSE);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+#if defined(USART6)
+ if((hirda->Instance == USART1) || (hirda->Instance == USART6))
+ {
+ SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
+ }
+#else
+ if(hirda->Instance == USART1)
+ {
+ SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
+ }
+#endif /* USART6 */
+ else
+ {
+ SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,602 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_irda.h
+ * @author MCD Application Team
+ * @brief Header file of IRDA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_IRDA_H
+#define __STM32F4xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+ * @{
+ */
+/**
+ * @brief IRDA Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref IRDA_Word_Length */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref IRDA_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref IRDA_Mode */
+
+ uint8_t Prescaler; /*!< Specifies the Prescaler */
+
+ uint32_t IrDAMode; /*!< Specifies the IrDA mode
+ This parameter can be a value of @ref IRDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+ * @brief HAL IRDA State structures definition
+ * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains IRDA state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef enum
+{
+ HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
+ Value is allowed for gState only */
+ HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+ HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ Value is allowed for gState only */
+ HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
+ Value is allowed for gState only */
+}HAL_IRDA_StateTypeDef;
+
+/**
+ * @brief IRDA handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* USART registers base address */
+
+ IRDA_InitTypeDef Init; /* IRDA communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* IRDA Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* IRDA Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_IRDA_StateTypeDef gState; /* IRDA state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+ __IO HAL_IRDA_StateTypeDef RxState; /* IRDA state information related to Rx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /* IRDA Error code */
+
+}IRDA_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported constants
+ * @{
+ */
+/** @defgroup IRDA_Error_Code IRDA Error Code
+ * @brief IRDA Error Code
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Word_Length IRDA Word Length
+ * @{
+ */
+#define IRDA_WORDLENGTH_8B 0x00000000U
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Parity IRDA Parity
+ * @{
+ */
+#define IRDA_PARITY_NONE 0x00000000U
+#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Mode IRDA Transfer Mode
+ * @{
+ */
+#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
+#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
+#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+ * @{
+ */
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Flags IRDA Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define IRDA_FLAG_TXE 0x00000080U
+#define IRDA_FLAG_TC 0x00000040U
+#define IRDA_FLAG_RXNE 0x00000020U
+#define IRDA_FLAG_IDLE 0x00000010U
+#define IRDA_FLAG_ORE 0x00000008U
+#define IRDA_FLAG_NE 0x00000004U
+#define IRDA_FLAG_FE 0x00000002U
+#define IRDA_FLAG_PE 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * @{
+ */
+#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+
+#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
+
+#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+ * @{
+ */
+
+/** @brief Reset IRDA handle gstate & RxState
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ } while(0U)
+
+/** @brief Flushs the IRDA DR register
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Checks whether the specified IRDA flag is set or not.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_FLAG_TXE: Transmit data register empty flag
+ * @arg IRDA_FLAG_TC: Transmission Complete flag
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
+ * @arg IRDA_FLAG_IDLE: Idle Line detection flag
+ * @arg IRDA_FLAG_ORE: OverRun Error flag
+ * @arg IRDA_FLAG_NE: Noise Error flag
+ * @arg IRDA_FLAG_FE: Framing Error flag
+ * @arg IRDA_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified IRDA pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg IRDA_FLAG_TC: Transmission Complete flag.
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Clear the IRDA PE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0U)
+
+/** @brief Clear the IRDA FE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the IRDA NE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the IRDA ORE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the IRDA IDLE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enables or disables the specified IRDA interrupt.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
+
+/** @brief Checks whether the specified IRDA interrupt has occurred or not.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __IT__ specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
+
+/** @brief Macro to enable the IRDA's one bit sample method
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Macro to disable the IRDA's one bit sample method
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART/USART associated to IRDA Handle
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART/USART associated to IRDA Handle
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+ * @{
+ */
+
+/** @brief IRDA interruptions flag mask
+ *
+ */
+#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
+
+#define IRDA_CR1_REG_INDEX 1U
+#define IRDA_CR2_REG_INDEX 2U
+#define IRDA_CR3_REG_INDEX 3U
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+ ((PARITY) == IRDA_PARITY_EVEN) || \
+ ((PARITY) == IRDA_PARITY_ODD))
+#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+ ((MODE) == IRDA_POWERMODE_NORMAL))
+#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
+
+#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
+#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
+ (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+ (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,256 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_iwdg.c
+ * @author MCD Application Team
+ * @brief IWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
+ * + Initialization and Start functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### IWDG Generic features #####
+ ==============================================================================
+ [..]
+ (+) The IWDG can be started by either software or hardware (configurable
+ through option byte).
+
+ (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
+ if the main clock fails.
+
+ (+) Once the IWDG is started, the LSI is forced ON and both can not be
+ disabled. The counter starts counting down from the reset value (0xFFF).
+ When it reaches the end of count value (0x000) a reset signal is
+ generated (IWDG reset).
+
+ (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+ the IWDG_RLR value is reloaded in the counter and the watchdog reset is
+ prevented.
+
+ (+) The IWDG is implemented in the VDD voltage domain that is still functional
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+ reset occurs.
+
+ (+) Debug mode : When the microcontroller enters debug mode (core halted),
+ the IWDG counter either continues to work normally or stops, depending
+ on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+
+ [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
+ devices provide the capability to measure the LSI frequency (LSI clock
+ connected internally to TIM5 CH4 input capture). The measured value
+ can be used to have an IWDG timeout with an acceptable accuracy.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ clock is forced ON and IWDG counter starts downcounting.
+ (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
+ (++) Configure the IWDG prescaler and counter reload value. This reload
+ value will be loaded in the IWDG counter each time the watchdog is
+ reloaded, then the IWDG will start counting down from this value.
+ (++) wait for status flags to be reset"
+
+ (#) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+
+ *** IWDG HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IWDG HAL driver:
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+ the reload register
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @defgroup IWDG IWDG
+ * @brief IWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+ * @{
+ */
+/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
+ higher prescaler (256), and according to HSI variation, we need to wait at
+ least 6 cycles so 48 ms. */
+#define HAL_IWDG_DEFAULT_TIMEOUT 48U
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @brief Initialization and Start functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Start functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the IWDG according to the specified parameters in the
+ IWDG_InitTypeDef of associated handle.
+ (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+ is reloaded in order to exit function with correct time base.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the IWDG according to the specified parameters in the
+ * IWDG_InitTypeDef and start watchdog. Before exiting function,
+ * watchdog is refreshed in order to have correct time base.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart;
+
+ /* Check the IWDG handle allocation */
+ if(hiwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+
+ /* Enable IWDG. LSI is turned on automaticaly */
+ __HAL_IWDG_START(hiwdg);
+
+ /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+ /* Write to IWDG registers the Prescaler & Reload values to work with */
+ hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+ hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+ /* Check pending flag, if previous update not done, return timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for register to be updated */
+ while(hiwdg->Instance->SR != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Refresh the IWDG.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the IWDG.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,237 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_iwdg.h
+ * @author MCD Application Team
+ * @brief Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_IWDG_H
+#define __STM32F4xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/**
+ * @brief IWDG Handle Structure definition
+ */
+typedef struct
+{
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+}IWDG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the IWDG peripheral.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+ * @brief Reload IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR & IWDG_RLR registers disabled).
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+ * @{
+ */
+/* Initialization/Start functions ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+/**
+ * @brief IWDG Key Register BitMask
+ */
+#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+ * @{
+ */
+
+/**
+ * @brief Enable write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disable write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__ IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+ * @brief Check IWDG prescaler value.
+ * @param __PRESCALER__ IWDG prescaler value
+ * @retval None
+ */
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+ * @brief Check IWDG reload value.
+ * @param __RELOAD__ IWDG reload value
+ * @retval None
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1694 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_lptim.c
+ * @author MCD Application Team
+ * @brief LPTIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Low Power Timer (LPTIM) peripheral:
+ * + Initialization and de-initialization functions.
+ * + Start/Stop operation functions in polling mode.
+ * + Start/Stop operation functions in interrupt mode.
+ * + Reading operation functions.
+ * + Peripheral State functions.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LPTIM HAL driver can be used as follows:
+
+ (#)Initialize the LPTIM low level resources by implementing the
+ HAL_LPTIM_MspInit():
+ (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
+ (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
+ (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
+ (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
+ (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
+
+ (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
+ configures mainly:
+ (##) The instance: LPTIM1.
+ (##) Clock: the counter clock.
+ (+++) Source : it can be either the ULPTIM input (IN1) or one of
+ the internal clock; (APB, LSE or LSI).
+ (+++) Prescaler: select the clock divider.
+ (##) UltraLowPowerClock : To be used only if the ULPTIM is selected
+ as counter clock source.
+ (+++) Polarity: polarity of the active edge for the counter unit
+ if the ULPTIM input is selected.
+ (+++) SampleTime: clock sampling time to configure the clock glitch
+ filter.
+ (##) Trigger: How the counter start.
+ (+++) Source: trigger can be software or one of the hardware triggers.
+ (+++) ActiveEdge : only for hardware trigger.
+ (+++) SampleTime : trigger sampling time to configure the trigger
+ glitch filter.
+ (##) OutputPolarity : 2 opposite polarities are possibles.
+ (##) UpdateMode: specifies whether the update of the autoreload and
+ the compare values is done immediately or after the end of current
+ period.
+
+ (#)Six modes are available:
+
+ (##) PWM Mode: To generate a PWM signal with specified period and pulse,
+ call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
+ mode.
+
+ (##) One Pulse Mode: To generate pulse with specified width in response
+ to a stimulus, call HAL_LPTIM_OnePulse_Start() or
+ HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
+
+ (##) Set once Mode: In this mode, the output changes the level (from
+ low level to high level if the output polarity is configured high, else
+ the opposite) when a compare match occurs. To start this mode, call
+ HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
+ interruption mode.
+
+ (##) Encoder Mode: To use the encoder interface call
+ HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
+ interruption mode.
+
+ (##) Time out Mode: an active edge on one selected trigger input rests
+ the counter. The first trigger event will start the timer, any
+ successive trigger event will reset the counter and the timer will
+ restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
+ HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
+
+ (##) Counter Mode: counter can be used to count external events on
+ the LPTIM Input1 or it can be used to count internal clock cycles.
+ To start this mode, call HAL_LPTIM_Counter_Start() or
+ HAL_LPTIM_Counter_Start_IT() for interruption mode.
+
+ (#) User can stop any process by calling the corresponding API:
+ HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
+ already started in interruption mode.
+
+ (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup LPTIM LPTIM
+ * @brief LPTIM HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private types -------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Types LPTIM Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Defines LPTIM Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/** @defgroup LPTIM_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the LPTIM according to the specified parameters in the
+ LPTIM_InitTypeDef and creates the associated handle.
+ (+) DeInitialize the LPTIM peripheral.
+ (+) Initialize the LPTIM MSP.
+ (+) DeInitialize LPTIM MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the LPTIM according to the specified parameters in the
+ * LPTIM_InitTypeDef and creates the associated handle.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
+{
+ uint32_t tmpcfgr = 0U;
+
+ /* Check the LPTIM handle allocation */
+ if(hlptim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
+ }
+ assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
+ assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ }
+ assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
+ assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
+ assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
+
+ if(hlptim->State == HAL_LPTIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hlptim->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_LPTIM_MspInit(hlptim);
+ }
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Get the LPTIMx CFGR value */
+ tmpcfgr = hlptim->Instance->CFGR;
+
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+ }
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ }
+
+ /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+ LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
+
+ /* Set initialization parameters */
+ tmpcfgr |= (hlptim->Init.Clock.Source |
+ hlptim->Init.Clock.Prescaler |
+ hlptim->Init.OutputPolarity |
+ hlptim->Init.UpdateMode |
+ hlptim->Init.CounterSource);
+
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ hlptim->Init.UltraLowPowerClock.SampleTime);
+ }
+
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Enable External trigger and set the trigger source */
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge |
+ hlptim->Init.Trigger.SampleTime);
+ }
+
+ /* Write to LPTIMx CFGR */
+ hlptim->Instance->CFGR = tmpcfgr;
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the LPTIM peripheral.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the LPTIM handle allocation */
+ if(hlptim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the LPTIM Peripheral Clock */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_LPTIM_MspDeInit(hlptim);
+
+ /* Change the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hlptim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the LPTIM MSP.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes LPTIM MSP.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions
+ * @brief Start-Stop operation functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM Start Stop operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start the PWM mode.
+ (+) Stop the PWM mode.
+ (+) Start the One pulse mode.
+ (+) Stop the One pulse mode.
+ (+) Start the Set once mode.
+ (+) Stop the Set once mode.
+ (+) Start the Encoder mode.
+ (+) Stop the Encoder mode.
+ (+) Start the Timeout mode.
+ (+) Stop the Timeout mode.
+ (+) Start the Counter mode.
+ (+) Stop the Counter mode.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the LPTIM PWM generation.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Reset WAVE bit to set PWM mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM PWM generation.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM PWM generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF
+ * @param Pulse Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Reset WAVE bit to set PWM mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable Autoreload write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Enable Compare write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Enable Autoreload match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Enable Compare match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM PWM generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Disable Autoreload write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Disable Compare write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Disable Autoreload match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Disable Compare match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then disable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Disable external trigger interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM One pulse generation.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Reset WAVE bit to set one pulse mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM One pulse generation.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Reset WAVE bit to set one pulse mode */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+ /* Enable Autoreload write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Enable Compare write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Enable Autoreload match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Enable Compare match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Disable Autoreload write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Disable Compare write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Disable Autoreload match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Disable Compare match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then disable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Disable external trigger interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM in Set once mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Set WAVE bit to enable the set once mode */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in single mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM Set once mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the LPTIM Set once mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Pulse Specifies the compare value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Pulse));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Set WAVE bit to enable the set once mode */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+
+ /* Enable Autoreload write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Enable Compare write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Enable Autoreload match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Enable Compare match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then enable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Enable external trigger interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Start timer in single mode */
+ __HAL_LPTIM_START_SINGLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the LPTIM Set once mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Disable Autoreload write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Disable Compare write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+
+ /* Disable Autoreload match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Disable Compare match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* If external trigger source is used, then disable external trigger interrupt */
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ /* Disable external trigger interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+ }
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Encoder interface.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+ uint32_t tmpcfgr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Get the LPTIMx CFGR value */
+ tmpcfgr = hlptim->Instance->CFGR;
+
+ /* Clear CKPOL bits */
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+ /* Set Input polarity */
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
+
+ /* Write to LPTIMx CFGR */
+ hlptim->Instance->CFGR = tmpcfgr;
+
+ /* Set ENC bit to enable the encoder interface */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Encoder interface.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset ENC bit to disable the encoder interface */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Encoder interface in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+ uint32_t tmpcfgr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Configure edge sensitivity for encoder mode */
+ /* Get the LPTIMx CFGR value */
+ tmpcfgr = hlptim->Instance->CFGR;
+
+ /* Clear CKPOL bits */
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+ /* Set Input polarity */
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
+
+ /* Write to LPTIMx CFGR */
+ hlptim->Instance->CFGR = tmpcfgr;
+
+ /* Set ENC bit to enable the encoder interface */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+ /* Enable "switch to down direction" interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
+
+ /* Enable "switch to up direction" interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Encoder interface in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset ENC bit to disable the encoder interface */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+
+ /* Disable "switch to down direction" interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
+
+ /* Disable "switch to up direction" interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Timeout function. The first trigger event will start the
+ * timer, any successive trigger event will reset the counter and
+ * the timer restarts.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Timeout Specifies the TimeOut value to rest the counter.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Timeout));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Set TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the Timeout value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Timeout function.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Timeout function in interrupt mode. The first trigger
+ * event will start the timer, any successive trigger event will reset
+ * the counter and the timer restarts.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @param Timeout Specifies the TimeOut value to rest the counter.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+ assert_param(IS_LPTIM_PULSE(Timeout));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+ /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+ /* Set TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+
+ /* Enable Compare match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Load the Timeout value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Timeout function in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+
+ /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Reset TIMOUT bit to enable the timeout function */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+
+ /* Disable Compare match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Counter mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ {
+ /* Check if clock is prescaled */
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+ /* Set clock prescaler to 0 */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+ }
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Counter mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the Counter mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
+ * This parameter must be a value between 0x0000 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+ assert_param(IS_LPTIM_PERIOD(Period));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+ /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ {
+ /* Check if clock is prescaled */
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+ /* Set clock prescaler to 0 */
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+ }
+
+ /* Enable Autoreload write complete interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Enable Autoreload match interrupt */
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Start timer in continuous mode */
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the Counter mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ /* Set the LPTIM state */
+ hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+ /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+
+ /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ /* Disable Autoreload write complete interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+
+ /* Disable Autoreload match interrupt */
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+
+ /* Change the TIM state*/
+ hlptim->State= HAL_LPTIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Group3 LPTIM Read operation functions
+ * @brief Read operation functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM Read operation functions #####
+ ==============================================================================
+[..] This section provides LPTIM Reading functions.
+ (+) Read the counter value.
+ (+) Read the period (Auto-reload) value.
+ (+) Read the pulse (Compare)value.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function returns the current counter value.
+ * @param hlptim LPTIM handle
+ * @retval Counter value.
+ */
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ return (hlptim->Instance->CNT);
+}
+
+/**
+ * @brief This function return the current Autoreload (Period) value.
+ * @param hlptim LPTIM handle
+ * @retval Autoreload value.
+ */
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ return (hlptim->Instance->ARR);
+}
+
+/**
+ * @brief This function return the current Compare (Pulse) value.
+ * @param hlptim LPTIM handle
+ * @retval Compare value.
+ */
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+ return (hlptim->Instance->CMP);
+}
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup LPTIM_Group4 LPTIM IRQ handler
+ * @brief LPTIM IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### LPTIM IRQ handler #####
+ ==============================================================================
+[..] This section provides LPTIM IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles LPTIM interrupt request.
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Compare match interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)
+ {
+ /* Clear Compare match flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
+ /* Compare match Callback */
+ HAL_LPTIM_CompareMatchCallback(hlptim);
+ }
+ }
+
+ /* Autoreload match interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)
+ {
+ /* Clear Autoreload match flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
+ /* Autoreload match Callback */
+ HAL_LPTIM_AutoReloadMatchCallback(hlptim);
+ }
+ }
+
+ /* Trigger detected interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)
+ {
+ /* Clear Trigger detected flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
+ /* Trigger detected callback */
+ HAL_LPTIM_TriggerCallback(hlptim);
+ }
+ }
+
+ /* Compare write interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)
+ {
+ /* Clear Compare write flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+ /* Compare write Callback */
+ HAL_LPTIM_CompareWriteCallback(hlptim);
+ }
+ }
+
+ /* Autoreload write interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)
+ {
+ /* Clear Autoreload write flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+ /* Autoreload write Callback */
+ HAL_LPTIM_AutoReloadWriteCallback(hlptim);
+ }
+ }
+
+ /* Direction counter changed from Down to Up interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)
+ {
+ /* Clear Direction counter changed from Down to Up flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
+ /* Direction counter changed from Down to Up Callback */
+ HAL_LPTIM_DirectionUpCallback(hlptim);
+ }
+ }
+
+ /* Direction counter changed from Up to Down interrupt */
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
+ {
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)
+ {
+ /* Clear Direction counter changed from Up to Down flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
+ /* Direction counter changed from Up to Down Callback */
+ HAL_LPTIM_DirectionDownCallback(hlptim);
+ }
+ }
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+}
+
+/**
+ * @brief Compare match callback in non blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Autoreload match callback in non blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Trigger detected callback in non blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Compare write callback in non blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Autoreload write callback in non blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Direction counter changed from Down to Up callback in non blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Direction counter changed from Up to Down callback in non blocking mode
+ * @param hlptim LPTIM handle
+ * @retval None
+ */
+__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Group5 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the LPTIM state.
+ * @param hlptim LPTIM handle
+ * @retval HAL state
+ */
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
+{
+ return hlptim->State;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,761 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_lptim.h
+ * @author MCD Application Team
+ * @brief Header file of LPTIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_LPTIM_H
+#define __STM32F4xx_HAL_LPTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup LPTIM LPTIM
+ * @brief LPTIM HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
+ * @{
+ */
+
+/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line
+ * @{
+ */
+#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
+/**
+ * @}
+ */
+
+/**
+ * @brief LPTIM Clock configuration definition
+ */
+typedef struct
+{
+ uint32_t Source; /*!< Selects the clock source.
+ This parameter can be a value of @ref LPTIM_Clock_Source */
+
+ uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
+ This parameter can be a value of @ref LPTIM_Clock_Prescaler */
+
+}LPTIM_ClockConfigTypeDef;
+
+/**
+ * @brief LPTIM Clock configuration definition
+ */
+typedef struct
+{
+ uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
+ if the ULPTIM input is selected.
+ Note: This parameter is used only when Ultra low power clock source is used.
+ Note: If the polarity is configured on 'both edges', an auxiliary clock
+ (one of the Low power oscillator) must be active.
+ This parameter can be a value of @ref LPTIM_Clock_Polarity */
+
+ uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
+ Note: This parameter is used only when Ultra low power clock source is used.
+ This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
+
+}LPTIM_ULPClockConfigTypeDef;
+
+/**
+ * @brief LPTIM Trigger configuration definition
+ */
+typedef struct
+{
+ uint32_t Source; /*!< Selects the Trigger source.
+ This parameter can be a value of @ref LPTIM_Trigger_Source */
+
+ uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
+ Note: This parameter is used only when an external trigger is used.
+ This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
+
+ uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
+ Note: This parameter is used only when an external trigger is used.
+ This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
+}LPTIM_TriggerConfigTypeDef;
+
+/**
+ * @brief LPTIM Initialization Structure definition
+ */
+typedef struct
+{
+ LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
+
+ LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
+
+ LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
+
+ uint32_t OutputPolarity; /*!< Specifies the Output polarity.
+ This parameter can be a value of @ref LPTIM_Output_Polarity */
+
+ uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare
+ values is done immediately or after the end of current period.
+ This parameter can be a value of @ref LPTIM_Updating_Mode */
+
+ uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
+ or each external event.
+ This parameter can be a value of @ref LPTIM_Counter_Source */
+
+}LPTIM_InitTypeDef;
+
+/**
+ * @brief HAL LPTIM State structure definition
+ */
+typedef enum __HAL_LPTIM_StateTypeDef
+{
+ HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
+}HAL_LPTIM_StateTypeDef;
+
+/**
+ * @brief LPTIM handle Structure definition
+ */
+typedef struct
+{
+ LPTIM_TypeDef *Instance; /*!< Register base address */
+
+ LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
+
+ HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
+
+ HAL_LockTypeDef Lock; /*!< LPTIM locking object */
+
+ __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
+
+}LPTIM_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
+ * @{
+ */
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00U
+#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
+ * @{
+ */
+#define LPTIM_PRESCALER_DIV1 0x00000000U
+#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
+#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
+#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
+#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
+#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
+ * @{
+ */
+
+#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
+#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
+ * @{
+ */
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
+ * @{
+ */
+
+#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
+#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
+ * @{
+ */
+#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
+#define LPTIM_TRIGSOURCE_0 0x00000000U
+#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
+#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
+#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
+#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
+#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
+ * @{
+ */
+#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
+#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
+#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
+ * @{
+ */
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
+#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
+#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
+#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
+ * @{
+ */
+
+#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
+#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
+ * @{
+ */
+
+#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
+#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
+ * @{
+ */
+
+#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
+#define LPTIM_FLAG_UP LPTIM_ISR_UP
+#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
+#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
+#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
+#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
+#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
+ * @{
+ */
+
+#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
+#define LPTIM_IT_UP LPTIM_IER_UPIE
+#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
+#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
+#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
+#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
+#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_Option Register Definition
+ * @{
+ */
+#define LPTIM_OP_PAD_AF 0x00000000U
+#define LPTIM_OP_PAD_PA4 LPTIM_OR_LPT_IN1_RMP_0
+#define LPTIM_OP_PAD_PB9 LPTIM_OR_LPT_IN1_RMP_1
+#define LPTIM_OP_TIM_DAC LPTIM_OR_LPT_IN1_RMP
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset LPTIM handle state
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
+
+/**
+ * @brief Enable/Disable the LPTIM peripheral.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
+#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
+#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
+
+/**
+ * @brief Starts the LPTIM peripheral in Continuous or in single mode.
+ * @param __HANDLE__ DMA handle
+ * @retval None
+ */
+#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
+#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
+
+
+/**
+ * @brief Writes the passed parameter in the Autoreload register.
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Autoreload value
+ * @retval None
+ */
+#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
+
+/**
+ * @brief Writes the passed parameter in the Compare register.
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Compare value
+ * @retval None
+ */
+#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
+
+/**
+ * @brief Checks whether the specified LPTIM flag is set or not.
+ * @param __HANDLE__ LPTIM handle
+ * @param __FLAG__ LPTIM flag to check
+ * This parameter can be a value of:
+ * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
+ * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
+ * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
+ * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
+ * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+ * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
+ * @arg LPTIM_FLAG_CMPM : Compare match Flag.
+ * @retval The state of the specified flag (SET or RESET).
+ */
+#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the specified LPTIM flag.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __FLAG__ LPTIM flag to clear.
+ * This parameter can be a value of:
+ * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
+ * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
+ * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
+ * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
+ * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+ * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
+ * @arg LPTIM_FLAG_CMPM : Compare match Flag.
+ * @retval None.
+ */
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable the specified LPTIM interrupt.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
+ * This parameter can be a value of:
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.
+ * @retval None.
+ */
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+ /**
+ * @brief Disable the specified LPTIM interrupt.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
+ * This parameter can be a value of:
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.
+ * @retval None.
+ */
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+ /**
+ * @brief Checks whether the specified LPTIM interrupt is set or not.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to check.
+ * This parameter can be a value of:
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.
+ * @retval Interrupt status.
+ */
+
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief LPTIM Option Register
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ This parameter can be a value of :
+ * @arg LPTIM_OP_PAD_AF
+ * @arg LPTIM_OP_PAD_PA4
+ * @arg LPTIM_OP_PAD_PB9
+ * @arg LPTIM_OP_TIM_DAC
+ * @retval None
+ */
+#define __HAL_LPTIM_OPTR_CONFIG(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->OR = (__VALUE__))
+
+/**
+ * @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
+ }while(0U)
+
+/**
+ * @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
+ }while(0U)
+
+/**
+ * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* MSP functions *************************************************************/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* Start/Stop operation functions *********************************************/
+/* ################################# PWM Mode ################################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# One Pulse Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Set once Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################### Encoder Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# Time out Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Counter Mode ###############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* Reading operation functions ************************************************/
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+
+/* LPTIM IRQ functions *******************************************************/
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
+
+/* CallBack functions ********************************************************/
+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
+
+/* Peripheral State functions ************************************************/
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Types LPTIM Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
+ * @{
+ */
+
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
+ ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
+
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
+
+#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
+ ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
+
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
+
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
+
+#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+ ((__TRIG__) == LPTIM_TRIGSOURCE_5))
+
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \
+ ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \
+ ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
+
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
+
+#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
+ ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
+ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
+
+#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
+
+#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU)
+
+#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_LPTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1894 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_ltdc.c
+ * @author MCD Application Team
+ * @brief LTDC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the LTDC peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Program the required configuration through the following parameters:
+ the LTDC timing, the horizontal and vertical polarity,
+ the pixel clock polarity, Data Enable polarity and the LTDC background color value
+ using HAL_LTDC_Init() function
+
+ (#) Program the required configuration through the following parameters:
+ the pixel format, the blending factors, input alpha value, the window size
+ and the image size using HAL_LTDC_ConfigLayer() function for foreground
+ or/and background layer.
+
+ (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
+ HAL_LTDC_EnableCLUT functions.
+
+ (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().
+
+ (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
+ and HAL_LTDC_EnableColorKeying functions.
+
+ (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
+ function
+
+ (#) If needed, reconfigure and change the pixel format value, the alpha value
+ value, the window size, the window position and the layer start address
+ for foreground or/and background layer using respectively the following
+ functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
+ HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
+
+ (#) Variant functions with _NoReload post fix allows to set the LTDC configuration/settings without immediate reload.
+ This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
+ then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload
+
+ After calling the _NoReload functions to set different color/format/layer settings,
+ the program can call the function HAL_LTDC_Reload To apply(Reload) these settings.
+ Function HAL_LTDC_Reload can be called with the parameter ReloadType
+ set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
+ Function HAL_LTDC_Reload can be called with the parameter ReloadType
+ set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period,
+ this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
+
+
+ (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
+
+ *** LTDC HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in LTDC HAL driver.
+
+ (+) __HAL_LTDC_ENABLE: Enable the LTDC.
+ (+) __HAL_LTDC_DISABLE: Disable the LTDC.
+ (+) __HAL_LTDC_LAYER_ENABLE: Enable a LTDC Layer.
+ (+) __HAL_LTDC_LAYER_DISABLE: Disable a LTDC Layer.
+ (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
+ (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
+ (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
+
+ [..]
+ (@) You can refer to the LTDC HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup LTDC LTDC
+ * @brief LTDC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+
+#if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LTDC_Exported_Functions LTDC Exported Functions
+ * @{
+ */
+
+/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the LTDC
+ (+) De-initialize the LTDC
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
+{
+ uint32_t tmp = 0U, tmp1 = 0U;
+
+ /* Check the LTDC peripheral state */
+ if(hltdc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
+ assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
+ assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
+ assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
+ assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
+ assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
+ assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
+ assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
+ assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
+ assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
+ assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
+ assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
+ assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
+
+ if(hltdc->State == HAL_LTDC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hltdc->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_LTDC_MspInit(hltdc);
+ }
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Configure the HS, VS, DE and PC polarity */
+ hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
+ hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
+ hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
+
+ /* Set Synchronization size */
+ hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
+ tmp = (hltdc->Init.HorizontalSync << 16U);
+ hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
+
+ /* Set Accumulated Back porch */
+ hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
+ tmp = (hltdc->Init.AccumulatedHBP << 16U);
+ hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
+
+ /* Set Accumulated Active Width */
+ hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
+ tmp = (hltdc->Init.AccumulatedActiveW << 16U);
+ hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
+
+ /* Set Total Width */
+ hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
+ tmp = (hltdc->Init.TotalWidth << 16U);
+ hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
+
+ /* Set the background color value */
+ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
+ tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
+ hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
+ hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
+
+ /* Enable the Transfer Error and FIFO underrun interrupts */
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
+
+ /* Enable LTDC by setting LTDCEN bit */
+ __HAL_LTDC_ENABLE(hltdc);
+
+ /* Initialize the error code */
+ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
+
+ /* Initialize the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initialize the LTDC peripheral.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval None
+ */
+
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
+{
+ /* DeInit the low level hardware */
+ HAL_LTDC_MspDeInit(hltdc);
+
+ /* Initialize the error code */
+ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
+
+ /* Initialize the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the LTDC MSP.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval None
+ */
+__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hltdc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LTDC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-initialize the LTDC MSP.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval None
+ */
+__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hltdc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LTDC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides function allowing to:
+ (+) Handle LTDC interrupt request
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Handle LTDC interrupt request.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval HAL status
+ */
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
+{
+ uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
+ uint32_t itsources = READ_REG(hltdc->Instance->IER);
+
+ /* Transfer Error Interrupt management ***************************************/
+ if(((isrflags & LTDC_ISR_TERRIF) != RESET) && ((itsources & LTDC_IER_TERRIE) != RESET))
+ {
+ /* Disable the transfer Error interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
+
+ /* Clear the transfer error flag */
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
+
+ /* Update error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
+
+ /* Change LTDC state */
+ hltdc->State = HAL_LTDC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ /* Transfer error Callback */
+ HAL_LTDC_ErrorCallback(hltdc);
+ }
+
+ /* FIFO underrun Interrupt management ***************************************/
+ if(((isrflags & LTDC_ISR_FUIF) != RESET) && ((itsources & LTDC_IER_FUIE) != RESET))
+ {
+ /* Disable the FIFO underrun interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
+
+ /* Clear the FIFO underrun flag */
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
+
+ /* Update error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
+
+ /* Change LTDC state */
+ hltdc->State = HAL_LTDC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ /* Transfer error Callback */
+ HAL_LTDC_ErrorCallback(hltdc);
+ }
+
+ /* Line Interrupt management ************************************************/
+ if(((isrflags & LTDC_ISR_LIF) != RESET) && ((itsources & LTDC_IER_LIE) != RESET))
+ {
+ /* Disable the Line interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
+
+ /* Clear the Line interrupt flag */
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
+
+ /* Change LTDC state */
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ /* Line interrupt Callback */
+ HAL_LTDC_LineEventCallback(hltdc);
+ }
+
+ /* Register reload Interrupt management ***************************************/
+ if(((isrflags & LTDC_ISR_RRIF) != RESET) && ((itsources & LTDC_IER_RRIE) != RESET))
+ {
+ /* Disable the register reload interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
+
+ /* Clear the register reload flag */
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
+
+ /* Change LTDC state */
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ /* Register reload interrupt Callback */
+ HAL_LTDC_ReloadEventCallback(hltdc);
+ }
+}
+
+/**
+ * @brief Error LTDC callback.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval None
+ */
+__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hltdc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LTDC_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Line Event callback.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval None
+ */
+__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hltdc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LTDC_LineEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Reload Event callback.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval None
+ */
+__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hltdc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the LTDC foreground or/and background parameters.
+ (+) Set the active layer.
+ (+) Configure the color keying.
+ (+) Configure the C-LUT.
+ (+) Enable / Disable the color keying.
+ (+) Enable / Disable the C-LUT.
+ (+) Update the layer position.
+ (+) Update the layer size.
+ (+) Update pixel format on the fly.
+ (+) Update transparency on the fly.
+ (+) Update address on the fly.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the LTDC Layer according to the specified
+ * parameters in the LTDC_InitTypeDef and create the associated handle.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
+ * the configuration information for the Layer.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+ assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
+ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+ assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+ assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
+ assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+ assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Copy new layer configuration into handle structure */
+ hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
+
+ /* Configure the LTDC Layer */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Initialize the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the color keying.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param RGBValue the color key value
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Configure the default color values */
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Load the color lookup table.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param pCLUT pointer to the color lookup table address.
+ * @param CLUTSize the color lookup table size.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
+{
+ uint32_t tmp = 0U;
+ uint32_t counter = 0U;
+ uint32_t pcounter = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ for(counter = 0U; (counter < CLUTSize); counter++)
+ {
+ if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
+ {
+ tmp = (((counter + 16U*counter) << 24U) | ((uint32_t)(*pCLUT) & 0xFFU) | ((uint32_t)(*pCLUT) & 0xFF00U) | ((uint32_t)(*pCLUT) & 0xFF0000U));
+ }
+ else
+ {
+ tmp = ((counter << 24U) | ((uint32_t)(*pCLUT) & 0xFFU) | ((uint32_t)(*pCLUT) & 0xFF00U) | ((uint32_t)(*pCLUT) & 0xFF0000U));
+ }
+ pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);
+ pCLUT = (uint32_t *)pcounter;
+
+ /* Specifies the C-LUT address and RGB value */
+ LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp;
+ }
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the color keying.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Enable LTDC color keying by setting COLKEN bit */
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the color keying.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Disable LTDC color keying by setting COLKEN bit */
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the color lookup table.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Enable LTDC color lookup table by setting CLUTEN bit */
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the color lookup table.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Disable LTDC color lookup table by setting CLUTEN bit */
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable Dither.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
+{
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Enable Dither by setting DTEN bit */
+ LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable Dither.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
+{
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Disable Dither by setting DTEN bit */
+ LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the LTDC window size.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param XSize LTDC Pixel per line
+ * @param YSize LTDC Line number
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters (Layers parameters)*/
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_CFBLL(XSize));
+ assert_param(IS_LTDC_CFBLNBR(YSize));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* update horizontal stop */
+ pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
+
+ /* update vertical stop */
+ pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
+
+ /* Reconfigures the color frame buffer pitch in byte */
+ pLayerCfg->ImageWidth = XSize;
+
+ /* Reconfigures the frame buffer line number */
+ pLayerCfg->ImageHeight = YSize;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the LTDC window position.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param X0 LTDC window X offset
+ * @param Y0 LTDC window Y offset
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_CFBLL(X0));
+ assert_param(IS_LTDC_CFBLNBR(Y0));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* update horizontal start/stop */
+ pLayerCfg->WindowX0 = X0;
+ pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
+
+ /* update vertical start/stop */
+ pLayerCfg->WindowY0 = Y0;
+ pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reconfigure the pixel format.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param Pixelformat new pixel format value.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* Reconfigure the pixel format */
+ pLayerCfg->PixelFormat = Pixelformat;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reconfigure the layer alpha value.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param Alpha new alpha value.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_ALPHA(Alpha));
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* Reconfigure the Alpha value */
+ pLayerCfg->Alpha = Alpha;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+/**
+ * @brief Reconfigure the frame buffer Address.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param Address new address value.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* Reconfigure the Address */
+ pLayerCfg->FBStartAdress = Address;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Set the Immediate Reload type */
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
+ * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
+ * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
+ * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
+ * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
+ * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+ * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
+{
+ uint32_t tmp = 0U;
+ uint32_t pitchUpdate = 0U;
+ uint32_t pixelFormat = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* get LayerIdx used pixel format */
+ pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
+
+ if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ {
+ tmp = 4U;
+ }
+ else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+ {
+ tmp = 3U;
+ }
+ else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ {
+ tmp = 2U;
+ }
+ else
+ {
+ tmp = 1U;
+ }
+
+ pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
+
+ /* Clear previously set standard pitch */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
+
+ /* Set the Reload type as immediate update of LTDC pitch configured above */
+ LTDC->SRCR |= LTDC_SRCR_IMR;
+
+ /* Set new line pitch value */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
+
+ /* Set the Reload type as immediate update of LTDC pitch configured above */
+ LTDC->SRCR |= LTDC_SRCR_IMR;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Define the position of the line interrupt.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param Line Line Interrupt Position.
+ * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LIPOS(Line));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Disable the Line interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
+
+ /* Set the Line Interrupt position */
+ LTDC->LIPCR = (uint32_t)Line;
+
+ /* Enable the Line interrupt */
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reload LTDC Layers configuration.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param ReloadType This parameter can be one of the following values :
+ * LTDC_RELOAD_IMMEDIATE : Immediate Reload
+ * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking
+ * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_RELOAD(ReloadType));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Enable the Reload interrupt */
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
+
+ /* Apply Reload type */
+ hltdc->Instance->SRCR = ReloadType;
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the LTDC Layer according to the specified without reloading
+ * parameters in the LTDC_InitTypeDef and create the associated handle.
+ * Variant of the function HAL_LTDC_ConfigLayer without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
+ * the configuration information for the Layer.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+ assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
+ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+ assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+ assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
+ assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+ assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Copy new layer configuration into handle structure */
+ hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
+
+ /* Configure the LTDC Layer */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Do not set the Immediate Reload */
+
+ /* Initialize the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the LTDC window size without reloading.
+ * Variant of the function HAL_LTDC_SetWindowSize without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param XSize LTDC Pixel per line
+ * @param YSize LTDC Line number
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters (Layers parameters)*/
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_CFBLL(XSize));
+ assert_param(IS_LTDC_CFBLNBR(YSize));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* update horizontal stop */
+ pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
+
+ /* update vertical stop */
+ pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
+
+ /* Reconfigures the color frame buffer pitch in byte */
+ pLayerCfg->ImageWidth = XSize;
+
+ /* Reconfigures the frame buffer line number */
+ pLayerCfg->ImageHeight = YSize;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the LTDC window position without reloading.
+ * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param X0 LTDC window X offset
+ * @param Y0 LTDC window Y offset
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_CFBLL(X0));
+ assert_param(IS_LTDC_CFBLNBR(Y0));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* update horizontal start/stop */
+ pLayerCfg->WindowX0 = X0;
+ pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
+
+ /* update vertical start/stop */
+ pLayerCfg->WindowY0 = Y0;
+ pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reconfigure the pixel format without reloading.
+ * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains
+ * the configuration information for the LTDC.
+ * @param Pixelformat new pixel format value.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* Reconfigure the pixel format */
+ pLayerCfg->PixelFormat = Pixelformat;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reconfigure the layer alpha value without reloading.
+ * Variant of the function HAL_LTDC_SetAlpha without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param Alpha new alpha value.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_ALPHA(Alpha));
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* Reconfigure the Alpha value */
+ pLayerCfg->Alpha = Alpha;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reconfigure the frame buffer Address without reloading.
+ * Variant of the function HAL_LTDC_SetAddress without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param Address new address value.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
+{
+ LTDC_LayerCfgTypeDef *pLayerCfg;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Get layer configuration from handle structure */
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+ /* Reconfigure the Address */
+ pLayerCfg->FBStartAdress = Address;
+
+ /* Set LTDC parameters */
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
+ * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
+ * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
+ * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
+ * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
+ * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+ * Variant of the function HAL_LTDC_SetPitch without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+ * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
+{
+ uint32_t tmp = 0U;
+ uint32_t pitchUpdate = 0U;
+ uint32_t pixelFormat = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* get LayerIdx used pixel format */
+ pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
+
+ if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ {
+ tmp = 4U;
+ }
+ else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+ {
+ tmp = 3U;
+ }
+ else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ {
+ tmp = 2U;
+ }
+ else
+ {
+ tmp = 1U;
+ }
+
+ pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
+
+ /* Clear previously set standard pitch */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
+
+ /* Set new line pitch value */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Configure the color keying without reloading.
+ * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param RGBValue the color key value
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Configure the default color values */
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the color keying without reloading.
+ * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Enable LTDC color keying by setting COLKEN bit */
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the color keying without reloading.
+ * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Disable LTDC color keying by setting COLKEN bit */
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the color lookup table without reloading.
+ * Variant of the function HAL_LTDC_EnableCLUT without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Disable LTDC color lookup table by setting CLUTEN bit */
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the color lookup table without reloading.
+ * Variant of the function HAL_LTDC_DisableCLUT without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values:
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
+ /* Disable LTDC color lookup table by setting CLUTEN bit */
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
+
+ /* Do not set the Immediate Reload */
+
+ /* Change the LTDC state*/
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the LTDC handle state.
+ (+) Get the LTDC handle error code.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the LTDC handle state.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @retval HAL state
+ */
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
+{
+ return hltdc->State;
+}
+
+/**
+ * @brief Return the LTDC handle error code.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+* @retval LTDC Error Code
+*/
+uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
+{
+ return hltdc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Private_Functions LTDC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configure the LTDC peripheral
+ * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param pLayerCfg Pointer LTDC Layer Configuration structure
+ * @param LayerIdx LTDC Layer index.
+ * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+ * @retval None
+ */
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+{
+ uint32_t tmp = 0U;
+ uint32_t tmp1 = 0U;
+ uint32_t tmp2 = 0U;
+
+ /* Configure the horizontal start and stop position */
+ tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
+
+ /* Configure the vertical start and stop position */
+ tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
+ LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
+ LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
+
+ /* Specifies the pixel format */
+ LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
+ LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
+
+ /* Configure the default color values */
+ tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
+ tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
+ tmp2 = (pLayerCfg->Alpha0 << 24U);
+ LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
+ LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
+
+ /* Specifies the constant alpha value */
+ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
+ LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
+
+ /* Specifies the blending factors */
+ LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
+ LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
+
+ /* Configure the color frame buffer start address */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
+ LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
+
+ if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ {
+ tmp = 4U;
+ }
+ else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+ {
+ tmp = 3U;
+ }
+ else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ {
+ tmp = 2U;
+ }
+ else
+ {
+ tmp = 1U;
+ }
+
+ /* Configure the color frame buffer pitch in byte */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
+
+ /* Configure the frame buffer line number */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
+
+ /* Enable LTDC_Layer by setting LEN bit */
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,647 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_ltdc.h
+ * @author MCD Application Team
+ * @brief Header file of LTDC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_LTDC_H
+#define __STM32F4xx_HAL_LTDC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup LTDC LTDC
+ * @brief LTDC HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Types LTDC Exported Types
+ * @{
+ */
+#define MAX_LAYER 2U
+
+/**
+ * @brief LTDC color structure definition
+ */
+typedef struct
+{
+ uint8_t Blue; /*!< Configures the blue value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint8_t Green; /*!< Configures the green value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint8_t Red; /*!< Configures the red value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint8_t Reserved; /*!< Reserved 0xFF */
+} LTDC_ColorTypeDef;
+
+/**
+ * @brief LTDC Init structure definition
+ */
+typedef struct
+{
+ uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
+ This parameter can be one value of @ref LTDC_HS_POLARITY */
+
+ uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
+ This parameter can be one value of @ref LTDC_VS_POLARITY */
+
+ uint32_t DEPolarity; /*!< configures the data enable polarity.
+ This parameter can be one of value of @ref LTDC_DE_POLARITY */
+
+ uint32_t PCPolarity; /*!< configures the pixel clock polarity.
+ This parameter can be one of value of @ref LTDC_PC_POLARITY */
+
+ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+ uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
+ This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
+
+ uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
+ This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
+
+ uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
+ This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+
+ uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
+ This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
+
+ uint32_t TotalWidth; /*!< configures the total width.
+ This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
+
+ uint32_t TotalHeigh; /*!< configures the total height.
+ This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
+
+ LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
+} LTDC_InitTypeDef;
+
+/**
+ * @brief LTDC Layer structure definition
+ */
+typedef struct
+{
+ uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+ uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
+
+ uint32_t PixelFormat; /*!< Specifies the pixel format.
+ This parameter can be one of value of @ref LTDC_Pixelformat */
+
+ uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t Alpha0; /*!< Configures the default alpha value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t BlendingFactor1; /*!< Select the blending factor 1.
+ This parameter can be one of value of @ref LTDC_BlendingFactor1 */
+
+ uint32_t BlendingFactor2; /*!< Select the blending factor 2.
+ This parameter can be one of value of @ref LTDC_BlendingFactor2 */
+
+ uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
+
+ uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+
+ uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+ LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
+} LTDC_LayerCfgTypeDef;
+
+/**
+ * @brief HAL LTDC State structures definition
+ */
+typedef enum
+{
+ HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */
+ HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */
+ HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
+ HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
+ HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
+}HAL_LTDC_StateTypeDef;
+
+/**
+ * @brief LTDC handle Structure definition
+ */
+typedef struct
+{
+ LTDC_TypeDef *Instance; /*!< LTDC Register base address */
+
+ LTDC_InitTypeDef Init; /*!< LTDC parameters */
+
+ LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
+
+ HAL_LockTypeDef Lock; /*!< LTDC Lock */
+
+ __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
+
+ __IO uint32_t ErrorCode; /*!< LTDC Error code */
+
+} LTDC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
+ * @{
+ */
+
+/** @defgroup LTDC_Error_Code LTDC Error Code
+ * @{
+ */
+#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */
+#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */
+#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */
+#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Layer LTDC Layer
+ * @{
+ */
+#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */
+#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
+ * @{
+ */
+#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */
+#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
+ * @{
+ */
+#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */
+#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
+ * @{
+ */
+#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */
+#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
+ * @{
+ */
+#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */
+#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_SYNC LTDC SYNC
+ * @{
+ */
+#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */
+#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
+ * @{
+ */
+#define LTDC_COLOR 0x000000FFU /*!< Color mask */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
+ * @{
+ */
+#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
+ * @{
+ */
+#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Pixelformat LTDC Pixel format
+ * @{
+ */
+#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Alpha LTDC Alpha
+ * @{
+ */
+#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
+ * @{
+ */
+#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */
+#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
+
+#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
+#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Interrupts LTDC Interrupts
+ * @{
+ */
+#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */
+#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */
+#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */
+#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Flags LTDC Flags
+ * @{
+ */
+#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */
+#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */
+#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */
+#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Reload_Type LTDC Reload Type
+ * @{
+ */
+#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
+#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
+ * @{
+ */
+
+/** @brief Reset LTDC handle state.
+ * @param __HANDLE__ LTDC handle
+ * @retval None
+ */
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
+
+/**
+ * @brief Enable the LTDC.
+ * @param __HANDLE__ LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
+
+/**
+ * @brief Disable the LTDC.
+ * @param __HANDLE__ LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
+
+/**
+ * @brief Enable the LTDC Layer.
+ * @param __HANDLE__ LTDC handle
+ * @param __LAYER__ Specify the layer to be enabled.
+ * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+ * @retval None.
+ */
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
+
+/**
+ * @brief Disable the LTDC Layer.
+ * @param __HANDLE__ LTDC handle
+ * @param __LAYER__ Specify the layer to be disabled.
+ * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+ * @retval None.
+ */
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
+
+/**
+ * @brief Reload immediately all LTDC Layers.
+ * @param __HANDLE__ LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
+
+/**
+ * @brief Reload during vertical blanking period all LTDC Layers.
+ * @param __HANDLE__ LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the LTDC pending flags.
+ * @param __HANDLE__ LTDC handle
+ * @param __FLAG__ Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_FLAG_LI: Line Interrupt flag
+ * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+ * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the LTDC pending flags.
+ * @param __HANDLE__ LTDC handle
+ * @param __FLAG__ Specify the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_FLAG_LI: Line Interrupt flag
+ * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+ * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+ * @retval None
+ */
+#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enables the specified LTDC interrupts.
+ * @param __HANDLE__ LTDC handle
+ * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_IT_LI: Line Interrupt flag
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag
+ * @retval None
+ */
+#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified LTDC interrupts.
+ * @param __HANDLE__ LTDC handle
+ * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_IT_LI: Line Interrupt flag
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag
+ * @retval None
+ */
+#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified LTDC interrupt has occurred or not.
+ * @param __HANDLE__ LTDC handle
+ * @param __INTERRUPT__ Specify the LTDC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg LTDC_IT_LI: Line Interrupt flag
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag
+ * @retval The state of INTERRUPT (SET or RESET).
+ */
+#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+/**
+ * @}
+ */
+
+/* Include LTDC HAL Extension module */
+#include "stm32f4xx_hal_ltdc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LTDC_Exported_Functions
+ * @{
+ */
+/** @addtogroup LTDC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
+void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
+/**
+ * @}
+ */
+
+/** @addtogroup LTDC_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
+/**
+ * @}
+ */
+
+/** @addtogroup LTDC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+
+/**
+ * @}
+ */
+
+/** @addtogroup LTDC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
+uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LTDC_Private_Macros LTDC Private Macros
+ * @{
+ */
+#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
+#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
+#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
+#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
+#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
+#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
+#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
+#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
+#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
+#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
+ ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
+#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
+ ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
+#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
+#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
+#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
+#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
+#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
+#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
+#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
+#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
+#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_SRCR_VBR))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LTDC_Private_Functions LTDC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_LTDC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,160 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_ltdc_ex.c
+ * @author MCD Application Team
+ * @brief LTDC Extension HAL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup LTDCEx LTDCEx
+ * @brief LTDC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the LTDC
+
+@endverbatim
+ * @{
+ */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Retrieve common parameters from DSI Video mode configuration structure
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
+ * the DSI video mode configuration parameters
+ * @note The implementation of this function is taking into account the LTDC
+ * polarities inversion as described in the current LTDC specification
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg)
+{
+ /* Retrieve signal polarities from DSI */
+
+ /* The following polarity is inverted:
+ LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
+
+ /* Note 1 : Code in line w/ Current LTDC specification */
+ hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+ hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
+ hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
+
+ /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
+ /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
+ hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
+ hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
+
+ /* Retrieve vertical timing parameters from DSI */
+ hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
+ hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
+ hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U;
+ hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Retrieve common parameters from DSI Adapted command mode configuration structure
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
+ * the DSI command mode configuration parameters
+ * @note The implementation of this function is taking into account the LTDC
+ * polarities inversion as described in the current LTDC specification
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg)
+{
+ /* Retrieve signal polarities from DSI */
+
+ /* The following polarities are inverted:
+ LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
+ LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
+ LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
+
+ /* Note 1 : Code in line w/ Current LTDC specification */
+ hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+ hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
+ hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
+
+ /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
+ /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
+ hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
+ hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
+
+ return HAL_OK;
+}
+#endif /* STM32F469xx || STM32F479xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DCMI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,100 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_ltdc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of LTDC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_LTDC_EX_H
+#define __STM32F4xx_HAL_LTDC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+#include "stm32f4xx_hal_dsi.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup LTDCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LTDCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup LTDCEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg);
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F469xx || STM32F479xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_LTDC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2602 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_mmc.c
+ * @author MCD Application Team
+ * @brief MMC card HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Secure Digital (MMC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + MMC card Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+ the user in HAL_MMC_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
+ examples.
+ You can easily tailor this configuration according to hardware resources.
+
+ [..]
+ This driver is a generic layered driver for SDMMC memories which uses the HAL
+ SDMMC driver functions to interface with MMC and eMMC cards devices.
+ It is used as follows:
+
+ (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+ (##) SDMMC pins configuration for MMC card
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+ and according to your pin assignment;
+ (##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA()
+ and HAL_MMC_WriteBlocks_DMA() APIs).
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+ (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
+ (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
+ (+++) Configure the SDMMC and DMA interrupt priorities using functions
+ HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
+ (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
+ and __HAL_MMC_DISABLE_IT() inside the communication process.
+ (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
+ and __HAL_MMC_CLEAR_IT()
+ (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
+ and HAL_MMC_WriteBlocks_IT() APIs).
+ (+++) Configure the SDMMC interrupt priorities using function
+ HAL_NVIC_SetPriority();
+ (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
+ and __HAL_MMC_DISABLE_IT() inside the communication process.
+ (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
+ and __HAL_MMC_CLEAR_IT()
+ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
+
+
+ *** MMC Card Initialization and configuration ***
+ ================================================
+ [..]
+ To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
+ SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
+ This function provide the following operations:
+
+ (#) Initialize the SDMMC peripheral interface with defaullt configuration.
+ The initialization process is done at 400KHz. You can change or adapt
+ this frequency by adjusting the "ClockDiv" field.
+ The MMC Card frequency (SDMMC_CK) is computed as follows:
+
+ SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
+
+ In initialization mode and according to the MMC Card standard,
+ make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+ This phase of initialization is done through SDMMC_Init() and
+ SDMMC_PowerState_ON() SDMMC low level APIs.
+
+ (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
+ This phase allows the card initialization and identification
+ and check the MMC Card type (Standard Capacity or High Capacity)
+ The initialization flow is compatible with MMC standard.
+
+ This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
+ of plug-off plug-in.
+
+ (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
+ frequency is set to 24MHz. You can change or adapt this frequency by adjusting
+ the "ClockDiv" field.
+ In transfer mode and according to the MMC Card standard, make sure that the
+ SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+ To be able to use a frequency higher than 24MHz, you should use the SDMMC
+ peripheral in bypass mode. Refer to the corresponding reference manual
+ for more details.
+
+ (#) Select the corresponding MMC Card according to the address read with the step 2.
+
+ (#) Configure the MMC Card in wide bus mode: 4-bits data.
+
+ *** MMC Card Read operation ***
+ ==============================
+ [..]
+ (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+
+ (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the DMA transfer process through the MMC Rx interrupt event.
+
+ (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the IT transfer process through the MMC Rx interrupt event.
+
+ *** MMC Card Write operation ***
+ ===============================
+ [..]
+ (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+
+ (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the DMA transfer process through the MMC Tx interrupt event.
+
+ (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the IT transfer process through the MMC Tx interrupt event.
+
+ *** MMC card status ***
+ ======================
+ [..]
+ (+) The MMC Status contains status bits that are related to the MMC Memory
+ Card proprietary features. To get MMC card status use the HAL_MMC_GetCardStatus().
+
+ *** MMC card information ***
+ ===========================
+ [..]
+ (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
+ It returns useful information about the MMC card such as block size, card type,
+ block number ...
+
+ *** MMC card CSD register ***
+ ============================
+ [..]
+ (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
+ Some of the CSD parameters are useful for card initialization and identification.
+
+ *** MMC card CID register ***
+ ============================
+ [..]
+ (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
+ Some of the CID parameters are useful for card initialization and identification.
+
+ *** MMC HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in MMC HAL driver.
+
+ (+) __HAL_MMC_ENABLE : Enable the MMC device
+ (+) __HAL_MMC_DISABLE : Disable the MMC device
+ (+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer
+ (+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer
+ (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
+ (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
+ (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
+ (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
+
+ [..]
+ (@) You can refer to the MMC HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup MMC
+ * @{
+ */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup MMC_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+ * @{
+ */
+static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
+static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
+static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc);
+static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc);
+static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void MMC_DMAError(DMA_HandleTypeDef *hdma);
+static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma);
+static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup MMC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup MMC_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize the MMC
+ card device to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the MMC according to the specified parameters in the
+ MMC_HandleTypeDef and create the associated handle.
+ * @param hmmc Pointer to the MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
+{
+ /* Check the MMC handle allocation */
+ if(hmmc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance));
+ assert_param(IS_SDIO_CLOCK_EDGE(hmmc->Init.ClockEdge));
+ assert_param(IS_SDIO_CLOCK_BYPASS(hmmc->Init.ClockBypass));
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
+ assert_param(IS_SDIO_BUS_WIDE(hmmc->Init.BusWide));
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
+ assert_param(IS_SDIO_CLKDIV(hmmc->Init.ClockDiv));
+
+ if(hmmc->State == HAL_MMC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hmmc->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_MMC_MspInit(hmmc);
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize the Card parameters */
+ HAL_MMC_InitCard(hmmc);
+
+ /* Initialize the error code */
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the MMC operation */
+ hmmc->Context = MMC_CONTEXT_NONE;
+
+ /* Initialize the MMC state */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MMC Card.
+ * @param hmmc Pointer to MMC handle
+ * @note This function initializes the MMC card. It could be used when a card
+ re-initialization is needed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ MMC_InitTypeDef Init;
+
+ /* Default SDMMC peripheral configuration for MMC card initialization */
+ Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+ Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+ Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+ Init.BusWide = SDIO_BUS_WIDE_1B;
+ Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+ Init.ClockDiv = SDIO_INIT_CLK_DIV;
+
+ /* Initialize SDMMC peripheral interface with default configuration */
+ SDIO_Init(hmmc->Instance, Init);
+
+ /* Disable SDMMC Clock */
+ __HAL_MMC_DISABLE(hmmc);
+
+ /* Set Power State to ON */
+ SDIO_PowerState_ON(hmmc->Instance);
+
+ /* Enable SDMMC Clock */
+ __HAL_MMC_ENABLE(hmmc);
+
+ /* Required power up waiting time before starting the SD initialization
+ sequence */
+ HAL_Delay(2U);
+
+ /* Identify card operating voltage */
+ errorstate = MMC_PowerON(hmmc);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ /* Card initialization */
+ errorstate = MMC_InitCard(hmmc);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initializes the MMC card.
+ * @param hmmc Pointer to MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
+{
+ /* Check the MMC handle allocation */
+ if(hmmc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance));
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Set SD power state to off */
+ MMC_PowerOFF(hmmc);
+
+ /* De-Initialize the MSP layer */
+ HAL_MMC_MspDeInit(hmmc);
+
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_RESET;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the MMC MSP.
+ * @param hmmc Pointer to MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MMC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize MMC MSP.
+ * @param hmmc Pointer to MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MMC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup MMC_Exported_Functions_Group2
+ * @brief Data transfer functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the data
+ transfer from/to MMC card.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc Pointer to MMC handle
+ * @param pData pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of MMC blocks to read
+ * @param Timeout Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U, *tempbuff = (uint32_t *)pData;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ /* Read block(s) in polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Poll on SDMMC flags */
+#ifdef SDIO_STA_STBITERR
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
+ {
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ *(tempbuff + count) = SDIO_ReadFIFO(hmmc->Instance);
+ }
+ tempbuff += 8U;
+ }
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State= HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send stop transmission command in case of multiblock read */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get error state */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Empty FIFO if there is still any data */
+ while ((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXDAVL)))
+ {
+ *tempbuff = SDIO_ReadFIFO(hmmc->Instance);
+ tempbuff++;
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State= HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Allows to write block(s) to a specified address in a card. The Data
+ * transfer is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc Pointer to MMC handle
+ * @param pData pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of MMC blocks to write
+ * @param Timeout Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U;
+ uint32_t *tempbuff = (uint32_t *)pData;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ /* Write block(s) in polling mode */
+#ifdef SDIO_STA_STBITERR
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
+ {
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE))
+ {
+ /* Write data to SDIO Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ SDIO_WriteFIFO(hmmc->Instance, (tempbuff + count));
+ }
+ tempbuff += 8U;
+ }
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send stop transmission command in case of multiblock write */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get error state */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the IT transfer process through the MMC Rx
+ * interrupt event.
+ * @param hmmc Pointer to MMC handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ hmmc->pRxBuffPtr = (uint32_t *)pData;
+ hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Read Blocks in IT mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the IT transfer process through the MMC Tx
+ * interrupt event.
+ * @param hmmc Pointer to MMC handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ hmmc->pTxBuffPtr = (uint32_t *)pData;
+ hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ /* Enable transfer interrupts */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the DMA transfer process through the MMC Rx
+ * interrupt event.
+ * @param hmmc Pointer MMC handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+#ifdef SDIO_STA_STBITER
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+#endif /* SDIO_STA_STBITERR */
+
+ /* Set the DMA transfer complete callback */
+ hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hmmc->hdmarx->XferErrorCallback = MMC_DMAError;
+
+ /* Set the DMA Abort callback */
+ hmmc->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+
+ /* Enable MMC DMA transfer */
+ __HAL_MMC_DMA_ENABLE(hmmc);
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Read Blocks in DMA mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the DMA transfer process through the MMC Tx
+ * interrupt event.
+ * @param hmmc Pointer to MMC handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ /* Enable MMC Error interrupts */
+#ifdef SDIO_STA_STBITER
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
+#endif /* SDIO_STA_STBITERR */
+
+ /* Set the DMA transfer complete callback */
+ hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hmmc->hdmatx->XferErrorCallback = MMC_DMAError;
+
+ /* Set the DMA Abort callback */
+ hmmc->hdmatx->XferAbortCallback = NULL;
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Enable SDIO DMA transfer */
+ __HAL_MMC_DMA_ENABLE(hmmc);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Erases the specified memory area of the given MMC card.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc Pointer to MMC handle
+ * @param BlockStartAdd Start Block address
+ * @param BlockEndAdd End Block address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if(BlockEndAdd < BlockStartAdd)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(BlockEndAdd > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Check if the card command class supports erase command */
+ if(((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE) == 0U)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ if((SDIO_GetResponse(hmmc->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockStartAdd *= 512U;
+ BlockEndAdd *= 512U;
+ }
+
+ /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
+ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, BlockStartAdd);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
+ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, BlockEndAdd);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send CMD38 ERASE */
+ errorstate = SDMMC_CmdErase(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles MMC card interrupt request.
+ * @param hmmc Pointer to MMC handle
+ * @retval None
+ */
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ /* Check for SDIO interrupt flags */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DATAEND) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_DATAEND);
+
+#ifdef SDIO_STA_STBITERR
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR);
+#endif
+
+ if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ {
+ if(((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+ if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
+ {
+ HAL_MMC_RxCpltCallback(hmmc);
+ }
+ else
+ {
+ HAL_MMC_TxCpltCallback(hmmc);
+ }
+ }
+ else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
+ {
+ if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+ if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
+ {
+ /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+ in the MMC DCTRL register */
+ hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ HAL_MMC_TxCpltCallback(hmmc);
+ }
+ }
+ }
+
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXFIFOHE) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_TXFIFOHE);
+
+ MMC_Write_IT(hmmc);
+ }
+
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXFIFOHF) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_RXFIFOHF);
+
+ MMC_Read_IT(hmmc);
+ }
+
+#ifdef SDIO_STA_STBITERR
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET)
+ {
+ /* Set Error code */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_STBITERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ }
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR);
+
+ /* Disable all interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR);
+
+ if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
+ {
+ /* Abort the MMC DMA Streams */
+ if(hmmc->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
+ {
+ MMC_DMATxAbort(hmmc->hdmatx);
+ }
+ }
+ else if(hmmc->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
+ {
+ MMC_DMARxAbort(hmmc->hdmarx);
+ }
+ }
+ else
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ }
+ else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ {
+ /* Set the MMC state to ready to be able to start again the process */
+ hmmc->State = HAL_MMC_STATE_READY;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+#else /* SDIO_STA_STBITERR not defined */
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR) != RESET)
+ {
+ /* Set Error code */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ }
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ /* Disable all interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
+ {
+ /* Abort the MMC DMA Streams */
+ if(hmmc->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
+ {
+ MMC_DMATxAbort(hmmc->hdmatx);
+ }
+ }
+ else if(hmmc->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
+ {
+ MMC_DMARxAbort(hmmc->hdmarx);
+ }
+ }
+ else
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ }
+ else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ {
+ /* Set the MMC state to ready to be able to start again the process */
+ hmmc->State = HAL_MMC_STATE_READY;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+#endif /* SDIO_STA_STBITERR */
+}
+
+/**
+ * @brief return the MMC state
+ * @param hmmc Pointer to mmc handle
+ * @retval HAL state
+ */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
+{
+ return hmmc->State;
+}
+
+/**
+* @brief Return the MMC error code
+* @param hmmc Pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information.
+* @retval MMC Error Code
+*/
+uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
+{
+ return hmmc->ErrorCode;
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hmmc Pointer to MMC handle
+ * @retval None
+ */
+ __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hmmc Pointer MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief MMC error callbacks
+ * @param hmmc Pointer MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief MMC Abort callbacks
+ * @param hmmc Pointer MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_ErrorCallback can be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup MMC_Exported_Functions_Group3
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the MMC card
+ operations and get the related information
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CID register.
+ * @param hmmc Pointer to MMC handle
+ * @param pCID Pointer to a HAL_MMC_CIDTypedef structure that
+ * contains all CID register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
+{
+ uint32_t tmp = 0U;
+
+ /* Byte 0 */
+ tmp = (uint8_t)((hmmc->CID[0U] & 0xFF000000U) >> 24U);
+ pCID->ManufacturerID = tmp;
+
+ /* Byte 1 */
+ tmp = (uint8_t)((hmmc->CID[0U] & 0x00FF0000U) >> 16U);
+ pCID->OEM_AppliID = tmp << 8U;
+
+ /* Byte 2 */
+ tmp = (uint8_t)((hmmc->CID[0U] & 0x000000FF00U) >> 8U);
+ pCID->OEM_AppliID |= tmp;
+
+ /* Byte 3 */
+ tmp = (uint8_t)(hmmc->CID[0U] & 0x000000FFU);
+ pCID->ProdName1 = tmp << 24U;
+
+ /* Byte 4 */
+ tmp = (uint8_t)((hmmc->CID[1U] & 0xFF000000U) >> 24U);
+ pCID->ProdName1 |= tmp << 16U;
+
+ /* Byte 5 */
+ tmp = (uint8_t)((hmmc->CID[1U] & 0x00FF0000U) >> 16U);
+ pCID->ProdName1 |= tmp << 8U;
+
+ /* Byte 6 */
+ tmp = (uint8_t)((hmmc->CID[1U] & 0x0000FF00U) >> 8U);
+ pCID->ProdName1 |= tmp;
+
+ /* Byte 7 */
+ tmp = (uint8_t)(hmmc->CID[1U] & 0x000000FFU);
+ pCID->ProdName2 = tmp;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hmmc->CID[2U] & 0xFF000000U) >> 24U);
+ pCID->ProdRev = tmp;
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hmmc->CID[2U] & 0x00FF0000U) >> 16U);
+ pCID->ProdSN = tmp << 24U;
+
+ /* Byte 10 */
+ tmp = (uint8_t)((hmmc->CID[2U] & 0x0000FF00U) >> 8U);
+ pCID->ProdSN |= tmp << 16U;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hmmc->CID[2U] & 0x000000FFU);
+ pCID->ProdSN |= tmp << 8U;
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hmmc->CID[3U] & 0xFF000000U) >> 24U);
+ pCID->ProdSN |= tmp;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hmmc->CID[3U] & 0x00FF0000U) >> 16U);
+ pCID->Reserved1 |= (tmp & 0xF0U) >> 4U;
+ pCID->ManufactDate = (tmp & 0x0FU) << 8U;
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hmmc->CID[3U] & 0x0000FF00U) >> 8U);
+ pCID->ManufactDate |= tmp;
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hmmc->CID[3U] & 0x000000FFU);
+ pCID->CID_CRC = (tmp & 0xFEU) >> 1U;
+ pCID->Reserved2 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CSD register.
+ * @param hmmc Pointer to MMC handle
+ * @param pCSD Pointer to a HAL_MMC_CardInfoTypeDef structure that
+ * contains all CSD register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
+{
+ uint32_t tmp = 0U;
+
+ /* Byte 0 */
+ tmp = (hmmc->CSD[0U] & 0xFF000000U) >> 24U;
+ pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U);
+ pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
+ pCSD->Reserved1 = tmp & 0x03U;
+
+ /* Byte 1 */
+ tmp = (hmmc->CSD[0U] & 0x00FF0000U) >> 16U;
+ pCSD->TAAC = (uint8_t)tmp;
+
+ /* Byte 2 */
+ tmp = (hmmc->CSD[0U] & 0x0000FF00U) >> 8U;
+ pCSD->NSAC = (uint8_t)tmp;
+
+ /* Byte 3 */
+ tmp = hmmc->CSD[0U] & 0x000000FFU;
+ pCSD->MaxBusClkFrec = (uint8_t)tmp;
+
+ /* Byte 4 */
+ tmp = (hmmc->CSD[1U] & 0xFF000000U) >> 24U;
+ pCSD->CardComdClasses = (uint16_t)(tmp << 4U);
+
+ /* Byte 5 */
+ tmp = (hmmc->CSD[1U] & 0x00FF0000U) >> 16U;
+ pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U);
+ pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU);
+
+ /* Byte 6 */
+ tmp = (hmmc->CSD[1U] & 0x0000FF00U) >> 8U;
+ pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U);
+ pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
+ pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
+ pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U);
+ pCSD->Reserved2 = 0; /*!< Reserved */
+
+ pCSD->DeviceSize = (tmp & 0x03U) << 10U;
+
+ /* Byte 7 */
+ tmp = (uint8_t)(hmmc->CSD[1U] & 0x000000FFU);
+ pCSD->DeviceSize |= (tmp) << 2U;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hmmc->CSD[2U] & 0xFF000000U) >> 24U);
+ pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U;
+
+ pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
+ pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U);
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hmmc->CSD[2U] & 0x00FF0000U) >> 16U);
+ pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
+ pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
+ pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U;
+ /* Byte 10 */
+ tmp = (uint8_t)((hmmc->CSD[2] & 0x0000FF00U) >> 8U);
+ pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U;
+
+ hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
+ hmmc->MmcCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U));
+ hmmc->MmcCard.BlockSize = 1U << (pCSD->RdBlockLen);
+
+ hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
+ hmmc->MmcCard.LogBlockSize = 512U;
+
+ pCSD->EraseGrSize = (tmp & 0x40U) >> 6U;
+ pCSD->EraseGrMul = (tmp & 0x3FU) << 1U;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hmmc->CSD[2U] & 0x000000FFU);
+ pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U;
+ pCSD->WrProtectGrSize = (tmp & 0x7FU);
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hmmc->CSD[3U] & 0xFF000000U) >> 24U);
+ pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U;
+ pCSD->ManDeflECC = (tmp & 0x60U) >> 5U;
+ pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U;
+ pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hmmc->CSD[3U] & 0x00FF0000U) >> 16U);
+ pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U;
+ pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
+ pCSD->Reserved3 = 0U;
+ pCSD->ContentProtectAppli = (tmp & 0x01U);
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hmmc->CSD[3U] & 0x0000FF00U) >> 8U);
+ pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U;
+ pCSD->CopyFlag = (tmp & 0x40U) >> 6U;
+ pCSD->PermWrProtect = (tmp & 0x20U) >> 5U;
+ pCSD->TempWrProtect = (tmp & 0x10U) >> 4U;
+ pCSD->FileFormat = (tmp & 0x0CU) >> 2U;
+ pCSD->ECC = (tmp & 0x03U);
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hmmc->CSD[3U] & 0x000000FFU);
+ pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U;
+ pCSD->Reserved4 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the MMC card info.
+ * @param hmmc Pointer to MMC handle
+ * @param pCardInfo Pointer to the HAL_MMC_CardInfoTypeDef structure that
+ * will contain the MMC card status information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
+{
+ pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType);
+ pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class);
+ pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd);
+ pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr);
+ pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize);
+ pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
+ pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables wide bus operation for the requested card if supported by
+ * card.
+ * @param hmmc Pointer to MMC handle
+ * @param WideMode Specifies the MMC card wide bus mode
+ * This parameter can be one of the following values:
+ * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
+ * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
+ * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
+{
+ __IO uint32_t count = 0U;
+ SDIO_InitTypeDef Init;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t response = 0U, busy = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_BUS_WIDE(WideMode));
+
+ /* Chnage Satte */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Update Clock for Bus mode update */
+ Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+ Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+ Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+ Init.ClockDiv = SDIO_INIT_CLK_DIV;
+ /* Initialize SDIO*/
+ SDIO_Init(hmmc->Instance, Init);
+
+ if(WideMode == SDIO_BUS_WIDE_8B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ else if(WideMode == SDIO_BUS_WIDE_4B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ else if(WideMode == SDIO_BUS_WIDE_1B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ else
+ {
+ /* WideMode is not a valid argument*/
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ }
+
+ /* Check for switch error and violation of the trial number of sending CMD 13 */
+ while(busy == 0U)
+ {
+ if(count++ == SDMMC_MAX_TRIAL)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ return HAL_ERROR;
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+
+ /* Get operating voltage*/
+ busy = (((response >> 7U) == 1U) ? 0U : 1U);
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_DATATIMEOUT;
+ while((response & 0x00000100U) == 0U)
+ {
+ if(count-- == 0U)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ return HAL_ERROR;
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+ }
+
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Configure the SDIO peripheral */
+ Init.ClockEdge = hmmc->Init.ClockEdge;
+ Init.ClockBypass = hmmc->Init.ClockBypass;
+ Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
+ Init.ClockDiv = hmmc->Init.ClockDiv;
+ SDIO_Init(hmmc->Instance, Init);
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Gets the current mmc card data state.
+ * @param hmmc pointer to MMC handle
+ * @retval Card state
+ */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardStateTypeDef cardstate = HAL_MMC_CARD_TRANSFER;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t resp1 = 0U;
+
+ errorstate = MMC_SendStatus(hmmc, &resp1);
+ if(errorstate != HAL_OK)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+ cardstate = (HAL_MMC_CardStateTypeDef)((resp1 >> 9U) & 0x0FU);
+
+ return cardstate;
+}
+
+/**
+ * @brief Abort the current transfer and disable the MMC.
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information for MMC module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
+ {
+ /* Disable the MMC DMA request */
+ hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Abort the MMC DMA Tx Stream */
+ if(hmmc->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hmmc->hdmatx);
+ }
+ /* Abort the MMC DMA Rx Stream */
+ if(hmmc->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hmmc->hdmarx);
+ }
+ }
+
+ hmmc->State = HAL_MMC_STATE_READY;
+ CardState = HAL_MMC_GetCardState(hmmc);
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
+ }
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the current transfer and disable the MMC (IT mode).
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information for MMC module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
+ {
+ /* Disable the MMC DMA request */
+ hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Abort the MMC DMA Tx Stream */
+ if(hmmc->hdmatx != NULL)
+ {
+ hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
+ if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
+ {
+ hmmc->hdmatx = NULL;
+ }
+ }
+ /* Abort the MMC DMA Rx Stream */
+ if(hmmc->hdmarx != NULL)
+ {
+ hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
+ if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
+ {
+ hmmc->hdmarx = NULL;
+ }
+ }
+ }
+
+ /* No transfer ongoing on both DMA channels*/
+ if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL))
+ {
+ CardState = HAL_MMC_GetCardState(hmmc);
+ hmmc->State = HAL_MMC_STATE_READY;
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
+ }
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup MMC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA MMC transmit process complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+
+ /* Enable DATAEND Interrupt */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DATAEND));
+}
+
+/**
+ * @brief DMA MMC receive process complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ /* Send stop command in multiblock write */
+ if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+
+ /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+ in the MMC DCTRL register */
+ hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ HAL_MMC_RxCpltCallback(hmmc);
+}
+
+/**
+ * @brief DMA MMC communication error callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void MMC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+ HAL_MMC_CardStateTypeDef CardState;
+
+ if((hmmc->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hmmc->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
+ {
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ /* Disable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
+ CardState = HAL_MMC_GetCardState(hmmc);
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+ }
+
+ hmmc->State= HAL_MMC_STATE_READY;
+ }
+
+ HAL_MMC_ErrorCallback(hmmc);
+}
+
+/**
+ * @brief DMA MMC Tx Abort callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+ HAL_MMC_CardStateTypeDef CardState;
+
+ if(hmmc->hdmatx != NULL)
+ {
+ hmmc->hdmatx = NULL;
+ }
+
+ /* All DMA channels are aborted */
+ if(hmmc->hdmarx == NULL)
+ {
+ CardState = HAL_MMC_GetCardState(hmmc);
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ else
+ {
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+ }
+}
+
+/**
+ * @brief DMA MMC Rx Abort callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+ HAL_MMC_CardStateTypeDef CardState;
+
+ if(hmmc->hdmarx != NULL)
+ {
+ hmmc->hdmarx = NULL;
+ }
+
+ /* All DMA channels are aborted */
+ if(hmmc->hdmatx == NULL)
+ {
+ CardState = HAL_MMC_GetCardState(hmmc);
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ else
+ {
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+ }
+}
+
+
+/**
+ * @brief Initializes the mmc card.
+ * @param hmmc Pointer to MMC handle
+ * @retval MMC Card error state
+ */
+static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardCSDTypeDef CSD;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint16_t mmc_rca = 1;
+
+ /* Check the power State */
+ if(SDIO_GetPowerState(hmmc->Instance) == 0U)
+ {
+ /* Power off */
+ return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+
+ /* Send CMD2 ALL_SEND_CID */
+ errorstate = SDMMC_CmdSendCID(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card identification number data */
+ hmmc->CID[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+ hmmc->CID[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2);
+ hmmc->CID[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
+ hmmc->CID[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
+ }
+
+ /* Send CMD3 SET_REL_ADDR with argument 0 */
+ /* MMC Card publishes its RCA. */
+ errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Get the MMC card RCA */
+ hmmc->MmcCard.RelCardAdd = mmc_rca;
+
+ /* Send CMD9 SEND_CSD with argument as card's RCA */
+ errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card Specific Data */
+ hmmc->CSD[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+ hmmc->CSD[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2);
+ hmmc->CSD[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
+ hmmc->CSD[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
+ }
+
+ /* Get the Card Class */
+ hmmc->MmcCard.Class = (SDIO_GetResponse(hmmc->Instance, SDIO_RESP2) >> 20U);
+
+ /* Get CSD parameters */
+ HAL_MMC_GetCardCSD(hmmc, &CSD);
+
+ /* Select the Card */
+ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Configure SDIO peripheral interface */
+ SDIO_Init(hmmc->Instance, hmmc->Init);
+
+ /* All cards are initialized */
+ return HAL_MMC_ERROR_NONE;
+}
+
+/**
+ * @brief Enquires cards about their operating voltage and configures clock
+ * controls and stores MMC information that will be needed in future
+ * in the MMC handle.
+ * @param hmmc Pointer to MMC handle
+ * @retval error state
+ */
+static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
+{
+ __IO uint32_t count = 0U;
+ uint32_t response = 0U, validvoltage = 0U;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ /* CMD0: GO_IDLE_STATE */
+ errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ while(validvoltage == 0U)
+ {
+ if(count++ == SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_MMC_ERROR_INVALID_VOLTRANGE;
+ }
+
+ /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
+ errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+ }
+
+ /* When power routine is finished and command returns valid voltage */
+ if ((response & eMMC_HIGH_VOLTAGE_RANGE) == MMC_HIGH_VOLTAGE_RANGE)
+ {
+ /* When voltage range of the card is within 2.7V and 3.6V */
+ hmmc->MmcCard.CardType = MMC_HIGH_VOLTAGE_CARD;
+ }
+ else
+ {
+ /* When voltage range of the card is within 1.65V and 1.95V or 2.7V and 3.6V */
+ hmmc->MmcCard.CardType = MMC_DUAL_VOLTAGE_CARD;
+ }
+
+ return HAL_MMC_ERROR_NONE;
+}
+
+/**
+ * @brief Turns the SDIO output signals off.
+ * @param hmmc Pointer to MMC handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
+{
+ /* Set Power State to OFF */
+ SDIO_PowerState_OFF(hmmc->Instance);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the current card's status.
+ * @param hmmc Pointer to MMC handle
+ * @param pCardStatus pointer to the buffer that will contain the MMC card
+ * status (Card Status register)
+ * @retval error state
+ */
+static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(pCardStatus == NULL)
+ {
+ return HAL_MMC_ERROR_PARAM;
+ }
+
+ /* Send Status command */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ /* Get MMC card status */
+ *pCardStatus = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+
+ return HAL_MMC_ERROR_NONE;
+}
+
+/**
+ * @brief Wrap up reading in non-blocking mode.
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t count = 0U;
+ uint32_t* tmp;
+
+ tmp = (uint32_t*)hmmc->pRxBuffPtr;
+
+ /* Read data from SDMMC Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ *(tmp + count) = SDIO_ReadFIFO(hmmc->Instance);
+ }
+
+ hmmc->pRxBuffPtr += 8U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Wrap up writing in non-blocking mode.
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t count = 0U;
+ uint32_t* tmp;
+
+ tmp = (uint32_t*)hmmc->pTxBuffPtr;
+
+ /* Write data to SDMMC Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ SDIO_WriteFIFO(hmmc->Instance, (tmp + count));
+ }
+
+ hmmc->pTxBuffPtr += 8U;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,724 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_mmc.h
+ * @author MCD Application Team
+ * @brief Header file of MMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_MMC_H
+#define __STM32F4xx_HAL_MMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup MMC MMC
+ * @brief MMC HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_Types MMC Exported Types
+ * @{
+ */
+
+/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
+ HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
+ HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
+ HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
+ HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
+ HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
+ HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
+ HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
+}HAL_MMC_StateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_CARD_READY = 0x00000001U, /*!< Card state is ready */
+ HAL_MMC_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
+ HAL_MMC_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
+ HAL_MMC_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
+ HAL_MMC_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
+ HAL_MMC_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
+ HAL_MMC_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
+ HAL_MMC_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
+ HAL_MMC_CARD_ERROR = 0x000000FFU /*!< Card response Error */
+}HAL_MMC_CardStateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
+ * @{
+ */
+#define MMC_InitTypeDef SDIO_InitTypeDef
+#define MMC_TypeDef SDIO_TypeDef
+
+/**
+ * @brief MMC Card Information Structure definition
+ */
+typedef struct
+{
+ uint32_t CardType; /*!< Specifies the card Type */
+
+ uint32_t Class; /*!< Specifies the class of the card class */
+
+ uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
+
+ uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
+
+ uint32_t BlockSize; /*!< Specifies one block size in bytes */
+
+ uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
+
+ uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
+
+}HAL_MMC_CardInfoTypeDef;
+
+/**
+ * @brief MMC handle Structure definition
+ */
+typedef struct
+{
+ MMC_TypeDef *Instance; /*!< MMC registers base address */
+
+ MMC_InitTypeDef Init; /*!< MMC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< MMC locking object */
+
+ uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
+
+ uint32_t TxXferSize; /*!< MMC Tx Transfer size */
+
+ uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
+
+ uint32_t RxXferSize; /*!< MMC Rx Transfer size */
+
+ __IO uint32_t Context; /*!< MMC transfer context */
+
+ __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
+
+ __IO uint32_t ErrorCode; /*!< MMC Card Error codes */
+
+ DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
+
+ HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
+
+ uint32_t CSD[4U]; /*!< MMC card specific data table */
+
+ uint32_t CID[4U]; /*!< MMC card identification number table */
+
+}MMC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t CSDStruct; /*!< CSD structure */
+ __IO uint8_t SysSpecVersion; /*!< System specification version */
+ __IO uint8_t Reserved1; /*!< Reserved */
+ __IO uint8_t TAAC; /*!< Data read access time 1 */
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ __IO uint16_t CardComdClasses; /*!< Card command classes */
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ __IO uint8_t DSRImpl; /*!< DSR implemented */
+ __IO uint8_t Reserved2; /*!< Reserved */
+ __IO uint32_t DeviceSize; /*!< Device Size */
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ __IO uint8_t EraseGrSize; /*!< Erase group size */
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ __IO uint8_t Reserved3; /*!< Reserved */
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
+ __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
+ __IO uint8_t FileFormat; /*!< File format */
+ __IO uint8_t ECC; /*!< ECC code */
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */
+ __IO uint8_t Reserved4; /*!< Always 1 */
+
+}HAL_MMC_CardCSDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ __IO uint32_t ProdName1; /*!< Product Name part1 */
+ __IO uint8_t ProdName2; /*!< Product Name part2 */
+ __IO uint8_t ProdRev; /*!< Product Revision */
+ __IO uint32_t ProdSN; /*!< Product Serial Number */
+ __IO uint8_t Reserved1; /*!< Reserved1 */
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */
+ __IO uint8_t CID_CRC; /*!< CID CRC */
+ __IO uint8_t Reserved2; /*!< Always 1 */
+
+}HAL_MMC_CardCIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group6 MMC Card Status returned by ACMD13
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
+ __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
+ __IO uint16_t CardType; /*!< Carries information about card type */
+ __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
+ __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
+ __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
+ __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
+ __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
+ __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
+ __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
+
+}HAL_MMC_CardStatusTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Constants Exported Constants
+ * @{
+ */
+
+#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
+
+#define CAPACITY 0x400000U /*!< Log Block Nuumber for 2 G bytes Cards */
+
+/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
+ * @{
+ */
+#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
+#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
+#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
+#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
+#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
+#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
+#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
+#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
+#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
+#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
+#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
+#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
+#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
+#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
+#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
+#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
+#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
+#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
+#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
+#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
+#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
+#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
+#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
+#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
+#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
+#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
+#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
+#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration structure
+ * @{
+ */
+#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
+#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
+ * @{
+ */
+/**
+ * @brief
+ */
+#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
+#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
+#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
+#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
+#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
+ * @{
+ */
+#define MMC_HIGH_VOLTAGE_CARD 0x00000000U
+#define MMC_DUAL_VOLTAGE_CARD 0x00000001U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_macros MMC Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the MMC device.
+ * @retval None
+ */
+#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the MMC device.
+ * @retval None
+ */
+#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the SDMMC DMA transfer.
+ * @retval None
+ */
+#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the SDMMC DMA transfer.
+ * @retval None
+ */
+#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the MMC device interrupt.
+ * @param __HANDLE__ MMC Handle
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Disable the MMC device interrupt.
+ * @param __HANDLE__ MMC Handle
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified MMC flag is set or not.
+ * @param __HANDLE__ MMC Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval The new state of MMC FLAG (SET or RESET).
+ */
+#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Clear the MMC's pending flags.
+ * @param __HANDLE__ MMC Handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval None
+ */
+#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Check whether the specified MMC interrupt has occurred or not.
+ * @param __HANDLE__ MMC Handle
+ * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval The new state of MMC IT (SET or RESET).
+ */
+#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Clear the MMC's interrupt pending bits.
+ * @param __HANDLE__ MMC Handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Functions MMC Exported Functions
+ * @{
+ */
+
+/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
+ * @{
+ */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
+ * @{
+ */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
+uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MMC_Private_Types MMC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MMC_Private_Defines MMC Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Variables MMC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Constants MMC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MMC_Private_Macros MMC Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_MMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1816 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_nand.c
+ * @author MCD Application Team
+ * @brief NAND HAL module driver.
+ * This file provides a generic firmware to drive NAND memories mounted
+ * as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NAND flash memories. It uses the FMC/FSMC layer functions to interface
+ with NAND devices. This driver is used as follows:
+
+ (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
+ with control and timing parameters for both common and attribute spaces.
+
+ (+) Read NAND flash memory maker and device IDs using the function
+ HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NAND flash memory by read/write operations using the functions
+ HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
+ HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
+ HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
+ HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
+ to read/write page(s)/spare area(s). These functions use specific device
+ information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
+ structure. The read/write address information is contained by the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
+
+ (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
+ The erase block address information is contained in the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
+
+ (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
+ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
+ feature or the function HAL_NAND_GetECC() to get the ECC correction code.
+
+ (+) You can monitor the NAND device HAL state by calling the function
+ HAL_NAND_GetState()
+
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NAND flash operations.
+ If a NAND flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+
+#ifdef HAL_NAND_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/** @defgroup NAND NAND
+ * @brief NAND HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NAND memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform NAND memory Initialization sequence
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ComSpace_Timing pointer to Common space timing structure
+ * @param AttSpace_Timing pointer to Attribute space timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+{
+ /* Check the NAND handle state */
+ if(hnand == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hnand->State == HAL_NAND_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnand->Lock = HAL_UNLOCKED;
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspInit(hnand);
+ }
+
+ /* Initialize NAND control Interface */
+ FMC_NAND_Init(hnand->Instance, &(hnand->Init));
+
+ /* Initialize NAND common space timing Interface */
+ FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+
+ /* Initialize NAND attribute space timing Interface */
+ FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+
+ /* Enable the NAND device */
+ __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform NAND memory De-Initialization sequence
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
+{
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspDeInit(hnand);
+
+ /* Configure the NAND registers with their reset values */
+ FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+
+ /* Reset the NAND controller state */
+ hnand->State = HAL_NAND_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND MSP Init
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnand);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NAND MSP DeInit
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnand);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief This function handles NAND device interrupt request.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+*/
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
+{
+ /* Check NAND interrupt Rising edge flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Rising edge pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
+ }
+
+ /* Check NAND interrupt Level flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Level pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
+ }
+
+ /* Check NAND interrupt Falling edge flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Falling edge pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
+ }
+
+ /* Check NAND interrupt FIFO empty flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt FIFO empty pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
+ }
+}
+
+/**
+ * @brief NAND interrupt feature callback
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnand);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_ITCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NAND
+ memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the NAND memory electronic signature
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pNAND_ID NAND ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
+{
+ __IO uint32_t data = 0U;
+ __IO uint32_t data1 = 0U;
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send Read ID command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+
+ /* Read the electronic signature from NAND flash */
+#ifdef FSMC_PCR2_PWID
+ if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
+#else /* FMC_PCR2_PWID is defined */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
+#endif
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
+ }
+ else
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+ data1 = *((__IO uint32_t *)deviceaddress + 4U);
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
+ pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory reset
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send NAND reset command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
+
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Configure the device: Enter the physical parameters of the device
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
+{
+ hnand->Config.PageSize = pDeviceConfig->PageSize;
+ hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
+ hnand->Config.BlockSize = pDeviceConfig->BlockSize;
+ hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
+ hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
+ hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
+ hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer
+ * @param NumPageToRead number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) read loop */
+ while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
+
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ /* Check if an extra command is needed for reading pages */
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ __DSB();
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read pages number */
+ numPagesRead++;
+
+ /* Decrement pages to read */
+ NumPageToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
+ * @param NumPageToRead number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) read loop */
+ while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
+
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
+ }
+
+ /* Increment read pages number */
+ numPagesRead++;
+
+ /* Decrement pages to read */
+ NumPageToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Page(s) to NAND memory block (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumPageToWrite number of pages to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) write loop */
+ while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
+
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
+ }
+
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numPagesWritten++;
+
+ /* Decrement pages to write */
+ NumPageToWrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Page(s) to NAND memory block (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
+ * @param NumPageToWrite number of pages to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) write loop */
+ while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
+
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ __DSB();
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numPagesWritten++;
+
+ /* Decrement pages to write */
+ NumPageToWrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaToRead Number of spare area to read
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
+
+ /* Spare area(s) read loop */
+ while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read spare areas number */
+ numSpareAreaRead++;
+
+ /* Decrement spare areas to read */
+ NumSpareAreaToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaToRead Number of spare area to read
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+
+ /* Spare area(s) read loop */
+ while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
+ }
+
+ /* Increment read spare areas number */
+ numSpareAreaRead++;
+
+ /* Decrement spare areas to read */
+ NumSpareAreaToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaTowrite number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the FMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Page address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
+
+ /* Spare area(s) write loop */
+ while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ numSpareAreaWritten++;
+
+ /* Decrement spare areas to write */
+ NumSpareAreaTowrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaTowrite number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the FMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+
+ /* Spare area(s) write loop */
+ while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ numSpareAreaWritten++;
+
+ /* Decrement spare areas to write */
+ NumSpareAreaTowrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory Block erase
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t deviceaddress = 0U;
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send Erase block command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory read status
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval NAND status
+ */
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+{
+ uint32_t data = 0U;
+ uint32_t deviceaddress = 0U;
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Send Read status operation command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
+
+ /* Read status register data */
+ data = *(__IO uint8_t *)deviceaddress;
+
+ /* Return the status */
+ if((data & NAND_ERROR) == NAND_ERROR)
+ {
+ return NAND_ERROR;
+ }
+ else if((data & NAND_READY) == NAND_READY)
+ {
+ return NAND_READY;
+ }
+
+ return NAND_BUSY;
+}
+
+/**
+ * @brief Increment the NAND memory address
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @retval The new status of the increment address operation. It can be:
+ * - NAND_VALID_ADDRESS: When the new address is valid address
+ * - NAND_INVALID_ADDRESS: When the new address is invalid address
+ */
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t status = NAND_VALID_ADDRESS;
+
+ /* Increment page address */
+ pAddress->Page++;
+
+ /* Check NAND address is valid */
+ if(pAddress->Page == hnand->Config.BlockSize)
+ {
+ pAddress->Page = 0U;
+ pAddress->Block++;
+
+ if(pAddress->Block == hnand->Config.PlaneSize)
+ {
+ pAddress->Block = 0U;
+ pAddress->Plane++;
+
+ if(pAddress->Plane == (hnand->Config.PlaneNbr))
+ {
+ status = NAND_INVALID_ADDRESS;
+ }
+ }
+ }
+
+ return (status);
+}
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically NAND ECC feature.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Enable ECC feature */
+ FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Disable ECC feature */
+ FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NAND ECC feature.
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ECCval pointer to ECC value
+ * @param Timeout maximum timeout to wait
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Get NAND ECC value */
+ status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NAND controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NAND state
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL state
+ */
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+{
+ return hnand->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,356 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_nand.h
+ * @author MCD Application Team
+ * @brief Header file of NAND HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_NAND_H
+#define __STM32F4xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NAND
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL NAND State structures definition
+ */
+typedef enum
+{
+ HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
+}HAL_NAND_StateTypeDef;
+
+/**
+ * @brief NAND Memory electronic signature Structure definition
+ */
+typedef struct
+{
+ /*<! NAND memory electronic signature maker and device IDs */
+
+ uint8_t Maker_Id;
+
+ uint8_t Device_Id;
+
+ uint8_t Third_Id;
+
+ uint8_t Fourth_Id;
+}NAND_IDTypeDef;
+
+/**
+ * @brief NAND Memory address Structure definition
+ */
+typedef struct
+{
+ uint16_t Page; /*!< NAND memory Page address */
+
+ uint16_t Plane; /*!< NAND memory Plane address */
+
+ uint16_t Block; /*!< NAND memory Block address */
+
+}NAND_AddressTypeDef;
+
+/**
+ * @brief NAND Memory info Structure definition
+ */
+typedef struct
+{
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
+ for 8 bits adressing or words for 16 bits addressing */
+
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
+ for 8 bits adressing or words for 16 bits addressing */
+
+ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
+
+ uint32_t BlockNbr; /*!< NAND memory number of total blocks */
+
+ uint32_t PlaneNbr; /*!< NAND memory number of planes */
+
+ uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */
+
+ FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
+ parameter is mandatory for some NAND parts after the read
+ command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
+ Example: Toshiba THTH58BYG3S0HBAI6.
+ This parameter could be ENABLE or DISABLE
+ Please check the Read Mode sequnece in the NAND device datasheet */
+}NAND_DeviceConfigTypeDef;
+
+/**
+ * @brief NAND handle Structure definition
+ */
+typedef struct
+{
+ FMC_NAND_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NAND locking object */
+
+ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
+
+ NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
+
+}NAND_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Macros NAND Exported Macros
+ * @{
+ */
+
+/** @brief Reset NAND handle state
+ * @param __HANDLE__ specifies the NAND handle.
+ * @retval None
+ */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NAND Control functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+#define NAND_DEVICE1 0x70000000U
+#define NAND_DEVICE2 0x80000000U
+#define NAND_WRITE_TIMEOUT 0x01000000U
+
+#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
+#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS 0x00000100U
+#define NAND_INVALID_ADDRESS 0x00000200U
+#define NAND_TIMEOUT_ERROR 0x00000400U
+#define NAND_BUSY 0x00000000U
+#define NAND_ERROR 0x00000001U
+#define NAND_READY 0x00000040U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @brief NAND memory address computation.
+ * @param __ADDRESS__ NAND memory address.
+ * @param __HANDLE__ NAND handle.
+ * @retval NAND Raw address value
+ */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+
+/**
+ * @brief NAND memory Column address computation.
+ * @param __HANDLE__ NAND handle.
+ * @retval NAND Raw address value
+ */
+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
+
+/**
+ * @brief NAND memory address cycling.
+ * @param __ADDRESS__ NAND memory address.
+ * @retval NAND address cycling value.
+ */
+#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
+
+/**
+ * @brief NAND memory Columns cycling.
+ * @param __ADDRESS__ NAND memory address.
+ * @retval NAND Column address cycling value.
+ */
+#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
+#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx || STM32F469xx || STM32F479xx */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1050 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_nor.c
+ * @author MCD Application Team
+ * @brief NOR HAL module driver.
+ * This file provides a generic firmware to drive NOR memories mounted
+ * as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NOR flash memories. It uses the FMC/FSMC layer functions to interface
+ with NOR devices. This driver is used as follows:
+
+ (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
+ with control and timing parameters for both normal and extended mode.
+
+ (+) Read NOR flash memory manufacturer code and device IDs using the function
+ HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NOR flash memory by read/write data unit operations using the functions
+ HAL_NOR_Read(), HAL_NOR_Program().
+
+ (+) Perform NOR flash erase block/chip operations using the functions
+ HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
+
+ (+) Read the NOR flash CFI (common flash interface) IDs using the function
+ HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
+ structure declared by the function caller.
+
+ (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
+ HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
+
+ (+) You can monitor the NOR device HAL state by calling the function
+ HAL_NOR_GetState()
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NOR flash operations.
+ If a NOR flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ *** NOR HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in NOR HAL driver.
+
+ (+) NOR_WRITE : NOR memory write data to specified address
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup NOR NOR
+ * @brief NOR driver modules
+ * @{
+ */
+#ifdef HAL_NOR_MODULE_ENABLED
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup NOR_Private_Defines NOR Private Defines
+ * @{
+ */
+
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Variables NOR Private Variables
+ * @{
+ */
+
+static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform the NOR memory Initialization sequence
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timing pointer to NOR control timing structure
+ * @param ExtTiming pointer to NOR extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ /* Check the NOR handle parameter */
+ if(hnor == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hnor->State == HAL_NOR_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnor->Lock = HAL_UNLOCKED;
+ /* Initialize the low level hardware (MSP) */
+ HAL_NOR_MspInit(hnor);
+ }
+
+ /* Initialize NOR control Interface */
+ FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+
+ /* Initialize NOR timing Interface */
+ FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
+
+ /* Initialize NOR extended mode timing Interface */
+ FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+
+ /* Initialize NOR Memory Data Width*/
+ if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_8B;
+ }
+ else
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_16B;
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform NOR memory De-Initialization sequence
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_NOR_MspDeInit(hnor);
+
+ /* Configure the NOR registers with their reset values */
+ FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NOR MSP Init
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnor);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP DeInit
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnor);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP Wait for Ready/Busy signal
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timeout Maximum timeout value
+ * @retval None
+ */
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hnor);
+ UNUSED(Timeout);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspWait could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read NOR flash IDs
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_ID pointer to NOR ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read ID command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+
+ /* Read the NOR IDs */
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the NOR memory to Read mode.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read data from NOR memory
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress pointer to Device address
+ * @param pData pointer to read data
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read data command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+
+ /* Read the data */
+ *pData = *(__IO uint32_t *)(uint32_t)pAddress;
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Program data to NOR memory
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress Device address
+ * @param pData pointer to the data to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send program data command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+
+ /* Write the data */
+ NOR_WRITE(pAddress, *pData);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a half-word buffer from the NOR memory.
+ * @param hnor pointer to the NOR handle
+ * @param uwAddress NOR memory internal address to read from.
+ * @param pData pointer to the buffer that receives the data read from the
+ * NOR memory.
+ * @param uwBufferSize number of Half word to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read data command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+
+ /* Read buffer */
+ while( uwBufferSize > 0U)
+ {
+ *pData++ = *(__IO uint16_t *)uwAddress;
+ uwAddress += 2U;
+ uwBufferSize--;
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes a half-word buffer to the NOR memory. This function must be used
+ only with S29GL128P NOR memory.
+ * @param hnor pointer to the NOR handle
+ * @param uwAddress NOR memory internal start write address
+ * @param pData pointer to source data buffer.
+ * @param uwBufferSize Size of the buffer to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+ uint16_t * p_currentaddress = (uint16_t *)NULL;
+ uint16_t * p_endaddress = (uint16_t *)NULL;
+ uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Initialize variables */
+ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
+ p_endaddress = p_currentaddress + (uwBufferSize-1U);
+ lastloadedaddress = (uint32_t)(uwAddress);
+
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+
+ /* Write Buffer Load Command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U));
+
+ /* Load Data into NOR Buffer */
+ while(p_currentaddress <= p_endaddress)
+ {
+ /* Store last loaded address & data value (for polling) */
+ lastloadedaddress = (uint32_t)p_currentaddress;
+
+ NOR_WRITE(p_currentaddress, *pData++);
+
+ p_currentaddress ++;
+ }
+
+ NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Erase the specified block of the NOR memory
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param BlockAddress Block to erase address
+ * @param Address Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send block erase command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Erase the entire NOR chip.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Address);
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send NOR chip erase command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read NOR flash CFI IDs
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_CFI pointer to NOR CFI IDs structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
+{
+ uint32_t deviceaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read CFI query command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+
+ /* read the NOR CFI information */
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NOR interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically NOR write operation.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
+{
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Enable write operation */
+ FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NOR write operation.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
+{
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the SRAM controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Disable write operation */
+ FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NOR controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NOR controller state
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval NOR controller state
+ */
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+{
+ return hnor->State;
+}
+
+/**
+ * @brief Returns the NOR operation status.
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address Device address
+ * @param Timeout NOR programming Timeout
+ * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+ * or HAL_NOR_STATUS_TIMEOUT
+ */
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+{
+ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
+ uint16_t tmpSR1 = 0, tmpSR2 = 0;
+ uint32_t tickstart = 0U;
+
+ /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+ HAL_NOR_MspWait(hnor, Timeout);
+
+ /* Get the NOR memory operation status -------------------------------------*/
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ status = HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+
+ /* Read NOR status register (DQ6 and DQ5) */
+ tmpSR1 = *(__IO uint16_t *)Address;
+ tmpSR2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS ;
+ }
+
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ status = HAL_NOR_STATUS_ONGOING;
+ }
+
+ tmpSR1 = *(__IO uint16_t *)Address;
+ tmpSR2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ return HAL_NOR_STATUS_ERROR;
+ }
+ }
+
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
+ STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx ||\
+ STM32F423xx */
+#endif /* HAL_NOR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,303 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_nor.h
+ * @author MCD Application Team
+ * @brief Header file of NOR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_NOR_H
+#define __STM32F4xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NOR
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
+}HAL_NOR_StateTypeDef;
+
+/**
+ * @brief FMC NOR Status typedef
+ */
+typedef enum
+{
+ HAL_NOR_STATUS_SUCCESS = 0U,
+ HAL_NOR_STATUS_ONGOING,
+ HAL_NOR_STATUS_ERROR,
+ HAL_NOR_STATUS_TIMEOUT
+}HAL_NOR_StatusTypeDef;
+
+/**
+ * @brief FMC NOR ID typedef
+ */
+typedef struct
+{
+ uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
+ These codes can be accessed by performing read operations with specific
+ control signals and addresses set.They can also be accessed by issuing
+ an Auto Select command */
+}NOR_IDTypeDef;
+
+/**
+ * @brief FMC NOR CFI typedef
+ */
+typedef struct
+{
+ /*!< Defines the information stored in the memory's Common flash interface
+ which contains a description of various electrical and timing parameters,
+ density information and functions supported by the memory */
+
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4;
+}NOR_CFITypeDef;
+
+/**
+ * @brief NOR handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
+
+ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+
+}NOR_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+ * @{
+ */
+/** @brief Reset NOR handle state
+ * @param __HANDLE__ specifies the NOR handle.
+ * @retval None
+ */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group3
+ * @{
+ */
+/* NOR Control functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group4
+ * @{
+ */
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
+ * @{
+ */
+/* NOR device IDs addresses */
+#define MC_ADDRESS ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS ((uint16_t)0x0061)
+#define CFI2_ADDRESS ((uint16_t)0x0062)
+#define CFI3_ADDRESS ((uint16_t)0x0063)
+#define CFI4_ADDRESS ((uint16_t)0x0064)
+
+/* NOR operation wait timeout */
+#define NOR_TMEOUT ((uint16_t)0xFFFF)
+
+/* NOR memory data width */
+#define NOR_MEMORY_8B ((uint8_t)0x00)
+#define NOR_MEMORY_16B ((uint8_t)0x01)
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS1 0x60000000U
+#define NOR_MEMORY_ADRESS2 0x64000000U
+#define NOR_MEMORY_ADRESS3 0x68000000U
+#define NOR_MEMORY_ADRESS4 0x6C000000U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+ * @{
+ */
+/**
+ * @brief NOR memory address shifting.
+ * @param __NOR_ADDRESS__ NOR base address
+ * @param NOR_MEMORY_WIDTH NOR memory width
+ * @param ADDRESS NOR memory address
+ * @retval NOR shifted address value
+ */
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\
+ ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
+
+/**
+ * @brief NOR memory write data to specified address.
+ * @param ADDRESS NOR memory address
+ * @param DATA Data to write
+ * @retval None
+ */
+#define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
+ STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,746 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pccard.c
+ * @author MCD Application Team
+ * @brief PCCARD HAL module driver.
+ * This file provides a generic firmware to drive PCCARD memories mounted
+ * as external device.
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions
+ to interface with PCCARD devices. This driver is used for:
+
+ (+) PCCARD/Compact Flash memory configuration sequence using the function
+ HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
+ both common and attribute spaces.
+
+ (+) Read PCCARD/Compact Flash memory maker and device IDs using the function
+ HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
+ the CompactFlash_ID structure declared by the function caller.
+
+ (+) Access PCCARD/Compact Flash memory by read/write operations using the functions
+ HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
+ HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
+
+ (+) Perform PCCARD/Compact Flash Reset chip operation using the function
+ HAL_PCCARD_Reset()/HAL_CF_Reset.
+
+ (+) Perform PCCARD/Compact Flash erase sector operation using the function
+ HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.
+
+ (+) Read the PCCARD/Compact Flash status operation using the function
+ HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().
+
+ (+) You can monitor the PCCARD/Compact Flash device HAL state by calling
+ the function HAL_PCCARD_GetState()/HAL_CF_GetState()
+
+ [..]
+ (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
+ operations. If a PCCARD/Compact Flash device contains different operations
+ and/or implementations, it should be implemented separately.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @defgroup PCCARD PCCARD
+ * @brief PCCARD HAL module driver
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PCCARD_Private_Defines PCCARD Private Defines
+ * @{
+ */
+#define PCCARD_TIMEOUT_READ_ID 0x0000FFFFU
+#define PCCARD_TIMEOUT_READ_WRITE_SECTOR 0x0000FFFFU
+#define PCCARD_TIMEOUT_ERASE_SECTOR 0x00000400U
+#define PCCARD_TIMEOUT_STATUS 0x01000000U
+
+#define PCCARD_STATUS_OK (uint8_t)0x58
+#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function ----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### PCCARD Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the PCCARD memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform the PCCARD memory Initialization sequence
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param ComSpaceTiming Common space timing structure
+ * @param AttSpaceTiming Attribute space timing structure
+ * @param IOSpaceTiming IO space timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
+{
+ /* Check the PCCARD controller state */
+ if(hpccard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hpccard->State == HAL_PCCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpccard->Lock = HAL_UNLOCKED;
+ /* Initialize the low level hardware (MSP) */
+ HAL_PCCARD_MspInit(hpccard);
+ }
+
+ /* Initialize the PCCARD state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize PCCARD control Interface */
+ FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
+
+ /* Init PCCARD common space timing Interface */
+ FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
+
+ /* Init PCCARD attribute space timing Interface */
+ FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
+
+ /* Init PCCARD IO space timing Interface */
+ FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
+
+ /* Enable the PCCARD device */
+ __FMC_PCCARD_ENABLE(hpccard->Instance);
+
+ /* Update the PCCARD state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Perform the PCCARD memory De-initialization sequence
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_PCCARD_MspDeInit(hpccard);
+
+ /* Configure the PCCARD registers with their reset values */
+ FMC_PCCARD_DeInit(hpccard->Instance);
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief PCCARD MSP Init
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpccard);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PCCARD MSP DeInit
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpccard);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### PCCARD Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the PCCARD memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read Compact Flash's ID.
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param CompactFlash_ID Compact flash ID structure.
+ * @param pStatus pointer to compact flash status
+ * @retval HAL status
+ *
+ */
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize the PCCARD status */
+ *pStatus = PCCARD_READY;
+
+ /* Send the Identify Command */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC;
+
+ /* Read PCCARD IDs and timeout treatment */
+ do
+ {
+ /* Read the PCCARD status */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+ else
+ {
+ /* Read PCCARD ID bytes */
+ for(index = 0U; index < 16U; index++)
+ {
+ CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
+ }
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read sector from PCCARD memory
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer pointer to destination read buffer
+ * @param SectorAddress Sector address to read
+ * @param pStatus pointer to PCCARD status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize PCCARD status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
+
+ do
+ {
+ /* wait till the Status = 0x80 */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status == 0x80) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
+
+ do
+ {
+ /* wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Read bytes */
+ for(; index < PCCARD_SECTOR_SIZE; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Write sector to PCCARD memory
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer pointer to source write buffer
+ * @param SectorAddress Sector address to write
+ * @param pStatus pointer to PCCARD status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize PCCARD status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
+
+ do
+ {
+ /* Wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Write bytes */
+ for(; index < PCCARD_SECTOR_SIZE; index++)
+ {
+ *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
+ }
+
+ do
+ {
+ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Erase sector from PCCARD memory
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param SectorAddress Sector address to erase
+ * @param pStatus pointer to PCCARD status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize PCCARD status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
+
+ /* wait till the PCCARD is ready */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ while((status != PCCARD_STATUS_WRITE_OK) && timeout)
+ {
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }
+
+ if(timeout == 0U)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the PCCARD memory
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Provide a SW reset and Read and verify the:
+ - PCCard Configuration Option Register at address 0x98000200 --> 0x80
+ - Card Configuration and Status Register at address 0x98000202 --> 0x00
+ - Pin Replacement Register at address 0x98000204 --> 0x0C
+ - Socket and Copy Register at address 0x98000206 --> 0x00
+ */
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01;
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles PCCARD device interrupt request.
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+*/
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Check PCCARD interrupt Rising edge flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Rising edge pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
+ }
+
+ /* Check PCCARD interrupt Level flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Level pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
+ }
+
+ /* Check PCCARD interrupt Falling edge flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Falling edge pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
+ }
+
+ /* Check PCCARD interrupt FIFO empty flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt FIFO empty pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
+ }
+}
+
+/**
+ * @brief PCCARD interrupt feature callback
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpccard);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_ITCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group3 State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### PCCARD State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the PCCARD controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the PCCARD controller state
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL state
+ */
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
+{
+ return hpccard->State;
+}
+
+/**
+ * @brief Get the compact flash memory status
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval New status of the PCCARD operation. This parameter can be:
+ * - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
+ * a Timeout error
+ * - CompactFlash_READY: when memory is ready for the next operation
+ */
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U;
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_PCCARD_STATUS_ONGOING;
+ }
+
+ status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ while((status_pccard == PCCARD_BUSY) && timeout)
+ {
+ status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }
+
+ if(timeout == 0U)
+ {
+ status_pccard = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Return the operation status */
+ return (HAL_PCCARD_StatusTypeDef) status_pccard;
+}
+
+/**
+ * @brief Reads the Compact Flash memory status using the Read status command
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval The status of the Compact Flash memory. This parameter can be:
+ * - CompactFlash_BUSY: when memory is busy
+ * - CompactFlash_READY: when memory is ready for the next operation
+ * - CompactFlash_ERROR: when the previous operation generates error
+ */
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
+{
+ uint8_t data = 0U, status_pccard = PCCARD_BUSY;
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_PCCARD_STATUS_ONGOING;
+ }
+
+ /* Read status operation */
+ data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
+ {
+ status_pccard = PCCARD_TIMEOUT_ERROR;
+ }
+ else if((data & PCCARD_READY) == PCCARD_READY)
+ {
+ status_pccard = PCCARD_READY;
+ }
+
+ return (HAL_PCCARD_StatusTypeDef) status_pccard;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,264 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pccard.h
+ * @author MCD Application Team
+ * @brief Header file of PCCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PCCARD_H
+#define __STM32F4xx_HAL_PCCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/** @addtogroup PCCARD
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL PCCARD State structures definition
+ */
+typedef enum
+{
+ HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
+ HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
+ HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
+ HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
+}HAL_PCCARD_StateTypeDef;
+
+typedef enum
+{
+ HAL_PCCARD_STATUS_SUCCESS = 0U,
+ HAL_PCCARD_STATUS_ONGOING,
+ HAL_PCCARD_STATUS_ERROR,
+ HAL_PCCARD_STATUS_TIMEOUT
+}HAL_PCCARD_StatusTypeDef;
+
+/**
+ * @brief FMC_PCCARD handle Structure definition
+ */
+typedef struct
+{
+ FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
+
+ FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
+
+ __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
+
+ HAL_LockTypeDef Lock; /*!< PCCARD Lock */
+
+}PCCARD_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
+ * @{
+ */
+/** @brief Reset PCCARD handle state
+ * @param __HANDLE__ specifies the PCCARD handle.
+ * @retval None
+ */
+#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCCARD_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group3
+ * @{
+ */
+/* PCCARD State functions *******************************************************/
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
+ * @{
+ */
+#define PCCARD_DEVICE_ADDRESS 0x90000000U
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS 0x98000000U /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
+#define PCCARD_IO_SPACE_ADDRESS 0x9C000000U /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR 0x9C0001F0U /* IO space size to @0x9FFF FFFF */
+
+/* Flash-ATA registers description */
+#define ATA_DATA ((uint8_t)0x00) /* Data register */
+#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
+#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
+#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
+#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
+#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
+#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
+#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
+#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
+#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
+
+/* Flash-ATA commands */
+#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
+#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
+#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
+#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
+
+/* PC Card/Compact Flash status */
+#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
+#define PCCARD_BUSY ((uint8_t)0x80)
+#define PCCARD_PROGR ((uint8_t)0x01)
+#define PCCARD_READY ((uint8_t)0x40)
+
+#define PCCARD_SECTOR_SIZE 255U /* In half words */
+
+/**
+ * @}
+ */
+/* Compact Flash redefinition */
+#define HAL_CF_Init HAL_PCCARD_Init
+#define HAL_CF_DeInit HAL_PCCARD_DeInit
+#define HAL_CF_MspInit HAL_PCCARD_MspInit
+#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit
+
+#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
+#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
+#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
+#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
+#define HAL_CF_Reset HAL_PCCARD_Reset
+#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler
+#define HAL_CF_ITCallback HAL_PCCARD_ITCallback
+
+#define HAL_CF_GetState HAL_PCCARD_GetState
+#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
+#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
+
+#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR
+#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef
+
+#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
+#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
+#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
+#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
+#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
+
+#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
+#define CF_BUSY PCCARD_BUSY
+#define CF_PROGR PCCARD_PROGR
+#define CF_READY PCCARD_READY
+
+#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
+
+/* Private macros ------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_PCCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1374 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pcd.c
+ * @author MCD Application Team
+ * @brief PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The PCD HAL driver can be used as follows:
+
+ (#) Declare a PCD_HandleTypeDef handle structure, for example:
+ PCD_HandleTypeDef hpcd;
+
+ (#) Fill parameters of Init structure in HCD handle
+
+ (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
+
+ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+ (##) Enable the PCD/USB Low Level interface clock using
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure PCD pin-out
+ (##) Configure PCD NVIC interrupt
+
+ (#)Associate the Upper USB device stack to the HAL PCD Driver:
+ (##) hpcd.pData = pdev;
+
+ (#)Enable PCD transmission and reception:
+ (##) HAL_PCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCD PCD
+ * @brief PCD HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the PCD according to the specified
+ * parameters in the PCD_InitTypeDef and initialize the associated handle.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+ uint32_t i = 0U;
+
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+/* MBED */
+ if(hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpcd->Lock = HAL_UNLOCKED;
+ for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
+ hpcd->EPLock[i].Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+/* MBED */
+
+ /* Disable the Interrupts */
+ __HAL_PCD_DISABLE(hpcd);
+
+ /*Init the Core (common init.) */
+ USB_CoreInit(hpcd->Instance, hpcd->Init);
+
+ /* Force Device Mode*/
+ USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
+
+ /* Init endpoints structures */
+ for (i = 0U; i < 15U; i++)
+ {
+ /* Init ep structure */
+ hpcd->IN_ep[i].is_in = 1U;
+ hpcd->IN_ep[i].num = i;
+ hpcd->IN_ep[i].tx_fifo_num = i;
+ /* Control until ep is activated */
+ hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+ hpcd->IN_ep[i].maxpacket = 0U;
+ hpcd->IN_ep[i].xfer_buff = 0U;
+ hpcd->IN_ep[i].xfer_len = 0U;
+ }
+
+ for (i = 0U; i < 15U; i++)
+ {
+ hpcd->OUT_ep[i].is_in = 0U;
+ hpcd->OUT_ep[i].num = i;
+ hpcd->IN_ep[i].tx_fifo_num = i;
+ /* Control until ep is activated */
+ hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+ hpcd->OUT_ep[i].maxpacket = 0U;
+ hpcd->OUT_ep[i].xfer_buff = 0U;
+ hpcd->OUT_ep[i].xfer_len = 0U;
+
+ hpcd->Instance->DIEPTXF[i] = 0U;
+ }
+
+ /* Init Device */
+ USB_DevInit(hpcd->Instance, hpcd->Init);
+
+ hpcd->State= HAL_PCD_STATE_READY;
+
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ /* Activate LPM */
+ if (hpcd->Init.lpm_enable == 1U)
+ {
+ HAL_PCDEx_ActivateLPM(hpcd);
+ }
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+
+#ifdef USB_OTG_GCCFG_BCDEN
+ /* Activate Battery charging */
+ if (hpcd->Init.battery_charging_enable == 1U)
+ {
+ HAL_PCDEx_ActivateBCD(hpcd);
+ }
+#endif /* USB_OTG_GCCFG_BCDEN */
+
+ USB_DevDisconnect (hpcd->Instance);
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the PCD peripheral.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Stop Device */
+ HAL_PCD_Stop(hpcd);
+
+ /* DeInit the low level hardware */
+ HAL_PCD_MspDeInit(hpcd);
+
+ hpcd->State = HAL_PCD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the PCD MSP.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes PCD MSP.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start The USB OTG Device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+/* MBED */
+ //__HAL_LOCK(hpcd);
+/* MBED */
+ USB_DevConnect (hpcd->Instance);
+ __HAL_PCD_ENABLE(hpcd);
+/* MBED */
+ //__HAL_UNLOCK(hpcd);
+/* MBED */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop The USB OTG Device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+/* MBED */
+ //__HAL_LOCK(hpcd);
+/* MBED */
+ __HAL_PCD_DISABLE(hpcd);
+ USB_StopDevice(hpcd->Instance);
+ USB_DevDisconnect(hpcd->Instance);
+/* MBED */
+ //__HAL_UNLOCK(hpcd);
+/* MBED */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles PCD interrupt request.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t i = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
+ uint32_t fifoemptymsk = 0U, temp = 0U;
+ USB_OTG_EPTypeDef *ep;
+ uint32_t hclk = 180000000U;
+
+ /* ensure that we are in device mode */
+ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
+ {
+ /* avoid spurious interrupt */
+ if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
+ {
+ return;
+ }
+
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+ {
+ /* incorrect mode, acknowledge the interrupt */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
+ }
+
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+ {
+ epnum = 0U;
+
+ /* Read in the device interrupt bits */
+ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
+
+ while ( ep_intr )
+ {
+ if (ep_intr & 0x1U)
+ {
+ epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
+
+ if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
+
+ if(hpcd->Init.dma_enable == 1U)
+ {
+ hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+ hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+ }
+
+ HAL_PCD_DataOutStageCallback(hpcd, epnum);
+ if(hpcd->Init.dma_enable == 1U)
+ {
+ if((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+ {
+ /* this is ZLP, so prepare EP0 for next setup */
+ USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
+ }
+ }
+
+ if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+ {
+ /* Inform the upper layer that a setup packet is available */
+ HAL_PCD_SetupStageCallback(hpcd);
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+ }
+
+ if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
+ }
+
+#ifdef USB_OTG_DOEPINT_OTEPSPR
+ /* Clear Status Phase Received interrupt */
+ if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+ }
+#endif /* USB_OTG_DOEPINT_OTEPSPR */
+ }
+ epnum++;
+ ep_intr >>= 1U;
+ }
+ }
+
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+ {
+ /* Read in the device interrupt bits */
+ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
+
+ epnum = 0U;
+
+ while ( ep_intr )
+ {
+ if (ep_intr & 0x1U) /* In ITR */
+ {
+ epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
+
+ if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+ {
+ fifoemptymsk = 0x1U << epnum;
+
+/* MBED */
+ atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK,fifoemptymsk);
+/* MBED */
+
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
+ }
+
+ HAL_PCD_DataInStageCallback(hpcd, epnum);
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ /* this is ZLP, so prepare EP0 for next setup */
+ if((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
+ {
+ /* prepare to rx more setup packets */
+ USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
+ }
+ }
+ if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
+ }
+ if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
+ }
+ if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
+ }
+ if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
+ }
+ if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+ {
+ PCD_WriteEmptyTxFifo(hpcd , epnum);
+ }
+ }
+ epnum++;
+ ep_intr >>= 1U;
+ }
+ }
+
+ /* Handle Resume Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+ {
+ /* Clear the Remote Wake-up Signaling */
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ if(hpcd->LPM_State == LPM_L1)
+ {
+ hpcd->LPM_State = LPM_L0;
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+ }
+ else
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+ {
+ HAL_PCD_ResumeCallback(hpcd);
+ }
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+ }
+
+ /* Handle Suspend Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+ {
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+ {
+
+ HAL_PCD_SuspendCallback(hpcd);
+ }
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
+ }
+
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ /* Handle LPM Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
+ if( hpcd->LPM_State == LPM_L0)
+ {
+ hpcd->LPM_State = LPM_L1;
+ hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+ }
+ else
+ {
+ HAL_PCD_SuspendCallback(hpcd);
+ }
+ }
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+
+ /* Handle Reset Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+ {
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+ USB_FlushTxFifo(hpcd->Instance , 0x10U);
+
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ {
+ USBx_INEP(i)->DIEPINT = 0xFFU;
+ USBx_OUTEP(i)->DOEPINT = 0xFFU;
+ }
+ USBx_DEVICE->DAINT = 0xFFFFFFFFU;
+ USBx_DEVICE->DAINTMSK |= 0x10001U;
+
+ if(hpcd->Init.use_dedicated_ep1)
+ {
+ USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
+ USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+ }
+ else
+ {
+#ifdef USB_OTG_DOEPINT_OTEPSPR
+ USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
+#else
+ USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
+#endif /* USB_OTG_DOEPINT_OTEPSPR */
+ USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+ }
+
+ /* Set Default Address to 0 */
+ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
+
+ /* setup EP0 to receive SETUP packets */
+ USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
+ }
+
+ /* Handle Enumeration done Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+ {
+ USB_ActivateSetup(hpcd->Instance);
+ hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+
+ if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
+ {
+ hpcd->Init.speed = USB_OTG_SPEED_HIGH;
+ hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ;
+ hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+ else
+ {
+ hpcd->Init.speed = USB_OTG_SPEED_FULL;
+ hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
+
+ /* The USBTRD is configured according to the tables below, depending on AHB frequency
+ used by application. In the low AHB frequency range it is used to stretch enough the USB response
+ time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+ latency to the Data FIFO */
+
+ /* Get hclk frequency value */
+ hclk = HAL_RCC_GetHCLKFreq();
+
+ if((hclk >= 14200000U)&&(hclk < 15000000U))
+ {
+ /* hclk Clock Range between 14.2-15 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 15000000U)&&(hclk < 16000000U))
+ {
+ /* hclk Clock Range between 15-16 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 16000000U)&&(hclk < 17200000U))
+ {
+ /* hclk Clock Range between 16-17.2 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 17200000U)&&(hclk < 18500000U))
+ {
+ /* hclk Clock Range between 17.2-18.5 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 18500000U)&&(hclk < 20000000U))
+ {
+ /* hclk Clock Range between 18.5-20 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 20000000U)&&(hclk < 21800000U))
+ {
+ /* hclk Clock Range between 20-21.8 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 21800000U)&&(hclk < 24000000U))
+ {
+ /* hclk Clock Range between 21.8-24 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 24000000U)&&(hclk < 27700000U))
+ {
+ /* hclk Clock Range between 24-27.7 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 27700000U)&&(hclk < 32000000U))
+ {
+ /* hclk Clock Range between 27.7-32 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else /* if(hclk >= 32000000) */
+ {
+ /* hclk Clock Range between 32-180 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10U) & USB_OTG_GUSBCFG_TRDT);
+ }
+ }
+
+ HAL_PCD_ResetCallback(hpcd);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
+ }
+
+ /* Handle RxQLevel Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+ {
+ USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+ temp = USBx->GRXSTSP;
+
+ ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+
+ if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT)
+ {
+ if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+ {
+ USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U);
+ ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
+ }
+ }
+ else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT)
+ {
+ USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
+ }
+ USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
+
+ /* Handle SOF Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+ {
+ HAL_PCD_SOFCallback(hpcd);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
+ }
+
+ /* Handle Incomplete ISO IN Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+ {
+ HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
+ }
+
+ /* Handle Incomplete ISO OUT Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ {
+ HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+ }
+
+ /* Handle Connection event Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+ {
+ HAL_PCD_ConnectCallback(hpcd);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
+ }
+
+ /* Handle Disconnection event Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+ {
+ temp = hpcd->Instance->GOTGINT;
+
+ if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+ {
+ HAL_PCD_DisconnectCallback(hpcd);
+ }
+ hpcd->Instance->GOTGINT |= temp;
+ }
+ }
+}
+
+/**
+ * @brief Data OUT stage callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Data IN stage callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_DataInStageCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Setup stage callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Start Of Frame callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_SOFCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Reset callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Suspend event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_SuspendCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Resume event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ResumeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO OUT callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO IN callback.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Connection event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ConnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disconnection event callback.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Connect the USB device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+ USB_DevConnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disconnect the USB device.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+ USB_DevDisconnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the USB Device address.
+ * @param hpcd PCD handle
+ * @param address new device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+ __HAL_LOCK(hpcd);
+ USB_SetDevAddress(hpcd->Instance, address);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+/**
+ * @brief Open and configure an endpoint.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param ep_mps endpoint max packet size
+ * @param ep_type endpoint type
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ USB_OTG_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ }
+ ep->num = ep_addr & 0x7F;
+
+ ep->is_in = (0x80 & ep_addr) != 0;
+ ep->maxpacket = ep_mps;
+ ep->type = ep_type;
+ if (ep->is_in)
+ {
+ /* Assign a Tx FIFO */
+ ep->tx_fifo_num = ep->num;
+ }
+ /* Set initial data PID. */
+ if (ep_type == EP_TYPE_BULK )
+ {
+ ep->data_pid_start = 0U;
+ }
+
+/* MBED */
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+ USB_ActivateEndpoint(hpcd->Instance , ep);
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+ return ret;
+}
+
+
+/**
+ * @brief Deactivate an endpoint.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ USB_OTG_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ }
+ ep->num = ep_addr & 0x7F;
+
+ ep->is_in = (0x80 & ep_addr) != 0;
+
+/* MBED */
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+ USB_DeactivateEndpoint(hpcd->Instance , ep);
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the reception buffer
+ * @param len amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+ USB_OTG_EPTypeDef *ep;
+
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0U;
+ ep->is_in = 0U;
+ ep->num = ep_addr & 0x7F;
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ ep->dma_addr = (uint32_t)pBuf;
+ }
+
+/* MBED */
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+
+ if ((ep_addr & 0x7F) == 0)
+ {
+ USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ }
+ else
+ {
+ USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ }
+/* MBED */
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get Received Data Size.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval Data Size
+ */
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+/* MBED */
+ return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
+/* MBED */
+}
+/**
+ * @brief Send an amount of data.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the transmission buffer
+ * @param len amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+ USB_OTG_EPTypeDef *ep;
+
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0U;
+ ep->is_in = 1U;
+ ep->num = ep_addr & 0x7F;
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ ep->dma_addr = (uint32_t)pBuf;
+ }
+
+/* MBED */
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+
+ if ((ep_addr & 0x7F) == 0)
+ {
+ USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ }
+ else
+ {
+ USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ }
+
+/* MBED */
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set a STALL condition over an endpoint.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ USB_OTG_EPTypeDef *ep;
+
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 1U;
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+
+
+/* MBED */
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+ USB_EPSetStall(hpcd->Instance , ep);
+ if((ep_addr & 0x7F) == 0)
+ {
+ USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+ }
+/* MBED */
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear a STALL condition over in an endpoint.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ USB_OTG_EPTypeDef *ep;
+
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 0U;
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+
+/* MBED */
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+ USB_EPClearStall(hpcd->Instance , ep);
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Flush an endpoint.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+/* MBED */
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
+ }
+ else
+ {
+ USB_FlushRxFifo(hpcd->Instance);
+ }
+
+/* MBED */
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Activate remote wakeup signalling.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+ {
+ /* Activate Remote wakeup signaling */
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief De-activate remote wakeup signalling.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ /* De-activate Remote wakeup signaling */
+ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PCD handle state.
+ * @param hpcd PCD handle
+ * @retval HAL state
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+ return hpcd->State;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Check FIFO for the next packet to be loaded.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ USB_OTG_EPTypeDef *ep;
+ uint32_t len;
+ uint32_t len32b;
+ uint32_t fifoemptymsk = 0U;
+
+ ep = &hpcd->IN_ep[epnum];
+ len = ep->xfer_len - ep->xfer_count;
+
+ if (len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ }
+
+
+ len32b = (len + 3U) / 4U;
+
+ while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) &&
+ (ep->xfer_count < ep->xfer_len) &&
+ (ep->xfer_len != 0U))
+ {
+ /* Write the FIFO */
+ len = ep->xfer_len - ep->xfer_count;
+
+ if (len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ }
+ len32b = (len + 3U) / 4U;
+
+ USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
+
+ ep->xfer_buff += len;
+ ep->xfer_count += len;
+ }
+
+ if (ep->xfer_count >= ep->xfer_len)
+ {
+ fifoemptymsk = 0x1U << epnum;
+/* MBED */
+ atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
+/* MBED */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+ STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,352 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pcd.h
+ * @author MCD Application Team
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PCD_H
+#define __STM32F4xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usb.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief PCD State structure definition
+ */
+typedef enum
+{
+ HAL_PCD_STATE_RESET = 0x00U,
+ HAL_PCD_STATE_READY = 0x01U,
+ HAL_PCD_STATE_ERROR = 0x02U,
+ HAL_PCD_STATE_BUSY = 0x03U,
+ HAL_PCD_STATE_TIMEOUT = 0x04U
+} PCD_StateTypeDef;
+
+#ifdef USB_OTG_GLPMCFG_LPMEN
+/* Device LPM suspend state */
+typedef enum
+{
+ LPM_L0 = 0x00U, /* on */
+ LPM_L1 = 0x01U, /* LPM L1 sleep */
+ LPM_L2 = 0x02U, /* suspend */
+ LPM_L3 = 0x03U /* off */
+}PCD_LPM_StateTypeDef;
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+
+typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
+
+/**
+ * @brief PCD Handle Structure definition
+ */
+
+/* MBED */
+typedef struct
+{
+ HAL_LockTypeDef Lock;
+} PCD_EPLockDef;
+/* MBED */
+
+typedef struct
+{
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ PCD_EPTypeDef IN_ep[16U]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[16U]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+/* MBED */
+ PCD_EPLockDef EPLock[15]; /*!< PCD endpoint peripheral status */
+/* MBED */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12U]; /*!< Setup packet buffer */
+#ifdef USB_OTG_GLPMCFG_LPMEN
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ uint32_t BESL;
+ uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+#endif /* USB_OTG_GLPMCFG_LPMEN */
+#ifdef USB_OTG_GCCFG_BCDEN
+ uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+#endif /* USB_OTG_GCCFG_BCDEN */
+ void *pData; /*!< Pointer to upper stack Handler */
+} PCD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Include PCD HAL Extension module */
+#include "stm32f4xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+/** @defgroup PCD_Speed PCD Speed
+ * @{
+ */
+#define PCD_SPEED_HIGH 0U
+#define PCD_SPEED_HIGH_IN_FULL 1U
+#define PCD_SPEED_FULL 2U
+/**
+ * @}
+ */
+
+/** @defgroup PCD_PHY_Module PCD PHY Module
+ * @{
+ */
+#define PCD_PHY_ULPI 1U
+#define PCD_PHY_EMBEDDED 2U
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
+ * @{
+ */
+#ifndef USBD_HS_TRDT_VALUE
+ #define USBD_HS_TRDT_VALUE 9U
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+ #define USBD_FS_TRDT_VALUE 5U
+#endif /* USBD_FS_TRDT_VALUE */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
+ ~(USB_OTG_PCGCCTL_STOPCLK)
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10U)
+
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
+
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
+
+#define USB_OTG_HS_WAKEUP_EXTI_LINE 0x00100000U /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
+#define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
+ }while(0U)
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ }while(0U)
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
+ }while(0U)
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+ }while(0U)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ }while(0U)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+ }while(0U)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+ STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,322 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pcd_ex.c
+ * @author MCD Application Team
+ * @brief PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCDEx PCDEx
+ * @brief PCD Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_PCD_MODULE_ENABLED
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief PCDEx control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Update FIFO configuration
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set Tx FIFO
+ * @param hpcd PCD handle
+ * @param fifo The number of Tx fifo
+ * @param size Fifo size
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+ uint8_t i = 0;
+ uint32_t Tx_Offset = 0U;
+
+ /* TXn min size = 16 words. (n : Transmit FIFO index)
+ When a TxFIFO is not used, the Configuration should be as follows:
+ case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
+ --> Txm can use the space allocated for Txn.
+ case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
+ --> Txn should be configured with the minimum space of 16 words
+ The FIFO is used optimally when used TxFIFOs are allocated in the top
+ of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+ When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+
+ Tx_Offset = hpcd->Instance->GRXFSIZ;
+
+ if(fifo == 0)
+ {
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
+ }
+ else
+ {
+ Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
+ for (i = 0; i < (fifo - 1); i++)
+ {
+ Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U);
+ }
+
+ /* Multiply Tx_Size by 2 to get higher performance */
+ hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Rx FIFO
+ * @param hpcd PCD handle
+ * @param size Size of Rx fifo
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+ hpcd->Instance->GRXFSIZ = size;
+
+ return HAL_OK;
+}
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief Activate LPM feature
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = ENABLE;
+ hpcd->LPM_State = LPM_L0;
+ USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
+ USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate LPM feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = DISABLE;
+ USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
+ USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Send LPM message to user layer callback.
+ * @param hpcd PCD handle
+ * @param msg LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+}
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief HAL_PCDEx_BCD_VBUSDetect : handle BatteryCharging Process
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Start BCD When device is connected */
+ if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
+ {
+ /* Enable DCD : Data Contact Detect */
+ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
+
+ /* Wait Detect flag or a timeout is happen*/
+ while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > 1000U)
+ {
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+ return;
+ }
+ }
+
+ /* Right response got */
+ HAL_Delay(100U);
+
+ /* Check Detect flag*/
+ if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
+ {
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+ }
+
+ /*Primary detection: checks if connected to Standard Downstream Port
+ (without charging capability) */
+ USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
+ USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
+ HAL_Delay(100U);
+
+ if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
+ {
+ /* Case of Standard Downstream Port */
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+ }
+ else
+ {
+ /* start secondary detection to check connection to Charging Downstream
+ Port or Dedicated Charging Port */
+ USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
+ USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
+ HAL_Delay(100U);
+
+ if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
+ {
+ /* case Dedicated Charging Port */
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+ }
+ else
+ {
+ /* case Charging Downstream Port */
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+ }
+ }
+ /* Battery Charging capability discovery finished */
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+ }
+}
+
+/**
+ * @brief HAL_PCDEx_ActivateBCD : active BatteryCharging feature
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+ hpcd->battery_charging_active = ENABLE;
+ USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCDEx_DeActivateBCD : de-active BatteryCharging feature
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ hpcd->battery_charging_active = DISABLE;
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCDEx_BatteryCharging_Callback : Send BatteryCharging message to user layer
+ * @param hpcd PCD handle
+ * @param msg LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+}
+
+#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+ STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,131 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pcd_ex.h
+ * @author MCD Application Team
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PCD_EX_H
+#define __STM32F4xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCDEx
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+typedef enum
+{
+ PCD_LPM_L0_ACTIVE = 0x00U, /* on */
+ PCD_LPM_L1_ACTIVE = 0x01U /* LPM L1 sleep */
+}PCD_LPM_MsgTypeDef;
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+typedef enum
+{
+ PCD_BCD_ERROR = 0xFFU,
+ PCD_BCD_CONTACT_DETECTION = 0xFEU,
+ PCD_BCD_STD_DOWNSTREAM_PORT = 0xFDU,
+ PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFCU,
+ PCD_BCD_DEDICATED_CHARGING_PORT = 0xFBU,
+ PCD_BCD_DISCOVERY_COMPLETED = 0x00U
+}PCD_BCD_MsgTypeDef;
+#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
+ * @{
+ */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+void HAL_PCDEx_ADP_Sensing_Start(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_ADP_Sensing_Callback(PCD_HandleTypeDef *hpcd);
+#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+ STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,575 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pwr.c
+ * @author MCD Application Team
+ * @brief PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWR PWR
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWR_Private_Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+ * @{
+ */
+#define PVD_MODE_IT 0x00010000U
+#define PVD_MODE_EVT 0x00020000U
+#define PVD_RISING_EDGE 0x00000001U
+#define PVD_FALLING_EDGE 0x00000002U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ After reset, the backup domain (RTC registers, RTC backup data
+ registers and backup SRAM) is protected against possible unwanted
+ write accesses.
+ To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() macro.
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
+ * @retval None
+ */
+void HAL_PWR_DeInit(void)
+{
+ __HAL_RCC_PWR_FORCE_RESET();
+ __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+ * @brief Enables access to the backup domain (RTC registers, RTC
+ * backup data registers and backup SRAM).
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables access to the backup domain (RTC registers, RTC
+ * backup data registers and backup SRAM).
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Low Power modes configuration functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+
+ *** PVD configuration ***
+ =========================
+ [..]
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
+ than the PVD threshold. This event is internally connected to the EXTI
+ line16 and can generate an interrupt if enabled. This is done through
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+ (+) The PVD is stopped in Standby mode.
+
+ *** Wake-up pin configuration ***
+ ================================
+ [..]
+ (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
+ forced in input pull-down configuration and is active on rising edges.
+ (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
+ (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
+ (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
+
+ *** Low Power modes configuration ***
+ =====================================
+ [..]
+ The devices feature 3 low-power modes:
+ (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+ (+) Stop mode: all clocks are stopped, regulator running, regulator
+ in low power mode
+ (+) Standby mode: 1.2V domain powered off.
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (+) Entry:
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
+ functions with
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+
+ -@@- The Regulator parameter is not used for the STM32F4 family
+ and is kept as parameter just to maintain compatibility with the
+ lower power families (STM32L).
+ (+) Exit:
+ Any peripheral interrupt acknowledged by the nested vectored interrupt
+ controller (NVIC) can wake up the device from Sleep mode.
+
+ *** Stop mode ***
+ =================
+ [..]
+ In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+ and the HSE RC oscillators are disabled. Internal SRAM and register contents
+ are preserved.
+ The voltage regulator can be configured either in normal or low-power mode.
+ To minimize the consumption In Stop mode, FLASH can be powered off before
+ entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
+ It can be switched on again by software after exiting the Stop mode using
+ the HAL_PWREx_DisableFlashPowerDown() function.
+
+ (+) Entry:
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
+ function with:
+ (++) Main regulator ON.
+ (++) Low Power regulator ON.
+ (+) Exit:
+ Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+ *** Standby mode ***
+ ====================
+ [..]
+ (+)
+ The Standby mode allows to achieve the lowest power consumption. It is based
+ on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
+ The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
+ the HSE oscillator are also switched off. SRAM and register contents are lost
+ except for the RTC registers, RTC backup registers, backup SRAM and Standby
+ circuitry.
+
+ The voltage regulator is OFF.
+
+ (++) Entry:
+ (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+ (++) Exit:
+ (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+ *** Auto-wake-up (AWU) from low-power mode ***
+ =============================================
+ [..]
+
+ (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
+ Wake-up event, a tamper event or a time-stamp event, without depending on
+ an external interrupt (Auto-wake-up mode).
+
+ (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
+
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
+ is necessary to configure the RTC to detect the tamper or time stamp event using the
+ HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+
+ (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
+ configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
+ * information for the PVD.
+ * @note Refer to the electrical characteristics of your device datasheet for
+ * more details about the voltage threshold corresponding to each
+ * detection level.
+ * @retval None
+ */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+ /* Set PLS[7:5] bits according to PVDLevel value */
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
+
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure interrupt mode */
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+ }
+}
+
+/**
+ * @brief Enables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_EnablePVD(void)
+{
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_DisablePVD(void)
+{
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Enables the Wake-up PINx functionality.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN1
+ * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+ * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
+{
+ /* Check the parameter */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+ /* Enable the wake up pin */
+ SET_BIT(PWR->CSR, WakeUpPinx);
+}
+
+/**
+ * @brief Disables the Wake-up PINx functionality.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN1
+ * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+ * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+ /* Check the parameter */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+ /* Disable the wake up pin */
+ CLEAR_BIT(PWR->CSR, WakeUpPinx);
+}
+
+/**
+ * @brief Enters Sleep mode.
+ *
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+ *
+ * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
+ * systick interrupt when used as time base for Timeout
+ *
+ * @param Regulator Specifies the regulator state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
+ * @note This parameter is not used for the STM32F4 family and is kept as parameter
+ * just to maintain compatibility with the lower power families.
+ * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select SLEEP mode entry -------------------------------------------------*/
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters Stop mode.
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
+ * the HSI RC oscillator is selected as system clock.
+ * @note When the voltage regulator operates in low power mode, an additional
+ * startup delay is incurred when waking up from Stop mode.
+ * By keeping the internal regulator ON during Stop mode, the consumption
+ * is higher although the startup time is reduced.
+ * @param Regulator Specifies the regulator state in Stop mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
+ * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Stop mode entry --------------------------------------------------*/
+ if(STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Enters Standby mode.
+ * @note In Standby mode, all I/O pins are high impedance except for:
+ * - Reset pad (still available)
+ * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
+ * Alarm out, or RTC clock calibration out.
+ * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
+ * - WKUP pin 1 (PA0) if enabled.
+ * @retval None
+ */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+ /* Select Standby mode */
+ SET_BIT(PWR->CR, PWR_CR_PDDS);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief This function handles the PWR PVD interrupt request.
+ * @note This API should be called under the PVD_IRQHandler().
+ * @retval None
+ */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+ /* Check PWR Exti flag */
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+ {
+ /* PWR PVD interrupt user callback */
+ HAL_PWR_PVDCallback();
+
+ /* Clear PWR Exti pending bit */
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+ }
+}
+
+/**
+ * @brief PWR PVD interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWR_PVDCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWR_PVDCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enables CORTEX M4 SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Disables CORTEX M4 SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,447 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_H
+#define __STM32F4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+ * @{
+ */
+
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
+ This parameter can be a value of @ref PWR_PVD_detection_level */
+
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWR_PVD_Mode */
+}PWR_PVDTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+ * @{
+ */
+#define PWR_WAKEUP_PIN1 0x00000100U
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
+ (Compare internally to VREFINT) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON 0x00000000U
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag PWR Flag
+ * @{
+ */
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO
+#define PWR_FLAG_BRR PWR_CSR_BRR
+#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+ * @{
+ */
+
+/** @brief Check PWR flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ * was received from the WKUP pin or from the RTC alarm (Alarm A
+ * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+ * An additional wakeup event is detected if the WKUP pin is enabled
+ * (by setting the EWUP bit) when the WKUP pin level is already high.
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ * resumed from StandBy mode.
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ * For this reason, this bit is equal to 0 after Standby or reset
+ * until the PVDE bit is set.
+ * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
+ * when the device wakes up from Standby mode or by a system reset
+ * or power reset.
+ * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
+ * scaling output selection is ready.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the PWR's pending flags.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
+
+/**
+ * @brief Enable the PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable the PVD EXTI Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Enable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+ * @brief PVD EXTI line configuration: set rising & falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
+ }while(0U)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
+ }while(0U)
+
+/**
+ * @brief checks whether the specified PVD Exti interrupt flag is set or not.
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Clear the PVD Exti flag.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Generates a Software interrupt on PVD EXTI line.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @}
+ */
+
+/* Include PWR HAL Extension module */
+#include "stm32f4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Power PVD IRQ Handler */
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+/* Cortex System Control functions *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+ * @{
+ */
+#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_register_alias_address PWR Register alias address
+ * @{
+ */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+#define PWR_CR_OFFSET 0x00U
+#define PWR_CSR_OFFSET 0x04U
+#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
+#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CR_register_alias PWR CR Register alias address
+ * @{
+ */
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define DBP_BIT_NUMBER PWR_CR_DBP_Pos
+#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
+#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
+
+/* Alias word address of VOS bit */
+#define VOS_BIT_NUMBER PWR_CR_VOS_Pos
+#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
+ * @{
+ */
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+ * @{
+ */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_NORMAL))
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,640 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pwr_ex.c
+ * @author MCD Application Team
+ * @brief Extended PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of PWR extension peripheral:
+ * + Peripheral Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWREx PWREx
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Constants
+ * @{
+ */
+#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U
+#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U
+#define PWR_BKPREG_TIMEOUT_VALUE 1000U
+#define PWR_VOSRDY_TIMEOUT_VALUE 1000U
+/**
+ * @}
+ */
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+ * @{
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
+ * @brief Peripheral Extended features functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral extended features functions #####
+ ===============================================================================
+
+ *** Main and Backup Regulators configuration ***
+ ================================================
+ [..]
+ (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
+ the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
+ retained even in Standby or VBAT mode when the low power backup regulator
+ is enabled. It can be considered as an internal EEPROM when VBAT is
+ always present. You can use the HAL_PWREx_EnableBkUpReg() function to
+ enable the low power backup regulator.
+
+ (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
+ the backup SRAM is powered from VDD which replaces the VBAT power supply to
+ save battery life.
+
+ (+) The backup SRAM is not mass erased by a tamper event. It is read
+ protected to prevent confidential data, such as cryptographic private
+ key, from being accessed. The backup SRAM can be erased only through
+ the Flash interface when a protection level change from level 1 to
+ level 0 is requested.
+ -@- Refer to the description of Read protection (RDP) in the Flash
+ programming manual.
+
+ (+) The main internal regulator can be configured to have a tradeoff between
+ performance and power consumption when the device does not operate at
+ the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
+ macro which configure VOS bit in PWR_CR register
+
+ Refer to the product datasheets for more details.
+
+ *** FLASH Power Down configuration ****
+ =======================================
+ [..]
+ (+) By setting the FPDS bit in the PWR_CR register by using the
+ HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
+ down mode when the device enters Stop mode. When the Flash memory
+ is in power down mode, an additional startup delay is incurred when
+ waking up from Stop mode.
+
+ (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL
+ is OFF and the HSI or HSE clock source is selected as system clock.
+ The new value programmed is active only when the PLL is ON.
+ When the PLL is OFF, the voltage scale 3 is automatically selected.
+ Refer to the datasheets for more details.
+
+ *** Over-Drive and Under-Drive configuration ****
+ =================================================
+ [..]
+ (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
+ 2 operating modes available:
+ (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
+ voltage scaling (scale 1, scale 2 or scale 3)
+ (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
+ higher frequency than the normal mode for a given voltage scaling (scale 1,
+ scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
+ disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
+ the sequence described in Reference manual.
+
+ (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator
+ supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
+ and internal SRAM. 2 operating modes are available:
+ (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
+ available when the main regulator or the low power regulator is used in Scale 3 or
+ low voltage mode.
+ (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
+ available when the main regulator or the low power regulator is in low voltage mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables the Backup Regulator.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
+{
+ uint32_t tickstart = 0U;
+
+ *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till Backup regulator ready flag is set */
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the Backup Regulator.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
+{
+ uint32_t tickstart = 0U;
+
+ *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till Backup regulator ready flag is set */
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the Flash Power Down in Stop mode.
+ * @retval None
+ */
+void HAL_PWREx_EnableFlashPowerDown(void)
+{
+ *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the Flash Power Down in Stop mode.
+ * @retval None
+ */
+void HAL_PWREx_DisableFlashPowerDown(void)
+{
+ *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Return Voltage Scaling Range.
+ * @retval The configured scale for the regulator voltage(VOS bit field).
+ * The returned value can be one of the following:
+ * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+ */
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+ return (PWR->CR & PWR_CR_VOS);
+}
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/**
+ * @brief Configures the main internal regulator output voltage.
+ * @param VoltageScaling specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption.
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+ * the maximum value of fHCLK = 168 MHz.
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+ * the maximum value of fHCLK = 144 MHz.
+ * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
+ * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
+ * When moving from Range 2 to Range 1, the system frequency can be increased to
+ * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+ uint32_t tickstart = 0U;
+
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+
+ /* Enable PWR RCC Clock Peripheral */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Set Range */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+ {
+ if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief Configures the main internal regulator output voltage.
+ * @param VoltageScaling specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption.
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+ * the maximum value of fHCLK is 168 MHz. It can be extended to
+ * 180 MHz by activating the over-drive mode.
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+ * the maximum value of fHCLK is 144 MHz. It can be extended to,
+ * 168 MHz by activating the over-drive mode.
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
+ * the maximum value of fHCLK is 120 MHz.
+ * @note To update the system clock frequency(SYSCLK):
+ * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
+ * - Call the HAL_RCC_OscConfig() to configure the PLL.
+ * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
+ * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
+ * @note The scale can be modified only when the HSI or HSE clock source is selected
+ * as system clock source, otherwise the API returns HAL_ERROR.
+ * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
+ * value in the PWR_CR1 register are not taken in account.
+ * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
+ * @note The new voltage scale is active only when the PLL is ON.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+ uint32_t tickstart = 0U;
+
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+
+ /* Enable PWR RCC Clock Peripheral */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ {
+ /* Disable the main PLL */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set Range */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+
+ /* Enable the main PLL */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+ {
+ if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Enables Wakeup Pin Detection on high level (rising edge).
+ * @retval None
+ */
+void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
+{
+ *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Enables Wakeup Pin Detection on low level (falling edge).
+ * @retval None
+ */
+void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
+{
+ *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
+}
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+ defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief Enables Main Regulator low voltage mode.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+ * STM32F413xx/STM32F423xx devices.
+ * @retval None
+ */
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
+{
+ *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables Main Regulator low voltage mode.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+ * STM32F413xx/STM32F423xxdevices.
+ * @retval None
+ */
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
+{
+ *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Enables Low Power Regulator low voltage mode.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+ * STM32F413xx/STM32F423xx devices.
+ * @retval None
+ */
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
+{
+ *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables Low Power Regulator low voltage mode.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+ * STM32F413xx/STM32F423xx devices.
+ * @retval None
+ */
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
+{
+ *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
+}
+
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx ||
+ STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Activates the Over-Drive mode.
+ * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+ * This mode allows the CPU and the core logic to operate at a higher frequency
+ * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
+ * @note It is recommended to enter or exit Over-drive mode when the application is not running
+ * critical tasks and when the system clock source is either HSI or HSE.
+ * During the Over-drive switch activation, no peripheral clocks should be enabled.
+ * The peripheral clocks must be enabled once the Over-drive mode is activated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
+{
+ uint32_t tickstart = 0U;
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
+ __HAL_PWR_OVERDRIVE_ENABLE();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+ {
+ if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable the Over-drive switch */
+ __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+ {
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates the Over-Drive mode.
+ * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+ * This mode allows the CPU and the core logic to operate at a higher frequency
+ * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
+ * @note It is recommended to enter or exit Over-drive mode when the application is not running
+ * critical tasks and when the system clock source is either HSI or HSE.
+ * During the Over-drive switch activation, no peripheral clocks should be enabled.
+ * The peripheral clocks must be enabled once the Over-drive mode is activated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
+{
+ uint32_t tickstart = 0U;
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Disable the Over-drive switch */
+ __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+ {
+ if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable the Over-drive */
+ __HAL_PWR_OVERDRIVE_DISABLE();
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+ {
+ if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters in Under-Drive STOP mode.
+ *
+ * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+ *
+ * @note This mode can be selected only when the Under-Drive is already active
+ *
+ * @note This mode is enabled only with STOP low power mode.
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
+ * mode is only available when the main regulator or the low power regulator
+ * is in low voltage mode
+ *
+ * @note If the Under-drive mode was enabled, it is automatically disabled after
+ * exiting Stop mode.
+ * When the voltage regulator operates in Under-drive mode, an additional
+ * startup delay is induced when waking up from Stop mode.
+ *
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ *
+ * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
+ * the HSI RC oscillator is selected as system clock.
+ *
+ * @note When the voltage regulator operates in low power mode, an additional
+ * startup delay is incurred when waking up from Stop mode.
+ * By keeping the internal regulator ON during Stop mode, the consumption
+ * is higher although the startup time is reduced.
+ *
+ * @param Regulator specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
+ * and Flash memory in power-down when the device is in Stop under-drive mode
+ * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
+ * and Flash memory in power-down when the device is in Stop under-drive mode
+ * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
+ * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+ uint32_t tmpreg1 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Enable Power ctrl clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ /* Enable the Under-drive Mode ---------------------------------------------*/
+ /* Clear Under-drive flag */
+ __HAL_PWR_CLEAR_ODRUDR_FLAG();
+
+ /* Enable the Under-drive */
+ __HAL_PWR_UNDERDRIVE_ENABLE();
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg1 = PWR->CR;
+ /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
+ tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
+
+ /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
+ tmpreg1 |= Regulator;
+
+ /* Store the new value */
+ PWR->CR = tmpreg1;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(STOPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __WFE();
+ }
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+ return HAL_OK;
+}
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,370 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pwr_ex.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_EX_H
+#define __STM32F4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
+#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
+ * @{
+ */
+#define PWR_FLAG_ODRDY PWR_CSR_ODRDY
+#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
+#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
+ 180 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
+ 168 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
+/**
+ * @}
+ */
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
+ * @{
+ */
+#define PWR_WAKEUP_PIN2 0x00000080U
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define PWR_WAKEUP_PIN3 0x00000040U
+#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+ STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+/** @brief macros configure the main internal regulator output voltage.
+ * @param __REGULATOR__ specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption when the device does
+ * not operate at the maximum frequency (refer to the datasheets for more details).
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * @retval None
+ */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
+ UNUSED(tmpreg); \
+ } while(0U)
+#else
+/** @brief macros configure the main internal regulator output voltage.
+ * @param __REGULATOR__ specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption when the device does
+ * not operate at the maximum frequency (refer to the datasheets for more details).
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+ * @retval None
+ */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
+ UNUSED(tmpreg); \
+ } while(0U)
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macros to enable or disable the Over drive mode.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ */
+#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Over drive switching.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ */
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Under drive mode.
+ * @note This mode is enabled only with STOP low power mode.
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
+ * mode is only available when the main regulator or the low power regulator
+ * is in low voltage mode.
+ * @note If the Under-drive mode was enabled, it is automatically disabled after
+ * exiting Stop mode.
+ * When the voltage regulator operates in Under-drive mode, an additional
+ * startup delay is induced when waking up from Stop mode.
+ */
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
+
+/** @brief Check PWR flag is set or not.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
+ * is ready
+ * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
+ * switching is ready
+ * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
+ * is enabled in Stop mode
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the Under-Drive Ready flag.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ */
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group1
+ * @{
+ */
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void);
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
+void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
+ defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
+#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWREx_Private_Constants PWREx Private Constants
+ * @{
+ */
+
+/** @defgroup PWREx_register_alias_address PWREx Register alias address
+ * @{
+ */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+/* --- CR Register ---*/
+/* Alias word address of FPDS bit */
+#define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos
+#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
+
+/* Alias word address of ODEN bit */
+#define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos
+#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
+
+/* Alias word address of ODSWEN bit */
+#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos
+#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
+
+/* Alias word address of MRLVDS bit */
+#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos
+#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
+
+/* Alias word address of LPLVDS bit */
+#define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos
+#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
+
+ /**
+ * @}
+ */
+
+/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
+ * @{
+ */
+/* --- CSR Register ---*/
+/* Alias word address of BRE bit */
+#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos
+#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of WUPP bit */
+#define WUPP_BIT_NUMBER PWR_CSR_WUPP_Pos
+#define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+ * @{
+ */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+#else
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
+
+#if defined(STM32F446xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
+#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
+ ((PIN) == PWR_WAKEUP_PIN3))
+#else
+#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
+#endif /* STM32F446xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2422 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_qspi.c
+ * @author MCD Application Team
+ * @brief QSPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the QuadSPI interface (QSPI).
+ * + Initialization and de-initialization functions
+ * + Indirect functional mode management
+ * + Memory-mapped functional mode management
+ * + Auto-polling functional mode management
+ * + Interrupts and flags management
+ * + DMA channel configuration for indirect functional mode
+ * + Errors management and abort functionality
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ *** Initialization ***
+ ======================
+ [..]
+ (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
+ (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
+ (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+ (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
+ (++) If interrupt mode is used, enable and configure QuadSPI global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+ link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
+ DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (#) Configure the flash size, the clock prescaler, the fifo threshold, the
+ clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
+
+ *** Indirect functional mode ***
+ ================================
+ [..]
+ (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
+ functions :
+ (++) Instruction phase : the mode used and if present the instruction opcode.
+ (++) Address phase : the mode used and if present the size and the address value.
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+ bytes values.
+ (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (++) Data phase : the mode used and if present the number of bytes.
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ if activated.
+ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (#) If no data is required for the command, it is sent directly to the memory :
+ (++) In polling mode, the output of the function is done when the transfer is complete.
+ (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
+ (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
+ HAL_QSPI_Transmit_IT() after the command configuration :
+ (++) In polling mode, the output of the function is done when the transfer is complete.
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+ (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
+ HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+ (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
+ HAL_QSPI_Receive_IT() after the command configuration :
+ (++) In polling mode, the output of the function is done when the transfer is complete.
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+ (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
+ HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+
+ *** Auto-polling functional mode ***
+ ====================================
+ [..]
+ (#) Configure the command sequence and the auto-polling functional mode using the
+ HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
+ (++) Instruction phase : the mode used and if present the instruction opcode.
+ (++) Address phase : the mode used and if present the size and the address value.
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+ bytes values.
+ (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (++) Data phase : the mode used.
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ if activated.
+ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+ the polling interval and the automatic stop activation.
+ (#) After the configuration :
+ (++) In polling mode, the output of the function is done when the status match is reached. The
+ automatic stop is activated to avoid an infinite loop.
+ (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
+
+ *** Memory-mapped functional mode ***
+ =====================================
+ [..]
+ (#) Configure the command sequence and the memory-mapped functional mode using the
+ HAL_QSPI_MemoryMapped() functions :
+ (++) Instruction phase : the mode used and if present the instruction opcode.
+ (++) Address phase : the mode used and the size.
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+ bytes values.
+ (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (++) Data phase : the mode used.
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ if activated.
+ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (++) The timeout activation and the timeout period.
+ (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
+ the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
+
+ *** Errors management and abort functionality ***
+ ==================================================
+ [..]
+ (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
+ (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
+ flushes the fifo :
+ (++) In polling mode, the output of the function is done when the transfer
+ complete bit is set and the busy bit cleared.
+ (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
+ the transfer complete bi is set.
+
+ *** Control functions ***
+ =========================
+ [..]
+ (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
+ (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
+ (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
+ (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+
+ *** Workarounds linked to Silicon Limitation ***
+ ====================================================
+ [..]
+ (#) Workarounds Implemented inside HAL Driver
+ (++) Extra data written in the FIFO at the end of a read transfer
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup QSPI QSPI
+ * @brief QSPI HAL module driver
+ * @{
+ */
+#ifdef HAL_QSPI_MODULE_ENABLED
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup QSPI_Private_Constants
+ * @{
+ */
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!<Indirect write mode*/
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
+#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
+#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @addtogroup QSPI_Private_Macros QSPI Private Macros
+ * @{
+ */
+#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
+ ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
+ ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
+ ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
+ * @{
+ */
+
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Initialize the QuadSPI.
+ (+) De-initialize the QuadSPI.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the QSPI mode according to the specified parameters
+ * in the QSPI_InitTypeDef and creates the associated handle.
+ * @param hqspi qspi handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the QSPI handle allocation */
+ if(hqspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
+ assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
+ assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
+ assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
+ assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
+ assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
+ assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
+ assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
+
+ if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
+ {
+ assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hqspi->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_QSPI_MspInit(hqspi);
+
+ /* Configure the default timeout for the QSPI memory access */
+ HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
+ }
+
+ /* Configure QSPI FIFO Threshold */
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1U) << 8U));
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
+ if(status == HAL_OK)
+ {
+
+ /* Configure QSPI Clock Prescaler and Sample Shift */
+ MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24U)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
+
+ /* Configure QSPI Flash Size, CS High Time and Clock Mode */
+ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
+ ((hqspi->Init.FlashSize << 16U) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+
+ /* Enable the QSPI peripheral */
+ __HAL_QSPI_ENABLE(hqspi);
+
+ /* Set QSPI error code to none */
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Initialize the QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DeInitializes the QSPI peripheral
+ * @param hqspi qspi handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
+{
+ /* Check the QSPI handle allocation */
+ if(hqspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ /* Disable the QSPI Peripheral Clock */
+ __HAL_QSPI_DISABLE(hqspi);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_QSPI_MspDeInit(hqspi);
+
+ /* Set QSPI error code to none */
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Initialize the QSPI state */
+ hqspi->State = HAL_QSPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief QSPI MSP Init
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_QSPI_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief QSPI MSP DeInit
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_QSPI_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
+ * @brief QSPI Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Handle the interrupts.
+ (+) Handle the command sequence.
+ (+) Transmit data in blocking, interrupt or DMA mode.
+ (+) Receive data in blocking, interrupt or DMA mode.
+ (+) Manage the auto-polling functional mode.
+ (+) Manage the memory-mapped functional mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles QSPI interrupt request.
+ * @param hqspi QSPI handle
+ * @retval None.
+ */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
+{
+ __IO uint32_t *data_reg;
+ uint32_t flag = READ_REG(hqspi->Instance->SR);
+ uint32_t itsource = READ_REG(hqspi->Instance->CR);
+
+ /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
+ if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
+ {
+ data_reg = &hqspi->Instance->DR;
+
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ {
+ /* Transmission process */
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
+ {
+ if (hqspi->TxXferCount > 0U)
+ {
+ /* Fill the FIFO until it is full */
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ hqspi->TxXferCount--;
+ }
+ else
+ {
+ /* No more data available for the transfer */
+ /* Disable the QSPI FIFO Threshold Interrupt */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+ break;
+ }
+ }
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+ {
+ /* Receiving Process */
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
+ {
+ if (hqspi->RxXferCount > 0U)
+ {
+ /* Read the FIFO until it is empty */
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ hqspi->RxXferCount--;
+ }
+ else
+ {
+ /* All data have been received for the transfer */
+ /* Disable the QSPI FIFO Threshold Interrupt */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+ break;
+ }
+ }
+ }
+
+ /* FIFO Threshold callback */
+ HAL_QSPI_FifoThresholdCallback(hqspi);
+ }
+
+ /* QSPI Transfer Complete interrupt occurred -------------------------------*/
+ else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
+ {
+ /* Clear interrupt */
+ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
+
+ /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+ /* Transfer complete callback */
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ {
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ {
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Disable the DMA channel */
+ __HAL_DMA_DISABLE(hqspi->hdma);
+ }
+
+ /* Clear Busy bit */
+ HAL_QSPI_Abort_IT(hqspi);
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* TX Complete callback */
+ HAL_QSPI_TxCpltCallback(hqspi);
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+ {
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ {
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Disable the DMA channel */
+ __HAL_DMA_DISABLE(hqspi->hdma);
+ }
+ else
+ {
+ data_reg = &hqspi->Instance->DR;
+ while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
+ {
+ if (hqspi->RxXferCount > 0U)
+ {
+ /* Read the last data received in the FIFO until it is empty */
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ hqspi->RxXferCount--;
+ }
+ else
+ {
+ /* All data have been received for the transfer */
+ break;
+ }
+ }
+ }
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ HAL_QSPI_Abort_IT(hqspi);
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* RX Complete callback */
+ HAL_QSPI_RxCpltCallback(hqspi);
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY)
+ {
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Command Complete callback */
+ HAL_QSPI_CmdCpltCallback(hqspi);
+ }
+ else if(hqspi->State == HAL_QSPI_STATE_ABORT)
+ {
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
+ {
+ /* Abort called by the user */
+
+ /* Abort Complete callback */
+ HAL_QSPI_AbortCpltCallback(hqspi);
+ }
+ else
+ {
+ /* Abort due to an error (eg : DMA error) */
+
+ /* Error callback */
+ HAL_QSPI_ErrorCallback(hqspi);
+ }
+ }
+ }
+
+ /* QSPI Status Match interrupt occurred ------------------------------------*/
+ else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
+ {
+ /* Clear interrupt */
+ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
+
+ /* Check if the automatic poll mode stop is activated */
+ if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
+ {
+ /* Disable the QSPI Transfer Error and Status Match Interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ /* Status match callback */
+ HAL_QSPI_StatusMatchCallback(hqspi);
+ }
+
+ /* QSPI Transfer Error interrupt occurred ----------------------------------*/
+ else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
+ {
+ /* Clear interrupt */
+ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
+
+ /* Disable all the QSPI Interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+ /* Set error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
+
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ {
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Disable the DMA channel */
+ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+ HAL_DMA_Abort_IT(hqspi->hdma);
+ }
+ else
+ {
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Error callback */
+ HAL_QSPI_ErrorCallback(hqspi);
+ }
+ }
+
+ /* QSPI Timeout interrupt occurred -----------------------------------------*/
+ else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
+ {
+ /* Clear interrupt */
+ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
+
+ /* Time out callback */
+ HAL_QSPI_TimeOutCallback(hqspi);
+ }
+}
+
+/**
+ * @brief Sets the command configuration.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
+ * @param Timeout Time out duration
+ * @note This function is used only in Indirect Read or Write Modes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Call the configuration function */
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ if (cmd->DataMode == QSPI_DATA_NONE)
+ {
+ /* When there is no data phase, the transfer start as soon as the configuration is done
+ so wait until TC flag is set to go back in idle state */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+
+ }
+ else
+ {
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Sets the command configuration in interrupt mode.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
+ * @note This function is used only in Indirect Read or Write Modes
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
+{
+ __IO uint32_t count = 0U;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
+ /* Wait till BUSY flag reset */
+ count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
+ do
+ {
+ if (count-- == 0U)
+ {
+ hqspi->State = HAL_QSPI_STATE_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ }
+ while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
+
+ if (status == HAL_OK)
+ {
+ if (cmd->DataMode == QSPI_DATA_NONE)
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+ }
+
+ /* Call the configuration function */
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ if (cmd->DataMode == QSPI_DATA_NONE)
+ {
+ /* When there is no data phase, the transfer start as soon as the configuration is done
+ so activate TC and TE interrupts */
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI Transfer Error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
+ }
+ else
+ {
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Time out duration
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart = HAL_GetTick();
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ if(pData != NULL )
+ {
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+ /* Configure counters and size of the handle */
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->pTxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ while(hqspi->TxXferCount > 0U)
+ {
+ /* Wait until FT flag is set to send data */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
+
+ if (status != HAL_OK)
+ {
+ break;
+ }
+
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ hqspi->TxXferCount--;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Wait until TC flag is set to go back in idle state */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Clear Busy bit */
+ status = HAL_QSPI_Abort(hqspi);
+ }
+ }
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ else
+ {
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Time out duration
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+ if(pData != NULL )
+ {
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+ /* Configure counters and size of the handle */
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->pRxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ while(hqspi->RxXferCount > 0U)
+ {
+ /* Wait until FT or TC flag is set to read received data */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
+
+ if (status != HAL_OK)
+ {
+ break;
+ }
+
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ hqspi->RxXferCount--;
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Wait until TC flag is set to go back in idle state */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Clear Transfer Complete bit */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ status = HAL_QSPI_Abort(hqspi);
+ }
+ }
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ else
+ {
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ return status;
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @note This function is used only in Indirect Write Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+ if(pData != NULL )
+ {
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+ /* Configure counters and size of the handle */
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->pTxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+
+ }
+ else
+ {
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Receive an amount of data in no-blocking mode with Interrupt
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @note This function is used only in Indirect Read Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ if(pData != NULL )
+ {
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+ /* Configure counters and size of the handle */
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+ hqspi->pRxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+ }
+ else
+ {
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode with DMA.
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @note This function is used only in Indirect Write Mode
+ * @note If DMA peripheral access is configured as halfword, the number
+ * of data and the fifo threshold should be aligned on halfword
+ * @note If DMA peripheral access is configured as word, the number
+ * of data and the fifo threshold should be aligned on word
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp;
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ /* Clear the error code */
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ if(pData != NULL )
+ {
+ /* Configure counters of the handle */
+ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+ {
+ hqspi->TxXferCount = data_size;
+ }
+ else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+ {
+ if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
+ {
+ /* The number of data or the fifo threshold is not aligned on halfword
+ => no transfer possible with DMA peripheral access configured as halfword */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ else
+ {
+ hqspi->TxXferCount = (data_size >> 1);
+ }
+ }
+ else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+ {
+ if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
+ {
+ /* The number of data or the fifo threshold is not aligned on word
+ => no transfer possible with DMA peripheral access configured as word */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ else
+ {
+ hqspi->TxXferCount = (data_size >> 2U);
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+
+ /* Configure size and pointer of the handle */
+ hqspi->TxXferSize = hqspi->TxXferCount;
+ hqspi->pTxBuffPtr = pData;
+
+ /* Configure QSPI: CCR register with functional mode as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+ /* Set the QSPI DMA transfer complete callback */
+ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
+
+ /* Set the QSPI DMA Half transfer complete callback */
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+ /* Clear the DMA abort callback */
+ hqspi->hdma->XferAbortCallback = NULL;
+
+#if defined (QSPI1_V2_1L)
+ /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
+ AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
+ Change the following configuration of DMA peripheral
+ - Enable peripheral increment
+ - Disable memory increment
+ - Set DMA direction as peripheral to memory mode */
+
+ /* Enable peripheral increment mode of the DMA */
+ hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
+
+ /* Disable memory increment mode of the DMA */
+ hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
+
+ /* Update peripheral/memory increment mode bits */
+ MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
+
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
+#else
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+#endif /* QSPI1_V2_1L */
+
+ /* Update direction mode bit */
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+ /* Enable the QSPI transmit DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ }
+ else
+ {
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+
+ status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode with DMA.
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer.
+ * @note This function is used only in Indirect Read Mode
+ * @note If DMA peripheral access is configured as halfword, the number
+ * of data and the fifo threshold should be aligned on halfword
+ * @note If DMA peripheral access is configured as word, the number
+ * of data and the fifo threshold should be aligned on word
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp;
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ if(pData != NULL )
+ {
+ /* Configure counters of the handle */
+ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+ {
+ hqspi->RxXferCount = data_size;
+ }
+ else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+ {
+ if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
+ {
+ /* The number of data or the fifo threshold is not aligned on halfword
+ => no transfer possible with DMA peripheral access configured as halfword */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ else
+ {
+ hqspi->RxXferCount = (data_size >> 1U);
+ }
+ }
+ else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+ {
+ if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
+ {
+ /* The number of data or the fifo threshold is not aligned on word
+ => no transfer possible with DMA peripheral access configured as word */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ else
+ {
+ hqspi->RxXferCount = (data_size >> 2U);
+ }
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+
+ /* Configure size and pointer of the handle */
+ hqspi->RxXferSize = hqspi->RxXferCount;
+ hqspi->pRxBuffPtr = pData;
+
+ /* Set the QSPI DMA transfer complete callback */
+ hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
+
+ /* Set the QSPI DMA Half transfer complete callback */
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+ /* Clear the DMA abort callback */
+ hqspi->hdma->XferAbortCallback = NULL;
+
+#if defined (QSPI1_V2_1L)
+ /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
+ AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
+ Change the following configuration of DMA peripheral
+ - Enable peripheral increment
+ - Disable memory increment
+ - Set DMA direction as memory to peripheral mode
+ - 4 Extra words (32-bits) are added for read operation to guarantee
+ the last data is transferred from DMA FIFO to RAM memory */
+
+ /* Enable peripheral increment of the DMA */
+ hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
+
+ /* Disable memory increment of the DMA */
+ hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
+
+ /* Update peripheral/memory increment mode bits */
+ MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
+
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+
+ /* 4 Extra words (32-bits) are needed for read operation to guarantee
+ the last data is transferred from DMA FIFO to RAM memory */
+ WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U));
+
+ /* Update direction mode bit */
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Enable the DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+#else
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
+
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+ /* Enable the DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
+
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+#endif /* QSPI1_V2_1L */
+ }
+ }
+ else
+ {
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+ status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
+ * @param Timeout Time out duration
+ * @note This function is used only in Automatic Polling Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure QSPI: PSMAR register with the status match value */
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+ /* Configure QSPI: PSMKR register with the status mask value */
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+ /* Configure QSPI: PIR register with the interval value */
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+ /* Configure QSPI: CR register with Match mode and Automatic stop enabled
+ (otherwise there will be an infinite loop in blocking mode) */
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
+
+ /* Call the configuration function */
+ cmd->NbData = cfg->StatusBytesSize;
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+ /* Wait until SM flag is set to go back in idle state */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
+
+ if (status == HAL_OK)
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
+ * @note This function is used only in Automatic Polling Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
+{
+ __IO uint32_t count = 0U;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+ assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+ /* Wait till BUSY flag reset */
+ count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
+ do
+ {
+ if (count-- == 0U)
+ {
+ hqspi->State = HAL_QSPI_STATE_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ }
+ while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
+
+ if (status == HAL_OK)
+ {
+ /* Configure QSPI: PSMAR register with the status match value */
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+ /* Configure QSPI: PSMKR register with the status mask value */
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+ /* Configure QSPI: PIR register with the interval value */
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+ /* Configure QSPI: CR register with Match mode and Automatic stop mode */
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ (cfg->MatchMode | cfg->AutomaticStop));
+
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
+
+ /* Call the configuration function */
+ cmd->NbData = cfg->StatusBytesSize;
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI Transfer Error and status match Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Configure the Memory Mapped mode.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the memory mapped configuration information.
+ * @note This function is used only in Memory mapped Mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+ }
+
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+ }
+
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+ }
+
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+ assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
+
+ /* Wait till BUSY flag reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
+ if (status == HAL_OK)
+ {
+ /* Configure QSPI: CR register with timeout counter enable */
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
+
+ if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
+ {
+ assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
+
+ /* Configure QSPI: LPTR register with the low-power timeout value */
+ WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
+
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
+
+ /* Enable the QSPI TimeOut Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
+ }
+
+ /* Call the configuration function */
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
+ }
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Transfer Error callbacks
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Abort completed callback.
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_QSPI_AbortCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Command completed callback.
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_CmdCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks.
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FIFO Threshold callbacks
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Status Match callbacks
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_StatusMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timeout callbacks
+ * @param hqspi QSPI handle
+ * @retval None
+ */
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hqspi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_QSPI_TimeOutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
+ * @brief QSPI control and State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control and State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to :
+ (+) Check in run-time the state of the driver.
+ (+) Check the error code set during last operation.
+ (+) Abort any operation.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the QSPI handle state.
+ * @param hqspi QSPI handle
+ * @retval HAL state
+ */
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+{
+ /* Return QSPI handle state */
+ return hqspi->State;
+}
+
+/**
+* @brief Return the QSPI error code
+* @param hqspi QSPI handle
+* @retval QSPI Error Code
+*/
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+{
+ return hqspi->ErrorCode;
+}
+
+/**
+* @brief Abort the current transmission
+* @param hqspi QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check if the state is in one of the busy states */
+ if ((hqspi->State & 0x2U) != 0U)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ {
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Abort DMA channel */
+ status = HAL_DMA_Abort(hqspi->hdma);
+ if(status != HAL_OK)
+ {
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ }
+ }
+
+ /* Configure QSPI: CR register with Abort request */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+
+ /* Wait until TC flag is set to go back in idle state */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
+
+ if(status == HAL_OK)
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Wait until BUSY flag is reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+ }
+
+ if (status == HAL_OK)
+ {
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+
+ return status;
+}
+
+/**
+* @brief Abort the current transmission (non-blocking function)
+* @param hqspi QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check if the state is in one of the busy states */
+ if ((hqspi->State & 0x2U) != 0U)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Update QSPI state */
+ hqspi->State = HAL_QSPI_STATE_ABORT;
+
+ /* Disable all interrupts */
+ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
+
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ {
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Abort DMA channel */
+ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+ HAL_DMA_Abort_IT(hqspi->hdma);
+ }
+ else
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Enable the QSPI Transfer Complete Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+
+ /* Configure QSPI: CR register with Abort request */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+ }
+ }
+
+ return status;
+}
+
+/** @brief Set QSPI timeout
+ * @param hqspi QSPI handle.
+ * @param Timeout Timeout for the QSPI memory access.
+ * @retval None
+ */
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
+{
+ hqspi->Timeout = Timeout;
+}
+
+/** @brief Set QSPI Fifo threshold.
+ * @param hqspi QSPI handle.
+ * @param Threshold Threshold of the Fifo (value between 1 and 16).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ /* Synchronize init structure with new FIFO threshold value */
+ hqspi->Init.FifoThreshold = Threshold;
+
+ /* Configure QSPI FIFO Threshold */
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+ ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
+/** @brief Get QSPI Fifo threshold.
+ * @param hqspi QSPI handle.
+ * @retval Fifo threshold (value between 1 and 16)
+ */
+uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
+{
+ return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
+}
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief DMA QSPI receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hqspi->RxXferCount = 0U;
+
+ /* Enable the QSPI transfer complete Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+}
+
+/**
+ * @brief DMA QSPI transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hqspi->TxXferCount = 0U;
+
+ /* Enable the QSPI transfer complete Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+}
+
+/**
+ * @brief DMA QSPI receive process half complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_QSPI_RxHalfCpltCallback(hqspi);
+}
+
+/**
+ * @brief DMA QSPI transmit process half complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_QSPI_TxHalfCpltCallback(hqspi);
+}
+
+/**
+ * @brief DMA QSPI communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* if DMA error is FIFO error ignore it */
+ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+ {
+ hqspi->RxXferCount = 0U;
+ hqspi->TxXferCount = 0U;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Abort the QSPI */
+ HAL_QSPI_Abort_IT(hqspi);
+ }
+}
+
+/**
+ * @brief DMA QSPI abort complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
+{
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hqspi->RxXferCount = 0U;
+ hqspi->TxXferCount = 0U;
+
+ if(hqspi->State == HAL_QSPI_STATE_ABORT)
+ {
+ /* DMA Abort called by QSPI abort */
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+ /* Enable the QSPI Transfer Complete Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+
+ /* Configure QSPI: CR register with Abort request */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+ }
+ else
+ {
+ /* DMA Abort called due to a transfer error interrupt */
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Error callback */
+ HAL_QSPI_ErrorCallback(hqspi);
+ }
+}
+/**
+ * @brief Wait for a flag state until timeout.
+ * @param hqspi QSPI handle
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the time out
+ * @param tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
+ FlagStatus State, uint32_t tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is in expected state */
+ while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hqspi->State = HAL_QSPI_STATE_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the communication registers.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
+ * @param FunctionalMode functional mode to configured
+ * This parameter can be one of the following values:
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
+ * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
+ * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
+ * @retval None
+ */
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
+{
+ assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
+
+ if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+ {
+ /* Configure QSPI: DLR register with the number of data to read or write */
+ WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
+ }
+
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+ {
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ /* Configure QSPI: ABR register with alternate bytes value */
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with instruction, address and alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with instruction and alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
+ cmd->Instruction | FunctionalMode));
+ }
+ }
+ else
+ {
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with instruction and address ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+ cmd->Instruction | FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with only instruction ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
+ FunctionalMode));
+ }
+ }
+ }
+ else
+ {
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+ {
+ /* Configure QSPI: ABR register with alternate bytes value */
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with address and alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->InstructionMode | FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with only alternate bytes ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
+ FunctionalMode));
+ }
+ }
+ else
+ {
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+ {
+ /*---- Command with only address ----*/
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+ FunctionalMode));
+
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+ {
+ /* Configure QSPI: AR register with address value */
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);
+ }
+ }
+ else
+ {
+ /*---- Command with only data phase ----*/
+ if (cmd->DataMode != QSPI_DATA_NONE)
+ {
+ /* Configure QSPI: CCR register with all communications parameters */
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+ cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+ }
+ }
+ }
+ }
+}
+/**
+ * @}
+ */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx
+ STM32F413xx || STM32F423xx */
+
+#endif /* HAL_QSPI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,783 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_qspi.h
+ * @author MCD Application Team
+ * @brief Header file of QSPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_QSPI_H
+#define __STM32F4xx_HAL_QSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup QSPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Types QSPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief QSPI Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
+ This parameter can be a number between 0 and 255 */
+
+ uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
+ This parameter can be a value between 1 and 32 */
+
+ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
+ take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
+ This parameter can be a value of @ref QSPI_SampleShifting */
+
+ uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+ required to address the flash memory. The flash capacity can be up to 4GB
+ (addressed using 32 bits) in indirect mode, but the addressable space in
+ memory-mapped mode is limited to 256MB
+ This parameter can be a number between 0 and 31 */
+
+ uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
+ of clock cycles which the chip select must remain high between commands.
+ This parameter can be a value of @ref QSPI_ChipSelectHighTime */
+
+ uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
+ This parameter can be a value of @ref QSPI_ClockMode */
+
+ uint32_t FlashID; /* Specifies the Flash which will be used,
+ This parameter can be a value of @ref QSPI_Flash_Select */
+
+ uint32_t DualFlash; /* Specifies the Dual Flash Mode State
+ This parameter can be a value of @ref QSPI_DualFlash_Mode */
+}QSPI_InitTypeDef;
+
+/**
+ * @brief HAL QSPI State structures definition
+ */
+typedef enum
+{
+ HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
+ HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
+ HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
+ HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
+ HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
+ HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
+ HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
+ HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
+ HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
+}HAL_QSPI_StateTypeDef;
+
+/**
+ * @brief QSPI Handle Structure definition
+ */
+typedef struct
+{
+ QUADSPI_TypeDef *Instance; /* QSPI registers base address */
+ QSPI_InitTypeDef Init; /* QSPI communication parameters */
+ uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
+ __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
+ __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
+ uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
+ __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
+ __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
+ DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
+ __IO HAL_LockTypeDef Lock; /* Locking object */
+ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
+ __IO uint32_t ErrorCode; /* QSPI Error code */
+ uint32_t Timeout; /* Timeout for the QSPI memory access */
+}QSPI_HandleTypeDef;
+
+/**
+ * @brief QSPI Command structure definition
+ */
+typedef struct
+{
+ uint32_t Instruction; /* Specifies the Instruction to be sent
+ This parameter can be a value (8-bit) between 0x00 and 0xFF */
+ uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
+ uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
+ uint32_t AddressSize; /* Specifies the Address Size
+ This parameter can be a value of @ref QSPI_AddressSize */
+ uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
+ This parameter can be a value of @ref QSPI_AlternateBytesSize */
+ uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
+ This parameter can be a number between 0 and 31 */
+ uint32_t InstructionMode; /* Specifies the Instruction Mode
+ This parameter can be a value of @ref QSPI_InstructionMode */
+ uint32_t AddressMode; /* Specifies the Address Mode
+ This parameter can be a value of @ref QSPI_AddressMode */
+ uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
+ This parameter can be a value of @ref QSPI_AlternateBytesMode */
+ uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
+ This parameter can be a value of @ref QSPI_DataMode */
+ uint32_t NbData; /* Specifies the number of data to transfer.
+ This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
+ until end of memory)*/
+ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
+ This parameter can be a value of @ref QSPI_DdrMode */
+ uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
+ system clock in DDR mode.
+ This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
+ uint32_t SIOOMode; /* Specifies the send instruction only once mode
+ This parameter can be a value of @ref QSPI_SIOOMode */
+}QSPI_CommandTypeDef;
+
+/**
+ * @brief QSPI Auto Polling mode configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
+ This parameter can be any value between 0 and 0xFFFFFFFFU */
+ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
+ This parameter can be any value between 0 and 0xFFFFFFFFU */
+ uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
+ This parameter can be any value between 0 and 0xFFFFU */
+ uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
+ This parameter can be any value between 1 and 4 */
+ uint32_t MatchMode; /* Specifies the method used for determining a match.
+ This parameter can be a value of @ref QSPI_MatchMode */
+ uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
+ This parameter can be a value of @ref QSPI_AutomaticStop */
+}QSPI_AutoPollingTypeDef;
+
+/**
+ * @brief QSPI Memory Mapped mode configuration structure definition
+ */
+typedef struct
+{
+ uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+ This parameter can be any value between 0 and 0xFFFFU */
+ uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
+ This parameter can be a value of @ref QSPI_TimeOutActivation */
+}QSPI_MemoryMappedTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
+ * @{
+ */
+/** @defgroup QSPI_ErrorCode QSPI Error Code
+ * @{
+ */
+#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
+#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
+#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
+#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
+ * @{
+ */
+#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
+ * @{
+ */
+#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_ClockMode QSPI Clock Mode
+ * @{
+ */
+#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Flash_Select QSPI Flash Select
+ * @{
+ */
+#define QSPI_FLASH_ID_1 0x00000000U
+#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
+/**
+ * @}
+ */
+
+ /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
+ * @{
+ */
+#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
+#define QSPI_DUALFLASH_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AddressSize QSPI Address Size
+ * @{
+ */
+#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
+#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
+#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
+#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
+ * @{
+ */
+#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
+* @{
+*/
+#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
+#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
+#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
+#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AddressMode QSPI Address Mode
+* @{
+*/
+#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
+#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
+#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
+#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
+* @{
+*/
+#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
+#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
+#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_DataMode QSPI Data Mode
+ * @{
+ */
+#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
+#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
+#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
+#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_DdrMode QSPI Ddr Mode
+ * @{
+ */
+#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
+ * @{
+ */
+#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
+#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
+ * @{
+ */
+#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_MatchMode QSPI Match Mode
+ * @{
+ */
+#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
+ * @{
+ */
+#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
+ * @{
+ */
+#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Flags QSPI Flags
+ * @{
+ */
+#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
+#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
+#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
+#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
+#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
+#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Interrupts QSPI Interrupts
+ * @{
+ */
+#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
+#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
+#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
+#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
+#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
+ * @{
+ */
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset QSPI handle state
+ * @param __HANDLE__ QSPI handle.
+ * @retval None
+ */
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
+
+/** @brief Enable QSPI
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @retval None
+ */
+#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief Disable QSPI
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @retval None
+ */
+#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief Enables the specified QSPI interrupt.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_SM: QSPI Status match interrupt
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt
+ * @retval None
+ */
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/** @brief Disables the specified QSPI interrupt.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt
+ * @arg QSPI_IT_SM: QSPI Status match interrupt
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt
+ * @retval None
+ */
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief Checks whether the specified QSPI interrupt source is enabled.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_SM: QSPI Status match interrupt
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Get the selected QSPI's flag status.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __FLAG__ specifies the QSPI flag to check.
+ * This parameter can be one of the following values:
+ * @arg QSPI_FLAG_BUSY: QSPI Busy flag
+ * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_SM: QSPI Status match flag
+ * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag
+ * @retval None
+ */
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
+
+/** @brief Clears the specified QSPI's flag status.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __FLAG__ specifies the QSPI clear register flag that needs to be set
+ * This parameter can be one of the following values:
+ * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_SM: QSPI Status match flag
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag
+ * @retval None
+ */
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup QSPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
+/**
+ * @}
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+/* QSPI IRQ handler method */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+
+/* QSPI status flag polling mode */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
+
+/* QSPI memory-mapped mode */
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
+/**
+ * @}
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group3
+ * @{
+ */
+/* Callback functions in non-blocking modes ***********************************/
+void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI status flag polling mode */
+void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI memory-mapped mode */
+void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
+/**
+ * @}
+ */
+
+/** @addtogroup QSPI_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
+uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
+void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
+uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+ * @{
+ */
+/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
+ * @{
+ */
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
+ * @{
+ */
+#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
+/**
+ * @}
+ */
+
+#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+/** @defgroup QSPI_FlashSize QSPI Flash Size
+ * @{
+ */
+#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
+/**
+ * @}
+ */
+
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
+
+#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+ ((CLKMODE) == QSPI_CLOCK_MODE_3))
+
+#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
+ ((FLA) == QSPI_FLASH_ID_2))
+
+#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+ ((MODE) == QSPI_DUALFLASH_DISABLE))
+
+
+/** @defgroup QSPI_Instruction QSPI Instruction
+ * @{
+ */
+#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
+/**
+ * @}
+ */
+
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+
+
+/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
+ * @{
+ */
+#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
+/**
+ * @}
+ */
+
+#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
+ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
+ ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+ ((MODE) == QSPI_INSTRUCTION_4_LINES))
+
+#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
+ ((MODE) == QSPI_ADDRESS_1_LINE) || \
+ ((MODE) == QSPI_ADDRESS_2_LINES) || \
+ ((MODE) == QSPI_ADDRESS_4_LINES))
+
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+
+#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
+ ((MODE) == QSPI_DATA_1_LINE) || \
+ ((MODE) == QSPI_DATA_2_LINES) || \
+ ((MODE) == QSPI_DATA_4_LINES))
+
+#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+
+#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+
+#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+/** @defgroup QSPI_Interval QSPI Interval
+ * @{
+ */
+#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
+ * @{
+ */
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
+/**
+ * @}
+ */
+#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
+ ((MODE) == QSPI_MATCH_MODE_OR))
+
+#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+ ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+ ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
+
+/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
+ * @{
+ */
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
+/**
+ * @}
+ */
+
+#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
+ ((FLAG) == QSPI_FLAG_TO) || \
+ ((FLAG) == QSPI_FLAG_SM) || \
+ ((FLAG) == QSPI_FLAG_FT) || \
+ ((FLAG) == QSPI_FLAG_TC) || \
+ ((FLAG) == QSPI_FLAG_TE))
+
+#define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||
+ STM32F413xx || STM32F423xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_QSPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1113 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rcc.c
+ * @author MCD Application Team
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
+ and I-Cache are disabled, and all peripherals are off except internal
+ SRAM, Flash and JTAG.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+ all peripherals mapped on these busses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in input floating state, except the JTAG pins which
+ are assigned to be used for debug purpose.
+
+ [..]
+ Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB busses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals which clocks are not
+ derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+ after the clock enable bit is set on the hardware register
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+ after the clock enable bit is set on the hardware register
+
+ [..]
+ Implemented Workaround:
+ (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC
+ * @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
+
+/* Private macro -------------------------------------------------------------*/
+#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT GPIOA
+#define MCO1_PIN GPIO_PIN_8
+
+#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
+#define MCO2_GPIO_PORT GPIOC
+#define MCO2_PIN GPIO_PIN_9
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the internal/external oscillators
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
+ and APB2).
+
+ [..] Internal/external clock and PLL configuration
+ (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
+
+ (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+ (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+ (++) The first output is used to generate the high speed system clock (up to 168 MHz)
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+ the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
+
+ (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ clock source), the System clocks automatically switched to HSI and an interrupt
+ is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
+ (Non-Maskable Interrupt) exception vector.
+
+ (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+ clock (through a configurable prescaler) on PA8 pin.
+
+ (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
+ clock (through a configurable prescaler) on PC9 pin.
+
+ [..] System, AHB and APB busses clocks configuration
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these busses. You can use
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+ (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
+ frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
+ Depending on the device voltage range, the maximum frequency should
+ be adapted accordingly (refer to the product datasheets for more details).
+
+ (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
+ the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
+ Depending on the device voltage range, the maximum frequency should
+ be adapted accordingly (refer to the product datasheets for more details).
+
+ (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
+ PCLK2 84 MHz and PCLK1 42 MHz.
+ Depending on the device voltage range, the maximum frequency should
+ be adapted accordingly (refer to the product datasheets for more details).
+
+ (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
+ PCLK2 100 MHz and PCLK1 50 MHz.
+ Depending on the device voltage range, the maximum frequency should
+ be adapted accordingly (refer to the product datasheets for more details).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO1 and MCO2 OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this API. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this API. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if(RCC_OscInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is bypassed or disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ FlagStatus pwrclkchanged = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Restore clock configuration if changed */
+ if(pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the main PLL clock source, multiplication and division factors. */
+ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
+ RCC_OscInitStruct->PLL.PLLM | \
+ (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
+ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
+ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency FLASH Latency, this parameter depend on device selected
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ *
+ * @note Depending on the device voltage range, the software has to set correctly
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+ * (for more details refer to section above "Initialization/de-initialization functions")
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if(RCC_ClkInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) and the supply voltage of the device. */
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if(FLatency > __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ /* Set the highest APBx dividers in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ }
+
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+ }
+
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
+ (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLatency < __HAL_FLASH_GET_LATENCY())
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
+
+ /* Configure the source of time base considering new system clocks settings */
+ HAL_InitTick (TICK_INT_PRIORITY);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+ * @note PA8/PC9 should be configured in alternate function mode.
+ * @param RCC_MCOx specifies the output direction for the clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+ * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+ * @param RCC_MCOSource specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+ * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+ * @param RCC_MCODiv specifies the MCOx prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+ * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
+ * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
+ * @retval None
+ */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+ GPIO_InitTypeDef GPIO_InitStruct;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ /* RCC_MCO1 */
+ if(RCC_MCOx == RCC_MCO1)
+ {
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+ /* MCO1 Clock Enable */
+ __MCO1_CLK_ENABLE();
+
+ /* Configure the MCO1 pin in alternate function mode */
+ GPIO_InitStruct.Pin = MCO1_PIN;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+ /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+
+ /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
+#if defined(RCC_CFGR_MCO1EN)
+ __HAL_RCC_MCO1_ENABLE();
+#endif /* RCC_CFGR_MCO1EN */
+ }
+#if defined(RCC_CFGR_MCO2)
+ else
+ {
+ assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+ /* MCO2 Clock Enable */
+ __MCO2_CLK_ENABLE();
+
+ /* Configure the MCO2 pin in alternate function mode */
+ GPIO_InitStruct.Pin = MCO2_PIN;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+ HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+
+ /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
+
+ /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
+#if defined(RCC_CFGR_MCO2EN)
+ __HAL_RCC_MCO2_ENABLE();
+#endif /* RCC_CFGR_MCO2EN */
+ }
+#endif /* RCC_CFGR_MCO2 */
+}
+
+/**
+ * @brief Enables the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+ * @retval None
+ */
+void HAL_RCC_EnableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the Clock Security System.
+ * @retval None
+ */
+void HAL_RCC_DisableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Returns the SYSCLK frequency
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+__weak uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
+ uint32_t sysclockfreq = 0U;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLP */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ }
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
+
+ sysclockfreq = pllvco/pllp;
+ break;
+ }
+ default:
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+
+/**
+ * @brief Returns the HCLK frequency
+ * @note Each time HCLK changes, this function must be called to update the
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated within this function
+ * @retval HCLK frequency
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ return SystemCoreClock;
+}
+
+/**
+ * @brief Returns the PCLK1 frequency
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
+}
+
+/**
+ * @brief Returns the PCLK2 frequency
+ * @note Each time PCLK2 changes, this function must be called to update the
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK2 frequency
+ */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
+}
+
+/**
+ * @brief Configures the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+ * will be configured.
+ * @param pFLatency Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+ * @brief This function handles the RCC CSS interrupt request.
+ * @note This API should be called under the NMI_Handler().
+ * @retval None
+ */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+ /* Check RCC CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+ {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_CSSCallback();
+
+ /* Clear RCC CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ }
+}
+
+/**
+ * @brief RCC Clock Security System interrupt callback
+ * @retval None
+ */
+__weak void HAL_RCC_CSSCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RCC_CSSCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1480 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_H
+#define __STM32F4xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/* Include RCC HAL Extended module */
+/* (include on top of file since RCC structures are defined in extended file) */
+#include "stm32f4xx_hal_rcc_ex.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+}RCC_OscInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
+
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE 0x00000000U
+#define RCC_OSCILLATORTYPE_HSE 0x00000001U
+#define RCC_OSCILLATORTYPE_HSI 0x00000002U
+#define RCC_OSCILLATORTYPE_LSE 0x00000004U
+#define RCC_OSCILLATORTYPE_LSI 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config HSE Config
+ * @{
+ */
+#define RCC_HSE_OFF 0x00000000U
+#define RCC_HSE_ON RCC_CR_HSEON
+#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config LSE Config
+ * @{
+ */
+#define RCC_LSE_OFF 0x00000000U
+#define RCC_LSE_ON RCC_BDCR_LSEON
+#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config HSI Config
+ * @{
+ */
+#define RCC_HSI_OFF ((uint8_t)0x00)
+#define RCC_HSI_ON ((uint8_t)0x01)
+
+#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint8_t)0x00)
+#define RCC_LSI_ON ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint8_t)0x00)
+#define RCC_PLL_OFF ((uint8_t)0x01)
+#define RCC_PLL_ON ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
+ * @{
+ */
+#define RCC_PLLP_DIV2 0x00000002U
+#define RCC_PLLP_DIV4 0x00000004U
+#define RCC_PLLP_DIV6 0x00000006U
+#define RCC_PLLP_DIV8 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+ * @{
+ */
+#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
+#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
+#define RCC_CLOCKTYPE_HCLK 0x00000002U
+#define RCC_CLOCKTYPE_PCLK1 0x00000004U
+#define RCC_CLOCKTYPE_PCLK2 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+ * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
+ * STM32F446xx devices.
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
+#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
+ * STM32F446xx devices.
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
+#define RCC_RTCCLKSOURCE_LSE 0x00000100U
+#define RCC_RTCCLKSOURCE_LSI 0x00000200U
+#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
+#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
+#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
+#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
+#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
+#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
+#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
+#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
+#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
+#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
+#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
+#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
+#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
+#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
+#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
+#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
+#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
+#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
+#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
+#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Index MCO Index
+ * @{
+ */
+#define RCC_MCO1 0x00000000U
+#define RCC_MCO2 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_HSI 0x00000000U
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
+ * @{
+ */
+#define RCC_MCODIV_1 0x00000000U
+#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt Interrupts
+ * @{
+ */
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
+#define RCC_IT_CSS ((uint8_t)0x80)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag Flags
+ * Elements values convention: 0XXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - 0XX : Register index
+ * - 01: CR register
+ * - 10: BDCR register
+ * - 11: CSR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+#define RCC_FLAG_BORRST ((uint8_t)0x79)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+
+#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
+
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
+
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param __HSICalibrationValue__ specifies the calibration trimming value.
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
+ RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
+ * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param __STATE__ specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator.
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \
+ do { \
+ if ((__STATE__) == RCC_HSE_ON) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if ((__STATE__) == RCC_HSE_BYPASS) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ } while(0U)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+ * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param __STATE__ specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator.
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+ do { \
+ if((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else if((__STATE__) == RCC_LSE_BYPASS) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ } while(0U)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
+
+/** @brief Macros to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+ * a Power On Reset (POR).
+ * @param __RTCCLKSource__ specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
+ * as RTC clock, where x:[2,31]
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wake-up source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
+ * RTC clock source).
+ */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
+ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
+ } while(0U)
+
+/** @brief Macro to get the RTC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/**
+ * @brief Get the RTC and HSE clock divider (RTCPRE).
+ * @retval Returned value can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
+ * as RTC clock, where x:[2,31]
+ */
+#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
+
+/** @brief Macros to force or release the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_CSR register.
+ * @note The BKPSRAM is not affected by this reset.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
+
+/** @brief Macro to configure the PLL clock source.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __PLLSOURCE__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ *
+ */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief Macro to configure the PLL multiplication factor.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ *
+ */
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+ * @{
+ */
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
+ * This parameter can be one of the following values:
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
+ * parameter is available only for STM32F446xx devices.
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
+ * is available only for STM32F446xx devices.
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
+
+/** @brief Macro to get the oscillator used as PLL clock source.
+ * @retval The oscillator used as PLL clock source. The returned value can be one
+ * of the following:
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the MCO1 clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+ * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+ */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @brief Macro to configure the MCO2 clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+ * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+ * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
+ * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
+ */
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+ * the selected interrupts).
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+ * the selected interrupts).
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
+
+/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+ * bits to clear the selected interrupt pending bits.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__ specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+ * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
+ * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
+ * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
+ * @arg RCC_FLAG_PINRST: Pin reset.
+ * @arg RCC_FLAG_PORRST: POR/PDR reset.
+ * @arg RCC_FLAG_SFTRST: Software reset.
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+ * @arg RCC_FLAG_LPWRRST: Low Power reset.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define RCC_FLAG_MASK ((uint8_t)0x1FU)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+ /** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+/* --- CR Register --- */
+/* Alias word address of HSION bit */
+#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
+#define RCC_HSION_BIT_NUMBER 0x00U
+#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
+/* Alias word address of CSSON bit */
+#define RCC_CSSON_BIT_NUMBER 0x13U
+#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
+/* Alias word address of PLLON bit */
+#define RCC_PLLON_BIT_NUMBER 0x18U
+#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
+
+/* --- BDCR Register --- */
+/* Alias word address of RTCEN bit */
+#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
+#define RCC_RTCEN_BIT_NUMBER 0x0FU
+#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
+/* Alias word address of BDRST bit */
+#define RCC_BDRST_BIT_NUMBER 0x10U
+#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
+
+/* --- CSR Register --- */
+/* Alias word address of LSION bit */
+#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
+#define RCC_LSION_BIT_NUMBER 0x00U
+#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS 0x40023802U
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
+
+/* BDCR register base address */
+#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
+
+#define RCC_DBP_TIMEOUT_VALUE 2U
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
+#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+ * @{
+ */
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
+
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
+
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
+
+#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
+ ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
+ ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
+ ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
+ ((HCLK) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
+ ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
+ ((PCLK) == RCC_HCLK_DIV16))
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+ ((DIV) == RCC_MCODIV_5))
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,3758 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @brief Extension RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extension peripheral:
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCCEx HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ [..]
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
+ the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F446xx)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals
+ * clocks(I2S, SAI, LTDC RTC and TIM).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg1 = 0U;
+ uint32_t plli2sp = 0U;
+ uint32_t plli2sq = 0U;
+ uint32_t plli2sr = 0U;
+ uint32_t pllsaip = 0U;
+ uint32_t pllsaiq = 0U;
+ uint32_t plli2sused = 0U;
+ uint32_t pllsaiused = 0U;
+
+ /* Check the peripheral clock selection parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*------------------------ I2S APB1 configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
+
+ /* Configure I2S Clock source */
+ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for I2S */
+ if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1U;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- I2S APB2 configuration ----------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
+
+ /* Configure I2S Clock source */
+ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for I2S */
+ if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1U;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*--------------------------- SAI1 configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+ /* Configure SAI1 Clock source */
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1U;
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+ {
+ pllsaiused = 1U;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*-------------------------- SAI2 configuration ----------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+ /* Configure SAI2 Clock source */
+ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1U;
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+ {
+ pllsaiused = 1U;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------------- RTC configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- TIM configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ /* Configure Timer Prescaler */
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- FMPI2C1 Configuration -----------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+ /* Configure the FMPI2C1 clock source */
+ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------ CEC Configuration -------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------------- CLK48 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+ /* Configure the CLK48 clock source */
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+ /* Enable the PLLSAI when it's used as clock source for CLK48 */
+ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
+ {
+ pllsaiused = 1U;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------------- SDIO Configuration -------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+ /* Configure the SDIO clock source */
+ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------ SPDIFRX Configuration ---------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
+
+ /* Configure the SPDIFRX clock source */
+ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for SPDIFRX */
+ if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
+ {
+ plli2sused = 1U;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- PLLI2S Configuration ------------------------*/
+ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
+ I2S on APB2 or SPDIFRX */
+ if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+ {
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* check for common PLLI2S Parameters */
+ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+ /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+ /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
+ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+ plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
+ {
+ /* Check for PLLI2S Parameters */
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ /* Check for PLLI2S/DIVQ parameters */
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+ /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+ plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ }
+
+ /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+ plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
+ }
+
+ /*----------------- In Case of PLLI2S is just selected -----------------*/
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+ {
+ /* Check for Parameters */
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------------- PLLSAI Configuration -----------------------*/
+ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
+ if(pllsaiused == 1U)
+ {
+ /* Disable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is disabled */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check the PLLSAI division factors */
+ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+ /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
+ {
+ /* check for PLLSAIQ Parameter */
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+ /* check for PLLSAI/DIVQ Parameter */
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+ }
+
+ /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
+ /* In Case of PLLI2S is selected as source clock for CLK48 */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+ /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ /* Configure the PLLSAI division factors */
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
+ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
+ }
+
+ /* Enable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is ready */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\
+ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO |\
+ RCC_PERIPHCLK_SPDIFRX;
+
+ /* Get the PLLI2S Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ /* Get the PLLSAI Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
+
+ /* Get the SAI1 clock configuration ----------------------------------------*/
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+
+ /* Get the SAI2 clock configuration ----------------------------------------*/
+ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+
+ /* Get the I2S APB1 clock configuration ------------------------------------*/
+ PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
+
+ /* Get the I2S APB2 clock configuration ------------------------------------*/
+ PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
+
+ /* Get the RTC Clock configuration -----------------------------------------*/
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+ /* Get the CEC clock configuration -----------------------------------------*/
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+
+ /* Get the FMPI2C1 clock configuration -------------------------------------*/
+ PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+ /* Get the CLK48 clock configuration ----------------------------------------*/
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+ /* Get the SDIO clock configuration ----------------------------------------*/
+ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+ /* Get the SPDIFRX clock configuration -------------------------------------*/
+ PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
+
+ /* Get the TIM Prescaler configuration -------------------------------------*/
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+}
+
+/**
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
+ * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
+ * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
+ * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
+ * @retval Frequency in KHz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ uint32_t tmpreg1 = 0U;
+ /* This variable used to store the SAI clock frequency (value in Hz) */
+ uint32_t frequency = 0U;
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0U;
+ /* This variable used to store the SAI clock source */
+ uint32_t saiclocksource = 0U;
+ uint32_t srcclk = 0U;
+ /* This variable used to store the VCO Output (value in Hz) */
+ uint32_t vcooutput = 0U;
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_SAI1:
+ case RCC_PERIPHCLK_SAI2:
+ {
+ saiclocksource = RCC->DCKCFGR;
+ saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
+ switch (saiclocksource)
+ {
+ case 0U: /* PLLSAI is the clock source for SAI*/
+ {
+ /* Configure the PLLSAI division factor */
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
+ }
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
+ frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
+ frequency = frequency/(tmpreg1);
+ break;
+ }
+ case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
+ case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
+ frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
+ frequency = frequency/(tmpreg1);
+ break;
+ }
+ case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
+ case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ /* SAI_CLK_x = PLL_VCO Output/PLLR */
+ tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
+ frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
+ break;
+ }
+ case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
+ {
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ frequency = (uint32_t)(HSI_VALUE);
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ frequency = (uint32_t)(HSE_VALUE);
+ }
+ break;
+ }
+ default :
+ {
+ break;
+ }
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_I2S_APB1:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
+ switch (srcclk)
+ {
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SAPB1CLKSOURCE_EXT:
+ {
+ /* Set the I2S clock to the external clock value */
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+ case RCC_I2SAPB1CLKSOURCE_PLLI2S:
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+ break;
+ }
+ /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+ case RCC_I2SAPB1CLKSOURCE_PLLR:
+ {
+ /* Configure the PLL division factor R */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+ /* I2S_CLK = PLL_VCO Output/PLLR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+ break;
+ }
+ /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+ case RCC_I2SAPB1CLKSOURCE_PLLSRC:
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ frequency = HSE_VALUE;
+ }
+ else
+ {
+ frequency = HSI_VALUE;
+ }
+ break;
+ }
+ /* Clock not enabled for I2S*/
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_I2S_APB2:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
+ switch (srcclk)
+ {
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SAPB2CLKSOURCE_EXT:
+ {
+ /* Set the I2S clock to the external clock value */
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+ case RCC_I2SAPB2CLKSOURCE_PLLI2S:
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+ break;
+ }
+ /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+ case RCC_I2SAPB2CLKSOURCE_PLLR:
+ {
+ /* Configure the PLL division factor R */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+ /* I2S_CLK = PLL_VCO Output/PLLR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+ break;
+ }
+ /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+ case RCC_I2SAPB2CLKSOURCE_PLLSRC:
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ frequency = HSE_VALUE;
+ }
+ else
+ {
+ frequency = HSI_VALUE;
+ }
+ break;
+ }
+ /* Clock not enabled for I2S*/
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ return frequency;
+}
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals
+ * clocks(I2S, SAI, LTDC, RTC and TIM).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg1 = 0U;
+ uint32_t pllsaip = 0U;
+ uint32_t pllsaiq = 0U;
+ uint32_t pllsair = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*--------------------------- CLK48 Configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+ /* Configure the CLK48 clock source */
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------ SDIO Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+ /* Configure the SDIO clock source */
+ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
+ /*------------------- Common configuration SAI/I2S -------------------------*/
+ /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+ factor is common parameters for both peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*---------------------- I2S configuration -------------------------------*/
+ /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+ only for I2S configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /*---------------------------- SAI configuration -------------------------*/
+ /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+ be added only for SAI configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+ {
+ /* Check the PLLI2S division factors */
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ }
+
+ /*----------------- In Case of PLLI2S is just selected -----------------*/
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+ {
+ /* Check for Parameters */
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+ /* Configure the PLLI2S multiplication and division factors */
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
+ /*----------------------- Common configuration SAI/LTDC --------------------*/
+ /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
+ factor is common parameters for these peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) &&
+ (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
+ {
+ /* Check the PLLSAI division factors */
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+ /* Disable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is disabled */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*---------------------------- SAI configuration -------------------------*/
+ /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+ be added only for SAI configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+ {
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+ /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+ }
+
+ /*---------------------------- LTDC configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+ {
+ assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+ /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+ }
+
+ /*---------------------------- CLK48 configuration ------------------------*/
+ /* Configure the PLLSAI when it is used as clock source for CLK48 */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
+ (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
+ {
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+
+ /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
+ }
+
+ /* Enable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is ready */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- RTC configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- TIM configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\
+ RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
+ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO;
+
+ /* Get the PLLI2S Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ /* Get the PLLSAI Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
+ /* Get the RTC Clock configuration -----------------------------------------*/
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+ /* Get the CLK48 clock configuration -------------------------------------*/
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+ /* Get the SDIO clock configuration ----------------------------------------*/
+ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+}
+
+/**
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+ * @retval Frequency in KHz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ /* This variable used to store the I2S clock frequency (value in Hz) */
+ uint32_t frequency = 0U;
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0U;
+ uint32_t srcclk = 0U;
+ /* This variable used to store the VCO Output (value in Hz) */
+ uint32_t vcooutput = 0U;
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_I2S:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_SOURCE();
+ switch (srcclk)
+ {
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SCLKSOURCE_EXT:
+ {
+ /* Set the I2S clock to the external clock value */
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+ case RCC_I2SCLKSOURCE_PLLI2S:
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+ break;
+ }
+ /* Clock not enabled for I2S*/
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ return frequency;
+}
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals
+ * clocks(I2S, LTDC RTC and TIM).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg1 = 0U;
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ uint32_t plli2sq = 0U;
+#endif /* STM32F413xx || STM32F423xx */
+ uint32_t plli2sused = 0U;
+
+ /* Check the peripheral clock selection parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*----------------------------------- I2S APB1 configuration ---------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
+
+ /* Configure I2S Clock source */
+ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for I2S */
+ if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1U;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------------------- I2S APB2 configuration ---------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
+
+ /* Configure I2S Clock source */
+ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for I2S */
+ if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
+ {
+ plli2sused = 1U;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ /*----------------------- SAI1 Block A configuration -----------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection));
+
+ /* Configure SAI1 Clock source */
+ __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)
+ {
+ plli2sused = 1U;
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)
+ {
+ /* Check for PLL/DIVR parameters */
+ assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+ __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------- SAI1 Block B configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection));
+
+ /* Configure SAI1 Clock source */
+ __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection);
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)
+ {
+ plli2sused = 1U;
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)
+ {
+ /* Check for PLL/DIVR parameters */
+ assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+ __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+#endif /* STM32F413xx || STM32F423xx */
+
+ /*------------------------------------ RTC configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------------ TIM configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ /* Configure Timer Prescaler */
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------------- FMPI2C1 Configuration --------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+ /* Configure the FMPI2C1 clock source */
+ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------------- CLK48 Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+ /* Configure the SDIO clock source */
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+ /* Enable the PLLI2S when it's used as clock source for CLK48 */
+ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
+ {
+ plli2sused = 1U;
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*------------------------------------- SDIO Configuration -----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+ /* Configure the SDIO clock source */
+ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*-------------------------------------- PLLI2S Configuration --------------*/
+ /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
+ I2S on APB2*/
+ if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+ {
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* check for common PLLI2S Parameters */
+ assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));
+ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+ /*-------------------- Set the PLL I2S clock -----------------------------*/
+ __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
+
+ /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) ||
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
+ {
+ /* Check for PLLI2S Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ /* Check for PLLI2S/DIVR parameters */
+ assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR));
+
+ /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+ plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);
+ }
+#endif /* STM32F413xx || STM32F423xx */
+
+ /*----------------- In Case of PLLI2S is just selected ------------------*/
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+ {
+ /* Check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*-------------------- DFSDM1 clock source configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+ /* Configure the DFSDM1 interface clock source */
+ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*-------------------- DFSDM1 Audio clock source configuration -------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
+
+ /* Configure the DFSDM1 Audio interface clock source */
+ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ /*-------------------- DFSDM2 clock source configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
+
+ /* Configure the DFSDM1 interface clock source */
+ __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*-------------------- DFSDM2 Audio clock source configuration -------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection));
+
+ /* Configure the DFSDM1 Audio interface clock source */
+ __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- LPTIM1 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+ /* Configure the LPTIM1 clock source */
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+#endif /* STM32F413xx || STM32F423xx */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
+ RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 |\
+ RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\
+ RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2 |\
+ RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1 |\
+ RCC_PERIPHCLK_SAIA | RCC_PERIPHCLK_SAIB;
+#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
+ RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 |\
+ RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\
+ RCC_PERIPHCLK_DFSDM1_AUDIO;
+#endif /* STM32F413xx || STM32F423xx */
+
+
+
+ /* Get the PLLI2S Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ /* Get the PLL/PLLI2S division factors -------------------------------------*/
+ PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos);
+ PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos);
+#endif /* STM32F413xx || STM32F423xx */
+
+ /* Get the I2S APB1 clock configuration ------------------------------------*/
+ PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
+
+ /* Get the I2S APB2 clock configuration ------------------------------------*/
+ PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
+
+ /* Get the RTC Clock configuration -----------------------------------------*/
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+ /* Get the FMPI2C1 clock configuration -------------------------------------*/
+ PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+ /* Get the CLK48 clock configuration ---------------------------------------*/
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+ /* Get the SDIO clock configuration ----------------------------------------*/
+ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+ /* Get the DFSDM1 clock configuration --------------------------------------*/
+ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
+
+ /* Get the DFSDM1 Audio clock configuration --------------------------------*/
+ PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ /* Get the DFSDM2 clock configuration --------------------------------------*/
+ PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
+
+ /* Get the DFSDM2 Audio clock configuration --------------------------------*/
+ PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE();
+
+ /* Get the LPTIM1 clock configuration --------------------------------------*/
+ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+ /* Get the SAI1 Block Aclock configuration ---------------------------------*/
+ PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE();
+
+ /* Get the SAI1 Block B clock configuration --------------------------------*/
+ PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE();
+#endif /* STM32F413xx || STM32F423xx */
+
+ /* Get the TIM Prescaler configuration -------------------------------------*/
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+}
+
+/**
+ * @brief Return the peripheral clock frequency for a given peripheral(I2S..)
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
+ * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
+ * @retval Frequency in KHz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ /* This variable used to store the I2S clock frequency (value in Hz) */
+ uint32_t frequency = 0U;
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0U;
+ uint32_t srcclk = 0U;
+ /* This variable used to store the VCO Output (value in Hz) */
+ uint32_t vcooutput = 0U;
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_I2S_APB1:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
+ switch (srcclk)
+ {
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SAPB1CLKSOURCE_EXT:
+ {
+ /* Set the I2S clock to the external clock value */
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+ case RCC_I2SAPB1CLKSOURCE_PLLI2S:
+ {
+ if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ }
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+ break;
+ }
+ /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+ case RCC_I2SAPB1CLKSOURCE_PLLR:
+ {
+ /* Configure the PLL division factor R */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+ /* I2S_CLK = PLL_VCO Output/PLLR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+ break;
+ }
+ /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+ case RCC_I2SAPB1CLKSOURCE_PLLSRC:
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ frequency = HSE_VALUE;
+ }
+ else
+ {
+ frequency = HSI_VALUE;
+ }
+ break;
+ }
+ /* Clock not enabled for I2S*/
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_I2S_APB2:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
+ switch (srcclk)
+ {
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SAPB2CLKSOURCE_EXT:
+ {
+ /* Set the I2S clock to the external clock value */
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+ case RCC_I2SAPB2CLKSOURCE_PLLI2S:
+ {
+ if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ }
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+ break;
+ }
+ /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+ case RCC_I2SAPB2CLKSOURCE_PLLR:
+ {
+ /* Configure the PLL division factor R */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+ /* I2S_CLK = PLL_VCO Output/PLLR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+ break;
+ }
+ /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+ case RCC_I2SAPB2CLKSOURCE_PLLSRC:
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ frequency = HSE_VALUE;
+ }
+ else
+ {
+ frequency = HSI_VALUE;
+ }
+ break;
+ }
+ /* Clock not enabled for I2S*/
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ return frequency;
+}
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
+ * RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+ *
+ * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+ * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+ * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg1 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- RTC configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- TIM configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- FMPI2C1 Configuration -----------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+ /* Configure the FMPI2C1 clock source */
+ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- LPTIM1 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+ /* Configure the LPTIM1 clock source */
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ }
+
+ /*---------------------------- I2S Configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
+
+ /* Configure the I2S clock source */
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+ /* Get the FMPI2C1 clock configuration -------------------------------------*/
+ PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+ /* Get the I2S clock configuration -----------------------------------------*/
+ PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
+
+
+}
+/**
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+ * @retval Frequency in KHz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ /* This variable used to store the I2S clock frequency (value in Hz) */
+ uint32_t frequency = 0U;
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0U;
+ uint32_t srcclk = 0U;
+ /* This variable used to store the VCO Output (value in Hz) */
+ uint32_t vcooutput = 0U;
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_I2S:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_SOURCE();
+ switch (srcclk)
+ {
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SAPBCLKSOURCE_EXT:
+ {
+ /* Set the I2S clock to the external clock value */
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+ case RCC_I2SAPBCLKSOURCE_PLLR:
+ {
+ /* Configure the PLL division factor R */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+ /* I2S_CLK = PLL_VCO Output/PLLR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+ break;
+ }
+ /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+ case RCC_I2SAPBCLKSOURCE_PLLSRC:
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ frequency = HSE_VALUE;
+ }
+ else
+ {
+ frequency = HSI_VALUE;
+ }
+ break;
+ }
+ /* Clock not enabled for I2S*/
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ return frequency;
+}
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals
+ * clocks(I2S, SAI, LTDC RTC and TIM).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg1 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
+ /*----------------------- Common configuration SAI/I2S ---------------------*/
+ /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+ factor is common parameters for both peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*---------------------------- I2S configuration -------------------------*/
+ /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+ only for I2S configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
+ /*---------------------------- SAI configuration -------------------------*/
+ /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+ be added only for SAI configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+ {
+ /* Check the PLLI2S division factors */
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ }
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
+ /*----------------------- Common configuration SAI/LTDC --------------------*/
+ /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
+ factor is common parameters for both peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
+ {
+ /* Check the PLLSAI division factors */
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+ /* Disable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is disabled */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*---------------------------- SAI configuration -------------------------*/
+ /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+ be added only for SAI configuration */
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+ {
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+ /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+ }
+
+ /*---------------------------- LTDC configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+ {
+ assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+ /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+ }
+ /* Enable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLSAI is ready */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- RTC configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ /*--------------------------------------------------------------------------*/
+
+ /*---------------------------- TIM configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the PeriphClkInit according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+
+ /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
+ /* Get the RTC Clock configuration -----------------------------------------------*/
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+}
+
+/**
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+ * @retval Frequency in KHz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ /* This variable used to store the I2S clock frequency (value in Hz) */
+ uint32_t frequency = 0U;
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0U;
+ uint32_t srcclk = 0U;
+ /* This variable used to store the VCO Output (value in Hz) */
+ uint32_t vcooutput = 0U;
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_I2S:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_SOURCE();
+ switch (srcclk)
+ {
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SCLKSOURCE_EXT:
+ {
+ /* Set the I2S clock to the external clock value */
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+ case RCC_I2SCLKSOURCE_PLLI2S:
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+ break;
+ }
+ /* Clock not enabled for I2S */
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ return frequency;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
+ * RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+ *
+ * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+ * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+ * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg1 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- I2S configuration ---------------------------*/
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+#if defined(STM32F411xE)
+ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+#endif /* STM32F411xE */
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+#if defined(STM32F411xE)
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
+#else
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+#endif /* STM32F411xE */
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /*---------------------------- RTC configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg1;
+
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ /*---------------------------- TIM configuration ---------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ {
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ }
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tempreg;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
+
+ /* Get the PLLI2S Clock configuration --------------------------------------*/
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+#if defined(STM32F411xE)
+ PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
+#endif /* STM32F411xE */
+ /* Get the RTC Clock configuration -----------------------------------------*/
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ /* Get the TIM Prescaler configuration -------------------------------------*/
+ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ }
+ else
+ {
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ }
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+}
+
+/**
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+ * @retval Frequency in KHz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ /* This variable used to store the I2S clock frequency (value in Hz) */
+ uint32_t frequency = 0U;
+ /* This variable used to store the VCO Input (value in Hz) */
+ uint32_t vcoinput = 0U;
+ uint32_t srcclk = 0U;
+ /* This variable used to store the VCO Output (value in Hz) */
+ uint32_t vcooutput = 0U;
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_I2S:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_SOURCE();
+ switch (srcclk)
+ {
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SCLKSOURCE_EXT:
+ {
+ /* Set the I2S clock to the external clock value */
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+ case RCC_I2SCLKSOURCE_PLLI2S:
+ {
+#if defined(STM32F411xE)
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+ }
+#else
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+#endif /* STM32F411xE */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+ /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+ frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+ break;
+ }
+ /* Clock not enabled for I2S*/
+ default:
+ {
+ frequency = 0U;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ return frequency;
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief Select LSE mode
+ *
+ * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
+ *
+ * @param Mode specifies the LSE mode.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
+ * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
+ * @retval None
+ */
+void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE_MODE(Mode));
+ if(Mode == RCC_LSE_HIGHDRIVE_MODE)
+ {
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+ }
+}
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ * @brief Extended Clock management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended clock management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the
+ activation or deactivation of PLLI2S, PLLSAI.
+@endverbatim
+ * @{
+ */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Enable PLLI2S.
+ * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
+ * contains the configuration information for the PLLI2S
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
+{
+ uint32_t tickstart;
+
+ /* Check for parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+ assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM));
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+ assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Wait till PLLI2S is disabled */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the PLLI2S division factors */
+#if defined(STM32F446xx)
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ /* I2SPCLK = PLLI2S_VCO / PLLI2SP */
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
+ PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
+ PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F411xE)
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
+#else
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
+#endif /* STM32F446xx */
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+
+ /* Wait till PLLI2S is ready */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLLI2S.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+{
+ uint32_t tickstart;
+
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Wait till PLLI2S is disabled */
+ tickstart = HAL_GetTick();
+ while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+ * @brief Enable PLLSAI.
+ * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that
+ * contains the configuration information for the PLLSAI
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
+{
+ uint32_t tickstart;
+
+ /* Check for parameters */
+ assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+ assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM));
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+ assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+ assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+ /* Disable the PLLSAI */
+ __HAL_RCC_PLLSAI_DISABLE();
+
+ /* Wait till PLLSAI is disabled */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the PLLSAI division factors */
+#if defined(STM32F446xx)
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */
+ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+ /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \
+ PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U);
+#elif defined(STM32F469xx) || defined(STM32F479xx)
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+ /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
+ PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#else
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+ /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#endif /* STM32F446xx */
+
+ /* Enable the PLLSAI */
+ __HAL_RCC_PLLSAI_ENABLE();
+
+ /* Wait till PLLSAI is ready */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLLSAI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
+{
+ uint32_t tickstart;
+
+ /* Disable the PLLSAI */
+ __HAL_RCC_PLLSAI_DISABLE();
+
+ /* Wait till PLLSAI is disabled */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F446xx)
+/**
+ * @brief Returns the SYSCLK frequency
+ *
+ * @note This function implementation is valid only for STM32F446xx devices.
+ * @note This function add the PLL/PLLR System clock source
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+ * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ uint32_t pllm = 0U;
+ uint32_t pllvco = 0U;
+ uint32_t pllp = 0U;
+ uint32_t pllr = 0U;
+ uint32_t sysclockfreq = 0U;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLP */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ }
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
+
+ sysclockfreq = pllvco/pllp;
+ break;
+ }
+ case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ }
+ pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
+
+ sysclockfreq = pllvco/pllr;
+ break;
+ }
+ default:
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+#endif /* STM32F446xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE, PLL, PLLI2S and PLLSAI OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO1 and MCO2 OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+ uint32_t tickstart;
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Set HSION bit to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set HSITRIM[4:0] bits to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Wait till clock switch is ready */
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Clear HSEON, HSEBYP and CSSON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+
+ /* Wait till HSE is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Clear PLLON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+
+ /* Wait till PLL is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+#if defined(RCC_PLLI2S_SUPPORT)
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Reset PLLI2SON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+
+ /* Wait till PLLI2S is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Reset PLLSAI bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+
+ /* Wait till PLLSAI is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+#endif /* RCC_PLLSAI_SUPPORT */
+
+ /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
+#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
+ defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1;
+#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3;
+#else
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2;
+#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+ /* Reset PLLI2SCFGR register to default value */
+#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
+ defined(STM32F423xx) || defined(STM32F446xx)
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F411xE)
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */
+
+ /* Reset PLLSAICFGR register */
+#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1;
+#elif defined(STM32F446xx)
+ RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2;
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+ /* Disable all interrupts */
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
+
+#if defined(RCC_CIR_PLLI2SRDYIE)
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+#endif /* RCC_CIR_PLLI2SRDYIE */
+
+#if defined(RCC_CIR_PLLSAIRDYIE)
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+#endif /* RCC_CIR_PLLSAIRDYIE */
+
+ /* Clear all interrupt flags */
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
+
+#if defined(RCC_CIR_PLLI2SRDYC)
+ SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+#endif /* RCC_CIR_PLLI2SRDYC */
+
+#if defined(RCC_CIR_PLLSAIRDYC)
+ SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+#endif /* RCC_CIR_PLLSAIRDYC */
+
+ /* Clear LSION bit */
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+ /* Reset all CSR flags */
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HSI_VALUE;
+
+ /* Adapt Systick interrupt period */
+ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+}
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this API. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this API. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @note This function add the PLL/PLLR factor management during PLL configuration this feature
+ * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+#if defined(STM32F446xx)
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+#else
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+#endif /* STM32F446xx */
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is bypassed or disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+#if defined(STM32F446xx)
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+#else
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+#endif /* STM32F446xx */
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ FlagStatus pwrclkchanged = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Restore clock configuration if changed */
+ if(pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+ }
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the main PLL clock source, multiplication and division factors. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN,
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ,
+ RCC_OscInitStruct->PLL.PLLR);
+
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
+ *
+ * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
+ * @note This function add the PLL/PLLR factor management
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
+ RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
+}
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,7119 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_EX_H
+#define __STM32F4xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
+
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432
+ except for STM32F411xE devices where the Min_Data = 192 */
+
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
+
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+ uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+ This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
+ and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+}RCC_PLLInitTypeDef;
+
+#if defined(STM32F446xx)
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
+
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
+
+ uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
+ This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
+
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+}RCC_PLLI2SInitTypeDef;
+
+/**
+ * @brief PLLSAI Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
+
+ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
+
+ uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
+ This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
+
+ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+}RCC_PLLSAIInitTypeDef;
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
+
+ uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
+
+ uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
+
+ uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+
+ uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+ uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+ uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
+
+ uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
+ This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F446xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+
+ uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
+
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
+
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+}RCC_PLLI2SInitTypeDef;
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLL is selected as Clock Source SAI */
+
+ uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+#endif /* STM32F413xx || STM32F423xx */
+
+ uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
+
+ uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+
+ uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+ uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
+ This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+
+ uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
+ This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
+
+ uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
+ This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection.
+ This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
+
+ uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
+ This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
+
+ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+
+ uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection
+ This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
+
+ uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection
+ This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
+#endif /* STM32F413xx || STM32F423xx */
+
+ uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
+
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+}RCC_PLLI2SInitTypeDef;
+
+/**
+ * @brief PLLSAI Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
+ This parameter is only available in STM32F469xx/STM32F479xx devices.
+ This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
+#endif /* STM32F469xx || STM32F479xx */
+
+ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
+
+}RCC_PLLSAIInitTypeDef;
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+ uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
+ This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
+ This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+
+ uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+#endif /* STM32F469xx || STM32F479xx */
+}RCC_PeriphCLKInitTypeDef;
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+#if defined(STM32F411xE)
+ uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
+#endif /* STM32F411xE */
+
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432
+ Except for STM32F411xE devices where the Min_Data = 192.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+}RCC_PLLI2SInitTypeDef;
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
+ * @{
+ */
+/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
+#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
+#define RCC_PERIPHCLK_TIM 0x00000004U
+#define RCC_PERIPHCLK_RTC 0x00000008U
+#define RCC_PERIPHCLK_FMPI2C1 0x00000010U
+#define RCC_PERIPHCLK_CLK48 0x00000020U
+#define RCC_PERIPHCLK_SDIO 0x00000040U
+#define RCC_PERIPHCLK_PLLI2S 0x00000080U
+#define RCC_PERIPHCLK_DFSDM1 0x00000100U
+#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
+#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define RCC_PERIPHCLK_DFSDM2 0x00000400U
+#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
+#define RCC_PERIPHCLK_LPTIM1 0x00001000U
+#define RCC_PERIPHCLK_SAIA 0x00002000U
+#define RCC_PERIPHCLK_SAIB 0x00004000U
+#endif /* STM32F413xx || STM32F423xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- Peripheral Clock source for STM32F410xx ----------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define RCC_PERIPHCLK_I2S 0x00000001U
+#define RCC_PERIPHCLK_TIM 0x00000002U
+#define RCC_PERIPHCLK_RTC 0x00000004U
+#define RCC_PERIPHCLK_FMPI2C1 0x00000008U
+#define RCC_PERIPHCLK_LPTIM1 0x00000010U
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- Peripheral Clock source for STM32F446xx ----------------*/
+#if defined(STM32F446xx)
+#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
+#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
+#define RCC_PERIPHCLK_SAI1 0x00000004U
+#define RCC_PERIPHCLK_SAI2 0x00000008U
+#define RCC_PERIPHCLK_TIM 0x00000010U
+#define RCC_PERIPHCLK_RTC 0x00000020U
+#define RCC_PERIPHCLK_CEC 0x00000040U
+#define RCC_PERIPHCLK_FMPI2C1 0x00000080U
+#define RCC_PERIPHCLK_CLK48 0x00000100U
+#define RCC_PERIPHCLK_SDIO 0x00000200U
+#define RCC_PERIPHCLK_SPDIFRX 0x00000400U
+#define RCC_PERIPHCLK_PLLI2S 0x00000800U
+#endif /* STM32F446xx */
+/*-----------------------------------------------------------------------------*/
+
+/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define RCC_PERIPHCLK_I2S 0x00000001U
+#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
+#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
+#define RCC_PERIPHCLK_LTDC 0x00000008U
+#define RCC_PERIPHCLK_TIM 0x00000010U
+#define RCC_PERIPHCLK_RTC 0x00000020U
+#define RCC_PERIPHCLK_PLLI2S 0x00000040U
+#define RCC_PERIPHCLK_CLK48 0x00000080U
+#define RCC_PERIPHCLK_SDIO 0x00000100U
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#define RCC_PERIPHCLK_I2S 0x00000001U
+#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
+#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
+#define RCC_PERIPHCLK_LTDC 0x00000008U
+#define RCC_PERIPHCLK_TIM 0x00000010U
+#define RCC_PERIPHCLK_RTC 0x00000020U
+#define RCC_PERIPHCLK_PLLI2S 0x00000040U
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define RCC_PERIPHCLK_I2S 0x00000001U
+#define RCC_PERIPHCLK_RTC 0x00000002U
+#define RCC_PERIPHCLK_PLLI2S 0x00000004U
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define RCC_PERIPHCLK_TIM 0x00000008U
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+/*----------------------------------------------------------------------------*/
+/**
+ * @}
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
+ defined(STM32F479xx)
+/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
+#define RCC_I2SCLKSOURCE_EXT 0x00000001U
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
+
+/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+#define RCC_PLLSAIDIVR_2 0x00000000U
+#define RCC_PLLSAIDIVR_4 0x00010000U
+#define RCC_PLLSAIDIVR_8 0x00020000U
+#define RCC_PLLSAIDIVR_16 0x00030000U
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
+ * @{
+ */
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx)
+#define RCC_PLLI2SP_DIV2 0x00000002U
+#define RCC_PLLI2SP_DIV4 0x00000004U
+#define RCC_PLLI2SP_DIV6 0x00000006U
+#define RCC_PLLI2SP_DIV8 0x00000008U
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
+ * @{
+ */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define RCC_PLLSAIP_DIV2 0x00000002U
+#define RCC_PLLSAIP_DIV4 0x00000004U
+#define RCC_PLLSAIP_DIV6 0x00000006U
+#define RCC_PLLSAIP_DIV8 0x00000008U
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
+ * @{
+ */
+#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
+#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
+#define RCC_SAIACLKSOURCE_EXT 0x00200000U
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
+ * @{
+ */
+#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
+#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
+#define RCC_SAIBCLKSOURCE_EXT 0x00800000U
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
+ * @{
+ */
+#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
+#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
+ * @{
+ */
+#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
+#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
+ * @{
+ */
+#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
+#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
+/**
+ * @}
+ */
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
+ * @{
+ */
+#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
+#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
+#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
+#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
+ * @{
+ */
+#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
+#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
+#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
+#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
+ * @{
+ */
+#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
+#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
+ * @{
+ */
+#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
+#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
+#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
+#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
+ * @{
+ */
+#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
+ * @{
+ */
+#define RCC_CECCLKSOURCE_HSI 0x00000000U
+#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
+ * @{
+ */
+#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
+#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
+ * @{
+ */
+#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
+#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
+ * @{
+ */
+#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
+#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
+/**
+ * @}
+ */
+
+#endif /* STM32F446xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source
+ * @{
+ */
+#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
+#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
+#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
+#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source
+ * @{
+ */
+#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
+#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
+#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
+#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
+ * @{
+ */
+#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
+#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
+#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source
+ * @{
+ */
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source
+ * @{
+ */
+#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
+#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
+/**
+ * @}
+ */
+
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
+ * @{
+ */
+#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
+#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
+ * @{
+ */
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
+ * @{
+ */
+#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
+#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
+ * @{
+ */
+#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
+#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
+ * @{
+ */
+#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
+#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
+#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
+#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
+ * @{
+ */
+#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
+ * @{
+ */
+#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
+#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
+ * @{
+ */
+#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
+#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
+/**
+ * @}
+ */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+
+/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
+ * @{
+ */
+#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
+#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
+#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
+ * @{
+ */
+#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
+ * @{
+ */
+#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
+#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
+#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
+ * @{
+ */
+#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
+#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+ STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
+ * @{
+ */
+#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
+#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
+ STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
+ * @{
+ */
+#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
+#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+ STM32F412Rx || STM32F413xx | STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
+ * @{
+ */
+#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
+#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
+/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
+#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
+#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+
+/**
+ * @brief Enable ETHERNET clock.
+ */
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
+ } while(0U)
+/**
+ * @brief Disable ETHERNET clock.
+ */
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \
+ } while(0U)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
+ __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
+ __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
+ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
+ __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+ #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0U)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
+
+#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
+#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
+#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
+#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
+#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
+#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
+#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
+#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
+#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
+
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+/**
+ * @brief Enable ETHERNET clock.
+ */
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
+ } while(0U)
+
+/**
+ * @brief Disable ETHERNET clock.
+ */
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \
+ } while(0U)
+#endif /* STM32F407xx || STM32F417xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+/**
+ * @brief Enable ETHERNET clock.
+ */
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
+#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
+ __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
+ __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
+/**
+ * @brief Disable ETHERNET clock.
+ */
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
+#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
+ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
+ __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
+#endif /* STM32F407xx || STM32F417xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0U)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx)
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+#endif /* STM32F415xx || STM32F417xx */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
+
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
+#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
+
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
+#endif /* STM32F415xx || STM32F417xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+ /**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
+
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx)
+#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#endif /* STM32F415xx || STM32F417xx */
+
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
+
+#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx)
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#endif /* STM32F415xx || STM32F417xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------- STM32F401xE/STM32F401xC --------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0U)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+/**
+ * @}
+ */
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+/**
+ * @}
+ */
+#endif /* STM32F401xC || STM32F401xE*/
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F410xx -------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
+
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB1) peripheral clock.
+ * @{
+ */
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @{
+ */
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
+
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET()
+#define __HAL_RCC_AHB2_RELEASE_RESET()
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET()
+#define __HAL_RCC_AHB3_RELEASE_RESET()
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @{
+ */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @{
+ */
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
+/**
+ * @}
+ */
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F411xx -------------------------------*/
+#if defined(STM32F411xE)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0U)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @{
+ */
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @{
+ */
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+/**
+ * @}
+ */
+#endif /* STM32F411xE */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F446xx -----------------------------*/
+#if defined(STM32F446xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0U)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
+
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
+
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
+
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
+/**
+ * @}
+ */
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
+#endif /* STM32F423xx */
+
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\
+ }while(0U)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
+#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
+#endif /* STM32F423xx */
+
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+ * @brief Enables or disables the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+
+#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
+
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+#endif /* STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
+#endif /* STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_UART10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
+#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))
+#endif /* STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
+#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET)
+#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)
+#endif /* STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ * @brief Force or release AHB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
+ * @brief Force or release AHB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
+
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
+#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
+#endif /* STM32F423xx */
+
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
+ * @brief Force or release AHB3 peripheral reset.
+ * @{
+ */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
+
+#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Cx)
+#define __HAL_RCC_AHB3_FORCE_RESET()
+#define __HAL_RCC_AHB3_RELEASE_RESET()
+
+#define __HAL_RCC_FSMC_FORCE_RESET()
+#define __HAL_RCC_QSPI_FORCE_RESET()
+
+#define __HAL_RCC_FSMC_RELEASE_RESET()
+#define __HAL_RCC_QSPI_RELEASE_RESET()
+#endif /* STM32F412Cx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+#endif /* STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST))
+#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST))
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
+#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
+#endif /* STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
+#endif /* STM32F423xx */
+
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN))
+#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
+#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------- PLL Configuration --------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ *
+ * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
+ STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
+ (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
+ ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
+ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \
+ ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
+#else
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432
+ * Except for STM32F411xE devices where Min_Data = 192.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
+ * where frequency is between 192 and 432 MHz.
+ * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
+ (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
+ ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
+ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
+ #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------PLLI2S Configuration ---------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/** @brief Macros to enable or disable the PLLI2S.
+ * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+ STM32F412Rx || STM32F412Cx */
+#if defined(STM32F446xx)
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 1 MHz to limit PLLI2S jitter.
+ *
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+ *
+ * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock.
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note the PLLI2SP parameter is only available with STM32F446xx Devices
+ *
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ * @param __PLLI2SQ__ specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
+ (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
+ ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
+ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 1 MHz to limit PLLI2S jitter.
+ *
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+ *
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ * @param __PLLI2SQ__ specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
+ (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
+ ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#else
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+ *
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
+ (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#endif /* STM32F446xx */
+
+#if defined(STM32F411xE)
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
+ * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLLI2S jitter.
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ */
+#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
+ ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#endif /* STM32F411xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API)
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+ * @param __PLLI2SQ__ specifies the division factor for SAI1 clock.
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
+ * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ */
+#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\
+ ((__PLLI2SQ__) << 24U) |\
+ ((__PLLI2SR__) << 28U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------ PLLSAI Configuration ------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macros to Enable or Disable the PLLISAI.
+ * @note The PLLSAI is only available with STM32F429x/439x Devices.
+ * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
+#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
+
+#if defined(STM32F446xx)
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
+ *
+ * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 1 MHz to limit PLLI2S jitter.
+ * @note The PLLSAIM parameter is only used with STM32F446xx Devices
+ *
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+ *
+ * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note the PLLSAIP parameter is only available with STM32F446xx Devices
+ *
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ *
+ * @param __PLLSAIR__ specifies the division factor for LTDC clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
+ */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
+ (RCC->PLLSAICFGR = ((__PLLSAIM__) | \
+ ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \
+ ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
+ *
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+ *
+ * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ *
+ * @param __PLLSAIR__ specifies the division factor for LTDC clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
+ (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\
+ ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\
+ ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
+ *
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+ *
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ *
+ * @param __PLLSAIR__ specifies the division factor for LTDC clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
+ */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
+ (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \
+ ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
+ * @note This function must be called before enabling the PLLI2S.
+ * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__
+ */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
+
+/** @brief Macro to configure the SAI clock Divider coming from PLL.
+ * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock.
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLR) / __PLLDivR__
+ */
+#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
+ * @note This function must be called before enabling the PLLI2S.
+ * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
+ */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
+
+/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
+ * @note This function must be called before enabling the PLLSAI.
+ * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
+ * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
+ * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
+ */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
+ *
+ * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
+ * @note This function must be called before enabling the PLLSAI.
+ * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
+ * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
+ */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------- Peripheral Clock selection -----------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
+ defined(STM32F479xx)
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __SOURCE__ specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source.
+ */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
+
+
+/** @brief Macro to get the I2S clock source (I2SCLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+ * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ */
+#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/** @brief Macro to configure SAI1BlockA clock source selection.
+ * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__ specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block A clock.
+ */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+
+/** @brief Macro to configure SAI1BlockB clock source selection.
+ * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__ specifies the SAI Block B clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block B clock.
+ * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block B clock.
+ * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block B clock.
+ */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+/** @brief Macro to configure SAI1 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__ specifies the SAI1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ */
+#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
+
+/** @brief Macro to Get SAI1 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
+ * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+ */
+#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
+
+/** @brief Macro to configure SAI2 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__ specifies the SAI2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+ */
+#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
+
+/** @brief Macro to Get SAI2 clock source selection.
+ * @note This configuration is only available with STM32F446xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+ */
+#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
+
+/** @brief Macro to configure I2S APB1 clock source selection.
+ * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
+ * @param __SOURCE__ specifies the I2S APB1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S APB1 clock source selection.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
+
+/** @brief Macro to configure I2S APB2 clock source selection.
+ * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
+ * @param __SOURCE__ specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S APB2 clock source selection.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
+
+/** @brief Macro to configure the CEC clock.
+ * @param __SOURCE__ specifies the CEC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+ */
+#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the CEC clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+ */
+#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
+
+/** @brief Macro to configure the FMPI2C1 clock.
+ * @param __SOURCE__ specifies the FMPI2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the FMPI2C1 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief Macro to configure the CLK48 clock.
+ * @param __SOURCE__ specifies the CLK48 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
+ * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
+ */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the CLK48 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
+ * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
+ */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
+
+/** @brief Macro to configure the SDIO clock.
+ * @param __SOURCE__ specifies the SDIO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the SDIO clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
+
+/** @brief Macro to configure the SPDIFRX clock.
+ * @param __SOURCE__ specifies the SPDIFRX clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
+ */
+#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the SPDIFRX clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
+ * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
+ */
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+
+/** @brief Macro to configure the CLK48 clock.
+ * @param __SOURCE__ specifies the CLK48 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
+ * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
+ */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the CLK48 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
+ * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
+ */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
+
+/** @brief Macro to configure the SDIO clock.
+ * @param __SOURCE__ specifies the SDIO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the SDIO clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
+
+/** @brief Macro to configure the DSI clock.
+ * @param __SOURCE__ specifies the DSI clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
+ * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
+ */
+#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the DSI clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
+ * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
+ */
+#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
+
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+ /** @brief Macro to configure the DFSDM1 clock.
+ * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
+ * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
+ * @retval None
+ */
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
+
+/** @brief Macro to get the DFSDM1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
+ * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
+ */
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
+
+/** @brief Macro to configure DFSDM1 Audio clock source selection.
+ * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
+ STM32F413xx/STM32F423xx Devices.
+ * @param __SOURCE__ specifies the DFSDM1 Audio clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+ */
+#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
+
+/** @brief Macro to Get DFSDM1 Audio clock source selection.
+ * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
+ STM32F413xx/STM32F423xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+ */
+#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ /** @brief Macro to configure the DFSDM2 clock.
+ * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
+ * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
+ * @retval None
+ */
+#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
+
+/** @brief Macro to get the DFSDM2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
+ * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
+ */
+#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
+
+/** @brief Macro to configure DFSDM1 Audio clock source selection.
+ * @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
+ * @param __SOURCE__ specifies the DFSDM2 Audio clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+ * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+ */
+#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
+
+/** @brief Macro to Get DFSDM2 Audio clock source selection.
+ * @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+ * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+ */
+#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
+
+/** @brief Macro to configure SAI1BlockA clock source selection.
+ * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__ specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+
+/** @brief Macro to Get SAI1 BlockA clock source selection.
+ * @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
+
+/** @brief Macro to configure SAI1 BlockB clock source selection.
+ * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__ specifies the SAI Block B clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+ * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
+ * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+ * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+
+/** @brief Macro to Get SAI1 BlockB clock source selection.
+ * @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+ * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
+ * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+ * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
+
+/** @brief Macro to configure the LPTIM1 clock.
+ * @param __SOURCE__ specifies the LPTIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+ */
+#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the LPTIM1 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+ */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
+#endif /* STM32F413xx || STM32F423xx */
+
+/** @brief Macro to configure I2S APB1 clock source selection.
+ * @param __SOURCE__ specifies the I2S APB1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+ * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S APB1 clock source selection.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+ * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+ * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
+
+/** @brief Macro to configure I2S APB2 clock source selection.
+ * @param __SOURCE__ specifies the I2S APB2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+ * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S APB2 clock source selection.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+ * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+ * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ */
+#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
+
+/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
+ * @note This macro must be called before enabling the I2S APB clock.
+ * @param __SOURCE__ specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+ * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source.
+ */
+#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
+
+/** @brief Macro to configure the FMPI2C1 clock.
+ * @param __SOURCE__ specifies the FMPI2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the FMPI2C1 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief Macro to configure the CLK48 clock.
+ * @param __SOURCE__ specifies the CLK48 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
+ * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
+ */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the CLK48 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
+ * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
+ */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
+
+/** @brief Macro to configure the SDIO clock.
+ * @param __SOURCE__ specifies the SDIO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the SDIO clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
+ * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
+ */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
+
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @brief Macro to configure I2S clock source selection.
+ * @param __SOURCE__ specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+ * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+ */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
+
+/** @brief Macro to Get I2S clock source selection.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+ * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+ */
+#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
+
+/** @brief Macro to configure the FMPI2C1 clock.
+ * @param __SOURCE__ specifies the FMPI2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the FMPI2C1 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+ * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+ */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief Macro to configure the LPTIM1 clock.
+ * @param __SOURCE__ specifies the LPTIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+ */
+#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief Macro to Get the LPTIM1 clock.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+ */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+ defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief Macro to configure the Timers clocks prescalers
+ * @note This feature is only available with STM32F429x/439x Devices.
+ * @param __PRESC__ specifies the Timers clocks prescalers selection
+ * This parameter can be one of the following values:
+ * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1 or 2,
+ * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
+ * division by 4 or more.
+ * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
+ * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
+ * to division by 8 or more.
+ */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
+ STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\
+ STM32F423xx */
+
+/*----------------------------------------------------------------------------*/
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Enable PLLSAI_RDY interrupt.
+ */
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Disable PLLSAI_RDY interrupt.
+ */
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Clear the PLLSAI RDY interrupt pending bits.
+ */
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
+
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.
+ * @retval The new state (TRUE or FALSE).
+ */
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Check PLLSAI RDY flag is set or not.
+ * @retval The new state (TRUE or FALSE).
+ */
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @brief Macros to enable or disable the RCC MCO1 feature.
+ */
+#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
+#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the RCC MCO2 feature.
+ */
+#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
+#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#if defined(RCC_PLLI2S_SUPPORT)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
+#endif /* RCC_PLLSAI_SUPPORT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+/* --- CR Register ---*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of PLLSAION bit */
+#define RCC_PLLSAION_BIT_NUMBER 0x1CU
+#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
+
+#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Alias word address of PLLI2SON bit */
+#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
+#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/* --- DCKCFGR Register ---*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
+ defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Alias word address of TIMPRE bit */
+#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU)
+#define RCC_TIMPRE_BIT_NUMBER 0x18U
+#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\
+ STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/* --- CFGR Register ---*/
+#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of I2SSRC bit */
+#define RCC_I2SSRC_BIT_NUMBER 0x17U
+#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
+
+#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+/* --- PLLI2SCFGR Register ---*/
+#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
+/* Alias word address of PLLI2SSRC bit */
+#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U
+#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
+
+#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/* Alias word address of MCO1EN bit */
+#define RCC_MCO1EN_BIT_NUMBER 0x8U
+#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
+
+/* Alias word address of MCO2EN bit */
+#define RCC_MCO2EN_BIT_NUMBER 0x9U
+#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#define PLL_TIMEOUT_VALUE 2U /* 2 ms */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+ * @{
+ */
+#if defined(STM32F411xE)
+#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
+#else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
+ STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx ||
+ STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx ||
+ STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
+#endif /* STM32F411xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
+#endif /* STM32F413xx || STM32F423xx */
+
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
+
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_4) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_8) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_16))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
+
+#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+ ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+ ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
+ ((VALUE) == RCC_PLLI2SP_DIV4) ||\
+ ((VALUE) == RCC_PLLI2SP_DIV6) ||\
+ ((VALUE) == RCC_PLLI2SP_DIV8))
+
+#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
+
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV8))
+
+#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
+
+#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
+
+ #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+
+#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+ ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+ ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+ ((VALUE) == RCC_PLLSAIP_DIV8))
+
+#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+ ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+ ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
+
+#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+ ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \
+ ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
+
+#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
+
+ #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+ ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+ ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+ ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \
+ ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \
+ ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
+
+#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\
+ ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
+
+#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\
+ ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\
+ ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\
+ ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
+
+#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#endif /* STM32F413xx || STM32F423xx */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
+ STM32F412Rx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rng.c
+ * @author MCD Application Team
+ * @brief RNG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Random Number Generator (RNG) peripheral:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The RNG HAL driver can be used as follows:
+
+ (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
+ in HAL_RNG_MspInit().
+ (#) Activate the RNG peripheral using HAL_RNG_Init() function.
+ (#) Wait until the 32 bit Random Number Generator contains a valid
+ random data using (polling/interrupt) mode.
+ (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RNG
+ * @{
+ */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RNG_Private_Constants
+ * @{
+ */
+#define RNG_TIMEOUT_VALUE 2U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RNG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RNG_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the RNG according to the specified parameters
+ in the RNG_InitTypeDef and create the associated handle
+ (+) DeInitialize the RNG peripheral
+ (+) Initialize the RNG MSP
+ (+) DeInitialize RNG MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RNG peripheral and creates the associated handle.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
+{
+ /* Check the RNG handle allocation */
+ if(hrng == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hrng->State == HAL_RNG_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrng->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_RNG_MspInit(hrng);
+ }
+
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Enable the RNG Peripheral */
+ __HAL_RNG_ENABLE(hrng);
+
+ /* Initialize the RNG state */
+ hrng->State = HAL_RNG_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the RNG peripheral.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
+{
+ /* Check the RNG handle allocation */
+ if(hrng == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Disable the RNG Peripheral */
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
+
+ /* Clear RNG interrupt status flags */
+ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
+
+ /* DeInit the low level hardware */
+ HAL_RNG_MspDeInit(hrng);
+
+ /* Update the RNG state */
+ hrng->State = HAL_RNG_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+
+ /* Return the function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RNG MSP.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval None
+ */
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitializes the RNG MSP.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval None
+ */
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_MspDeInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RNG_Exported_Functions_Group2
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Get the 32 bit Random number
+ (+) Get the 32 bit Random number with interrupt enabled
+ (+) Handle RNG interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Generates a 32-bit random number.
+ * @note Each time the random number data is read the RNG_FLAG_DRDY flag
+ * is automatically cleared.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @param random32bit pointer to generated random number variable if successful.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
+{
+ uint32_t tickstart = 0U;
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hrng);
+
+ /* Check RNG peripheral state */
+ if(hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if data register contains valid random data */
+ while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ {
+ hrng->State = HAL_RNG_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get a 32bit Random number */
+ hrng->RandomNumber = hrng->Instance->DR;
+ *random32bit = hrng->RandomNumber;
+
+ hrng->State = HAL_RNG_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ return status;
+}
+
+/**
+ * @brief Generates a 32-bit random number in interrupt mode.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hrng);
+
+ /* Check RNG peripheral state */
+ if(hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+ __HAL_RNG_ENABLE_IT(hrng);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Handles RNG interrupt request.
+ * @note In the case of a clock error, the RNG is no more able to generate
+ * random numbers because the PLL48CLK clock is not correct. User has
+ * to check that the clock controller is correctly configured to provide
+ * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
+ * The clock error has no impact on the previously generated
+ * random numbers, and the RNG_DR register contents can be used.
+ * @note In the case of a seed error, the generation of random numbers is
+ * interrupted as long as the SECS bit is '1'. If a number is
+ * available in the RNG_DR register, it must not be used because it may
+ * not have enough entropy. In this case, it is recommended to clear the
+ * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
+ * the RNG peripheral to reinitialize and restart the RNG.
+ * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+ * or CEIS are set.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval None
+
+ */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+ /* RNG clock error interrupt occurred */
+ if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_ERROR;
+
+ HAL_RNG_ErrorCallback(hrng);
+
+ /* Clear the clock error flag */
+ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
+
+ }
+
+ /* Check RNG data ready interrupt occurred */
+ if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+ {
+ /* Generate random number once, so disable the IT */
+ __HAL_RNG_DISABLE_IT(hrng);
+
+ /* Get the 32bit Random number (DRDY flag automatically cleared) */
+ hrng->RandomNumber = hrng->Instance->DR;
+
+ if(hrng->State != HAL_RNG_STATE_ERROR)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_READY;
+
+ /* Data Ready callback */
+ HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+ }
+ }
+}
+
+/**
+ * @brief Returns generated random number in polling mode (Obsolete)
+ * Use HAL_RNG_GenerateRandomNumber() API instead.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval Random value
+ */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+{
+ if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
+ {
+ return hrng->RandomNumber;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+/**
+ * @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
+ * Use HAL_RNG_GenerateRandomNumber_IT() API instead.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval 32-bit random number
+ */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+ uint32_t random32bit = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Get a 32bit Random number */
+ random32bit = hrng->Instance->DR;
+
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+ __HAL_RNG_ENABLE_IT(hrng);
+
+ /* Return the 32 bit random number */
+ return random32bit;
+}
+
+/**
+ * @brief Read latest generated random number.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval random value
+ */
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+{
+ return(hrng->RandomNumber);
+}
+
+/**
+ * @brief Data Ready callback in non-blocking mode.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @param random32bit generated random number.
+ * @retval None
+ */
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+ UNUSED(random32bit);
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_ReadyDataCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief RNG error callbacks.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval None
+ */
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_RNG_ErrorCallback must be implemented in the user file.
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @addtogroup RNG_Exported_Functions_Group3
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the RNG state.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval HAL state
+ */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+{
+ return hrng->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,367 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rng.h
+ * @author MCD Application Team
+ * @brief Header file of RNG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RNG_H
+#define __STM32F4xx_HAL_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
+ defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+ defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RNG RNG
+ * @brief RNG HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Types RNG Exported Types
+ * @{
+ */
+
+/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
+ * @{
+ */
+typedef enum
+{
+ HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
+ HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
+ HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
+ HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
+ HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
+
+}HAL_RNG_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
+ * @{
+ */
+typedef struct
+{
+ RNG_TypeDef *Instance; /*!< Register base address */
+
+ HAL_LockTypeDef Lock; /*!< RNG locking object */
+
+ __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
+
+ uint32_t RandomNumber; /*!< Last Generated RNG Data */
+
+}RNG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Constants RNG Exported Constants
+ * @{
+ */
+
+/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
+ * @{
+ */
+#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
+#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
+#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
+ * @{
+ */
+#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
+#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
+#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Macros RNG Exported Macros
+ * @{
+ */
+
+/** @brief Reset RNG handle state
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+
+/**
+ * @brief Enables the RNG peripheral.
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
+
+/**
+ * @brief Disables the RNG peripheral.
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
+
+/**
+ * @brief Check the selected RNG flag status.
+ * @param __HANDLE__ RNG Handle
+ * @param __FLAG__ RNG flag
+ * This parameter can be one of the following values:
+ * @arg RNG_FLAG_DRDY: Data ready
+ * @arg RNG_FLAG_CECS: Clock error current status
+ * @arg RNG_FLAG_SECS: Seed error current status
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the selected RNG flag status.
+ * @param __HANDLE__ RNG handle
+ * @param __FLAG__ RNG flag to clear
+ * @note WARNING: This is a dummy macro for HAL code alignment,
+ * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
+ * @retval None
+ */
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
+
+
+
+/**
+ * @brief Enables the RNG interrupts.
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
+
+/**
+ * @brief Disables the RNG interrupts.
+ * @param __HANDLE__ RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
+
+/**
+ * @brief Checks whether the specified RNG interrupt has occurred or not.
+ * @param __HANDLE__ RNG Handle
+ * @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
+ * This parameter can be one of the following values:
+ * @arg RNG_IT_DRDY: Data ready interrupt
+ * @arg RNG_IT_CEI: Clock error interrupt
+ * @arg RNG_IT_SEI: Seed error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Clear the RNG interrupt status flags.
+ * @param __HANDLE__ RNG Handle
+ * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg RNG_IT_CEI: Clock error interrupt
+ * @arg RNG_IT_SEI: Seed error interrupt
+ * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
+ * @retval None
+ */
+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Functions RNG Exported Functions
+ * @{
+ */
+
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup RNG_Private_Types RNG Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RNG_Private_Defines RNG Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Variables RNG Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Constants RNG Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNG_Private_Macros RNG Private Macros
+ * @{
+ */
+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
+ ((IT) == RNG_IT_SEI))
+
+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Functions RNG Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_RNG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1557 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rtc.c
+ * @author MCD Application Team
+ * @brief RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real Time Clock (RTC) peripheral:
+ * + Initialization and de-initialization functions
+ * + RTC Time and Date functions
+ * + RTC Alarm functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Backup Domain Operating Condition #####
+ ==============================================================================
+ [..] The real-time clock (RTC), the RTC backup registers, and the backup
+ SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
+ VDD supply is powered off.
+ To retain the content of the RTC backup registers, backup SRAM, and supply
+ the RTC when VDD is turned off, VBAT pin can be connected to an optional
+ standby voltage supplied by a battery or by another source.
+
+ [..] To allow the RTC operating even when the main digital supply (VDD) is turned
+ off, the VBAT pin powers the following blocks:
+ (#) The RTC
+ (#) The LSE oscillator
+ (#) The backup SRAM when the low power backup regulator is enabled
+ (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
+
+ [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
+ the following pins are available:
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins
+ (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
+ (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
+
+ [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
+ because VDD is not present), the following pins are available:
+ (#) PC14 and PC15 can be used as LSE pins only
+ (#) PC13 can be used as the RTC_AF1 pin
+ (#) PI8 can be used as the RTC_AF2 pin
+
+ ##### Backup Domain Reset #####
+ ==================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
+ to their reset values. The BKPSRAM is not affected by this reset. The only
+ way to reset the BKPSRAM is through the Flash interface by requesting
+ a protection level change from 1 to 0.
+ [..] A backup domain reset is generated when one of the following events occurs:
+ (#) Software reset, triggered by setting the BDRST bit in the
+ RCC Backup domain control register (RCC_BDCR).
+ (#) VDD or VBAT power on, if both supplies have previously been powered off.
+
+ ##### Backup Domain Access #####
+ ==================================================================
+ [..] After reset, the backup domain (RTC registers, RTC backup data
+ registers and backup SRAM) is protected against possible unwanted write
+ accesses.
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() function.
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
+ (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
+
+
+ ##### How to use this driver #####
+ ==================================================================
+ [..]
+ (+) Enable the RTC domain access (see description in the section above).
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ and HAL_RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
+ *** Alarm configuration ***
+ ===========================
+ [..]
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+
+ ##### RTC and low power modes #####
+ ==================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
+ RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
+ These RTC alternate functions can wake up the system from the Stop and
+ Standby low power modes.
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wake-up mode), by using the RTC alarm
+ or the RTC wake-up events.
+ [..] The RTC provides a programmable time base for waking up from the
+ Stop or Standby mode at regular intervals.
+ Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
+ is LSE or LSI.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTC RTC
+ * @brief RTC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize power consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WPR.
+ (#) To configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wake-up from low power modes
+ the software must first clear the RSF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
+ implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RTC peripheral
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+ /* Check the RTC peripheral state */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
+ assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+ assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
+ assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));
+ assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+ assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+
+ if(hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+ /* Initialize RTC MSP */
+ HAL_RTC_MspInit(hrtc);
+ }
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
+ hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief DeInitializes the RTC peripheral
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note This function doesn't reset the RTC Backup Data registers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Reset TR, DR and CR registers */
+ hrtc->Instance->TR = 0x00000000U;
+ hrtc->Instance->DR = 0x00002101U;
+ /* Reset All CR bits except CR[2:0] */
+ hrtc->Instance->CR &= 0x00000007U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till WUTWF flag is set and if Time out is reached exit */
+ while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset all RTC CR register bits */
+ hrtc->Instance->CR &= 0x00000000U;
+ hrtc->Instance->WUTR = 0x0000FFFFU;
+ hrtc->Instance->PRER = 0x007F00FFU;
+ hrtc->Instance->CALIBR = 0x00000000U;
+ hrtc->Instance->ALRMAR = 0x00000000U;
+ hrtc->Instance->ALRMBR = 0x00000000U;
+ hrtc->Instance->SHIFTR = 0x00000000U;
+ hrtc->Instance->CALR = 0x00000000U;
+ hrtc->Instance->ALRMASSR = 0x00000000U;
+ hrtc->Instance->ALRMBSSR = 0x00000000U;
+
+ /* Reset ISR register and exit initialization mode */
+ hrtc->Instance->ISR = 0x00000000U;
+
+ /* Reset Tamper and alternate functions configuration register */
+ hrtc->Instance->TAFCR = 0x00000000U;
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* De-Initialize RTC MSP */
+ HAL_RTC_MspDeInit(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RTC MSP.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the RTC MSP.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+ * @brief RTC Time and Date functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Time and Date functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Time and Date features
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets RTC current time.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sTime->Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sTime->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sTime->Minutes));
+ assert_param(IS_RTC_SECONDS(sTime->Seconds));
+
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
+ (((uint32_t)sTime->TimeFormat) << 16U));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sTime->Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+ tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
+ ((uint32_t)(sTime->Minutes) << 8U) | \
+ ((uint32_t)sTime->Seconds) | \
+ ((uint32_t)(sTime->TimeFormat) << 16U));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set the RTC_TR register */
+ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+ /* Clear the bits to be configured */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Gets RTC current time.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+ * value in second fraction ratio with time unit following generic formula:
+ * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until current date is read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get subseconds structure field from the corresponding register */
+ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+
+ /* Get SecondFraction structure field from the corresponding register field*/
+ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
+
+ /* Get the TR register */
+ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
+ sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
+
+ /* Check the input parameters format */
+ if(Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the time structure parameters to Binary format */
+ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
+ sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
+ sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets RTC current date.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sDate Pointer to date structure
+ * @param Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
+ {
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
+ }
+
+ assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(sDate->Year));
+ assert_param(IS_RTC_MONTH(sDate->Month));
+ assert_param(IS_RTC_DATE(sDate->Date));
+
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+ ((uint32_t)sDate->WeekDay << 13U));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+ assert_param(IS_RTC_MONTH(datetmpreg));
+ assert_param(IS_RTC_DATE(datetmpreg));
+
+ datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
+ (((uint32_t)sDate->Month) << 8U) | \
+ ((uint32_t)sDate->Date) | \
+ (((uint32_t)sDate->WeekDay) << 13U));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set the RTC_DR register */
+ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY ;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Gets RTC current date.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sDate Pointer to Date structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the DR register */
+ datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
+ sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
+
+ /* Check the input parameters format */
+ if(Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the date structure parameters to Binary format */
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+ sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+ * @brief RTC Alarm functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Sets the specified RTC Alarm.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ }
+ else
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ }
+
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+
+ /* Configure the Alarm A or Alarm B Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if(sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ }
+ else
+ {
+ /* Disable the Alarm B interrupt */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+ /* Configure the Alarm B Sub Second register */
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMB_ENABLE(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the specified RTC Alarm with Interrupt
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
+ __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U) ;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ }
+ else
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ }
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ /* Configure the Alarm A or Alarm B Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if(sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ do
+ {
+ if (count-- == 0U)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET);
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
+ }
+ else
+ {
+ /* Disable the Alarm B interrupt */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* Clear flag alarm B */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+ do
+ {
+ if (count-- == 0U)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET);
+
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+ /* Configure the Alarm B Sub Second register */
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMB_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
+ }
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+
+ EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate the specified RTC Alarm
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ if(Alarm == RTC_ALARM_A)
+ {
+ /* AlarmA */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* AlarmB */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the RTC Alarm value and masks.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm Pointer to Date structure
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ if(Alarm == RTC_ALARM_A)
+ {
+ /* AlarmA */
+ sAlarm->Alarm = RTC_ALARM_A;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
+ }
+ else
+ {
+ sAlarm->Alarm = RTC_ALARM_B;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
+ }
+
+ /* Fill the structure with the read parameters */
+ sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
+ sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
+ sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+ sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+ sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
+ sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+ sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Alarm interrupt request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
+{
+ if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
+ {
+ /* Get the status of the Interrupt */
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
+ {
+ /* AlarmA callback */
+ HAL_RTC_AlarmAEventCallback(hrtc);
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
+ }
+ }
+
+ if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
+ {
+ /* Get the status of the Interrupt */
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
+ {
+ /* AlarmB callback */
+ HAL_RTCEx_AlarmBEventCallback(hrtc);
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
+ }
+ }
+
+ /* Clear the EXTI's line Flag for RTC Alarm */
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Alarm A callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles AlarmA Polling request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wake-up from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Clear RSF flag */
+ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the registers to be synchronised */
+ while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get RTC state
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Returns the RTC state.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL state
+ */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
+{
+ return hrtc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check if the Initialization mode is set */
+ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Converts a 2 digit decimal to BCD format.
+ * @param Value Byte to be converted
+ * @retval Converted byte
+ */
+uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint32_t bcdhigh = 0U;
+
+ while(Value >= 10U)
+ {
+ bcdhigh++;
+ Value -= 10U;
+ }
+
+ return ((uint8_t)(bcdhigh << 4U) | Value);
+}
+
+/**
+ * @brief Converts from 2 digit BCD to Binary.
+ * @param Value BCD value to be converted
+ * @retval Converted word
+ */
+uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint32_t tmp = 0U;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,831 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rtc.h
+ * @author MCD Application Team
+ * @brief Header file of RTC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RTC_H
+#define __STM32F4xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
+}HAL_RTCStateTypeDef;
+
+/**
+ * @brief RTC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
+ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
+ This parameter can be a value of @ref RTC_Output_selection_Definitions */
+
+ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
+ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity */
+
+ uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
+ corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity.
+ This field will be used only by HAL_RTC_GetTime function */
+
+ uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation.
+ This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+
+ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
+ in CR register to store the operation.
+ This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+
+}RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
+ This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint32_t Alarm; /*!< Specifies the alarm .
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
+}RTC_AlarmTypeDef;
+
+/**
+ * @brief RTC Handle Structure definition
+ */
+typedef struct
+{
+ RTC_TypeDef *Instance; /*!< Register base address */
+
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+}RTC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
+ * @{
+ */
+#define RTC_HOURFORMAT_24 0x00000000U
+#define RTC_HOURFORMAT_12 0x00000040U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DISABLE 0x00000000U
+#define RTC_OUTPUT_ALARMA 0x00200000U
+#define RTC_OUTPUT_ALARMB 0x00400000U
+#define RTC_OUTPUT_WAKEUP 0x00600000U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
+ * @{
+ */
+#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
+#define RTC_OUTPUT_POLARITY_LOW 0x00100000U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
+ * @{
+ */
+#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
+#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
+ * @{
+ */
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
+ * @{
+ */
+#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U
+#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U
+#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
+ * @{
+ */
+#define RTC_STOREOPERATION_RESET 0x00000000U
+#define RTC_STOREOPERATION_SET 0x00040000U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
+ * @{
+ */
+#define RTC_FORMAT_BIN 0x00000000U
+#define RTC_FORMAT_BCD 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+ * @{
+ */
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
+ * @{
+ */
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
+ * @{
+ */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE 0x00000000U
+#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL 0x80808080U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
+ * @{
+ */
+#define RTC_ALARM_A RTC_CR_ALRAE
+#define RTC_ALARM_B RTC_CR_ALRBE
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
+ * @{
+ */
+#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
+ for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm
+ comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm
+ comparison. Only SS[1:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm
+ comparison. Only SS[2:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm
+ comparison. Only SS[3:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm
+ comparison. Only SS[4:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm
+ comparison. Only SS[5:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm
+ comparison. Only SS[6:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm
+ comparison. Only SS[7:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm
+ comparison. Only SS[8:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm
+ comparison. Only SS[9:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm
+ comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm
+ comparison.Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm
+ comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm
+ comparison.Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match
+ to activate alarm. */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
+ * @{
+ */
+#define RTC_IT_TS 0x00008000U
+#define RTC_IT_WUT 0x00004000U
+#define RTC_IT_ALRB 0x00002000U
+#define RTC_IT_ALRA 0x00001000U
+#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1 0x00020000U
+#define RTC_IT_TAMP2 0x00040000U
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
+ * @{
+ */
+#define RTC_FLAG_RECALPF 0x00010000U
+#define RTC_FLAG_TAMP2F 0x00004000U
+#define RTC_FLAG_TAMP1F 0x00002000U
+#define RTC_FLAG_TSOVF 0x00001000U
+#define RTC_FLAG_TSF 0x00000800U
+#define RTC_FLAG_WUTF 0x00000400U
+#define RTC_FLAG_ALRBF 0x00000200U
+#define RTC_FLAG_ALRAF 0x00000100U
+#define RTC_FLAG_INITF 0x00000040U
+#define RTC_FLAG_RSF 0x00000020U
+#define RTC_FLAG_INITS 0x00000010U
+#define RTC_FLAG_SHPF 0x00000008U
+#define RTC_FLAG_WUTWF 0x00000004U
+#define RTC_FLAG_ALRBWF 0x00000002U
+#define RTC_FLAG_ALRAWF 0x00000001U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @brief Reset RTC handle state
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xCAU; \
+ (__HANDLE__)->Instance->WPR = 0x53U; \
+ } while(0U)
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xFFU; \
+ } while(0U)
+
+/**
+ * @brief Enable the RTC ALARMA peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
+
+/**
+ * @brief Disable the RTC ALARMA peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
+
+/**
+ * @brief Enable the RTC ALARMB peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
+
+/**
+ * @brief Disable the RTC ALARMB peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
+
+/**
+ * @brief Enable the RTC Alarm interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Alarm interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Alarm's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @arg RTC_FLAG_ALRAWF
+ * @arg RTC_FLAG_ALRBWF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Alarm's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Enable interrupt on the RTC Alarm associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Alarm associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
+ } while(0U)
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
+ __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
+ } while(0U)
+
+/**
+ * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Clear the RTC Alarm associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
+/**
+ * @}
+ */
+
+/* Include RTC HAL Extension module */
+#include "stm32f4xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group2
+ * @{
+ */
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group3
+ * @{
+ */
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group5
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK 0x007F7F7FU
+#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
+#define RTC_INIT_MASK 0xFFFFFFFFU
+#define RTC_RSF_MASK 0xFFFFFF5FU
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+
+#define RTC_TIMEOUT_VALUE 1000
+
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t Value);
+uint8_t RTC_Bcd2ToByte(uint8_t Value);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1780 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rtc_ex.c
+ * @author MCD Application Team
+ * @brief RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real Time Clock (RTC) Extension peripheral:
+ * + RTC Time Stamp functions
+ * + RTC Tamper functions
+ * + RTC Wake-up functions
+ * + Extension Control functions
+ * + Extension RTC features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable the RTC domain access.
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** RTC Wake-up configuration ***
+ ================================
+ [..]
+ (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
+ function. You can also configure the RTC Wake-up timer in interrupt mode
+ using the HAL_RTC_SetWakeUpTimer_IT() function.
+ (+) To read the RTC Wake-up Counter register, use the HAL_RTC_GetWakeUpTimer()
+ function.
+
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the
+ HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+ interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
+ function.
+ (+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
+ or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in
+ RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
+ or HAL_RTC_SetTimeStamp_IT() function.
+
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
+ or Level according to the Tamper filter (if equal to 0 Edge else Level)
+ value, sampling frequency, precharge or discharge and Pull-UP using the
+ HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt
+ mode using HAL_RTC_SetTamper_IT() function.
+ (+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
+ or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in
+ RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
+ or HAL_RTC_SetTamper_IT() function.
+
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
+ function.
+ (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
+ function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTCEx RTCEx
+ * @brief RTC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
+ * @brief RTC TimeStamp and Tamper functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC TimeStamp and Tamper functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure TimeStamp feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets TimeStamp.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_POS1: PI8/PA0 is selected as RTC TimeStamp Pin.
+ * (not applicable in the case of STM32F412xx, STM32F413xx and STM32F423xx devices)
+ * (PI8 for all STM32 devices except for STM32F446xx devices the PA0 is used)
+ * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg|= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
+ hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets TimeStamp with Interrupt.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx, STM32F412xx, STM32F413xx and STM32F423xx devices)
+ * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg |= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
+ hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin);
+
+ /* Clear RTC Timestamp flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable IT timestamp */
+ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
+
+ /* RTC timestamp Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+
+ EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates TimeStamp.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the RTC TimeStamp value.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTimeStamp Pointer to Time structure
+ * @param sTimeStampDate Pointer to Date structure
+ * @param Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * RTC_FORMAT_BIN: Binary data format
+ * RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
+{
+ uint32_t tmptime = 0U, tmpdate = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
+ sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
+ sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
+
+ /* Fill the Date structure fields with the read parameters */
+ sTimeStampDate->Year = 0U;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
+ sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
+
+ /* Check the input parameters format */
+ if(Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the TimeStamp structure parameters to Binary format */
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+ sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
+ sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
+
+ /* Convert the DateTimeStamp structure parameters to Binary format */
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+ sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
+ }
+
+ /* Clear the TIMESTAMP Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets Tamper
+ * @note By calling this API we disable the tamper interrupt for all tampers.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTamper Pointer to Tamper Structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ {
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
+ }
+
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger |\
+ (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL | (uint32_t)RTC_TAFCR_TAMPIE);
+
+ hrtc->Instance->TAFCR |= tmpreg;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets Tamper with interrupt.
+ * @note By calling this API we force the tamper interrupt for all tampers.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTamper Pointer to RTC Tamper.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Configure the tamper trigger */
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ {
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
+ }
+
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger |\
+ (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL);
+
+ hrtc->Instance->TAFCR |= tmpreg;
+
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */
+ hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
+
+ if(sTamper->Tamper == RTC_TAMPER_1)
+ {
+ /* Clear RTC Tamper 1 flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+ }
+ else
+ {
+ /* Clear RTC Tamper 2 flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+ }
+
+ /* RTC Tamper Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+
+ EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates Tamper.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Tamper Selected tamper pin.
+ * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
+{
+ assert_param(IS_RTC_TAMPER(Tamper));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the selected Tamper pin */
+ hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles TimeStamp interrupt request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
+ {
+ /* Get the status of the Interrupt */
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
+ {
+ /* TIMESTAMP callback */
+ HAL_RTCEx_TimeStampEventCallback(hrtc);
+
+ /* Clear the TIMESTAMP interrupt pending bit */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
+ }
+ }
+
+ /* Get the status of the Interrupt */
+ if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1))
+ {
+ /* Get the TAMPER Interrupt enable bit and pending bit */
+ if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET)
+ {
+ /* Tamper callback */
+ HAL_RTCEx_Tamper1EventCallback(hrtc);
+
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+ }
+ }
+
+ /* Get the status of the Interrupt */
+ if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2))
+ {
+ /* Get the TAMPER Interrupt enable bit and pending bit */
+ if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
+ {
+ /* Tamper callback */
+ HAL_RTCEx_Tamper2EventCallback(hrtc);
+
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+ }
+ }
+ /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief TimeStamp callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_TimeStampEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 1 callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_Tamper1EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 2 callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_Tamper2EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles TimeStamp polling request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+ {
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
+ {
+ /* Clear the TIMESTAMP Overrun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Change TIMESTAMP state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Tamper1 Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Tamper2 Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
+ * @brief RTC Wake-up functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Wake-up functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Wake-up feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets wake up timer.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear the Wake-up Timer clock source bits in CR register */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+ /* Configure the Wake-up Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+ /* Enable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets wake up timer with interrupt
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+ __IO uint32_t count;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Check RTC WUTWF flag is reset only when wake up timer enabled */
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ {
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET);
+ }
+
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET);
+
+ /* Configure the Wake-up Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+ /* Clear the Wake-up Timer clock source bits in CR register */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+ /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+ EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
+
+ /* Clear RTC Wake Up timer Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Configure the Interrupt in the RTC_CR register */
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
+
+ /* Enable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates wake up timer counter.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets wake up timer counter.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval Counter value
+ */
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the counter value */
+ return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+ * @brief This function handles Wake Up Timer interrupt request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
+ {
+ /* Get the status of the Interrupt */
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
+ {
+ /* WAKEUPTIMER callback */
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+
+ /* Clear the WAKEUPTIMER interrupt pending bit */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+ }
+ }
+
+ /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Wake Up Timer callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles Wake Up Timer Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the WAKEUPTIMER Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions
+ * @brief Extension Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Write a data in a specified RTC Backup data register
+ (+) Read a data in a specified RTC Backup data register
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
+ (+) Disable the RTC reference clock detection.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param BackupRegister RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
+ * specify the register.
+ * @param Data Data to be written in the specified RTC Backup data register.
+ * @retval None
+ */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+ uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp += (BackupRegister * 4U);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param BackupRegister RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
+ * specify the register.
+ * @retval Read value
+ */
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+ uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp += (BackupRegister * 4U);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @brief Sets the Coarse calibration parameters.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param CalibSign Specifies the sign of the coarse calibration value.
+ * This parameter can be one of the following values :
+ * @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive
+ * @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative
+ * @param Value value of coarse calibration expressed in ppm (coded on 5 bits).
+ *
+ * @note This Calibration value should be between 0 and 63 when using negative
+ * sign with a 2-ppm step.
+ *
+ * @note This Calibration value should be between 0 and 126 when using positive
+ * sign with a 4-ppm step.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_SIGN(CalibSign));
+ assert_param(IS_RTC_CALIB_VALUE(Value));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Enable the Coarse Calibration */
+ __HAL_RTC_COARSE_CALIB_ENABLE(hrtc);
+
+ /* Set the coarse calibration value */
+ hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates the Coarse calibration parameters.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Enable the Coarse Calibration */
+ __HAL_RTC_COARSE_CALIB_DISABLE(hrtc);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the Smooth calibration parameters.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param SmoothCalibPeriod Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values :
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
+ * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
+ * @param SmouthCalibMinusPulsesValue Select the value of CALM[80] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
+ * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
+ * SmouthCalibMinusPulsesValue must be equal to 0.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* check if a calibration is pending*/
+ if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* check if a calibration is pending*/
+ while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure the Smooth calibration settings */
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param ShiftAdd1S Select to add or not 1 second to the time calendar.
+ * This parameter can be one of the following values :
+ * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
+ * @arg RTC_SHIFTADD1S_RESET: No effect.
+ * @param ShiftSubFS Select the number of Second Fractions to substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the shift is completed*/
+ while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the reference clock detection is disabled */
+ if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
+ {
+ /* Configure the Shift settings */
+ hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param CalibOutput Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
+ * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Clear flags before config */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)CalibOutput;
+
+ __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the RTC reference clock detection.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the RTC reference clock detection.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the Bypass Shadow feature.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set the BYPSHAD bit */
+ hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the Bypass Shadow feature.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Reset the BYPSHAD bit */
+ hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+ /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) RTC Alarm B callback
+ (+) RTC Poll for Alarm B request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Alarm B callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_AlarmBEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles AlarmB Polling request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm Flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1027 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rtc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of RTC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RTC_EX_H
+#define __STM32F4xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief RTC Tamper structure definition
+ */
+typedef struct
+{
+ uint32_t Tamper; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+
+ uint32_t PinSelection; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */
+
+ uint32_t Trigger; /*!< Specifies the Tamper Trigger.
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+
+ uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
+ This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
+
+ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
+ This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
+
+ uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
+
+ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
+ This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
+}RTC_TamperTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
+ * @{
+ */
+#define RTC_BKP_DR0 0x00000000U
+#define RTC_BKP_DR1 0x00000001U
+#define RTC_BKP_DR2 0x00000002U
+#define RTC_BKP_DR3 0x00000003U
+#define RTC_BKP_DR4 0x00000004U
+#define RTC_BKP_DR5 0x00000005U
+#define RTC_BKP_DR6 0x00000006U
+#define RTC_BKP_DR7 0x00000007U
+#define RTC_BKP_DR8 0x00000008U
+#define RTC_BKP_DR9 0x00000009U
+#define RTC_BKP_DR10 0x0000000AU
+#define RTC_BKP_DR11 0x0000000BU
+#define RTC_BKP_DR12 0x0000000CU
+#define RTC_BKP_DR13 0x0000000DU
+#define RTC_BKP_DR14 0x0000000EU
+#define RTC_BKP_DR15 0x0000000FU
+#define RTC_BKP_DR16 0x00000010U
+#define RTC_BKP_DR17 0x00000011U
+#define RTC_BKP_DR18 0x00000012U
+#define RTC_BKP_DR19 0x00000013U
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
+ * @{
+ */
+#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
+#define RTC_TIMESTAMPEDGE_FALLING 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
+ * @{
+ */
+#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
+
+#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx)
+#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
+ * @{
+ */
+
+#define RTC_TAMPERPIN_DEFAULT 0x00000000U
+
+#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx)
+#define RTC_TAMPERPIN_POS1 0x00010000U
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
+
+#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx)
+#define RTC_TIMESTAMPPIN_POS1 0x00020000U
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
+ * @{
+ */
+#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
+#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U
+#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
+#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
+ * @{
+ */
+#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+
+#define RTC_TAMPERFILTER_2SAMPLE 0x00000800U /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE 0x00001000U /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE 0x00001800U /*!< Tamper is activated after 8
+ consecutive samples at the active level. */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
+ * @{
+ */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 0x00000100U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 0x00000200U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 0x00000300U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 0x00000400U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 0x00000500U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 0x00000600U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 0x00000700U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
+ * @{
+ */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK 0x00002000U /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK 0x00004000U /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK 0x00006000U /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
+ * @{
+ */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
+ * @{
+ */
+#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
+ * @{
+ */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 0x00000001U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 0x00000002U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 0x00000003U
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS 0x00000004U
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS 0x00000006U
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
+ * @{
+ */
+#define RTC_CALIBSIGN_POSITIVE 0x00000000U
+#define RTC_CALIBSIGN_NEGATIVE 0x00000080U
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibration
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC 0x00002000U /*!< If RTCCLK = 32768 Hz, Smooth calibration
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC 0x00004000U /*!< If RTCCLK = 32768 Hz, Smooth calibration
+ period is 8s, else 2exp18 RTCCLK seconds */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET 0x00008000U /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
+ * @{
+ */
+#define RTC_SHIFTADD1S_RESET 0x00000000U
+#define RTC_SHIFTADD1S_SET 0x80000000U
+/**
+ * @}
+ */
+
+
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
+ * @{
+ */
+#define RTC_CALIBOUTPUT_512HZ 0x00000000U
+#define RTC_CALIBOUTPUT_1HZ 0x00080000U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
+ * @{
+ */
+
+/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
+
+/**
+ * @brief Disable the RTC Wake-up Timer peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+
+/**
+ * @brief Enable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC WakeUpTimer Flag to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTWF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Wake Up timer's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @brief Enable interrupt on the RTC Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Wake-up Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable event on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable event on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
+ } while(0U)
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
+ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
+ } while(0U)
+
+/**
+ * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Clear the RTC Wake-up Timer associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @}
+ */
+
+/* ---------------------------------TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Timestamp RTC Timestamp
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+
+/**
+ * @brief Disable the RTC TimeStamp peripheral.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+
+/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC TimeStamp's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC TimeStamp flag to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Time Stamp's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @}
+ */
+
+/* ---------------------------------TAMPER------------------------------------*/
+/** @defgroup RTCEx_Tamper RTC Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC Tamper1 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Disable the RTC Tamper1 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
+
+#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx)
+/**
+ * @brief Enable the RTC Tamper2 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
+
+/**
+ * @brief Disable the RTC Tamper2 input detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
+#endif
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1
+ * @arg RTC_IT_TAMP2
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+/**
+ * @}
+ */
+
+/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
+ * @{
+ */
+
+/**
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
+ } while(0U)
+
+/**
+ * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+/**
+ * @}
+ */
+
+/* ------------------------------Calibration----------------------------------*/
+/** @defgroup RTCEx_Calibration RTC Calibration
+ * @{
+ */
+
+/**
+ * @brief Enable the Coarse calibration process.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
+
+/**
+ * @brief Disable the Coarse calibration process.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
+
+/**
+ * @brief Enable the RTC calibration output.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+ * @brief Disable the calibration output.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+ * @brief Enable the clock reference detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+ * @brief Disable the clock reference detection.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+ * @brief Get the selected RTC shift operation's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_SHPF
+ * @retval None
+ */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+ * @{
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @{
+ */
+/* RTC TimeStamp and Tamper functions *****************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @{
+ */
+/* RTC Wake-up functions ******************************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @{
+ */
+/* Extension Control functions ************************************************/
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+
+HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group4
+ * @{
+ */
+/* Extension RTC features functions *******************************************/
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+ * @{
+ */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
+ ((BKP) == RTC_BKP_DR1) || \
+ ((BKP) == RTC_BKP_DR2) || \
+ ((BKP) == RTC_BKP_DR3) || \
+ ((BKP) == RTC_BKP_DR4) || \
+ ((BKP) == RTC_BKP_DR5) || \
+ ((BKP) == RTC_BKP_DR6) || \
+ ((BKP) == RTC_BKP_DR7) || \
+ ((BKP) == RTC_BKP_DR8) || \
+ ((BKP) == RTC_BKP_DR9) || \
+ ((BKP) == RTC_BKP_DR10) || \
+ ((BKP) == RTC_BKP_DR11) || \
+ ((BKP) == RTC_BKP_DR12) || \
+ ((BKP) == RTC_BKP_DR13) || \
+ ((BKP) == RTC_BKP_DR14) || \
+ ((BKP) == RTC_BKP_DR15) || \
+ ((BKP) == RTC_BKP_DR16) || \
+ ((BKP) == RTC_BKP_DR17) || \
+ ((BKP) == RTC_BKP_DR18) || \
+ ((BKP) == RTC_BKP_DR19))
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E ))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
+#else
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
+#endif
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT)
+#else
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \
+ ((PIN) == RTC_TAMPERPIN_POS1))
+#endif
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT)
+#else
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \
+ ((PIN) == RTC_TIMESTAMPPIN_POS1))
+#endif
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
+ ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
+
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U)
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RTC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2181 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai.c
+ * @author MCD Application Team
+ * @brief SAI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Audio Interface (SAI) peripheral:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ The SAI HAL driver can be used as follows:
+
+ (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
+ (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
+ (##) Enable the SAI interface clock.
+ (##) SAI pins configuration:
+ (+++) Enable the clock for the SAI GPIOs.
+ (+++) Configure these SAI pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
+ and HAL_SAI_Receive_IT() APIs):
+ (+++) Configure the SAI interrupt priority.
+ (+++) Enable the NVIC SAI IRQ handle.
+
+ (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
+ and HAL_SAI_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Stream.
+
+ (#) The initialization can be done by two ways
+ (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
+ (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
+
+ [..]
+ (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
+ will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
+ inside the transmit and receive process.
+
+ [..]
+ (@) SAI Clock Source configuration is managed differently depending on the selected
+ STM32F4 devices :
+ (+@) For STM32F446xx devices, the configuration is managed through RCCEx_PeriphCLKConfig()
+ function in the HAL RCC drivers
+ (+@) For STM32F439xx/STM32F437xx/STM32F429xx/STM32F427xx devices, the configuration
+ is managed within HAL SAI drivers through HAL_SAI_Init() function using
+ ClockSource field of SAI_InitTypeDef structure.
+ [..]
+ (@) Make sure that either:
+ (+@) I2S PLL is configured or
+ (+@) SAI PLL is configured or
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
+ [..]
+ (@) In master Tx mode: enabling the audio block immediately generates the bit clock
+ for the external slaves even if there is no data in the FIFO, However FS signal
+ generation is conditioned by the presence of data in the FIFO.
+
+ [..]
+ (@) In master Rx mode: enabling the audio block immediately generates the bit clock
+ and FS signal for the external slaves.
+
+ [..]
+ (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
+ (+@) First bit Offset <= (SLOT size - Data size)
+ (+@) Data size <= SLOT size
+ (+@) Number of SLOT x SLOT size = Frame length
+ (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
+
+ [..]
+ Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
+ (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
+ (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+ (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ =============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
+ (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+ (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+ (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
+ (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
+ (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
+
+ *** SAI HAL driver additional function list ***
+ ===============================================
+ [..]
+ Below the list the others API available SAI HAL driver :
+
+ (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
+ (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
+ (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
+ (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
+ (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
+ (+) HAL_SAI_Abort(): Abort the current transfer
+
+ *** SAI HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SAI HAL driver :
+
+ (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
+ (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
+ (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
+ (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
+ (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
+ enabled or disabled
+ (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SAI SAI
+ * @brief SAI HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+
+/** @defgroup SAI_Private_Typedefs SAI Private Typedefs
+ * @{
+ */
+typedef enum {
+ SAI_MODE_DMA,
+ SAI_MODE_IT
+}SAI_ModeTypedef;
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup SAI_Private_Constants SAI Private Constants
+ * @{
+ */
+#define SAI_FIFO_SIZE 8U
+#define SAI_DEFAULT_TIMEOUT 4U /* 4ms */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup SAI_Private_Functions SAI Private Functions
+ * @{
+ */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
+
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMAError(DMA_HandleTypeDef *hdma);
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Functions SAI Exported Functions
+ * @{
+ */
+
+/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SAIx peripheral:
+
+ (+) User must implement HAL_SAI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SAI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode (Master/slave TX/RX)
+ (++) Protocol
+ (++) Data Size
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) FIFO Threshold
+ (++) Frame Config
+ (++) Slot Config
+
+ (+) Call the function HAL_SAI_DeInit() to restore the default configuration
+ of the selected SAI peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the structure FrameInit, SlotInit and the low part of
+ * Init according to the specified parameters and call the function
+ * HAL_SAI_Init to initialize the SAI block.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol one of the supported protocol @ref SAI_Protocol
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
+ * the configuration information for SAI module.
+ * @param nbslot Number of slot.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+ switch(protocol)
+ {
+ case SAI_I2S_STANDARD :
+ case SAI_I2S_MSBJUSTIFIED :
+ case SAI_I2S_LSBJUSTIFIED :
+ status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
+ break;
+ case SAI_PCM_LONG :
+ case SAI_PCM_SHORT :
+ status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
+ break;
+ default :
+ status = HAL_ERROR;
+ break;
+ }
+
+ if(status == HAL_OK)
+ {
+ status = HAL_SAI_Init(hsai);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SAI according to the specified parameters.
+ * in the SAI_InitTypeDef structure and initialize the associated handle.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
+{
+ uint32_t tmpregisterGCR = 0U;
+
+ /* This variable used to store the SAI_CK_x (value in Hz) */
+ uint32_t freq = 0U;
+
+ /* This variable is used to compute CKSTR bits of SAI CR1 according to
+ ClockStrobing and AudioMode fields */
+ uint32_t ckstr_bits = 0U;
+ uint32_t syncen_bits = 0U;
+
+ /* Check the SAI handle allocation */
+ if(hsai == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* check the instance */
+ assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
+
+ /* Check the SAI Block parameters */
+ assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
+ assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
+ assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
+ assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
+ assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
+ assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
+ assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
+ assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
+ assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
+ assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
+ assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
+ assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
+ assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
+ assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
+
+ /* Check the SAI Block Frame parameters */
+ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
+ assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
+ assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
+ assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
+ assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
+
+ /* Check the SAI Block Slot parameters */
+ assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
+ assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
+ assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
+ assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
+
+ if(hsai->State == HAL_SAI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsai->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_SAI_MspInit(hsai);
+ }
+
+ hsai->State = HAL_SAI_STATE_BUSY;
+
+ /* Disable the selected SAI peripheral */
+ SAI_Disable(hsai);
+
+ /* SAI Block Synchro Configuration -----------------------------------------*/
+ SAI_BlockSynchroConfig(hsai);
+
+ /* Configure Master Clock using the following formula :
+ MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
+ FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
+ MCKDIV[3:0] = SAI_CK_x / FS * 512 */
+ if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
+ {
+ /* Get SAI clock source based on Source clock selection from RCC */
+ freq = SAI_GetInputClock(hsai);
+
+ /* (saiclocksource x 10) to keep Significant digits */
+ tmpregisterGCR = (((freq * 10U) / ((hsai->Init.AudioFrequency) * 512U)));
+
+ hsai->Init.Mckdiv = tmpregisterGCR / 10U;
+
+ /* Round result to the nearest integer */
+ if((tmpregisterGCR % 10U) > 8U)
+ {
+ hsai->Init.Mckdiv+= 1U;
+ }
+ }
+
+ /* Compute CKSTR bits of SAI CR1 according to ClockStrobing and AudioMode */
+ if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ {
+ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U: SAI_xCR1_CKSTR;
+ }
+ else
+ {
+ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR: 0U;
+ }
+
+ /* SAI Block Configuration -------------------------------------------------*/
+ switch(hsai->Init.Synchro)
+ {
+ case SAI_ASYNCHRONOUS :
+ {
+ syncen_bits = 0U;
+ }
+ break;
+ case SAI_SYNCHRONOUS :
+ {
+ syncen_bits = SAI_xCR1_SYNCEN_0;
+ }
+ break;
+ case SAI_SYNCHRONOUS_EXT_SAI1 :
+ case SAI_SYNCHRONOUS_EXT_SAI2 :
+ {
+ syncen_bits = SAI_xCR1_SYNCEN_1;
+ }
+ break;
+ default:
+ break;
+ }
+ /* SAI CR1 Configuration */
+ hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \
+ SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
+ SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \
+ SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);
+
+ hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \
+ hsai->Init.DataSize | hsai->Init.FirstBit | \
+ ckstr_bits | syncen_bits | \
+ hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \
+ hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20U));
+
+ /* SAI CR2 Configuration */
+ hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
+ hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
+
+ /* SAI Frame Configuration -----------------------------------------*/
+ hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
+ SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
+ hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1U) |
+ hsai->FrameInit.FSOffset |
+ hsai->FrameInit.FSDefinition |
+ hsai->FrameInit.FSPolarity |
+ ((hsai->FrameInit.ActiveFrameLength - 1U) << 8U));
+
+ /* SAI Block_x SLOT Configuration ------------------------------------------*/
+ /* This register has no meaning in AC 97 and SPDIF audio protocol */
+ hsai->Instance->SLOTR &= ~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \
+ SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN );
+
+ hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \
+ (hsai->SlotInit.SlotActive << 16U) | ((hsai->SlotInit.SlotNumber - 1U) << 8U);
+
+ /* Initialize the error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+ /* Initialize the SAI state */
+ hsai->State= HAL_SAI_STATE_READY;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the SAI peripheral.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
+{
+ /* Check the SAI handle allocation */
+ if(hsai == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hsai->State = HAL_SAI_STATE_BUSY;
+
+ /* Disabled All interrupt and clear all the flag */
+ hsai->Instance->IMR = 0U;
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ /* Disable the SAI */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_SAI_MspDeInit(hsai);
+
+ /* Initialize the error code */
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+ /* Initialize the SAI state */
+ hsai->State = HAL_SAI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SAI MSP.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SAI MSP.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SAI data
+ transfers.
+
+ (+) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (+) Blocking mode functions are :
+ (++) HAL_SAI_Transmit()
+ (++) HAL_SAI_Receive()
+
+ (+) Non Blocking mode functions with Interrupt are :
+ (++) HAL_SAI_Transmit_IT()
+ (++) HAL_SAI_Receive_IT()
+
+ (+) Non Blocking mode functions with DMA are :
+ (++) HAL_SAI_Transmit_DMA()
+ (++) HAL_SAI_Receive_DMA()
+
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_SAI_TxCpltCallback()
+ (++) HAL_SAI_RxCpltCallback()
+ (++) HAL_SAI_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->pBuffPtr = pData;
+ hsai->State = HAL_SAI_STATE_BUSY_TX;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+ /* Check if the SAI is already enabled */
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ {
+ /* fill the fifo with data before to enabled the SAI */
+ SAI_FillFifo(hsai);
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ while(hsai->XferCount > 0U)
+ {
+ /* Write data if the FIFO is not full */
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
+ {
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->Instance->DR = (*hsai->pBuffPtr++);
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 2U;
+ }
+ else
+ {
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 4U;
+ }
+ hsai->XferCount--;
+ }
+ else
+ {
+ /* Check for the Timeout */
+ if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0U)||((HAL_GetTick() - tickstart) > Timeout)))
+ {
+ /* Update error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+ /* Clear all the flags */
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ /* Disable SAI peripheral */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ /* Change the SAI state */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->State = HAL_SAI_STATE_BUSY_RX;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+ /* Check if the SAI is already enabled */
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Receive data */
+ while(hsai->XferCount > 0U)
+ {
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
+ {
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;
+ hsai->pBuffPtr+= 2U;
+ }
+ else
+ {
+ *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;
+ hsai->pBuffPtr+= 4U;
+ }
+ hsai->XferCount--;
+ }
+ else
+ {
+ /* Check for the Timeout */
+ if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)))
+ {
+ /* Update error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+ /* Clear all the flags */
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ /* Disable SAI peripheral */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ /* Change the SAI state */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->State = HAL_SAI_STATE_BUSY_TX;
+
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
+ }
+ else
+ {
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
+ }
+
+ /* Fill the fifo before starting the communication */
+ SAI_FillFifo(hsai);
+
+ /* Enable FRQ and OVRUDR interrupts */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Check if the SAI is already enabled */
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
+ }
+ else
+ {
+ hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
+ }
+
+ /* Enable TXE and OVRUDR interrupts */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Check if the SAI is already enabled */
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the audio stream playing from the Media.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ /* Pause the audio file playing by disabling the SAI DMA requests */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the audio stream playing from the Media.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ /* Enable the SAI DMA requests */
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+ /* If the SAI peripheral is still not enabled, enable it */
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the audio stream playing from the Media.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ /* Disable the SAI DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Abort the SAI DMA Streams */
+ if(hsai->hdmatx != NULL)
+ {
+ if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ if(hsai->hdmarx != NULL)
+ {
+ if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Disable SAI peripheral */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the current transfer and disable the SAI.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ /* Check SAI DMA is enabled or not */
+ if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+ {
+ /* Disable the SAI DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Abort the SAI DMA Streams */
+ if(hsai->hdmatx != NULL)
+ {
+ if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ if(hsai->hdmarx != NULL)
+ {
+ if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Disabled All interrupt and clear all the flag */
+ hsai->Instance->IMR = 0U;
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ /* Disable SAI peripheral */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->State = HAL_SAI_STATE_BUSY_TX;
+
+ /* Set the SAI Tx DMA Half transfer complete callback */
+ hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
+
+ /* Set the SAI TxDMA transfer complete callback */
+ hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hsai->hdmatx->XferErrorCallback = SAI_DMAError;
+
+ /* Set the DMA Tx abort callback */
+ hsai->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream */
+ if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
+ {
+ __HAL_UNLOCK(hsai);
+ return HAL_ERROR;
+ }
+
+ /* Check if the SAI is already enabled */
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Enable the interrupts for error handling */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+ /* Enable SAI Tx DMA Request */
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsai->State == HAL_SAI_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsai);
+
+ hsai->pBuffPtr = pData;
+ hsai->XferSize = Size;
+ hsai->XferCount = Size;
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+ hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+ /* Set the SAI Rx DMA Half transfer complete callback */
+ hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
+
+ /* Set the SAI Rx DMA transfer complete callback */
+ hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hsai->hdmarx->XferErrorCallback = SAI_DMAError;
+
+ /* Set the DMA Rx abort callback */
+ hsai->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream */
+ if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
+ {
+ __HAL_UNLOCK(hsai);
+ return HAL_ERROR;
+ }
+
+ /* Check if the SAI is already enabled */
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+ {
+ /* Enable SAI peripheral */
+ __HAL_SAI_ENABLE(hsai);
+ }
+
+ /* Enable the interrupts for error handling */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+ /* Enable SAI Rx DMA Request */
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsai);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the Tx mute mode.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param val value sent during the mute @ref SAI_Block_Mute_Value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
+{
+ assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
+
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disable the Tx mute mode.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Enable the Rx mute detection.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param callback function called when the mute is detected.
+ * @param counter number a data before mute detection max 63.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
+{
+ assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
+
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ /* set the mute counter */
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
+ SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos));
+ hsai->mutecallback = callback;
+ /* enable the IT interrupt */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disable the Rx mute detection.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ /* set the mutecallback to NULL */
+ hsai->mutecallback = (SAIcallback)NULL;
+ /* enable the IT interrupt */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
+ return HAL_OK;
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Handle SAI interrupt request.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->State != HAL_SAI_STATE_RESET)
+ {
+ uint32_t itflags = hsai->Instance->SR;
+ uint32_t itsources = hsai->Instance->IMR;
+ uint32_t cr1config = hsai->Instance->CR1;
+ uint32_t tmperror;
+
+ /* SAI Fifo request interrupt occured ------------------------------------*/
+ if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
+ {
+ hsai->InterruptServiceRoutine(hsai);
+ }
+ /* SAI Overrun error interrupt occurred ----------------------------------*/
+ else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
+ {
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ /* Get the SAI error code */
+ tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
+
+ /* Change the SAI error code */
+ hsai->ErrorCode |= tmperror;
+
+ /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+ HAL_SAI_ErrorCallback(hsai);
+ }
+ /* SAI mutedet interrupt occurred ----------------------------------*/
+ else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
+ {
+ /* Clear the SAI mutedet flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
+
+ /* call the call back function */
+ if(hsai->mutecallback != (SAIcallback)NULL)
+ {
+ /* inform the user that an RX mute event has been detected */
+ hsai->mutecallback();
+ }
+ }
+ /* SAI AFSDET interrupt occurred ----------------------------------*/
+ else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
+ {
+ /* Change the SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
+
+ /* Check SAI DMA is enabled or not */
+ if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+ {
+ /* Abort the SAI DMA Streams */
+ if(hsai->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ HAL_DMA_Abort_IT(hsai->hdmatx);
+ }
+ else if(hsai->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ HAL_DMA_Abort_IT(hsai->hdmarx);
+ }
+ }
+ else
+ {
+ /* Abort SAI */
+ HAL_SAI_Abort(hsai);
+
+ /* Set error callback */
+ HAL_SAI_ErrorCallback(hsai);
+ }
+ }
+ /* SAI LFSDET interrupt occurred ----------------------------------*/
+ else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
+ {
+ /* Change the SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
+
+ /* Check SAI DMA is enabled or not */
+ if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+ {
+ /* Abort the SAI DMA Streams */
+ if(hsai->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ HAL_DMA_Abort_IT(hsai->hdmatx);
+ }
+ else if(hsai->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ HAL_DMA_Abort_IT(hsai->hdmarx);
+ }
+ }
+ else
+ {
+ /* Abort SAI */
+ HAL_SAI_Abort(hsai);
+
+ /* Set error callback */
+ HAL_SAI_ErrorCallback(hsai);
+ }
+ }
+ /* SAI WCKCFG interrupt occurred ----------------------------------*/
+ else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
+ {
+ /* Change the SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
+
+ /* Check SAI DMA is enabled or not */
+ if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+ {
+ /* Abort the SAI DMA Streams */
+ if(hsai->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ HAL_DMA_Abort_IT(hsai->hdmatx);
+ }
+ else if(hsai->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+ /* Abort DMA in IT mode */
+ HAL_DMA_Abort_IT(hsai->hdmarx);
+ }
+ }
+ else
+ {
+ /* If WCKCFG occurs, SAI audio block is automatically disabled */
+ /* Disable all interrupts and clear all flags */
+ hsai->Instance->IMR = 0U;
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ /* Set the SAI state to ready to be able to start again the process */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Initialize XferCount */
+ hsai->XferCount = 0U;
+
+ /* SAI error Callback */
+ HAL_SAI_ErrorCallback(hsai);
+ }
+ }
+ /* SAI CNRDY interrupt occurred ----------------------------------*/
+ else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
+ {
+ /* Clear the SAI CNRDY flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
+
+ /* Change the SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
+
+ /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+ HAL_SAI_ErrorCallback(hsai);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer Half completed callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer half completed callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SAI error callback.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsai);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SAI_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SAI handle state.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL state
+ */
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
+{
+ return hsai->State;
+}
+
+/**
+* @brief Return the SAI error code.
+* @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for the specified SAI Block.
+* @retval SAI Error Code
+*/
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
+{
+ return hsai->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SAI_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the SAI I2S protocol according to the specified parameters
+ * in the SAI_InitTypeDef and create the associated handle.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol one of the supported protocol.
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
+ * the configuration information for SAI module.
+ * @param nbslot number of slot minimum value is 2 and max is 16.
+ * the value must be a multiple of 2.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
+ /* Compute ClockStrobing according AudioMode */
+ if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ { /* Transmit */
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+ }
+ else
+ { /* Receive */
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;
+ }
+ hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
+ hsai->SlotInit.FirstBitOffset = 0U;
+ hsai->SlotInit.SlotNumber = nbslot;
+
+ /* in IS2 the number of slot must be even */
+ if((nbslot & 0x1U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ switch(protocol)
+ {
+ case SAI_I2S_STANDARD :
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+ break;
+ case SAI_I2S_MSBJUSTIFIED :
+ case SAI_I2S_LSBJUSTIFIED :
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+ hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ /* Frame definition */
+ switch(datasize)
+ {
+ case SAI_PROTOCOL_DATASIZE_16BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 32U*(nbslot/2U);
+ hsai->FrameInit.ActiveFrameLength = 16U*(nbslot/2U);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 64U*(nbslot/2U);
+ hsai->FrameInit.ActiveFrameLength = 32U*(nbslot/2U);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_24BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_24;
+ hsai->FrameInit.FrameLength = 64U*(nbslot/2U);
+ hsai->FrameInit.ActiveFrameLength = 32U*(nbslot/2U);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_32BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_32;
+ hsai->FrameInit.FrameLength = 64U*(nbslot/2U);
+ hsai->FrameInit.ActiveFrameLength = 32U*(nbslot/2U);
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+ if(protocol == SAI_I2S_LSBJUSTIFIED)
+ {
+ if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
+ {
+ hsai->SlotInit.FirstBitOffset = 16U;
+ }
+ if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
+ {
+ hsai->SlotInit.FirstBitOffset = 8U;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SAI PCM protocol according to the specified parameters
+ * in the SAI_InitTypeDef and create the associated handle.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param protocol one of the supported protocol
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param nbslot number of slot minimum value is 1 and the max is 16.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
+ /* Compute ClockStrobing according AudioMode */
+ if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ { /* Transmit */
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;
+ }
+ else
+ { /* Receive */
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+ }
+ hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME;
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+ hsai->SlotInit.FirstBitOffset = 0U;
+ hsai->SlotInit.SlotNumber = nbslot;
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
+
+ switch(protocol)
+ {
+ case SAI_PCM_SHORT :
+ hsai->FrameInit.ActiveFrameLength = 1U;
+ break;
+ case SAI_PCM_LONG :
+ hsai->FrameInit.ActiveFrameLength = 13U;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ switch(datasize)
+ {
+ case SAI_PROTOCOL_DATASIZE_16BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 16U * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+ hsai->Init.DataSize = SAI_DATASIZE_16;
+ hsai->FrameInit.FrameLength = 32U * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_24BIT :
+ hsai->Init.DataSize = SAI_DATASIZE_24;
+ hsai->FrameInit.FrameLength = 32U * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ case SAI_PROTOCOL_DATASIZE_32BIT:
+ hsai->Init.DataSize = SAI_DATASIZE_32;
+ hsai->FrameInit.FrameLength = 32U * nbslot;
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+ break;
+ default :
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Fill the fifo.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
+{
+ /* fill the fifo with data before to enabled the SAI */
+ while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U))
+ {
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+ {
+ hsai->Instance->DR = (*hsai->pBuffPtr++);
+ }
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
+ {
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 2U;
+ }
+ else
+ {
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+ hsai->pBuffPtr+= 4U;
+ }
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief Return the interrupt flag to set according the SAI setup.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @param mode SAI_MODE_DMA or SAI_MODE_IT
+ * @retval the list of the IT flag to enable
+ */
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
+{
+ uint32_t tmpIT = SAI_IT_OVRUDR;
+
+ if(mode == SAI_MODE_IT)
+ {
+ tmpIT|= SAI_IT_FREQ;
+ }
+
+ if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
+ ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
+ {
+ tmpIT|= SAI_IT_CNRDY;
+ }
+
+ if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+ {
+ tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
+ }
+ else
+ {
+ /* hsai has been configured in master mode */
+ tmpIT|= SAI_IT_WCKCFG;
+ }
+ return tmpIT;
+}
+
+/**
+ * @brief Disable the SAI and wait for the disabling.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
+{
+ register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock /7U/1000U);
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Disable the SAI instance */
+ __HAL_SAI_DISABLE(hsai);
+
+ do
+ {
+ /* Check for the Timeout */
+ if (count-- == 0U)
+ {
+ /* Update error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+ status = HAL_TIMEOUT;
+ break;
+ }
+ } while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET);
+
+ return status;
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->XferCount == 0U)
+ {
+ /* Handle the end of the transmission */
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_TxCpltCallback(hsai);
+ }
+ else
+ {
+ /* Write data on DR register */
+ hsai->Instance->DR = (*hsai->pBuffPtr++);
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->XferCount == 0U)
+ {
+ /* Handle the end of the transmission */
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_TxCpltCallback(hsai);
+ }
+ else
+ {
+ /* Write data on DR register */
+ hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
+ hsai->pBuffPtr+=2U;
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+ if(hsai->XferCount == 0U)
+ {
+ /* Handle the end of the transmission */
+ /* Disable FREQ and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_TxCpltCallback(hsai);
+ }
+ else
+ {
+ /* Write data on DR register */
+ hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
+ hsai->pBuffPtr+=4U;
+ hsai->XferCount--;
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if(hsai->XferCount == 0U)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_RxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
+ hsai->pBuffPtr+=2U;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if(hsai->XferCount == 0U)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_RxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval None
+ */
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+ /* Receive data */
+ *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;
+ hsai->pBuffPtr+=4U;
+ hsai->XferCount--;
+
+ /* Check end of the transfer */
+ if(hsai->XferCount == 0U)
+ {
+ /* Disable TXE and OVRUDR interrupts */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+ /* Clear the SAI Overrun flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+ hsai->State = HAL_SAI_STATE_READY;
+ HAL_SAI_RxCpltCallback(hsai);
+ }
+}
+
+/**
+ * @brief DMA SAI transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ hsai->XferCount = 0U;
+
+ /* Disable SAI Tx DMA Request */
+ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+
+ /* Stop the interrupts error handling */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+ hsai->State= HAL_SAI_STATE_READY;
+ }
+ HAL_SAI_TxCpltCallback(hsai);
+}
+
+/**
+ * @brief DMA SAI transmit process half complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_SAI_TxHalfCpltCallback(hsai);
+}
+
+/**
+ * @brief DMA SAI receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ /* Disable Rx DMA Request */
+ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+ hsai->XferCount = 0U;
+
+ /* Stop the interrupts error handling */
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+ hsai->State = HAL_SAI_STATE_READY;
+ }
+ HAL_SAI_RxCpltCallback(hsai);
+}
+
+/**
+ * @brief DMA SAI receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_SAI_RxHalfCpltCallback(hsai);
+}
+
+/**
+ * @brief DMA SAI communication error callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set SAI error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+ if((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE))
+ {
+ /* Disable the SAI DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Disable SAI peripheral */
+ SAI_Disable(hsai);
+
+ /* Set the SAI state ready to be able to start again the process */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Initialize XferCount */
+ hsai->XferCount = 0U;
+ }
+ /* SAI error Callback */
+ HAL_SAI_ErrorCallback(hsai);
+}
+
+/**
+ * @brief DMA SAI Abort callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable DMA request */
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+ /* Disable all interrupts and clear all flags */
+ hsai->Instance->IMR = 0U;
+ hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+ if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
+ {
+ /* Disable SAI peripheral */
+ SAI_Disable(hsai);
+
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+ }
+ /* Set the SAI state to ready to be able to start again the process */
+ hsai->State = HAL_SAI_STATE_READY;
+
+ /* Initialize XferCount */
+ hsai->XferCount = 0U;
+
+ /* SAI error Callback */
+ HAL_SAI_ErrorCallback(hsai);
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,864 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai.h
+ * @author MCD Application Team
+ * @brief Header file of SAI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SAI_H
+#define __STM32F4xx_HAL_SAI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \
+ defined(STM32F423xx)
+
+/** @addtogroup SAI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Types SAI Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */
+ HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */
+ HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
+ HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
+ HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
+ HAL_SAI_STATE_TIMEOUT = 0x03U, /*!< SAI timeout state */
+ HAL_SAI_STATE_ERROR = 0x04U /*!< SAI error state */
+}HAL_SAI_StateTypeDef;
+
+/**
+ * @brief SAI Callback prototype
+ */
+typedef void (*SAIcallback)(void);
+
+/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
+ * @brief SAI Init Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
+ This parameter can be a value of @ref SAI_Block_Mode */
+
+ uint32_t Synchro; /*!< Specifies SAI Block synchronization
+ This parameter can be a value of @ref SAI_Block_Synchronization */
+
+ uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
+ for BlockA and BlockB
+ This parameter can be a value of @ref SAI_Block_SyncExt
+ @note: If both audio blocks of same SAI are used, this parameter has
+ to be set to the same value for each audio block */
+
+ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
+ This parameter can be a value of @ref SAI_Block_Output_Drive
+ @note this value has to be set before enabling the audio block
+ but after the audio block configuration. */
+
+ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
+ This parameter can be a value of @ref SAI_Block_NoDivider
+ @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+ should be aligned to a number equal to a power of 2, from 8 to 256.
+ If bit NODIV in the SAI_xCR1 register is set, the frame length can
+ take any of the values without constraint since the input clock of
+ the audio block should be equal to the bit clock.
+ There is no MCLK_x clock which can be output. */
+
+ uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
+ This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
+
+ uint32_t ClockSource; /*!< Specifies the SAI Block x Clock source.
+ This parameter is not used for STM32F446xx devices. */
+
+ uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
+ This parameter can be a value of @ref SAI_Audio_Frequency */
+
+ uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
+ AudioFrequency the user choice
+ This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
+
+ uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
+ This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
+
+ uint32_t CompandingMode; /*!< Specifies the companding mode type.
+ This parameter can be a value of @ref SAI_Block_Companding_Mode */
+
+ uint32_t TriState; /*!< Specifies the companding mode type.
+ This parameter can be a value of @ref SAI_TRIState_Management */
+
+ /* This part of the structure is automatically filled if your are using the high level intialisation
+ function HAL_SAI_InitProtocol */
+
+ uint32_t Protocol; /*!< Specifies the SAI Block protocol.
+ This parameter can be a value of @ref SAI_Block_Protocol */
+
+ uint32_t DataSize; /*!< Specifies the SAI Block data size.
+ This parameter can be a value of @ref SAI_Block_Data_Size */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+
+ uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
+ This parameter can be a value of @ref SAI_Block_Clock_Strobing */
+}SAI_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
+ * @brief SAI Frame Init structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
+ This parameter must be a number between Min_Data = 8 and Max_Data = 256.
+ @note If master clock MCLK_x pin is declared as an output, the frame length
+ should be aligned to a number equal to power of 2 in order to keep
+ in an audio frame, an integer number of MCLK pulses by bit Clock. */
+
+ uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
+ This Parameter specifies the length in number of bit clock (SCK + 1)
+ of the active level of FS signal in audio frame.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
+
+ uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
+ This parameter can be a value of @ref SAI_Block_FS_Definition */
+
+ uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
+ This parameter can be a value of @ref SAI_Block_FS_Polarity */
+
+ uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
+ This parameter can be a value of @ref SAI_Block_FS_Offset */
+}SAI_FrameInitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
+ * @brief SAI Block Slot Init Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
+
+ uint32_t SlotSize; /*!< Specifies the Slot Size.
+ This parameter can be a value of @ref SAI_Block_Slot_Size */
+
+ uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
+ This parameter can be a value of @ref SAI_Block_Slot_Active */
+}SAI_SlotInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
+ * @brief SAI handle Structure definition
+ * @{
+ */
+typedef struct __SAI_HandleTypeDef
+{
+ SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
+
+ SAI_InitTypeDef Init; /*!< SAI communication parameters */
+
+ SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
+
+ SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
+
+ uint16_t XferSize; /*!< SAI transfer size */
+
+ uint16_t XferCount; /*!< SAI transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
+
+ SAIcallback mutecallback;/*!< SAI mute callback */
+
+ void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
+
+ HAL_LockTypeDef Lock; /*!< SAI locking object */
+
+ __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SAI Error code */
+}SAI_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Constants SAI Exported Constants
+ * @{
+ */
+
+/** @defgroup SAI_Error_Code SAI Error Code
+ * @{
+ */
+#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */
+#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */
+#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */
+#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */
+#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */
+#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation
+ * @{
+ */
+#define SAI_SYNCEXT_DISABLE 0U
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Protocol SAI Supported protocol
+ * @{
+ */
+#define SAI_I2S_STANDARD 0U
+#define SAI_I2S_MSBJUSTIFIED 1U
+#define SAI_I2S_LSBJUSTIFIED 2U
+#define SAI_PCM_LONG 3U
+#define SAI_PCM_SHORT 4U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Protocol_DataSize SAI protocol data size
+ * @{
+ */
+#define SAI_PROTOCOL_DATASIZE_16BIT 0U
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
+#define SAI_PROTOCOL_DATASIZE_24BIT 2U
+#define SAI_PROTOCOL_DATASIZE_32BIT 3U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
+ * @{
+ */
+#define SAI_AUDIO_FREQUENCY_192K 192000U
+#define SAI_AUDIO_FREQUENCY_96K 96000U
+#define SAI_AUDIO_FREQUENCY_48K 48000U
+#define SAI_AUDIO_FREQUENCY_44K 44100U
+#define SAI_AUDIO_FREQUENCY_32K 32000U
+#define SAI_AUDIO_FREQUENCY_22K 22050U
+#define SAI_AUDIO_FREQUENCY_16K 16000U
+#define SAI_AUDIO_FREQUENCY_11K 11025U
+#define SAI_AUDIO_FREQUENCY_8K 8000U
+#define SAI_AUDIO_FREQUENCY_MCKDIV 0U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mode SAI Block Mode
+ * @{
+ */
+#define SAI_MODEMASTER_TX 0x00000000U
+#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
+#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
+#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Protocol SAI Block Protocol
+ * @{
+ */
+#define SAI_FREE_PROTOCOL 0x00000000U
+#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
+#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Data_Size SAI Block Data Size
+ * @{
+ */
+#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
+#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
+#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
+#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
+ * @{
+ */
+#define SAI_FIRSTBIT_MSB 0x00000000U
+#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
+ * @{
+ */
+#define SAI_CLOCKSTROBING_FALLINGEDGE 0U
+#define SAI_CLOCKSTROBING_RISINGEDGE 1U
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
+ * @{
+ */
+#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */
+#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */
+#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U
+#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
+ * @{
+ */
+#define SAI_MASTERDIVIDER_ENABLE 0x00000000U
+#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
+ * @{
+ */
+#define SAI_FS_STARTFRAME 0x00000000U
+#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
+ * @{
+ */
+#define SAI_FS_ACTIVE_LOW 0x00000000U
+#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
+ * @{
+ */
+#define SAI_FS_FIRSTBIT 0x00000000U
+#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
+ * @{
+ */
+#define SAI_SLOTSIZE_DATASIZE 0x00000000U
+#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
+#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
+ * @{
+ */
+#define SAI_SLOT_NOTACTIVE 0x00000000U
+#define SAI_SLOTACTIVE_0 0x00000001U
+#define SAI_SLOTACTIVE_1 0x00000002U
+#define SAI_SLOTACTIVE_2 0x00000004U
+#define SAI_SLOTACTIVE_3 0x00000008U
+#define SAI_SLOTACTIVE_4 0x00000010U
+#define SAI_SLOTACTIVE_5 0x00000020U
+#define SAI_SLOTACTIVE_6 0x00000040U
+#define SAI_SLOTACTIVE_7 0x00000080U
+#define SAI_SLOTACTIVE_8 0x00000100U
+#define SAI_SLOTACTIVE_9 0x00000200U
+#define SAI_SLOTACTIVE_10 0x00000400U
+#define SAI_SLOTACTIVE_11 0x00000800U
+#define SAI_SLOTACTIVE_12 0x00001000U
+#define SAI_SLOTACTIVE_13 0x00002000U
+#define SAI_SLOTACTIVE_14 0x00004000U
+#define SAI_SLOTACTIVE_15 0x00008000U
+#define SAI_SLOTACTIVE_ALL 0x0000FFFFU
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
+ * @{
+ */
+#define SAI_STEREOMODE 0x00000000U
+#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_TRIState_Management SAI TRIState Management
+ * @{
+ */
+#define SAI_OUTPUT_NOTRELEASED 0x00000000U
+#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
+ * @{
+ */
+#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
+#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
+#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
+ * @{
+ */
+#define SAI_NOCOMPANDING 0x00000000U
+#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
+#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
+#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
+#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
+ * @{
+ */
+#define SAI_ZERO_VALUE 0x00000000U
+#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
+ * @{
+ */
+#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
+#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
+#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
+#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
+#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
+#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
+#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
+ * @{
+ */
+#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
+#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
+#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
+#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
+#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
+#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
+#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
+ * @{
+ */
+#define SAI_FIFOSTATUS_EMPTY 0x00000000U
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
+#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
+#define SAI_FIFOSTATUS_HALFFULL 0x00030000U
+#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
+#define SAI_FIFOSTATUS_FULL 0x00050000U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Macros SAI Exported Macros
+ * @brief macros to handle interrupts and specific configurations
+ * @{
+ */
+
+/** @brief Reset SAI handle state
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @retval NoneS
+ */
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+
+/** @brief Enable or disable the specified SAI interrupts.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+ * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+ * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+ * @arg SAI_IT_FREQ: FIFO request interrupt enable
+ * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+ * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+ * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+ * @retval None
+ */
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
+
+/** @brief Check if the specified SAI interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
+ * @param __INTERRUPT__ specifies the SAI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+ * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+ * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+ * @arg SAI_IT_FREQ: FIFO request interrupt enable
+ * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+ * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+ * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SAI flag is set or not.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
+ * @arg SAI_FLAG_MUTEDET: Mute detection flag.
+ * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
+ * @arg SAI_FLAG_FREQ: FIFO request flag.
+ * @arg SAI_FLAG_CNRDY: Codec not ready flag.
+ * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
+ * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified SAI pending flag.
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
+ * @arg SAI_FLAG_MUTEDET: Clear Mute detection
+ * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
+ * @arg SAI_FLAG_FREQ: Clear FIFO request
+ * @arg SAI_FLAG_CNRDY: Clear Codec not ready
+ * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
+ * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
+ * @retval None
+ */
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
+
+/** @brief Enable SAI
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @retval None
+ */
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
+
+/** @brief Disable SAI
+ * @param __HANDLE__ specifies the SAI Handle.
+ * @retval None
+ */
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
+
+ /**
+ * @}
+ */
+
+/* Include RCC SAI Extension module */
+#include "stm32f4xx_hal_sai_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SAI_Exported_Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+/** @addtogroup SAI_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+
+/**
+ * @}
+ */
+
+/* I/O operation functions *****************************************************/
+/** @addtogroup SAI_Exported_Functions_Group2
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+
+/* Abort function */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
+
+/* Mute management */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
+
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+
+/** @addtogroup SAI_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SAI_Private_Macros
+ * @{
+ */
+#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
+
+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
+ ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
+ ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
+ ((PROTOCOL) == SAI_PCM_LONG) ||\
+ ((PROTOCOL) == SAI_PCM_SHORT))
+
+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
+
+#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
+ ((MODE) == SAI_MODEMASTER_RX) || \
+ ((MODE) == SAI_MODESLAVE_TX) || \
+ ((MODE) == SAI_MODESLAVE_RX))
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
+ ((PROTOCOL) == SAI_AC97_PROTOCOL) || \
+ ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
+ ((DATASIZE) == SAI_DATASIZE_10) || \
+ ((DATASIZE) == SAI_DATASIZE_16) || \
+ ((DATASIZE) == SAI_DATASIZE_20) || \
+ ((DATASIZE) == SAI_DATASIZE_24) || \
+ ((DATASIZE) == SAI_DATASIZE_32))
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+ ((BIT) == SAI_FIRSTBIT_LSB))
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+ ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
+ ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
+ ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
+
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
+ ((VALUE) == SAI_LAST_SENT_VALUE))
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
+ ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+ ((STATE) == SAI_OUTPUT_RELEASED))
+
+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+ ((MODE) == SAI_STEREOMODE))
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
+
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+ ((SIZE) == SAI_SLOTSIZE_16B) || \
+ ((SIZE) == SAI_SLOTSIZE_32B))
+
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+ ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U)
+
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
+
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
+
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SAI_Private_Functions SAI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SAI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,325 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai_ex.c
+ * @author MCD Application Team
+ * @brief SAI Extension HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of SAI extension peripheral:
+ * + Extension features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SAI peripheral extension features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the SAI interface for STM32F446xx
+ devices contains the following additional features :
+
+ (+) Possibility to be clocked from PLLR
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to manage several sources to clock SAI
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SAIEx SAIEx
+ * @brief SAI Extension HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \
+ defined(STM32F423xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SAI registers Masks */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SAI_Private_Functions SAI Private Functions
+ * @{
+ */
+ /**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions
+ * @brief Extension features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension features Functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the possible
+ SAI clock sources.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure SAI Block synchronization mode
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval SAI Clock Input
+ */
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
+{
+ uint32_t tmpregisterGCR = 0U;
+
+#if defined(STM32F446xx)
+ /* This setting must be done with both audio block (A & B) disabled */
+ switch(hsai->Init.SynchroExt)
+ {
+ case SAI_SYNCEXT_DISABLE :
+ tmpregisterGCR = 0U;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+ break;
+ default:
+ break;
+ }
+
+ if((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2)
+ {
+ tmpregisterGCR |= SAI_GCR_SYNCIN_0;
+ }
+
+ if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+ {
+ SAI1->GCR = tmpregisterGCR;
+ }
+ else
+ {
+ SAI2->GCR = tmpregisterGCR;
+ }
+#endif /* STM32F446xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+ /* This setting must be done with both audio block (A & B) disabled */
+ switch(hsai->Init.SynchroExt)
+ {
+ case SAI_SYNCEXT_DISABLE :
+ tmpregisterGCR = 0U;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+ break;
+ case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+ break;
+ default:
+ break;
+ }
+ SAI1->GCR = tmpregisterGCR;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+}
+ /**
+ * @brief Get SAI Input Clock based on SAI source clock selection
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval SAI Clock Input
+ */
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
+{
+ /* This variable used to store the SAI_CK_x (value in Hz) */
+ uint32_t saiclocksource = 0U;
+
+#if defined(STM32F446xx)
+ if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+ {
+ saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
+ }
+ else /* SAI2_Block_A || SAI2_Block_B*/
+ {
+ saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
+ }
+#endif /* STM32F446xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+ uint32_t vcoinput = 0U, tmpreg = 0U;
+
+ /* Check the SAI Block parameters */
+ assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
+
+ /* SAI Block clock source selection */
+ if(hsai->Instance == SAI1_Block_A)
+ {
+ __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
+ }
+ else
+ {
+ __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2U));
+ }
+
+ /* VCO Input Clock value calculation */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+ }
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
+ if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLR)
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ /* PLL_VCO Output = PLL_VCO Input * PLLN */
+ /* SAI_CLK(first level) = PLL_VCO Output/PLLR */
+ tmpreg = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
+ saiclocksource = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+ tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> 8U) + 1U);
+
+ saiclocksource = saiclocksource/(tmpreg);
+
+ }
+ else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U;
+ saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
+ tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) + 1U);
+ saiclocksource = saiclocksource/(tmpreg);
+ }
+ else if(hsai->Init.ClockSource == SAI_CLKSOURCE_HS)
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* Get the I2S source clock value */
+ saiclocksource = (uint32_t)(HSE_VALUE);
+ }
+ else
+ {
+ /* Get the I2S source clock value */
+ saiclocksource = (uint32_t)(HSI_VALUE);
+ }
+ }
+ else /* sConfig->ClockSource == SAI_CLKSource_Ext */
+ {
+ saiclocksource = EXTERNAL_CLOCK_VALUE;
+ }
+#else
+ /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
+ if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
+ saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
+ saiclocksource = saiclocksource/(tmpreg);
+
+ }
+ else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
+ saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
+ saiclocksource = saiclocksource/(tmpreg);
+ }
+ else /* sConfig->ClockSource == SAI_CLKSource_Ext */
+ {
+ /* Enable the External Clock selection */
+ __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
+
+ saiclocksource = EXTERNAL_CLOCK_VALUE;
+ }
+#endif /* STM32F413xx || STM32F423xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+ /* the return result is the value of SAI clock */
+ return saiclocksource;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,132 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SAI Extension HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SAI_EX_H
+#define __STM32F4xx_HAL_SAI_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SAIEx
+ * @{
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \
+ defined(STM32F423xx)
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SAI_Clock_Source SAI Clock Source
+ * @{
+ */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define SAI_CLKSOURCE_PLLI2S 0x00000000U
+#define SAI_CLKSOURCE_EXT 0x00100000U
+#define SAI_CLKSOURCE_PLLR 0x00200000U
+#define SAI_CLKSOURCE_HS 0x00300000U
+#else
+#define SAI_CLKSOURCE_PLLSAI 0x00000000U
+#define SAI_CLKSOURCE_PLLI2S 0x00100000U
+#define SAI_CLKSOURCE_EXT 0x00200000U
+#define SAI_CLKSOURCE_NA 0x00400000U /*!< No applicable for STM32F446xx */
+#endif
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAIEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SAIEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Extended features functions ************************************************/
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai);
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == SAI_CLKSOURCE_EXT)||\
+ ((SOURCE) == SAI_CLKSOURCE_PLLR)||\
+ ((SOURCE) == SAI_CLKSOURCE_HS))
+#else
+#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == SAI_CLKSOURCE_EXT)||\
+ ((SOURCE) == SAI_CLKSOURCE_PLLI2S)||\
+ ((SOURCE) == SAI_CLKSOURCE_NA))
+#endif
+/* Private functions ---------------------------------------------------------*/
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SAI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,3025 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sd.c
+ * @author MCD Application Team
+ * @brief SD card HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Secure Digital (SD) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + SD card Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
+ the user in HAL_SD_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
+ examples.
+ You can easily tailor this configuration according to hardware resources.
+
+ [..]
+ This driver is a generic layered driver for SDIO memories which uses the HAL
+ SDIO driver functions to interface with SD and uSD cards devices.
+ It is used as follows:
+
+ (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
+ (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
+ (##) SDIO pins configuration for SD card
+ (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
+ and according to your pin assignment;
+ (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+ and HAL_SD_WriteBlocks_DMA() APIs).
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+ (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
+ (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
+ (+++) Configure the SDIO and DMA interrupt priorities using functions
+ HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
+ (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ and __HAL_SD_DISABLE_IT() inside the communication process.
+ (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+ and __HAL_SD_CLEAR_IT()
+ (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+ and HAL_SD_WriteBlocks_IT() APIs).
+ (+++) Configure the SDIO interrupt priorities using function
+ HAL_NVIC_SetPriority();
+ (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ and __HAL_SD_DISABLE_IT() inside the communication process.
+ (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+ and __HAL_SD_CLEAR_IT()
+ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+
+
+ *** SD Card Initialization and configuration ***
+ ================================================
+ [..]
+ To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+ SDIO IP(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
+ This function provide the following operations:
+
+ (#) Initialize the SDIO peripheral interface with defaullt configuration.
+ The initialization process is done at 400KHz. You can change or adapt
+ this frequency by adjusting the "ClockDiv" field.
+ The SD Card frequency (SDIO_CK) is computed as follows:
+
+ SDIO_CK = SDIOCLK / (ClockDiv + 2)
+
+ In initialization mode and according to the SD Card standard,
+ make sure that the SDIO_CK frequency doesn't exceed 400KHz.
+
+ This phase of initialization is done through SDIO_Init() and
+ SDIO_PowerState_ON() SDIO low level APIs.
+
+ (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+ This phase allows the card initialization and identification
+ and check the SD Card type (Standard Capacity or High Capacity)
+ The initialization flow is compatible with SD standard.
+
+ This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+ of plug-off plug-in.
+
+ (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
+ frequency is set to 24MHz. You can change or adapt this frequency by adjusting
+ the "ClockDiv" field.
+ In transfer mode and according to the SD Card standard, make sure that the
+ SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+ To be able to use a frequency higher than 24MHz, you should use the SDIO
+ peripheral in bypass mode. Refer to the corresponding reference manual
+ for more details.
+
+ (#) Select the corresponding SD Card according to the address read with the step 2.
+
+ (#) Configure the SD Card in wide bus mode: 4-bits data.
+
+ *** SD Card Read operation ***
+ ==============================
+ [..]
+ (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+
+ (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the DMA transfer process through the SD Rx interrupt event.
+
+ (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the IT transfer process through the SD Rx interrupt event.
+
+ *** SD Card Write operation ***
+ ===============================
+ [..]
+ (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+
+ (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the DMA transfer process through the SD Tx interrupt event.
+
+ (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the IT transfer process through the SD Tx interrupt event.
+
+ *** SD card status ***
+ ======================
+ [..]
+ (+) The SD Status contains status bits that are related to the SD Memory
+ Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+
+ *** SD card information ***
+ ===========================
+ [..]
+ (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+ It returns useful information about the SD card such as block size, card type,
+ block number ...
+
+ *** SD card CSD register ***
+ ============================
+ [..]
+ (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+ Some of the CSD parameters are useful for card initialization and identification.
+
+ *** SD card CID register ***
+ ============================
+ [..]
+ (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+ Some of the CSD parameters are useful for card initialization and identification.
+
+ *** SD HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SD HAL driver.
+
+ (+) __HAL_SD_ENABLE : Enable the SD device
+ (+) __HAL_SD_DISABLE : Disable the SD device
+ (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
+ (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer
+ (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+ (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+ (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+ (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+
+ [..]
+ (@) You can refer to the SD HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SD
+ * @{
+ */
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup SD_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+ * @{
+ */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd);
+static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd);
+static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd);
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAError(DMA_HandleTypeDef *hdma);
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SD_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize the SD
+ card device to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SD according to the specified parameters in the
+ SD_HandleTypeDef and create the associated handle.
+ * @param hsd Pointer to the SD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{
+ /* Check the SD handle allocation */
+ if(hsd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
+ assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge));
+ assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass));
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+ assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+ assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));
+
+ if(hsd->State == HAL_SD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsd->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_SD_MspInit(hsd);
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize the Card parameters */
+ HAL_SD_InitCard(hsd);
+
+ /* Initialize the error code */
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the SD operation */
+ hsd->Context = SD_CONTEXT_NONE;
+
+ /* Initialize the SD state */
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the SD Card.
+ * @param hsd Pointer to SD handle
+ * @note This function initializes the SD card. It could be used when a card
+ re-initialization is needed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ SD_InitTypeDef Init;
+
+ /* Default SDIO peripheral configuration for SD card initialization */
+ Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+ Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+ Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+ Init.BusWide = SDIO_BUS_WIDE_1B;
+ Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+ Init.ClockDiv = SDIO_INIT_CLK_DIV;
+
+ /* Initialize SDIO peripheral interface with default configuration */
+ SDIO_Init(hsd->Instance, Init);
+
+ /* Disable SDIO Clock */
+ __HAL_SD_DISABLE(hsd);
+
+ /* Set Power State to ON */
+ SDIO_PowerState_ON(hsd->Instance);
+
+ /* Enable SDIO Clock */
+ __HAL_SD_ENABLE(hsd);
+
+ /* Required power up waiting time before starting the SD initialization
+ sequence */
+ HAL_Delay(2U);
+
+ /* Identify card operating voltage */
+ errorstate = SD_PowerON(hsd);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ /* Card initialization */
+ errorstate = SD_InitCard(hsd);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initializes the SD card.
+ * @param hsd Pointer to SD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+{
+ /* Check the SD handle allocation */
+ if(hsd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Set SD power state to off */
+ SD_PowerOFF(hsd);
+
+ /* De-Initialize the MSP layer */
+ HAL_SD_MspDeInit(hsd);
+
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the SD MSP.
+ * @param hsd Pointer to SD handle
+ * @retval None
+ */
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize SD MSP.
+ * @param hsd Pointer to SD handle
+ * @retval None
+ */
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup SD_Exported_Functions_Group2
+ * @brief Data transfer functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the data
+ transfer from/to SD card.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @param hsd Pointer to SD handle
+ * @param pData pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of SD blocks to read
+ * @param Timeout Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U, *tempbuff = (uint32_t *)pData;
+
+ if(NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Read block(s) in polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Poll on SDIO flags */
+#ifdef SDIO_STA_STBITERR
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
+ {
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ {
+ /* Read data from SDIO Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+ }
+ tempbuff += 8U;
+ }
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+ hsd->State= HAL_SD_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send stop transmission command in case of multiblock read */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Get error state */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Empty FIFO if there is still any data */
+ while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
+ {
+ *tempbuff = SDIO_ReadFIFO(hsd->Instance);
+ tempbuff++;
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+ hsd->State= HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Allows to write block(s) to a specified address in a card. The Data
+ * transfer is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @param hsd Pointer to SD handle
+ * @param pData pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of SD blocks to write
+ * @param Timeout Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U;
+ uint32_t *tempbuff = (uint32_t *)pData;
+
+ if(NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Write block(s) in polling mode */
+#ifdef SDIO_STA_STBITERR
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
+ {
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
+ {
+ /* Write data to SDIO Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
+ }
+ tempbuff += 8U;
+ }
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send stop transmission command in case of multiblock write */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Get error state */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the IT transfer process through the SD Rx
+ * interrupt event.
+ * @param hsd Pointer to SD handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ hsd->pRxBuffPtr = (uint32_t *)pData;
+ hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+#ifdef SDIO_STA_STBITER
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
+#endif /* SDIO_STA_STBITERR */
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Read Blocks in IT mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the IT transfer process through the SD Tx
+ * interrupt event.
+ * @param hsd Pointer to SD handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ hsd->pTxBuffPtr = (uint32_t *)pData;
+ hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ /* Enable transfer interrupts */
+#ifdef SDIO_STA_STBITER
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
+#endif /* SDIO_STA_STBITERR */
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the DMA transfer process through the SD Rx
+ * interrupt event.
+ * @param hsd Pointer SD handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+#ifdef SDIO_STA_STBITER
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+#endif /* SDIO_STA_STBITERR */
+
+ /* Set the DMA transfer complete callback */
+ hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hsd->hdmarx->XferErrorCallback = SD_DMAError;
+
+ /* Set the DMA Abort callback */
+ hsd->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+
+ /* Enable SD DMA transfer */
+ __HAL_SD_DMA_ENABLE(hsd);
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Read Blocks in DMA mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the DMA transfer process through the SD Tx
+ * interrupt event.
+ * @param hsd Pointer to SD handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ /* Enable SD Error interrupts */
+#ifdef SDIO_STA_STBITER
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
+#endif /* SDIO_STA_STBITERR */
+
+ /* Set the DMA transfer complete callback */
+ hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hsd->hdmatx->XferErrorCallback = SD_DMAError;
+
+ /* Set the DMA Abort callback */
+ hsd->hdmatx->XferAbortCallback = NULL;
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Enable SDIO DMA transfer */
+ __HAL_SD_DMA_ENABLE(hsd);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Erases the specified memory area of the given SD card.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @param hsd Pointer to SD handle
+ * @param BlockStartAdd Start Block address
+ * @param BlockEndAdd End Block address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if(BlockEndAdd < BlockStartAdd)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(BlockEndAdd > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Check if the card command class supports erase command */
+ if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Get start and end block for high capacity cards */
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockStartAdd *= 512U;
+ BlockEndAdd *= 512U;
+ }
+
+ /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send CMD32 SD_ERASE_GRP_START with argument as addr */
+ errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send CMD33 SD_ERASE_GRP_END with argument as addr */
+ errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Send CMD38 ERASE */
+ errorstate = SDMMC_CmdErase(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles SD card interrupt request.
+ * @param hsd Pointer to SD handle
+ * @retval None
+ */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ /* Check for SDIO interrupt flags */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DATAEND) != RESET)
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
+
+#ifdef SDIO_STA_STBITERR
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+#endif
+
+ if((hsd->Context & SD_CONTEXT_IT) != RESET)
+ {
+ if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= errorstate;
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+ if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
+ {
+ HAL_SD_RxCpltCallback(hsd);
+ }
+ else
+ {
+ HAL_SD_TxCpltCallback(hsd);
+ }
+ }
+ else if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+ {
+ if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
+ {
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= errorstate;
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
+ if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
+ {
+ /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+ in the SD DCTRL register */
+ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ HAL_SD_TxCpltCallback(hsd);
+ }
+ }
+ }
+
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXFIFOHE) != RESET)
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_TXFIFOHE);
+
+ SD_Write_IT(hsd);
+ }
+
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXFIFOHF) != RESET)
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXFIFOHF);
+
+ SD_Read_IT(hsd);
+ }
+
+#ifdef SDIO_STA_STBITERR
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET)
+ {
+ /* Set Error code */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DTIMEOUT) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXOVERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXUNDERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_STBITERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR);
+
+ /* Disable all interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR);
+
+ if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+ {
+ /* Abort the SD DMA Streams */
+ if(hsd->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+ {
+ SD_DMATxAbort(hsd->hdmatx);
+ }
+ }
+ else if(hsd->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+ {
+ SD_DMARxAbort(hsd->hdmarx);
+ }
+ }
+ else
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_READY;
+ HAL_SD_AbortCallback(hsd);
+ }
+ }
+ else if((hsd->Context & SD_CONTEXT_IT) != RESET)
+ {
+ /* Set the SD state to ready to be able to start again the process */
+ hsd->State = HAL_SD_STATE_READY;
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
+#else /* SDIO_STA_STBITERR not defined */
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR) != RESET)
+ {
+ /* Set Error code */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DTIMEOUT) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXOVERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXUNDERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ }
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* Disable all interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+ {
+ /* Abort the SD DMA Streams */
+ if(hsd->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+ {
+ SD_DMATxAbort(hsd->hdmatx);
+ }
+ }
+ else if(hsd->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+ {
+ SD_DMARxAbort(hsd->hdmarx);
+ }
+ }
+ else
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_READY;
+ HAL_SD_AbortCallback(hsd);
+ }
+ }
+ else if((hsd->Context & SD_CONTEXT_IT) != RESET)
+ {
+ /* Set the SD state to ready to be able to start again the process */
+ hsd->State = HAL_SD_STATE_READY;
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
+#endif
+}
+
+/**
+ * @brief return the SD state
+ * @param hsd Pointer to sd handle
+ * @retval HAL state
+ */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+{
+ return hsd->State;
+}
+
+/**
+* @brief Return the SD error code
+* @param hsd Pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information.
+* @retval SD Error Code
+*/
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+{
+ return hsd->ErrorCode;
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hsd Pointer to SD handle
+ * @retval None
+ */
+ __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hsd Pointer SD handle
+ * @retval None
+ */
+__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD error callbacks
+ * @param hsd Pointer SD handle
+ * @retval None
+ */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD Abort callbacks
+ * @param hsd Pointer SD handle
+ * @retval None
+ */
+__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_ErrorCallback can be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup SD_Exported_Functions_Group3
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SD card
+ operations and get the related information
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CID register.
+ * @param hsd Pointer to SD handle
+ * @param pCID Pointer to a HAL_SD_CIDTypeDef structure that
+ * contains all CID register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
+{
+ uint32_t tmp = 0U;
+
+ /* Byte 0 */
+ tmp = (uint8_t)((hsd->CID[0U] & 0xFF000000U) >> 24U);
+ pCID->ManufacturerID = tmp;
+
+ /* Byte 1 */
+ tmp = (uint8_t)((hsd->CID[0U] & 0x00FF0000U) >> 16U);
+ pCID->OEM_AppliID = tmp << 8U;
+
+ /* Byte 2 */
+ tmp = (uint8_t)((hsd->CID[0U] & 0x000000FF00U) >> 8U);
+ pCID->OEM_AppliID |= tmp;
+
+ /* Byte 3 */
+ tmp = (uint8_t)(hsd->CID[0U] & 0x000000FFU);
+ pCID->ProdName1 = tmp << 24U;
+
+ /* Byte 4 */
+ tmp = (uint8_t)((hsd->CID[1U] & 0xFF000000U) >> 24U);
+ pCID->ProdName1 |= tmp << 16;
+
+ /* Byte 5 */
+ tmp = (uint8_t)((hsd->CID[1U] & 0x00FF0000U) >> 16U);
+ pCID->ProdName1 |= tmp << 8U;
+
+ /* Byte 6 */
+ tmp = (uint8_t)((hsd->CID[1U] & 0x0000FF00U) >> 8U);
+ pCID->ProdName1 |= tmp;
+
+ /* Byte 7 */
+ tmp = (uint8_t)(hsd->CID[1U] & 0x000000FFU);
+ pCID->ProdName2 = tmp;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hsd->CID[2U] & 0xFF000000U) >> 24U);
+ pCID->ProdRev = tmp;
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hsd->CID[2U] & 0x00FF0000U) >> 16U);
+ pCID->ProdSN = tmp << 24U;
+
+ /* Byte 10 */
+ tmp = (uint8_t)((hsd->CID[2U] & 0x0000FF00U) >> 8U);
+ pCID->ProdSN |= tmp << 16U;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hsd->CID[2U] & 0x000000FFU);
+ pCID->ProdSN |= tmp << 8U;
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hsd->CID[3U] & 0xFF000000U) >> 24U);
+ pCID->ProdSN |= tmp;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hsd->CID[3U] & 0x00FF0000U) >> 16U);
+ pCID->Reserved1 |= (tmp & 0xF0U) >> 4U;
+ pCID->ManufactDate = (tmp & 0x0FU) << 8U;
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hsd->CID[3U] & 0x0000FF00U) >> 8U);
+ pCID->ManufactDate |= tmp;
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hsd->CID[3U] & 0x000000FFU);
+ pCID->CID_CRC = (tmp & 0xFEU) >> 1U;
+ pCID->Reserved2 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CSD register.
+ * @param hsd Pointer to SD handle
+ * @param pCSD Pointer to a HAL_SD_CardCSDTypeDef structure that
+ * contains all CSD register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+{
+ uint32_t tmp = 0U;
+
+ /* Byte 0 */
+ tmp = (hsd->CSD[0U] & 0xFF000000U) >> 24U;
+ pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U);
+ pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
+ pCSD->Reserved1 = tmp & 0x03U;
+
+ /* Byte 1 */
+ tmp = (hsd->CSD[0U] & 0x00FF0000U) >> 16U;
+ pCSD->TAAC = (uint8_t)tmp;
+
+ /* Byte 2 */
+ tmp = (hsd->CSD[0U] & 0x0000FF00U) >> 8U;
+ pCSD->NSAC = (uint8_t)tmp;
+
+ /* Byte 3 */
+ tmp = hsd->CSD[0U] & 0x000000FFU;
+ pCSD->MaxBusClkFrec = (uint8_t)tmp;
+
+ /* Byte 4 */
+ tmp = (hsd->CSD[1U] & 0xFF000000U) >> 24U;
+ pCSD->CardComdClasses = (uint16_t)(tmp << 4U);
+
+ /* Byte 5 */
+ tmp = (hsd->CSD[1U] & 0x00FF0000U) >> 16U;
+ pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U);
+ pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU);
+
+ /* Byte 6 */
+ tmp = (hsd->CSD[1U] & 0x0000FF00U) >> 8U;
+ pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U);
+ pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
+ pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
+ pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U);
+ pCSD->Reserved2 = 0U; /*!< Reserved */
+
+ if(hsd->SdCard.CardType == CARD_SDSC)
+ {
+ pCSD->DeviceSize = (tmp & 0x03U) << 10U;
+
+ /* Byte 7 */
+ tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
+ pCSD->DeviceSize |= (tmp) << 2U;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
+ pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U;
+
+ pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
+ pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U);
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
+ pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
+ pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
+ pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U;
+ /* Byte 10 */
+ tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
+ pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U;
+
+ hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
+ hsd->SdCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U));
+ hsd->SdCard.BlockSize = 1U << (pCSD->RdBlockLen);
+
+ hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+ hsd->SdCard.LogBlockSize = 512U;
+ }
+ else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
+ {
+ /* Byte 7 */
+ tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
+ pCSD->DeviceSize = (tmp & 0x3FU) << 16U;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
+
+ pCSD->DeviceSize |= (tmp << 8U);
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
+
+ pCSD->DeviceSize |= (tmp);
+
+ /* Byte 10 */
+ tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
+
+ hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1U) * 1024U);
+ hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512U;
+ }
+ else
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ pCSD->EraseGrSize = (tmp & 0x40U) >> 6U;
+ pCSD->EraseGrMul = (tmp & 0x3FU) << 1U;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hsd->CSD[2U] & 0x000000FFU);
+ pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U;
+ pCSD->WrProtectGrSize = (tmp & 0x7FU);
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hsd->CSD[3U] & 0xFF000000U) >> 24U);
+ pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U;
+ pCSD->ManDeflECC = (tmp & 0x60U) >> 5U;
+ pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U;
+ pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hsd->CSD[3U] & 0x00FF0000U) >> 16U);
+ pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U;
+ pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
+ pCSD->Reserved3 = 0U;
+ pCSD->ContentProtectAppli = (tmp & 0x01U);
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hsd->CSD[3U] & 0x0000FF00U) >> 8U);
+ pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U;
+ pCSD->CopyFlag = (tmp & 0x40U) >> 6U;
+ pCSD->PermWrProtect = (tmp & 0x20U) >> 5U;
+ pCSD->TempWrProtect = (tmp & 0x10U) >> 4U;
+ pCSD->FileFormat = (tmp & 0x0CU) >> 2U;
+ pCSD->ECC = (tmp & 0x03U);
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hsd->CSD[3U] & 0x000000FFU);
+ pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U;
+ pCSD->Reserved4 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the SD status info.
+ * @param hsd Pointer to SD handle
+ * @param pStatus Pointer to the HAL_SD_CardStatusTypeDef structure that
+ * will contain the SD card status information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
+{
+ uint32_t tmp = 0U;
+ uint32_t sd_status[16U];
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ errorstate = SD_SendSDStatus(hsd, sd_status);
+ if(errorstate != HAL_OK)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Byte 0 */
+ tmp = (sd_status[0U] & 0xC0U) >> 6U;
+ pStatus->DataBusWidth = (uint8_t)tmp;
+
+ /* Byte 0 */
+ tmp = (sd_status[0U] & 0x20U) >> 5U;
+ pStatus->SecuredMode = (uint8_t)tmp;
+
+ /* Byte 2 */
+ tmp = (sd_status[0U] & 0x00FF0000U) >> 16U;
+ pStatus->CardType = (uint16_t)(tmp << 8U);
+
+ /* Byte 3 */
+ tmp = (sd_status[0U] & 0xFF000000U) >> 24U;
+ pStatus->CardType |= (uint16_t)tmp;
+
+ /* Byte 4 */
+ tmp = (sd_status[1U] & 0xFFU);
+ pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24U);
+
+ /* Byte 5 */
+ tmp = (sd_status[1U] & 0xFF00U) >> 8U;
+ pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16U);
+
+ /* Byte 6 */
+ tmp = (sd_status[1U] & 0xFF0000U) >> 16U;
+ pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8U);
+
+ /* Byte 7 */
+ tmp = (sd_status[1U] & 0xFF000000U) >> 24U;
+ pStatus->ProtectedAreaSize |= (uint32_t)tmp;
+
+ /* Byte 8 */
+ tmp = (sd_status[2U] & 0xFFU);
+ pStatus->SpeedClass = (uint8_t)tmp;
+
+ /* Byte 9 */
+ tmp = (sd_status[2U] & 0xFF00U) >> 8U;
+ pStatus->PerformanceMove = (uint8_t)tmp;
+
+ /* Byte 10 */
+ tmp = (sd_status[2U] & 0xF00000U) >> 20U;
+ pStatus->AllocationUnitSize = (uint8_t)tmp;
+
+ /* Byte 11 */
+ tmp = (sd_status[2U] & 0xFF000000U) >> 24U;
+ pStatus->EraseSize = (uint16_t)(tmp << 8U);
+
+ /* Byte 12 */
+ tmp = (sd_status[3U] & 0xFFU);
+ pStatus->EraseSize |= (uint16_t)tmp;
+
+ /* Byte 13 */
+ tmp = (sd_status[3U] & 0xFC00U) >> 10U;
+ pStatus->EraseTimeout = (uint8_t)tmp;
+
+ /* Byte 13 */
+ tmp = (sd_status[3U] & 0x0300U) >> 8U;
+ pStatus->EraseOffset = (uint8_t)tmp;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the SD card info.
+ * @param hsd Pointer to SD handle
+ * @param pCardInfo Pointer to the HAL_SD_CardInfoTypeDef structure that
+ * will contain the SD card status information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+{
+ pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType);
+ pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion);
+ pCardInfo->Class = (uint32_t)(hsd->SdCard.Class);
+ pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd);
+ pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr);
+ pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
+ pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
+ pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables wide bus operation for the requested card if supported by
+ * card.
+ * @param hsd Pointer to SD handle
+ * @param WideMode Specifies the SD card wide bus mode
+ * This parameter can be one of the following values:
+ * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
+ * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
+ * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+ SDIO_InitTypeDef Init;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_BUS_WIDE(WideMode));
+
+ /* Chnage Satte */
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ if(WideMode == SDIO_BUS_WIDE_8B)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else if(WideMode == SDIO_BUS_WIDE_4B)
+ {
+ errorstate = SD_WideBus_Enable(hsd);
+
+ hsd->ErrorCode |= errorstate;
+ }
+ else if(WideMode == SDIO_BUS_WIDE_1B)
+ {
+ errorstate = SD_WideBus_Disable(hsd);
+
+ hsd->ErrorCode |= errorstate;
+ }
+ else
+ {
+ /* WideMode is not a valid argument*/
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ }
+ }
+ else
+ {
+ /* MMC Card does not support this feature */
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Configure the SDIO peripheral */
+ Init.ClockEdge = hsd->Init.ClockEdge;
+ Init.ClockBypass = hsd->Init.ClockBypass;
+ Init.ClockPowerSave = hsd->Init.ClockPowerSave;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ SDIO_Init(hsd->Instance, Init);
+ }
+
+ /* Change State */
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Gets the current sd card data state.
+ * @param hsd pointer to SD handle
+ * @retval Card state
+ */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardStateTypeDef cardstate = HAL_SD_CARD_TRANSFER;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t resp1 = 0;
+
+ errorstate = SD_SendStatus(hsd, &resp1);
+ if(errorstate != HAL_OK)
+ {
+ hsd->ErrorCode |= errorstate;
+ }
+
+ cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9U) & 0x0FU);
+
+ return cardstate;
+}
+
+/**
+ * @brief Abort the current transfer and disable the SD.
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information for SD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
+ {
+ /* Disable the SD DMA request */
+ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Abort the SD DMA Tx Stream */
+ if(hsd->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hsd->hdmatx);
+ }
+ /* Abort the SD DMA Rx Stream */
+ if(hsd->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hsd->hdmarx);
+ }
+ }
+
+ hsd->State = HAL_SD_STATE_READY;
+ CardState = HAL_SD_GetCardState(hsd);
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+ }
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the current transfer and disable the SD (IT mode).
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information for SD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
+ {
+ /* Disable the SD DMA request */
+ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Abort the SD DMA Tx Stream */
+ if(hsd->hdmatx != NULL)
+ {
+ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+ if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+ {
+ hsd->hdmatx = NULL;
+ }
+ }
+ /* Abort the SD DMA Rx Stream */
+ if(hsd->hdmarx != NULL)
+ {
+ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+ if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+ {
+ hsd->hdmarx = NULL;
+ }
+ }
+ }
+
+ /* No transfer ongoing on both DMA channels*/
+ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
+ {
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->State = HAL_SD_STATE_READY;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+ }
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ HAL_SD_AbortCallback(hsd);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA SD transmit process complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+
+ /* Enable DATAEND Interrupt */
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
+}
+
+/**
+ * @brief DMA SD receive process complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ /* Send stop command in multiblock write */
+ if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= errorstate;
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
+
+ /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+ in the SD DCTRL register */
+ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ HAL_SD_RxCpltCallback(hsd);
+}
+
+/**
+ * @brief DMA SD communication error callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ HAL_SD_CardStateTypeDef CardState;
+
+ if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
+ {
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* Disable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ CardState = HAL_SD_GetCardState(hsd);
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+ }
+
+ hsd->State= HAL_SD_STATE_READY;
+ }
+
+ HAL_SD_ErrorCallback(hsd);
+}
+
+/**
+ * @brief DMA SD Tx Abort callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ HAL_SD_CardStateTypeDef CardState;
+
+ if(hsd->hdmatx != NULL)
+ {
+ hsd->hdmatx = NULL;
+ }
+
+ /* All DMA channels are aborted */
+ if(hsd->hdmarx == NULL)
+ {
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_READY;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ HAL_SD_AbortCallback(hsd);
+ }
+ else
+ {
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
+ }
+}
+
+/**
+ * @brief DMA SD Rx Abort callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ HAL_SD_CardStateTypeDef CardState;
+
+ if(hsd->hdmarx != NULL)
+ {
+ hsd->hdmarx = NULL;
+ }
+
+ /* All DMA channels are aborted */
+ if(hsd->hdmatx == NULL)
+ {
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_READY;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ HAL_SD_AbortCallback(hsd);
+ }
+ else
+ {
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
+ }
+}
+
+
+/**
+ * @brief Initializes the sd card.
+ * @param hsd Pointer to SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardCSDTypeDef CSD;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint16_t sd_rca = 1U;
+
+ /* Check the power State */
+ if(SDIO_GetPowerState(hsd->Instance) == 0U)
+ {
+ /* Power off */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send CMD2 ALL_SEND_CID */
+ errorstate = SDMMC_CmdSendCID(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card identification number data */
+ hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+ hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+ hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+ hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+ }
+ }
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send CMD3 SET_REL_ADDR with argument 0 */
+ /* SD Card publishes its RCA. */
+ errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ }
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Get the SD card RCA */
+ hsd->SdCard.RelCardAdd = sd_rca;
+
+ /* Send CMD9 SEND_CSD with argument as card's RCA */
+ errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card Specific Data */
+ hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+ hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+ hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+ hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+ }
+ }
+
+ /* Get the Card Class */
+ hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
+
+ /* Get CSD parameters */
+ HAL_SD_GetCardCSD(hsd, &CSD);
+
+ /* Select the Card */
+ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Configure SDIO peripheral interface */
+ SDIO_Init(hsd->Instance, hsd->Init);
+
+ /* All cards are initialized */
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Enquires cards about their operating voltage and configures clock
+ * controls and stores SD information that will be needed in future
+ * in the SD handle.
+ * @param hsd Pointer to SD handle
+ * @retval error state
+ */
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+{
+ __IO uint32_t count = 0U;
+ uint32_t response = 0U, validvoltage = 0U;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ /* CMD0: GO_IDLE_STATE */
+ errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+ errorstate = SDMMC_CmdOperCond(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->SdCard.CardVersion = CARD_V1_X;
+
+ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+ while(validvoltage == 0U)
+ {
+ if(count++ == SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_SD_ERROR_INVALID_VOLTRANGE;
+ }
+
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Send CMD41 */
+ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+ }
+ /* Card type is SDSC */
+ hsd->SdCard.CardType = CARD_SDSC;
+ }
+ else
+ {
+ hsd->SdCard.CardVersion = CARD_V2_X;
+
+ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+ while(validvoltage == 0U)
+ {
+ if(count++ == SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_SD_ERROR_INVALID_VOLTRANGE;
+ }
+
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD41 */
+ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+ }
+
+ if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+ {
+ hsd->SdCard.CardType = CARD_SDHC_SDXC;
+ }
+ else
+ {
+ hsd->SdCard.CardType = CARD_SDSC;
+ }
+ }
+
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Turns the SDIO output signals off.
+ * @param hsd Pointer to SD handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
+{
+ /* Set Power State to OFF */
+ SDIO_PowerState_OFF(hsd->Instance);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Send Status info command.
+ * @param hsd pointer to SD handle
+ * @param pSDstatus Pointer to the buffer that will contain the SD card status
+ * SD Status register)
+ * @retval error state
+ */
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U;
+
+ /* Check SD response */
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ }
+
+ /* Set block size for card if it is not equal to current block size for card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ return errorstate;
+ }
+
+ /* Send CMD55 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 64U;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
+ errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ return errorstate;
+ }
+
+ /* Get status data */
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+ {
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ {
+ for(count = 0U; count < 8U; count++)
+ {
+ *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
+ }
+
+ pSDstatus += 8U;
+ }
+
+ if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ return HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ return HAL_SD_ERROR_DATA_CRC_FAIL;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ {
+ return HAL_SD_ERROR_RX_OVERRUN;
+ }
+
+ while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
+ {
+ *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
+ pSDstatus++;
+
+ if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear all the static status flags*/
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Returns the current card's status.
+ * @param hsd Pointer to SD handle
+ * @param pCardStatus pointer to the buffer that will contain the SD card
+ * status (Card Status register)
+ * @retval error state
+ */
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ if(pCardStatus == NULL)
+ {
+ return HAL_SD_ERROR_PARAM;
+ }
+
+ /* Send Status command */
+ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ /* Get SD card status */
+ *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Enables the SDIO wide bus mode.
+ * @param hsd pointer to SD handle
+ * @retval error state
+ */
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+ uint32_t scr[2U] = {0U, 0U};
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ }
+
+ /* Get SCR Register */
+ errorstate = SD_FindSCR(hsd, scr);
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ /* If requested card supports wide bus operation */
+ if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ {
+ /* Send CMD55 APP_CMD with argument as card's RCA.*/
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ return HAL_SD_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+}
+
+/**
+ * @brief Disables the SDIO wide bus mode.
+ * @param hsd Pointer to SD handle
+ * @retval error state
+ */
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+ uint32_t scr[2U] = {0U, 0U};
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ }
+
+ /* Get SCR Register */
+ errorstate = SD_FindSCR(hsd, scr);
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ /* If requested card supports 1 bit mode operation */
+ if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ {
+ /* Send CMD55 APP_CMD with argument as card's RCA */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ return HAL_SD_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+}
+
+
+/**
+ * @brief Finds the SD card SCR register value.
+ * @param hsd Pointer to SD handle
+ * @param pSCR pointer to the buffer that will contain the SCR value
+ * @retval error state
+ */
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t index = 0U;
+ uint32_t tempscr[2U] = {0U, 0U};
+
+ /* Set Block Size To 8 Bytes */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD55 APP_CMD with argument as card's RCA */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 8U;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+ errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+ {
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
+ {
+ *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
+ index++;
+ }
+
+ if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+
+ return HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+
+ return HAL_SD_ERROR_DATA_CRC_FAIL;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+
+ return HAL_SD_ERROR_RX_OVERRUN;
+ }
+ else
+ {
+ /* No error flag set */
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ *(pSCR + 1U) = ((tempscr[0U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0U] & SDMMC_8TO15BITS) << 8U) |\
+ ((tempscr[0U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0U] & SDMMC_24TO31BITS) >> 24U);
+
+ *(pSCR) = ((tempscr[1U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1U] & SDMMC_8TO15BITS) << 8U) |\
+ ((tempscr[1U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1U] & SDMMC_24TO31BITS) >> 24U);
+ }
+
+ return HAL_SD_ERROR_NONE;
+}
+
+/**
+ * @brief Wrap up reading in non-blocking mode.
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd)
+{
+ uint32_t count = 0U;
+ uint32_t* tmp;
+
+ tmp = (uint32_t*)hsd->pRxBuffPtr;
+
+ /* Read data from SDIO Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ *(tmp + count) = SDIO_ReadFIFO(hsd->Instance);
+ }
+
+ hsd->pRxBuffPtr += 8U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Wrap up writing in non-blocking mode.
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+ uint32_t count = 0U;
+ uint32_t* tmp;
+
+ tmp = (uint32_t*)hsd->pTxBuffPtr;
+
+ /* Write data to SDIO Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ SDIO_WriteFIFO(hsd->Instance, (tmp + count));
+ }
+
+ hsd->pTxBuffPtr += 8U;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,723 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sd.h
+ * @author MCD Application Team
+ * @brief Header file of SD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SD_H
+#define __STM32F4xx_HAL_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SD SD
+ * @brief SD HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SD_Exported_Types SD Exported Types
+ * @{
+ */
+
+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
+ HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
+ HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
+ HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
+ HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
+ HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receinving State */
+ HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
+ HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
+}HAL_SD_StateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_SD_CARD_READY = 0x00000001U, /*!< Card state is ready */
+ HAL_SD_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
+ HAL_SD_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
+ HAL_SD_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
+ HAL_SD_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
+ HAL_SD_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
+ HAL_SD_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
+ HAL_SD_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
+ HAL_SD_CARD_ERROR = 0x000000FFU /*!< Card response Error */
+}HAL_SD_CardStateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
+ * @{
+ */
+#define SD_InitTypeDef SDIO_InitTypeDef
+#define SD_TypeDef SDIO_TypeDef
+
+/**
+ * @brief SD Card Information Structure definition
+ */
+typedef struct
+{
+ uint32_t CardType; /*!< Specifies the card Type */
+
+ uint32_t CardVersion; /*!< Specifies the card version */
+
+ uint32_t Class; /*!< Specifies the class of the card class */
+
+ uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
+
+ uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
+
+ uint32_t BlockSize; /*!< Specifies one block size in bytes */
+
+ uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
+
+ uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
+
+}HAL_SD_CardInfoTypeDef;
+
+/**
+ * @brief SD handle Structure definition
+ */
+typedef struct
+{
+ SD_TypeDef *Instance; /*!< SD registers base address */
+
+ SD_InitTypeDef Init; /*!< SD required parameters */
+
+ HAL_LockTypeDef Lock; /*!< SD locking object */
+
+ uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
+
+ uint32_t TxXferSize; /*!< SD Tx Transfer size */
+
+ uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
+
+ uint32_t RxXferSize; /*!< SD Rx Transfer size */
+
+ __IO uint32_t Context; /*!< SD transfer context */
+
+ __IO HAL_SD_StateTypeDef State; /*!< SD card State */
+
+ __IO uint32_t ErrorCode; /*!< SD Card Error codes */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
+
+ HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
+
+ uint32_t CSD[4]; /*!< SD card specific data table */
+
+ uint32_t CID[4]; /*!< SD card identification number table */
+
+}SD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t CSDStruct; /*!< CSD structure */
+ __IO uint8_t SysSpecVersion; /*!< System specification version */
+ __IO uint8_t Reserved1; /*!< Reserved */
+ __IO uint8_t TAAC; /*!< Data read access time 1 */
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ __IO uint16_t CardComdClasses; /*!< Card command classes */
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ __IO uint8_t DSRImpl; /*!< DSR implemented */
+ __IO uint8_t Reserved2; /*!< Reserved */
+ __IO uint32_t DeviceSize; /*!< Device Size */
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ __IO uint8_t EraseGrSize; /*!< Erase group size */
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ __IO uint8_t Reserved3; /*!< Reserved */
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
+ __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
+ __IO uint8_t FileFormat; /*!< File format */
+ __IO uint8_t ECC; /*!< ECC code */
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */
+ __IO uint8_t Reserved4; /*!< Always 1 */
+
+}HAL_SD_CardCSDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ __IO uint32_t ProdName1; /*!< Product Name part1 */
+ __IO uint8_t ProdName2; /*!< Product Name part2 */
+ __IO uint8_t ProdRev; /*!< Product Revision */
+ __IO uint32_t ProdSN; /*!< Product Serial Number */
+ __IO uint8_t Reserved1; /*!< Reserved1 */
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */
+ __IO uint8_t CID_CRC; /*!< CID CRC */
+ __IO uint8_t Reserved2; /*!< Always 1 */
+
+}HAL_SD_CardCIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
+ __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
+ __IO uint16_t CardType; /*!< Carries information about card type */
+ __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
+ __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
+ __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
+ __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
+ __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
+ __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
+ __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
+
+}HAL_SD_CardStatusTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants Exported Constants
+ * @{
+ */
+
+#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
+
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
+ * @{
+ */
+#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
+#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
+#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
+#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
+#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
+#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
+#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
+#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
+#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
+#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
+#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
+#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
+#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
+#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
+#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
+#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
+#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
+#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
+ * @{
+ */
+#define SD_CONTEXT_NONE 0x00000000U /*!< None */
+#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
+ * @{
+ */
+#define CARD_SDSC 0x00000000U
+#define CARD_SDHC_SDXC 0x00000001U
+#define CARD_SECURED 0x00000003U
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
+ * @{
+ */
+#define CARD_V1_X 0x00000000U
+#define CARD_V2_X 0x00000001U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SD_Exported_macros SD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the SD device.
+ * @retval None
+ */
+#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the SD device.
+ * @retval None
+ */
+#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the SDMMC DMA transfer.
+ * @retval None
+ */
+#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the SDMMC DMA transfer.
+ * @retval None
+ */
+#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the SD device interrupt.
+ * @param __HANDLE__ SD Handle
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Disable the SD device interrupt.
+ * @param __HANDLE__ SD Handle
+ * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified SD flag is set or not.
+ * @param __HANDLE__ SD Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval The new state of SD FLAG (SET or RESET).
+ */
+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Clear the SD's pending flags.
+ * @param __HANDLE__ SD Handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval None
+ */
+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Check whether the specified SD interrupt has occurred or not.
+ * @param __HANDLE__ SD Handle
+ * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval The new state of SD IT (SET or RESET).
+ */
+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Clear the SD's interrupt pending bits.
+ * @param __HANDLE__ SD Handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SD_Exported_Functions SD Exported Functions
+ * @{
+ */
+
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group4 SD card related functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
+ * @{
+ */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
+ * @{
+ */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_SD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,851 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sdram.c
+ * @author MCD Application Team
+ * @brief SDRAM HAL module driver.
+ * This file provides a generic firmware to drive SDRAM memories mounted
+ * as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control SDRAM memories. It uses the FMC layer functions to interface
+ with SDRAM devices.
+ The following sequence should be followed to configure the FMC to interface
+ with SDRAM memories:
+
+ (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
+ SDRAM_HandleTypeDef hdsram
+
+ (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
+ values of the structure member.
+
+ (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
+ base register instance for NOR or SDRAM device
+
+ (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
+ FMC_SDRAM_TimingTypeDef Timing;
+ and fill its fields with the allowed values of the structure member.
+
+ (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
+ performs the following sequence:
+
+ (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
+ (##) Control register configuration using the FMC SDRAM interface function
+ FMC_SDRAM_Init()
+ (##) Timing register configuration using the FMC SDRAM interface function
+ FMC_SDRAM_Timing_Init()
+ (##) Program the SDRAM external device by applying its initialization sequence
+ according to the device plugged in your hardware. This step is mandatory
+ for accessing the SDRAM device.
+
+ (#) At this stage you can perform read/write accesses from/to the memory connected
+ to the SDRAM Bank. You can perform either polling or DMA transfer using the
+ following APIs:
+ (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
+ (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
+
+ (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
+ HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
+ the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
+ device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
+ structure.
+
+ (#) You can continuously monitor the SDRAM device HAL state by calling the function
+ HAL_SDRAM_GetState()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SDRAM SDRAM
+ * @brief SDRAM driver modules
+ * @{
+ */
+#ifdef HAL_SDRAM_MODULE_ENABLED
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
+ * @{
+ */
+
+/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SDRAM Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the SDRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Performs the SDRAM device initialization sequence.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param Timing Pointer to SDRAM control timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
+{
+ /* Check the SDRAM handle parameter */
+ if(hsdram == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsdram->State == HAL_SDRAM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsdram->Lock = HAL_UNLOCKED;
+ /* Initialize the low level hardware (MSP) */
+ HAL_SDRAM_MspInit(hsdram);
+ }
+
+ /* Initialize the SDRAM controller state */
+ hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+ /* Initialize SDRAM control Interface */
+ FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
+
+ /* Initialize SDRAM timing Interface */
+ FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
+
+ /* Update the SDRAM controller state */
+ hsdram->State = HAL_SDRAM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform the SDRAM device initialization sequence.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
+{
+ /* Initialize the low level hardware (MSP) */
+ HAL_SDRAM_MspDeInit(hsdram);
+
+ /* Configure the SDRAM registers with their reset values */
+ FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
+
+ /* Reset the SDRAM controller state */
+ hsdram->State = HAL_SDRAM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsdram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SDRAM MSP Init.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @retval None
+ */
+__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdram);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_SDRAM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SDRAM MSP DeInit.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @retval None
+ */
+__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdram);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_SDRAM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles SDRAM refresh error interrupt request.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @retval HAL status
+*/
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
+{
+ /* Check SDRAM interrupt Rising edge flag */
+ if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
+ {
+ /* SDRAM refresh error interrupt callback */
+ HAL_SDRAM_RefreshErrorCallback(hsdram);
+
+ /* Clear SDRAM refresh error interrupt pending bit */
+ __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
+ }
+}
+
+/**
+ * @brief SDRAM Refresh error callback.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @retval None
+ */
+__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsdram);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SDRAM Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the SDRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads 8-bit data buffer from the SDRAM memory.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsdram);
+
+ /* Check the SDRAM controller state */
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read data from source */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
+ pDstBuffer++;
+ pSdramAddress++;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsdram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 8-bit data buffer to SDRAM memory.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
+ uint32_t tmp = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hsdram);
+
+ /* Check the SDRAM controller state */
+ tmp = hsdram->State;
+
+ if(tmp == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write data to memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
+ pSrcBuffer++;
+ pSdramAddress++;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsdram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 16-bit data buffer from the SDRAM memory.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsdram);
+
+ /* Check the SDRAM controller state */
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read data from source */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
+ pDstBuffer++;
+ pSdramAddress++;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsdram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 16-bit data buffer to SDRAM memory.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
+ uint32_t tmp = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hsdram);
+
+ /* Check the SDRAM controller state */
+ tmp = hsdram->State;
+
+ if(tmp == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write data to memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
+ pSrcBuffer++;
+ pSdramAddress++;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsdram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 32-bit data buffer from the SDRAM memory.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsdram);
+
+ /* Check the SDRAM controller state */
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read data from source */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
+ pDstBuffer++;
+ pSdramAddress++;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsdram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 32-bit data buffer to SDRAM memory.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
+ uint32_t tmp = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hsdram);
+
+ /* Check the SDRAM controller state */
+ tmp = hsdram->State;
+
+ if(tmp == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write data to memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
+ pSrcBuffer++;
+ pSdramAddress++;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsdram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a Words data from the SDRAM memory using DMA transfer.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ uint32_t tmp = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hsdram);
+
+ /* Check the SDRAM controller state */
+ tmp = hsdram->State;
+
+ if(tmp == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure DMA user callbacks */
+ hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+ hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsdram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ uint32_t tmp = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hsdram);
+
+ /* Check the SDRAM controller state */
+ tmp = hsdram->State;
+
+ if(tmp == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure DMA user callbacks */
+ hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+ hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsdram);
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup SDRAM_Exported_Functions_Group3 Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SDRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the SDRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically SDRAM write protection.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
+{
+ /* Check the SDRAM controller state */
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the SDRAM state */
+ hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+ /* Enable write protection */
+ FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
+
+ /* Update the SDRAM state */
+ hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically SDRAM write protection.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
+{
+ /* Check the SDRAM controller state */
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the SDRAM state */
+ hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+ /* Disable write protection */
+ FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
+
+ /* Update the SDRAM state */
+ hsdram->State = HAL_SDRAM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sends Command to the SDRAM bank.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param Command SDRAM command structure
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
+{
+ /* Check the SDRAM controller state */
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the SDRAM state */
+ hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+ /* Send SDRAM command */
+ FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
+
+ /* Update the SDRAM controller state */
+ if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
+ {
+ hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
+ }
+ else
+ {
+ hsdram->State = HAL_SDRAM_STATE_READY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Programs the SDRAM Memory Refresh rate.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param RefreshRate The SDRAM refresh rate value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
+{
+ /* Check the SDRAM controller state */
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the SDRAM state */
+ hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+ /* Program the refresh rate */
+ FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
+
+ /* Update the SDRAM state */
+ hsdram->State = HAL_SDRAM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @param AutoRefreshNumber The SDRAM auto Refresh number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
+{
+ /* Check the SDRAM controller state */
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the SDRAM state */
+ hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+ /* Set the Auto-Refresh number */
+ FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
+
+ /* Update the SDRAM state */
+ hsdram->State = HAL_SDRAM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the SDRAM memory current mode.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @retval The SDRAM memory mode.
+ */
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
+{
+ /* Return the SDRAM memory current mode */
+ return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SDRAM_Exported_Functions_Group4 State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SDRAM State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the SDRAM controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the SDRAM state.
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
+ * @retval HAL state
+ */
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
+{
+ return hsdram->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,195 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sdram.h
+ * @author MCD Application Team
+ * @brief Header file of SDRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SDRAM_H
+#define __STM32F4xx_HAL_SDRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_fmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SDRAM
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL SDRAM State structure definition
+ */
+typedef enum
+{
+ HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */
+ HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */
+ HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */
+ HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */
+ HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */
+ HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */
+
+}HAL_SDRAM_StateTypeDef;
+
+/**
+ * @brief SDRAM handle Structure definition
+ */
+typedef struct
+{
+ FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
+
+ __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
+
+ HAL_LockTypeDef Lock; /*!< SDRAM locking object */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+}SDRAM_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
+ * @{
+ */
+
+/** @brief Reset SDRAM handle state
+ * @param __HANDLE__ specifies the SDRAM handle.
+ * @retval None
+ */
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
+ * @{
+ */
+
+/** @addtogroup SDRAM_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization/de-initialization functions *********************************/
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
+
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup SDRAM_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+/**
+ * @}
+ */
+
+/** @addtogroup SDRAM_Exported_Functions_Group3
+ * @{
+ */
+/* SDRAM Control functions *****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
+/**
+ * @}
+ */
+
+/** @addtogroup SDRAM_Exported_Functions_Group4
+ * @{
+ */
+/* SDRAM State functions ********************************************************/
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SDRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1909 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_smartcard.c
+ * @author MCD Application Team
+ * @brief SMARTCARD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the SMARTCARD peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMARTCARD HAL driver can be used as follows:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure.
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+ (##) Enable the USARTx interface clock.
+ (##) SMARTCARD pins configuration:
+ (+++) Enable the clock for the SMARTCARD GPIOs.
+ (+++) Configure these SMARTCARD pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+ and HAL_SMARTCARD_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+ and HAL_SMARTCARD_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+
+ (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
+ flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
+
+ (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+ (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+
+ *** SMARTCARD HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARD SMARTCARD
+ * @brief HAL USART SMARTCARD module driver
+ * @{
+ */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+ * @{
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in Smartcard mode.
+ [..]
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard.
+ [..]
+ The USART can provide a clock to the smartcard through the SCLK output.
+ In smartcard mode, SCLK is not associated to the communication but is simply derived
+ from the internal peripheral input clock through a 5-bit prescaler.
+ [..]
+ (+) For the Smartcard mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length => Should be 9 bits (8 bits + parity)
+ (++) Stop Bit
+ (++) Parity: => Should be enabled
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+ (++) Prescaler
+ (++) GuardTime
+ (++) NACKState: The Smartcard NACK state
+
+ (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
+ (++) Word Length = 9 Bits
+ (++) 1.5 Stop Bit
+ (++) Even parity
+ (++) BaudRate = 12096 baud
+ (++) Tx and Rx enabled
+ [..]
+ Please refer to the ISO 7816-3 specification for more details.
+
+ [..]
+ (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended
+ to use 1.5 stop bits for both transmitting and receiving to avoid switching
+ between the two configurations.
+ [..]
+ The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
+ procedure (details for the procedure are available in reference manual (RM0329)).
+
+@endverbatim
+
+ The SMARTCARD frame format is given in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | SMARTCARD frame |
+ |---------------------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
+ * @{
+ */
+
+/**
+ * @brief Initializes the SmartCard mode according to the specified
+ * parameters in the SMARTCARD_InitTypeDef and create the associated handle .
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
+ assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
+
+ if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsc->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_SMARTCARD_MspInit(hsc);
+ }
+
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Set the Prescaler */
+ MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
+
+ /* Set the Guard Time */
+ MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8U));
+
+ /* Set the Smartcard Communication parameters */
+ SMARTCARD_SetConfig(hsc);
+
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the SMARTCARD Framing Error Interrupt */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the Peripheral */
+ __HAL_SMARTCARD_ENABLE(hsc);
+
+ /* Configure the Smartcard NACK state */
+ MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
+
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+ hsc->Instance->CR3 |= (USART_CR3_SCEN);
+
+ /* Initialize the SMARTCARD state*/
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->gState= HAL_SMARTCARD_STATE_READY;
+ hsc->RxState= HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the USART SmartCard peripheral
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
+
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_SMARTCARD_DISABLE(hsc);
+
+ /* DeInit the low level hardware */
+ HAL_SMARTCARD_MspDeInit(hsc);
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->gState = HAL_SMARTCARD_STATE_RESET;
+ hsc->RxState = HAL_SMARTCARD_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SMARTCARD MSP Init
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMARTCARD MSP DeInit
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+ [..]
+ (#) Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard.
+ (#) The USART should be configured as:
+ (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_SMARTCARD_Transmit()
+ (++) HAL_SMARTCARD_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_SMARTCARD_Transmit_IT()
+ (++) HAL_SMARTCARD_Receive_IT()
+ (++) HAL_SMARTCARD_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_SMARTCARD_Transmit_DMA()
+ (++) HAL_SMARTCARD_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_SMARTCARD_TxCpltCallback()
+ (++) HAL_SMARTCARD_RxCpltCallback()
+ (++) HAL_SMARTCARD_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ if(hsc->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
+ hsc->TxXferSize = Size;
+ hsc->TxXferCount = Size;
+ while(hsc->TxXferCount > 0U)
+ {
+ hsc->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pData;
+ hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ pData +=1U;
+ }
+
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
+ hsc->RxXferSize = Size;
+ hsc->RxXferCount = Size;
+
+ /* Check the remain data to be received */
+ while(hsc->RxXferCount > 0U)
+ {
+ hsc->RxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+/* MBED */
+ *pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
+/* MBED */
+ pData +=1U;
+ }
+
+ /* At end of Rx process, restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in non blocking mode
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if(hsc->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->pTxBuffPtr = pData;
+ hsc->TxXferSize = Size;
+ hsc->TxXferCount = Size;
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the SMARTCARD Transmit data register empty Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non blocking mode
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->pRxBuffPtr = pData;
+ hsc->RxXferSize = Size;
+ hsc->RxXferCount = Size;
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in non blocking mode
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check that a Tx process is not already ongoing */
+ if(hsc->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->pTxBuffPtr = pData;
+ hsc->TxXferSize = Size;
+ hsc->TxXferCount = Size;
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the SMARTCARD transmit DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD CR3 register */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non blocking mode
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check that a Rx process is not already ongoing */
+ if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->pRxBuffPtr = pData;
+ hsc->RxXferSize = Size;
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+ __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD CR3 register */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsc->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsc->hdmatx);
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsc->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsc->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hsc->TxXferCount = 0x00U;
+ hsc->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Restore hsc->RxState and hsc->gState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsc->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsc->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hsc->TxXferCount = 0x00U;
+
+ /* Restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsc->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsc->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hsc->RxXferCount = 0x00U;
+
+ /* Restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint32_t AbortCplt = 0x01U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hsc->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+ }
+ else
+ {
+ hsc->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+ }
+ else
+ {
+ hsc->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at SMARTCARD level */
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hsc->hdmatx != NULL)
+ {
+ /* SMARTCARD Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
+ {
+ hsc->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hsc->hdmarx != NULL)
+ {
+ /* SMARTCARD Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+ {
+ hsc->hdmarx->XferAbortCallback = NULL;
+ AbortCplt = 0x01U;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if(AbortCplt == 0x01U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hsc->TxXferCount = 0x00U;
+ hsc->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Restore hsc->gState and hsc->RxState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsc);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsc->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */
+ hsc->hdmatx->XferAbortCallback(hsc->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsc->TxXferCount = 0x00U;
+
+ /* Restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsc->TxXferCount = 0x00U;
+
+ /* Restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */
+ hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsc->RxXferCount = 0x00U;
+
+ /* Restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsc->RxXferCount = 0x00U;
+
+ /* Restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles SMARTCARD interrupt request.
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval None
+ */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint32_t isrflags = READ_REG(hsc->Instance->SR);
+ uint32_t cr1its = READ_REG(hsc->Instance->CR1);
+ uint32_t cr3its = READ_REG(hsc->Instance->CR3);
+ uint32_t dmarequest = 0x00U;
+ uint32_t errorflags = 0x00U;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+ if(errorflags == RESET)
+ {
+ /* SMARTCARD in mode Receiver -------------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsc);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ {
+ /* SMARTCARD parity error interrupt occurred ---------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ }
+
+ /* SMARTCARD frame error interrupt occurred ----------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ }
+
+ /* SMARTCARD noise error interrupt occurred ----------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ }
+
+ /* SMARTCARD Over-Run interrupt occurred -------------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ }
+ /* Call the Error call Back in case of Errors */
+ if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ /* SMARTCARD in mode Receiver -----------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsc);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
+ if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ SMARTCARD_EndRxTransfer(hsc);
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsc);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsc);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsc);
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ }
+ }
+ return;
+ } /* End if some error occurs */
+
+ /* SMARTCARD in mode Transmitter -------------------------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ SMARTCARD_Transmit_IT(hsc);
+ return;
+ }
+
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ {
+ SMARTCARD_EndTransmit_IT(hsc);
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMARTCARD error callbacks
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsc SMARTCARD handle.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Transmit Complete callback.
+ * @param hsc SMARTCARD handle.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort ReceiveComplete callback.
+ * @param hsc SMARTCARD handle.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SmartCard.
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
+ (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the SMARTCARD state
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval HAL state
+ */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
+ temp1 = hsc->gState;
+ temp2 = hsc->RxState;
+
+ return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the SMARTCARD error code
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD.
+ * @retval SMARTCARD Error Code
+ */
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
+{
+ return hsc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA SMARTCARD transmit process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->RxXferCount = 0U;
+
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_RxCpltCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ uint32_t dmarequest = 0x00U;
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsc->RxXferCount = 0U;
+ hsc->TxXferCount = 0U;
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ /* Stop SMARTCARD DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT);
+ if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
+ {
+ SMARTCARD_EndTxTransfer(hsc);
+ }
+
+ /* Stop SMARTCARD DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
+ if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
+ {
+ SMARTCARD_EndRxTransfer(hsc);
+ }
+
+ HAL_SMARTCARD_ErrorCallback(hsc);
+}
+
+/**
+ * @brief This function handles SMARTCARD Communication Timeout.
+ * @param hsc SMARTCARD handle
+ * @param Flag specifies the SMARTCARD flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ {
+ /* Disable TXE and RXNE interrupts for the interrupt process */
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
+
+ hsc->gState= HAL_SMARTCARD_STATE_READY;
+ hsc->RxState= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+ * @param hsc SMARTCARD handle.
+ * @retval None
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* At end of Tx process, restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
+ * @param hsc SMARTCARD handle.
+ * @retval None
+ */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* At end of Rx process, restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Send an amount of data in non blocking mode
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint16_t* tmp;
+
+ /* Check that a Tx process is ongoing */
+ if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ tmp = (uint16_t*) hsc->pTxBuffPtr;
+ hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ hsc->pTxBuffPtr += 1U;
+
+ if(--hsc->TxXferCount == 0U)
+ {
+ /* Disable the SMARTCARD Transmit data register empty Interrupt */
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hsmartcard pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TCIE);
+
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Tx process is ended, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non blocking mode
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint16_t* tmp;
+
+ /* Check that a Rx process is ongoing */
+ if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ tmp = (uint16_t*) hsc->pRxBuffPtr;
+ *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
+ hsc->pRxBuffPtr += 1U;
+
+ if(--hsc->RxXferCount == 0U)
+ {
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_RxCpltCallback(hsc);
+
+ return HAL_OK;
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsc->RxXferCount = 0x00U;
+ hsc->TxXferCount = 0x00U;
+
+ HAL_SMARTCARD_ErrorCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsc->hdmarx != NULL)
+ {
+ if(hsc->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsc->TxXferCount = 0x00U;
+ hsc->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Restore hsc->gState and hsc->RxState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsc->hdmatx != NULL)
+ {
+ if(hsc->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsc->TxXferCount = 0x00U;
+ hsc->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Restore hsc->gState and hsc->RxState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->TxXferCount = 0x00U;
+
+ /* Restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->RxXferCount = 0x00U;
+
+ /* Restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+}
+
+/**
+ * @brief Configure the SMARTCARD peripheral
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint32_t tmpreg = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
+ assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
+ assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
+ assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
+ assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
+ assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
+ assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
+
+ /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
+ receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /*---------------------------- USART CR2 Configuration ---------------------*/
+ tmpreg = hsc->Instance->CR2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL));
+ /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
+ /* Set CPOL bit according to hsc->Init.CLKPolarity value */
+ /* Set CPHA bit according to hsc->Init.CLKPhase value */
+ /* Set LBCL bit according to hsc->Init.CLKLastBit value */
+ /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
+ tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity |
+ hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
+ /* Write to USART CR2 */
+ WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
+
+ tmpreg = hsc->Instance->CR2;
+
+ /* Clear STOP[13:12] bits */
+ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+
+ /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
+ tmpreg |= (uint32_t)(hsc->Init.StopBits);
+
+ /* Write to USART CR2 */
+ WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = hsc->Instance->CR1;
+
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE));
+
+ /* Configure the SMARTCARD Word Length, Parity and mode:
+ Set the M bits according to hsc->Init.WordLength value
+ Set PCE and PS bits according to hsc->Init.Parity value
+ Set TE and RE bits according to hsc->Init.Mode value */
+ tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
+
+ /* Write to USART CR1 */
+ WRITE_REG(hsc->Instance->CR1, (uint32_t)tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Clear CTSE and RTSE bits */
+ CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+#if defined(USART6)
+ if((hsc->Instance == USART1) || (hsc->Instance == USART6))
+ {
+ hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
+ }
+#else
+ if(hsc->Instance == USART1)
+ {
+ hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
+ }
+#endif /* USART6 */
+ else
+ {
+ hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,685 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_smartcard.h
+ * @author MCD Application Team
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SMARTCARD_H
+#define __STM32F4xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
+
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref SMARTCARD_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref SMARTCARD_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref SMARTCARD_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits).*/
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref SMARTCARD_Mode */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+ uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
+ to provide the smartcard clock. The value given in the register (5 significant bits)
+ is multiplied by 2 to give the division factor of the source clock frequency.
+ This parameter can be a value of @ref SMARTCARD_Prescaler */
+
+ uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
+
+ uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
+ This parameter can be a value of @ref SMARTCARD_NACK_State */
+}SMARTCARD_InitTypeDef;
+
+/**
+ * @brief HAL SMARTCARD State structures definition
+ * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains SMARTCARD state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef enum
+{
+ HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ Value is allowed for gState only */
+ HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
+ Value is allowed for gState only */
+}HAL_SMARTCARD_StateTypeDef;
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* SmartCard Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* SmartCard Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_SMARTCARD_StateTypeDef gState; /* SmartCard state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO HAL_SMARTCARD_StateTypeDef RxState; /* SmartCard state information related to Rx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /* SmartCard Error code */
+
+}SMARTCARD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
+ * @{
+ */
+/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
+ * @brief SMARTCARD Error Code
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+ * @{
+ */
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Mode
+ * @{
+ */
+#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW 0x00000000U
+#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+ * @{
+ */
+#define SMARTCARD_PHASE_1EDGE 0x00000000U
+#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+ * @{
+ */
+#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
+#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
+ * @{
+ */
+#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
+ * @{
+ */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_Flags SMARTCARD Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define SMARTCARD_FLAG_TXE 0x00000080U
+#define SMARTCARD_FLAG_TC 0x00000040U
+#define SMARTCARD_FLAG_RXNE 0x00000020U
+#define SMARTCARD_FLAG_IDLE 0x00000010U
+#define SMARTCARD_FLAG_ORE 0x00000008U
+#define SMARTCARD_FLAG_NE 0x00000004U
+#define SMARTCARD_FLAG_FE 0x00000002U
+#define SMARTCARD_FLAG_PE 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR3 register
+ * @{
+ */
+#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMARTCARD handle gstate & RxState
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ } while(0U)
+
+/** @brief Flushs the Smartcard DR register
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Checks whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
+ * @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
+ * @arg SMARTCARD_FLAG_ORE: Overrun Error flag
+ * @arg SMARTCARD_FLAG_NE: Noise Error flag
+ * @arg SMARTCARD_FLAG_FE: Framing Error flag
+ * @arg SMARTCARD_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified Smartcard pending flags.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
+ * error) flags are cleared by software sequence: a read operation to
+ * USART_SR register followed by a read operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Clear the SMARTCARD PE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * SMARTCARD peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0U)
+
+/** @brief Clear the SMARTCARD FE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * SMARTCARD peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the SMARTCARD NE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * SMARTCARD peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the SMARTCARD ORE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * SMARTCARD peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the SMARTCARD IDLE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * SMARTCARD peripheral.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enables or disables the specified SmartCard interrupts.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+
+/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__ specifies the SmartCard Handle.
+ * @param __IT__ specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
+
+/** @brief Macro to enable the SMARTCARD's one bit sample method
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Macro to disable the SMARTCARD's one bit sample method
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Macros to enable or disable the SmartCard DMA request.
+ * @param __HANDLE__ specifies the SmartCard Handle.
+ * @param __REQUEST__ specifies the SmartCard DMA request.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
+ * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+ */
+#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
+#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
+
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+
+/** @brief SMARTCARD interruptions flag mask
+ *
+ */
+#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR3_EIE )
+
+#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
+#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+/* SMARTCARD BRR = mantissa + overflow + fraction
+ = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
+#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
+ (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+ (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
+
+#define SMARTCARD_CR1_REG_INDEX 1U
+#define SMARTCARD_CR3_REG_INDEX 3U
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
+ ((PARITY) == SMARTCARD_PARITY_ODD))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
+ ((NACK) == SMARTCARD_NACK_DISABLE))
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1296 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spdifrx.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the SPDIFRX audio interface:
+ * + Initialization and Configuration
+ * + Data transfers functions
+ * + DMA transfers management
+ * + Interrupts and flags management
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The SPDIFRX HAL driver can be used as follow:
+
+ (#) Declare SPDIFRX_HandleTypeDef handle structure.
+ (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
+ (##) Enable the SPDIFRX interface clock.
+ (##) SPDIFRX pins configuration:
+ (+++) Enable the clock for the SPDIFRX GPIOs.
+ (+++) Configure these SPDIFRX pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
+ (+++) Configure the SPDIFRX interrupt priority.
+ (+++) Enable the NVIC SPDIFRX IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
+ (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
+ (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
+ (+++) Configure the DMA Channel.
+ (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA CtrlRx/DataRx channel.
+
+ (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
+ using HAL_SPDIFRX_Init() function.
+
+ -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
+ __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
+ -@- Make sure that ck_spdif clock is configured.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode for reception operation (for debug purpose) ***
+ ================================================================
+ [..]
+ (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
+ (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
+
+ *** Interrupt mode for reception operation ***
+ =========================================
+ [..]
+ (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
+ (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
+
+ *** DMA mode for reception operation ***
+ ========================================
+ [..]
+ (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
+ (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
+ (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
+
+ *** SPDIFRX HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in SPDIFRX HAL driver.
+ (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
+ (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
+ (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
+ (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
+ (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
+ (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
+
+ [..]
+ (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup SPDIFRX SPDIFRX
+ * @brief SPDIFRX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+
+#if defined(STM32F446xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SPDIFRX_TIMEOUT_VALUE 0xFFFF
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @addtogroup SPDIFRX_Private_Functions
+ * @{
+ */
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+/**
+ * @}
+ */
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions
+ * @{
+ */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPDIFRX peripheral:
+
+ (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
+ the selected configuration:
+ (++) Input Selection (IN0, IN1,...)
+ (++) Maximum allowed re-tries during synchronization phase
+ (++) Wait for activity on SPDIF selected input
+ (++) Channel status selection (from channel A or B)
+ (++) Data format (LSB, MSB, ...)
+ (++) Stereo mode
+ (++) User bits masking (PT,C,U,V,...)
+
+ (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
+ of the selected SPDIFRXx peripheral.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SPDIFRX according to the specified parameters
+ * in the SPDIFRX_InitTypeDef and create the associated handle.
+ * @param hspdif SPDIFRX handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the SPDIFRX handle allocation */
+ if(hspdif == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the SPDIFRX parameters */
+ assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
+ assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
+ assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
+ assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
+ assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
+ assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
+ assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
+ assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
+ assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
+ assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
+
+ if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspdif->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_SPDIFRX_MspInit(hspdif);
+ }
+
+ /* SPDIFRX peripheral state is BUSY*/
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Disable SPDIFRX interface (IDLE State) */
+ __HAL_SPDIFRX_IDLE(hspdif);
+
+ /* Reset the old SPDIFRX CR configuration */
+ tmpreg = hspdif->Instance->CR;
+
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |
+ SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
+ SPDIFRX_CR_INSEL);
+
+ /* Sets the new configuration of the SPDIFRX peripheral */
+ tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
+ hspdif->Init.InputSelection |
+ hspdif->Init.Retries |
+ hspdif->Init.WaitForActivity |
+ hspdif->Init.ChannelSelection |
+ hspdif->Init.DataFormat |
+ hspdif->Init.PreambleTypeMask |
+ hspdif->Init.ChannelStatusMask |
+ hspdif->Init.ValidityBitMask |
+ hspdif->Init.ParityErrorMask);
+
+ hspdif->Instance->CR = tmpreg;
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* SPDIFRX peripheral state is READY*/
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the SPDIFRX peripheral
+ * @param hspdif SPDIFRX handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Check the SPDIFRX handle allocation */
+ if(hspdif == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
+
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Disable SPDIFRX interface (IDLE state) */
+ __HAL_SPDIFRX_IDLE(hspdif);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPDIFRX_MspDeInit(hspdif);
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* SPDIFRX peripheral state is RESET*/
+ hspdif->State = HAL_SPDIFRX_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SPDIFRX MSP Init
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspdif);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPDIFRX MSP DeInit
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspdif);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Sets the SPDIFRX dtat format according to the specified parameters
+ * in the SPDIFRX_InitTypeDef.
+ * @param hspdif SPDIFRX handle
+ * @param sDataFormat SPDIFRX data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the SPDIFRX handle allocation */
+ if(hspdif == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the SPDIFRX parameters */
+ assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
+ assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
+ assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
+ assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
+ assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
+ assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
+
+ /* Reset the old SPDIFRX CR configuration */
+ tmpreg = hspdif->Instance->CR;
+
+ if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
+ (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
+ ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
+ {
+ return HAL_ERROR;
+ }
+
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
+
+ /* Sets the new configuration of the SPDIFRX peripheral */
+ tmpreg |= ((uint16_t) sDataFormat.StereoMode |
+ sDataFormat.DataFormat |
+ sDataFormat.PreambleTypeMask |
+ sDataFormat.ChannelStatusMask |
+ sDataFormat.ValidityBitMask |
+ sDataFormat.ParityErrorMask);
+
+ hspdif->Instance->CR = tmpreg;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+===============================================================================
+ ##### IO operation functions #####
+===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPDIFRX data
+ transfers.
+
+ (#) There is two mode of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer start-up.
+ The end of the data processing will be indicated through the
+ dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_SPDIFRX_ReceiveDataFlow()
+ (++) HAL_SPDIFRX_ReceiveControlFlow()
+ (+@) Do not use blocking mode to receive both control and data flow at the same time.
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_SPDIFRX_ReceiveControlFlow_IT()
+ (++) HAL_SPDIFRX_ReceiveDataFlow_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()
+ (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_SPDIFRX_RxCpltCallback()
+ (++) HAL_SPDIFRX_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Receives an amount of data (Data Flow) in blocking mode.
+ * @param hspdif pointer to SPDIFRX_HandleTypeDef structure that contains
+ * the configuration information for SPDIFRX module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Start synchronisation */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+
+ /* Receive data flow */
+ while(Size > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*pData++) = hspdif->Instance->DR;
+ Size--;
+ }
+
+ /* SPDIFRX ready */
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data (Control Flow) in blocking mode.
+ * @param hspdif pointer to a SPDIFRX_HandleTypeDef structure that contains
+ * the configuration information for SPDIFRX module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+
+ /* Receive control flow */
+ while(Size > 0)
+ {
+ /* Wait until CSRNE flag is set */
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*pData++) = hspdif->Instance->CSR;
+ Size--;
+ }
+
+ /* SPDIFRX ready */
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
+ * @param hspdif SPDIFRX handle
+ * @param pData a 32-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be received .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->pRxBuffPtr = pData;
+ hspdif->RxXferSize = Size;
+ hspdif->RxXferCount = Size;
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* Check if a receive process is ongoing or not */
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
+
+ /* Enable the SPDIFRX PE Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+
+ /* Enable the SPDIFRX OVR Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ /* Enable the SPDIFRX RXNE interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ do
+ {
+ if (count-- == 0U)
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Control Flow) with Interrupt
+ * @param hspdif SPDIFRX handle
+ * @param pData a 32-bit pointer to the Receive data buffer.
+ * @param Size number of data sample (Control Flow) to be received :
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->pCsBuffPtr = pData;
+ hspdif->CsXferSize = Size;
+ hspdif->CsXferCount = Size;
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+ /* Check if a receive process is ongoing or not */
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
+
+ /* Enable the SPDIFRX PE Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+
+ /* Enable the SPDIFRX OVR Error Interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ /* Enable the SPDIFRX CSRNE interrupt */
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ do
+ {
+ if (count-- == 0U)
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Data Flow) mode with DMA
+ * @param hspdif SPDIFRX handle
+ * @param pData a 32-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be received :
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ {
+ hspdif->pRxBuffPtr = pData;
+ hspdif->RxXferSize = Size;
+ hspdif->RxXferCount = Size;
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
+
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */
+ hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
+
+ /* Set the SPDIFRX Rx DMA transfer complete callback */
+ hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
+
+ /* Enable the DMA request */
+ HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
+
+ /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
+ hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ do
+ {
+ if (count-- == 0U)
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Control Flow) with DMA
+ * @param hspdif SPDIFRX handle
+ * @param pData a 32-bit pointer to the Receive data buffer.
+ * @param Size number of data (Control Flow) sample to be received :
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ {
+ hspdif->pCsBuffPtr = pData;
+ hspdif->CsXferSize = Size;
+ hspdif->CsXferCount = Size;
+
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
+
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */
+ hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
+
+ /* Set the SPDIFRX Rx DMA transfer complete callback */
+ hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
+
+ /* Set the DMA error callback */
+ hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
+
+ /* Enable the DMA request */
+ HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
+
+ /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
+ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
+
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+ {
+ /* Start synchronization */
+ __HAL_SPDIFRX_SYNC(hspdif);
+
+ /* Wait until SYNCD flag is set */
+ do
+ {
+ if (count-- == 0U)
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+ /* Start reception */
+ __HAL_SPDIFRX_RCV(hspdif);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief stop the audio stream receive from the Media.
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
+ /* Disable the SPDIFRX DMA requests */
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
+
+ /* Disable the SPDIFRX DMA channel */
+ __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
+ __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
+
+ /* Disable SPDIFRX peripheral */
+ __HAL_SPDIFRX_IDLE(hspdif);
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles SPDIFRX interrupt request.
+ * @param hspdif SPDIFRX handle
+ * @retval HAL status
+ */
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
+ SPDIFRX_ReceiveDataFlow_IT(hspdif);
+ }
+
+ /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
+ SPDIFRX_ReceiveControlFlow_IT(hspdif);
+ }
+
+ /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
+
+ /* Change the SPDIFRX error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
+
+ /* the transfer is not stopped */
+ HAL_SPDIFRX_ErrorCallback(hspdif);
+ }
+
+ /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
+ {
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
+
+ /* Change the SPDIFRX error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
+
+ /* the transfer is not stopped */
+ HAL_SPDIFRX_ErrorCallback(hspdif);
+ }
+}
+
+/**
+ * @brief Rx Transfer (Data flow) half completed callbacks
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspdif);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer (Data flow) completed callbacks
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspdif);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx (Control flow) Transfer half completed callbacks
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspdif);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer (Control flow) completed callbacks
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspdif);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPDIFRX error callbacks
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspdif);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+===============================================================================
+ ##### Peripheral State and Errors functions #####
+===============================================================================
+[..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPDIFRX state
+ * @param hspdif SPDIFRX handle
+ * @retval HAL state
+ */
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)
+{
+ return hspdif->State;
+}
+
+/**
+ * @brief Return the SPDIFRX error code
+ * @param hspdif SPDIFRX handle
+ * @retval SPDIFRX Error Code
+ */
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
+{
+ return hspdif->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA SPDIFRX receive process (Data flow) complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx DMA Request */
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+ hspdif->RxXferCount = 0U;
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+ HAL_SPDIFRX_RxCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX receive process (Data flow) half complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX receive process (Control flow) complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Cb DMA Request */
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
+ hspdif->CsXferCount = 0U;
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+ HAL_SPDIFRX_CxCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX receive process (Control flow) half complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
+}
+
+/**
+ * @brief DMA SPDIFRX communication error callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx and Cb DMA Request */
+ hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
+ hspdif->RxXferCount = 0U;
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
+ HAL_SPDIFRX_ErrorCallback(hspdif);
+}
+
+/**
+ * @brief Receive an amount of data (Data Flow) with Interrupt
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Receive data */
+ (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
+ hspdif->RxXferCount--;
+
+ if(hspdif->RxXferCount == 0U)
+ {
+ /* Disable RXNE/PE and OVR interrupts */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ HAL_SPDIFRX_RxCpltCallback(hspdif);
+ }
+}
+
+/**
+ * @brief Receive an amount of data (Control Flow) with Interrupt
+ * @param hspdif SPDIFRX handle
+ * @retval None
+ */
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
+{
+ /* Receive data */
+ (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
+ hspdif->CsXferCount--;
+
+ if(hspdif->CsXferCount == 0U)
+ {
+ /* Disable CSRNE interrupt */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ HAL_SPDIFRX_CxCpltCallback(hspdif);
+ }
+}
+
+/**
+ * @brief This function handles SPDIFRX Communication Timeout.
+ * @param hspdif SPDIFRX handle
+ * @param Flag Flag checked
+ * @param Status Value of the flag expected
+ * @param Timeout Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,553 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spdifrx.h
+ * @author MCD Application Team
+ * @brief Header file of SPDIFRX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SPDIFRX_H
+#define __STM32F4xx_HAL_SPDIFRX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F446xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPDIFRX
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPDIFRX Init structure definition
+ */
+typedef struct
+{
+ uint32_t InputSelection; /*!< Specifies the SPDIF input selection.
+ This parameter can be a value of @ref SPDIFRX_Input_Selection */
+
+ uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
+ This parameter can be a value of @ref SPDIFRX_Max_Retries */
+
+ uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
+ This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
+
+ uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
+ This parameter can be a value of @ref SPDIFRX_Channel_Selection */
+
+ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
+ This parameter can be a value of @ref SPDIFRX_Data_Format */
+
+ uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
+ This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
+
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
+
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_V_Mask */
+
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */
+}SPDIFRX_InitTypeDef;
+
+/**
+ * @brief SPDIFRX SetDataFormat structure definition
+ */
+typedef struct
+{
+ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
+ This parameter can be a value of @ref SPDIFRX_Data_Format */
+
+ uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
+ This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
+
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
+
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_V_Mask */
+
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */
+}SPDIFRX_SetDataFormatTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SPDIFRX_STATE_RESET = 0x00U, /*!< SPDIFRX not yet initialized or disabled */
+ HAL_SPDIFRX_STATE_READY = 0x01U, /*!< SPDIFRX initialized and ready for use */
+ HAL_SPDIFRX_STATE_BUSY = 0x02U, /*!< SPDIFRX internal process is ongoing */
+ HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */
+ HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */
+ HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */
+}HAL_SPDIFRX_StateTypeDef;
+
+/**
+ * @brief SPDIFRX handle Structure definition
+ */
+typedef struct
+{
+ SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
+
+ SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */
+
+ uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
+
+ uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
+
+ __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
+
+ __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */
+
+ __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */
+
+ __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
+
+ __IO uint32_t ErrorCode; /* SPDIFRX Error code */
+}SPDIFRX_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
+ * @{
+ */
+/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
+ * @{
+ */
+#define HAL_SPDIFRX_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SPDIFRX_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
+#define HAL_SPDIFRX_ERROR_OVR 0x00000002U /*!< OVR error */
+#define HAL_SPDIFRX_ERROR_PE 0x00000004U /*!< Parity error */
+#define HAL_SPDIFRX_ERROR_DMA 0x00000008U /*!< DMA transfer error */
+#define HAL_SPDIFRX_ERROR_UNKNOWN 0x00000010U /*!< Unknown Error error */
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
+ * @{
+ */
+#define SPDIFRX_INPUT_IN0 0x00000000U
+#define SPDIFRX_INPUT_IN1 0x00010000U
+#define SPDIFRX_INPUT_IN2 0x00020000U
+#define SPDIFRX_INPUT_IN3 0x00030000U
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
+ * @{
+ */
+#define SPDIFRX_MAXRETRIES_NONE 0x00000000U
+#define SPDIFRX_MAXRETRIES_3 0x00001000U
+#define SPDIFRX_MAXRETRIES_15 0x00002000U
+#define SPDIFRX_MAXRETRIES_63 0x00003000U
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
+ * @{
+ */
+#define SPDIFRX_WAITFORACTIVITY_OFF 0x00000000U
+#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
+* @{
+*/
+#define SPDIFRX_PREAMBLETYPEMASK_OFF 0x00000000U
+#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
+* @{
+*/
+#define SPDIFRX_CHANNELSTATUS_OFF 0x00000000U /* The channel status and user bits are copied into the SPDIF_DR */
+#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
+* @{
+*/
+#define SPDIFRX_VALIDITYMASK_OFF 0x00000000U
+#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
+* @{
+*/
+#define SPDIFRX_PARITYERRORMASK_OFF 0x00000000U
+#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
+ * @{
+ */
+#define SPDIFRX_CHANNEL_A 0x00000000U
+#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
+ * @{
+ */
+#define SPDIFRX_DATAFORMAT_LSB 0x00000000U
+#define SPDIFRX_DATAFORMAT_MSB 0x00000010U
+#define SPDIFRX_DATAFORMAT_32BITS 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
+ * @{
+ */
+#define SPDIFRX_STEREOMODE_DISABLE 0x00000000U
+#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_State SPDIFRX State
+ * @{
+ */
+
+#define SPDIFRX_STATE_IDLE 0xFFFFFFFCU
+#define SPDIFRX_STATE_SYNC 0x00000001U
+#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
+ * @{
+ */
+#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
+#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
+#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
+#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
+#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
+#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
+#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
+/**
+ * @}
+ */
+
+/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
+ * @{
+ */
+#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
+#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
+#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
+#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
+#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
+#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
+#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
+#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
+#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPDIFRX handle state
+ * @param __HANDLE__ SPDIFRX handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
+
+/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
+
+/** @brief Enable the specified SPDIFRX peripheral (SYNC State).
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
+
+
+/** @brief Enable the specified SPDIFRX peripheral (RCV State).
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @retval None
+ */
+#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
+
+/** @brief Enable or disable the specified SPDIFRX interrupts.
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_IT_RXNE
+ * @arg SPDIFRX_IT_CSRNE
+ * @arg SPDIFRX_IT_PERRIE
+ * @arg SPDIFRX_IT_OVRIE
+ * @arg SPDIFRX_IT_SBLKIE
+ * @arg SPDIFRX_IT_SYNCDIE
+ * @arg SPDIFRX_IT_IFEIE
+ * @retval None
+ */
+#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
+
+/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_IT_RXNE
+ * @arg SPDIFRX_IT_CSRNE
+ * @arg SPDIFRX_IT_PERRIE
+ * @arg SPDIFRX_IT_OVRIE
+ * @arg SPDIFRX_IT_SBLKIE
+ * @arg SPDIFRX_IT_SYNCDIE
+ * @arg SPDIFRX_IT_IFEIE
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified SPDIFRX flag is set or not.
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_FLAG_RXNE
+ * @arg SPDIFRX_FLAG_CSRNE
+ * @arg SPDIFRX_FLAG_PERR
+ * @arg SPDIFRX_FLAG_OVR
+ * @arg SPDIFRX_FLAG_SBD
+ * @arg SPDIFRX_FLAG_SYNCD
+ * @arg SPDIFRX_FLAG_FERR
+ * @arg SPDIFRX_FLAG_SERR
+ * @arg SPDIFRX_FLAG_TERR
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg SPDIFRX_FLAG_PERR
+ * @arg SPDIFRX_FLAG_OVR
+ * @arg SPDIFRX_SR_SBD
+ * @arg SPDIFRX_SR_SYNCD
+ * @retval None
+ */
+#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPDIFRX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
+/**
+ * @}
+ */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+/**
+ * @}
+ */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
+ * @{
+ */
+#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
+ ((INPUT) == SPDIFRX_INPUT_IN2) || \
+ ((INPUT) == SPDIFRX_INPUT_IN3) || \
+ ((INPUT) == SPDIFRX_INPUT_IN0))
+#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
+ ((RET) == SPDIFRX_MAXRETRIES_3) || \
+ ((RET) == SPDIFRX_MAXRETRIES_15) || \
+ ((RET) == SPDIFRX_MAXRETRIES_63))
+#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
+ ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
+#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
+ ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
+ ((VAL) == SPDIFRX_VALIDITYMASK_ON))
+#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
+ ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
+#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
+ ((CHANNEL) == SPDIFRX_CHANNEL_B))
+#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
+#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
+ ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
+
+#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
+ ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_SPDIFRX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,3272 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spi.c
+ * @author MCD Application Team
+ * @brief SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
+ (+++) Enable the DMAx clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx stream
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream
+
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SPI_MspInit() API.
+ [..]
+ Circular mode restriction:
+ (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
+ (##) Master 2Lines RxOnly
+ (##) Master 1Line Rx
+ (#) The CRC feature is not managed when the DMA circular mode is enabled
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+ [..]
+ Master Receive mode restriction:
+ (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
+ bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
+ does not initiate a new transfer the following procedure has to be respected:
+ (##) HAL_SPI_DeInit()
+ (##) HAL_SPI_Init()
+
+ @endverbatim
+
+ Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
+ the following tables resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+
+ DataSize = SPI_DATASIZE_8BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
+ +----------------------------------------------------------------------------------------------+
+
+ DataSize = SPI_DATASIZE_16BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
+ +----------------------------------------------------------------------------------------------+
+ [..]
+ (@) The max SPI frequency depend on SPI data size (8bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ (@)
+ (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+/** @defgroup SPI SPI
+ * @brief SPI HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_DEFAULT_TIMEOUT 100U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
+/* MBED */
+static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+/* MBED */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#if (USE_SPI_CRC != 0U)
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPIx peripheral:
+
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Direction
+ (++) Data Size
+ (++) Clock Polarity and Phase
+ (++) NSS Management
+ (++) BaudRate Prescaler
+ (++) FirstBit
+ (++) TIMode
+ (++) CRC Calculation
+ (++) CRC Polynomial if CRC enabled
+
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if(hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ if(hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+ {
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ }
+#if (USE_SPI_CRC != 0U)
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+ if(hspi->State == HAL_SPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
+ Communication speed, First bit and CRC calculation state */
+ WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
+
+ /* Configure : NSS management */
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
+
+#if (USE_SPI_CRC != 0U)
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+ /* Configure : CRC Polynomial */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+ }
+#endif /* USE_SPI_CRC */
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* USE_SPI_CRC */
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De Initialize the SPI peripheral.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if(hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check SPI Instance parameter */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the SPI Peripheral Clock */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspDeInit(hspi);
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SPI MSP.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit should be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize the SPI MSP.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPI
+ data transfers.
+
+ [..] The SPI supports master and slave mode :
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit data in 16 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ {
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ /* Transmit data in 16 Bit mode */
+ while (hspi->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+ {
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
+ {
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
+ pData += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ while (hspi->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+ {
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
+ pData += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+
+ /* Wait until TXE flag */
+/* MBED */
+ if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK)
+/* MBED */
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Check Busy flag */
+ if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ errorcode = HAL_ERROR;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ goto error;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error:
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ /* this is done to handle the CRCNEXT before the latest data */
+ hspi->RxXferCount--;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Configure communication direction: 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Receive data in 8 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ {
+ /* Transfer loop */
+ while(hspi->RxXferCount > 0U)
+ {
+ /* Check the RXNE flag */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+ {
+ /* read the received data */
+ (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR;
+ pData += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Transfer loop */
+ while(hspi->RxXferCount > 0U)
+ {
+ /* Check the RXNE flag */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+ {
+ *((uint16_t*)pData) = hspi->Instance->DR;
+ pData += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Handle the CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* freeze the CRC before the latest data */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+
+ /* Read the latest data */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* the latest data has not been received */
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Receive last data in 16 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ *((uint16_t*)pData) = hspi->Instance->DR;
+ }
+ /* Receive last data in 8 Bit mode */
+ else
+ {
+ (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ }
+
+ /* Wait the CRC data */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in blocking mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmp = 0U, tmp1 = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg1 = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
+ /* Variable used to alternate Rx and Tx during transfer */
+ uint32_t txallowed = 1U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if(!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferCount = Size;
+ hspi->RxXferSize = Size;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferCount = Size;
+ hspi->TxXferSize = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit and Receive data in 16 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+ {
+ /* Check TXE flag */
+ if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* Check RXNE flag */
+ if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ {
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
+ }
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData);
+ pTxData += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+ {
+ /* check TXE flag */
+ if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+ hspi->TxXferCount--;
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* Wait until RXNE flag is reset */
+ if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ {
+ (*(uint8_t *)pRxData++) = hspi->Instance->DR;
+ hspi->RxXferCount--;
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
+ }
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Read CRC from DR to close CRC calculation process */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ /* Read CRC */
+ tmpreg1 = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg1);
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ /* Clear CRC Flag */
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+
+ errorcode = HAL_ERROR;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Wait until TXE flag */
+/* MBED */
+ if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK)
+/* MBED */
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Check Busy flag */
+ if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ errorcode = HAL_ERROR;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ goto error;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->RxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ /* Enable TXE interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
+ }
+ else
+ {
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->TxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->RxISR = SPI_RxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t tmp = 0U, tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if(!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Set the function for IT treatment */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfer complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable the SPI Error Interrupt Bit */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData pointer to data buffer
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfer complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable the SPI Error Interrupt Bit */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+error:
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @param Size amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t tmp = 0U, tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+ if(!((tmp == HAL_SPI_STATE_READY) ||
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t*)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t*)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+ /* Enable the SPI Error Interrupt Bit */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
+ * before starting new SPI receive process.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ }
+
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ HAL_DMA_Abort(hspi->hdmatx);
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
+
+ /* Wait until TXE flag is set */
+ do
+ {
+ if(count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
+ }
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ }
+ /* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ HAL_DMA_Abort(hspi->hdmarx);
+
+ /* Disable peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
+
+ }
+ }
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
+ * before starting new SPI receive process.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+ uint32_t abortcplt;
+
+ /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ }
+
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ abortcplt = 1U;
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx channel */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ /* Abort the SPI DMA Rx channel */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Abort the SPI DMA Tx channel */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Abort the SPI DMA Rx channel */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ if(abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Enable the SPI DMA Tx & Rx requests */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx Stream */
+ if(hspi->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmatx);
+ }
+ /* Abort the SPI DMA rx Stream */
+ if(hspi->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmarx);
+ }
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SPI interrupt request.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None
+ */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+ uint32_t itsource = hspi->Instance->CR2;
+ uint32_t itflag = hspi->Instance->SR;
+
+ /* SPI in mode Receiver ----------------------------------------------------*/
+ if(((itflag & SPI_FLAG_OVR) == RESET) &&
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+ {
+ hspi->RxISR(hspi);
+ return;
+ }
+
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+ {
+ hspi->TxISR(hspi);
+ return;
+ }
+
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
+ {
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if((itflag & SPI_FLAG_OVR) != RESET)
+ {
+ if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ else
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ return;
+ }
+ }
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if((itflag & SPI_FLAG_MODF) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if((itflag & SPI_FLAG_FRE) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Disable the SPI DMA requests if enabled */
+ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+ {
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+
+ /* Abort the SPI DMA Rx channel */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmarx);
+ }
+ /* Abort the SPI DMA Tx channel */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmatx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Half Transfer callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI error callback.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+ and user can use HAL_SPI_GetError() API to check the latest error occurred
+ */
+}
+
+/**
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
+ */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SPI control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SPI.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPI handle state.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI handle state */
+ return hspi->State;
+}
+
+/**
+ * @brief Return the SPI error code.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI error code in bitmap format
+ */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI ErrorCode */
+ return hspi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+/**
+ * @brief DMA SPI transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Check the end of the transaction */
+ if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received data is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->TxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+#if (USE_SPI_CRC != 0U)
+ uint32_t tickstart = 0U;
+ __IO uint16_t tmpreg = 0U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+#endif /* USE_SPI_CRC */
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until RXNE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Check the end of the transaction */
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_RxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO int16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait the CRC data */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+#endif /* USE_SPI_CRC */
+ /* Check the end of the transaction */
+ if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxRxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication error callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+/* Stop the disable DMA transfer on SPI side */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN );
+
+ /* Wait until TXE flag is set */
+ do
+ {
+ if(count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
+ }
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+ /* Check if an Abort process is still ongoing */
+ if(hspi->hdmarx != NULL)
+ {
+ if(hspi->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Check if an Abort process is still ongoing */
+ if(hspi->hdmatx != NULL)
+ {
+ if(hspi->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 8bit mode */
+ *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+
+ /* check end of the reception */
+ if(hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if(hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+
+ UNUSED(tmpreg);
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if(hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+
+ /* check the end of the transmission */
+ if(hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if(hspi->RxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ if(hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if(hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = hspi->Instance->DR;
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ SPI_CloseRxTx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if(hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if(hspi->RxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 8-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ SPI_CloseRx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the receive 8-bit in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = hspi->Instance->DR;
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ SPI_CloseRx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the 16-bit receive in Interrupt context.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+
+ if(hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+/* MBED */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
+/* MBED */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ if(hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+/* MBED */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
+/* MBED */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
+{
+/* MBED */
+ while((hspi->Instance->SR & Flag) != State)
+/* MBED */
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State= HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/* MBED */
+/**
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag: SPI TXE flag to check
+ * @param State: flag state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State= HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+/* MBED */
+
+/**
+ * @brief Handle to check BSY flag before start a new transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Control the BSY flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the end of the RXTX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ uint32_t tickstart = 0U;
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Wait until TXE flag is set */
+ do
+ {
+ if(count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
+ }
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+ /* Check the end of the transaction */
+ if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+ }
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+ * @brief Handle the end of the RX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+ * @brief Handle the end of the TX transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ uint32_t tickstart = 0U;
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Wait until TXE flag is set */
+ do
+ {
+ if(count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
+ }
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+ /* Check Busy flag */
+ if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_TxCpltCallback(hspi);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Handle abort a Tx or Rx transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg = 0U;
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Wait until TXE flag is set */
+ do
+ {
+ if(count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
+ }
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ /* Flush DR Register */
+ tmpreg = (*(__IO uint32_t *)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+}
+
+/**
+ * @brief Handle abort a Tx or Rx transaction.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+}
+/**
+ * @}
+ */
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,585 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SPI_H
+#define __STM32F4xx_HAL_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_Mode */
+
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
+ This parameter can be a value of @ref SPI_Direction */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_Data_Size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ This parameter can be a value of @ref SPI_TI_mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+}SPI_InitTypeDef;
+
+/**
+ * @brief HAL SPI State structure definition
+ */
+typedef enum
+{
+ HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
+}HAL_SPI_StateTypeDef;
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /* SPI registers base address */
+
+ SPI_InitTypeDef Init; /* SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* SPI Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* SPI Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
+
+ DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
+
+ __IO uint32_t ErrorCode; /* SPI Error code */
+
+}SPI_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_Error_Code SPI Error Code
+ * @{
+ */
+#define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
+#define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
+#define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
+#define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
+#define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Mode SPI Mode
+ * @{
+ */
+#define SPI_MODE_SLAVE 0x00000000U
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+ * @{
+ */
+#define SPI_DIRECTION_2LINES 0x00000000U
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+ * @{
+ */
+#define SPI_DATASIZE_8BIT 0x00000000U
+#define SPI_DATASIZE_16BIT SPI_CR1_DFF
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW 0x00000000U
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE 0x00000000U
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT 0x00000000U
+#define SPI_NSS_HARD_OUTPUT 0x00040000U
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_2 0x00000000U
+#define SPI_BAUDRATEPRESCALER_4 0x00000008U
+#define SPI_BAUDRATEPRESCALER_8 0x00000010U
+#define SPI_BAUDRATEPRESCALER_16 0x00000018U
+#define SPI_BAUDRATEPRESCALER_32 0x00000020U
+#define SPI_BAUDRATEPRESCALER_64 0x00000028U
+#define SPI_BAUDRATEPRESCALER_128 0x00000030U
+#define SPI_BAUDRATEPRESCALER_256 0x00000038U
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB 0x00000000U
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_mode SPI TI Mode
+ * @{
+ */
+#define SPI_TIMODE_DISABLE 0x00000000U
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLE 0x00000000U
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
+ * @{
+ */
+#define SPI_IT_TXE SPI_CR2_TXEIE
+#define SPI_IT_RXNE SPI_CR2_RXNEIE
+#define SPI_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Flags_definition SPI Flags Definition
+ * @{
+ */
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPI handle state.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief Enable or disable the specified SPI interrupts.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified SPI interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_modf = 0x00U; \
+ tmpreg_modf = (__HANDLE__)->Instance->SR; \
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
+ UNUSED(tmpreg_modf); \
+ } while(0U)
+
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ } while(0U)
+
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_fre = 0x00U; \
+ tmpreg_fre = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_fre); \
+ }while(0U)
+
+/** @brief Enable the SPI peripheral.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
+
+/** @brief Disable the SPI peripheral.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+
+/** @brief Reset the CRC calculation of the SPI.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+ ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,691 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sram.c
+ * @author MCD Application Team
+ * @brief SRAM HAL module driver.
+ * This file provides a generic firmware to drive SRAM memories
+ * mounted as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control SRAM memories. It uses the FMC layer functions to interface
+ with SRAM devices.
+ The following sequence should be followed to configure the FMC/FSMC to interface
+ with SRAM/PSRAM memories:
+
+ (#) Declare a SRAM_HandleTypeDef handle structure, for example:
+ SRAM_HandleTypeDef hsram; and:
+
+ (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
+ values of the structure member.
+
+ (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
+ base register instance for NOR or SRAM device
+
+ (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
+ base register instance for NOR or SRAM extended mode
+
+ (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
+ mode timings; for example:
+ FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
+ and fill its fields with the allowed values of the structure member.
+
+ (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
+ performs the following sequence:
+
+ (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
+ (##) Control register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Init()
+ (##) Timing register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Timing_Init()
+ (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Extended_Timing_Init()
+ (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
+
+ (#) At this stage you can perform read/write accesses from/to the memory connected
+ to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
+ following APIs:
+ (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
+ (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
+
+ (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
+ HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
+
+ (#) You can continuously monitor the SRAM device HAL state by calling the function
+ HAL_SRAM_GetState()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SRAM SRAM
+ * @brief SRAM driver modules
+ * @{
+ */
+#ifdef HAL_SRAM_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
+ * @{
+ */
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Initialization and de_initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to initialize/de-initialize
+ the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Performs the SRAM device initialization sequence
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param Timing Pointer to SRAM control timing structure
+ * @param ExtTiming Pointer to SRAM extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ /* Check the SRAM handle parameter */
+ if(hsram == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsram->State == HAL_SRAM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsram->Lock = HAL_UNLOCKED;
+ /* Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspInit(hsram);
+ }
+
+ /* Initialize SRAM control Interface */
+ FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+
+ /* Initialize SRAM timing Interface */
+ FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
+
+ /* Initialize SRAM extended mode timing Interface */
+ FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Performs the SRAM device De-initialization sequence.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspDeInit(hsram);
+
+ /* Configure the SRAM registers with their reset values */
+ FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+
+ hsram->State = HAL_SRAM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SRAM MSP Init.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsram);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRAM MSP DeInit.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsram);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete error callback.
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads 8-bit buffer from SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint8_t *)pSramAddress;
+ pDstBuffer++;
+ pSramAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 8-bit buffer to SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
+
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
+ pSrcBuffer++;
+ pSramAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 16-bit buffer from SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint16_t *)pSramAddress;
+ pDstBuffer++;
+ pSramAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 16-bit buffer to SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
+
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
+ pSrcBuffer++;
+ pSramAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 32-bit buffer from SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint32_t *)pAddress;
+ pDstBuffer++;
+ pAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 32-bit buffer to SRAM memory.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0U; BufferSize--)
+ {
+ *(__IO uint32_t *)pAddress = *pSrcBuffer;
+ pSrcBuffer++;
+ pAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a Words data from the SRAM memory using DMA transfer.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the SRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically SRAM write operation.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Enable write operation */
+ FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically SRAM write operation.
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Disable write operation */
+ FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group4 State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the SRAM controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the SRAM controller state
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL state
+ */
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+{
+ return hsram->State;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* HAL_SRAM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,206 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sram.h
+ * @author MCD Application Team
+ * @brief Header file of SRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SRAM_H
+#define __STM32F4xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/** @addtogroup SRAM
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+ * @{
+ */
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
+ HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
+ HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
+ HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
+ HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
+
+}HAL_SRAM_StateTypeDef;
+
+/**
+ * @brief SRAM handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< SRAM locking object */
+
+ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+}SRAM_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+ * @{
+ */
+/** @brief Reset SRAM handle state
+ * @param __HANDLE__ SRAM handle
+ * @retval None
+ */
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SRAM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group3
+ * @{
+ */
+/* SRAM Control functions ******************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group4
+ * @{
+ */
+/* SRAM State functions *********************************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,5397 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_tim.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + Time Base Initialization
+ * + Time Base Start
+ * + Time Base Start Interruption
+ * + Time Base Start DMA
+ * + Time Output Compare/PWM Initialization
+ * + Time Output Compare/PWM Channel Configuration
+ * + Time Output Compare/PWM Start
+ * + Time Output Compare/PWM Start Interruption
+ * + Time Output Compare/PWM Start DMA
+ * + Time Input Capture Initialization
+ * + Time Input Capture Channel Configuration
+ * + Time Input Capture Start
+ * + Time Input Capture Start Interruption
+ * + Time Input Capture Start DMA
+ * + Time One Pulse Initialization
+ * + Time One Pulse Channel Configuration
+ * + Time One Pulse Start
+ * + Time Encoder Interface Initialization
+ * + Time Encoder Interface Start
+ * + Time Encoder Interface Start Interruption
+ * + Time Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + Time OCRef clear configuration
+ * + Time External Clock configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+
+static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0U) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
+ * @brief Time Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the Time Output Compare.
+ (+) Stop the Time Output Compare.
+ (+) Start the Time Output Compare and enable interrupt.
+ (+) Stop the Time Output Compare and disable interrupt.
+ (+) Start the Time Output Compare and enable DMA transfer.
+ (+) Stop the Time Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
+ * @brief Time PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM OPWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the Time PWM.
+ (+) Stop the Time PWM.
+ (+) Start the Time PWM and enable interrupt.
+ (+) Stop the Time PWM and disable interrupt.
+ (+) Start the Time PWM and enable DMA transfer.
+ (+) Stop the Time PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
+ * @brief Time Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the Time Input Capture.
+ (+) Stop the Time Input Capture.
+ (+) Start the Time Input Capture and enable interrupt.
+ (+) Stop the Time Input Capture and disable interrupt.
+ (+) Start the Time Input Capture and enable DMA transfer.
+ (+) Stop the Time Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM INput Capture MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement on in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0U) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement on in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
+ * @brief Time One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the Time One Pulse.
+ (+) Stop the Time One Pulse.
+ (+) Start the Time One Pulse and enable interrupt.
+ (+) Stop the Time One Pulse and disable interrupt.
+ (+) Start the Time One Pulse and enable DMA transfer.
+ (+) Stop the Time One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OnePulseMode Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel TIM Channels to be disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
+ * @brief Time Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the Time Encoder.
+ (+) Stop the Time Encoder.
+ (+) Start the Time Encoder and enable interrupt.
+ (+) Stop the Time Encoder and disable interrupt.
+ (+) Start the Time Encoder and enable DMA transfer.
+ (+) Stop the Time Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and create the associated handle.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sConfig TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
+{
+ uint32_t tmpsmcr = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS bits */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2 */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @param pData1 The destination Buffer address for IC1.
+ * @param pData2 The destination Buffer address for IC2.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_ALL:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ /* Capture compare 1 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+ {
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ HAL_TIM_PeriodElapsedCallback(htim);
+ }
+ }
+ /* TIM Break input event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ HAL_TIMEx_BreakCallback(htim);
+ }
+ }
+ /* TIM Trigger detection event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ HAL_TIM_TriggerCallback(htim);
+ }
+ }
+ /* TIM commutation event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ HAL_TIMEx_CommutationCallback(htim);
+ }
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sConfig TIM Input Capture configuration structure
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (Channel == TIM_CHANNEL_1)
+ {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+ }
+ else if (Channel == TIM_CHANNEL_3)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ }
+ else
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ __HAL_LOCK(htim);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse Channels according to the specified
+ * parameters in the TIM_OnePulse_InitTypeDef.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sConfig TIM One Pulse configuration structure
+ * @param OutputChannel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param InputChannel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+{
+ TIM_OC_InitTypeDef temp1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+ if(OutputChannel != InputChannel)
+ {
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Extract the Output compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
+ switch (OutputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ default:
+ break;
+ }
+ switch (InputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write.
+ * This parameters can be on of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc TIM DMA Request sources.
+ * This parameters can be on of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t* BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0U) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ default:
+ break;
+ }
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM DMA Burst mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param BurstRequestSrc TIM DMA Request sources to disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read.
+ * This parameters can be on of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc TIM DMA Request sources.
+ * This parameters can be on of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0U) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA burst reading
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param BurstRequestSrc TIM DMA Request sources to disable.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Generate a software event
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param EventSource specifies the event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @note TIM6 and TIM7 can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the event sources */
+ htim->Instance->EGR = EventSource;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel specifies the TIM Channel.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
+ {
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the clock source to be used
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+{
+ uint32_t tmpsmcr = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ htim->Instance->SMCR = tmpsmcr;
+
+ switch (sClockSourceConfig->ClockSource)
+ {
+ case TIM_CLOCKSOURCE_INTERNAL:
+ {
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE1:
+ {
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+ /* Reset the SMS and TS Bits */
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ /* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE2:
+ {
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Enable the External clock mode2 */
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_TI1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI1ED:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR0:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR1:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR3:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input
+ * or a XOR combination between CH1_input, CH2_input & CH3_input
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param TI1_Selection Indicate whether or not channel 1 is connected to the
+ * output of a XOR gate.
+ * This parameter can be one of the following values:
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+ * pins are connected to the TI1 input (XOR combination)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Reset the TI1 selection */
+ tmpcr2 &= ~TIM_CR2_TI1S;
+
+ /* Set the TI1 selection */
+ tmpcr2 |= TI1_Selection;
+
+ /* Write to TIMxCR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channels to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpreg = 0U;
+
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+ return tmpreg;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) Timer Period elapsed callback
+ (+) Timer Output Compare callback
+ (+) Timer Input capture callback
+ (+) Timer Trigger callback
+ (+) Timer Error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Output Compare callback in non blocking mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture callback in non blocking mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non blocking mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non blocking mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non blocking mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base state
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC state
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM state
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture state
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode state
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode state
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+/**
+ * @}
+ */
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx TIM peripheral
+ * @param Structure pointer on TIM Time Base required parameters
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1 = 0U;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Auto-reload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = (uint32_t)Structure->Prescaler;
+
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter(only for TIM1 and TIM8) value immediately */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Output Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4U);
+
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_ErrorCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_IC_CaptureCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_PeriodElapsedCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_TriggerCallback(htim);
+}
+
+/**
+ * @brief Time Output Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Output Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8U);
+
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Output Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The output configuration structure
+ * @retval None
+ */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12U);
+
+ /*if((TIMx == TIM1) || (TIMx == TIM8))*/
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Output Compare 4 configuration
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sSlaveConfig The slave configuration structure
+ * @retval None
+ */
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ uint32_t tmpsmcr = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
+
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger)
+ {
+ case TIM_TS_ETRF:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI1F_ED:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+
+ }
+ break;
+
+ case TIM_TS_TI1FP1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI2FP2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_ITR0:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR1:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR2:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR3:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+
+/**
+ * @brief Configure the Polarity and Filter for TI1.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= (TIM_ICFilter << 4U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= TIM_ICPolarity;
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ tmpccmr1 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI2.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= (TIM_ICFilter << 12U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (TIM_ICPolarity << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ tmpccmr2 |= TIM_ICSelection;
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ tmpccmr2 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ITRx The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
+{
+ uint32_t tmpsmcr = 0U;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ uint32_t tmpsmcr = 0U;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1771 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_TIM_H
+#define __STM32F4xx_HAL_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+ * @brief Clock Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< TIM clock sources.
+ This parameter can be a value of @ref TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity.
+ This parameter can be a value of @ref TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler.
+ This parameter can be a value of @ref TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClockConfigTypeDef;
+
+/**
+ * @brief Clear Input Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClearInputState; /*!< TIM clear Input state.
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources.
+ This parameter can be a value of @ref TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
+ This parameter can be a value of @ref TIM_ClearInput_Prescaler */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct {
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIM_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+}TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
+}HAL_TIM_StateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
+}HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+typedef struct
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+}TIM_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+ * @{
+ */
+#define TIM_COUNTERMODE_UP 0x00000000U
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+ * @{
+ */
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U
+#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING 0x00000000U
+#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE 0x00000000U
+#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+ * @{
+ */
+#define TIM_OCPOLARITY_HIGH 0x00000000U
+#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
+ * @{
+ */
+#define TIM_OCNPOLARITY_HIGH 0x00000000U
+#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+ * @{
+ */
+#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
+#define TIM_OCIDLESTATE_RESET 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
+ * @{
+ */
+#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
+#define TIM_OCNIDLESTATE_RESET 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel TIM Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 0x00000000U
+#define TIM_CHANNEL_2 0x00000004U
+#define TIM_CHANNEL_3 0x00000008U
+#define TIM_CHANNEL_4 0x0000000CU
+#define TIM_CHANNEL_ALL 0x00000018U
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+ * @{
+ */
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+ * @{
+ */
+#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+ * @{
+ */
+#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
+#define TIM_OPMODE_REPETITIVE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
+ * @{
+ */
+#define TIM_IT_UPDATE (TIM_DIER_UIE)
+#define TIM_IT_CC1 (TIM_DIER_CC1IE)
+#define TIM_IT_CC2 (TIM_DIER_CC2IE)
+#define TIM_IT_CC3 (TIM_DIER_CC3IE)
+#define TIM_IT_CC4 (TIM_DIER_CC4IE)
+#define TIM_IT_COM (TIM_DIER_COMIE)
+#define TIM_IT_TRIGGER (TIM_DIER_TIE)
+#define TIM_IT_BREAK (TIM_DIER_BIE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources TIM DMA sources
+ * @{
+ */
+#define TIM_DMA_UPDATE (TIM_DIER_UDE)
+#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
+#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
+#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
+#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
+#define TIM_DMA_COM (TIM_DIER_COMDE)
+#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition TIM Flag definition
+ * @{
+ */
+#define TIM_FLAG_UPDATE (TIM_SR_UIF)
+#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
+#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
+#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
+#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
+#define TIM_FLAG_COM (TIM_SR_COMIF)
+#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
+#define TIM_FLAG_BREAK (TIM_SR_BIF)
+#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
+#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
+#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
+#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
+#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
+#define TIM_CLOCKSOURCE_ITR0 0x00000000U
+#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
+#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
+#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+ * @{
+ */
+#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+ * @{
+ */
+#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Lock_level TIM Lock level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF 0x00000000U
+#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+/**
+ * @}
+ */
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
+ * @{
+ */
+#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity TIM Break Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW 0x00000000U
+#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
+#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+ * @{
+ */
+#define TIM_TRGO_RESET 0x00000000U
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode TIM Slave Mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE 0x00000000U
+#define TIM_SLAVEMODE_RESET 0x00000004U
+#define TIM_SLAVEMODE_GATED 0x00000005U
+#define TIM_SLAVEMODE_TRIGGER 0x00000006U
+#define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
+ * @{
+ */
+#define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+ * @{
+ */
+#define TIM_TS_ITR0 0x00000000U
+#define TIM_TS_ITR1 0x00000010U
+#define TIM_TS_ITR2 0x00000020U
+#define TIM_TS_ITR3 0x00000030U
+#define TIM_TS_TI1F_ED 0x00000040U
+#define TIM_TS_TI1FP1 0x00000050U
+#define TIM_TS_TI2FP2 0x00000060U
+#define TIM_TS_ETRF 0x00000070U
+#define TIM_TS_NONE 0x0000FFFFU
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Selection
+ * @{
+ */
+#define TIM_TI1SELECTION_CH1 0x00000000U
+#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base address
+ * @{
+ */
+#define TIM_DMABASE_CR1 0x00000000U
+#define TIM_DMABASE_CR2 0x00000001U
+#define TIM_DMABASE_SMCR 0x00000002U
+#define TIM_DMABASE_DIER 0x00000003U
+#define TIM_DMABASE_SR 0x00000004U
+#define TIM_DMABASE_EGR 0x00000005U
+#define TIM_DMABASE_CCMR1 0x00000006U
+#define TIM_DMABASE_CCMR2 0x00000007U
+#define TIM_DMABASE_CCER 0x00000008U
+#define TIM_DMABASE_CNT 0x00000009U
+#define TIM_DMABASE_PSC 0x0000000AU
+#define TIM_DMABASE_ARR 0x0000000BU
+#define TIM_DMABASE_RCR 0x0000000CU
+#define TIM_DMABASE_CCR1 0x0000000DU
+#define TIM_DMABASE_CCR2 0x0000000EU
+#define TIM_DMABASE_CCR3 0x0000000FU
+#define TIM_DMABASE_CCR4 0x00000010U
+#define TIM_DMABASE_BDTR 0x00000011U
+#define TIM_DMABASE_DCR 0x00000012U
+#define TIM_DMABASE_OR 0x00000013U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+ * @{
+ */
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Handle_index DMA Handle index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+ * @}
+ */
+
+/** @defgroup Channel_CC_State Channel CC State
+ * @{
+ */
+#define TIM_CCx_ENABLE 0x00000001U
+#define TIM_CCx_DISABLE 0x00000000U
+#define TIM_CCxN_ENABLE 0x00000004U
+#define TIM_CCxN_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
+/** @brief Reset TIM handle state
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0U)
+
+/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0U)
+
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled unconditionally
+ */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief Enable the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+
+/** @brief Disable the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief Enable the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief Disable the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief Check whether the specified TIM interrupt flag is set or not.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified TIM interrupt flag.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+ * @brief Check whether the specified TIM interrupt source is enabled or not.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval The state of TIM_IT (SET or RESET).
+ */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+ * @brief Indicates whether or not the TIM Counter is used as downcounter.
+ * @param __HANDLE__ TIM handle.
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+ */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+ * @brief Set the TIM Prescaler on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __PRESC__ specifies the Prescaler new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
+
+/**
+ * @brief Sets the TIM Capture Compare Register value on runtime without
+ * calling another time ConfigChannel function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __COMPARE__ specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
+
+/**
+ * @brief Gets the TIM Capture Compare Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
+
+/**
+ * @brief Sets the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __COUNTER__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Gets the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+ */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+
+/**
+ * @brief Sets the TIM Autoreload Register value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __AUTORELOAD__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0U)
+/**
+ * @brief Gets the TIM Autoreload Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+ */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+
+/**
+ * @brief Sets the TIM Clock Division value on runtime without calling another time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CKD__ specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ * @retval None
+ */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0U)
+/**
+ * @brief Gets the TIM Clock Division value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval The clock division can be one of the following values:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+ * @brief Sets the TIM Input Capture prescaler on runtime without calling
+ * another time HAL_TIM_IC_ConfigChannel() function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0U)
+
+/**
+ * @brief Get the TIM Input Capture prescaler on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval The input capture prescaler can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__ TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__ TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * _ Counter overflow/underflow
+ * _ Setting the UG bit
+ * _ Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+
+/**
+ * @brief Sets the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__ Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0U)
+/**
+ * @}
+ */
+
+/* Include TIM HAL Extension module */
+#include "stm32f4xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1
+ * @{
+ */
+
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group2
+ * @{
+ */
+/* Timer Output Compare functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3
+ * @{
+ */
+/* Timer PWM functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4
+ * @{
+ */
+/* Timer Input Capture functions ***********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5
+ * @{
+ */
+/* Timer One Pulse functions ***************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6
+ * @{
+ */
+/* Timer Encoder functions *****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7
+ * @{
+ */
+/* Interrupt Handler functions **********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group8
+ * @{
+ */
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group9
+ * @{
+ */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group10
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+
+/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
+ * @{
+ */
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
+
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
+ ((BASE) == TIM_DMABASE_CR2) || \
+ ((BASE) == TIM_DMABASE_SMCR) || \
+ ((BASE) == TIM_DMABASE_DIER) || \
+ ((BASE) == TIM_DMABASE_SR) || \
+ ((BASE) == TIM_DMABASE_EGR) || \
+ ((BASE) == TIM_DMABASE_CCMR1) || \
+ ((BASE) == TIM_DMABASE_CCMR2) || \
+ ((BASE) == TIM_DMABASE_CCER) || \
+ ((BASE) == TIM_DMABASE_CNT) || \
+ ((BASE) == TIM_DMABASE_PSC) || \
+ ((BASE) == TIM_DMABASE_ARR) || \
+ ((BASE) == TIM_DMABASE_RCR) || \
+ ((BASE) == TIM_DMABASE_CCR1) || \
+ ((BASE) == TIM_DMABASE_CCR2) || \
+ ((BASE) == TIM_DMABASE_CCR3) || \
+ ((BASE) == TIM_DMABASE_CCR4) || \
+ ((BASE) == TIM_DMABASE_BDTR) || \
+ ((BASE) == TIM_DMABASE_DCR) || \
+ ((BASE) == TIM_DMABASE_OR))
+
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Mask_Definitions TIM Mask Definition
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1882 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_tim_ex.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer extension peripheral:
+ * + Time Hall Sensor Interface Initialization
+ * + Time Hall Sensor Interface Start
+ * + Time Complementary signal bread and dead time configuration
+ * + Time Master and Slave synchronization configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Extended features #####
+ ==============================================================================
+ [..]
+ The Timer Extension features include:
+ (#) Complementary outputs with programmable dead-time for :
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to
+ interconnect several timers together.
+ (#) Break input to put the timer output signals in reset state or in a known state.
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
+ (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
+ (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
+
+ (#) Activate the TIM peripheral using one of the start functions:
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIMEx TIMEx
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions
+ * @{
+ */
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Hall Sensor functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure TIM HAL Sensor.
+ (+) De-initialize TIM HAL Sensor.
+ (+) Start the Hall Sensor Interface.
+ (+) Stop the Hall Sensor Interface.
+ (+) Start the Hall Sensor Interface and enable interrupts.
+ (+) Stop the Hall Sensor Interface and disable interrupts.
+ (+) Start the Hall Sensor Interface and enable DMA transfers.
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sConfig TIM Hall Sensor configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+{
+ TIM_OC_InitTypeDef OC_Config;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ OC_Config.OCMode = TIM_OCMODE_PWM2;
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ register to 101 */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIMEx_HallSensor_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Hall Sensor MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Hall Sensor MSP.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Enable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall sensor Interface.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1, 2 and 3
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Enable the capture compare Interrupts 1 event */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts event */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Enable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Set the DMA Input Capture 1 Callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream for Capture 1*/
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the capture compare 1 Interrupt */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+ /* Disable the capture compare Interrupts 1 event */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary Output Compare/PWM.
+ (+) Stop the Complementary Output Compare/PWM.
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+{
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary PWM.
+ (+) Stop the Complementary PWM.
+ (+) Start the Complementary PWM and enable interrupts.
+ (+) Stop the Complementary PWM and disable interrupts.
+ (+) Start the Complementary PWM and enable DMA transfers.
+ (+) Stop the Complementary PWM and disable DMA transfers.
+ (+) Start the Complementary Input Capture measurement.
+ (+) Stop the Complementary Input Capture.
+ (+) Start the Complementary Input Capture and enable interrupts.
+ (+) Stop the Complementary Input Capture and disable interrupts.
+ (+) Start the Complementary Input Capture and enable DMA transfers.
+ (+) Stop the Complementary Input Capture and disable DMA transfers.
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the PWM signal generation on the complementary output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation on the complementary output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * complementary output
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0U) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
+ * output
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM One Pulse signal generation on the complementary
+ * output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation on the complementary
+ * output.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel TIM Channel to be enabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel TIM Channel to be disabled.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Configure the TIM commutation event sequence.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with interrupt.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation Interrupt Request */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with DMA.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation DMA Request */
+ /* Set the DMA Commutation Callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the Commutation DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Reset the MMS Bits */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Reset the MSM Bit */
+ htim->Instance->SMCR &= ~TIM_SMCR_MSM;
+ /* Set or Reset the MSM Bit */
+ htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+{
+ uint32_t tmpbdtr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
+
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Remap specifies the TIM input remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
+ * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
+ * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
+ * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
+ * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
+ * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
+ * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
+ * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
+ * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
+ * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
+ * (HSE divided by a programmable prescaler)
+ * @arg TIM_TIM9_TIM3_TRGO: TIM9 ITR1 input is connected to TIM3 Trigger output(default)
+ * @arg TIM_TIM9_LPTIM: TIM9 ITR1 input is connected to LPTIM.
+ * @arg TIM_TIM5_TIM3_TRGO: TIM5 ITR1 input is connected to TIM3 Trigger output(default)
+ * @arg TIM_TIM5_LPTIM: TIM5 ITR1 input is connected to LPTIM.
+ * @arg TIM_TIM1_TIM3_TRGO: TIM1 ITR2 input is connected to TIM3 Trigger output(default)
+ * @arg TIM_TIM1_LPTIM: TIM1 ITR2 input is connected to LPTIM.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+ __HAL_LOCK(htim);
+
+ /* Check parameters */
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_REMAP(Remap));
+
+#if defined(LPTIM_OR_TIM1_ITR2_RMP)
+ if ((Remap == TIM_TIM9_TIM3_TRGO)|| (Remap == TIM_TIM9_LPTIM)||(Remap ==TIM_TIM5_TIM3_TRGO)||\
+ (Remap == TIM_TIM5_LPTIM)||(Remap == TIM_TIM1_TIM3_TRGO)|| (Remap == TIM_TIM1_LPTIM))
+ {
+ __HAL_RCC_LPTIM1_CLK_ENABLE();
+
+ LPTIM1->OR = (Remap& 0xEFFFFFFFU);
+ }
+ else
+ {
+ /* Set the Timer remapping configuration */
+ htim->Instance->OR = Remap;
+ }
+#else
+ /* Set the Timer remapping configuration */
+ htim->Instance->OR = Remap;
+#endif
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
+ * @brief Extension Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extension Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides Extension TIM callback functions:
+ (+) Timer Commutation callback
+ (+) Timer Break callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Hall commutation changed callback in non blocking mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break detection callback in non blocking mode
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
+ * @brief Extension Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extension Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Hall Sensor interface state
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIMEx_CommutationCallback(htim);
+}
+/**
+ * @}
+ */
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * @retval None
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+ uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1NE << Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,368 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_TIM_EX_H
+#define __STM32F4xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/**
+ * @brief TIM Break and Dead time configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode.
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level.
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State.
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity.
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+}TIM_BreakDeadTimeConfigTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIMEx_Remap TIM Remap
+ * @{
+ */
+#define TIM_TIM2_TIM8_TRGO 0x00000000U
+#define TIM_TIM2_ETH_PTP 0x00000400U
+#define TIM_TIM2_USBFS_SOF 0x00000800U
+#define TIM_TIM2_USBHS_SOF 0x00000C00U
+#define TIM_TIM5_GPIO 0x00000000U
+#define TIM_TIM5_LSI 0x00000040U
+#define TIM_TIM5_LSE 0x00000080U
+#define TIM_TIM5_RTC 0x000000C0U
+#define TIM_TIM11_GPIO 0x00000000U
+#define TIM_TIM11_HSE 0x00000002U
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define TIM_TIM9_TIM3_TRGO 0x10000000U
+#define TIM_TIM9_LPTIM 0x10000010U
+#define TIM_TIM5_TIM3_TRGO 0x10000000U
+#define TIM_TIM5_LPTIM 0x10000008U
+#define TIM_TIM1_TIM3_TRGO 0x10000000U
+#define TIM_TIM1_LPTIM 0x10000004U
+#endif /* STM32F413xx | STM32F423xx */
+
+#if defined (STM32F446xx)
+#define TIM_TIM11_SPDIFRX 0x00000001U
+#endif /* STM32F446xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup TIMEx_SystemBreakInput TIM System Break Input
+ * @{
+ */
+#define TIM_SYSTEMBREAKINPUT_HARDFAULT 0x00000001U /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
+#define TIM_SYSTEMBREAKINPUT_PVD 0x00000004U /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
+#define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD 0x00000005U /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1
+ * @{
+ */
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2
+ * @{
+ */
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3
+ * @{
+ */
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4
+ * @{
+ */
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5
+ * @{
+ */
+/* Extension Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6
+ * @{
+ */
+/* Extension Callback *********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7
+ * @{
+ */
+/* Extension Peripheral State functions **************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Private Macros
+ * @{
+ */
+#if defined (STM32F446xx)
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM5_LSI)||\
+ ((TIM_REMAP) == TIM_TIM5_LSE)||\
+ ((TIM_REMAP) == TIM_TIM5_RTC)||\
+ ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_SPDIFRX)||\
+ ((TIM_REMAP) == TIM_TIM11_HSE))
+#elif defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM5_LSI)||\
+ ((TIM_REMAP) == TIM_TIM5_LSE)||\
+ ((TIM_REMAP) == TIM_TIM5_RTC)||\
+ ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_HSE)||\
+ ((TIM_REMAP) == TIM_TIM9_TIM3_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM9_LPTIM)||\
+ ((TIM_REMAP) == TIM_TIM5_TIM3_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM5_LPTIM)||\
+ ((TIM_REMAP) == TIM_TIM1_TIM3_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM1_LPTIM))
+#else
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM5_LSI)||\
+ ((TIM_REMAP) == TIM_TIM5_LSE)||\
+ ((TIM_REMAP) == TIM_TIM5_RTC)||\
+ ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_HSE))
+#endif /* STM32F446xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_TIM_SYSTEMBREAKINPUT(BREAKINPUT) (((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT)||\
+ ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_PVD)||\
+ ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD))
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
+
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2537 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_uart.c
+ * @author MCD Application Team
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+ (##) Enable the USARTx interface clock.
+ (##) UART pins configuration:
+ (+++) Enable the clock for the UART GPIOs.
+ (+++) Configure these UART pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ and HAL_UART_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ and HAL_UART_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required
+ Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx Stream.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode(Receiver/Transmitter) in the Init structure.
+
+ (#) For the UART asynchronous mode, initialize the UART registers by calling
+ the HAL_UART_Init() API.
+
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
+
+ (#) For the Multi-Processor mode, initialize the UART registers by calling
+ the HAL_MultiProcessor_Init() API.
+
+ [..]
+ (@) The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
+ and receive process.
+
+ [..]
+ (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
+ low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
+ HAL_UART_MspInit() API.
+
+ [..]
+ Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_UART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_UART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_UART_DMAStop()
+
+ *** UART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in UART HAL driver.
+
+ (+) __HAL_UART_ENABLE: Enable the UART peripheral
+ (+) __HAL_UART_DISABLE: Disable the UART peripheral
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+ (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+ (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
+
+ [..]
+ (@) You can refer to the UART HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UART UART
+ * @brief HAL UART module driver
+ * @{
+ */
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup UART_Private_Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void UART_SetConfig (UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ please refer to Reference manual for possible UART frame formats.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ [..]
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
+ follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
+ configuration procedures (details for the procedures are available in reference manual (RM0329)).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the UART mode according to the specified parameters in
+ * the UART_InitTypeDef and create the associated handle.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ {
+ /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ }
+ else
+ {
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ }
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ UART_SetConfig(huart);
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* Enable the peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Initialize the UART state */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState= HAL_UART_STATE_READY;
+ huart->RxState= HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and create the associated handle.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ UART_SetConfig(huart);
+
+ /* In half-duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+ /* Enable the peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Initialize the UART state*/
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState= HAL_UART_STATE_READY;
+ huart->RxState= HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and create the associated handle.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param BreakDetectLength Specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
+ * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+ assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ UART_SetConfig(huart);
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+ /* Set the USART LIN Break detection length. */
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);
+ SET_BIT(huart->Instance->CR2, BreakDetectLength);
+
+ /* Enable the peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Initialize the UART state*/
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState= HAL_UART_STATE_READY;
+ huart->RxState= HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the Multi-Processor mode according to the specified
+ * parameters in the UART_InitTypeDef and create the associated handle.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param Address USART address
+ * @param WakeUpMethod specifies the USART wake-up method.
+ * This parameter can be one of the following values:
+ * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
+ * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+ assert_param(IS_UART_ADDRESS(Address));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ UART_SetConfig(huart);
+
+ /* In Multi-Processor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register */
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* Clear the USART address */
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
+ /* Set the USART address node */
+ SET_BIT(huart->Instance->CR2, Address);
+
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);
+ SET_BIT(huart->Instance->CR1, WakeUpMethod);
+
+ /* Enable the peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Initialize the UART state */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState= HAL_UART_STATE_READY;
+ huart->RxState= HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the UART peripheral.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_UART_MspDeInit(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
+
+ /* Process Lock */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief UART MSP Init.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART MSP DeInit.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the UART asynchronous
+ and Half duplex data transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non blocking mode: The communication is performed using Interrupts
+ or DMA, these APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or receive process.
+ The HAL_UART_ErrorCallback() user callback will be executed when
+ a communication error is detected.
+
+ (#) Blocking mode APIs are:
+ (++) HAL_UART_Transmit()
+ (++) HAL_UART_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are:
+ (++) HAL_UART_Transmit_IT()
+ (++) HAL_UART_Receive_IT()
+ (++) HAL_UART_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are:
+ (++) HAL_UART_Transmit_DMA()
+ (++) HAL_UART_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
+ (++) HAL_UART_TxCpltCallback()
+ (++) HAL_UART_RxCpltCallback()
+ (++) HAL_UART_ErrorCallback()
+
+ [..]
+ (@) In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
+ can't be useful.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sends an amount of data in blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+ while(huart->TxXferCount > 0U)
+ {
+ huart->TxXferCount--;
+ if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pData;
+ huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ if(huart->Init.Parity == UART_PARITY_NONE)
+ {
+ pData +=2U;
+ }
+ else
+ {
+ pData +=1U;
+ }
+ }
+ else
+ {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
+ }
+ }
+
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Check the remain data to be received */
+ while(huart->RxXferCount > 0U)
+ {
+ huart->RxXferCount--;
+ if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pData;
+ if(huart->Init.Parity == UART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+ pData +=2U;
+ }
+ else
+ {
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
+ pData +=1U;
+ }
+
+ }
+ else
+ {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if(huart->Init.Parity == UART_PARITY_NONE)
+ {
+ *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+ }
+
+ }
+ }
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Transmit data register empty Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the UART transmit DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+ __HAL_UART_CLEAR_OREFLAG(huart);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+ uint32_t dmarequest = 0x00U;
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+ if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+ {
+ /* Disable the UART DMA Tx request */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+ if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+ {
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ if(huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Enable the UART DMA Tx request */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_UART_CLEAR_OREFLAG(huart);
+
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART DMA Rx request */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+ uint32_t dmarequest = 0x00U;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
+ */
+
+ /* Stop UART DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+ if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel */
+ if(huart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+ if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ UART_EndRxTransfer(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0x00U;
+ huart->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Restore huart->RxState and huart->gState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0x00U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0x00U;
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+ uint32_t AbortCplt = 0x01U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+ }
+ else
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+ }
+ else
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* UART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* UART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ AbortCplt = 0x01U;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if(AbortCplt == 0x01U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0x00U;
+ huart->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0x00U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0x00U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0x00U;
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0x00U;
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles UART interrupt request.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ uint32_t isrflags = READ_REG(huart->Instance->SR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+ uint32_t errorflags = 0x00U;
+ uint32_t dmarequest = 0x00U;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+ if(errorflags == RESET)
+ {
+ /* UART in mode Receiver -------------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ {
+ /* UART parity error interrupt occurred ----------------------------------*/
+ if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART noise error interrupt occurred -----------------------------------*/
+ if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* UART frame error interrupt occurred -----------------------------------*/
+ if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART Over-Run interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ /* Call UART Error Call back function if need be --------------------------*/
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver -----------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+ if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_UART_ErrorCallback(huart);
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+ } /* End if some error occurs */
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ UART_Transmit_IT(huart);
+ return;
+ }
+
+ /* UART in mode Transmitter end --------------------------------------------*/
+ if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ {
+ UART_EndTransmit_IT(huart);
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART error callbacks.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Receive Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART:
+ (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
+ (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
+ (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits break characters.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the UART in mute mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Exits the UART mute mode: wake up software.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the UART transmitter and disables the UART receiver.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg = 0x00U;
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = huart->Instance->CR1;
+
+ /* Clear TE and RE bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+ tmpreg |= (uint32_t)USART_CR1_TE;
+
+ /* Write to USART CR1 */
+ WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the UART receiver and disables the UART transmitter.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg = 0x00U;
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = huart->Instance->CR1;
+
+ /* Clear TE and RE bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+ tmpreg |= (uint32_t)USART_CR1_RE;
+
+ /* Write to USART CR1 */
+ WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief UART State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of
+ UART communication process, return Peripheral Errors occurred during communication
+ process
+ (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
+ (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the UART state.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
+ temp1 = huart->gState;
+ temp2 = huart->RxState;
+
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the UART error code
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval UART Error Code
+ */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+ return huart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode*/
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ huart->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_UART_TxCpltCallback(huart);
+ }
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_UART_TxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode*/
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ huart->RxXferCount = 0U;
+
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ }
+ HAL_UART_RxCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_UART_RxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ uint32_t dmarequest = 0x00U;
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Stop UART DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+ if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+ {
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+ if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+ {
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
+ }
+
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief This function handles UART Communication Timeout.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param Flag specifies the UART flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+}
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+}
+
+/**
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(huart->hdmarx != NULL)
+ {
+ if(huart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0x00U;
+ huart->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(huart->hdmatx != NULL)
+ {
+ if(huart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0x00U;
+ huart->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->TxXferCount = 0x00U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->RxXferCount = 0x00U;
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+
+ /* Check that a Tx process is ongoing */
+ if(huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) huart->pTxBuffPtr;
+ huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ if(huart->Init.Parity == UART_PARITY_NONE)
+ {
+ huart->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ huart->pTxBuffPtr += 1U;
+ }
+ }
+ else
+ {
+ huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
+ }
+
+ if(--huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Complete Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ HAL_UART_TxCpltCallback(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+
+ /* Check that a Rx process is ongoing */
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) huart->pRxBuffPtr;
+ if(huart->Init.Parity == UART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+ huart->pRxBuffPtr += 2U;
+ }
+ else
+ {
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
+ huart->pRxBuffPtr += 1U;
+ }
+ }
+ else
+ {
+ if(huart->Init.Parity == UART_PARITY_NONE)
+ {
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+ }
+ }
+
+ if(--huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ HAL_UART_RxCpltCallback(huart);
+
+ return HAL_OK;
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configures the UART peripheral.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+static void UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = huart->Instance->CR2;
+
+ /* Clear STOP[13:12] bits */
+ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */
+ tmpreg |= (uint32_t)huart->Init.StopBits;
+
+ /* Write to USART CR2 */
+ WRITE_REG(huart->Instance->CR2, (uint32_t)tmpreg);
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = huart->Instance->CR1;
+
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8));
+
+ /* Configure the UART Word Length, Parity and mode:
+ Set the M bits according to huart->Init.WordLength value
+ Set PCE and PS bits according to huart->Init.Parity value
+ Set TE and RE bits according to huart->Init.Mode value
+ Set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
+
+ /* Write to USART CR1 */
+ WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ tmpreg = huart->Instance->CR3;
+
+ /* Clear CTSE and RTSE bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+
+ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
+ tmpreg |= huart->Init.HwFlowCtl;
+
+ /* Write to USART CR3 */
+ WRITE_REG(huart->Instance->CR3, (uint32_t)tmpreg);
+
+ /* Check the Over Sampling */
+ if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ /*-------------------------- USART BRR Configuration ---------------------*/
+#if defined(USART6)
+ if((huart->Instance == USART1) || (huart->Instance == USART6))
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ }
+#else
+ if(huart->Instance == USART1)
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ }
+#endif /* USART6 */
+ else
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ }
+ }
+ else
+ {
+ /*-------------------------- USART BRR Configuration ---------------------*/
+#if defined(USART6)
+ if((huart->Instance == USART1) || (huart->Instance == USART6))
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ }
+#else
+ if(huart->Instance == USART1)
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ }
+#endif /* USART6 */
+ else
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,792 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_uart.h
+ * @author MCD Application Team
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_UART_H
+#define __STM32F4xx_HAL_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
+ Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UART_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode */
+
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control */
+
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling */
+}UART_InitTypeDef;
+
+/**
+ * @brief HAL UART State structures definition
+ * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains UART state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized. HAL UART Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef enum
+{
+ HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+ HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ Value is allowed for gState only */
+ HAL_UART_STATE_ERROR = 0xE0U /*!< Error
+ Value is allowed for gState only */
+}HAL_UART_StateTypeDef;
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< UART registers base address */
+
+ UART_InitTypeDef Init; /*!< UART communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
+}UART_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported constants
+ * @{
+ */
+
+/** @defgroup UART_Error_Code UART Error Code
+ * @brief UART Error Code
+ * @{
+ */
+#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Word_Length UART Word Length
+ * @{
+ */
+#define UART_WORDLENGTH_8B 0x00000000U
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+ * @{
+ */
+#define UART_STOPBITS_1 0x00000000U
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity UART Parity
+ * @{
+ */
+#define UART_PARITY_NONE 0x00000000U
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE 0x00000000U
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode UART Transfer Mode
+ * @{
+ */
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+/**
+ * @}
+ */
+
+ /** @defgroup UART_State UART State
+ * @{
+ */
+#define UART_STATE_DISABLE 0x00000000U
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 0x00000000U
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U
+#define UART_LINBREAKDETECTLENGTH_11B 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_functions UART Wakeup Functions
+ * @{
+ */
+#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U
+#define UART_WAKEUPMETHOD_ADDRESSMARK 0x00000800U
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags UART FLags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
+#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
+#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
+#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
+#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
+#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask (16 bits) in the Y register
+ * - Y : Interrupt source register (2bits)
+ * - 0001: CR1 register
+ * - 0010: CR2 register
+ * - 0011: CR3 register
+ *
+ * @{
+ */
+
+#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+
+#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
+
+#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
+
+/** @brief Reset UART handle gstate & RxState
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ } while(0U)
+
+/** @brief Flushes the UART DR register
+ * @param __HANDLE__ specifies the UART Handle.
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Checks whether the specified UART flag is set or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
+ * @arg UART_FLAG_LBD: LIN Break detection flag
+ * @arg UART_FLAG_TXE: Transmit data register empty flag
+ * @arg UART_FLAG_TC: Transmission Complete flag
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag
+ * @arg UART_FLAG_IDLE: Idle Line detection flag
+ * @arg UART_FLAG_ORE: Overrun Error flag
+ * @arg UART_FLAG_NE: Noise Error flag
+ * @arg UART_FLAG_FE: Framing Error flag
+ * @arg UART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified UART pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
+ * @arg UART_FLAG_LBD: LIN Break detection flag.
+ * @arg UART_FLAG_TC: Transmission Complete flag.
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Clear the UART PE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0U)
+
+/** @brief Clear the UART FE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART NE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART IDLE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__ specifies the UART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define UART_IT_MASK 0x0000FFFFU
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+/** @brief Disable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__ specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+
+/** @brief Checks whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __IT__ specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
+
+/** @brief Enable CTS flow control
+ * This macro allows to enable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * The Handle Instance can be USART1, USART2 or LPUART.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+ } while(0U)
+
+/** @brief Disable CTS flow control
+ * This macro allows to disable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * The Handle Instance can be USART1, USART2 or LPUART.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+ } while(0U)
+
+/** @brief Enable RTS flow control
+ * This macro allows to enable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * The Handle Instance can be USART1, USART2 or LPUART.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+ } while(0U)
+
+/** @brief Disable RTS flow control
+ * This macro allows to disable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * The Handle Instance can be USART1, USART2 or LPUART.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+ } while(0U)
+
+/** @brief macros to enables the UART's one bit sample method
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief macros to disables the UART's one bit sample method
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+/** @brief UART interruptions flag mask
+ *
+ */
+#define UART_CR1_REG_INDEX 1U
+#define UART_CR2_REG_INDEX 2U
+#define UART_CR3_REG_INDEX 3U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+ ((LENGTH) == UART_WORDLENGTH_9B))
+#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+ ((STOPBITS) == UART_STOPBITS_2))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+ ((PARITY) == UART_PARITY_EVEN) || \
+ ((PARITY) == UART_PARITY_ODD))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == UART_HWCONTROL_NONE) || \
+ ((CONTROL) == UART_HWCONTROL_RTS) || \
+ ((CONTROL) == UART_HWCONTROL_CTS) || \
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+ ((STATE) == UART_STATE_ENABLE))
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+ ((SAMPLING) == UART_OVERSAMPLING_8))
+#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
+
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
+
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
+ ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
+ (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2300 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_usart.c
+ * @author MCD Application Team
+ * @brief USART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The USART HAL driver can be used as follows:
+
+ (#) Declare a USART_HandleTypeDef handle structure.
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
+ (##) Enable the USARTx interface clock.
+ (##) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure these USART pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode(Receiver/Transmitter) in the husart Init structure.
+
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+ (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_USART_MspInit(&husart) API.
+
+ -@@- The specific USART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
+ (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_USART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_USART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+
+ *** USART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in USART HAL driver.
+
+ (+) __HAL_USART_ENABLE: Enable the USART peripheral
+ (+) __HAL_USART_DISABLE: Disable the USART peripheral
+ (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
+ (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
+ (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
+ (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
+
+ [..]
+ (@) You can refer to the USART HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USART USART
+ * @brief HAL USART Synchronous module driver
+ * @{
+ */
+#ifdef HAL_USART_MODULE_ENABLED
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup USART_Private_Constants
+ * @{
+ */
+#define DUMMY_DATA 0xFFFFU
+#define USART_TIMEOUT_VALUE 22000U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+static void USART_SetConfig (USART_HandleTypeDef *husart);
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in asynchronous and in synchronous modes.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ please refer to Reference manual for possible USART frame formats.
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_USART_Init() function follows the USART synchronous configuration
+ procedure (details for the procedure are available in reference manual (RM0329)).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and create the associated handle.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ if(husart->State == HAL_USART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_USART_MspInit(husart);
+ }
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Set the USART Communication parameters */
+ USART_SetConfig(husart);
+
+ /* In USART mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register */
+ CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* Enable the Peripheral */
+ __HAL_USART_ENABLE(husart);
+
+ /* Initialize the USART state */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State= HAL_USART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the USART peripheral.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_USART_DISABLE(husart);
+
+ /* DeInit the low level hardware */
+ HAL_USART_MspDeInit(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USART MSP Init.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_USART_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART MSP DeInit.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_USART_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the USART synchronous
+ data transfers.
+
+ [..]
+ The USART supports master mode only: it cannot receive or send data related to an input
+ clock (SCLK is always an output).
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
+ user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback() user callback will be executed when a communication
+ error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_USART_Transmit() in simplex mode
+ (++) HAL_USART_Receive() in full duplex receive only
+ (++) HAL_USART_TransmitReceive() in full duplex mode
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_USART_Transmit_IT()in simplex mode
+ (++) HAL_USART_Receive_IT() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_IT() in full duplex mode
+ (++) HAL_USART_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_USART_Transmit_DMA()in simplex mode
+ (++) HAL_USART_Receive_DMA() in full duplex receive only
+ (++) HAL_USART_TransmitReceie_DMA() in full duplex mode
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_USART_TxHalfCpltCallback()
+ (++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
+ (++) HAL_USART_RxCpltCallback()
+ (++) HAL_USART_ErrorCallback()
+ (++) HAL_USART_TxRxCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Simplex Send an amount of data in blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ while(husart->TxXferCount > 0U)
+ {
+ husart->TxXferCount--;
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ /* Wait for TC flag in order to write data in DR */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pTxData;
+ husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ pTxData += 2U;
+ }
+ else
+ {
+ pTxData += 1U;
+ }
+ }
+ else
+ {
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ husart->Instance->DR = (*pTxData++ & (uint8_t)0xFF);
+ }
+ }
+
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Receive an amount of data in blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pRxData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ /* Check the remain data to be received */
+ while(husart->RxXferCount > 0U)
+ {
+ husart->RxXferCount--;
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Send dummy byte in order to generate clock */
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pRxData ;
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+ pRxData +=2U;
+ }
+ else
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+ pRxData +=1U;
+ }
+ }
+ else
+ {
+ /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send Dummy Byte in order to generate clock */
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
+
+ /* Wait until RXNE flag is set to receive the byte */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ /* Receive data */
+ *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ /* Receive data */
+ *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+ }
+
+ }
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to data transmitted buffer
+ * @param pRxData Pointer to data received buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
+ husart->RxXferSize = Size;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ husart->RxXferCount = Size;
+
+ /* Check the remain data to be received */
+ while(husart->TxXferCount > 0U)
+ {
+ husart->TxXferCount--;
+ husart->RxXferCount--;
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ /* Wait for TC flag in order to write data in DR */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pTxData;
+ husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ pTxData += 2U;
+ }
+ else
+ {
+ pTxData += 1U;
+ }
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pRxData ;
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+ pRxData += 2U;
+ }
+ else
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+ pRxData += 1U;
+ }
+ }
+ else
+ {
+ /* Wait for TC flag in order to write data in DR */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ husart->Instance->DR = (*pTxData++ & (uint8_t)0x00FF);
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ /* Receive data */
+ *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ /* Receive data */
+ *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+ }
+ }
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ * @note The USART errors are not managed to avoid the overrun error.
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
+ are not managed by the USART transmit process to avoid the overrun interrupt
+ when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
+ to benefit for the frame error and noise interrupts the USART mode should be
+ configured only for transmit "USART_MODE_TX"
+ The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
+ Noise error interrupt */
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Simplex Receive an amount of data in non-blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pRxData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Send dummy byte in order to generate the clock for the slave to send data */
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to data transmitted buffer
+ * @param pRxData Pointer to data received buffer
+ * @param Size Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Data Register not empty Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* Set the USART DMA transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the DMA abort callback */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the USART transmit DMA Stream */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Receive an amount of data in non-blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pRxData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @retval HAL status
+ * @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pRxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Set the DMA abort callback */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ husart->hdmatx->XferHalfCpltCallback = NULL;
+ husart->hdmatx->XferCpltCallback = NULL;
+
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the USART receive DMA Stream */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA Stream: the transmit stream is used in order
+ to generate in the non-blocking mode the clock to the slave device,
+ this mode isn't a simplex receive mode but a full-duplex receive one */
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+
+ /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to data transmitted buffer
+ * @param pRxData Pointer to data received buffer
+ * @param Size Amount of data to be received
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Tx transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the USART DMA Tx transfer error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Set the DMA abort callback */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the USART receive DMA Stream */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA Stream */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
+
+ /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ /* Enable the USART DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+ uint32_t dmarequest = 0x00U;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
+ */
+
+ /* Stop USART DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
+ if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
+ {
+ USART_EndTxTransfer(husart);
+
+ /* Abort the USART DMA Tx channel */
+ if(husart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+
+ /* Disable the USART Tx DMA request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+
+ /* Stop USART DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+ if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+ {
+ USART_EndRxTransfer(husart);
+
+ /* Abort the USART DMA Rx channel */
+ if(husart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* Disable the USART Rx DMA request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
+ * as described by TransferType parameter) started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the USART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0x00U;
+ husart->RxXferCount = 0x00U;
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
+ * as described by TransferType parameter) started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+ uint32_t AbortCplt = 0x01U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(husart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+ }
+ else
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+ }
+ else
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the USART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at USART level */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(husart->hdmatx != NULL)
+ {
+ /* USART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(husart->hdmarx != NULL)
+ {
+ /* USART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ AbortCplt = 0x01U;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if(AbortCplt == 0x01U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0x00U;
+ husart->RxXferCount = 0x00U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles USART interrupt request.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+ uint32_t isrflags = READ_REG(husart->Instance->SR);
+ uint32_t cr1its = READ_REG(husart->Instance->CR1);
+ uint32_t cr3its = READ_REG(husart->Instance->CR3);
+ uint32_t errorflags = 0x00U;
+ uint32_t dmarequest = 0x00U;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+ if(errorflags == RESET)
+ {
+ /* USART in mode Receiver -------------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ return;
+ }
+ }
+ /* If some errors occur */
+ if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ {
+ /* USART parity error interrupt occurred ----------------------------------*/
+ if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_PE;
+ }
+
+ /* USART noise error interrupt occurred --------------------------------*/
+ if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_NE;
+ }
+
+ /* USART frame error interrupt occurred --------------------------------*/
+ if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_FE;
+ }
+
+ /* USART Over-Run interrupt occurred -----------------------------------*/
+ if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;
+ }
+
+ if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ {
+ /* USART in mode Receiver -----------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+ if(((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest)
+ {
+ /* Set the USART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ USART_EndRxTransfer(husart);
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Abort callback :
+ will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ husart->hdmarx->XferAbortCallback(husart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ }
+ }
+ return;
+ }
+
+ /* USART in mode Transmitter -----------------------------------------------*/
+ if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ USART_Transmit_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ return;
+ }
+
+ /* USART in mode Transmitter (transmission end) ----------------------------*/
+ if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ {
+ USART_EndTransmit_IT(husart);
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART error callbacks.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_USART_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART Abort Complete callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief USART State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of
+ USART communication
+ process, return Peripheral Errors occurred during communication process
+ (+) HAL_USART_GetState() API can be helpful to check in run-time the state
+ of the USART peripheral.
+ (+) HAL_USART_GetError() check in run-time errors that could be occurred during
+ communication.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the USART state.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL state
+ */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+ return husart->State;
+}
+
+/**
+ * @brief Return the USART error code
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART Error Code
+ */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+ return husart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ husart->TxXferCount = 0U;
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
+ }
+ }
+ /* DMA Circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ HAL_USART_TxCpltCallback(husart);
+ }
+ }
+}
+
+/**
+ * @brief DMA USART transmit process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_USART_TxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode */
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ husart->RxXferCount = 0x00U;
+
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the Transmit/receiver request by clearing the DMAT/DMAR bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* The USART state is HAL_USART_STATE_BUSY_RX */
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
+ /* DMA circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
+}
+
+/**
+ * @brief DMA USART receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_USART_RxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ uint32_t dmarequest = 0x00U;
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ husart->RxXferCount = 0x00U;
+ husart->TxXferCount = 0x00U;
+
+ /* Stop USART DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
+ if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
+ {
+ USART_EndTxTransfer(husart);
+ }
+
+ /* Stop USART DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+ if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+ {
+ USART_EndRxTransfer(husart);
+ }
+
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;
+ husart->State= HAL_USART_STATE_READY;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief This function handles USART Communication Timeout.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param Flag specifies the USART flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ {
+ /* Disable the USART Transmit Complete Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Disable the USART RXNE Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
+
+ /* Disable the USART Parity Error Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+ * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
+{
+ /* Disable RXNE, PE and ERR interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+ * @brief DMA USART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ husart->RxXferCount = 0x00U;
+ husart->TxXferCount = 0x00U;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief DMA USART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(husart->hdmarx != NULL)
+ {
+ if(husart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0x00U;
+ husart->RxXferCount = 0x00U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(husart->hdmatx != NULL)
+ {
+ if(husart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0x00U;
+ husart->RxXferCount = 0x00U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+}
+
+/**
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ * @note The USART errors are not managed to avoid the overrun error.
+ */
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ husart->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ husart->pTxBuffPtr += 1U;
+ }
+ }
+ else
+ {
+ husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
+ }
+
+ if(--husart->TxXferCount == 0U)
+ {
+ /* Disable the USART Transmit data register empty Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxCpltCallback(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Simplex Receive an amount of data in non-blocking mode.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp;
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr;
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+ husart->pRxBuffPtr += 2U;
+ }
+ else
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+ husart->pRxBuffPtr += 1U;
+ }
+ if(--husart->RxXferCount != 0x00U)
+ {
+ /* Send dummy byte in order to generate the clock for the slave to send the next data */
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
+ }
+ }
+ else
+ {
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+ }
+
+ if(--husart->RxXferCount != 0x00U)
+ {
+ /* Send dummy byte in order to generate the clock for the slave to send the next data */
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ }
+
+ if(husart->RxXferCount == 0U)
+ {
+ /* Disable the USART RXNE Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
+
+ /* Disable the USART Parity Error Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ husart->State = HAL_USART_STATE_READY;
+ HAL_USART_RxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ {
+ if(husart->TxXferCount != 0x00U)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+ {
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ husart->pTxBuffPtr += 2U;
+ }
+ else
+ {
+ husart->pTxBuffPtr += 1U;
+ }
+ }
+ else
+ {
+ husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
+ }
+ husart->TxXferCount--;
+
+ /* Check the latest data transmitted */
+ if(husart->TxXferCount == 0U)
+ {
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+ }
+ }
+ }
+
+ if(husart->RxXferCount != 0x00U)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+ {
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr;
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+ husart->pRxBuffPtr += 2U;
+ }
+ else
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+ husart->pRxBuffPtr += 1U;
+ }
+ }
+ else
+ {
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+ }
+ }
+ husart->RxXferCount--;
+ }
+ }
+
+ /* Check the latest data received */
+ if(husart->RxXferCount == 0U)
+ {
+ /* Disable the USART RXNE Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
+
+ /* Disable the USART Parity Error Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxRxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configures the USART pferipheral.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+static void USART_SetConfig(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpreg = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+ assert_param(IS_USART_PARITY(husart->Init.Parity));
+ assert_param(IS_USART_MODE(husart->Init.Mode));
+
+ /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
+ receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /*---------------------------- USART CR2 Configuration ---------------------*/
+ tmpreg = husart->Instance->CR2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP));
+ /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/
+ /* Set CPOL bit according to husart->Init.CLKPolarity value */
+ /* Set CPHA bit according to husart->Init.CLKPhase value */
+ /* Set LBCL bit according to husart->Init.CLKLastBit value */
+ /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
+ tmpreg |= (uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity |
+ husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
+ /* Write to USART CR2 */
+ WRITE_REG(husart->Instance->CR2, (uint32_t)tmpreg);
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = husart->Instance->CR1;
+
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8));
+
+ /* Configure the USART Word Length, Parity and mode:
+ Set the M bits according to husart->Init.WordLength value
+ Set PCE and PS bits according to husart->Init.Parity value
+ Set TE and RE bits according to husart->Init.Mode value
+ Force OVER8 bit to 1 in order to reach the max USART frequencies */
+ tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
+
+ /* Write to USART CR1 */
+ WRITE_REG(husart->Instance->CR1, (uint32_t)tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Clear CTSE and RTSE bits */
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+#if defined(USART6)
+ if((husart->Instance == USART1) || (husart->Instance == USART6))
+ {
+ husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
+ }
+#else
+ if(husart->Instance == USART1)
+ {
+ husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
+ }
+#endif /* USART6 */
+ else
+ {
+ husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,590 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_usart.h
+ * @author MCD Application Team
+ * @brief Header file of USART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_USART_H
+#define __STM32F4xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+ * @{
+ */
+
+/**
+ * @brief USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+}USART_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
+ HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04U /*!< Error */
+}HAL_USART_StateTypeDef;
+
+/**
+ * @brief USART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* USART registers base address */
+
+ USART_InitTypeDef Init; /* Usart communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to Usart Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* Usart Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /* Usart Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to Usart Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* Usart Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /* Usart Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* Usart Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* Usart Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_USART_StateTypeDef State; /* Usart communication state */
+
+ __IO uint32_t ErrorCode; /* USART Error code */
+
+}USART_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_Error_Code USART Error Code
+ * @brief USART Error Code
+ * @{
+ */
+#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Word_Length USART Word Length
+ * @{
+ */
+#define USART_WORDLENGTH_8B 0x00000000U
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits
+ * @{
+ */
+#define USART_STOPBITS_1 0x00000000U
+#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity USART Parity
+ * @{
+ */
+#define USART_PARITY_NONE 0x00000000U
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode USART Mode
+ * @{
+ */
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock USART Clock
+ * @{
+ */
+#define USART_CLOCK_DISABLE 0x00000000U
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity USART Clock Polarity
+ * @{
+ */
+#define USART_POLARITY_LOW 0x00000000U
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase USART Clock Phase
+ * @{
+ */
+#define USART_PHASE_1EDGE 0x00000000U
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit USART Last Bit
+ * @{
+ */
+#define USART_LASTBIT_DISABLE 0x00000000U
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+/**
+ * @}
+ */
+
+/** @defgroup USART_NACK_State USART NACK State
+ * @{
+ */
+#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define USART_NACK_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags USART Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define USART_FLAG_TXE 0x00000080U
+#define USART_FLAG_TC 0x00000040U
+#define USART_FLAG_RXNE 0x00000020U
+#define USART_FLAG_IDLE 0x00000010U
+#define USART_FLAG_ORE 0x00000008U
+#define USART_FLAG_NE 0x00000004U
+#define USART_FLAG_FE 0x00000002U
+#define USART_FLAG_PE 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ *
+ * @{
+ */
+#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+
+#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
+
+#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @brief Reset USART handle state
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief Checks whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: Overrun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified Smartcard pending flags.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Clear the USART PE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0U)
+
+/** @brief Clear the USART FE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the USART NE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the USART IDLE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enables or disables the specified USART interrupts.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
+
+/** @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param __HANDLE__ specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @param __IT__ specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
+
+/** @brief Macro to enable the USART's one bit sample method
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Macro to disable the USART's one bit sample method
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief Enable USART
+ * @param __HANDLE__ specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable USART
+ * @param __HANDLE__ specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+/** @brief USART interruptions flag mask
+ *
+ */
+#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
+
+#define USART_CR1_REG_INDEX 1U
+#define USART_CR2_REG_INDEX 2U
+#define USART_CR3_REG_INDEX 3U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
+ * @{
+ */
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
+ ((NACK) == USART_NACK_DISABLE))
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+ ((LASTBIT) == USART_LASTBIT_ENABLE))
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
+ ((CLOCK) == USART_CLOCK_ENABLE))
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
+ ((LENGTH) == USART_WORDLENGTH_9B))
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+ ((STOPBITS) == USART_STOPBITS_0_5) || \
+ ((STOPBITS) == USART_STOPBITS_1_5) || \
+ ((STOPBITS) == USART_STOPBITS_2))
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+ ((PARITY) == USART_PARITY_EVEN) || \
+ ((PARITY) == USART_PARITY_ODD))
+#define IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
+
+#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
+#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,312 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_wwdg.c
+ * @author MCD Application Team
+ * @brief WWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Window Watchdog (WWDG) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State functions
+ @verbatim
+ ==============================================================================
+ ##### WWDG specific features #####
+ ==============================================================================
+ [..]
+ Once enabled the WWDG generates a system reset on expiry of a programmed
+ time period, unless the program refreshes the counter (downcounter)
+ before reaching 0x3F value (i.e. a reset is generated when the counter
+ value rolls over from 0x40 to 0x3F).
+
+ (+) An MCU reset is also generated if the counter value is refreshed
+ before the counter has reached the refresh window value. This
+ implies that the counter must be refreshed in a limited window.
+ (+) Once enabled the WWDG cannot be disabled except by a system reset.
+ (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+ reset occurs.
+ (+) The WWDG counter input clock is derived from the APB clock divided
+ by a programmable prescaler.
+ (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+ (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
+ (+) WWDG Counter refresh is allowed between the following limits :
+ (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
+
+ (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms
+
+ (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
+ operations or data logging must be performed before the actual reset is
+ generated. When the downcounter reaches the value 0x40, an EWI interrupt
+ is generated and the corresponding interrupt service routine (ISR) can
+ be used to trigger specific actions (such as communications or data
+ logging), before resetting the device.
+ In some applications, the EWI interrupt can be used to manage a software
+ system check and/or system recovery/graceful degradation, without
+ generating a WWDG reset. In this case, the corresponding interrupt
+ service routine (ISR) should reload the WWDG counter to avoid the WWDG
+ reset, then trigger the required actions.
+ Note:When the EWI interrupt cannot be served, e.g. due to a system lock
+ in a higher priority task, the WWDG reset will eventually be generated.
+
+ (+) Debug mode : When the microcontroller enters debug mode (core halted),
+ the WWDG counter either continues to work normally or stops, depending
+ on DBG_WWDG_STOP configuration bit in DBG module, accessible through
+ __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+
+ (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
+ Interrupt mode using using HAL_WWDG_Init() function.
+ This enables WWDG peripheral and the downcounter starts downcounting
+ from given counter value.
+ Init function can be called again to modify all watchdog parameters,
+ however if EWI mode has been set once, it can't be clear until next
+ reset.
+
+ (+) The application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset using
+ HAL_WWDG_Refresh() function. This operation must occur only when
+ the counter is lower than the window value already programmed.
+
+ (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
+ the counter reaches 0x40. User can add his own code in weak function
+ HAL_WWDG_EarlyWakeupCallback().
+
+ *** WWDG HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in WWDG HAL driver.
+
+ (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+/** @defgroup WWDG WWDG
+ * @brief WWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and start the WWDG according to the specified parameters
+ in the WWDG_InitTypeDef of associated handle.
+ (+) Initialize the WWDG MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the WWDG according to the specified.
+ * parameters in the WWDG_InitTypeDef of associated handle.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check the WWDG handle allocation */
+ if(hwwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+ assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+ assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+ assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+ assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+ /* Init the low level hardware */
+ HAL_WWDG_MspInit(hwwdg);
+
+ /* Set WWDG Counter */
+ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
+
+ /* Set WWDG Prescaler and Window */
+ WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the WWDG MSP.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @note When rewriting this function in user file, mechanism may be added
+ * to avoid multiple initialize when HAL_WWDG_Init function is called
+ * again to change parameters.
+ * @retval None
+ */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Refresh the WWDG.
+ (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the WWDG.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Write to WWDG CR the WWDG Counter value to refresh with */
+ WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle WWDG interrupt request.
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+ * or data logging must be performed before the actual reset is generated.
+ * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
+ * EWIMode set to WWDG_EWI_ENABLE.
+ * When the downcounter reaches the value 0x40, and EWI interrupt is
+ * generated and the corresponding Interrupt Service Routine (ISR) can
+ * be used to trigger specific actions (such as communications or data
+ * logging), before resetting the device.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check if Early Wakeup Interrupt is enable */
+ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+ {
+ /* Check if WWDG Early Wakeup Interrupt occurred */
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
+ /* Clear the WWDG Early Wakeup flag */
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+ /* Early Wakeup callback */
+ HAL_WWDG_EarlyWakeupCallback(hwwdg);
+ }
+ }
+}
+
+/**
+ * @brief WWDG Early Wakeup callback.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,281 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_wwdg.h
+ * @author MCD Application Team
+ * @brief Header file of WWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_WWDG_H
+#define __STM32F4xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief WWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ This parameter can be a value of @ref WWDG_Prescaler */
+
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
+ This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+ uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+ This parameter can be a value of @ref WWDG_EWI_Mode */
+
+}WWDG_InitTypeDef;
+
+/**
+ * @brief WWDG handle Structure definition
+ */
+typedef struct
+{
+ WWDG_TypeDef *Instance; /*!< Register base address */
+
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+}WWDG_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+ * @{
+ */
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+ * @brief WWDG Flag definition
+ * @{
+ */
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Prescaler WWDG Prescaler
+ * @{
+ */
+#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+ * @{
+ */
+#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */
+#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+ * @{
+ */
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8))
+
+#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
+
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
+ ((__MODE__) == WWDG_EWI_DISABLE))
+/**
+ * @}
+ */
+
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enables the WWDG peripheral.
+ * @param __HANDLE__ WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+
+/**
+ * @brief Enables the WWDG early wakeup interrupt.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+ * @brief Checks whether the selected WWDG interrupt has occurred or not.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the it to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+
+/** @brief Clear the WWDG's interrupt pending bits
+ * bits to clear the selected interrupt pending bits.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified WWDG flag is set or not.
+ * @param __HANDLE__ WWDG handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the WWDG's pending flags.
+ * @param __HANDLE__ WWDG handle
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval None
+ */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
+
+/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
+ * @param __HANDLE__ WWDG Handle.
+ * @param __INTERRUPT__ specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early Wakeup Interrupt
+ * @retval state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,932 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_adc.c
+ * @author MCD Application Team
+ * @brief ADC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_adc.h"
+#include "stm32f4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* common to several ADC instances. */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
+ ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
+ ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
+ )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
+ ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
+ )
+
+#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
+ ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
+ || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
+ )
+
+#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
+ ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
+ || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ )
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
+ )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
+ )
+
+#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
+ ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
+ || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group injected */
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ )
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
+ ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
+ )
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
+ ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
+ )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* multimode. */
+#if defined(ADC3)
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
+ ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
+ )
+#else
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
+ ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
+ )
+#endif
+
+#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
+ ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
+ )
+
+#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
+ ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
+ )
+
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
+ ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
+ )
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+
+ /* Force reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of ADC common parameters
+ * (all ADC instances belonging to the same ADC common instance)
+ * and multimode (for devices with several ADC instances available).
+ * @note The setting of ADC common parameters is conditioned to
+ * ADC instances state:
+ * All ADC instances belonging to the same ADC common instance
+ * must be disabled.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are initialized
+ * - ERROR: ADC common registers are not initialized
+ */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+ assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
+ if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+ {
+ assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
+ assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Note: Hardware constraint (refer to description of functions */
+ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
+ /* On this STM32 serie, setting of these features is conditioned to */
+ /* ADC state: */
+ /* All ADC instances of the ADC common group must be disabled. */
+ if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - common to several ADC */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ /* - Set ADC clock (conversion clock) */
+ /* - multimode (if several ADC instances available on the */
+ /* selected device) */
+ /* - Set ADC multimode configuration */
+ /* - Set ADC multimode DMA transfer */
+ /* - Set ADC multimode: delay between 2 sampling phases */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+ {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_ADCPRE
+ | ADC_CCR_MULTI
+ | ADC_CCR_DMA
+ | ADC_CCR_DDS
+ | ADC_CCR_DELAY
+ ,
+ ADC_CommonInitStruct->CommonClock
+ | ADC_CommonInitStruct->Multimode
+ | ADC_CommonInitStruct->MultiDMATransfer
+ | ADC_CommonInitStruct->MultiTwoSamplingDelay
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_ADCPRE
+ | ADC_CCR_MULTI
+ | ADC_CCR_DMA
+ | ADC_CCR_DDS
+ | ADC_CCR_DELAY
+ ,
+ ADC_CommonInitStruct->CommonClock
+ | LL_ADC_MULTI_INDEPENDENT
+ );
+ }
+#else
+ LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
+#endif
+ }
+ else
+ {
+ /* Initialization error: One or several ADC instances belonging to */
+ /* the same ADC common instance are not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ /* Set ADC_CommonInitStruct fields to default values */
+ /* Set fields of ADC common */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Set fields of ADC multimode */
+ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
+ ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
+ ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @param ADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 1U)
+ {
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+ /* Set ADC group injected trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
+
+ /* Disable the ADC instance */
+ LL_ADC_Disable(ADCx);
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ /* (hardware requirements of bits state to reset registers below) */
+ if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register SR */
+ CLEAR_BIT(ADCx->SR,
+ ( LL_ADC_FLAG_STRT
+ | LL_ADC_FLAG_JSTRT
+ | LL_ADC_FLAG_EOCS
+ | LL_ADC_FLAG_OVR
+ | LL_ADC_FLAG_JEOS
+ | LL_ADC_FLAG_AWD1 )
+ );
+
+ /* Reset register CR1 */
+ CLEAR_BIT(ADCx->CR1,
+ ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
+ | ADC_CR1_JAWDEN
+ | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
+ | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
+ | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
+ | ADC_CR1_AWDCH )
+ );
+
+ /* Reset register CR2 */
+ CLEAR_BIT(ADCx->CR2,
+ ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
+ | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
+ | ADC_CR2_ALIGN | ADC_CR2_EOCS
+ | ADC_CR2_DDS | ADC_CR2_DMA
+ | ADC_CR2_CONT | ADC_CR2_ADON )
+ );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(ADCx->SMPR1,
+ ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
+ | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
+ | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
+ );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(ADCx->SMPR2,
+ ( ADC_SMPR2_SMP9
+ | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
+ | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
+ | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
+ );
+
+ /* Reset register JOFR1 */
+ CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
+ /* Reset register JOFR2 */
+ CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
+ /* Reset register JOFR3 */
+ CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
+ /* Reset register JOFR4 */
+ CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
+
+ /* Reset register HTR */
+ SET_BIT(ADCx->HTR, ADC_HTR_HT);
+ /* Reset register LTR */
+ CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(ADCx->SQR1,
+ ( ADC_SQR1_L
+ | ADC_SQR1_SQ16
+ | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
+ );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(ADCx->SQR2,
+ ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
+ | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
+ );
+
+
+ /* Reset register JSQR */
+ CLEAR_BIT(ADCx->JSQR,
+ ( ADC_JSQR_JL
+ | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
+ | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
+ );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset register CCR */
+ CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
+ assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+ assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC data resolution */
+ /* - Set ADC conversion data alignment */
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_RES
+ | ADC_CR1_SCAN
+ ,
+ ADC_InitStruct->Resolution
+ | ADC_InitStruct->SequencersScanMode
+ );
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_ALIGN
+ ,
+ ADC_InitStruct->DataAlignment
+ );
+
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ /* Set ADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
+ ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+
+ /* Enable scan mode to have a generic behavior with ADC of other */
+ /* STM32 families, without this setting available: */
+ /* ADC group regular sequencer and ADC group injected sequencer depend */
+ /* only of their own configuration. */
+ ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
+
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_DISCEN
+ | ADC_CR1_DISCNUM
+ ,
+ ADC_REG_InitStruct->SequencerLength
+ | ADC_REG_InitStruct->SequencerDiscont
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_DISCEN
+ | ADC_CR1_DISCNUM
+ ,
+ ADC_REG_InitStruct->SequencerLength
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ );
+ }
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_EXTSEL
+ | ADC_CR2_EXTEN
+ | ADC_CR2_CONT
+ | ADC_CR2_DMA
+ | ADC_CR2_DDS
+ ,
+ (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ );
+
+ /* Set ADC group regular sequencer length and scan direction */
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* Note: If ADC instance feature scan mode is disabled */
+ /* (refer to ADC instance initialization structure */
+ /* parameter @ref SequencersScanMode */
+ /* or function @ref LL_ADC_SetSequencersScanMode() ), */
+ /* this parameter is discarded. */
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ /* Set ADC_REG_InitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_JDISCEN
+ | ADC_CR1_JAUTO
+ ,
+ ADC_INJ_InitStruct->SequencerDiscont
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_JDISCEN
+ | ADC_CR1_JAUTO
+ ,
+ LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_JEXTSEL
+ | ADC_CR2_JEXTEN
+ ,
+ (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
+ );
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* Note: If ADC instance feature scan mode is disabled */
+ /* (refer to ADC instance initialization structure */
+ /* parameter @ref SequencersScanMode */
+ /* or function @ref LL_ADC_SetSequencersScanMode() ), */
+ /* this parameter is discarded. */
+ LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ /* Set ADC_INJ_InitStruct fields to default values */
+ /* Set fields of ADC group injected */
+ ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
+ ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+ ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+ ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,4760 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_ADC_H
+#define __STM32F4xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3)
+
+/** @defgroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Internal mask for ADC group regular sequencer: */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
+/* - sequencer register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET 0x00000000U
+#define ADC_SQR2_REGOFFSET 0x00000100U
+#define ADC_SQR3_REGOFFSET 0x00000200U
+#define ADC_SQR4_REGOFFSET 0x00000300U
+
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted */
+/* into ADC group regular sequencer ranks literals definition. */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
+
+/* Internal mask for ADC group injected sequencer: */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
+/* - data register offset */
+/* - offset register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET 0x00000000U
+#define ADC_JDR2_REGOFFSET 0x00000100U
+#define ADC_JDR3_REGOFFSET 0x00000200U
+#define ADC_JDR4_REGOFFSET 0x00000300U
+
+/* Internal register offset for ADC group injected offset configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JOFR1_REGOFFSET 0x00000000U
+#define ADC_JOFR2_REGOFFSET 0x00001000U
+#define ADC_JOFR3_REGOFFSET 0x00002000U
+#define ADC_JOFR4_REGOFFSET 0x00003000U
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Internal mask for ADC group regular trigger: */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
+/* - regular trigger source */
+/* - regular trigger edge */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
+ ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \
+ ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \
+ ((ADC_CR2_EXTSEL) >> (4U * 3U)))
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
+
+/* Definition of ADC group regular trigger bits information. */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
+
+
+
+/* Internal mask for ADC group injected trigger: */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
+/* - injected trigger source */
+/* - injected trigger edge */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
+ ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \
+ ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \
+ ((ADC_CR2_JEXTSEL) >> (4U * 3U)))
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
+
+/* Definition of ADC group injected trigger bits information. */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
+
+/* Internal mask for ADC channel: */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
+/* - channel identifier defined by number */
+/* - channel differentiation between external channels (connected to */
+/* GPIO pins) and internal channels (connected to internal paths) */
+/* - channel sampling time defined by SMPRx register offset */
+/* and SMPx bits positions into SMPRx register */
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET 0x00000000U
+#define ADC_SMPR2_REGOFFSET 0x02000000U
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+
+/* Definition of channels ID number information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_NUMBER 0x00000000U
+#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
+#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
+#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
+#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
+#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
+
+/* Definition of channels sampling time information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
+#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
+#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
+#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
+#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
+#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
+#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
+#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
+#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
+#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
+#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
+#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
+#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
+#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
+#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
+#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
+#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
+#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
+#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
+
+/* Internal mask for ADC analog watchdog: */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
+/* (concatenation of multiple bits used in different analog watchdogs, */
+/* (feature of several watchdogs not available on all STM32 families)). */
+/* - analog watchdog 1: monitored channel defined by number, */
+/* selection of ADC group (ADC groups regular and-or injected). */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET 0x00000000U
+
+#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
+#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
+#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
+
+/* ADC registers bits positions */
+#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
+#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+ */
+#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of ADC common parameters
+ * and multimode
+ * (all ADC instances belonging to the same ADC common instance).
+ * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
+ * is conditioned to ADC instances state (all ADC instances
+ * sharing the same ADC common instance):
+ * All ADC instances sharing the same ADC common instance must be
+ * disabled.
+ */
+typedef struct
+{
+ uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
+ This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
+
+ uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
+
+ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t Resolution; /*!< Set ADC resolution.
+ This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+
+ uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
+ This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+ uint32_t SequencersScanMode; /*!< Set ADC scan selection.
+ This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+ @note On this STM32 serie, setting of external trigger edge is performed
+ using function @ref LL_ADC_REG_StartConversionExtTrig().
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+ @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group regular sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+ This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+ Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+ This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+ @note On this STM32 serie, setting of external trigger edge is performed
+ using function @ref LL_ADC_INJ_StartConversionExtTrig().
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+ @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group injected sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+ Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
+#define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
+#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
+#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
+#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
+#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
+#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
+ * @{
+ */
+#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
+ * @{
+ */
+/* List of ADC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
+#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
+ * @{
+ */
+/* Note: Other measurement paths to internal channels may be available */
+/* (connections to other peripherals). */
+/* If they are not listed below, they do not require any specific */
+/* path enable. In this case, Access to measurement path is done */
+/* only by selecting the corresponding ADC internal channel. */
+#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
+#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
+ * @{
+ */
+#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
+ * @{
+ */
+#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
+#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
+#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
+#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
+ * @{
+ */
+#define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
+ * @{
+ */
+#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+* @{
+*/
+#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
+ * @{
+ */
+#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
+ * @{
+ */
+#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */
+#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
+* @{
+*/
+#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
+ * @{
+ */
+#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
+#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
+#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
+ * @{
+ */
+#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+#if defined(ADC3)
+#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
+ * @{
+ */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
+ * @{
+ */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
+ * @{
+ */
+#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
+#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
+/**
+ * @}
+ */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
+ * @note Only ADC IP HW delays are defined in ADC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
+/* not timeout values. */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Indications for estimation of ADC timeout delays, for this */
+/* STM32 serie: */
+/* - ADC enable time: maximum delay is 2us */
+/* (refer to device datasheet, parameter "tSTAB") */
+/* - ADC conversion time: duration depending on ADC clock and ADC */
+/* configuration. */
+/* (refer to device reference manual, section "Timing") */
+
+/* Delay for internal voltage reference stabilization time. */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay for temperature sensor stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals LL_ADC_CHANNEL_x.
+ * @note Example:
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+
+/**
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) <= 9U) \
+ ? ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ : \
+ ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
+ )
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @arg @ref LL_ADC_GROUP_INJECTED
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
+ : \
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
+ : \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
+ )
+
+/**
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to set the value of
+ * analog watchdog threshold high (on 8 bits):
+ * LL_ADC_SetAnalogWDThresholds
+ * (< ADCx param >,
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+ ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
+
+/**
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to get the value of
+ * analog watchdog threshold high (on 8 bits):
+ * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+ * (LL_ADC_RESOLUTION_8B,
+ * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+ ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+ (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+#endif
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#if defined(ADC1) && defined(ADC2) && defined(ADC3)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC123_COMMON)
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC12_COMMON)
+#else
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC1_COMMON)
+#endif
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#if defined(ADC1) && defined(ADC2) && defined(ADC3)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) | \
+ LL_ADC_IsEnabled(ADC3) )
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) )
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (LL_ADC_IsEnabled(ADC1))
+#endif
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
+ (((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
+ )
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 serie, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).
+ * On STM32F4, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).
+ * On STM32F4, refer to device datasheet parameter "V25".
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((( ( \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000) \
+ - \
+ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000) \
+ ) \
+ ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (__TEMPSENSOR_CALX_TEMP__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+ * @{
+ */
+/* Note: LL ADC functions to set DMA transfer are located into sections of */
+/* configuration of ADC instance, groups and multimode (if available): */
+/* @ref LL_ADC_REG_SetDMATransfer(), ... */
+
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+ * (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+ *
+ * (1) Available on devices with several ADC instances.
+ * @retval ADC register address
+ */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ register uint32_t data_reg_addr = 0U;
+
+ if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+ {
+ /* Retrieve address of register DR */
+ data_reg_addr = (uint32_t)&(ADCx->DR);
+ }
+ else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+ {
+ /* Retrieve address of register CDR */
+ data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+ }
+
+ return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ /* Retrieve address of register DR */
+ return (uint32_t)&(ADCx->DR);
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+ * @{
+ */
+
+/**
+ * @brief Set parameter common to several ADC: Clock source and prescaler.
+ * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param CommonClock This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
+}
+
+/**
+ * @brief Get parameter common to several ADC: Clock source and prescaler.
+ * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
+ * CCR VBATE LL_ADC_SetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
+}
+
+/**
+ * @brief Get parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
+ * CCR VBATE LL_ADC_GetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Set ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR1 RES LL_ADC_SetResolution
+ * @param ADCx ADC instance
+ * @param Resolution This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
+}
+
+/**
+ * @brief Get ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR1 RES LL_ADC_GetResolution
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
+}
+
+/**
+ * @brief Set ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @param DataAlignment This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
+}
+
+/**
+ * @brief Get ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
+}
+
+/**
+ * @brief Set ADC sequencers scan mode, for all ADC groups
+ * (group regular, group injected).
+ * @note According to sequencers scan mode :
+ * - If disabled: ADC conversion is performed in unitary conversion
+ * mode (one channel converted, that defined in rank 1).
+ * Configuration of sequencers of all ADC groups
+ * (sequencer scan length, ...) is discarded: equivalent to
+ * scan length of 1 rank.
+ * - If enabled: ADC conversions are performed in sequence conversions
+ * mode, according to configuration of sequencers of
+ * each ADC group (sequencer scan length, ...).
+ * Refer to function @ref LL_ADC_REG_SetSequencerLength()
+ * and to function @ref LL_ADC_INJ_SetSequencerLength().
+ * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
+ * @param ADCx ADC instance
+ * @param ScanMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
+}
+
+/**
+ * @brief Get ADC sequencers scan mode, for all ADC groups
+ * (group regular, group injected).
+ * @note According to sequencers scan mode :
+ * - If disabled: ADC conversion is performed in unitary conversion
+ * mode (one channel converted, that defined in rank 1).
+ * Configuration of sequencers of all ADC groups
+ * (sequencer scan length, ...) is discarded: equivalent to
+ * scan length of 1 rank.
+ * - If enabled: ADC conversions are performed in sequence conversions
+ * mode, according to configuration of sequencers of
+ * each ADC group (sequencer scan length, ...).
+ * Refer to function @ref LL_ADC_REG_SetSequencerLength()
+ * and to function @ref LL_ADC_INJ_SetSequencerLength().
+ * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, setting of external trigger edge is performed
+ * using function @ref LL_ADC_REG_StartConversionExtTrig().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
+ * CR2 EXTEN LL_ADC_REG_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 serie, ADC group regular external trigger edge */
+/* is used to perform a ADC conversion start. */
+/* This function does not set external trigger edge. */
+/* This feature is set using function */
+/* @ref LL_ADC_REG_StartConversionExtTrig(). */
+ MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
+ * CR2 EXTEN LL_ADC_REG_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
+ register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
+
+ /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
+ /* to match with triggers literals definition. */
+ return ((TriggerSource
+ & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
+ | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
+ );
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @note On this STM32 serie, setting of external trigger edge is performed
+ * using function @ref LL_ADC_REG_StartConversionExtTrig().
+ * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
+}
+
+
+/**
+ * @brief Set ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note On this STM32 serie, group regular sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note On this STM32 serie, group regular sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
+ * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
+ * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register and register position depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ return (uint32_t) (READ_BIT(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
+ );
+}
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
+ * @param ADCx ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
+}
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
+}
+
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
+ * CR2 DDS LL_ADC_REG_SetDMATransfer
+ * @param ADCx ADC instance
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
+}
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
+ * CR2 DDS LL_ADC_REG_GetDMATransfer
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
+}
+
+/**
+ * @brief Specify which ADC flag between EOC (end of unitary conversion)
+ * or EOS (end of sequence conversions) is used to indicate
+ * the end of conversion.
+ * @note This feature is aimed to be set when using ADC with
+ * programming model by polling or interruption
+ * (programming model by DMA usually uses DMA interruptions
+ * to indicate end of conversion and data transfer).
+ * @note For ADC group injected, end of conversion (flag&IT) is raised
+ * only at the end of the sequence.
+ * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
+ * @param ADCx ADC instance
+ * @param EocSelection This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
+ * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
+}
+
+/**
+ * @brief Get which ADC flag between EOC (end of unitary conversion)
+ * or EOS (end of sequence conversions) is used to indicate
+ * the end of conversion.
+ * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
+ * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, setting of external trigger edge is performed
+ * using function @ref LL_ADC_INJ_StartConversionExtTrig().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
+ * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 serie, ADC group injected external trigger edge */
+/* is used to perform a ADC conversion start. */
+/* This function does not set external trigger edge. */
+/* This feature is set using function */
+/* @ref LL_ADC_INJ_StartConversionExtTrig(). */
+ MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
+ * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
+ register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
+
+ /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
+ /* to match with triggers literals definition. */
+ return ((TriggerSource
+ & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
+ | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
+}
+
+/**
+ * @brief Set ADC group injected sequencer length and scan direction.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note On this STM32 serie, group injected sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note On this STM32 serie, group injected sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
+}
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
+
+ MODIFY_REG(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
+}
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
+
+ return (uint32_t)(READ_BIT(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
+ >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
+ );
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept (not erased by successive conversions of scan of
+ * ADC sequencer ranks), up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * in this case, ADC group injected is controlled only
+ * from ADC group regular.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
+ * @param ADCx ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
+}
+
+/**
+ * @brief Set ADC group injected offset.
+ * @note It sets:
+ * - ADC group injected rank to which the offset programmed
+ * will be applied
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note Offset cannot be enabled or disabled.
+ * To emulate offset disabled, set an offset value equal to 0.
+ * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
+ * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
+ * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
+ * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_JOFR1_JOFFSET1,
+ OffsetLevel);
+}
+
+/**
+ * @brief Get ADC group injected offset.
+ * @note It gives offset level (offset to be subtracted from the raw converted data).
+ * Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
+ * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
+ * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
+ * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JOFR1_JOFFSET1)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+ * @{
+ */
+
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * Refer to reference manual for ADC processing time of
+ * this STM32 serie.
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+ /* Set bits with content of parameter "SamplingTime" with bits position */
+ /* in register and register position depending on parameter "Channel". */
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
+ SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * Refer to reference manual for ADC processing time of
+ * this STM32 serie.
+ * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
+ * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
+ >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+ * @{
+ */
+
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel or all channels,
+ * on ADC groups regular and-or injected.
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
+ * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
+ * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDChannelGroup This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ *
+ * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
+ * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
+{
+ MODIFY_REG(ADCx->CR1,
+ (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
+ AWDChannelGroup);
+}
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Applicable only when the analog watchdog is set to monitor
+ * one channel.
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
+ * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
+ * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
+}
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
+ * LTR LT LL_ADC_SetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+
+ MODIFY_REG(*preg,
+ ADC_HTR_HT,
+ AWDThresholdValue);
+}
+
+/**
+ * @brief Get ADC analog watchdog threshold value of threshold high or
+ * threshold low.
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+ * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
+ * LTR LT LL_ADC_GetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+
+ return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+ * @{
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Set ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @rmtoll CCR MULTI LL_ADC_SetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param Multimode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
+}
+
+/**
+ * @brief Get ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @rmtoll CCR MULTI LL_ADC_GetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
+}
+
+/**
+ * @brief Set ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
+ * CCR DDS LL_ADC_SetMultiDMATransfer
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiDMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
+}
+
+/**
+ * @brief Get ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
+ * CCR DDS LL_ADC_GetMultiDMATransfer
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
+}
+
+/**
+ * @brief Set ADC multimode delay between 2 sampling phases.
+ * @note The sampling delay range depends on ADC resolution:
+ * - ADC resolution 12 bits can have maximum delay of 12 cycles.
+ * - ADC resolution 10 bits can have maximum delay of 10 cycles.
+ * - ADC resolution 8 bits can have maximum delay of 8 cycles.
+ * - ADC resolution 6 bits can have maximum delay of 6 cycles.
+ * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiTwoSamplingDelay This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+ * @brief Get ADC multimode delay between 2 sampling phases.
+ * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Enable the selected ADC instance.
+ * @note On this STM32 serie, after ADC enable, a delay for
+ * ADC internal analog stabilization is required before performing a
+ * ADC conversion start.
+ * Refer to device datasheet, parameter tSTAB.
+ * @rmtoll CR2 ADON LL_ADC_Enable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+ * @brief Disable the selected ADC instance.
+ * @rmtoll CR2 ADON LL_ADC_Disable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+ * @brief Get the selected ADC instance enable state.
+ * @rmtoll CR2 ADON LL_ADC_IsEnabled
+ * @param ADCx ADC instance
+ * @retval 0: ADC is disabled, 1: ADC is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Start ADC group regular conversion.
+ * @note On this STM32 serie, this function is relevant only for
+ * internal trigger (SW start), not for external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * start must be performed using function
+ * @ref LL_ADC_REG_StartConversionExtTrig().
+ * (if external trigger edge would have been set during ADC other
+ * settings, ADC conversion would start at trigger event
+ * as soon as ADC is enabled).
+ * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
+}
+
+/**
+ * @brief Start ADC group regular conversion from external trigger.
+ * @note ADC conversion will start at next trigger event (on the selected
+ * trigger edge) following the ADC start conversion command.
+ * @note On this STM32 serie, this function is relevant for
+ * ADC conversion start from external trigger.
+ * If internal trigger (SW start) is needed, perform ADC conversion
+ * start using function @ref LL_ADC_REG_StartConversionSWStart().
+ * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ SET_BIT(ADCx->CR2, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Stop ADC group regular conversion from external trigger.
+ * @note No more ADC conversion will start at next trigger event
+ * following the ADC stop conversion command.
+ * If a conversion is on-going, it will be completed.
+ * @note On this STM32 serie, there is no specific command
+ * to stop a conversion on-going or to stop ADC converting
+ * in continuous mode. These actions can be performed
+ * using function @ref LL_ADC_Disable().
+ * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 6 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get ADC multimode conversion data of ADC master, ADC slave
+ * or raw data with ADC master and slave concatenated.
+ * @note If raw data with ADC master and slave concatenated is retrieved,
+ * a macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * (however this macro is mainly intended for multimode
+ * transfer by DMA, because this function can do the same
+ * by getting multimode conversion data of ADC master or ADC slave
+ * separately).
+ * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
+ * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ConversionData This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+ ADC_DR_ADC2DATA)
+ >> POSITION_VAL(ConversionData)
+ );
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Start ADC group injected conversion.
+ * @note On this STM32 serie, this function is relevant only for
+ * internal trigger (SW start), not for external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * start must be performed using function
+ * @ref LL_ADC_INJ_StartConversionExtTrig().
+ * (if external trigger edge would have been set during ADC other
+ * settings, ADC conversion would start at trigger event
+ * as soon as ADC is enabled).
+ * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
+}
+
+/**
+ * @brief Start ADC group injected conversion from external trigger.
+ * @note ADC conversion will start at next trigger event (on the selected
+ * trigger edge) following the ADC start conversion command.
+ * @note On this STM32 serie, this function is relevant for
+ * ADC conversion start from external trigger.
+ * If internal trigger (SW start) is needed, perform ADC conversion
+ * start using function @ref LL_ADC_INJ_StartConversionSWStart().
+ * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ SET_BIT(ADCx->CR2, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Stop ADC group injected conversion from external trigger.
+ * @note No more ADC conversion will start at next trigger event
+ * following the ADC stop conversion command.
+ * If a conversion is on-going, it will be completed.
+ * @note On this STM32 serie, there is no specific command
+ * to stop a conversion on-going or to stop ADC converting
+ * in continuous mode. These actions can be performed
+ * using function @ref LL_ADC_Disable().
+ * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint8_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 6 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint8_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+ * @{
+ */
+
+/**
+ * @brief Get flag ADC group regular end of unitary conversion
+ * or end of sequence conversions, depending on
+ * ADC configuration.
+ * @note To configure flag of end of conversion,
+ * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+ * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
+}
+
+/**
+ * @brief Get flag ADC group regular overrun.
+ * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
+}
+
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 1 flag
+ * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+ * @brief Clear flag ADC group regular end of unitary conversion
+ * or end of sequence conversions, depending on
+ * ADC configuration.
+ * @note To configure flag of end of conversion,
+ * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+ * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
+}
+
+/**
+ * @brief Clear flag ADC group regular overrun.
+ * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
+}
+
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion
+ * or end of sequence conversions, depending on
+ * ADC configuration, of the ADC master.
+ * @note To configure flag of end of conversion,
+ * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+ * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion
+ * or end of sequence conversions, depending on
+ * ADC configuration, of the ADC slave 1.
+ * @note To configure flag of end of conversion,
+ * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+ * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion
+ * or end of sequence conversions, depending on
+ * ADC configuration, of the ADC slave 2.
+ * @note To configure flag of end of conversion,
+ * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+ * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
+}
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC master.
+ * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
+ * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
+ * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
+}
+
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+ * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
+ * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
+ * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
+ * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
+}
+
+/**
+ * @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
+ * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
+}
+
+/**
+ * @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
+ * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
+}
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+ * @{
+ */
+
+/**
+ * @brief Enable interruption ADC group regular end of unitary conversion
+ * or end of sequence conversions, depending on
+ * ADC configuration.
+ * @note To configure flag of end of conversion,
+ * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+ * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
+}
+
+/**
+ * @brief Enable ADC group regular interruption overrun.
+ * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
+}
+
+
+/**
+ * @brief Enable interruption ADC group injected end of sequence conversions.
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 1.
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion
+ * or end of sequence conversions, depending on
+ * ADC configuration.
+ * @note To configure flag of end of conversion,
+ * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+ * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
+}
+
+/**
+ * @brief Disable interruption ADC group regular overrun.
+ * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
+}
+
+
+/**
+ * @brief Disable interruption ADC group injected end of sequence conversions.
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 1.
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of unitary conversion
+ * or end of sequence conversions, depending on
+ * ADC configuration.
+ * @note To configure flag of end of conversion,
+ * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+ * (0: interrupt disabled, 1: interrupt enabled)
+ * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
+}
+
+/**
+ * @brief Get state of interruption ADC group regular overrun
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
+}
+
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
+}
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2124 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_bus.h
+ * @author MCD Application Team
+ * @brief Header file of BUS LL module.
+
+ @verbatim
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_BUS_H
+#define __STM32F4xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+ * @{
+ */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
+#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
+#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
+#if defined(GPIOD)
+#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
+#endif /* GPIOD */
+#if defined(GPIOE)
+#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
+#endif /* GPIOE */
+#if defined(GPIOF)
+#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
+#endif /* GPIOG */
+#if defined(GPIOH)
+#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
+#endif /* GPIOH */
+#if defined(GPIOI)
+#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
+#endif /* GPIOI */
+#if defined(GPIOJ)
+#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
+#endif /* GPIOJ */
+#if defined(GPIOK)
+#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
+#endif /* GPIOK */
+#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
+#if defined(RCC_AHB1ENR_BKPSRAMEN)
+#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
+#endif /* RCC_AHB1ENR_BKPSRAMEN */
+#if defined(RCC_AHB1ENR_CCMDATARAMEN)
+#define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN
+#endif /* RCC_AHB1ENR_CCMDATARAMEN */
+#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
+#if defined(RCC_AHB1ENR_RNGEN)
+#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN
+#endif /* RCC_AHB1ENR_RNGEN */
+#if defined(DMA2D)
+#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
+#endif /* DMA2D */
+#if defined(ETH)
+#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
+#endif /* ETH */
+#if defined(USB_OTG_HS)
+#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
+#endif /* USB_OTG_HS */
+#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
+#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
+#if defined(RCC_AHB1LPENR_SRAM2LPEN)
+#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
+#endif /* RCC_AHB1LPENR_SRAM2LPEN */
+#if defined(RCC_AHB1LPENR_SRAM3LPEN)
+#define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN
+#endif /* RCC_AHB1LPENR_SRAM3LPEN */
+/**
+ * @}
+ */
+
+#if defined(RCC_AHB2_SUPPORT)
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#if defined(DCMI)
+#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
+#endif /* DCMI */
+#if defined(CRYP)
+#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
+#endif /* CRYP */
+#if defined(AES)
+#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
+#endif /* AES */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
+#endif /* HASH */
+#if defined(RCC_AHB2ENR_RNGEN)
+#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
+#endif /* RCC_AHB2ENR_RNGEN */
+#if defined(USB_OTG_FS)
+#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
+#endif /* USB_OTG_FS */
+/**
+ * @}
+ */
+#endif /* RCC_AHB2_SUPPORT */
+
+#if defined(RCC_AHB3_SUPPORT)
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#if defined(FSMC_Bank1)
+#define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN
+#endif /* FSMC_Bank1 */
+#if defined(FMC_Bank1)
+#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
+#endif /* FMC_Bank1 */
+#if defined(QUADSPI)
+#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
+#endif /* QUADSPI */
+/**
+ * @}
+ */
+#endif /* RCC_AHB3_SUPPORT */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#if defined(TIM2)
+#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
+#endif /* TIM2 */
+#if defined(TIM3)
+#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
+#endif /* TIM3 */
+#if defined(TIM4)
+#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
+#endif /* TIM4 */
+#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
+#if defined(TIM6)
+#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
+#endif /* TIM6 */
+#if defined(TIM7)
+#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
+#endif /* TIM7 */
+#if defined(TIM12)
+#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
+#endif /* TIM12 */
+#if defined(TIM13)
+#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
+#endif /* TIM13 */
+#if defined(TIM14)
+#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
+#endif /* TIM14 */
+#if defined(LPTIM1)
+#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
+#endif /* LPTIM1 */
+#if defined(RCC_APB1ENR_RTCAPBEN)
+#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN
+#endif /* RCC_APB1ENR_RTCAPBEN */
+#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
+#endif /* SPI2 */
+#if defined(SPI3)
+#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
+#endif /* SPI3 */
+#if defined(SPDIFRX)
+#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
+#endif /* SPDIFRX */
+#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
+#if defined(USART3)
+#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
+#endif /* USART3 */
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
+#endif /* UART4 */
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
+#endif /* UART5 */
+#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
+#if defined(I2C3)
+#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
+#endif /* I2C3 */
+#if defined(FMPI2C1)
+#define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN
+#endif /* FMPI2C1 */
+#if defined(CAN1)
+#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
+#endif /* CAN1 */
+#if defined(CAN2)
+#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
+#endif /* CAN2 */
+#if defined(CAN3)
+#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
+#endif /* CAN3 */
+#if defined(CEC)
+#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
+#endif /* CEC */
+#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
+#if defined(DAC1)
+#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
+#endif /* DAC1 */
+#if defined(UART7)
+#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
+#endif /* UART7 */
+#if defined(UART8)
+#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
+#endif /* UART8 */
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
+#if defined(TIM8)
+#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
+#endif /* TIM8 */
+#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
+#if defined(USART6)
+#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
+#endif /* USART6 */
+#if defined(UART9)
+#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
+#endif /* UART9 */
+#if defined(UART10)
+#define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN
+#endif /* UART10 */
+#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
+#if defined(ADC2)
+#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
+#endif /* ADC2 */
+#if defined(ADC3)
+#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
+#endif /* ADC3 */
+#if defined(SDIO)
+#define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
+#endif /* SDIO */
+#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
+#if defined(SPI4)
+#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
+#endif /* SPI4 */
+#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
+#if defined(RCC_APB2ENR_EXTITEN)
+#define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN
+#endif /* RCC_APB2ENR_EXTITEN */
+#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
+#if defined(TIM10)
+#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
+#endif /* TIM10 */
+#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
+#if defined(SPI5)
+#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
+#endif /* SPI5 */
+#if defined(SPI6)
+#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
+#endif /* SPI6 */
+#if defined(SAI1)
+#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
+#endif /* SAI1 */
+#if defined(SAI2)
+#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
+#endif /* SAI2 */
+#if defined(LTDC)
+#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
+#endif /* LTDC */
+#if defined(DSI)
+#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
+#endif /* DSI */
+#if defined(DFSDM1_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
+#endif /* DFSDM1_Channel0 */
+#if defined(DFSDM2_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN
+#endif /* DFSDM2_Channel0 */
+#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ * @{
+ */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+ * @{
+ */
+
+/**
+ * @brief Enable AHB1 peripherals clock.
+ * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB1ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB1 peripheral clock is enabled or not
+ * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable AHB1 peripherals clock.
+ * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB1 peripherals reset.
+ * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB1 peripherals reset.
+ * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB1 peripheral clocks in low-power mode
+ * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
+ * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB1LPENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable AHB1 peripheral clocks in low-power mode
+ * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
+ * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+#if defined(RCC_AHB2_SUPPORT)
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+ * @{
+ */
+
+/**
+ * @brief Enable AHB2 peripherals clock.
+ * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB2 peripheral clock is enabled or not
+ * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable AHB2 peripherals clock.
+ * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB2 peripherals reset.
+ * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB2 peripherals reset.
+ * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB2 peripheral clocks in low-power mode
+ * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
+ * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
+ * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
+ * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
+ * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
+ * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2LPENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable AHB2 peripheral clocks in low-power mode
+ * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
+ * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
+ * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
+ * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
+ * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
+ * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_AHB2_SUPPORT */
+
+#if defined(RCC_AHB3_SUPPORT)
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+ * @{
+ */
+
+/**
+ * @brief Enable AHB3 peripherals clock.
+ * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB3ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB3 peripheral clock is enabled or not
+ * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable AHB3 peripherals clock.
+ * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB3 peripherals reset.
+ * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB3 peripherals reset.
+ * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB3 peripheral clocks in low-power mode
+ * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
+ * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
+ * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB3LPENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable AHB3 peripheral clocks in low-power mode
+ * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
+ * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
+ * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_AHB3_SUPPORT */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+ * @{
+ */
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1ENR, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @brief Enable APB1 peripheral clocks in low-power mode
+ * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
+ * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1LPENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable APB1 peripheral clocks in low-power mode
+ * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
+ * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1LPENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+ * @{
+ */
+
+/**
+ * @brief Enable APB2 peripherals clock.
+ * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB2 peripheral clock is enabled or not
+ * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB2 peripherals clock.
+ * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+ * @brief Force APB2 peripherals reset.
+ * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB2 peripherals reset.
+ * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Enable APB2 peripheral clocks in low-power mode
+ * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
+ * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2LPENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable APB2 peripheral clocks in low-power mode
+ * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
+ * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2LPENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_BUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,656 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL CORTEX driver contains a set of generic APIs that can be
+ used by user:
+ (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+ functions
+ (+) Low power mode configuration (SCB register of Cortex-MCU)
+ (+) MPU API to configure and enable regions
+ (MPU services provided only on some devices)
+ (+) API to access to MCU info (CPUID register)
+ (+) API to enable fault handler (SHCSR accesses)
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_CORTEX_H
+#define __STM32F4xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX_LL CORTEX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+ * @{
+ */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+ * @{
+ */
+#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+ * @{
+ */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+ * @{
+ */
+#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+ * @{
+ */
+#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+ * @{
+ */
+#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+ * @{
+ */
+#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+ * @{
+ */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+ * @{
+ */
+
+/**
+ * @brief This function checks if the Systick counter flag is active or not.
+ * @note It can be used in timeout function on application side.
+ * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+ return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+ * @brief Configures the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+ if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+ {
+ SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+ else
+ {
+ CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+}
+
+/**
+ * @brief Get the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+ return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+ * @brief Enable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Disable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Checks if the SYSTICK interrupt is enabled or disabled.
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+ return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+ * @{
+ */
+
+/**
+ * @brief Processor uses sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Processor uses deep sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
+ * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+ * empty main application.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Do not sleep when returning to Thread mode.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
+ * processor.
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+ /* Set SEVEONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+ * excluded
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+ /* Clear SEVEONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+ * @{
+ */
+
+/**
+ * @brief Enable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+ /* Enable the system handler fault */
+ SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @brief Disable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+ /* Disable the system handler fault */
+ CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+ * @{
+ */
+
+/**
+ * @brief Get Implementer code
+ * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
+ * @retval Value should be equal to 0x41 for ARM
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+ * @brief Get Variant number (The r value in the rnpn product revision identifier)
+ * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
+ * @retval Value between 0 and 255 (0x0: revision 0)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+ * @brief Get Constant number
+ * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
+ * @retval Value should be equal to 0xF for Cortex-M4 devices
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+ * @brief Get Part number
+ * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
+ * @retval Value should be equal to 0xC24 for Cortex-M4
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+ * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+ * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
+ * @retval Value between 0 and 255 (0x1: patch 1)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+ * @{
+ */
+
+/**
+ * @brief Enable MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
+ * @param Options This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+ /* Enable the MPU*/
+ WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+ /* Ensure MPU settings take effects */
+ __DSB();
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+/**
+ * @brief Disable MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+ * @brief Check if MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+ return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+ * @brief Enable a MPU region
+ * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Enable the MPU region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Configure and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RASR XN LL_MPU_ConfigRegion\n
+ * MPU_RASR AP LL_MPU_ConfigRegion\n
+ * MPU_RASR S LL_MPU_ConfigRegion\n
+ * MPU_RASR C LL_MPU_ConfigRegion\n
+ * MPU_RASR B LL_MPU_ConfigRegion\n
+ * MPU_RASR SIZE LL_MPU_ConfigRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Address Value of region base address
+ * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+ * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+ * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+ * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+ * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+ * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+ * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+ * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+ * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+ * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+ * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+ /* Configure MPU */
+ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+ * @brief Disable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
+ * MPU_RASR ENABLE LL_MPU_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_crc.c
+ * @author MCD Application Team
+ * @brief CRC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_crc.h"
+#include "stm32f4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize CRC registers (Registers restored to their default values).
+ * @param CRCx CRC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CRC registers are de-initialized
+ * - ERROR: CRC registers are not de-initialized
+ */
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+ if (CRCx == CRC)
+ {
+ /* Force CRC reset */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
+
+ /* Release CRC reset */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (CRC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,210 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_crc.h
+ * @author MCD Application Team
+ * @brief Header file of CRC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_CRC_H
+#define __STM32F4xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Reset the CRC calculation unit.
+ * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
+ * @param CRCx CRC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+ WRITE_REG(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Write given 32-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData32
+ * @param CRCx CRC Instance
+ * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+ * @brief Return current CRC calculation result. 32 bits value is returned.
+ * @rmtoll DR DR LL_CRC_ReadData32
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+ */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+ * @brief Return data stored in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one byte.
+ * @rmtoll IDR IDR LL_CRC_Read_IDR
+ * @param CRCx CRC Instance
+ * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
+ */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+ * @brief Store data in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one byte.
+ * @rmtoll IDR IDR LL_CRC_Write_IDR
+ * @param CRCx CRC Instance
+ * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
+}
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,281 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_dac.c
+ * @author MCD Application Team
+ * @brief DAC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_dac.h"
+#include "stm32f4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(DAC)
+
+/** @addtogroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DAC_LL_Private_Macros
+ * @{
+ */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
+ ( \
+ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
+ )
+#else
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
+ ( \
+ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ )
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
+ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
+ ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
+ )
+
+#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
+ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected DAC instance
+ * to their default reset values.
+ * @param DACx DAC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+
+ /* Force reset of DAC1 clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
+
+ /* Release reset of DAC1 clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of DAC instance.
+ * @note The setting of these parameters by function @ref LL_DAC_Init()
+ * is conditioned to DAC state:
+ * DAC instance must be disabled.
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are initialized
+ * - ERROR: DAC registers are not initialized
+ */
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+ assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
+ assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
+ assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
+ }
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* DAC instance must be disabled. */
+ if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
+ {
+ /* Configuration of DAC channel: */
+ /* - TriggerSource */
+ /* - WaveAutoGeneration */
+ /* - OutputBuffer */
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ MODIFY_REG(DACx->CR,
+ ( DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ | DAC_CR_MAMP1
+ | DAC_CR_BOFF1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ ( DAC_InitStruct->TriggerSource
+ | DAC_InitStruct->WaveAutoGeneration
+ | DAC_InitStruct->WaveAutoGenerationConfig
+ | DAC_InitStruct->OutputBuffer
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ else
+ {
+ MODIFY_REG(DACx->CR,
+ ( DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ | DAC_CR_BOFF1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ ( DAC_InitStruct->TriggerSource
+ | LL_DAC_WAVE_AUTO_GENERATION_NONE
+ | DAC_InitStruct->OutputBuffer
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ }
+ else
+ {
+ /* Initialization error: DAC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
+ * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ /* Set DAC_InitStruct fields to default values */
+ DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
+ DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
+ /* Note: Parameter discarded if wave auto generation is disabled, */
+ /* set anyway to its default value. */
+ DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
+ DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1438 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_dac.h
+ * @author MCD Application Team
+ * @brief Header file of DAC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_DAC_H
+#define __STM32F4xx_LL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(DAC)
+
+/** @defgroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/* Internal masks for DAC channels definition */
+/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
+/* - channel bits position into register CR */
+/* - channel bits position into register SWTRIG */
+/* - channel register offset of data holding register DHRx */
+/* - channel register offset of data output register DORx */
+#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+
+#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
+#else
+#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
+#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+
+#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+#else
+#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/* DAC registers bits positions */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/* Miscellaneous data */
+#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Macros DAC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+*/
+#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
+ * @retval Pointer to register address
+*/
+#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of DAC instance.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+
+ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ @note If waveform automatic generation mode is disabled, this parameter is discarded.
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
+
+ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+
+} LL_DAC_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
+ * @brief Flags defines which can be used with LL_DAC_ReadReg function
+ * @{
+ */
+/* DAC channel 1 flags */
+#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/* DAC channel 2 flags */
+#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_IT DAC interruptions
+ * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
+ * @{
+ */
+#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_CHANNEL DAC channels
+ * @{
+ */
+#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
+ * @{
+ */
+#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
+ * @{
+ */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
+ * @{
+ */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
+ * @{
+ */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
+ * @{
+ */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
+ * @{
+ */
+#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
+ * @{
+ */
+/* List of DAC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
+ * @note Only DAC IP HW delays are defined in DAC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for DAC channel voltage settling time from DAC channel startup */
+/* (transition from disable to enable). */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm (min), 50pF (max) */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tWAKEUP"). */
+/* Unit: us */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
+/* Delay for DAC channel voltage settling time. */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm min, 50pF max */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSETTLING"). */
+/* Unit: us */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get DAC channel number in decimal format
+ * from literals LL_DAC_CHANNEL_x.
+ * Example:
+ * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
+ * will return decimal number "1".
+ * @note The input can be a value from functions where a channel
+ * number is returned.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval 1...2 (value "2" depending on DAC channel 2 availability)
+ */
+#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
+
+/**
+ * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
+ * from number in decimal format.
+ * Example:
+ * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
+ * will return a data equivalent to "LL_DAC_CHANNEL_1".
+ * @note If the input parameter does not correspond to a DAC channel,
+ * this macro returns value '0'.
+ * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) == 1U) \
+ ? ( \
+ LL_DAC_CHANNEL_1 \
+ ) \
+ : \
+ (((__DECIMAL_NB__) == 2U) \
+ ? ( \
+ LL_DAC_CHANNEL_2 \
+ ) \
+ : \
+ ( \
+ 0 \
+ ) \
+ ) \
+ )
+#else
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) == 1U) \
+ ? ( \
+ LL_DAC_CHANNEL_1 \
+ ) \
+ : \
+ ( \
+ 0 \
+ ) \
+ )
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Helper macro to define the DAC conversion data full-scale digital
+ * value corresponding to the selected DAC resolution.
+ * @note DAC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
+
+/**
+ * @brief Helper macro to calculate the DAC conversion data (unit: digital
+ * value) corresponding to a voltage (unit: mVolt).
+ * @note This helper macro is intended to provide input data in voltage
+ * rather than digital value,
+ * to be used with LL DAC functions such as
+ * @ref LL_DAC_ConvertData12RightAligned().
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
+ * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
+ * (unit: mVolt).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval DAC conversion data (unit: digital value)
+ */
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
+ __DAC_VOLTAGE__,\
+ __DAC_RESOLUTION__) \
+ ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
+ * @{
+ */
+/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
+ * @{
+ */
+
+/**
+ * @brief Set the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note To set conversion trigger source, DAC channel must be disabled.
+ * Otherwise, the setting is discarded.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
+ * CR TSEL2 LL_DAC_SetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
+ * CR TSEL2 LL_DAC_GetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_SetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param WaveAutoGeneration This parameter can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_GetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param NoiseLFSRMask This parameter can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Set the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param TriangleAmplitude This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Set the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the output buffer for the selected DAC channel.
+ * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
+ * CR BOFF2 LL_DAC_SetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param OutputBuffer This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the output buffer state for the selected DAC channel.
+ * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
+ * CR BOFF2 LL_DAC_GetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
+ * CR DMAEN2 LL_DAC_EnableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
+ * CR DMAEN2 LL_DAC_DisableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC DMA transfer request state of the selected channel.
+ * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
+ * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
+ * CR DMAEN2 LL_DAC_IsDMAReqEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Function to help to configure DMA transfer to DAC: retrieve the
+ * DAC register address from DAC instance and a list of DAC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These DAC registers are data holding registers:
+ * when DAC conversion is requested, DAC generates a DMA transfer
+ * request to have data available in DAC data holding registers.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * (uint32_t)&< array or variable >,
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
+ * @retval DAC register address
+ */
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+{
+ /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
+ /* DAC channel selected. */
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
+}
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
+ * @{
+ */
+
+/**
+ * @brief Enable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Enable\n
+ * CR EN2 LL_DAC_Enable
+ * @note After enable from off state, DAC channel requires a delay
+ * for output voltage to reach accuracy +/- 1 LSB.
+ * Refer to device datasheet, parameter "tWAKEUP".
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Disable\n
+ * CR EN2 LL_DAC_Disable
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC enable state of the selected channel.
+ * (0: DAC channel is disabled, 1: DAC channel is enabled)
+ * @rmtoll CR EN1 LL_DAC_IsEnabled\n
+ * CR EN2 LL_DAC_IsEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Enable DAC trigger of the selected channel.
+ * @note - If DAC trigger is disabled, DAC conversion is performed
+ * automatically once the data holding register is updated,
+ * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...
+ * - If DAC trigger is enabled, DAC conversion is performed
+ * only when a hardware of software trigger event is occurring.
+ * Select trigger source using
+ * function @ref LL_DAC_SetTriggerSource().
+ * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
+ * CR TEN2 LL_DAC_EnableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC trigger of the selected channel.
+ * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
+ * CR TEN2 LL_DAC_DisableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC trigger state of the selected channel.
+ * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
+ * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
+ * CR TEN2 LL_DAC_IsTriggerEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Trig DAC conversion by software for the selected DAC channel.
+ * @note Preliminarily, DAC trigger must be set to software trigger
+ * using function @ref LL_DAC_SetTriggerSource()
+ * with parameter "LL_DAC_TRIGGER_SOFTWARE".
+ * and DAC trigger must be enabled using
+ * function @ref LL_DAC_EnableTrigger().
+ * @note For devices featuring DAC with 2 channels: this function
+ * can perform a SW start of both DAC channels simultaneously.
+ * Two channels can be selected as parameter.
+ * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
+ * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
+ * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can a combination of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->SWTRIGR,
+ (DAC_Channel & DAC_SWTR_CHX_MASK));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
+ * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR12R1_DACC1DHR,
+ Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for the selected DAC channel.
+ * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
+ * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR12L1_DACC1DHR,
+ Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
+ * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR8R1_DACC1DHR,
+ Data);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
+ * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR12RD,
+ (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for both DAC channels.
+ * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
+ * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
+ /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
+ /* the 4 LSB must be taken into account for the shift value. */
+ MODIFY_REG(DACx->DHR12LD,
+ (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
+ ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
+ * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR8RD,
+ (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @brief Retrieve output data currently generated for the selected DAC channel.
+ * @note Whatever alignment and resolution settings
+ * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...),
+ * output data format is 12 bits right aligned (LSB aligned on bit 0).
+ * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
+ * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
+
+ return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+/**
+ * @brief Get DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Get DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Clear DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Clear DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_IT_Management IT management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
+void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,441 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_dma.c
+ * @author MCD Application Team
+ * @brief DMA LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_dma.h"
+#include "stm32f4xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+ ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
+ ((__VALUE__) == LL_DMA_MODE_PFCTRL))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
+ ((__VALUE__) == LL_DMA_CHANNEL_1) || \
+ ((__VALUE__) == LL_DMA_CHANNEL_2) || \
+ ((__VALUE__) == LL_DMA_CHANNEL_3) || \
+ ((__VALUE__) == LL_DMA_CHANNEL_4) || \
+ ((__VALUE__) == LL_DMA_CHANNEL_5) || \
+ ((__VALUE__) == LL_DMA_CHANNEL_6) || \
+ ((__VALUE__) == LL_DMA_CHANNEL_7))
+
+#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
+ (((STREAM) == LL_DMA_STREAM_0) || \
+ ((STREAM) == LL_DMA_STREAM_1) || \
+ ((STREAM) == LL_DMA_STREAM_2) || \
+ ((STREAM) == LL_DMA_STREAM_3) || \
+ ((STREAM) == LL_DMA_STREAM_4) || \
+ ((STREAM) == LL_DMA_STREAM_5) || \
+ ((STREAM) == LL_DMA_STREAM_6) || \
+ ((STREAM) == LL_DMA_STREAM_7) || \
+ ((STREAM) == LL_DMA_STREAM_ALL))) ||\
+ (((INSTANCE) == DMA2) && \
+ (((STREAM) == LL_DMA_STREAM_0) || \
+ ((STREAM) == LL_DMA_STREAM_1) || \
+ ((STREAM) == LL_DMA_STREAM_2) || \
+ ((STREAM) == LL_DMA_STREAM_3) || \
+ ((STREAM) == LL_DMA_STREAM_4) || \
+ ((STREAM) == LL_DMA_STREAM_5) || \
+ ((STREAM) == LL_DMA_STREAM_6) || \
+ ((STREAM) == LL_DMA_STREAM_7) || \
+ ((STREAM) == LL_DMA_STREAM_ALL))))
+
+#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
+ ((STATE) == LL_DMA_FIFOMODE_ENABLE))
+
+#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
+ ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
+ ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
+ ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
+
+#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
+ ((BURST) == LL_DMA_MBURST_INC4) || \
+ ((BURST) == LL_DMA_MBURST_INC8) || \
+ ((BURST) == LL_DMA_MBURST_INC16))
+
+#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
+ ((BURST) == LL_DMA_PBURST_INC4) || \
+ ((BURST) == LL_DMA_PBURST_INC8) || \
+ ((BURST) == LL_DMA_PBURST_INC16))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the DMA registers to their default reset values.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @arg @ref LL_DMA_STREAM_ALL
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are de-initialized
+ * - ERROR: DMA registers are not de-initialized
+ */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
+ ErrorStatus status = SUCCESS;
+
+ /* Check the DMA Instance DMAx and Stream parameters*/
+ assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+
+ if (Stream == LL_DMA_STREAM_ALL)
+ {
+ if (DMAx == DMA1)
+ {
+ /* Force reset of DMA clock */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+
+ /* Release reset of DMA clock */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+ }
+ else if (DMAx == DMA2)
+ {
+ /* Force reset of DMA clock */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
+
+ /* Release reset of DMA clock */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ /* Disable the selected Stream */
+ LL_DMA_DisableStream(DMAx,Stream);
+
+ /* Get the DMA Stream Instance */
+ tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
+
+ /* Reset DMAx_Streamy configuration register */
+ LL_DMA_WriteReg(tmp, CR, 0U);
+
+ /* Reset DMAx_Streamy remaining bytes register */
+ LL_DMA_WriteReg(tmp, NDTR, 0U);
+
+ /* Reset DMAx_Streamy peripheral address register */
+ LL_DMA_WriteReg(tmp, PAR, 0U);
+
+ /* Reset DMAx_Streamy memory address register */
+ LL_DMA_WriteReg(tmp, M0AR, 0U);
+
+ /* Reset DMAx_Streamy memory address register */
+ LL_DMA_WriteReg(tmp, M1AR, 0U);
+
+ /* Reset DMAx_Streamy FIFO control register */
+ LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
+
+ /* Reset Channel register field for DMAx Stream*/
+ LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
+
+ if(Stream == LL_DMA_STREAM_0)
+ {
+ /* Reset the Stream0 pending flags */
+ DMAx->LIFCR = 0x0000003FU;
+ }
+ else if(Stream == LL_DMA_STREAM_1)
+ {
+ /* Reset the Stream1 pending flags */
+ DMAx->LIFCR = 0x00000F40U;
+ }
+ else if(Stream == LL_DMA_STREAM_2)
+ {
+ /* Reset the Stream2 pending flags */
+ DMAx->LIFCR = 0x003F0000U;
+ }
+ else if(Stream == LL_DMA_STREAM_3)
+ {
+ /* Reset the Stream3 pending flags */
+ DMAx->LIFCR = 0x0F400000U;
+ }
+ else if(Stream == LL_DMA_STREAM_4)
+ {
+ /* Reset the Stream4 pending flags */
+ DMAx->HIFCR = 0x0000003FU;
+ }
+ else if(Stream == LL_DMA_STREAM_5)
+ {
+ /* Reset the Stream5 pending flags */
+ DMAx->HIFCR = 0x00000F40U;
+ }
+ else if(Stream == LL_DMA_STREAM_6)
+ {
+ /* Reset the Stream6 pending flags */
+ DMAx->HIFCR = 0x003F0000U;
+ }
+ else if(Stream == LL_DMA_STREAM_7)
+ {
+ /* Reset the Stream7 pending flags */
+ DMAx->HIFCR = 0x0F400000U;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+ * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
+ * @arg @ref __LL_DMA_GET_INSTANCE
+ * @arg @ref __LL_DMA_GET_STREAM
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are initialized
+ * - ERROR: Not applicable
+ */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Check the DMA Instance DMAx and Stream parameters*/
+ assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+
+ /* Check the DMA parameters from DMA_InitStruct */
+ assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+ assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+ assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+ assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+ assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+ assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+ assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+ assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
+ assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+ assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
+ /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+ when FIFO mode is enabled */
+ if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+ {
+ assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
+ assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
+ assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
+ }
+
+ /*---------------------------- DMAx SxCR Configuration ------------------------
+ * Configure DMAx_Streamy: data transfer direction, data transfer mode,
+ * peripheral and memory increment mode,
+ * data size alignment and priority level with parameters :
+ * - Direction: DMA_SxCR_DIR[1:0] bits
+ * - Mode: DMA_SxCR_CIRC bit
+ * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
+ * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
+ * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
+ * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
+ * - Priority: DMA_SxCR_PL[1:0] bits
+ */
+ LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
+ DMA_InitStruct->Mode | \
+ DMA_InitStruct->PeriphOrM2MSrcIncMode | \
+ DMA_InitStruct->MemoryOrM2MDstIncMode | \
+ DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+ DMA_InitStruct->MemoryOrM2MDstDataSize | \
+ DMA_InitStruct->Priority
+ );
+
+ if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+ {
+ /*---------------------------- DMAx SxFCR Configuration ------------------------
+ * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
+ * - FIFOMode: DMA_SxFCR_DMDIS bit
+ * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
+ */
+ LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
+
+ /*---------------------------- DMAx SxCR Configuration --------------------------
+ * Configure DMAx_Streamy: memory burst transfer with parameters :
+ * - MemBurst: DMA_SxCR_MBURST[1:0] bits
+ */
+ LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
+
+ /*---------------------------- DMAx SxCR Configuration --------------------------
+ * Configure DMAx_Streamy: peripheral burst transfer with parameters :
+ * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
+ */
+ LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
+ }
+
+ /*-------------------------- DMAx SxM0AR Configuration --------------------------
+ * Configure the memory or destination base address with parameter :
+ * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
+ */
+ LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+ /*-------------------------- DMAx SxPAR Configuration ---------------------------
+ * Configure the peripheral or source base address with parameter :
+ * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
+ */
+ LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+ /*--------------------------- DMAx SxNDTR Configuration -------------------------
+ * Configure the peripheral base address with parameter :
+ * - NbData: DMA_SxNDT[15:0] bits
+ */
+ LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
+
+ /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
+ * Configure the peripheral base address with parameter :
+ * - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
+ */
+ LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
+ * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval None
+ */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Set DMA_InitStruct fields to default values */
+ DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
+ DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
+ DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+ DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
+ DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
+ DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
+ DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+ DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+ DMA_InitStruct->NbData = 0x00000000U;
+ DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
+ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
+ DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
+ DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
+ DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
+ DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2876 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_DMA_H
+#define __STM32F4xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+ * @{
+ */
+/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+static const uint8_t STREAM_OFFSET_TAB[] =
+{
+ (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+};
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
+ or as Source base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
+ or as Destination base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+ uint32_t Mode; /*!< Specifies the normal or circular operation mode.
+ This parameter can be a value of @ref DMA_LL_EC_MODE
+ @note The circular buffer mode cannot be used if the memory to memory
+ data transfer direction is configured on the selected Stream
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+ uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+ uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+ uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
+ The data unit is equal to the source buffer configuration set in PeripheralSize
+ or MemorySize parameters depending in the transfer direction.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+ uint32_t Channel; /*!< Specifies the peripheral channel.
+ This parameter can be a value of @ref DMA_LL_EC_CHANNEL
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
+
+ uint32_t Priority; /*!< Specifies the channel priority level.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
+
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+ This parameter can be a value of @ref DMA_LL_FIFOMODE
+ @note The Direct mode (FIFO mode disabled) cannot be used if the
+ memory-to-memory data transfer is configured on the selected stream
+
+ This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
+
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
+ This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
+
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptible
+ transaction.
+ This parameter can be a value of @ref DMA_LL_EC_MBURST
+ @note The burst mode is possible only if the address Increment mode is enabled.
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
+
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+ It specifies the amount of data to be transferred in a single non interruptible
+ transaction.
+ This parameter can be a value of @ref DMA_LL_EC_PBURST
+ @note The burst mode is possible only if the address Increment mode is enabled.
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+
+} LL_DMA_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_LL_EC_STREAM STREAM
+ * @{
+ */
+#define LL_DMA_STREAM_0 0x00000000U
+#define LL_DMA_STREAM_1 0x00000001U
+#define LL_DMA_STREAM_2 0x00000002U
+#define LL_DMA_STREAM_3 0x00000003U
+#define LL_DMA_STREAM_4 0x00000004U
+#define LL_DMA_STREAM_5 0x00000005U
+#define LL_DMA_STREAM_6 0x00000006U
+#define LL_DMA_STREAM_7 0x00000007U
+#define LL_DMA_STREAM_ALL 0xFFFF0000U
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+ * @{
+ */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MODE MODE
+ * @{
+ */
+#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
+#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
+#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
+ * @{
+ */
+#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
+#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PERIPH PERIPH
+ * @{
+ */
+#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
+#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MEMORY MEMORY
+ * @{
+ */
+#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
+#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+ * @{
+ */
+#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
+#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+ * @{
+ */
+#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
+#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+ * @{
+ */
+#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
+#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+ * @{
+ */
+#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
+#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
+#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
+#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ * @{
+ */
+#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
+#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
+#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
+#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
+#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
+#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
+#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
+#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MBURST MBURST
+ * @{
+ */
+#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
+#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
+#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
+#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PBURST PBURST
+ * @{
+ */
+#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
+#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
+#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
+#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+ * @{
+ */
+#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
+#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+ * @{
+ */
+#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
+#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
+#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
+#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
+#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
+#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+ * @{
+ */
+#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
+#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
+#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
+#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+ * @{
+ */
+#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
+#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+ * @{
+ */
+/**
+ * @brief Convert DMAx_Streamy into DMAx
+ * @param __STREAM_INSTANCE__ DMAx_Streamy
+ * @retval DMAx
+ */
+#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
+(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
+
+/**
+ * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
+ * @param __STREAM_INSTANCE__ DMAx_Streamy
+ * @retval LL_DMA_CHANNEL_y
+ */
+#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
+(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ LL_DMA_STREAM_7)
+
+/**
+ * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+ * @param __DMA_INSTANCE__ DMAx
+ * @param __STREAM__ LL_DMA_STREAM_y
+ * @retval DMAx_Streamy
+ */
+#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
+ DMA2_Stream7)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+ /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable DMA stream.
+ * @rmtoll CR EN LL_DMA_EnableStream
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
+}
+
+/**
+ * @brief Disable DMA stream.
+ * @rmtoll CR EN LL_DMA_DisableStream
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
+}
+
+/**
+ * @brief Check if DMA stream is enabled or disabled.
+ * @rmtoll CR EN LL_DMA_IsEnabledStream
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
+}
+
+/**
+ * @brief Configure all parameters linked to DMA transfer.
+ * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
+ * CR CIRC LL_DMA_ConfigTransfer\n
+ * CR PINC LL_DMA_ConfigTransfer\n
+ * CR MINC LL_DMA_ConfigTransfer\n
+ * CR PSIZE LL_DMA_ConfigTransfer\n
+ * CR MSIZE LL_DMA_ConfigTransfer\n
+ * CR PL LL_DMA_ConfigTransfer\n
+ * CR PFCTRL LL_DMA_ConfigTransfer
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
+ * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+ * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+ *@retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
+ DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
+ Configuration);
+}
+
+/**
+ * @brief Set Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
+}
+
+/**
+ * @brief Get Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
+}
+
+/**
+ * @brief Set DMA mode normal, circular or peripheral flow control.
+ * @rmtoll CR CIRC LL_DMA_SetMode\n
+ * CR PFCTRL LL_DMA_SetMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ * @arg @ref LL_DMA_MODE_PFCTRL
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
+}
+
+/**
+ * @brief Get DMA mode normal, circular or peripheral flow control.
+ * @rmtoll CR CIRC LL_DMA_GetMode\n
+ * CR PFCTRL LL_DMA_GetMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ * @arg @ref LL_DMA_MODE_PFCTRL
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
+}
+
+/**
+ * @brief Set Peripheral increment mode.
+ * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param IncrementMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
+}
+
+/**
+ * @brief Get Peripheral increment mode.
+ * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
+}
+
+/**
+ * @brief Set Memory increment mode.
+ * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param IncrementMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
+}
+
+/**
+ * @brief Get Memory increment mode.
+ * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
+}
+
+/**
+ * @brief Set Peripheral size.
+ * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Size This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
+}
+
+/**
+ * @brief Get Peripheral size.
+ * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
+}
+
+/**
+ * @brief Set Memory size.
+ * @rmtoll CR MSIZE LL_DMA_SetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Size This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
+}
+
+/**
+ * @brief Get Memory size.
+ * @rmtoll CR MSIZE LL_DMA_GetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
+}
+
+/**
+ * @brief Set Peripheral increment offset size.
+ * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param OffsetSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+ * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
+}
+
+/**
+ * @brief Get Peripheral increment offset size.
+ * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+ * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
+}
+
+/**
+ * @brief Set Stream priority level.
+ * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Priority This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
+}
+
+/**
+ * @brief Get Stream priority level.
+ * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
+}
+
+/**
+ * @brief Set Number of data to transfer.
+ * @rmtoll NDTR NDT LL_DMA_SetDataLength
+ * @note This action has no effect if
+ * stream is enabled.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param NbData Between 0 to 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
+}
+
+/**
+ * @brief Get Number of data to transfer.
+ * @rmtoll NDTR NDT LL_DMA_GetDataLength
+ * @note Once the stream is enabled, the return value indicate the
+ * remaining bytes to be transmitted.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Between 0 to 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
+}
+
+/**
+ * @brief Select Channel number associated to the Stream.
+ * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
+}
+
+/**
+ * @brief Get the Channel number associated to the Stream.
+ * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_0
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
+}
+
+/**
+ * @brief Set Memory burst transfer configuration.
+ * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Mburst This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MBURST_SINGLE
+ * @arg @ref LL_DMA_MBURST_INC4
+ * @arg @ref LL_DMA_MBURST_INC8
+ * @arg @ref LL_DMA_MBURST_INC16
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
+}
+
+/**
+ * @brief Get Memory burst transfer configuration.
+ * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MBURST_SINGLE
+ * @arg @ref LL_DMA_MBURST_INC4
+ * @arg @ref LL_DMA_MBURST_INC8
+ * @arg @ref LL_DMA_MBURST_INC16
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
+}
+
+/**
+ * @brief Set Peripheral burst transfer configuration.
+ * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Pburst This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PBURST_SINGLE
+ * @arg @ref LL_DMA_PBURST_INC4
+ * @arg @ref LL_DMA_PBURST_INC8
+ * @arg @ref LL_DMA_PBURST_INC16
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
+}
+
+/**
+ * @brief Get Peripheral burst transfer configuration.
+ * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PBURST_SINGLE
+ * @arg @ref LL_DMA_PBURST_INC4
+ * @arg @ref LL_DMA_PBURST_INC8
+ * @arg @ref LL_DMA_PBURST_INC16
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
+}
+
+/**
+ * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+ * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param CurrentMemory This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CURRENTTARGETMEM0
+ * @arg @ref LL_DMA_CURRENTTARGETMEM1
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
+}
+
+/**
+ * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+ * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_CURRENTTARGETMEM0
+ * @arg @ref LL_DMA_CURRENTTARGETMEM1
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
+}
+
+/**
+ * @brief Enable the double buffer mode.
+ * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
+}
+
+/**
+ * @brief Disable the double buffer mode.
+ * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
+}
+
+/**
+ * @brief Get FIFO status.
+ * @rmtoll FCR FS LL_DMA_GetFIFOStatus
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_FIFOSTATUS_0_25
+ * @arg @ref LL_DMA_FIFOSTATUS_25_50
+ * @arg @ref LL_DMA_FIFOSTATUS_50_75
+ * @arg @ref LL_DMA_FIFOSTATUS_75_100
+ * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+ * @arg @ref LL_DMA_FIFOSTATUS_FULL
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
+}
+
+/**
+ * @brief Disable Fifo mode.
+ * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+ * @brief Enable Fifo mode.
+ * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+ * @brief Select FIFO threshold.
+ * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
+}
+
+/**
+ * @brief Get FIFO threshold.
+ * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
+}
+
+/**
+ * @brief Configure the FIFO .
+ * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
+ * FCR DMDIS LL_DMA_ConfigFifo
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param FifoMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_FIFOMODE_ENABLE
+ * @arg @ref LL_DMA_FIFOMODE_DISABLE
+ * @param FifoThreshold This parameter can be one of the following values:
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
+}
+
+/**
+ * @brief Configure the Source and Destination addresses.
+ * @note This API must not be called when the DMA stream is enabled.
+ * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
+ * PAR PA LL_DMA_ConfigAddresses
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param SrcAddress Between 0 to 0xFFFFFFFF
+ * @param DstAddress Between 0 to 0xFFFFFFFF
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
+{
+ /* Direction Memory to Periph */
+ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+ {
+ WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
+ WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
+ }
+ /* Direction Periph to Memory and Memory to Memory */
+ else
+ {
+ WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
+ WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
+ }
+}
+
+/**
+ * @brief Set the Memory address.
+ * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param MemoryAddress Between 0 to 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Peripheral address.
+ * @rmtoll PAR PA LL_DMA_SetPeriphAddress
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param PeriphAddress Between 0 to 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
+{
+ WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
+}
+
+/**
+ * @brief Get the Memory address.
+ * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Between 0 to 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+ return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
+}
+
+/**
+ * @brief Get the Peripheral address.
+ * @rmtoll PAR PA LL_DMA_GetPeriphAddress
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Between 0 to 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+ return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
+}
+
+/**
+ * @brief Set the Memory to Memory Source address.
+ * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param MemoryAddress Between 0 to 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Memory to Memory Destination address.
+ * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param MemoryAddress Between 0 to 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+ {
+ WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
+ }
+
+/**
+ * @brief Get the Memory to Memory Source address.
+ * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Between 0 to 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+ {
+ return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
+ }
+
+/**
+ * @brief Get the Memory to Memory Destination address.
+ * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Between 0 to 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+ return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
+}
+
+/**
+ * @brief Set Memory 1 address (used in case of Double buffer mode).
+ * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @param Address Between 0 to 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
+{
+ MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
+}
+
+/**
+ * @brief Get Memory 1 address (used in case of Double buffer mode).
+ * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval Between 0 to 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Stream 0 half transfer flag.
+ * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
+}
+
+/**
+ * @brief Get Stream 1 half transfer flag.
+ * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
+}
+
+/**
+ * @brief Get Stream 2 half transfer flag.
+ * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
+}
+
+/**
+ * @brief Get Stream 3 half transfer flag.
+ * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
+}
+
+/**
+ * @brief Get Stream 4 half transfer flag.
+ * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
+}
+
+/**
+ * @brief Get Stream 5 half transfer flag.
+ * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
+}
+
+/**
+ * @brief Get Stream 6 half transfer flag.
+ * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
+}
+
+/**
+ * @brief Get Stream 7 half transfer flag.
+ * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
+}
+
+/**
+ * @brief Get Stream 0 transfer complete flag.
+ * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
+}
+
+/**
+ * @brief Get Stream 1 transfer complete flag.
+ * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
+}
+
+/**
+ * @brief Get Stream 2 transfer complete flag.
+ * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
+}
+
+/**
+ * @brief Get Stream 3 transfer complete flag.
+ * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
+}
+
+/**
+ * @brief Get Stream 4 transfer complete flag.
+ * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
+}
+
+/**
+ * @brief Get Stream 5 transfer complete flag.
+ * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
+}
+
+/**
+ * @brief Get Stream 6 transfer complete flag.
+ * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
+}
+
+/**
+ * @brief Get Stream 7 transfer complete flag.
+ * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
+}
+
+/**
+ * @brief Get Stream 0 transfer error flag.
+ * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
+}
+
+/**
+ * @brief Get Stream 1 transfer error flag.
+ * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
+}
+
+/**
+ * @brief Get Stream 2 transfer error flag.
+ * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
+}
+
+/**
+ * @brief Get Stream 3 transfer error flag.
+ * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
+}
+
+/**
+ * @brief Get Stream 4 transfer error flag.
+ * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
+}
+
+/**
+ * @brief Get Stream 5 transfer error flag.
+ * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
+}
+
+/**
+ * @brief Get Stream 6 transfer error flag.
+ * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
+}
+
+/**
+ * @brief Get Stream 7 transfer error flag.
+ * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
+}
+
+/**
+ * @brief Get Stream 0 direct mode error flag.
+ * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
+}
+
+/**
+ * @brief Get Stream 1 direct mode error flag.
+ * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
+}
+
+/**
+ * @brief Get Stream 2 direct mode error flag.
+ * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
+}
+
+/**
+ * @brief Get Stream 3 direct mode error flag.
+ * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
+}
+
+/**
+ * @brief Get Stream 4 direct mode error flag.
+ * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
+}
+
+/**
+ * @brief Get Stream 5 direct mode error flag.
+ * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
+}
+
+/**
+ * @brief Get Stream 6 direct mode error flag.
+ * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
+}
+
+/**
+ * @brief Get Stream 7 direct mode error flag.
+ * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
+}
+
+/**
+ * @brief Get Stream 0 FIFO error flag.
+ * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
+}
+
+/**
+ * @brief Get Stream 1 FIFO error flag.
+ * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
+}
+
+/**
+ * @brief Get Stream 2 FIFO error flag.
+ * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
+}
+
+/**
+ * @brief Get Stream 3 FIFO error flag.
+ * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
+}
+
+/**
+ * @brief Get Stream 4 FIFO error flag.
+ * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
+}
+
+/**
+ * @brief Get Stream 5 FIFO error flag.
+ * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
+}
+
+/**
+ * @brief Get Stream 6 FIFO error flag.
+ * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
+}
+
+/**
+ * @brief Get Stream 7 FIFO error flag.
+ * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
+}
+
+/**
+ * @brief Clear Stream 0 half transfer flag.
+ * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
+}
+
+/**
+ * @brief Clear Stream 1 half transfer flag.
+ * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
+}
+
+/**
+ * @brief Clear Stream 2 half transfer flag.
+ * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
+}
+
+/**
+ * @brief Clear Stream 3 half transfer flag.
+ * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
+}
+
+/**
+ * @brief Clear Stream 4 half transfer flag.
+ * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
+}
+
+/**
+ * @brief Clear Stream 5 half transfer flag.
+ * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
+}
+
+/**
+ * @brief Clear Stream 6 half transfer flag.
+ * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
+}
+
+/**
+ * @brief Clear Stream 7 half transfer flag.
+ * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
+}
+
+/**
+ * @brief Clear Stream 0 transfer complete flag.
+ * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
+}
+
+/**
+ * @brief Clear Stream 1 transfer complete flag.
+ * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
+}
+
+/**
+ * @brief Clear Stream 2 transfer complete flag.
+ * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
+}
+
+/**
+ * @brief Clear Stream 3 transfer complete flag.
+ * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
+}
+
+/**
+ * @brief Clear Stream 4 transfer complete flag.
+ * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
+}
+
+/**
+ * @brief Clear Stream 5 transfer complete flag.
+ * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
+}
+
+/**
+ * @brief Clear Stream 6 transfer complete flag.
+ * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
+}
+
+/**
+ * @brief Clear Stream 7 transfer complete flag.
+ * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
+}
+
+/**
+ * @brief Clear Stream 0 transfer error flag.
+ * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
+}
+
+/**
+ * @brief Clear Stream 1 transfer error flag.
+ * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
+}
+
+/**
+ * @brief Clear Stream 2 transfer error flag.
+ * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
+}
+
+/**
+ * @brief Clear Stream 3 transfer error flag.
+ * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
+}
+
+/**
+ * @brief Clear Stream 4 transfer error flag.
+ * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
+}
+
+/**
+ * @brief Clear Stream 5 transfer error flag.
+ * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
+}
+
+/**
+ * @brief Clear Stream 6 transfer error flag.
+ * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
+}
+
+/**
+ * @brief Clear Stream 7 transfer error flag.
+ * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
+}
+
+/**
+ * @brief Clear Stream 0 direct mode error flag.
+ * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
+}
+
+/**
+ * @brief Clear Stream 1 direct mode error flag.
+ * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
+}
+
+/**
+ * @brief Clear Stream 2 direct mode error flag.
+ * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
+}
+
+/**
+ * @brief Clear Stream 3 direct mode error flag.
+ * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
+}
+
+/**
+ * @brief Clear Stream 4 direct mode error flag.
+ * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
+}
+
+/**
+ * @brief Clear Stream 5 direct mode error flag.
+ * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
+}
+
+/**
+ * @brief Clear Stream 6 direct mode error flag.
+ * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
+}
+
+/**
+ * @brief Clear Stream 7 direct mode error flag.
+ * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
+}
+
+/**
+ * @brief Clear Stream 0 FIFO error flag.
+ * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
+}
+
+/**
+ * @brief Clear Stream 1 FIFO error flag.
+ * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
+}
+
+/**
+ * @brief Clear Stream 2 FIFO error flag.
+ * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
+}
+
+/**
+ * @brief Clear Stream 3 FIFO error flag.
+ * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
+}
+
+/**
+ * @brief Clear Stream 4 FIFO error flag.
+ * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
+}
+
+/**
+ * @brief Clear Stream 5 FIFO error flag.
+ * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
+}
+
+/**
+ * @brief Clear Stream 6 FIFO error flag.
+ * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
+}
+
+/**
+ * @brief Clear Stream 7 FIFO error flag.
+ * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Half transfer interrupt.
+ * @rmtoll CR HTIE LL_DMA_EnableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+ * @brief Enable Transfer error interrupt.
+ * @rmtoll CR TEIE LL_DMA_EnableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+ * @brief Enable Transfer complete interrupt.
+ * @rmtoll CR TCIE LL_DMA_EnableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+ * @brief Enable Direct mode error interrupt.
+ * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+ * @brief Enable FIFO error interrupt.
+ * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+ * @brief Disable Half transfer interrupt.
+ * @rmtoll CR HTIE LL_DMA_DisableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+ * @brief Disable Transfer error interrupt.
+ * @rmtoll CR TEIE LL_DMA_DisableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+ * @brief Disable Transfer complete interrupt.
+ * @rmtoll CR TCIE LL_DMA_DisableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+ * @brief Disable Direct mode error interrupt.
+ * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+ * @brief Disable FIFO error interrupt.
+ * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+ * @brief Check if Half transfer interrup is enabled.
+ * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
+}
+
+/**
+ * @brief Check if Transfer error nterrup is enabled.
+ * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
+}
+
+/**
+ * @brief Check if Transfer complete interrup is enabled.
+ * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
+}
+
+/**
+ * @brief Check if Direct mode error interrupt is enabled.
+ * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
+}
+
+/**
+ * @brief Check if FIFO error interrup is enabled.
+ * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,597 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_dma2d.c
+ * @author MCD Application Team
+ * @brief DMA2D LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_dma2d.h"
+#include "stm32f4xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA2D)
+
+/** @addtogroup DMA2D_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Private_Constants DMA2D Private Constants
+ * @{
+ */
+#define LL_DMA2D_COLOR 0xFFU /*!< Maximum output color setting */
+#define LL_DMA2D_NUMBEROFLINES DMA2D_NLR_NL /*!< Maximum number of lines */
+#define LL_DMA2D_NUMBEROFPIXELS (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos) /*!< Maximum number of pixels per lines */
+#define LL_DMA2D_OFFSET_MAX 0x3FFFU /*!< Maximum output line offset expressed in pixels */
+#define LL_DMA2D_CLUTSIZE_MAX 0xFFU /*!< Maximum CLUT size */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \
+ ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \
+ ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \
+ ((MODE) == LL_DMA2D_MODE_R2M))
+
+#define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \
+ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \
+ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565) || \
+ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \
+ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444))
+
+#define IS_LL_DMA2D_GREEN(GREEN) ((GREEN) <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_RED(RED) ((RED) <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR)
+
+#define IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX)
+
+#define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES)
+#define IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
+
+#define IS_LL_DMA2D_LCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8) || \
+ ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4))
+
+#define IS_LL_DMA2D_CLUTCMODE(CLUTCMODE) (((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \
+ ((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888))
+
+#define IS_LL_DMA2D_CLUTSIZE(SIZE) ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX)
+
+#define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \
+ ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \
+ ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
+ * @{
+ */
+
+/**
+ * @brief De-initialize DMA2D registers (registers restored to their default values).
+ * @param DMA2Dx DMA2D Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA2D registers are de-initialized
+ * - ERROR: DMA2D registers are not de-initialized
+ */
+ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+
+ if (DMA2Dx == DMA2D)
+ {
+ /* Force reset of DMA2D clock */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2D);
+
+ /* Release reset of DMA2D clock */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2D);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
+ * @note DMA2D transfers must be disabled to set initialization bits in configuration registers,
+ * otherwise ERROR result is returned.
+ * @param DMA2Dx DMA2D Instance
+ * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure
+ * that contains the configuration information for the specified DMA2D peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content
+ * - ERROR: Issue occurred during DMA2D registers initialization
+ */
+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ LL_DMA2D_ColorTypeDef DMA2D_ColorStruct;
+ uint32_t tmp = 0U, tmp1 = 0U, tmp2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode));
+ assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode));
+ assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines));
+ assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines));
+ assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen));
+ assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed));
+ assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue));
+ assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha));
+ assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset));
+
+ /* DMA2D transfers must be disabled to configure bits in initialization registers */
+ tmp = LL_DMA2D_IsTransferOngoing(DMA2Dx);
+ tmp1 = LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2Dx);
+ tmp2 = LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2Dx);
+ if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U))
+ {
+ /* DMA2D CR register configuration -------------------------------------------*/
+ LL_DMA2D_SetMode(DMA2Dx, DMA2D_InitStruct->Mode);
+
+ /* DMA2D OPFCCR register configuration ---------------------------------------*/
+ MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, DMA2D_InitStruct->ColorMode);
+
+ /* DMA2D OOR register configuration ------------------------------------------*/
+ LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset);
+
+ /* DMA2D NLR register configuration ------------------------------------------*/
+ LL_DMA2D_ConfigSize(DMA2Dx, DMA2D_InitStruct->NbrOfLines, DMA2D_InitStruct->NbrOfPixelsPerLines);
+
+ /* DMA2D OMAR register configuration ------------------------------------------*/
+ LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress);
+
+ /* DMA2D OCOLR register configuration ------------------------------------------*/
+ DMA2D_ColorStruct.ColorMode = DMA2D_InitStruct->ColorMode;
+ DMA2D_ColorStruct.OutputBlue = DMA2D_InitStruct->OutputBlue;
+ DMA2D_ColorStruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
+ DMA2D_ColorStruct.OutputRed = DMA2D_InitStruct->OutputRed;
+ DMA2D_ColorStruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
+ LL_DMA2D_ConfigOutputColor(DMA2Dx, &DMA2D_ColorStruct);
+
+ status = SUCCESS;
+ }
+ /* If DMA2D transfers are not disabled, return ERROR */
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value.
+ * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
+{
+ /* Set DMA2D_InitStruct fields to default values */
+ DMA2D_InitStruct->Mode = LL_DMA2D_MODE_M2M;
+ DMA2D_InitStruct->ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB8888;
+ DMA2D_InitStruct->NbrOfLines = 0x0U;
+ DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U;
+ DMA2D_InitStruct->LineOffset = 0x0U;
+ DMA2D_InitStruct->OutputBlue = 0x0U;
+ DMA2D_InitStruct->OutputGreen = 0x0U;
+ DMA2D_InitStruct->OutputRed = 0x0U;
+ DMA2D_InitStruct->OutputAlpha = 0x0U;
+ DMA2D_InitStruct->OutputMemoryAddress = 0x0U;
+}
+
+/**
+ * @brief Configure the foreground or background according to the specified parameters
+ * in the LL_DMA2D_LayerCfgTypeDef structure.
+ * @param DMA2Dx DMA2D Instance
+ * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
+ * the configuration information for the specified layer.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * 0(background) / 1(foreground)
+ * @retval None
+ */
+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_LL_DMA2D_OFFSET(DMA2D_LayerCfg->LineOffset));
+ assert_param(IS_LL_DMA2D_LCMODE(DMA2D_LayerCfg->ColorMode));
+ assert_param(IS_LL_DMA2D_CLUTCMODE(DMA2D_LayerCfg->CLUTColorMode));
+ assert_param(IS_LL_DMA2D_CLUTSIZE(DMA2D_LayerCfg->CLUTSize));
+ assert_param(IS_LL_DMA2D_ALPHAMODE(DMA2D_LayerCfg->AlphaMode));
+ assert_param(IS_LL_DMA2D_GREEN(DMA2D_LayerCfg->Green));
+ assert_param(IS_LL_DMA2D_RED(DMA2D_LayerCfg->Red));
+ assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue));
+ assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha));
+
+ if (LayerIdx == 0U)
+ {
+ /* Configure the background memory address */
+ LL_DMA2D_BGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
+
+ /* Configure the background line offset */
+ LL_DMA2D_BGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
+
+ /* Configure the background Alpha value, Alpha mode, CLUT size, CLUT Color mode and Color mode */
+ MODIFY_REG(DMA2Dx->BGPFCCR, \
+ (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \
+ ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->AlphaMode | \
+ (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
+ DMA2D_LayerCfg->ColorMode));
+
+ /* Configure the background color */
+ LL_DMA2D_BGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
+
+ /* Configure the background CLUT memory address */
+ LL_DMA2D_BGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
+ }
+ else
+ {
+ /* Configure the foreground memory address */
+ LL_DMA2D_FGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
+
+ /* Configure the foreground line offset */
+ LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
+
+ /* Configure the foreground Alpha value, Alpha mode, CLUT size, CLUT Color mode and Color mode */
+ MODIFY_REG(DMA2Dx->FGPFCCR, \
+ (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \
+ ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->AlphaMode | \
+ (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
+ DMA2D_LayerCfg->ColorMode));
+
+ /* Configure the foreground color */
+ LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
+
+ /* Configure the foreground CLUT memory address */
+ LL_DMA2D_FGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
+ }
+}
+
+/**
+ * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value.
+ * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
+{
+ /* Set DMA2D_LayerCfg fields to default values */
+ DMA2D_LayerCfg->MemoryAddress = 0x0U;
+ DMA2D_LayerCfg->ColorMode = LL_DMA2D_INPUT_MODE_ARGB8888;
+ DMA2D_LayerCfg->LineOffset = 0x0U;
+ DMA2D_LayerCfg->CLUTColorMode = LL_DMA2D_CLUT_COLOR_MODE_ARGB8888;
+ DMA2D_LayerCfg->CLUTSize = 0x0U;
+ DMA2D_LayerCfg->AlphaMode = LL_DMA2D_ALPHA_MODE_NO_MODIF;
+ DMA2D_LayerCfg->Alpha = 0x0U;
+ DMA2D_LayerCfg->Blue = 0x0U;
+ DMA2D_LayerCfg->Green = 0x0U;
+ DMA2D_LayerCfg->Red = 0x0U;
+ DMA2D_LayerCfg->CLUTMemoryAddress = 0x0U;
+}
+
+/**
+ * @brief Initialize DMA2D output color register according to the specified parameters
+ * in DMA2D_ColorStruct.
+ * @param DMA2Dx DMA2D Instance
+ * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains
+ * the color configuration information for the specified DMA2D peripheral.
+ * @retval None
+ */
+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
+{
+ uint32_t outgreen = 0U;
+ uint32_t outred = 0U;
+ uint32_t outalpha = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(DMA2D_ColorStruct->ColorMode));
+ assert_param(IS_LL_DMA2D_GREEN(DMA2D_ColorStruct->OutputGreen));
+ assert_param(IS_LL_DMA2D_RED(DMA2D_ColorStruct->OutputRed));
+ assert_param(IS_LL_DMA2D_BLUE(DMA2D_ColorStruct->OutputBlue));
+ assert_param(IS_LL_DMA2D_ALPHA(DMA2D_ColorStruct->OutputAlpha));
+
+ /* DMA2D OCOLR register configuration ------------------------------------------*/
+ if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
+ outred = DMA2D_ColorStruct->OutputRed << 16U;
+ outalpha = DMA2D_ColorStruct->OutputAlpha << 24U;
+ }
+ else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
+ outred = DMA2D_ColorStruct->OutputRed << 16U;
+ outalpha = 0x00000000U;
+ }
+ else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
+ outred = DMA2D_ColorStruct->OutputRed << 11U;
+ outalpha = 0x00000000U;
+ }
+ else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
+ outred = DMA2D_ColorStruct->OutputRed << 10U;
+ outalpha = DMA2D_ColorStruct->OutputAlpha << 15U;
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ outgreen = DMA2D_ColorStruct->OutputGreen << 4U;
+ outred = DMA2D_ColorStruct->OutputRed << 8U;
+ outalpha = DMA2D_ColorStruct->OutputAlpha << 12U;
+ }
+ LL_DMA2D_SetOutputColor(DMA2Dx, (outgreen | outred | DMA2D_ColorStruct->OutputBlue | outalpha));
+}
+
+/**
+ * @brief Return DMA2D output Blue color.
+ * @param DMA2Dx DMA2D Instance.
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF
+ */
+uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ uint32_t color = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+ /* DMA2D OCOLR register reading ------------------------------------------*/
+ if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU));
+ }
+
+ return color;
+}
+
+/**
+ * @brief Return DMA2D output Green color.
+ * @param DMA2Dx DMA2D Instance.
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF
+ */
+uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ uint32_t color = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+ /* DMA2D OCOLR register reading ------------------------------------------*/
+ if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7E0U) >> 5U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x3E0U) >> 5U);
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U);
+ }
+
+ return color;
+}
+
+/**
+ * @brief Return DMA2D output Red color.
+ * @param DMA2Dx DMA2D Instance.
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF
+ */
+uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ uint32_t color = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+ /* DMA2D OCOLR register reading ------------------------------------------*/
+ if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF800U) >> 11U);
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7C00U) >> 10U);
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U);
+ }
+
+ return color;
+}
+
+/**
+ * @brief Return DMA2D output Alpha color.
+ * @param DMA2Dx DMA2D Instance.
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF
+ */
+uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ uint32_t color = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+ assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+ /* DMA2D OCOLR register reading ------------------------------------------*/
+ if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF000000U) >> 24U);
+ }
+ else if ((ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) || (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565))
+ {
+ color = 0x0U;
+ }
+ else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x8000U) >> 15U);
+ }
+ else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+ {
+ color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U);
+ }
+
+ return color;
+}
+
+/**
+ * @brief Configure DMA2D transfer size.
+ * @param DMA2Dx DMA2D Instance
+ * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
+ * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
+ * @retval None
+ */
+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
+{
+ MODIFY_REG(DMA2Dx->NLR, (DMA2D_NLR_PL | DMA2D_NLR_NL), \
+ ((NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos) | NbrOfLines));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (DMA2D) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1849 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_dma2d.h
+ * @author MCD Application Team
+ * @brief Header file of DMA2D LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_DMA2D_H
+#define __STM32F4xx_LL_DMA2D_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA2D)
+
+/** @defgroup DMA2D_LL DMA2D
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL DMA2D Init Structure Definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
+
+ uint32_t ColorMode; /*!< Specifies the color format of the output image.
+ - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+ uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputRed; /*!< Specifies the Red value of the output image.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
+
+ uint32_t LineOffset; /*!< Specifies the output line offset value.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
+
+ uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
+
+ uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+
+} LL_DMA2D_InitTypeDef;
+
+/**
+ * @brief LL DMA2D Layer Configuration Structure Definition
+ */
+typedef struct
+{
+ uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
+
+ uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
+
+ uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
+
+ uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
+
+ uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
+
+ uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
+ - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
+
+ uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
+
+ uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
+
+ uint32_t Green; /*!< Specifies the foreground or background Green color value.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
+
+ uint32_t Red; /*!< Specifies the foreground or background Red color value.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
+
+ uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
+ - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+ This parameter can be modified afterwards using unitary functions
+ - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
+ - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
+
+} LL_DMA2D_LayerCfgTypeDef;
+
+/**
+ * @brief LL DMA2D Output Color Structure Definition
+ */
+typedef struct
+{
+ uint32_t ColorMode; /*!< Specifies the color format of the output image.
+ - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+ uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputRed; /*!< Specifies the Red value of the output image.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+ uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ function @ref LL_DMA2D_ConfigOutputColor(). */
+
+} LL_DMA2D_ColorTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
+ * @{
+ */
+#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
+#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
+#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
+#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
+ * @{
+ */
+#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
+#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
+#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
+#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
+#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
+#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
+#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
+#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
+ * @{
+ */
+#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
+#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
+#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
+#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
+#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
+ * @{
+ */
+#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
+#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
+#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
+#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
+#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
+#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
+#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
+#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
+#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
+#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
+#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
+ * @{
+ */
+#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
+#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
+#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
+ with original alpha channel value */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
+ * @{
+ */
+#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
+#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in DMA2D register.
+ * @param __INSTANCE__ DMA2D Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA2D register.
+ * @param __INSTANCE__ DMA2D Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
+ * @{
+ */
+
+/**
+ * @brief Start a DMA2D transfer.
+ * @rmtoll CR START LL_DMA2D_Start
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
+}
+
+/**
+ * @brief Indicate if a DMA2D transfer is ongoing.
+ * @rmtoll CR START LL_DMA2D_IsTransferOngoing
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START));
+}
+
+/**
+ * @brief Suspend DMA2D transfer.
+ * @note This API can be used to suspend automatic foreground or background CLUT loading.
+ * @rmtoll CR SUSP LL_DMA2D_Suspend
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
+{
+ MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
+}
+
+/**
+ * @brief Resume DMA2D transfer.
+ * @note This API can be used to resume automatic foreground or background CLUT loading.
+ * @rmtoll CR SUSP LL_DMA2D_Resume
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
+}
+
+/**
+ * @brief Indicate if DMA2D transfer is suspended.
+ * @note This API can be used to indicate whether or not automatic foreground or
+ * background CLUT loading is suspended.
+ * @rmtoll CR SUSP LL_DMA2D_IsSuspended
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP));
+}
+
+/**
+ * @brief Abort DMA2D transfer.
+ * @note This API can be used to abort automatic foreground or background CLUT loading.
+ * @rmtoll CR ABORT LL_DMA2D_Abort
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
+{
+ MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
+}
+
+/**
+ * @brief Indicate if DMA2D transfer is aborted.
+ * @note This API can be used to indicate whether or not automatic foreground or
+ * background CLUT loading is aborted.
+ * @rmtoll CR ABORT LL_DMA2D_IsAborted
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT));
+}
+
+/**
+ * @brief Set DMA2D mode.
+ * @rmtoll CR MODE LL_DMA2D_SetMode
+ * @param DMA2Dx DMA2D Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_MODE_M2M
+ * @arg @ref LL_DMA2D_MODE_M2M_PFC
+ * @arg @ref LL_DMA2D_MODE_M2M_BLEND
+ * @arg @ref LL_DMA2D_MODE_R2M
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
+{
+ MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
+}
+
+/**
+ * @brief Return DMA2D mode
+ * @rmtoll CR MODE LL_DMA2D_GetMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_MODE_M2M
+ * @arg @ref LL_DMA2D_MODE_M2M_PFC
+ * @arg @ref LL_DMA2D_MODE_M2M_BLEND
+ * @arg @ref LL_DMA2D_MODE_R2M
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
+}
+
+/**
+ * @brief Set DMA2D output color mode.
+ * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
+}
+
+/**
+ * @brief Return DMA2D output color mode.
+ * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
+}
+
+/**
+ * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll OOR LO LL_DMA2D_SetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+ MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
+}
+
+/**
+ * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll OOR LO LL_DMA2D_GetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
+}
+
+/**
+ * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
+ * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
+ * @param DMA2Dx DMA2D Instance
+ * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
+{
+ MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
+}
+
+/**
+ * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
+ * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
+ * @param DMA2Dx DMA2D Instance
+ * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
+}
+
+/**
+ * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+ * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
+ * @param DMA2Dx DMA2D Instance
+ * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
+{
+ MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
+}
+
+/**
+ * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+ * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
+ * @param DMA2Dx DMA2D Instance
+ * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
+}
+
+/**
+ * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
+}
+
+/**
+ * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
+ * @note Output color format depends on output color mode, ARGB8888, RGB888,
+ * RGB565, ARGB1555 or ARGB4444.
+ * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
+ * with respect to color mode is not done by the user code.
+ * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
+ * OCOLR GREEN LL_DMA2D_SetOutputColor\n
+ * OCOLR RED LL_DMA2D_SetOutputColor\n
+ * OCOLR ALPHA LL_DMA2D_SetOutputColor
+ * @param DMA2Dx DMA2D Instance
+ * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
+{
+ MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
+ OutputColor);
+}
+
+/**
+ * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
+ * @note Alpha channel and red, green, blue color values must be retrieved from the returned
+ * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
+ * as set by @ref LL_DMA2D_SetOutputColorMode.
+ * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
+ * OCOLR GREEN LL_DMA2D_GetOutputColor\n
+ * OCOLR RED LL_DMA2D_GetOutputColor\n
+ * OCOLR ALPHA LL_DMA2D_GetOutputColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
+ (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
+}
+
+/**
+ * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+ * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
+ * @param DMA2Dx DMA2D Instance
+ * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
+{
+ MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
+}
+
+/**
+ * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+ * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
+ * @param DMA2Dx DMA2D Instance
+ * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
+}
+
+/**
+ * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
+ * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
+{
+ MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
+}
+
+/**
+ * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
+ * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
+}
+
+/**
+ * @brief Enable DMA2D dead time functionality.
+ * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+ * @brief Disable DMA2D dead time functionality.
+ * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+ * @brief Indicate if DMA2D dead time functionality is enabled.
+ * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN));
+}
+
+/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
+ * @{
+ */
+
+/**
+ * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
+}
+
+/**
+ * @brief Enable DMA2D foreground CLUT loading.
+ * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
+}
+
+/**
+ * @brief Indicate if DMA2D foreground CLUT loading is enabled.
+ * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START));
+}
+
+/**
+ * @brief Set DMA2D foreground color mode.
+ * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+ * @arg @ref LL_DMA2D_INPUT_MODE_L8
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL44
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL88
+ * @arg @ref LL_DMA2D_INPUT_MODE_L4
+ * @arg @ref LL_DMA2D_INPUT_MODE_A8
+ * @arg @ref LL_DMA2D_INPUT_MODE_A4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
+}
+
+/**
+ * @brief Return DMA2D foreground color mode.
+ * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+ * @arg @ref LL_DMA2D_INPUT_MODE_L8
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL44
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL88
+ * @arg @ref LL_DMA2D_INPUT_MODE_L4
+ * @arg @ref LL_DMA2D_INPUT_MODE_A8
+ * @arg @ref LL_DMA2D_INPUT_MODE_A4
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
+}
+
+/**
+ * @brief Set DMA2D foreground alpha mode.
+ * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
+ * @param DMA2Dx DMA2D Instance
+ * @param AphaMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+ * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+ * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
+}
+
+/**
+ * @brief Return DMA2D foreground alpha mode.
+ * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+ * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+ * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
+}
+
+/**
+ * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
+ * @param DMA2Dx DMA2D Instance
+ * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+}
+
+/**
+ * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
+ * @param DMA2Dx DMA2D Instance
+ * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
+}
+
+/**
+ * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+ MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
+}
+
+/**
+ * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
+}
+
+/**
+ * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
+ * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
+ * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
+ * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Red Value between Min_Data=0 and Max_Data=0xFF
+ * @param Green Value between Min_Data=0 and Max_Data=0xFF
+ * @param Blue Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+ MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
+ ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+ * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Red Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+ MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
+}
+
+/**
+ * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
+}
+
+/**
+ * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Green Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+ MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
+}
+
+/**
+ * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
+}
+
+/**
+ * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Blue Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+ MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
+}
+
+/**
+ * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
+}
+
+/**
+ * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
+}
+
+/**
+ * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
+}
+
+/**
+ * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+ * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
+ * @param DMA2Dx DMA2D Instance
+ * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
+}
+
+/**
+ * @brief Set DMA2D foreground CLUT color mode.
+ * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+ MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+ * @brief Return DMA2D foreground CLUT color mode.
+ * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
+ * @{
+ */
+
+/**
+ * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
+}
+
+/**
+ * @brief Enable DMA2D background CLUT loading.
+ * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
+}
+
+/**
+ * @brief Indicate if DMA2D background CLUT loading is enabled.
+ * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START));
+}
+
+/**
+ * @brief Set DMA2D background color mode.
+ * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param ColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+ * @arg @ref LL_DMA2D_INPUT_MODE_L8
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL44
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL88
+ * @arg @ref LL_DMA2D_INPUT_MODE_L4
+ * @arg @ref LL_DMA2D_INPUT_MODE_A8
+ * @arg @ref LL_DMA2D_INPUT_MODE_A4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
+}
+
+/**
+ * @brief Return DMA2D background color mode.
+ * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+ * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+ * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+ * @arg @ref LL_DMA2D_INPUT_MODE_L8
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL44
+ * @arg @ref LL_DMA2D_INPUT_MODE_AL88
+ * @arg @ref LL_DMA2D_INPUT_MODE_L4
+ * @arg @ref LL_DMA2D_INPUT_MODE_A8
+ * @arg @ref LL_DMA2D_INPUT_MODE_A4
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
+}
+
+/**
+ * @brief Set DMA2D background alpha mode.
+ * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
+ * @param DMA2Dx DMA2D Instance
+ * @param AphaMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+ * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+ * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
+}
+
+/**
+ * @brief Return DMA2D background alpha mode.
+ * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+ * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+ * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
+}
+
+/**
+ * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
+ * @param DMA2Dx DMA2D Instance
+ * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
+}
+
+/**
+ * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
+ * @param DMA2Dx DMA2D Instance
+ * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
+}
+
+/**
+ * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+ MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
+}
+
+/**
+ * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+ * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
+ * @param DMA2Dx DMA2D Instance
+ * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
+}
+
+/**
+ * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
+ * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
+ * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
+ * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Red Value between Min_Data=0 and Max_Data=0xFF
+ * @param Green Value between Min_Data=0 and Max_Data=0xFF
+ * @param Blue Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+ MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
+ ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+ * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Red Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+ MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
+}
+
+/**
+ * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
+}
+
+/**
+ * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Green Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+ MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
+}
+
+/**
+ * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
+}
+
+/**
+ * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
+ * @param DMA2Dx DMA2D Instance
+ * @param Blue Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+ MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
+}
+
+/**
+ * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
+ * @param DMA2Dx DMA2D Instance
+ * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
+}
+
+/**
+ * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+ LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
+}
+
+/**
+ * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+ * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
+ * @param DMA2Dx DMA2D Instance
+ * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
+}
+
+/**
+ * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
+}
+
+/**
+ * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+ * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
+ * @param DMA2Dx DMA2D Instance
+ * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
+}
+
+/**
+ * @brief Set DMA2D background CLUT color mode.
+ * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @param CLUTColorMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+ MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+ * @brief Return DMA2D background CLUT color mode.
+ * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
+ * @param DMA2Dx DMA2D Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+ * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+ return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
+ * @{
+ */
+
+/**
+ * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
+ * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF));
+}
+
+/**
+ * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
+ * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF));
+}
+
+/**
+ * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
+ * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF));
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
+ * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF));
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
+ * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF));
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
+ * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF));
+}
+
+/**
+ * @brief Clear DMA2D Configuration Error Interrupt Flag
+ * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
+}
+
+/**
+ * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
+ * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
+}
+
+/**
+ * @brief Clear DMA2D CLUT Access Error Interrupt Flag
+ * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
+}
+
+/**
+ * @brief Clear DMA2D Transfer Watermark Interrupt Flag
+ * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
+}
+
+/**
+ * @brief Clear DMA2D Transfer Complete Interrupt Flag
+ * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
+}
+
+/**
+ * @brief Clear DMA2D Transfer Error Interrupt Flag
+ * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
+ * @{
+ */
+
+/**
+ * @brief Enable Configuration Error Interrupt
+ * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+ * @brief Enable CLUT Transfer Complete Interrupt
+ * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+ * @brief Enable CLUT Access Error Interrupt
+ * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+ * @brief Enable Transfer Watermark Interrupt
+ * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+ * @brief Enable Transfer Complete Interrupt
+ * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+ * @brief Enable Transfer Error Interrupt
+ * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+ * @brief Disable Configuration Error Interrupt
+ * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+ * @brief Disable CLUT Transfer Complete Interrupt
+ * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+ * @brief Disable CLUT Access Error Interrupt
+ * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+ * @brief Disable Transfer Watermark Interrupt
+ * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+ * @brief Disable Transfer Complete Interrupt
+ * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+ * @brief Disable Transfer Error Interrupt
+ * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+ * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
+ * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE));
+}
+
+/**
+ * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
+ * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE));
+}
+
+/**
+ * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
+ * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE));
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
+ * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE));
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
+ * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE));
+}
+
+/**
+ * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
+ * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
+ * @param DMA2Dx DMA2D Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+ return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE));
+}
+
+
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
+ * @{
+ */
+
+ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
+uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (DMA2D) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_DMA2D_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,230 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_exti.c
+ * @author MCD Application Team
+ * @brief EXTI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_exti.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the EXTI registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are de-initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_DeInit(void)
+{
+ /* Interrupt mask register set to default reset values */
+ LL_EXTI_WriteReg(IMR, 0x00000000U);
+ /* Event mask register set to default reset values */
+ LL_EXTI_WriteReg(EMR, 0x00000000U);
+ /* Rising Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(RTSR, 0x00000000U);
+ /* Falling Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(FTSR, 0x00000000U);
+ /* Software interrupt event register set to default reset values */
+ LL_EXTI_WriteReg(SWIER, 0x00000000U);
+ /* Pending register set to default reset values */
+ LL_EXTI_WriteReg(PR, 0x00FFFFFFU);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+ assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+ /* ENABLE LineCommand */
+ if (EXTI_InitStruct->LineCommand != DISABLE)
+ {
+ assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+ /* Configure EXTI Lines in range from 0 to 31 */
+ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Rising Trigger on provided Lines */
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+ }
+ /* DISABLE LineCommand */
+ else
+ {
+ /* De-configure EXTI Lines in range from 0 to 31 */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
+ * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval None
+ */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
+ EXTI_InitStruct->LineCommand = DISABLE;
+ EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
+ EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (EXTI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,972 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_EXTI_H
+#define __STM32F4xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+ * @{
+ */
+typedef struct
+{
+
+ uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+ FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+
+ uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+ uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+ * @{
+ */
+#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
+#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
+#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
+#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
+#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
+#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
+#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
+#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
+#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
+#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
+#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
+#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
+#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
+#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
+#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
+#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
+#if defined(EXTI_IMR_IM16)
+#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
+#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
+#endif
+#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
+#if defined(EXTI_IMR_IM20)
+#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR_IM21)
+#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR_IM22)
+#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
+#endif
+#if defined(EXTI_IMR_IM23)
+#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
+#endif
+#if defined(EXTI_IMR_IM24)
+#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR_IM25)
+#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR_IM26)
+#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR_IM27)
+#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR_IM28)
+#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR_IM29)
+#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR_IM30)
+#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR_IM31)
+#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+ * @{
+ */
+#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+ * @}
+ */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in EXTI register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in EXTI register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23(*)
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23(*)
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR, ExtiLine);
+}
+
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23(*)
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23(*)
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR, ExtiLine);
+
+}
+
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23(*)
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR, ExtiLine);
+}
+
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23(*)
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+ * @{
+ */
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 0 to 31
+ * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER, ExtiLine);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
+}
+
+
+/**
+ * @brief Clear ExtLine Flags for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19(*)
+ * @arg @ref LL_EXTI_LINE_20(*)
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @note (*): Available in some devices
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->PR, ExtiLine);
+}
+
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* EXTI */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1708 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fmc.c
+ * @author MCD Application Team
+ * @brief FMC Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FMC peripheral features #####
+ ==============================================================================
+ [..] The Flexible memory controller (FMC) includes three memory controllers:
+ (+) The NOR/PSRAM memory controller
+ (+) The NAND/PC Card memory controller
+ (+) The Synchronous DRAM (SDRAM) controller
+
+ [..] The FMC functional block makes the interface with synchronous and asynchronous static
+ memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
+ (+) to translate AHB transactions into the appropriate external device protocol
+ (+) to meet the access time requirements of the external memory devices
+
+ [..] All external memories share the addresses, data and control signals with the controller.
+ Each external device is accessed by means of a unique Chip Select. The FMC performs
+ only one access at a time to an external device.
+ The main features of the FMC controller are the following:
+ (+) Interface with static-memory mapped devices including:
+ (++) Static random access memory (SRAM)
+ (++) Read-only memory (ROM)
+ (++) NOR Flash memory/OneNAND Flash memory
+ (++) PSRAM (4 memory banks)
+ (++) 16-bit PC Card compatible devices
+ (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+ data
+ (+) Interface with synchronous DRAM (SDRAM) memories
+ (+) Independent Chip Select control for each memory bank
+ (+) Independent configuration for each memory bank
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMC_LL FMC Low Layer
+ * @brief FMC driver modules
+ * @{
+ */
+
+#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup FMC_LL_Private_Functions
+ * @{
+ */
+
+/** @addtogroup FMC_LL_NORSRAM
+ * @brief NORSRAM Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NORSRAM device driver #####
+ ==============================================================================
+
+ [..]
+ This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
+ to run the NORSRAM external devices.
+
+ (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
+ (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
+ (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
+ (+) FMC NORSRAM bank extended timing configuration using the function
+ FMC_NORSRAM_Extended_Timing_Init()
+ (+) FMC NORSRAM bank enable/disable write operation using the functions
+ FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
+
+
+@endverbatim
+ * @{
+ */
+
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NORSRAM interface
+ (+) De-initialize the FMC NORSRAM interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the FMC_NORSRAM device according to the specified
+ * control parameters in the FMC_NORSRAM_InitTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Init Pointer to NORSRAM Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
+ assert_param(IS_FMC_MUX(Init->DataAddressMux));
+ assert_param(IS_FMC_MEMORY(Init->MemoryType));
+ assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
+ assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+ assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
+ assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
+ assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
+ assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
+ assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+ assert_param(IS_FMC_PAGESIZE(Init->PageSize));
+#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Init->NSBank];
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */
+ tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
+ FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
+ FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \
+ FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
+ FMC_BCR1_ASYNCWAIT | FMC_BCR1_CPSIZE | FMC_BCR1_CBURSTRW | \
+ FMC_BCR1_CCLKEN));
+
+ /* Set NORSRAM device control parameters */
+ tmpr |= (uint32_t)(Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WrapMode |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->PageSize |\
+ Init->WriteBurst |\
+ Init->ContinuousClock);
+#else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
+ tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
+ FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
+ FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \
+ FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
+ FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \
+ FMC_BCR1_WFDIS));
+
+ /* Set NORSRAM device control parameters */
+ tmpr |= (uint32_t)(Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->WriteBurst |\
+ Init->ContinuousClock |\
+ Init->PageSize |\
+ Init->WriteFifo);
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+
+ if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
+ {
+ tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
+ }
+
+ Device->BTCR[Init->NSBank] = tmpr;
+
+ /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+ if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
+ {
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
+ }
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ if(Init->NSBank != FMC_NORSRAM_BANK1)
+ {
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
+ }
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the FMC_NORSRAM peripheral
+ * @param Device Pointer to NORSRAM device instance
+ * @param ExDevice Pointer to NORSRAM extended mode device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Disable the FMC_NORSRAM device */
+ __FMC_NORSRAM_DISABLE(Device, Bank);
+
+ /* De-initialize the FMC_NORSRAM device */
+ /* FMC_NORSRAM_BANK1 */
+ if(Bank == FMC_NORSRAM_BANK1)
+ {
+ Device->BTCR[Bank] = 0x000030DBU;
+ }
+ /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
+ else
+ {
+ Device->BTCR[Bank] = 0x000030D2U;
+ }
+
+ Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
+ ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMC_NORSRAM Timing according to the specified
+ * parameters in the FMC_NORSRAM_TimingTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Bank + 1U];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
+ FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
+ FMC_BTR1_ACCMOD));
+
+ /* Set FMC_NORSRAM device timing parameters */
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4U) |\
+ ((Timing->DataSetupTime) << 8U) |\
+ ((Timing->BusTurnAroundDuration) << 16U) |\
+ (((Timing->CLKDivision) - 1U) << 20U) |\
+ (((Timing->DataLatency) - 2U) << 24U) |\
+ (Timing->AccessMode));
+
+ Device->BTCR[Bank + 1U] = tmpr;
+
+ /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+ if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
+ {
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
+ tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U);
+ Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
+ * parameters in the FMC_NORSRAM_TimingTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
+
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+ if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
+ {
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Get the BWTR register value */
+ tmpr = Device->BWTR[Bank];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
+ FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
+
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4U) |\
+ ((Timing->DataSetupTime) << 8U) |\
+ ((Timing->BusTurnAroundDuration) << 16U) |\
+ (Timing->AccessMode));
+
+ Device->BWTR[Bank] = tmpr;
+ }
+ else
+ {
+ Device->BWTR[Bank] = 0x0FFFFFFFU;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NORSRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NORSRAM interface.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Enables dynamically FMC_NORSRAM write operation.
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Enable write operation */
+ Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NORSRAM write operation.
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Disable write operation */
+ Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_LL_NAND
+ * @brief NAND Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NAND device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FMC NAND banks in order
+ to run the NAND external devices.
+
+ (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
+ (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
+ (+) FMC NAND bank common space timing configuration using the function
+ FMC_NAND_CommonSpace_Timing_Init()
+ (+) FMC NAND bank attribute space timing configuration using the function
+ FMC_NAND_AttributeSpace_Timing_Init()
+ (+) FMC NAND bank enable/disable ECC correction feature using the functions
+ FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
+ (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NAND interface
+ (+) De-initialize the FMC NAND interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMC_NAND device according to the specified
+ * control parameters in the FMC_NAND_HandleTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ /* Get the NAND bank register value */
+ tmpr = Device->PCR;
+
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
+ FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
+ FMC_PCR_TAR | FMC_PCR_ECCPS));
+
+ /* Set NAND device control parameters */
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << 9U) |\
+ ((Init->TARSetupTime) << 13U));
+
+ /* NAND bank registers configuration */
+ Device->PCR = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PMEM;
+
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \
+ FMC_PMEM_MEMHIZ2));
+
+ /* Set FMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U)
+ );
+
+ /* NAND bank registers configuration */
+ Device->PMEM = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get the NAND bank register value */
+ tmpr = Device->PATT;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \
+ FMC_PATT_ATTHIZ2));
+
+ /* Set FMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U));
+
+ /* NAND bank registers configuration */
+ Device->PATT = tmpr;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the FMC_NAND device
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable the NAND Bank */
+ __FMC_NAND_DISABLE(Device, Bank);
+
+ /* De-initialize the NAND Bank */
+ /* Set the FMC_NAND_BANK registers to their reset values */
+ Device->PCR = 0x00000018U;
+ Device->SR = 0x00000040U;
+ Device->PMEM = 0xFCFCFCFCU;
+ Device->PATT = 0xFCFCFCFCU;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_FMC_NAND_Group2 Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Enable ECC feature */
+ Device->PCR |= FMC_PCR_ECCEN;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable ECC feature */
+ Device->PCR &= ~FMC_PCR_ECCEN;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FIFO is empty */
+ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Get the ECCR register value */
+ *ECCval = (uint32_t)Device->ECCR;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NAND interface
+ (+) De-initialize the FMC NAND interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the FMC_NAND device according to the specified
+ * control parameters in the FMC_NAND_HandleTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ if(Init->NandBank == FMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PCR2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PCR3;
+ }
+
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \
+ FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
+ FMC_PCR2_TAR | FMC_PCR2_ECCPS));
+
+ /* Set NAND device control parameters */
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << 9U) |\
+ ((Init->TARSetupTime) << 13U));
+
+ if(Init->NandBank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ Device->PCR2 = tmpr;
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ Device->PCR3 = tmpr;
+ }
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PMEM2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PMEM3;
+ }
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \
+ FMC_PMEM2_MEMHIZ2));
+
+ /* Set FMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U)
+ );
+
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ Device->PMEM2 = tmpr;
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ Device->PMEM3 = tmpr;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PATT2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PATT3;
+ }
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \
+ FMC_PATT2_ATTHIZ2));
+
+ /* Set FMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U));
+
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ Device->PATT2 = tmpr;
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ Device->PATT3 = tmpr;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the FMC_NAND device
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable the NAND Bank */
+ __FMC_NAND_DISABLE(Device, Bank);
+
+ /* De-initialize the NAND Bank */
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* Set the FMC_NAND_BANK2 registers to their reset values */
+ Device->PCR2 = 0x00000018U;
+ Device->SR2 = 0x00000040U;
+ Device->PMEM2 = 0xFCFCFCFCU;
+ Device->PATT2 = 0xFCFCFCFCU;
+ }
+ /* FMC_Bank3_NAND */
+ else
+ {
+ /* Set the FMC_NAND_BANK3 registers to their reset values */
+ Device->PCR3 = 0x00000018U;
+ Device->SR3 = 0x00000040U;
+ Device->PMEM3 = 0xFCFCFCFCU;
+ Device->PATT3 = 0xFCFCFCFCU;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_LL_NAND_Private_Functions_Group2
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NAND interface.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Enables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Enable ECC feature */
+ if(Bank == FMC_NAND_BANK2)
+ {
+ Device->PCR2 |= FMC_PCR2_ECCEN;
+ }
+ else
+ {
+ Device->PCR3 |= FMC_PCR3_ECCEN;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable ECC feature */
+ if(Bank == FMC_NAND_BANK2)
+ {
+ Device->PCR2 &= ~FMC_PCR2_ECCEN;
+ }
+ else
+ {
+ Device->PCR3 &= ~FMC_PCR3_ECCEN;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FIFO is empty */
+ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* Get the ECCR2 register value */
+ *ECCval = (uint32_t)Device->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ *ECCval = (uint32_t)Device->ECCR3;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
+/**
+ * @}
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @addtogroup FMC_LL_PCCARD
+ * @brief PCCARD Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use PCCARD device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FMC PCCARD bank in order
+ to run the PCCARD/compact flash external devices.
+
+ (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
+ (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
+ (+) FMC PCCARD bank common space timing configuration using the function
+ FMC_PCCARD_CommonSpace_Timing_Init()
+ (+) FMC PCCARD bank attribute space timing configuration using the function
+ FMC_PCCARD_AttributeSpace_Timing_Init()
+ (+) FMC PCCARD bank IO space timing configuration using the function
+ FMC_PCCARD_IOSpace_Timing_Init()
+@endverbatim
+ * @{
+ */
+
+/** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC PCCARD interface
+ (+) De-initialize the FMC PCCARD interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMC_PCCARD device according to the specified
+ * control parameters in the FMC_PCCARD_HandleTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Init Pointer to PCCARD Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ /* Get PCCARD control register value */
+ tmpr = Device->PCR4;
+
+ /* Clear TAR, TCLR, PWAITEN and PWID bits */
+ tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \
+ FMC_PCR4_PWID | FMC_PCR4_PTYP));
+
+ /* Set FMC_PCCARD device control parameters */
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
+ (Init->TCLRSetupTime << 9U) |\
+ (Init->TARSetupTime << 13U));
+
+ Device->PCR4 = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Get PCCARD common space timing register value */
+ tmpr = Device->PMEM4;
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \
+ FMC_PMEM4_MEMHIZ4));
+ /* Set PCCARD timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U));
+
+ Device->PMEM4 = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Get PCCARD timing parameters */
+ tmpr = Device->PATT4;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \
+ FMC_PATT4_ATTHIZ4));
+
+ /* Set PCCARD timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U));
+ Device->PATT4 = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ uint32_t tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Get FMC_PCCARD device timing parameters */
+ tmpr = Device->PIO4;
+
+ /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
+ tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \
+ FMC_PIO4_IOHIZ4));
+
+ /* Set FMC_PCCARD device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U));
+
+ Device->PIO4 = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the FMC_PCCARD device
+ * @param Device Pointer to PCCARD device instance
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+
+ /* Disable the FMC_PCCARD device */
+ __FMC_PCCARD_DISABLE(Device);
+
+ /* De-initialize the FMC_PCCARD device */
+ Device->PCR4 = 0x00000018U;
+ Device->SR4 = 0x00000000U;
+ Device->PMEM4 = 0xFCFCFCFCU;
+ Device->PATT4 = 0xFCFCFCFCU;
+ Device->PIO4 = 0xFCFCFCFCU;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/** @addtogroup FMC_LL_SDRAM
+ * @brief SDRAM Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use SDRAM device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FMC SDRAM banks in order
+ to run the SDRAM external devices.
+
+ (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
+ (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
+ (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
+ (+) FMC SDRAM bank enable/disable write operation using the functions
+ FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
+ (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
+
+@endverbatim
+ * @{
+ */
+
+/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC SDRAM interface
+ (+) De-initialize the FMC SDRAM interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMC_SDRAM device according to the specified
+ * control parameters in the FMC_SDRAM_InitTypeDef
+ * @param Device Pointer to SDRAM device instance
+ * @param Init Pointer to SDRAM Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
+{
+ uint32_t tmpr1 = 0U;
+ uint32_t tmpr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));
+ assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
+ assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
+ assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
+ assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
+ assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
+ assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
+ assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
+ assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
+ assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
+
+ /* Set SDRAM bank configuration parameters */
+ if (Init->SDBank != FMC_SDRAM_BANK2)
+ {
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
+
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+
+ tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
+ Init->RowBitsNumber |\
+ Init->MemoryDataWidth |\
+ Init->InternalBankNumber |\
+ Init->CASLatency |\
+ Init->WriteProtection |\
+ Init->SDClockPeriod |\
+ Init->ReadBurst |\
+ Init->ReadPipeDelay
+ );
+ Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
+ }
+ else /* FMC_Bank2_SDRAM */
+ {
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
+
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+ tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
+ Init->ReadBurst |\
+ Init->ReadPipeDelay);
+
+ tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
+
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+ tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+ tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
+ Init->RowBitsNumber |\
+ Init->MemoryDataWidth |\
+ Init->InternalBankNumber |\
+ Init->CASLatency |\
+ Init->WriteProtection);
+
+ Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
+ Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_SDRAM device timing according to the specified
+ * parameters in the FMC_SDRAM_TimingTypeDef
+ * @param Device Pointer to SDRAM device instance
+ * @param Timing Pointer to SDRAM Timing structure
+ * @param Bank SDRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr1 = 0U;
+ uint32_t tmpr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));
+ assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
+ assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
+ assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
+ assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
+ assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
+ assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
+ assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
+ assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+ /* Set SDRAM device timing parameters */
+ if (Bank != FMC_SDRAM_BANK2)
+ {
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
+
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+ FMC_SDTR1_TRCD));
+
+ tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\
+ (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
+ (((Timing->SelfRefreshTime)-1U) << 8U) |\
+ (((Timing->RowCycleDelay)-1U) << 12U) |\
+ (((Timing->WriteRecoveryTime)-1U) <<16U) |\
+ (((Timing->RPDelay)-1U) << 20U) |\
+ (((Timing->RCDDelay)-1U) << 24U));
+ Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
+ }
+ else /* FMC_Bank2_SDRAM */
+ {
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
+
+ /* Clear TRC and TRP bits */
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
+
+ tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) |\
+ (((Timing->RPDelay)-1U) << 20U));
+
+ tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
+
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+ tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+ FMC_SDTR1_TRCD));
+
+ tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\
+ (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
+ (((Timing->SelfRefreshTime)-1U) << 8U) |\
+ (((Timing->WriteRecoveryTime)-1U) <<16U) |\
+ (((Timing->RCDDelay)-1U) << 24U)));
+
+ Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
+ Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the FMC_SDRAM peripheral
+ * @param Device Pointer to SDRAM device instance
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));
+ assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+ /* De-initialize the SDRAM device */
+ Device->SDCR[Bank] = 0x000002D0U;
+ Device->SDTR[Bank] = 0x0FFFFFFFU;
+ Device->SDCMR = 0x00000000U;
+ Device->SDRTR = 0x00000000U;
+ Device->SDSR = 0x00000000U;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_SDRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC SDRAM interface.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Enables dynamically FMC_SDRAM write protection.
+ * @param Device Pointer to SDRAM device instance
+ * @param Bank SDRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));
+ assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+ /* Enable write protection */
+ Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_SDRAM write protection.
+ * @param hsdram FMC_SDRAM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));
+ assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+ /* Disable write protection */
+ Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Send Command to the FMC SDRAM bank
+ * @param Device Pointer to SDRAM device instance
+ * @param Command Pointer to SDRAM command structure
+ * @param Timing Pointer to SDRAM Timing structure
+ * @param Timeout Timeout wait value
+ * @retval HAL state
+ */
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
+{
+ __IO uint32_t tmpr = 0U;
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));
+ assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
+ assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
+ assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
+
+ /* Set command register */
+ tmpr = (uint32_t)((Command->CommandMode) |\
+ (Command->CommandTarget) |\
+ (((Command->AutoRefreshNumber)-1U) << 5U) |\
+ ((Command->ModeRegisterDefinition) << 9U)
+ );
+
+ Device->SDCMR = tmpr;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until command is send */
+ while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Program the SDRAM Memory Refresh rate.
+ * @param Device Pointer to SDRAM device instance
+ * @param RefreshRate The SDRAM refresh rate value.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));
+ assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
+
+ /* Set the refresh rate in command register */
+ Device->SDRTR |= (RefreshRate<<1U);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
+ * @param Device Pointer to SDRAM device instance
+ * @param AutoRefreshNumber Specifies the auto Refresh number.
+ * @retval None
+ */
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
+
+ /* Set the Auto-refresh number in command register */
+ Device->SDCMR |= (AutoRefreshNumber << 5U);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the indicated FMC SDRAM bank mode status.
+ * @param Device Pointer to SDRAM device instance
+ * @param Bank Defines the FMC SDRAM bank. This parameter can be
+ * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
+ * @retval The FMC SDRAM bank mode status, could be on of the following values:
+ * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
+ * FMC_SDRAM_POWER_DOWN_MODE.
+ */
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));
+ assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+ /* Get the corresponding bank mode */
+ if(Bank == FMC_SDRAM_BANK1)
+ {
+ tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
+ }
+ else
+ {
+ tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
+ }
+
+ /* Return the mode status */
+ return tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1419 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fmc.h
+ * @author MCD Application Team
+ * @brief Header file of FMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_FMC_H
+#define __STM32F4xx_LL_FMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMC_LL
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Types FMC Private Types
+ * @{
+ */
+
+/**
+ * @brief FMC NORSRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
+
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the data bus or not.
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory device.
+ This parameter can be a value of @ref FMC_Memory_Type */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
+
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+
+ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FMC_Wrap_Mode
+ This mode is not available for the STM32F446/467/479xx devices */
+
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Timing */
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
+ This parameter can be a value of @ref FMC_Write_Operation */
+
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal */
+
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FMC_Extended_Mode */
+
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FMC_AsynchronousWait */
+
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FMC_Write_Burst */
+
+ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
+
+ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Write_FIFO
+ This mode is available only for the STM32F446/469/479xx devices */
+
+ uint32_t PageSize; /*!< Specifies the memory page size.
+ This parameter can be a value of @ref FMC_Page_Size */
+}FMC_NORSRAM_InitTypeDef;
+
+/**
+ * @brief FMC NORSRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ NOR Flash memories. */
+
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ accesses. */
+
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FMC_Access_Mode */
+}FMC_NORSRAM_TimingTypeDef;
+
+/**
+ * @brief FMC NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
+ This parameter can be a value of @ref FMC_NAND_Bank */
+
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
+
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FMC_ECC */
+
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_NAND_InitTypeDef;
+
+/**
+ * @brief FMC NAND/PCCARD Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ data bus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_NAND_PCC_TimingTypeDef;
+
+/**
+ * @brief FMC NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_PCCARD_InitTypeDef;
+
+/**
+ * @brief FMC SDRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
+ This parameter can be a value of @ref FMC_SDRAM_Bank */
+
+ uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
+ This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
+
+ uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
+ This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
+
+ uint32_t MemoryDataWidth; /*!< Defines the memory device width.
+ This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
+
+ uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
+ This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
+
+ uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
+ This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
+
+ uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
+ This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
+
+ uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
+ to disable the clock before changing frequency.
+ This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
+
+ uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
+ commands during the CAS latency and stores data in the Read FIFO.
+ This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
+
+ uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
+ This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
+}FMC_SDRAM_InitTypeDef;
+
+/**
+ * @brief FMC SDRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
+ an active or Refresh command in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
+ issuing the Activate command in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
+ cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
+ and the delay between two consecutive Refresh commands in number of
+ memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
+ in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
+ command in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+}FMC_SDRAM_TimingTypeDef;
+
+/**
+ * @brief SDRAM command parameters structure definition
+ */
+typedef struct
+{
+ uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
+ This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
+
+ uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
+ This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
+
+ uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
+ in auto refresh mode.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+ uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
+}FMC_SDRAM_CommandTypeDef;
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Constants FMC Private Constants
+ * @{
+ */
+
+/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
+ * @{
+ */
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
+ * @{
+ */
+#define FMC_NORSRAM_BANK1 0x00000000U
+#define FMC_NORSRAM_BANK2 0x00000002U
+#define FMC_NORSRAM_BANK3 0x00000004U
+#define FMC_NORSRAM_BANK4 0x00000006U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
+ * @{
+ */
+#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
+#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Memory_Type FMC Memory Type
+ * @{
+ */
+#define FMC_MEMORY_TYPE_SRAM 0x00000000U
+#define FMC_MEMORY_TYPE_PSRAM 0x00000004U
+#define FMC_MEMORY_TYPE_NOR 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
+ * @{
+ */
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
+ * @{
+ */
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
+ * @{
+ */
+#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
+#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
+ * @{
+ */
+/** @note This mode is not available for the STM32F446/469/479xx devices
+ */
+#define FMC_WRAP_MODE_DISABLE 0x00000000U
+#define FMC_WRAP_MODE_ENABLE 0x00000400U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
+ * @{
+ */
+#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
+#define FMC_WAIT_TIMING_DURING_WS 0x00000800U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Operation FMC Write Operation
+ * @{
+ */
+#define FMC_WRITE_OPERATION_DISABLE 0x00000000U
+#define FMC_WRITE_OPERATION_ENABLE 0x00001000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
+#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
+ * @{
+ */
+#define FMC_EXTENDED_MODE_DISABLE 0x00000000U
+#define FMC_EXTENDED_MODE_ENABLE 0x00004000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
+ * @{
+ */
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Page_Size FMC Page Size
+ * @{
+ */
+#define FMC_PAGE_SIZE_NONE 0x00000000U
+#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
+#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
+#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
+#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_FIFO FMC Write FIFO
+ * @note These values are available only for the STM32F446/469/479xx devices.
+ * @{
+ */
+#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
+#define FMC_WRITE_FIFO_ENABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Burst FMC Write Burst
+ * @{
+ */
+#define FMC_WRITE_BURST_DISABLE 0x00000000U
+#define FMC_WRITE_BURST_ENABLE 0x00080000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Continous_Clock FMC Continuous Clock
+ * @{
+ */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Access_Mode FMC Access Mode
+ * @{
+ */
+#define FMC_ACCESS_MODE_A 0x00000000U
+#define FMC_ACCESS_MODE_B 0x10000000U
+#define FMC_ACCESS_MODE_C 0x20000000U
+#define FMC_ACCESS_MODE_D 0x30000000U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
+ * @{
+ */
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
+ * @{
+ */
+#define FMC_NAND_BANK2 0x00000010U
+#define FMC_NAND_BANK3 0x00000100U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_feature FMC Wait feature
+ * @{
+ */
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
+ * @{
+ */
+#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
+#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
+ * @{
+ */
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC FMC ECC
+ * @{
+ */
+#define FMC_NAND_ECC_DISABLE 0x00000000U
+#define FMC_NAND_ECC_ENABLE 0x00000040U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
+ * @{
+ */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
+ * @{
+ */
+/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
+ * @{
+ */
+#define FMC_SDRAM_BANK1 0x00000000U
+#define FMC_SDRAM_BANK2 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
+ * @{
+ */
+#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
+#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
+#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
+#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
+ * @{
+ */
+#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
+#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
+#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
+ * @{
+ */
+#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
+#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
+#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
+ * @{
+ */
+#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
+#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
+ * @{
+ */
+#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
+#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
+#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
+ * @{
+ */
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
+ * @{
+ */
+#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
+#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
+#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
+ * @{
+ */
+#define FMC_SDRAM_RBURST_DISABLE 0x00000000U
+#define FMC_SDRAM_RBURST_ENABLE 0x00001000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
+ * @{
+ */
+#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
+#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
+#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
+ * @{
+ */
+#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
+#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
+#define FMC_SDRAM_CMD_PALL 0x00000002U
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
+#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
+#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
+ * @{
+ */
+#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
+#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
+#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
+ * @{
+ */
+#define FMC_SDRAM_NORMAL_MODE 0x00000000U
+#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
+#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
+ * @{
+ */
+#define FMC_IT_RISING_EDGE 0x00000008U
+#define FMC_IT_LEVEL 0x00000010U
+#define FMC_IT_FALLING_EDGE 0x00000020U
+#define FMC_IT_REFRESH_ERROR 0x00004000U
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_Flag_definition FMC Flag definition
+ * @{
+ */
+#define FMC_FLAG_RISING_EDGE 0x00000001U
+#define FMC_FLAG_LEVEL 0x00000002U
+#define FMC_FLAG_FALLING_EDGE 0x00000004U
+#define FMC_FLAG_FEMPT 0x00000040U
+#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
+#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
+#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_Alias_definition FMC Alias definition
+ * @{
+ */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
+#else
+ #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
+ #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
+ #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
+ #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
+
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ #define FMC_NAND_DEVICE FMC_Bank3
+#else
+ #define FMC_NAND_DEVICE FMC_Bank2_3
+ #define FMC_PCCARD_DEVICE FMC_Bank4
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+ #define FMC_NORSRAM_DEVICE FMC_Bank1
+ #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
+ #define FMC_SDRAM_DEVICE FMC_Bank5_6
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Macros FMC Private Macros
+ * @{
+ */
+
+/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
+ * @retval None
+ */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
+ * @retval None
+ */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
+#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
+
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
+/**
+ * @}
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
+ * @brief macros to handle SRAM read/write operations
+ * @{
+ */
+/**
+ * @brief Enable the PCCARD device access.
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
+
+/**
+ * @brief Disable the PCCARD device access.
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
+/**
+ * @}
+ */
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+
+/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
+ * @brief macros to handle FMC flags and interrupts
+ * @{
+ */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__ FMC_NAND instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
+#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__ FMC_NAND instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/**
+ * @brief Enable the PCCARD device interrupt.
+ * @param __INSTANCE__ FMC_PCCARD instance
+ * @param __INTERRUPT__ FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the PCCARD device interrupt.
+ * @param __INSTANCE__ FMC_PCCARD instance
+ * @param __INTERRUPT__ FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the PCCARD device.
+ * @param __INSTANCE__ FMC_PCCARD instance
+ * @param __FLAG__ FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the PCCARD device.
+ * @param __INSTANCE__ FMC_PCCARD instance
+ * @param __FLAG__ FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
+
+/**
+ * @brief Enable the SDRAM device interrupt.
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __INTERRUPT__ FMC_SDRAM interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+ * @retval None
+ */
+#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the SDRAM device interrupt.
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __INTERRUPT__ FMC_SDRAM interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+ * @retval None
+ */
+#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the SDRAM device.
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __FLAG__ FMC_SDRAM flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
+ * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
+ * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the SDRAM device.
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __FLAG__ FMC_SDRAM flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
+ * @retval None
+ */
+#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
+ * @{
+ */
+#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
+ ((BANK) == FMC_NORSRAM_BANK2) || \
+ ((BANK) == FMC_NORSRAM_BANK3) || \
+ ((BANK) == FMC_NORSRAM_BANK4))
+
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FMC_ACCESS_MODE_D))
+
+#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
+ ((BANK) == FMC_NAND_BANK3))
+
+#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
+
+#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
+ ((STATE) == FMC_NAND_ECC_ENABLE))
+
+#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+
+#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
+
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
+ ((__MODE__) == FMC_WRAP_MODE_ENABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+
+#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
+
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
+
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
+
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
+
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
+
+#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
+
+#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
+ ((BANK) == FMC_SDRAM_BANK2))
+
+#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
+
+#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
+
+#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
+ ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
+
+
+#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
+
+#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
+ ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
+ ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
+
+#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
+ ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
+
+
+#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
+ ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
+ ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
+
+#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
+
+#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
+
+#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
+
+#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
+
+#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
+
+#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
+
+#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
+
+#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
+ ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
+
+#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
+ ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
+ ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
+
+#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
+
+#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
+
+#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
+
+#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
+
+#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
+ ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
+
+#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
+ ((SIZE) == FMC_PAGE_SIZE_128) || \
+ ((SIZE) == FMC_PAGE_SIZE_256) || \
+ ((SIZE) == FMC_PAGE_SIZE_512) || \
+ ((SIZE) == FMC_PAGE_SIZE_1024))
+
+#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
+ ((FIFO) == FMC_WRITE_FIFO_ENABLE))
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
+ * @{
+ */
+
+/** @defgroup FMC_LL_NORSRAM NOR SRAM
+ * @{
+ */
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NAND NAND
+ * @{
+ */
+/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @defgroup FMC_LL_PCCARD PCCARD
+ * @{
+ */
+/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @defgroup FMC_LL_SDRAM SDRAM
+ * @{
+ */
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
+ * @{
+ */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_FMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1025 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fsmc.c
+ * @author MCD Application Team
+ * @brief FSMC Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FSMC peripheral features #####
+ ==============================================================================
+ [..] The Flexible static memory controller (FSMC) includes two memory controllers:
+ (+) The NOR/PSRAM memory controller
+ (+) The NAND/PC Card memory controller
+
+ [..] The FSMC functional block makes the interface with synchronous and asynchronous static
+ memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
+ (+) to translate AHB transactions into the appropriate external device protocol.
+ (+) to meet the access time requirements of the external memory devices.
+
+ [..] All external memories share the addresses, data and control signals with the controller.
+ Each external device is accessed by means of a unique Chip Select. The FSMC performs
+ only one access at a time to an external device.
+ The main features of the FSMC controller are the following:
+ (+) Interface with static-memory mapped devices including:
+ (++) Static random access memory (SRAM).
+ (++) Read-only memory (ROM).
+ (++) NOR Flash memory/OneNAND Flash memory.
+ (++) PSRAM (4 memory banks).
+ (++) 16-bit PC Card compatible devices.
+ (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+ data.
+ (+) Independent Chip Select control for each memory bank.
+ (+) Independent configuration for each memory bank.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FSMC_LL FSMC Low Layer
+ * @brief FSMC driver modules
+ * @{
+ */
+
+#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup FSMC_LL_Private_Functions
+ * @{
+ */
+
+/** @addtogroup FSMC_LL_NORSRAM
+ * @brief NORSRAM Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NORSRAM device driver #####
+ ==============================================================================
+
+ [..]
+ This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
+ to run the NORSRAM external devices.
+
+ (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
+ (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
+ (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
+ (+) FSMC NORSRAM bank extended timing configuration using the function
+ FSMC_NORSRAM_Extended_Timing_Init()
+ (+) FSMC NORSRAM bank enable/disable write operation using the functions
+ FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
+
+@endverbatim
+ * @{
+ */
+
+/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FSMC NORSRAM interface
+ (+) De-initialize the FSMC NORSRAM interface
+ (+) Configure the FSMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the FSMC_NORSRAM device according to the specified
+ * control parameters in the FSMC_NORSRAM_InitTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Init Pointer to NORSRAM Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
+ assert_param(IS_FSMC_MUX(Init->DataAddressMux));
+ assert_param(IS_FSMC_MEMORY(Init->MemoryType));
+ assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
+ assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+ assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+ assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
+ assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
+ assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
+ assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
+ assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
+ assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+ assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
+ assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+#endif /* STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
+
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Init->NSBank];
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */
+ tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
+ FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
+ FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
+ FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
+ FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW));
+ /* Set NORSRAM device control parameters */
+ tmpr |= (uint32_t)(Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WrapMode |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->PageSize |\
+ Init->WriteBurst
+ );
+#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */
+ tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
+ FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
+ FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \
+ FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \
+ FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \
+ FSMC_BCR1_WFDIS));
+ /* Set NORSRAM device control parameters */
+ tmpr |= (uint32_t)(Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->WriteBurst |\
+ Init->ContinuousClock |\
+ Init->PageSize |\
+ Init->WriteFifo);
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+ if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
+ {
+ tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
+ }
+
+ Device->BTCR[Init->NSBank] = tmpr;
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+ /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+ if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
+ {
+ Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
+ }
+
+ if(Init->NSBank != FSMC_NORSRAM_BANK1)
+ {
+ Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
+ }
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the FSMC_NORSRAM peripheral
+ * @param Device Pointer to NORSRAM device instance
+ * @param ExDevice Pointer to NORSRAM extended mode device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+ assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+ /* Disable the FSMC_NORSRAM device */
+ __FSMC_NORSRAM_DISABLE(Device, Bank);
+
+ /* De-initialize the FSMC_NORSRAM device */
+ /* FSMC_NORSRAM_BANK1 */
+ if(Bank == FSMC_NORSRAM_BANK1)
+ {
+ Device->BTCR[Bank] = 0x000030DBU;
+ }
+ /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
+ else
+ {
+ Device->BTCR[Bank] = 0x000030D2U;
+ }
+
+ Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
+ ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initialize the FSMC_NORSRAM Timing according to the specified
+ * parameters in the FSMC_NORSRAM_TimingTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+ assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
+ assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
+ assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+ /* Get the BTCR register value */
+ tmpr = Device->BTCR[Bank + 1U];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
+ FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
+ FSMC_BTR1_ACCMOD));
+
+ /* Set FSMC_NORSRAM device timing parameters */
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4U) |\
+ ((Timing->DataSetupTime) << 8U) |\
+ ((Timing->BusTurnAroundDuration) << 16U) |\
+ (((Timing->CLKDivision)-1U) << 20U) |\
+ (((Timing->DataLatency)-2U) << 24U) |\
+ (Timing->AccessMode));
+
+ Device->BTCR[Bank + 1] = tmpr;
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+ /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+ if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
+ {
+ tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
+ tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U);
+ Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr;
+ }
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
+ * parameters in the FSMC_NORSRAM_TimingTypeDef
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
+
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+ if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
+ {
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+ assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+ /* Get the BWTR register value */
+ tmpr = Device->BWTR[Bank];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
+ tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
+ FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD));
+
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << 4U) |\
+ ((Timing->DataSetupTime) << 8U) |\
+ ((Timing->BusTurnAroundDuration) << 16U) |\
+ (Timing->AccessMode));
+
+ Device->BWTR[Bank] = tmpr;
+ }
+ else
+ {
+ Device->BWTR[Bank] = 0x0FFFFFFFU;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FSMC_NORSRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FSMC NORSRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically FSMC_NORSRAM write operation.
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+ /* Enable write operation */
+ Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FSMC_NORSRAM write operation.
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+ /* Disable write operation */
+ Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/** @addtogroup FSMC_LL_NAND
+ * @brief NAND Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NAND device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FSMC NAND banks in order
+ to run the NAND external devices.
+
+ (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
+ (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
+ (+) FSMC NAND bank common space timing configuration using the function
+ FSMC_NAND_CommonSpace_Timing_Init()
+ (+) FSMC NAND bank attribute space timing configuration using the function
+ FSMC_NAND_AttributeSpace_Timing_Init()
+ (+) FSMC NAND bank enable/disable ECC correction feature using the functions
+ FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
+ (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
+
+@endverbatim
+ * @{
+ */
+
+/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FSMC NAND interface
+ (+) De-initialize the FSMC NAND interface
+ (+) Configure the FSMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FSMC_NAND device according to the specified
+ * control parameters in the FSMC_NAND_HandleTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
+ assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
+ assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
+ assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
+
+ if(Init->NandBank == FSMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PCR2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PCR3;
+ }
+
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
+ FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
+ FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
+
+ /* Set NAND device control parameters */
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FSMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << 9U) |\
+ ((Init->TARSetupTime) << 13U));
+
+ if(Init->NandBank == FSMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ Device->PCR2 = tmpr;
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ Device->PCR3 = tmpr;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FSMC_NAND Common space Timing according to the specified
+ * parameters in the FSMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PMEM2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PMEM3;
+ }
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
+ FSMC_PMEM2_MEMHIZ2));
+
+ /* Set FSMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U)
+ );
+
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ Device->PMEM2 = tmpr;
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ Device->PMEM3 = tmpr;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
+ * parameters in the FSMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* Get the NAND bank 2 register value */
+ tmpr = Device->PATT2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmpr = Device->PATT3;
+ }
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
+ FSMC_PATT2_ATTHIZ2));
+
+ /* Set FSMC_NAND device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U)
+ );
+
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ Device->PATT2 = tmpr;
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ Device->PATT3 = tmpr;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the FSMC_NAND device
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Disable the NAND Bank */
+ __FSMC_NAND_DISABLE(Device, Bank);
+
+ /* De-initialize the NAND Bank */
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* Set the FSMC_NAND_BANK2 registers to their reset values */
+ Device->PCR2 = 0x00000018U;
+ Device->SR2 = 0x00000040U;
+ Device->PMEM2 = 0xFCFCFCFCU;
+ Device->PATT2 = 0xFCFCFCFCU;
+ }
+ /* FSMC_Bank3_NAND */
+ else
+ {
+ /* Set the FSMC_NAND_BANK3 registers to their reset values */
+ Device->PCR3 = 0x00000018U;
+ Device->SR3 = 0x00000040U;
+ Device->PMEM3 = 0xFCFCFCFCU;
+ Device->PATT3 = 0xFCFCFCFCU;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FSMC_NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FSMC NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically FSMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Enable ECC feature */
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ Device->PCR2 |= FSMC_PCR2_ECCEN;
+ }
+ else
+ {
+ Device->PCR3 |= FSMC_PCR3_ECCEN;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FSMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Disable ECC feature */
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ Device->PCR2 &= ~FSMC_PCR2_ECCEN;
+ }
+ else
+ {
+ Device->PCR3 &= ~FSMC_PCR3_ECCEN;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FSMC_NAND ECC feature.
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_NAND_DEVICE(Device));
+ assert_param(IS_FSMC_NAND_BANK(Bank));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FIFO is empty */
+ while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if(Bank == FSMC_NAND_BANK2)
+ {
+ /* Get the ECCR2 register value */
+ *ECCval = (uint32_t)Device->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ *ECCval = (uint32_t)Device->ECCR3;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FSMC_LL_PCCARD
+ * @brief PCCARD Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use PCCARD device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
+ to run the PCCARD/compact flash external devices.
+
+ (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
+ (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
+ (+) FSMC PCCARD bank common space timing configuration using the function
+ FSMC_PCCARD_CommonSpace_Timing_Init()
+ (+) FSMC PCCARD bank attribute space timing configuration using the function
+ FSMC_PCCARD_AttributeSpace_Timing_Init()
+ (+) FSMC PCCARD bank IO space timing configuration using the function
+ FSMC_PCCARD_IOSpace_Timing_Init()
+
+@endverbatim
+ * @{
+ */
+
+/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FSMC PCCARD interface
+ (+) De-initialize the FSMC PCCARD interface
+ (+) Configure the FSMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FSMC_PCCARD device according to the specified
+ * control parameters in the FSMC_PCCARD_HandleTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Init Pointer to PCCARD Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
+
+ /* Get PCCARD control register value */
+ tmpr = Device->PCR4;
+
+ /* Clear TAR, TCLR, PWAITEN and PWID bits */
+ tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
+ FSMC_PCR4_PWID | FSMC_PCR4_PTYP));
+
+ /* Set FSMC_PCCARD device control parameters */
+ tmpr |= (uint32_t)(Init->Waitfeature |\
+ FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
+ (Init->TCLRSetupTime << 9U) |\
+ (Init->TARSetupTime << 13U));
+
+ Device->PCR4 = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
+ * parameters in the FSMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Get PCCARD common space timing register value */
+ tmpr = Device->PMEM4;
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
+ FSMC_PMEM4_MEMHIZ4));
+ /* Set PCCARD timing parameters */
+ tmpr |= (uint32_t)((Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ (Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U));
+
+ Device->PMEM4 = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
+ * parameters in the FSMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Get PCCARD timing parameters */
+ tmpr = Device->PATT4;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
+ FSMC_PATT4_ATTHIZ4));
+
+ /* Set PCCARD timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U));
+ Device->PATT4 = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
+ * parameters in the FSMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ uint32_t tmpr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Get FSMC_PCCARD device timing parameters */
+ tmpr = Device->PIO4;
+
+ /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
+ tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
+ FSMC_PIO4_IOHIZ4));
+
+ /* Set FSMC_PCCARD device timing parameters */
+ tmpr |= (uint32_t)(Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << 8U) |\
+ ((Timing->HoldSetupTime) << 16U) |\
+ ((Timing->HiZSetupTime) << 24U));
+
+ Device->PIO4 = tmpr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the FSMC_PCCARD device
+ * @param Device Pointer to PCCARD device instance
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
+{
+ /* Disable the FSMC_PCCARD device */
+ __FSMC_PCCARD_DISABLE(Device);
+
+ /* De-initialize the FSMC_PCCARD device */
+ Device->PCR4 = 0x00000018U;
+ Device->SR4 = 0x00000000U;
+ Device->PMEM4 = 0xFCFCFCFCU;
+ Device->PATT4 = 0xFCFCFCFCU;
+ Device->PIO4 = 0xFCFCFCFCU;
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
+#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1049 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fsmc.h
+ * @author MCD Application Team
+ * @brief Header file of FSMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_FSMC_H
+#define __STM32F4xx_LL_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FSMC_LL
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Types FSMC Private Types
+ * @{
+ */
+
+/**
+ * @brief FSMC NORSRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the data bus or not.
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory device.
+ This parameter can be a value of @ref FSMC_Memory_Type */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
+
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wrap_Mode
+ This mode is available only for the STM32F405/407/4015/417xx devices */
+
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Timing */
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
+
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal */
+
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FSMC_Extended_Mode */
+
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FSMC_Write_Burst */
+
+ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock
+ This mode is available only for the STM32F412Vx/Zx/Rx devices */
+
+ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Write_FIFO
+ This mode is available only for the STM32F412Vx/Vx devices */
+
+ uint32_t PageSize; /*!< Specifies the memory page size.
+ This parameter can be a value of @ref FMC_Page_Size */
+}FSMC_NORSRAM_InitTypeDef;
+
+/**
+ * @brief FSMC NORSRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ NOR Flash memories. */
+
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ accesses. */
+
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FSMC_Access_Mode */
+
+}FSMC_NORSRAM_TimingTypeDef;
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/**
+ * @brief FSMC NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FSMC_NAND_Data_Width */
+
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FSMC_ECC */
+
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_NAND_InitTypeDef;
+
+/**
+ * @brief FSMC NAND/PCCARD Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ data bus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_NAND_PCC_TimingTypeDef;
+
+/**
+ * @brief FSMC NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_PCCARD_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
+ * @{
+ */
+
+/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
+ * @{
+ */
+/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
+ * @{
+ */
+#define FSMC_NORSRAM_BANK1 0x00000000U
+#define FSMC_NORSRAM_BANK2 0x00000002U
+#define FSMC_NORSRAM_BANK3 0x00000004U
+#define FSMC_NORSRAM_BANK4 0x00000006U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
+ * @{
+ */
+#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
+#define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Memory_Type FSMC Memory Type
+ * @{
+ */
+#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
+#define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
+#define FSMC_MEMORY_TYPE_NOR 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
+ * @{
+ */
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
+ * @{
+ */
+#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
+#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
+ * @{
+ */
+#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
+#define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
+ * @{
+ */
+#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
+#define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
+ * @note These values are available only for the STM32F405/415/407/417xx devices.
+ * @{
+ */
+#define FSMC_WRAP_MODE_DISABLE 0x00000000U
+#define FSMC_WRAP_MODE_ENABLE 0x00000400U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
+ * @{
+ */
+#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
+#define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Operation FSMC Write Operation
+ * @{
+ */
+#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
+#define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
+ * @{
+ */
+#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
+#define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
+ * @{
+ */
+#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
+#define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
+ * @{
+ */
+#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
+#define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Page_Size FSMC Page Size
+ * @{
+ */
+#define FSMC_PAGE_SIZE_NONE 0x00000000U
+#define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
+#define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
+#define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
+#define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_FIFO FSMC Write FIFO
+ * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
+ * @{
+ */
+#define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
+#define FSMC_WRITE_FIFO_ENABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Burst FSMC Write Burst
+ * @{
+ */
+#define FSMC_WRITE_BURST_DISABLE 0x00000000U
+#define FSMC_WRITE_BURST_ENABLE 0x00080000U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Continous_Clock FSMC Continous Clock
+ * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
+ * @{
+ */
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Access_Mode FSMC Access Mode
+ * @{
+ */
+#define FSMC_ACCESS_MODE_A 0x00000000U
+#define FSMC_ACCESS_MODE_B 0x10000000U
+#define FSMC_ACCESS_MODE_C 0x20000000U
+#define FSMC_ACCESS_MODE_D 0x30000000U
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
+ * @{
+ */
+/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
+ * @{
+ */
+#define FSMC_NAND_BANK2 0x00000010U
+#define FSMC_NAND_BANK3 0x00000100U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_feature FSMC Wait feature
+ * @{
+ */
+#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
+#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
+ * @{
+ */
+#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
+#define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
+ * @{
+ */
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC FSMC ECC
+ * @{
+ */
+#define FSMC_NAND_ECC_DISABLE 0x00000000U
+#define FSMC_NAND_ECC_ENABLE 0x00000040U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
+ * @{
+ */
+#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
+#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
+#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
+#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
+#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
+#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
+ * @{
+ */
+#define FSMC_IT_RISING_EDGE 0x00000008U
+#define FSMC_IT_LEVEL 0x00000010U
+#define FSMC_IT_FALLING_EDGE 0x00000020U
+#define FSMC_IT_REFRESH_ERROR 0x00004000U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
+ * @{
+ */
+#define FSMC_FLAG_RISING_EDGE 0x00000001U
+#define FSMC_FLAG_LEVEL 0x00000002U
+#define FSMC_FLAG_FALLING_EDGE 0x00000004U
+#define FSMC_FLAG_FEMPT 0x00000040U
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
+ * @{
+ */
+#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
+#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#define FSMC_NORSRAM_DEVICE FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FSMC_NAND_DEVICE FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE FSMC_Bank4
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
+
+#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
+#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
+#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
+
+#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
+#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
+#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
+#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
+#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
+#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
+
+#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
+#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
+#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
+#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
+
+#define FMC_NAND_Init FSMC_NAND_Init
+#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
+#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
+#define FMC_NAND_DeInit FSMC_NAND_DeInit
+#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
+#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
+#define FMC_NAND_GetECC FSMC_NAND_GetECC
+#define FMC_PCCARD_Init FSMC_PCCARD_Init
+#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
+#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
+#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
+#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
+
+#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
+#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
+#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
+#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
+#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
+#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
+#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
+#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
+#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
+#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
+#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
+#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
+#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
+#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
+#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
+
+#define FMC_NAND_BANK2 FSMC_NAND_BANK2
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
+#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
+#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
+
+#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
+#define FMC_IT_LEVEL FSMC_IT_LEVEL
+#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
+#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
+
+#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
+#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
+#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
+#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
+ * @{
+ */
+
+/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__ FSMC_NORSRAM Instance
+ * @param __BANK__ FSMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__ FSMC_NORSRAM Instance
+ * @param __BANK__ FSMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @retval none
+ */
+#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @retval none
+ */
+#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
+ * @brief macros to handle SRAM read/write operations
+ * @{
+ */
+/**
+ * @brief Enable the PCCARD device access.
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @retval none
+ */
+#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
+
+/**
+ * @brief Disable the PCCARD device access.
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @retval none
+ */
+#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
+ * @brief macros to handle FSMC flags and interrupts
+ * @{
+ */
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @param __INTERRUPT__ FSMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @param __INTERRUPT__ FSMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @param __FLAG__ FSMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @param __FLAG__ FSMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+
+/**
+ * @brief Enable the PCCARD device interrupt.
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __INTERRUPT__ FSMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the PCCARD device interrupt.
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __INTERRUPT__ FSMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the PCCARD device.
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __FLAG__ FSMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the PCCARD device.
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __FLAG__ FSMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
+ * @{
+ */
+#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK4))
+
+#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
+
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_D))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
+ ((BANK) == FSMC_NAND_BANK3))
+
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
+ ((STATE) == FSMC_NAND_ECC_ENABLE))
+
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
+
+#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
+
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
+
+#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
+
+#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
+
+#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
+ ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
+
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
+
+#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
+
+#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
+
+#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
+
+#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
+
+#define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
+ ((SIZE) == FSMC_PAGE_SIZE_128) || \
+ ((SIZE) == FSMC_PAGE_SIZE_256) || \
+ ((SIZE) == FSMC_PAGE_SIZE_512) || \
+ ((SIZE) == FSMC_PAGE_SIZE_1024))
+
+#define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
+ ((FIFO) == FSMC_WRITE_FIFO_ENABLE))
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
+ * @{
+ */
+
+/** @defgroup FSMC_LL_NORSRAM NOR SRAM
+ * @{
+ */
+
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/** @defgroup FSMC_LL_NAND NAND
+ * @{
+ */
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_PCCARD PCCARD
+ * @{
+ */
+/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_FSMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,323 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_gpio.h"
+#include "stm32f4xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @addtogroup GPIO_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
+ ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
+ ((__VALUE__) == LL_GPIO_PULL_UP) ||\
+ ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_1 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_2 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_3 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_4 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_5 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_6 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_7 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_8 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_9 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_10 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_11 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_12 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_13 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_14 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize GPIO registers (Registers restored to their default values).
+ * @param GPIOx GPIO Port
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are de-initialized
+ * - ERROR: Wrong GPIO Port
+ */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Force and Release reset on clock of GPIOx Port */
+ if (GPIOx == GPIOA)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+ }
+#if defined(GPIOD)
+ else if (GPIOx == GPIOD)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+ }
+#endif /* GPIOD */
+#if defined(GPIOE)
+ else if (GPIOx == GPIOE)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+ }
+#endif /* GPIOE */
+#if defined(GPIOF)
+ else if (GPIOx == GPIOF)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+ }
+#endif /* GPIOF */
+#if defined(GPIOG)
+ else if (GPIOx == GPIOG)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+ }
+#endif /* GPIOG */
+#if defined(GPIOH)
+ else if (GPIOx == GPIOH)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+ }
+#endif /* GPIOH */
+#if defined(GPIOI)
+ else if (GPIOx == GPIOI)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI);
+ }
+#endif /* GPIOI */
+#if defined(GPIOJ)
+ else if (GPIOx == GPIOJ)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
+ }
+#endif /* GPIOJ */
+#if defined(GPIOK)
+ else if (GPIOx == GPIOK)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK);
+ }
+#endif /* GPIOK */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+ * @param GPIOx GPIO Port
+ * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+ * that contains the configuration information for the specified GPIO peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00000000U;
+ uint32_t currentpin = 0x00000000U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+ assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+ /* Configure the port pins */
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+ {
+ /* Get current io position */
+ currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+
+ if (currentpin)
+ {
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+ /* Speed mode configuration */
+ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+ }
+
+ /* Pull-up Pull down resistor configuration*/
+ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+ if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+ {
+ /* Check Alternate parameter */
+ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+ /* Speed mode configuration */
+ if (POSITION_VAL(currentpin) < 0x00000008U)
+ {
+ LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ else
+ {
+ LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ }
+ }
+ pinpos++;
+ }
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
+ }
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+ * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
+ GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
+ GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,998 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_GPIO_H
+#define __STM32F4xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @defgroup GPIO_LL GPIO
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL GPIO Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+ uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+ uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+ uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \
+ GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \
+ GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \
+ GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
+ GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
+ GPIO_BSRR_BS_15) /*!< Select all pins */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+ * @{
+ */
+#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+ * @{
+ */
+#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
+#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+ * @{
+ */
+#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+ * @{
+ */
+#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_SetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+ MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_GetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->MODER,
+ (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @param OutputType This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+ * @brief Return gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+ * @brief Configure gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Speed This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
+{
+ MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
+ (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+ (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Pull This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+ MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+ (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
+ (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+ (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
+ (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+ (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+
+/**
+ * @brief Lock configuration of several pins for a dedicated port.
+ * @note When the lock sequence has been applied on a port bit, the
+ * value of this port bit can no longer be modified until the
+ * next reset.
+ * @note Each lock bit freezes a specific configuration register
+ * (control and alternate function registers).
+ * @rmtoll LCKR LCKK LL_GPIO_LockPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ __IO uint32_t temp;
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ WRITE_REG(GPIOx->LCKR, PinMask);
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ temp = READ_REG(GPIOx->LCKR);
+ (void) temp;
+}
+
+/**
+ * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+ * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
+}
+
+/**
+ * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
+ * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
+ * @param GPIOx GPIO Port
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+ return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+ * @{
+ */
+
+/**
+ * @brief Return full input data register value for a dedicated port.
+ * @rmtoll IDR IDy LL_GPIO_ReadInputPort
+ * @param GPIOx GPIO Port
+ * @retval Input data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
+}
+
+/**
+ * @brief Write output data register for the port.
+ * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
+ * @param GPIOx GPIO Port
+ * @param PortValue Level value for each pin of the port
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+ WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+ * @brief Return full output data register value for a dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
+ * @param GPIOx GPIO Port
+ * @retval Output data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
+}
+
+/**
+ * @brief Set several pins to high level on dedicated gpio port.
+ * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+ * @brief Set several pins to low level on dedicated gpio port.
+ * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BSRR, (PinMask << 16));
+}
+
+/**
+ * @brief Toggle data value for several pin of dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_TogglePin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_i2c.c
+ * @author MCD Application Team
+ * @brief I2C LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_i2c.h"
+#include "stm32f4xx_ll_bus.h"
+#include "stm32f4xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
+
+#define IS_LL_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
+ ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
+
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
+ ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
+
+#endif
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
+ ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+ ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the I2C registers to their default reset values.
+ * @param I2Cx I2C Instance.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are de-initialized
+ * - ERROR: I2C registers are not de-initialized
+ */
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+ }
+ else if (I2Cx == I2C2)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ }
+#if defined(I2C3)
+ else if (I2Cx == I2C3)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
+ }
+#endif
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+ * @param I2Cx I2C Instance.
+ * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are initialized
+ * - ERROR: Not applicable
+ */
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ LL_RCC_ClocksTypeDef rcc_clocks;
+
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ /* Check the I2C parameters from I2C_InitStruct */
+ assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+ assert_param(IS_LL_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
+ assert_param(IS_LL_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+ assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
+ assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
+#endif
+ assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+ assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+ assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+ /* Disable the selected I2Cx Peripheral */
+ LL_I2C_Disable(I2Cx);
+
+ /* Retrieve Clock frequencies */
+ LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+ /*---------------------------- I2Cx FLTR Configuration -----------------------
+ * Configure the analog and digital noise filters with parameters :
+ * - AnalogFilter: I2C_FLTR_ANFOFF bit
+ * - DigitalFilter: I2C_FLTR_DNF[3:0] bits
+ */
+ LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
+
+#endif
+ /*---------------------------- I2Cx SCL Clock Speed Configuration ------------
+ * Configure the SCL speed :
+ * - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS,
+ * and I2C_CCR_CCR[11:0] bits
+ * - DutyCycle: I2C_CCR_DUTY[7:0] bits
+ */
+ LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle);
+
+ /*---------------------------- I2Cx OAR1 Configuration -----------------------
+ * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+ * - OwnAddress1: I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits
+ * - OwnAddrSize: I2C_OAR1_ADDMODE bit
+ */
+ LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+
+ /*---------------------------- I2Cx MODE Configuration -----------------------
+ * Configure I2Cx peripheral mode with parameter :
+ * - PeripheralMode: I2C_CR1_SMBUS, I2C_CR1_SMBTYPE and I2C_CR1_ENARP bits
+ */
+ LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+ /* Enable the selected I2Cx Peripheral */
+ LL_I2C_Enable(I2Cx);
+
+ /*---------------------------- I2Cx CR2 Configuration ------------------------
+ * Configure the ACKnowledge or Non ACKnowledge condition
+ * after the address receive match code or next received byte with parameter :
+ * - TypeAcknowledge: I2C_CR2_NACK bit
+ */
+ LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
+ * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval None
+ */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Set I2C_InitStruct fields to default values */
+ I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
+ I2C_InitStruct->ClockSpeed = 5000U;
+ I2C_InitStruct->DutyCycle = LL_I2C_DUTYCYCLE_2;
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+ I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
+ I2C_InitStruct->DigitalFilter = 0U;
+#endif
+ I2C_InitStruct->OwnAddress1 = 0U;
+ I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+ I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1908 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_i2c.h
+ * @author MCD Application Team
+ * @brief Header file of I2C LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_I2C_H
+#define __STM32F4xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+ * @{
+ */
+
+/* Defines used to perform compute and check in the macros */
+#define LL_I2C_MAX_SPEED_STANDARD 100000U
+#define LL_I2C_MAX_SPEED_FAST 400000U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
+ This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+
+ uint32_t ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz (in Hz)
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
+ or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
+
+ uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
+
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
+
+ This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+ uint32_t DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
+
+#endif
+ uint32_t OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+
+ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+ This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2C_ReadReg function
+ * @{
+ */
+#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
+#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
+ Address matched flag (slave mode) */
+#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
+#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
+#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
+#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
+#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
+#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
+#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
+#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
+#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
+#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
+#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
+#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
+#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
+#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
+#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
+#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
+#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
+ * @{
+ */
+#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
+#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
+#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
+/**
+ * @}
+ */
+
+#if defined(I2C_FLTR_ANOFF)
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+ * @{
+ */
+#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
+#define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/
+/**
+ * @}
+ */
+
+#endif
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+ * @{
+ */
+#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
+ * @{
+ */
+#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
+#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
+ * @{
+ */
+#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
+#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+ * @{
+ */
+#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
+#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
+#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+ * @{
+ */
+#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+ * @{
+ */
+#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
+#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ * @{
+ */
+
+/**
+ * @brief Convert Peripheral Clock Frequency in Mhz.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+ * @retval Value of peripheral clock (in Mhz)
+ */
+#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
+
+/**
+ * @brief Convert Peripheral Clock Frequency in Hz.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
+ * @retval Value of peripheral clock (in Hz)
+ */
+#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
+
+/**
+ * @brief Compute I2C Clock rising time.
+ * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
+ * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
+ * @retval Value between Min_Data=0x02 and Max_Data=0x3F
+ */
+#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
+
+/**
+ * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+ * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
+ * @param __DUTYCYCLE__ This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
+ */
+#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
+ (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
+ (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
+
+/**
+ * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+ * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
+ * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
+ */
+#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
+
+/**
+ * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+ * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
+ * @param __DUTYCYCLE__ This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
+ */
+#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
+ (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
+ (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
+
+/**
+ * @brief Get the Least significant bits of a 10-Bits address.
+ * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+/**
+ * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
+ * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
+ * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
+ */
+#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+
+/**
+ * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
+ * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
+ * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
+ */
+#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable I2C peripheral (PE = 1).
+ * @rmtoll CR1 PE LL_I2C_Enable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Disable I2C peripheral (PE = 0).
+ * @rmtoll CR1 PE LL_I2C_Disable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Check if the I2C peripheral is enabled or disabled.
+ * @rmtoll CR1 PE LL_I2C_IsEnabled
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
+}
+
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+/**
+ * @brief Configure Noise Filters (Analog and Digital).
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * The filters can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n
+ * FLTR DNF LL_I2C_ConfigFilters
+ * @param I2Cx I2C Instance.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+ * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
+ * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+ MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter);
+}
+#endif
+#if defined(I2C_FLTR_DNF)
+
+/**
+ * @brief Configure Digital Noise Filter.
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter
+ * @param I2Cx I2C Instance.
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
+ * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+ MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter);
+}
+
+/**
+ * @brief Get the current Digital Noise Filter configuration.
+ * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF));
+}
+#endif
+#if defined(I2C_FLTR_ANOFF)
+
+/**
+ * @brief Enable Analog Noise Filter.
+ * @note This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
+}
+
+/**
+ * @brief Disable Analog Noise Filter.
+ * @note This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
+}
+
+/**
+ * @brief Check if Analog Noise Filter is enabled or disabled.
+ * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF));
+}
+#endif
+
+/**
+ * @brief Enable DMA transmission requests.
+ * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+ * @brief Disable DMA transmission requests.
+ * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+ * @brief Check if DMA transmission requests are enabled or disabled.
+ * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
+}
+
+/**
+ * @brief Enable DMA reception requests.
+ * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+ * @brief Disable DMA reception requests.
+ * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+ * @brief Check if DMA reception requests are enabled or disabled.
+ * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer.
+ * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
+ * @param I2Cx I2C Instance.
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t) & (I2Cx->DR);
+}
+
+/**
+ * @brief Enable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Disable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Check if Clock stretching is enabled or disabled.
+ * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
+}
+
+/**
+ * @brief Enable General Call.
+ * @note When enabled the Address 0x00 is ACKed.
+ * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
+}
+
+/**
+ * @brief Disable General Call.
+ * @note When disabled the Address 0x00 is NACKed.
+ * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
+}
+
+/**
+ * @brief Check if General Call is enabled or disabled.
+ * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
+}
+
+/**
+ * @brief Set the Own Address1.
+ * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
+ * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
+ * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
+ * OAR1 ADDMODE LL_I2C_SetOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+ * @param OwnAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_I2C_OWNADDRESS1_7BIT
+ * @arg @ref LL_I2C_OWNADDRESS1_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+ MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+ * @brief Set the 7bits Own Address2.
+ * @note This action has no effect if own address2 is enabled.
+ * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
+{
+ MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
+}
+
+/**
+ * @brief Configure the Peripheral clock frequency.
+ * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
+ * @param I2Cx I2C Instance.
+ * @param PeriphClock Peripheral Clock (in Hz)
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
+}
+
+/**
+ * @brief Get the Peripheral clock frequency.
+ * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
+ * @param I2Cx I2C Instance.
+ * @retval Value of Peripheral Clock (in Hz)
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
+}
+
+/**
+ * @brief Configure the Duty cycle (Fast mode only).
+ * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
+ * @param I2Cx I2C Instance.
+ * @param DutyCycle This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
+{
+ MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
+}
+
+/**
+ * @brief Get the Duty cycle (Fast mode only).
+ * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
+}
+
+/**
+ * @brief Configure the I2C master clock speed mode.
+ * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
+ * @param I2Cx I2C Instance.
+ * @param ClockSpeedMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
+ * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
+{
+ MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
+}
+
+/**
+ * @brief Get the the I2C master speed mode.
+ * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
+ * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
+}
+
+/**
+ * @brief Configure the SCL, SDA rising time.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
+ * @param I2Cx I2C Instance.
+ * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
+{
+ MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
+}
+
+/**
+ * @brief Get the SCL, SDA rising time.
+ * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x02 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
+}
+
+/**
+ * @brief Configure the SCL high and low period.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CCR CCR LL_I2C_SetClockPeriod
+ * @param I2Cx I2C Instance.
+ * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
+{
+ MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
+}
+
+/**
+ * @brief Get the SCL high and low period.
+ * @rmtoll CCR CCR LL_I2C_GetClockPeriod
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
+}
+
+/**
+ * @brief Configure the SCL speed.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
+ * TRISE TRISE LL_I2C_ConfigSpeed\n
+ * CCR FS LL_I2C_ConfigSpeed\n
+ * CCR DUTY LL_I2C_ConfigSpeed\n
+ * CCR CCR LL_I2C_ConfigSpeed
+ * @param I2Cx I2C Instance.
+ * @param PeriphClock Peripheral Clock (in Hz)
+ * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
+ * @param DutyCycle This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
+ uint32_t DutyCycle)
+{
+ register uint32_t freqrange = 0x0U;
+ register uint32_t clockconfig = 0x0U;
+
+ /* Compute frequency range */
+ freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
+
+ /* Configure I2Cx: Frequency range register */
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
+
+ /* Configure I2Cx: Rise Time register */
+ MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
+
+ /* Configure Speed mode, Duty Cycle and Clock control register value */
+ if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
+ {
+ /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
+ clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
+ __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
+ DutyCycle;
+ }
+ else
+ {
+ /* Set Speed mode at standard for Clock Speed request in standard clock range */
+ clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
+ __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
+ }
+
+ /* Configure I2Cx: Clock control register */
+ MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
+}
+
+/**
+ * @brief Configure peripheral mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
+ * CR1 SMBTYPE LL_I2C_SetMode\n
+ * CR1 ENARP LL_I2C_SetMode
+ * @param I2Cx I2C Instance.
+ * @param PeripheralMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
+}
+
+/**
+ * @brief Get peripheral mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
+ * CR1 SMBTYPE LL_I2C_GetMode\n
+ * CR1 ENARP LL_I2C_GetMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
+}
+
+/**
+ * @brief Enable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is drived low and
+ * Alert Response Address Header acknowledge is enabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is supported.
+ * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
+}
+
+/**
+ * @brief Disable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+ * Alert Response Address Header acknowledge is disabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is not supported.
+ * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
+}
+
+/**
+ * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
+}
+
+/**
+ * @brief Enable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
+}
+
+/**
+ * @brief Disable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
+}
+
+/**
+ * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable TXE interrupt.
+ * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
+ * CR2 ITBUFEN LL_I2C_EnableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Disable TXE interrupt.
+ * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
+ * CR2 ITBUFEN LL_I2C_DisableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Check if the TXE Interrupt is enabled or disabled.
+ * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
+ * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
+}
+
+/**
+ * @brief Enable RXNE interrupt.
+ * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
+ * CR2 ITBUFEN LL_I2C_EnableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Disable RXNE interrupt.
+ * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
+ * CR2 ITBUFEN LL_I2C_DisableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Check if the RXNE Interrupt is enabled or disabled.
+ * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
+ * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
+}
+
+/**
+ * @brief Enable Events interrupts.
+ * @note Any of these events will generate interrupt :
+ * Start Bit (SB)
+ * Address sent, Address matched (ADDR)
+ * 10-bit header sent (ADD10)
+ * Stop detection (STOPF)
+ * Byte transfer finished (BTF)
+ *
+ * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
+ * Receive buffer not empty (RXNE)
+ * Transmit buffer empty (TXE)
+ * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
+}
+
+/**
+ * @brief Disable Events interrupts.
+ * @note Any of these events will generate interrupt :
+ * Start Bit (SB)
+ * Address sent, Address matched (ADDR)
+ * 10-bit header sent (ADD10)
+ * Stop detection (STOPF)
+ * Byte transfer finished (BTF)
+ * Receive buffer not empty (RXNE)
+ * Transmit buffer empty (TXE)
+ * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
+}
+
+/**
+ * @brief Check if Events interrupts are enabled or disabled.
+ * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
+}
+
+/**
+ * @brief Enable Buffer interrupts.
+ * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
+ * Receive buffer not empty (RXNE)
+ * Transmit buffer empty (TXE)
+ * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Disable Buffer interrupts.
+ * @note Any of these Buffer events will generate interrupt :
+ * Receive buffer not empty (RXNE)
+ * Transmit buffer empty (TXE)
+ * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Check if Buffer interrupts are enabled or disabled.
+ * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
+}
+
+/**
+ * @brief Enable Error interrupts.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Bus Error detection (BERR)
+ * Arbitration Loss (ARLO)
+ * Acknowledge Failure(AF)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (SMBALERT)
+ * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
+}
+
+/**
+ * @brief Disable Error interrupts.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Bus Error detection (BERR)
+ * Arbitration Loss (ARLO)
+ * Acknowledge Failure(AF)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (SMBALERT)
+ * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
+}
+
+/**
+ * @brief Check if Error interrupts are enabled or disabled.
+ * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of Transmit data register empty flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
+}
+
+/**
+ * @brief Indicate the status of Byte Transfer Finished flag.
+ * RESET: When Data byte transfer not done.
+ * SET: When Data byte transfer succeeded.
+ * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
+}
+
+/**
+ * @brief Indicate the status of Receive data register not empty flag.
+ * @note RESET: When Receive data register is read.
+ * SET: When the received data is copied in Receive data register.
+ * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
+}
+
+/**
+ * @brief Indicate the status of Start Bit (master mode).
+ * @note RESET: When No Start condition.
+ * SET: When Start condition is generated.
+ * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
+}
+
+/**
+ * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
+ * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
+}
+
+/**
+ * @brief Indicate the status of 10-bit header sent (master mode).
+ * @note RESET: When no ADD10 event occured.
+ * SET: When the master has sent the first address byte (header).
+ * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
+}
+
+/**
+ * @brief Indicate the status of Acknowledge failure flag.
+ * @note RESET: No acknowledge failure.
+ * SET: When an acknowledge failure is received after a byte transmission.
+ * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
+}
+
+/**
+ * @brief Indicate the status of Stop detection flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When a Stop condition is detected.
+ * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
+}
+
+/**
+ * @brief Indicate the status of Bus error flag.
+ * @note RESET: Clear default value.
+ * SET: When a misplaced Start or Stop condition is detected.
+ * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
+}
+
+/**
+ * @brief Indicate the status of Arbitration lost flag.
+ * @note RESET: Clear default value.
+ * SET: When arbitration lost.
+ * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
+}
+
+/**
+ * @brief Indicate the status of Overrun/Underrun flag.
+ * @note RESET: Clear default value.
+ * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+ * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
+}
+
+/**
+ * @brief Indicate the status of SMBus PEC error flag in reception.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
+}
+
+/**
+ * @brief Indicate the status of SMBus Timeout detection flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
+}
+
+/**
+ * @brief Indicate the status of SMBus alert flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
+}
+
+/**
+ * @brief Indicate the status of Bus Busy flag.
+ * @note RESET: Clear default value.
+ * SET: When a Start condition is detected.
+ * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
+}
+
+/**
+ * @brief Indicate the status of Dual flag.
+ * @note RESET: Received address matched with OAR1.
+ * SET: Received address matched with OAR2.
+ * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
+}
+
+/**
+ * @brief Indicate the status of SMBus Host address reception (Slave mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: No SMBus Host address
+ * SET: SMBus Host address received.
+ * @note This status is cleared by hardware after a STOP condition or repeated START condition.
+ * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
+}
+
+/**
+ * @brief Indicate the status of SMBus Device default address reception (Slave mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: No SMBus Device default address
+ * SET: SMBus Device default address received.
+ * @note This status is cleared by hardware after a STOP condition or repeated START condition.
+ * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
+}
+
+/**
+ * @brief Indicate the status of General call address reception (Slave mode).
+ * @note RESET: No Generall call address
+ * SET: General call address received.
+ * @note This status is cleared by hardware after a STOP condition or repeated START condition.
+ * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
+}
+
+/**
+ * @brief Indicate the status of Master/Slave flag.
+ * @note RESET: Slave Mode.
+ * SET: Master Mode.
+ * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
+}
+
+/**
+ * @brief Clear Address Matched flag.
+ * @note Clearing this flag is done by a read access to the I2Cx_SR1
+ * register followed by a read access to the I2Cx_SR2 register.
+ * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = I2Cx->SR1;
+ (void) tmpreg;
+ tmpreg = I2Cx->SR2;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear Acknowledge failure flag.
+ * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
+}
+
+/**
+ * @brief Clear Stop detection flag.
+ * @note Clearing this flag is done by a read access to the I2Cx_SR1
+ * register followed by a write access to I2Cx_CR1 register.
+ * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
+ * CR1 PE LL_I2C_ClearFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = I2Cx->SR1;
+ (void) tmpreg;
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Clear Bus error flag.
+ * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
+}
+
+/**
+ * @brief Clear Arbitration lost flag.
+ * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
+}
+
+/**
+ * @brief Clear Overrun/Underrun flag.
+ * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
+}
+
+/**
+ * @brief Clear SMBus PEC error flag.
+ * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
+}
+
+/**
+ * @brief Clear SMBus Timeout detection flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
+}
+
+/**
+ * @brief Clear SMBus Alert flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Reset of I2C peripheral.
+ * @rmtoll CR1 SWRST LL_I2C_EnableReset
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+}
+
+/**
+ * @brief Disable Reset of I2C peripheral.
+ * @rmtoll CR1 SWRST LL_I2C_DisableReset
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+}
+
+/**
+ * @brief Check if the I2C peripheral is under reset state or not.
+ * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
+}
+
+/**
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ * @note Usage in Slave or Master mode.
+ * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
+ * @param I2Cx I2C Instance.
+ * @param TypeAcknowledge This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ACK
+ * @arg @ref LL_I2C_NACK
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
+}
+
+/**
+ * @brief Generate a START or RESTART condition
+ * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
+ * This action has no effect when RELOAD is set.
+ * @rmtoll CR1 START LL_I2C_GenerateStartCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_START);
+}
+
+/**
+ * @brief Generate a STOP condition after the current byte transfer (master mode).
+ * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
+}
+
+/**
+ * @brief Enable bit POS (master/host mode).
+ * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
+ * @rmtoll CR1 POS LL_I2C_EnableBitPOS
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_POS);
+}
+
+/**
+ * @brief Disable bit POS (master/host mode).
+ * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
+ * @rmtoll CR1 POS LL_I2C_DisableBitPOS
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
+}
+
+/**
+ * @brief Check if bit POS is enabled or disabled.
+ * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
+}
+
+/**
+ * @brief Indicate the value of transfer direction.
+ * @note RESET: Bus is in read transfer (peripheral point of view).
+ * SET: Bus is in write transfer (peripheral point of view).
+ * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_DIRECTION_WRITE
+ * @arg @ref LL_I2C_DIRECTION_READ
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
+}
+
+/**
+ * @brief Enable DMA last transfer.
+ * @note This action mean that next DMA EOT is the last transfer.
+ * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
+}
+
+/**
+ * @brief Disable DMA last transfer.
+ * @note This action mean that next DMA EOT is not the last transfer.
+ * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
+}
+
+/**
+ * @brief Check if DMA last transfer is enabled or disabled.
+ * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
+}
+
+/**
+ * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
+ * or by a START or STOP condition, it is also cleared by software.
+ * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
+}
+
+/**
+ * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
+}
+
+/**
+ * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
+}
+
+/**
+ * @brief Get the SMBus Packet Error byte calculated.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
+}
+
+/**
+ * @brief Read Receive Data register.
+ * @rmtoll DR DR LL_I2C_ReceiveData8
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+ return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
+}
+
+/**
+ * @brief Write in Transmit Data Register .
+ * @rmtoll DR DR LL_I2C_TransmitData8
+ * @param I2Cx I2C Instance.
+ * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+ MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_iwdg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_iwdg.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,327 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_iwdg.h
+ * @author MCD Application Team
+ * @brief Header file of IWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_IWDG_H
+#define __STM32F4xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
+#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_IWDG_ReadReg function
+ * @{
+ */
+#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
+ * @{
+ */
+#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
+#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
+#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
+#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
+#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
+#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
+#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Start the Independent Watchdog
+ * @note Except if the hardware watchdog option is selected
+ * @rmtoll KR KEY LL_IWDG_Enable
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * @rmtoll KR KEY LL_IWDG_ReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+ * @brief Select the prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_SetPrescaler
+ * @param IWDGx IWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
+{
+ WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+ * @brief Get the selected prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_GetPrescaler
+ * @param IWDGx IWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->PR));
+}
+
+/**
+ * @brief Specify the IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_SetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
+{
+ WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+ * @brief Get the specified IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_GetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->RLR));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if flag Prescaler Value Update is set or not
+ * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+}
+
+/**
+ * @brief Check if flag Reload Value Update is set or not
+ * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+}
+
+
+/**
+ * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
+ * @rmtoll SR PVU LL_IWDG_IsReady\n
+ * SR RVU LL_IWDG_IsReady
+ * @param IWDGx IWDG Instance
+ * @retval State of bits (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* IWDG) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,210 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_lptim.c
+ * @author MCD Application Team
+ * @brief LPTIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_lptim.h"
+#include "stm32f4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (LPTIM1) || defined (LPTIM2)
+
+/** @addtogroup LPTIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Private_Macros
+ * @{
+ */
+#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
+ || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup LPTIM_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set LPTIMx registers to their reset values.
+ * @param LPTIMx LP Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx registers are de-initialized
+ * - ERROR: invalid LPTIMx instance
+ */
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+
+ if (LPTIMx == LPTIM1)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
+ }
+#if defined(LPTIM2)
+ else if (LPTIMx == LPTIM2)
+ {
+ LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
+ LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
+ }
+#endif
+ else
+ {
+ result = ERROR;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set each fields of the LPTIM_InitStruct structure to its default
+ * value.
+ * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+ * @retval None
+ */
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+{
+ /* Set the default configuration */
+ LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
+ LPTIM_InitStruct->Prescaler = LL_LPTIM_PRESCALER_DIV1;
+ LPTIM_InitStruct->Waveform = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
+ LPTIM_InitStruct->Polarity = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
+}
+
+/**
+ * @brief Configure the LPTIMx peripheral according to the specified parameters.
+ * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
+ * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
+ * @param LPTIMx LP Timer Instance
+ * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx instance has been initialized
+ * - ERROR: LPTIMx instance hasn't been initialized
+ */
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
+ (ENABLE bit is reset to 0).
+ */
+ if (LL_LPTIM_IsEnabled(LPTIMx))
+ {
+ result = ERROR;
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+ assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+ assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+ assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+
+ /* Set CKSEL bitfield according to ClockSource value */
+ /* Set PRESC bitfield according to Prescaler value */
+ /* Set WAVE bitfield according to Waveform value */
+ /* Set WAVEPOL bitfield according to Polarity value */
+ MODIFY_REG(LPTIMx->CFGR,
+ (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL),
+ LPTIM_InitStruct->ClockSource | \
+ LPTIM_InitStruct->Prescaler | \
+ LPTIM_InitStruct->Waveform | \
+ LPTIM_InitStruct->Polarity);
+ }
+
+ return result;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (LPTIM1) || defined (LPTIM2) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1375 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_lptim.h
+ * @author MCD Application Team
+ * @brief Header file of LPTIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_LPTIM_H
+#define __STM32F4xx_LL_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+#if defined (LPTIM1)
+
+/** @defgroup LPTIM_LL LPTIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief LPTIM Init structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
+ This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
+
+ This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
+
+ uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
+ This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
+
+ This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
+
+ uint32_t Waveform; /*!< Specifies the waveform shape.
+ This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
+
+ This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+
+ uint32_t Polarity; /*!< Specifies waveform polarity.
+ This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+} LL_LPTIM_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
+ * @{
+ */
+#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
+#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
+#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
+#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
+#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
+#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
+#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
+ * @{
+ */
+#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
+#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
+#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
+#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
+#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
+#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
+#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
+ * @{
+ */
+#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
+#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
+ * @{
+ */
+#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
+#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
+ * @{
+ */
+#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
+#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
+ * @{
+ */
+#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
+#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
+ * @{
+ */
+#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
+ * @{
+ */
+#define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
+#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
+#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
+#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
+#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
+#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
+#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
+#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
+ * @{
+ */
+#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
+#define LL_LPTIM_TRIG_SOURCE_TIM1_TRGO LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to TIM1*/
+#define LL_LPTIM_TRIG_SOURCE_TIM5_TRGO (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to TIM5*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
+ * @{
+ */
+#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
+ * @{
+ */
+#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
+ * @{
+ */
+#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
+#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
+ * @{
+ */
+#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
+#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
+ * @{
+ */
+#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
+ * @{
+ */
+
+/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in LPTIM register
+ * @param __INSTANCE__ LPTIM Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in LPTIM register
+ * @param __INSTANCE__ LPTIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the LPTIM instance
+ * @note After setting the ENABLE bit, a delay of two counter clock is needed
+ * before the LPTIM instance is actually enabled.
+ * @rmtoll CR ENABLE LL_LPTIM_Enable
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+ * @brief Disable the LPTIM instance
+ * @rmtoll CR ENABLE LL_LPTIM_Disable
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+ * @brief Indicates whether the LPTIM instance is enabled.
+ * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
+}
+
+/**
+ * @brief Starts the LPTIM counter in the desired mode.
+ * @note LPTIM instance must be enabled before starting the counter.
+ * @note It is possible to change on the fly from One Shot mode to
+ * Continuous mode.
+ * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
+ * CR SNGSTRT LL_LPTIM_StartCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @param OperatingMode This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
+ * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
+{
+ MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
+}
+
+
+/**
+ * @brief Set the LPTIM registers update mode (enable/disable register preload)
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param UpdateMode This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
+}
+
+/**
+ * @brief Get the LPTIM registers update mode
+ * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
+}
+
+/**
+ * @brief Set the auto reload value
+ * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
+ * @note After a write to the LPTIMx_ARR register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the ARROK flag be set, will
+ * lead to unpredictable results.
+ * @note autoreload value be strictly greater than the compare value.
+ * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
+{
+ MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
+}
+
+/**
+ * @brief Get actual auto reload value
+ * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
+}
+
+/**
+ * @brief Set the compare value
+ * @note After a write to the LPTIMx_CMP register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the CMPOK flag be set, will
+ * lead to unpredictable results.
+ * @rmtoll CMP CMP LL_LPTIM_SetCompare
+ * @param LPTIMx Low-Power Timer instance
+ * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
+{
+ MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value
+ * @rmtoll CMP CMP LL_LPTIM_GetCompare
+ * @param LPTIMx Low-Power Timer instance
+ * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
+}
+
+/**
+ * @brief Get actual counter value
+ * @note When the LPTIM instance is running with an asynchronous clock, reading
+ * the LPTIMx_CNT register may return unreliable values. So in this case
+ * it is necessary to perform two consecutive read accesses and verify
+ * that the two returned values are identical.
+ * @rmtoll CNT CNT LL_LPTIM_GetCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Counter value
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
+}
+
+/**
+ * @brief Set the counter mode (selection of the LPTIM counter clock source).
+ * @note The counter mode can be set only when the LPTIM instance is disabled.
+ * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
+}
+
+/**
+ * @brief Get the counter mode
+ * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
+}
+
+/**
+ * @brief Configure the LPTIM instance output (LPTIMx_OUT)
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note Regarding the LPTIM output polarity the change takes effect
+ * immediately, so the output default value will change immediately after
+ * the polarity is re-configured, even before the timer is enabled.
+ * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
+ * CFGR WAVPOL LL_LPTIM_ConfigOutput
+ * @param LPTIMx Low-Power Timer instance
+ * @param Waveform This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
+}
+
+/**
+ * @brief Set waveform shape
+ * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @param Waveform This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
+}
+
+/**
+ * @brief Get actual waveform shape
+ * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
+}
+
+/**
+ * @brief Set output polarity
+ * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
+}
+
+/**
+ * @brief Get actual output polarity
+ * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
+}
+
+/**
+ * @brief Set actual prescaler division ratio.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When the LPTIM is configured to be clocked by an internal clock source
+ * and the LPTIM counter is configured to be updated by active edges
+ * detected on the LPTIM external Input1, the internal clock provided to
+ * the LPTIM must be not be prescaled.
+ * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_PRESCALER_DIV1
+ * @arg @ref LL_LPTIM_PRESCALER_DIV2
+ * @arg @ref LL_LPTIM_PRESCALER_DIV4
+ * @arg @ref LL_LPTIM_PRESCALER_DIV8
+ * @arg @ref LL_LPTIM_PRESCALER_DIV16
+ * @arg @ref LL_LPTIM_PRESCALER_DIV32
+ * @arg @ref LL_LPTIM_PRESCALER_DIV64
+ * @arg @ref LL_LPTIM_PRESCALER_DIV128
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
+}
+
+/**
+ * @brief Get actual prescaler division ratio.
+ * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_PRESCALER_DIV1
+ * @arg @ref LL_LPTIM_PRESCALER_DIV2
+ * @arg @ref LL_LPTIM_PRESCALER_DIV4
+ * @arg @ref LL_LPTIM_PRESCALER_DIV8
+ * @arg @ref LL_LPTIM_PRESCALER_DIV16
+ * @arg @ref LL_LPTIM_PRESCALER_DIV32
+ * @arg @ref LL_LPTIM_PRESCALER_DIV64
+ * @arg @ref LL_LPTIM_PRESCALER_DIV128
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note The first trigger event will start the timer, any successive trigger
+ * event will reset the counter and the timer will restart.
+ * @note The timeout value corresponds to the compare value; if no trigger
+ * occurs within the expected time frame, the MCU is waked-up by the
+ * compare match event.
+ * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+ * @brief Disable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note A trigger event arriving when the timer is already started will be
+ * ignored.
+ * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+ * @brief Indicate whether the timeout function is enabled.
+ * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
+}
+
+/**
+ * @brief Start the LPTIM counter
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
+}
+
+/**
+ * @brief Configure the external trigger used as a trigger event for the LPTIM.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note An internal clock source must be present when a digital filter is
+ * required for the trigger.
+ * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
+ * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
+ * CFGR TRIGEN LL_LPTIM_ConfigTrigger
+ * @param LPTIMx Low-Power Timer instance
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM1_TRGO
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM5_TRGO
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LL_LPTIM_TRIG_FILTER_2
+ * @arg @ref LL_LPTIM_TRIG_FILTER_4
+ * @arg @ref LL_LPTIM_TRIG_FILTER_8
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
+}
+
+/**
+ * @brief Get actual external trigger source.
+ * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM1_TRGO
+ * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM5_TRGO
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
+}
+
+/**
+ * @brief Get actual external trigger filter.
+ * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LL_LPTIM_TRIG_FILTER_2
+ * @arg @ref LL_LPTIM_TRIG_FILTER_4
+ * @arg @ref LL_LPTIM_TRIG_FILTER_8
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
+}
+
+/**
+ * @brief Get actual external trigger polarity.
+ * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
+ * @{
+ */
+
+/**
+ * @brief Set the source of the clock used by the LPTIM instance.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
+}
+
+/**
+ * @brief Get actual LPTIM instance clock source.
+ * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
+}
+
+/**
+ * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When both external clock signal edges are considered active ones,
+ * the LPTIM must also be clocked by an internal clock source with a
+ * frequency equal to at least four times the external clock frequency.
+ * @note An internal clock source must be present when a digital filter is
+ * required for external clock.
+ * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
+ * CFGR CKPOL LL_LPTIM_ConfigClock
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockFilter This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_FILTER_NONE
+ * @arg @ref LL_LPTIM_CLK_FILTER_2
+ * @arg @ref LL_LPTIM_CLK_FILTER_4
+ * @arg @ref LL_LPTIM_CLK_FILTER_8
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
+}
+
+/**
+ * @brief Get actual clock polarity
+ * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+ * @brief Get actual clock digital filter
+ * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_CLK_FILTER_NONE
+ * @arg @ref LL_LPTIM_CLK_FILTER_2
+ * @arg @ref LL_LPTIM_CLK_FILTER_4
+ * @arg @ref LL_LPTIM_CLK_FILTER_8
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
+ * @{
+ */
+
+/**
+ * @brief Configure the encoder mode.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
+}
+
+/**
+ * @brief Get actual encoder mode.
+ * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+ * @brief Enable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note In this mode the LPTIM instance must be clocked by an internal clock
+ * source. Also, the prescaler division ratio must be equal to 1.
+ * @note LPTIM instance must be configured in continuous mode prior enabling
+ * the encoder mode.
+ * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+ * @brief Disable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+ * @brief Indicates whether the LPTIM operates in encoder mode.
+ * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear the compare match flag (CMPMCF)
+ * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
+}
+
+/**
+ * @brief Inform application whether a compare match interrupt has occurred.
+ * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
+}
+
+/**
+ * @brief Clear the autoreload match flag (ARRMCF)
+ * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
+}
+
+/**
+ * @brief Inform application whether a autoreload match interrupt has occured.
+ * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
+}
+
+/**
+ * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
+ * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
+}
+
+/**
+ * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
+ * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
+}
+
+/**
+ * @brief Clear the compare register update interrupt flag (CMPOKCF).
+ * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
+ * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
+}
+
+/**
+ * @brief Clear the autoreload register update interrupt flag (ARROKCF).
+ * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
+ * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
+}
+
+/**
+ * @brief Clear the counter direction change to up interrupt flag (UPCF).
+ * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+ * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
+}
+
+/**
+ * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
+ * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+ * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable compare match interrupt (CMPMIE).
+ * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
+}
+
+/**
+ * @brief Disable compare match interrupt (CMPMIE).
+ * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
+}
+
+/**
+ * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
+ * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
+}
+
+/**
+ * @brief Enable autoreload match interrupt (ARRMIE).
+ * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
+}
+
+/**
+ * @brief Disable autoreload match interrupt (ARRMIE).
+ * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
+ * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
+}
+
+/**
+ * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
+}
+
+/**
+ * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
+}
+
+/**
+ * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
+ * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
+}
+
+/**
+ * @brief Enable compare register write completed interrupt (CMPOKIE).
+ * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
+}
+
+/**
+ * @brief Disable compare register write completed interrupt (CMPOKIE).
+ * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
+}
+
+/**
+ * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
+ * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
+}
+
+/**
+ * @brief Enable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
+}
+
+/**
+ * @brief Disable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
+ * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
+}
+
+/**
+ * @brief Enable direction change to up interrupt (UPIE).
+ * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
+}
+
+/**
+ * @brief Disable direction change to up interrupt (UPIE).
+ * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
+ * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
+}
+
+/**
+ * @brief Enable direction change to down interrupt (DOWNIE).
+ * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
+}
+
+/**
+ * @brief Disable direction change to down interrupt (DOWNIE).
+ * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
+ * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+ return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* LPTIM1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_LPTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,101 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_pwr.c
+ * @author MCD Application Team
+ * @brief PWR LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_pwr.h"
+#include "stm32f4xx_ll_bus.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PWR_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the PWR registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PWR registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_PWR_DeInit(void)
+{
+ /* Force reset of PWR clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ /* Release reset of PWR clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(PWR) */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1005 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_PWR_H
+#define __STM32F4xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_WriteReg function
+ * @{
+ */
+#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
+#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_ReadReg function
+ * @{
+ */
+#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
+#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
+#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
+#define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */
+#if defined(PWR_CSR_EWUP)
+#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */
+#elif defined(PWR_CSR_EWUP1)
+#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
+#endif /* PWR_CSR_EWUP */
+#if defined(PWR_CSR_EWUP2)
+#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
+#endif /* PWR_CSR_EWUP2 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
+#endif /* PWR_CSR_EWUP3 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
+ * @{
+ */
+#if defined(PWR_CR_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1)
+#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
+#else
+#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS)
+#define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U
+#endif /* PWR_CR_VOS_0 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+ * @{
+ */
+#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
+#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
+#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
+#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
+#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
+#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
+#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
+#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
+ * @{
+ */
+#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+ * @{
+ */
+#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
+#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
+#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
+#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
+#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
+#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
+#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
+/**
+ * @}
+ */
+/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
+ * @{
+ */
+#if defined(PWR_CSR_EWUP)
+#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */
+#endif /* PWR_CSR_EWUP */
+#if defined(PWR_CSR_EWUP1)
+#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
+#endif /* PWR_CSR_EWUP1 */
+#if defined(PWR_CSR_EWUP2)
+#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */
+#endif /* PWR_CSR_EWUP2 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */
+#endif /* PWR_CSR_EWUP3 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in PWR register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in PWR register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+ * @{
+ */
+#if defined(PWR_CR_FISSR)
+/**
+ * @brief Enable FLASH interface STOP while system Run is ON
+ * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP
+ * @note This mode is enabled only with STOP low power mode.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_FISSR);
+}
+
+/**
+ * @brief Disable FLASH Interface STOP while system Run is ON
+ * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
+}
+
+/**
+ * @brief Check if FLASH Interface STOP while system Run feature is enabled
+ * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
+}
+#endif /* PWR_CR_FISSR */
+
+#if defined(PWR_CR_FMSSR)
+/**
+ * @brief Enable FLASH Memory STOP while system Run is ON
+ * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP
+ * @note This mode is enabled only with STOP low power mode.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_FMSSR);
+}
+
+/**
+ * @brief Disable FLASH Memory STOP while system Run is ON
+ * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
+}
+
+/**
+ * @brief Check if FLASH Memory STOP while system Run feature is enabled
+ * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
+}
+#endif /* PWR_CR_FMSSR */
+#if defined(PWR_CR_UDEN)
+/**
+ * @brief Enable Under Drive Mode
+ * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode
+ * @note This mode is enabled only with STOP low power mode.
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
+ * mode is only available when the main Regulator or the low power Regulator
+ * is in low voltage mode.
+ * @note If the Under-drive mode was enabled, it is automatically disabled after
+ * exiting Stop mode.
+ * When the voltage Regulator operates in Under-drive mode, an additional
+ * startup delay is induced when waking up from Stop mode.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_UDEN);
+}
+
+/**
+ * @brief Disable Under Drive Mode
+ * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
+}
+
+/**
+ * @brief Check if Under Drive Mode is enabled
+ * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
+}
+#endif /* PWR_CR_UDEN */
+
+#if defined(PWR_CR_ODSWEN)
+/**
+ * @brief Enable Over drive switching
+ * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_ODSWEN);
+}
+
+/**
+ * @brief Disable Over drive switching
+ * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
+}
+
+/**
+ * @brief Check if Over drive switching is enabled
+ * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
+}
+#endif /* PWR_CR_ODSWEN */
+#if defined(PWR_CR_ODEN)
+/**
+ * @brief Enable Over drive Mode
+ * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_ODEN);
+}
+
+/**
+ * @brief Disable Over drive Mode
+ * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
+}
+
+/**
+ * @brief Check if Over drive switching is enabled
+ * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
+}
+#endif /* PWR_CR_ODEN */
+#if defined(PWR_CR_MRUDS)
+/**
+ * @brief Enable Main Regulator in deepsleep under-drive Mode
+ * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_MRUDS);
+}
+
+/**
+ * @brief Disable Main Regulator in deepsleep under-drive Mode
+ * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
+}
+
+/**
+ * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled
+ * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
+}
+#endif /* PWR_CR_MRUDS */
+
+#if defined(PWR_CR_LPUDS)
+/**
+ * @brief Enable Low Power Regulator in deepsleep under-drive Mode
+ * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_LPUDS);
+}
+
+/**
+ * @brief Disable Low Power Regulator in deepsleep under-drive Mode
+ * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
+}
+
+/**
+ * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled
+ * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
+}
+#endif /* PWR_CR_LPUDS */
+
+#if defined(PWR_CR_MRLVDS)
+/**
+ * @brief Enable Main Regulator low voltage Mode
+ * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_MRLVDS);
+}
+
+/**
+ * @brief Disable Main Regulator low voltage Mode
+ * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
+}
+
+/**
+ * @brief Check if Main Regulator low voltage Mode is enabled
+ * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
+}
+#endif /* PWR_CR_MRLVDS */
+
+#if defined(PWR_CR_LPLVDS)
+/**
+ * @brief Enable Low Power Regulator low voltage Mode
+ * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_LPLVDS);
+}
+
+/**
+ * @brief Disable Low Power Regulator low voltage Mode
+ * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
+}
+
+/**
+ * @brief Check if Low Power Regulator low voltage Mode is enabled
+ * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
+}
+#endif /* PWR_CR_LPLVDS */
+/**
+ * @brief Set the main internal Regulator output voltage
+ * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
+ * @param VoltageScaling This parameter can be one of the following values:
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+ * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
+}
+
+/**
+ * @brief Get the main internal Regulator output voltage
+ * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+ * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
+}
+/**
+ * @brief Enable the Flash Power Down in Stop Mode
+ * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_FPDS);
+}
+
+/**
+ * @brief Disable the Flash Power Down in Stop Mode
+ * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
+}
+
+/**
+ * @brief Check if the Flash Power Down in Stop Mode is enabled
+ * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
+}
+
+/**
+ * @brief Enable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Disable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Check if the backup domain is enabled
+ * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
+}
+/**
+ * @brief Enable the backup Regulator
+ * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
+ * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
+ * The LL_PWR_EnableBkUpAccess() must be called before using this API.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
+{
+ SET_BIT(PWR->CSR, PWR_CSR_BRE);
+}
+
+/**
+ * @brief Disable the backup Regulator
+ * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
+ * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
+ * The LL_PWR_EnableBkUpAccess() must be called before using this API.
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
+{
+ CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
+}
+
+/**
+ * @brief Check if the backup Regulator is enabled
+ * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
+}
+
+/**
+ * @brief Set voltage Regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
+ * @param RegulMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
+}
+
+/**
+ * @brief Get voltage Regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
+}
+
+/**
+ * @brief Set Power Down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_SetPowerMode
+ * @param PDMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
+ *
+ * (*) not available on all devices
+ * @arg @ref LL_PWR_MODE_STANDBY
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
+{
+#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
+#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
+#else
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
+#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
+}
+
+/**
+ * @brief Get Power Down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_GetPowerMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
+ *
+ * (*) not available on all devices
+ * @arg @ref LL_PWR_MODE_STANDBY
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
+ return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
+#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
+ return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
+#else
+ return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
+#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
+}
+
+/**
+ * @brief Configure the voltage threshold detected by the Power Voltage Detector
+ * @rmtoll CR PLS LL_PWR_SetPVDLevel
+ * @param PVDLevel This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
+}
+
+/**
+ * @brief Get the voltage threshold detection
+ * @rmtoll CR PLS LL_PWR_GetPVDLevel
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
+}
+
+/**
+ * @brief Enable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_EnablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Disable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_DisablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Check if Power Voltage Detector is enabled
+ * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
+}
+
+/**
+ * @brief Enable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n
+ * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
+ * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
+ * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+ *
+ * (*) not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+ SET_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Disable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n
+ * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
+ * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
+ * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+ *
+ * (*) not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+ CLEAR_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Check if the WakeUp PINx functionality is enabled
+ * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n
+ * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
+ * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
+ * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+ *
+ * (*) not available on all devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+ return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Wake-up Flag
+ * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
+}
+
+/**
+ * @brief Get Standby Flag
+ * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
+}
+
+/**
+ * @brief Get Backup Regulator ready Flag
+ * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
+}
+/**
+ * @brief Indicate whether VDD voltage is below the selected PVD threshold
+ * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
+}
+
+/**
+ * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
+ * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+ return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
+}
+#if defined(PWR_CR_ODEN)
+/**
+ * @brief Indicate whether the Over-Drive mode is ready or not
+ * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
+}
+#endif /* PWR_CR_ODEN */
+
+#if defined(PWR_CR_ODSWEN)
+/**
+ * @brief Indicate whether the Over-Drive mode switching is ready or not
+ * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
+}
+#endif /* PWR_CR_ODSWEN */
+
+#if defined(PWR_CR_UDEN)
+/**
+ * @brief Indicate whether the Under-Drive mode is ready or not
+ * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
+}
+#endif /* PWR_CR_UDEN */
+/**
+ * @brief Clear Standby Flag
+ * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CSBF);
+}
+
+/**
+ * @brief Clear Wake-up Flags
+ * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CWUF);
+}
+#if defined(PWR_CSR_UDRDY)
+/**
+ * @brief Clear Under-Drive ready Flag
+ * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
+{
+ WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
+}
+#endif /* PWR_CSR_UDRDY */
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PWR) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1677 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_rcc.c
+ * @author MCD Application Team
+ * @brief RCC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @addtogroup RCC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+ * @{
+ */
+#if defined(FMPI2C1)
+#define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+#if defined(RCC_DCKCFGR_SAI1SRC)
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
+#elif defined(RCC_DCKCFGR_SAI1ASRC)
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))
+#endif /* RCC_DCKCFGR_SAI1SRC */
+#endif /* SAI1 */
+
+#if defined(SDIO)
+#define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))
+#endif /* SDIO */
+
+#if defined(RNG)
+#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+#endif /* USB_OTG_FS || USB_OTG_HS */
+
+#if defined(DFSDM2_Channel0)
+#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
+
+#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))
+#elif defined(DFSDM1_Channel0)
+#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
+
+#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
+#endif /* DFSDM2_Channel0 */
+
+#if defined(RCC_DCKCFGR_I2S2SRC)
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
+#else
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
+#endif /* RCC_DCKCFGR_I2S2SRC */
+
+#if defined(CEC)
+#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
+#endif /* CEC */
+
+#if defined(DSI)
+#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
+#endif /* DSI */
+
+#if defined(LTDC)
+#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
+#endif /* LTDC */
+
+#if defined(SPDIFRX)
+#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
+#endif /* SPDIFRX */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+ * @{
+ */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
+uint32_t RCC_PLL_GetFreqDomain_48M(void);
+#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
+uint32_t RCC_PLL_GetFreqDomain_I2S(void);
+#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
+#if defined(SPDIFRX)
+uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);
+#endif /* SPDIFRX */
+#if defined(RCC_PLLCFGR_PLLR)
+#if defined(SAI1)
+uint32_t RCC_PLL_GetFreqDomain_SAI(void);
+#endif /* SAI1 */
+#endif /* RCC_PLLCFGR_PLLR */
+#if defined(DSI)
+uint32_t RCC_PLL_GetFreqDomain_DSI(void);
+#endif /* DSI */
+#if defined(RCC_PLLSAI_SUPPORT)
+uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+#if defined(LTDC)
+uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
+#endif /* LTDC */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2S_SUPPORT)
+uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+uint32_t RCC_PLLI2S_GetFreqDomain_48M(void);
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+#if defined(SAI1)
+uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
+#endif /* SAI1 */
+#if defined(SPDIFRX)
+uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
+#endif /* SPDIFRX */
+#endif /* RCC_PLLI2S_SUPPORT */
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RCC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RCC_DeInit(void)
+{
+ uint32_t vl_mask = 0U;
+
+ /* Set HSION bit */
+ LL_RCC_HSI_Enable();
+
+ /* Wait for HSI READY bit */
+ while(LL_RCC_HSI_IsReady() != 1U)
+ {}
+
+ /* Reset CFGR register */
+ LL_RCC_WriteReg(CFGR, 0x00000000U);
+
+ vl_mask = 0xFFFFFFFFU;
+
+ /* Reset HSEON, PLLSYSON bits */
+ CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
+
+#if defined(RCC_PLLSAI_SUPPORT)
+ /* Reset PLLSAION bit */
+ CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
+#endif /* RCC_PLLSAI_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+ /* Reset PLLI2SON bit */
+ CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
+#endif /* RCC_PLLI2S_SUPPORT */
+
+ /* Write new mask in CR register */
+ LL_RCC_WriteReg(CR, vl_mask);
+
+ /* Set HSITRIM bits to the reset value*/
+ LL_RCC_HSI_SetCalibTrimming(0x10U);
+
+ /* Wait for PLL READY bit to be reset */
+ while(LL_RCC_PLL_IsReady() != 0U)
+ {}
+
+ /* Reset PLLCFGR register */
+ LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
+
+#if defined(RCC_PLLI2S_SUPPORT)
+ /* Reset PLLI2SCFGR register */
+ LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+ /* Reset PLLSAICFGR register */
+ LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
+#endif /* RCC_PLLSAI_SUPPORT */
+
+ /* Disable all interrupts */
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
+
+#if defined(RCC_CIR_PLLI2SRDYIE)
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+#endif /* RCC_CIR_PLLI2SRDYIE */
+
+#if defined(RCC_CIR_PLLSAIRDYIE)
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+#endif /* RCC_CIR_PLLSAIRDYIE */
+
+ /* Clear all interrupt flags */
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
+
+#if defined(RCC_CIR_PLLI2SRDYC)
+ SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+#endif /* RCC_CIR_PLLI2SRDYC */
+
+#if defined(RCC_CIR_PLLSAIRDYC)
+ SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+#endif /* RCC_CIR_PLLSAIRDYC */
+
+ /* Clear LSION bit */
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+ /* Reset all CSR flags */
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * and different peripheral clocks available on the device.
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
+ * or HSI_VALUE(**) multiplied/divided by the PLL factors.
+ * @note (**) HSI_VALUE is a constant defined in this file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (***) HSE_VALUE is a constant defined in this file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ * @note The result of this function could be incorrect when using fractional
+ * value for HSE crystal.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ * @{
+ */
+
+/**
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ * must be called to update structure fields. Otherwise, any
+ * configuration based on this function will be incorrect.
+ * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+ * @retval None
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+ /* Get SYSCLK frequency */
+ RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+#if defined(FMPI2C1)
+/**
+ * @brief Return FMPI2Cx clock frequency
+ * @param FMPI2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
+ * @retval FMPI2C clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+ */
+uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)
+{
+ uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));
+
+ if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)
+ {
+ /* FMPI2C1 CLK clock frequency */
+ switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))
+ {
+ case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */
+ FMPI2C_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ FMPI2C_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */
+ default:
+ FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+
+ return FMPI2C_frequency;
+}
+#endif /* FMPI2C1 */
+
+/**
+ * @brief Return I2Sx clock frequency
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval I2S clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ */
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
+{
+ uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
+
+ if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
+ {
+ /* I2S1 CLK clock frequency */
+ switch (LL_RCC_GetI2SClockSource(I2SxSource))
+ {
+#if defined(RCC_PLLI2S_SUPPORT)
+ case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
+ if (LL_RCC_PLLI2S_IsReady())
+ {
+ i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
+ }
+ break;
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
+ case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */
+ if (LL_RCC_PLL_IsReady())
+ {
+ i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
+ }
+ break;
+
+ case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */
+ switch (LL_RCC_PLL_GetMainSource())
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */
+ if (LL_RCC_HSE_IsReady())
+ {
+ i2s_frequency = HSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ i2s_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ break;
+#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
+
+ case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
+ default:
+ i2s_frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ }
+#if defined(RCC_DCKCFGR_I2S2SRC)
+ else
+ {
+ /* I2S2 CLK clock frequency */
+ switch (LL_RCC_GetI2SClockSource(I2SxSource))
+ {
+ case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */
+ if (LL_RCC_PLLI2S_IsReady())
+ {
+ i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
+ }
+ break;
+
+ case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
+ if (LL_RCC_PLL_IsReady())
+ {
+ i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
+ }
+ break;
+
+ case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */
+ switch (LL_RCC_PLL_GetMainSource())
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */
+ if (LL_RCC_HSE_IsReady())
+ {
+ i2s_frequency = HSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ i2s_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ break;
+
+ case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
+ default:
+ i2s_frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ }
+#endif /* RCC_DCKCFGR_I2S2SRC */
+
+ return i2s_frequency;
+}
+
+#if defined(LPTIM1)
+/**
+ * @brief Return LPTIMx clock frequency
+ * @param LPTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+ * @retval LPTIM clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+{
+ uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+
+ if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
+ {
+ /* LPTIM1CLK clock frequency */
+ switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+ {
+ case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
+ if (LL_RCC_LSI_IsReady())
+ {
+ lptim_frequency = LSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ lptim_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ lptim_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
+ default:
+ lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+
+ return lptim_frequency;
+}
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/**
+ * @brief Return SAIx clock frequency
+ * @param SAIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval SAI clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ */
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
+{
+ uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
+
+#if defined(RCC_DCKCFGR_SAI1SRC)
+ if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))
+ {
+ /* SAI1CLK clock frequency */
+ switch (LL_RCC_GetSAIClockSource(SAIxSource))
+ {
+ case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
+ case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
+ if (LL_RCC_PLLSAI_IsReady())
+ {
+ sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
+ case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
+ if (LL_RCC_PLLI2S_IsReady())
+ {
+ sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
+ case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
+ switch (LL_RCC_PLL_GetMainSource())
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
+ if (LL_RCC_HSE_IsReady())
+ {
+ sai_frequency = HSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ sai_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ break;
+
+ case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
+ default:
+ sai_frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ }
+#endif /* RCC_DCKCFGR_SAI1SRC */
+#if defined(RCC_DCKCFGR_SAI1ASRC)
+ if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))
+ {
+ /* SAI1CLK clock frequency */
+ switch (LL_RCC_GetSAIClockSource(SAIxSource))
+ {
+#if defined(RCC_PLLSAI_SUPPORT)
+ case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */
+ case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */
+ if (LL_RCC_PLLSAI_IsReady())
+ {
+ sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
+ }
+ break;
+#endif /* RCC_PLLSAI_SUPPORT */
+
+ case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */
+ case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */
+ if (LL_RCC_PLLI2S_IsReady())
+ {
+ sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
+ }
+ break;
+
+#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
+ case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */
+ case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+ }
+ break;
+
+ case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:
+ case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:
+ switch (LL_RCC_PLL_GetMainSource())
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */
+ if (LL_RCC_HSE_IsReady())
+ {
+ sai_frequency = HSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ sai_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ break;
+#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
+
+ case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */
+ case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */
+ default:
+ sai_frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+ }
+#endif /* RCC_DCKCFGR_SAI1ASRC */
+
+ return sai_frequency;
+}
+#endif /* SAI1 */
+
+#if defined(SDIO)
+/**
+ * @brief Return SDIOx clock frequency
+ * @param SDIOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDIO_CLKSOURCE
+ * @retval SDIO clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ */
+uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)
+{
+ uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));
+
+ if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)
+ {
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+ /* SDIOCLK clock frequency */
+ switch (LL_RCC_GetSDIOClockSource(SDIOxSource))
+ {
+ case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */
+ switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
+ {
+ case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
+ if (LL_RCC_PLL_IsReady())
+ {
+ SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+ break;
+
+#if defined(RCC_PLLSAI_SUPPORT)
+ case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
+ default:
+ if (LL_RCC_PLLSAI_IsReady())
+ {
+ SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+ }
+ break;
+#endif /* RCC_PLLSAI_SUPPORT */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+ case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */
+ default:
+ if (LL_RCC_PLLI2S_IsReady())
+ {
+ SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();
+ }
+ break;
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+ }
+ break;
+
+ case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */
+ default:
+ SDIO_frequency = RCC_GetSystemClockFreq();
+ break;
+ }
+#else
+ /* PLL clock used as 48Mhz domain clock */
+ if (LL_RCC_PLL_IsReady())
+ {
+ SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+ }
+
+ return SDIO_frequency;
+}
+#endif /* SDIO */
+
+#if defined(RNG)
+/**
+ * @brief Return RNGx clock frequency
+ * @param RNGxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE
+ * @retval RNG clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ */
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
+{
+ uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+ /* RNGCLK clock frequency */
+ switch (LL_RCC_GetRNGClockSource(RNGxSource))
+ {
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+ case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */
+ if (LL_RCC_PLLI2S_IsReady())
+ {
+ rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();
+ }
+ break;
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+ case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
+ if (LL_RCC_PLLSAI_IsReady())
+ {
+ rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+ }
+ break;
+#endif /* RCC_PLLSAI_SUPPORT */
+
+ case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
+ default:
+ if (LL_RCC_PLL_IsReady())
+ {
+ rng_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+ break;
+ }
+#else
+ /* PLL clock used as RNG clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ rng_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+ return rng_frequency;
+}
+#endif /* RNG */
+
+#if defined(CEC)
+/**
+ * @brief Return CEC clock frequency
+ * @param CECxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE
+ * @retval CEC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
+{
+ uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
+
+ /* CECCLK clock frequency */
+ switch (LL_RCC_GetCECClockSource(CECxSource))
+ {
+ case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ cec_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ cec_frequency = HSI_VALUE/488U;
+ }
+ break;
+ }
+
+ return cec_frequency;
+}
+#endif /* CEC */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/**
+ * @brief Return USBx clock frequency
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval USB clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+ uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+ /* USBCLK clock frequency */
+ switch (LL_RCC_GetUSBClockSource(USBxSource))
+ {
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+ case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */
+ if (LL_RCC_PLLI2S_IsReady())
+ {
+ usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();
+ }
+ break;
+
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+ case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
+ if (LL_RCC_PLLSAI_IsReady())
+ {
+ usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+ }
+ break;
+#endif /* RCC_PLLSAI_SUPPORT */
+
+ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
+ default:
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+ break;
+ }
+#else
+ /* PLL clock used as USB clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+ return usb_frequency;
+}
+#endif /* USB_OTG_FS || USB_OTG_HS */
+
+#if defined(DFSDM1_Channel0)
+/**
+ * @brief Return DFSDMx clock frequency
+ * @param DFSDMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+ * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval DFSDM clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
+{
+ uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
+
+ if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)
+ {
+ /* DFSDM1CLK clock frequency */
+ switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
+ {
+ case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
+ dfsdm_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
+ default:
+ dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+#if defined(DFSDM2_Channel0)
+ else
+ {
+ /* DFSDM2CLK clock frequency */
+ switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
+ {
+ case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */
+ dfsdm_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */
+ default:
+ dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+#endif /* DFSDM2_Channel0 */
+
+ return dfsdm_frequency;
+}
+
+/**
+ * @brief Return DFSDMx Audio clock frequency
+ * @param DFSDMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+ * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval DFSDM clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ */
+uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
+{
+ uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
+
+ if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)
+ {
+ /* DFSDM1CLK clock frequency */
+ switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
+ {
+ case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */
+ dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
+ break;
+
+ case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */
+ default:
+ dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
+ break;
+ }
+ }
+#if defined(DFSDM2_Channel0)
+ else
+ {
+ /* DFSDM2CLK clock frequency */
+ switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
+ {
+ case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */
+ dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
+ break;
+
+ case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */
+ default:
+ dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
+ break;
+ }
+ }
+#endif /* DFSDM2_Channel0 */
+
+ return dfsdm_frequency;
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+/**
+ * @brief Return DSI clock frequency
+ * @param DSIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE
+ * @retval DSI clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
+ */
+uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
+{
+ uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
+
+ /* DSICLK clock frequency */
+ switch (LL_RCC_GetDSIClockSource(DSIxSource))
+ {
+ case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
+ if (LL_RCC_PLL_IsReady())
+ {
+ dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
+ }
+ break;
+
+ case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
+ default:
+ dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return dsi_frequency;
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Return LTDC clock frequency
+ * @param LTDCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE
+ * @retval LTDC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
+ */
+uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
+{
+ uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
+
+ if (LL_RCC_PLLSAI_IsReady())
+ {
+ ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
+ }
+
+ return ltdc_frequency;
+}
+#endif /* LTDC */
+
+#if defined(SPDIFRX)
+/**
+ * @brief Return SPDIFRX clock frequency
+ * @param SPDIFRXxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
+ * @retval SPDIFRX clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ */
+uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
+{
+ uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
+
+ /* SPDIFRX1CLK clock frequency */
+ switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
+ {
+ case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */
+ if (LL_RCC_PLLI2S_IsReady())
+ {
+ spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
+ }
+ break;
+
+ case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */
+ default:
+ if (LL_RCC_PLL_IsReady())
+ {
+ spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();
+ }
+ break;
+ }
+
+ return spdifrx_frequency;
+}
+#endif /* SPDIFRX */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Return SYSTEM clock frequency
+ * @retval SYSTEM clock frequency (in Hz)
+ */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+ uint32_t frequency = 0U;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (LL_RCC_GetSysClkSource())
+ {
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ frequency = HSI_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ frequency = HSE_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
+ frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
+ break;
+
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+ case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */
+ frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);
+ break;
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+
+ default:
+ frequency = HSI_VALUE;
+ break;
+ }
+
+ return frequency;
+}
+
+/**
+ * @brief Return HCLK clock frequency
+ * @param SYSCLK_Frequency SYSCLK clock frequency
+ * @retval HCLK clock frequency (in Hz)
+ */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+ * @brief Return PCLK1 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+ * @brief Return PCLK2 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK2 clock frequency */
+ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @param SYSCLK_Source System clock source
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / (PLLP or PLLR)
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+
+ if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ {
+ plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
+ }
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+ else
+ {
+ plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
+ }
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+
+ return plloutputfreq;
+}
+
+/**
+ * @brief Return PLL clock frequency used for 48 MHz domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_48M(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
+ 48M Domain clock = PLL_VCO / PLLQ
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
+}
+
+#if defined(DSI)
+/**
+ * @brief Return PLL clock frequency used for DSI clock
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_DSI(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ DSICLK = PLL_VCO / PLLR
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
+}
+#endif /* DSI */
+
+#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
+/**
+ * @brief Return PLL clock frequency used for I2S clock
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_I2S(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ I2SCLK = PLL_VCO / PLLR
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
+}
+#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
+
+#if defined(SPDIFRX)
+/**
+ * @brief Return PLL clock frequency used for SPDIFRX clock
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SPDIFRXCLK = PLL_VCO / PLLR
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
+}
+#endif /* SPDIFRX */
+
+#if defined(RCC_PLLCFGR_PLLR)
+#if defined(SAI1)
+/**
+ * @brief Return PLL clock frequency used for SAI clock
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_SAI(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SAICLK = (PLL_VCO / PLLR) / PLLDIVR
+ or
+ SAICLK = PLL_VCO / PLLR
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+
+#if defined(RCC_DCKCFGR_PLLDIVR)
+ plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());
+#else
+ plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
+#endif /* RCC_DCKCFGR_PLLDIVR */
+
+ return plloutputfreq;
+}
+#endif /* SAI1 */
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+ * @brief Return PLLSAI clock frequency used for SAI domain
+ * @retval PLLSAI clock frequency (in Hz)
+ */
+uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
+ SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
+ LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
+}
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+ * @brief Return PLLSAI clock frequency used for 48Mhz domain
+ * @retval PLLSAI clock frequency (in Hz)
+ */
+uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
+ 48M Domain clock = PLLSAI_VCO / PLLSAIP
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
+ LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+#if defined(LTDC)
+/**
+ * @brief Return PLLSAI clock frequency used for LTDC domain
+ * @retval PLLSAI clock frequency (in Hz)
+ */
+uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
+ LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
+ LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
+}
+#endif /* LTDC */
+#endif /* RCC_PLLSAI_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+#if defined(SAI1)
+/**
+ * @brief Return PLLI2S clock frequency used for SAI domains
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
+{
+ uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
+
+ /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
+ SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
+ or
+ SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR
+ */
+ plli2ssource = LL_RCC_PLLI2S_GetMainSource();
+
+ switch (plli2ssource)
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
+ plli2sinputfreq = HSE_VALUE;
+ break;
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
+ case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
+ plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
+ break;
+#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
+ default:
+ plli2sinputfreq = HSI_VALUE;
+ break;
+ }
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+ plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
+ LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
+#else
+ plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
+ LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+
+ return plli2soutputfreq;
+}
+#endif /* SAI1 */
+
+#if defined(SPDIFRX)
+/**
+ * @brief Return PLLI2S clock frequency used for SPDIFRX domain
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
+ SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
+ */
+ pllsource = LL_RCC_PLLI2S_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+
+ return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),
+ LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
+}
+#endif /* SPDIFRX */
+
+/**
+ * @brief Return PLLI2S clock frequency used for I2S domain
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
+{
+ uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
+
+ /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
+ I2S Domain clock = PLLI2S_VCO / PLLI2SR
+ */
+ plli2ssource = LL_RCC_PLLI2S_GetMainSource();
+
+ switch (plli2ssource)
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
+ plli2sinputfreq = HSE_VALUE;
+ break;
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
+ case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
+ plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
+ break;
+#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
+ default:
+ plli2sinputfreq = HSI_VALUE;
+ break;
+ }
+
+ plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
+ LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
+
+ return plli2soutputfreq;
+}
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+ * @brief Return PLLI2S clock frequency used for 48Mhz domain
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+uint32_t RCC_PLLI2S_GetFreqDomain_48M(void)
+{
+ uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
+
+ /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
+ 48M Domain clock = PLLI2S_VCO / PLLI2SQ
+ */
+ plli2ssource = LL_RCC_PLLI2S_GetMainSource();
+
+ switch (plli2ssource)
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
+ plli2sinputfreq = HSE_VALUE;
+ break;
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
+ case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
+ plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
+ break;
+#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
+ default:
+ plli2sinputfreq = HSI_VALUE;
+ break;
+ }
+
+ plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
+ LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());
+
+ return plli2soutputfreq;
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_PLLI2S_SUPPORT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,7115 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_RCC_H
+#define __STM32F4xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+ * @{
+ */
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVR)
+static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
+#endif /* RCC_DCKCFGR_PLLSAIDIVR */
+
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+ * @{
+ */
+
+/**
+ * @brief RCC Clocks Frequency Structure
+ */
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+ * @brief Defines used to adapt values of different oscillators
+ * @note These values could be modified in the user environment according to
+ * HW set-up.
+ * @{
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_WriteReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */
+#endif /* RCC_PLLSAI_SUPPORT */
+#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_ReadReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */
+#endif /* RCC_PLLSAI_SUPPORT */
+#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
+#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
+#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
+#if defined(RCC_CSR_BORRSTF)
+#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
+#endif /* RCC_CSR_BORRSTF */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */
+#endif /* RCC_PLLSAI_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+#if defined(RCC_CFGR_SW_PLLR)
+#define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */
+#endif /* RCC_CFGR_SW_PLLR */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
+ * @{
+ */
+#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
+ * @{
+ */
+#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
+ * @{
+ */
+#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
+ * @{
+ */
+#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
+#if defined(RCC_CFGR_MCO2)
+#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
+#endif /* RCC_CFGR_MCO2 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
+ * @{
+ */
+#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
+#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
+#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
+#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
+#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
+#if defined(RCC_CFGR_MCO2PRE)
+#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
+#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
+#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
+#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
+#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
+#endif /* RCC_CFGR_MCO2PRE */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
+ * @{
+ */
+#define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
+#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
+#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
+#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
+#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
+#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
+#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
+#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
+#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
+#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
+#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
+#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
+#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
+#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
+#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
+#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
+#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
+#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
+#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
+#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
+#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
+#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
+#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
+#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
+#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
+#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
+#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
+#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
+#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
+#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
+#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ * @{
+ */
+#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+#if defined(FMPI2C1)
+/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
+ * @{
+ */
+#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */
+#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */
+#define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */
+/**
+ * @}
+ */
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
+ * @{
+ */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */
+/**
+ * @}
+ */
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
+ * @{
+ */
+#if defined(RCC_DCKCFGR_SAI1SRC)
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */
+#endif /* RCC_DCKCFGR_SAI1SRC */
+#if defined(RCC_DCKCFGR_SAI2SRC)
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */
+#endif /* RCC_DCKCFGR_SAI2SRC */
+#if defined(RCC_DCKCFGR_SAI1ASRC)
+#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */
+#else
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */
+#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
+#endif /* RCC_DCKCFGR_SAI1ASRC */
+#if defined(RCC_DCKCFGR_SAI1BSRC)
+#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */
+#else
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */
+#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
+#endif /* RCC_DCKCFGR_SAI1BSRC */
+/**
+ * @}
+ */
+#endif /* SAI1 */
+
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
+ * @{
+ */
+#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */
+#if defined(RCC_DCKCFGR_SDIOSEL)
+#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */
+#else
+#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */
+#endif /* RCC_DCKCFGR_SDIOSEL */
+/**
+ * @}
+ */
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
+ * @{
+ */
+#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
+#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */
+/**
+ * @}
+ */
+#endif /* DSI */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
+ * @{
+ */
+#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */
+#define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */
+/**
+ * @}
+ */
+#endif /* CEC */
+
+/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
+ * @{
+ */
+#if defined(RCC_CFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
+#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */
+#endif /* RCC_DCKCFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2S1SRC)
+#define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */
+#endif /* RCC_DCKCFGR_I2S1SRC */
+#if defined(RCC_DCKCFGR_I2S2SRC)
+#define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */
+#define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */
+#define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */
+#define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */
+#endif /* RCC_DCKCFGR_I2S2SRC */
+/**
+ * @}
+ */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
+ * @{
+ */
+#if defined(RCC_DCKCFGR_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
+#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
+#endif /* RCC_DCKCFGR_CK48MSEL */
+#if defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_DCKCFGR2_CK48MSEL */
+/**
+ * @}
+ */
+
+#if defined(RNG)
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
+ * @{
+ */
+#define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+/**
+ * @}
+ */
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+/**
+ * @}
+ */
+#endif /* USB_OTG_FS || USB_OTG_HS */
+
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
+ * @{
+ */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */
+#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */
+#endif /* DFSDM2_Channel0 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
+ * @{
+ */
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */
+#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */
+#endif /* DFSDM2_Channel0 */
+/**
+ * @}
+ */
+#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
+
+#if defined(FMPI2C1)
+/** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
+ * @{
+ */
+#define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */
+/**
+ * @}
+ */
+#endif /* FMPI2C1 */
+
+#if defined(SPDIFRX)
+/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
+ * @{
+ */
+#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */
+#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */
+/**
+ * @}
+ */
+#endif /* SPDIFRX */
+
+#if defined(LPTIM1)
+/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
+ * @{
+ */
+#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
+/**
+ * @}
+ */
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
+ * @{
+ */
+#if defined(RCC_DCKCFGR_SAI1ASRC)
+#define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */
+#endif /* RCC_DCKCFGR_SAI1ASRC */
+#if defined(RCC_DCKCFGR_SAI1BSRC)
+#define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */
+#endif /* RCC_DCKCFGR_SAI1BSRC */
+#if defined(RCC_DCKCFGR_SAI1SRC)
+#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */
+#endif /* RCC_DCKCFGR_SAI1SRC */
+#if defined(RCC_DCKCFGR_SAI2SRC)
+#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */
+#endif /* RCC_DCKCFGR_SAI2SRC */
+/**
+ * @}
+ */
+#endif /* SAI1 */
+
+#if defined(SDIO)
+/** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
+ * @{
+ */
+#if defined(RCC_DCKCFGR_SDIOSEL)
+#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */
+#elif defined(RCC_DCKCFGR2_SDIOSEL)
+#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */
+#else
+#define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */
+#endif
+/**
+ * @}
+ */
+#endif /* SDIO */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
+ * @{
+ */
+#if defined(RCC_DCKCFGR_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL */
+#if defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL */
+/**
+ * @}
+ */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(RNG)
+/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
+ * @{
+ */
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */
+#else
+#define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+/**
+ * @}
+ */
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
+ * @{
+ */
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */
+#else
+#define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+/**
+ * @}
+ */
+#endif /* USB_OTG_FS || USB_OTG_HS */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
+ * @{
+ */
+#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
+/**
+ * @}
+ */
+#endif /* CEC */
+
+/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
+ * @{
+ */
+#if defined(RCC_CFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */
+#endif /* RCC_DCKCFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2S1SRC)
+#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */
+#endif /* RCC_DCKCFGR_I2S1SRC */
+#if defined(RCC_DCKCFGR_I2S2SRC)
+#define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */
+#endif /* RCC_DCKCFGR_I2S2SRC */
+/**
+ * @}
+ */
+
+#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
+ * @{
+ */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */
+#endif /* DFSDM2_Channel0 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
+ * @{
+ */
+#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */
+#endif /* DFSDM2_Channel0 */
+/**
+ * @}
+ */
+#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
+
+#if defined(SPDIFRX)
+/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
+ * @{
+ */
+#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */
+/**
+ * @}
+ */
+#endif /* SPDIFRX */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
+ * @{
+ */
+#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */
+/**
+ * @}
+ */
+#endif /* DSI */
+
+#if defined(LTDC)
+/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
+ * @{
+ */
+#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */
+/**
+ * @}
+ */
+#endif /* LTDC */
+
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
+ * @{
+ */
+#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
+/**
+ * @}
+ */
+
+#if defined(RCC_DCKCFGR_TIMPRE)
+/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
+ * @{
+ */
+#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */
+#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */
+/**
+ * @}
+ */
+#endif /* RCC_DCKCFGR_TIMPRE */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
+ * @{
+ */
+#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
+#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
+#define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */
+#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
+ * @{
+ */
+#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
+#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
+#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
+#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
+#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
+#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
+#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
+#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
+#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
+#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
+#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
+#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
+#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
+#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
+#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
+#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
+#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
+#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
+#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
+#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
+#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
+#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
+#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
+#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
+#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
+#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
+#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
+#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
+#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
+#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
+#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
+#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
+#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
+#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
+#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
+#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
+#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
+#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
+#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
+#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
+#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
+#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
+#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
+#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
+#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
+#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
+#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
+#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
+#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
+#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
+#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
+#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
+#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
+#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
+#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
+#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
+#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
+#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
+#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
+#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
+#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
+#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLCFGR_PLLR)
+/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
+ * @{
+ */
+#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
+#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
+#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
+#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
+#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
+#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_DCKCFGR_PLLDIVR)
+/** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
+ * @{
+ */
+#define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */
+#define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */
+#define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */
+#define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */
+#define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */
+#define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */
+#define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */
+#define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */
+#define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */
+#define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */
+#define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */
+#define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */
+#define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */
+#define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */
+#define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */
+#define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */
+#define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */
+#define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */
+#define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */
+#define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */
+#define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */
+#define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */
+#define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */
+#define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */
+#define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */
+#define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */
+#define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */
+#define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */
+#define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */
+#define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */
+#define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */
+/**
+ * @}
+ */
+#endif /* RCC_DCKCFGR_PLLDIVR */
+
+/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
+ * @{
+ */
+#define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
+#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
+#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
+ * @{
+ */
+#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
+#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
+#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
+#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
+#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
+#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
+#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
+#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
+#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
+#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
+#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
+#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
+#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
+#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
+ * @{
+ */
+#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
+#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
+ * @{
+ */
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+#define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */
+#define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */
+#define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */
+#define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */
+#define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */
+#define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */
+#define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */
+#define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */
+#define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */
+#define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */
+#define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */
+#define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */
+#define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */
+#define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */
+#define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */
+#define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */
+#define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */
+#define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */
+#define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */
+#define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */
+#define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */
+#define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */
+#define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */
+#define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */
+#define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */
+#define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */
+#define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */
+#define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */
+#define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */
+#define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */
+#define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */
+#define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */
+#define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */
+#define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */
+#define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */
+#define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */
+#define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */
+#define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */
+#define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */
+#define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */
+#define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */
+#define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */
+#define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */
+#define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */
+#define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */
+#define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */
+#define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */
+#define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */
+#define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */
+#define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */
+#define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */
+#define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */
+#define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */
+#define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */
+#define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */
+#define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */
+#define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */
+#define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */
+#define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */
+#define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */
+#define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */
+#define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */
+#else
+#define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */
+#define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */
+#define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */
+#define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */
+#define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */
+#define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */
+#define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */
+#define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */
+#define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */
+#define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */
+#define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */
+#define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */
+#define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */
+#define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */
+#define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */
+#define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */
+#define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */
+#define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */
+#define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */
+#define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */
+#define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */
+#define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */
+#define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */
+#define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */
+#define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */
+#define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */
+#define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */
+#define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */
+#define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */
+#define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */
+#define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */
+#define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */
+#define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */
+#define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */
+#define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */
+#define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */
+#define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */
+#define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */
+#define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */
+#define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */
+#define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */
+#define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */
+#define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */
+#define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */
+#define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */
+#define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */
+#define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */
+#define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */
+#define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */
+#define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */
+#define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */
+#define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */
+#define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */
+#define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */
+#define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */
+#define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */
+#define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */
+#define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */
+#define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */
+#define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */
+#define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */
+#define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
+ * @{
+ */
+#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */
+#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */
+#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */
+#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */
+#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */
+#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */
+#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */
+#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */
+#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */
+#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */
+#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */
+#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */
+#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */
+#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
+ * @{
+ */
+#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
+#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
+#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
+#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
+#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
+#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
+#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
+#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
+#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
+#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
+#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
+#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
+#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
+#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
+#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
+#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
+#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
+#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
+#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
+#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
+#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
+#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
+#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
+#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
+#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
+#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
+#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
+#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
+#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
+#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
+#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
+#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
+/**
+ * @}
+ */
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVR)
+/** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
+ * @{
+ */
+#define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */
+#define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */
+#define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */
+#define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */
+#define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */
+#define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */
+#define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */
+#define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */
+#define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */
+#define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */
+#define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */
+#define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */
+#define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */
+#define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */
+#define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */
+#define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */
+#define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */
+#define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */
+#define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */
+#define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */
+#define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */
+#define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */
+#define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */
+#define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */
+#define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */
+#define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */
+#define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */
+#define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */
+#define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */
+#define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */
+#define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */
+/**
+ * @}
+ */
+#endif /* RCC_DCKCFGR_PLLI2SDIVR */
+
+/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
+ * @{
+ */
+#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
+#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
+#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
+#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
+#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
+#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
+ * @{
+ */
+#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */
+#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */
+#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */
+#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
+ * @{
+ */
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+#define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */
+#define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */
+#define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */
+#define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */
+#define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */
+#define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */
+#define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */
+#define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */
+#define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */
+#define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */
+#define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */
+#define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */
+#define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */
+#define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */
+#define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */
+#define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */
+#define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */
+#define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */
+#define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */
+#define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */
+#define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */
+#define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */
+#define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */
+#define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */
+#define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */
+#define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */
+#define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */
+#define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */
+#define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */
+#define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */
+#define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */
+#define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */
+#define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */
+#define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */
+#define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */
+#define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */
+#define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */
+#define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */
+#define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */
+#define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */
+#define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */
+#define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */
+#define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */
+#define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */
+#define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */
+#define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */
+#define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */
+#define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */
+#define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */
+#define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */
+#define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */
+#define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */
+#define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */
+#define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */
+#define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */
+#define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */
+#define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */
+#define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */
+#define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */
+#define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */
+#define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */
+#define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */
+#else
+#define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */
+#define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */
+#define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */
+#define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */
+#define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */
+#define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */
+#define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */
+#define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */
+#define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */
+#define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */
+#define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */
+#define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */
+#define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */
+#define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */
+#define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */
+#define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */
+#define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */
+#define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */
+#define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */
+#define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */
+#define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */
+#define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */
+#define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */
+#define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */
+#define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */
+#define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */
+#define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */
+#define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */
+#define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */
+#define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */
+#define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */
+#define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */
+#define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */
+#define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */
+#define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */
+#define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */
+#define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */
+#define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */
+#define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */
+#define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */
+#define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */
+#define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */
+#define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */
+#define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */
+#define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */
+#define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */
+#define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */
+#define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */
+#define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */
+#define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */
+#define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */
+#define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */
+#define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */
+#define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */
+#define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */
+#define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */
+#define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */
+#define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */
+#define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */
+#define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */
+#define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */
+#define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
+ * @{
+ */
+#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */
+#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */
+#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */
+#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */
+#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */
+#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */
+#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */
+#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */
+#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */
+#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */
+#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */
+#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */
+#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */
+#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */
+/**
+ * @}
+ */
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVQ)
+/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
+ * @{
+ */
+#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
+#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
+#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
+#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
+#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
+#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
+#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
+#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
+#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
+#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
+#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
+#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
+#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
+#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
+#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
+#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
+#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
+#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
+#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
+#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
+#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
+#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
+#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
+#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
+#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
+#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
+#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
+#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
+#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
+#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
+#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
+#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
+/**
+ * @}
+ */
+#endif /* RCC_DCKCFGR_PLLSAIDIVQ */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
+ * @{
+ */
+#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */
+#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */
+#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */
+#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */
+#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */
+#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVR)
+/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
+ * @{
+ */
+#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
+#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
+#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
+#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
+/**
+ * @}
+ */
+#endif /* RCC_DCKCFGR_PLLSAIDIVR */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
+ * @{
+ */
+#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */
+#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */
+#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */
+#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+#endif /* RCC_PLLSAI_SUPPORT */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RCC register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RCC register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+ * @{
+ */
+
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency on system domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param __PLLN__ Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLP__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+ ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
+
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLRCLK frequency on system domain
+ * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param __PLLN__ Between 50 and 432
+ * @param __PLLR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param __PLLN__ Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLQ__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLQ_DIV_2
+ * @arg @ref LL_RCC_PLLQ_DIV_3
+ * @arg @ref LL_RCC_PLLQ_DIV_4
+ * @arg @ref LL_RCC_PLLQ_DIV_5
+ * @arg @ref LL_RCC_PLLQ_DIV_6
+ * @arg @ref LL_RCC_PLLQ_DIV_7
+ * @arg @ref LL_RCC_PLLQ_DIV_8
+ * @arg @ref LL_RCC_PLLQ_DIV_9
+ * @arg @ref LL_RCC_PLLQ_DIV_10
+ * @arg @ref LL_RCC_PLLQ_DIV_11
+ * @arg @ref LL_RCC_PLLQ_DIV_12
+ * @arg @ref LL_RCC_PLLQ_DIV_13
+ * @arg @ref LL_RCC_PLLQ_DIV_14
+ * @arg @ref LL_RCC_PLLQ_DIV_15
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+ ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
+
+#if defined(DSI)
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on DSI
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param __PLLN__ Between 50 and 432
+ * @param __PLLR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* DSI */
+
+#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on I2S
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param __PLLN__ Between 50 and 432
+ * @param __PLLR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
+
+#if defined(SPDIFRX)
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param __PLLN__ Between 50 and 432
+ * @param __PLLR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* SPDIFRX */
+
+#if defined(RCC_PLLCFGR_PLLR)
+#if defined(SAI1)
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on SAI
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param __PLLN__ Between 50 and 432
+ * @param __PLLR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ * @param __PLLDIVR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval PLL clock frequency (in Hz)
+ */
+#if defined(RCC_DCKCFGR_PLLDIVR)
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
+#else
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+ ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* RCC_DCKCFGR_PLLDIVR */
+#endif /* SAI1 */
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
+ * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIM_DIV_2
+ * @arg @ref LL_RCC_PLLSAIM_DIV_3
+ * @arg @ref LL_RCC_PLLSAIM_DIV_4
+ * @arg @ref LL_RCC_PLLSAIM_DIV_5
+ * @arg @ref LL_RCC_PLLSAIM_DIV_6
+ * @arg @ref LL_RCC_PLLSAIM_DIV_7
+ * @arg @ref LL_RCC_PLLSAIM_DIV_8
+ * @arg @ref LL_RCC_PLLSAIM_DIV_9
+ * @arg @ref LL_RCC_PLLSAIM_DIV_10
+ * @arg @ref LL_RCC_PLLSAIM_DIV_11
+ * @arg @ref LL_RCC_PLLSAIM_DIV_12
+ * @arg @ref LL_RCC_PLLSAIM_DIV_13
+ * @arg @ref LL_RCC_PLLSAIM_DIV_14
+ * @arg @ref LL_RCC_PLLSAIM_DIV_15
+ * @arg @ref LL_RCC_PLLSAIM_DIV_16
+ * @arg @ref LL_RCC_PLLSAIM_DIV_17
+ * @arg @ref LL_RCC_PLLSAIM_DIV_18
+ * @arg @ref LL_RCC_PLLSAIM_DIV_19
+ * @arg @ref LL_RCC_PLLSAIM_DIV_20
+ * @arg @ref LL_RCC_PLLSAIM_DIV_21
+ * @arg @ref LL_RCC_PLLSAIM_DIV_22
+ * @arg @ref LL_RCC_PLLSAIM_DIV_23
+ * @arg @ref LL_RCC_PLLSAIM_DIV_24
+ * @arg @ref LL_RCC_PLLSAIM_DIV_25
+ * @arg @ref LL_RCC_PLLSAIM_DIV_26
+ * @arg @ref LL_RCC_PLLSAIM_DIV_27
+ * @arg @ref LL_RCC_PLLSAIM_DIV_28
+ * @arg @ref LL_RCC_PLLSAIM_DIV_29
+ * @arg @ref LL_RCC_PLLSAIM_DIV_30
+ * @arg @ref LL_RCC_PLLSAIM_DIV_31
+ * @arg @ref LL_RCC_PLLSAIM_DIV_32
+ * @arg @ref LL_RCC_PLLSAIM_DIV_33
+ * @arg @ref LL_RCC_PLLSAIM_DIV_34
+ * @arg @ref LL_RCC_PLLSAIM_DIV_35
+ * @arg @ref LL_RCC_PLLSAIM_DIV_36
+ * @arg @ref LL_RCC_PLLSAIM_DIV_37
+ * @arg @ref LL_RCC_PLLSAIM_DIV_38
+ * @arg @ref LL_RCC_PLLSAIM_DIV_39
+ * @arg @ref LL_RCC_PLLSAIM_DIV_40
+ * @arg @ref LL_RCC_PLLSAIM_DIV_41
+ * @arg @ref LL_RCC_PLLSAIM_DIV_42
+ * @arg @ref LL_RCC_PLLSAIM_DIV_43
+ * @arg @ref LL_RCC_PLLSAIM_DIV_44
+ * @arg @ref LL_RCC_PLLSAIM_DIV_45
+ * @arg @ref LL_RCC_PLLSAIM_DIV_46
+ * @arg @ref LL_RCC_PLLSAIM_DIV_47
+ * @arg @ref LL_RCC_PLLSAIM_DIV_48
+ * @arg @ref LL_RCC_PLLSAIM_DIV_49
+ * @arg @ref LL_RCC_PLLSAIM_DIV_50
+ * @arg @ref LL_RCC_PLLSAIM_DIV_51
+ * @arg @ref LL_RCC_PLLSAIM_DIV_52
+ * @arg @ref LL_RCC_PLLSAIM_DIV_53
+ * @arg @ref LL_RCC_PLLSAIM_DIV_54
+ * @arg @ref LL_RCC_PLLSAIM_DIV_55
+ * @arg @ref LL_RCC_PLLSAIM_DIV_56
+ * @arg @ref LL_RCC_PLLSAIM_DIV_57
+ * @arg @ref LL_RCC_PLLSAIM_DIV_58
+ * @arg @ref LL_RCC_PLLSAIM_DIV_59
+ * @arg @ref LL_RCC_PLLSAIM_DIV_60
+ * @arg @ref LL_RCC_PLLSAIM_DIV_61
+ * @arg @ref LL_RCC_PLLSAIM_DIV_62
+ * @arg @ref LL_RCC_PLLSAIM_DIV_63
+ * @param __PLLSAIN__ Between 49/50(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLSAIQ__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_2
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_3
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_4
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_5
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_6
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_7
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_8
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_9
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_10
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_11
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_12
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_13
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_14
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_15
+ * @param __PLLSAIDIVQ__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+ * @retval PLLSAI clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+ (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+ * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
+ * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIM_DIV_2
+ * @arg @ref LL_RCC_PLLSAIM_DIV_3
+ * @arg @ref LL_RCC_PLLSAIM_DIV_4
+ * @arg @ref LL_RCC_PLLSAIM_DIV_5
+ * @arg @ref LL_RCC_PLLSAIM_DIV_6
+ * @arg @ref LL_RCC_PLLSAIM_DIV_7
+ * @arg @ref LL_RCC_PLLSAIM_DIV_8
+ * @arg @ref LL_RCC_PLLSAIM_DIV_9
+ * @arg @ref LL_RCC_PLLSAIM_DIV_10
+ * @arg @ref LL_RCC_PLLSAIM_DIV_11
+ * @arg @ref LL_RCC_PLLSAIM_DIV_12
+ * @arg @ref LL_RCC_PLLSAIM_DIV_13
+ * @arg @ref LL_RCC_PLLSAIM_DIV_14
+ * @arg @ref LL_RCC_PLLSAIM_DIV_15
+ * @arg @ref LL_RCC_PLLSAIM_DIV_16
+ * @arg @ref LL_RCC_PLLSAIM_DIV_17
+ * @arg @ref LL_RCC_PLLSAIM_DIV_18
+ * @arg @ref LL_RCC_PLLSAIM_DIV_19
+ * @arg @ref LL_RCC_PLLSAIM_DIV_20
+ * @arg @ref LL_RCC_PLLSAIM_DIV_21
+ * @arg @ref LL_RCC_PLLSAIM_DIV_22
+ * @arg @ref LL_RCC_PLLSAIM_DIV_23
+ * @arg @ref LL_RCC_PLLSAIM_DIV_24
+ * @arg @ref LL_RCC_PLLSAIM_DIV_25
+ * @arg @ref LL_RCC_PLLSAIM_DIV_26
+ * @arg @ref LL_RCC_PLLSAIM_DIV_27
+ * @arg @ref LL_RCC_PLLSAIM_DIV_28
+ * @arg @ref LL_RCC_PLLSAIM_DIV_29
+ * @arg @ref LL_RCC_PLLSAIM_DIV_30
+ * @arg @ref LL_RCC_PLLSAIM_DIV_31
+ * @arg @ref LL_RCC_PLLSAIM_DIV_32
+ * @arg @ref LL_RCC_PLLSAIM_DIV_33
+ * @arg @ref LL_RCC_PLLSAIM_DIV_34
+ * @arg @ref LL_RCC_PLLSAIM_DIV_35
+ * @arg @ref LL_RCC_PLLSAIM_DIV_36
+ * @arg @ref LL_RCC_PLLSAIM_DIV_37
+ * @arg @ref LL_RCC_PLLSAIM_DIV_38
+ * @arg @ref LL_RCC_PLLSAIM_DIV_39
+ * @arg @ref LL_RCC_PLLSAIM_DIV_40
+ * @arg @ref LL_RCC_PLLSAIM_DIV_41
+ * @arg @ref LL_RCC_PLLSAIM_DIV_42
+ * @arg @ref LL_RCC_PLLSAIM_DIV_43
+ * @arg @ref LL_RCC_PLLSAIM_DIV_44
+ * @arg @ref LL_RCC_PLLSAIM_DIV_45
+ * @arg @ref LL_RCC_PLLSAIM_DIV_46
+ * @arg @ref LL_RCC_PLLSAIM_DIV_47
+ * @arg @ref LL_RCC_PLLSAIM_DIV_48
+ * @arg @ref LL_RCC_PLLSAIM_DIV_49
+ * @arg @ref LL_RCC_PLLSAIM_DIV_50
+ * @arg @ref LL_RCC_PLLSAIM_DIV_51
+ * @arg @ref LL_RCC_PLLSAIM_DIV_52
+ * @arg @ref LL_RCC_PLLSAIM_DIV_53
+ * @arg @ref LL_RCC_PLLSAIM_DIV_54
+ * @arg @ref LL_RCC_PLLSAIM_DIV_55
+ * @arg @ref LL_RCC_PLLSAIM_DIV_56
+ * @arg @ref LL_RCC_PLLSAIM_DIV_57
+ * @arg @ref LL_RCC_PLLSAIM_DIV_58
+ * @arg @ref LL_RCC_PLLSAIM_DIV_59
+ * @arg @ref LL_RCC_PLLSAIM_DIV_60
+ * @arg @ref LL_RCC_PLLSAIM_DIV_61
+ * @arg @ref LL_RCC_PLLSAIM_DIV_62
+ * @arg @ref LL_RCC_PLLSAIM_DIV_63
+ * @param __PLLSAIN__ Between 50 and 432
+ * @param __PLLSAIP__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIP_DIV_2
+ * @arg @ref LL_RCC_PLLSAIP_DIV_4
+ * @arg @ref LL_RCC_PLLSAIP_DIV_6
+ * @arg @ref LL_RCC_PLLSAIP_DIV_8
+ * @retval PLLSAI clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+ ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+#if defined(LTDC)
+/**
+ * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
+ * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIM_DIV_2
+ * @arg @ref LL_RCC_PLLSAIM_DIV_3
+ * @arg @ref LL_RCC_PLLSAIM_DIV_4
+ * @arg @ref LL_RCC_PLLSAIM_DIV_5
+ * @arg @ref LL_RCC_PLLSAIM_DIV_6
+ * @arg @ref LL_RCC_PLLSAIM_DIV_7
+ * @arg @ref LL_RCC_PLLSAIM_DIV_8
+ * @arg @ref LL_RCC_PLLSAIM_DIV_9
+ * @arg @ref LL_RCC_PLLSAIM_DIV_10
+ * @arg @ref LL_RCC_PLLSAIM_DIV_11
+ * @arg @ref LL_RCC_PLLSAIM_DIV_12
+ * @arg @ref LL_RCC_PLLSAIM_DIV_13
+ * @arg @ref LL_RCC_PLLSAIM_DIV_14
+ * @arg @ref LL_RCC_PLLSAIM_DIV_15
+ * @arg @ref LL_RCC_PLLSAIM_DIV_16
+ * @arg @ref LL_RCC_PLLSAIM_DIV_17
+ * @arg @ref LL_RCC_PLLSAIM_DIV_18
+ * @arg @ref LL_RCC_PLLSAIM_DIV_19
+ * @arg @ref LL_RCC_PLLSAIM_DIV_20
+ * @arg @ref LL_RCC_PLLSAIM_DIV_21
+ * @arg @ref LL_RCC_PLLSAIM_DIV_22
+ * @arg @ref LL_RCC_PLLSAIM_DIV_23
+ * @arg @ref LL_RCC_PLLSAIM_DIV_24
+ * @arg @ref LL_RCC_PLLSAIM_DIV_25
+ * @arg @ref LL_RCC_PLLSAIM_DIV_26
+ * @arg @ref LL_RCC_PLLSAIM_DIV_27
+ * @arg @ref LL_RCC_PLLSAIM_DIV_28
+ * @arg @ref LL_RCC_PLLSAIM_DIV_29
+ * @arg @ref LL_RCC_PLLSAIM_DIV_30
+ * @arg @ref LL_RCC_PLLSAIM_DIV_31
+ * @arg @ref LL_RCC_PLLSAIM_DIV_32
+ * @arg @ref LL_RCC_PLLSAIM_DIV_33
+ * @arg @ref LL_RCC_PLLSAIM_DIV_34
+ * @arg @ref LL_RCC_PLLSAIM_DIV_35
+ * @arg @ref LL_RCC_PLLSAIM_DIV_36
+ * @arg @ref LL_RCC_PLLSAIM_DIV_37
+ * @arg @ref LL_RCC_PLLSAIM_DIV_38
+ * @arg @ref LL_RCC_PLLSAIM_DIV_39
+ * @arg @ref LL_RCC_PLLSAIM_DIV_40
+ * @arg @ref LL_RCC_PLLSAIM_DIV_41
+ * @arg @ref LL_RCC_PLLSAIM_DIV_42
+ * @arg @ref LL_RCC_PLLSAIM_DIV_43
+ * @arg @ref LL_RCC_PLLSAIM_DIV_44
+ * @arg @ref LL_RCC_PLLSAIM_DIV_45
+ * @arg @ref LL_RCC_PLLSAIM_DIV_46
+ * @arg @ref LL_RCC_PLLSAIM_DIV_47
+ * @arg @ref LL_RCC_PLLSAIM_DIV_48
+ * @arg @ref LL_RCC_PLLSAIM_DIV_49
+ * @arg @ref LL_RCC_PLLSAIM_DIV_50
+ * @arg @ref LL_RCC_PLLSAIM_DIV_51
+ * @arg @ref LL_RCC_PLLSAIM_DIV_52
+ * @arg @ref LL_RCC_PLLSAIM_DIV_53
+ * @arg @ref LL_RCC_PLLSAIM_DIV_54
+ * @arg @ref LL_RCC_PLLSAIM_DIV_55
+ * @arg @ref LL_RCC_PLLSAIM_DIV_56
+ * @arg @ref LL_RCC_PLLSAIM_DIV_57
+ * @arg @ref LL_RCC_PLLSAIM_DIV_58
+ * @arg @ref LL_RCC_PLLSAIM_DIV_59
+ * @arg @ref LL_RCC_PLLSAIM_DIV_60
+ * @arg @ref LL_RCC_PLLSAIM_DIV_61
+ * @arg @ref LL_RCC_PLLSAIM_DIV_62
+ * @arg @ref LL_RCC_PLLSAIM_DIV_63
+ * @param __PLLSAIN__ Between 49/50(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLSAIR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIR_DIV_2
+ * @arg @ref LL_RCC_PLLSAIR_DIV_3
+ * @arg @ref LL_RCC_PLLSAIR_DIV_4
+ * @arg @ref LL_RCC_PLLSAIR_DIV_5
+ * @arg @ref LL_RCC_PLLSAIR_DIV_6
+ * @arg @ref LL_RCC_PLLSAIR_DIV_7
+ * @param __PLLSAIDIVR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+ * @retval PLLSAI clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+ (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
+#endif /* LTDC */
+#endif /* RCC_PLLSAI_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
+/**
+ * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+ * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SM_DIV_2
+ * @arg @ref LL_RCC_PLLI2SM_DIV_3
+ * @arg @ref LL_RCC_PLLI2SM_DIV_4
+ * @arg @ref LL_RCC_PLLI2SM_DIV_5
+ * @arg @ref LL_RCC_PLLI2SM_DIV_6
+ * @arg @ref LL_RCC_PLLI2SM_DIV_7
+ * @arg @ref LL_RCC_PLLI2SM_DIV_8
+ * @arg @ref LL_RCC_PLLI2SM_DIV_9
+ * @arg @ref LL_RCC_PLLI2SM_DIV_10
+ * @arg @ref LL_RCC_PLLI2SM_DIV_11
+ * @arg @ref LL_RCC_PLLI2SM_DIV_12
+ * @arg @ref LL_RCC_PLLI2SM_DIV_13
+ * @arg @ref LL_RCC_PLLI2SM_DIV_14
+ * @arg @ref LL_RCC_PLLI2SM_DIV_15
+ * @arg @ref LL_RCC_PLLI2SM_DIV_16
+ * @arg @ref LL_RCC_PLLI2SM_DIV_17
+ * @arg @ref LL_RCC_PLLI2SM_DIV_18
+ * @arg @ref LL_RCC_PLLI2SM_DIV_19
+ * @arg @ref LL_RCC_PLLI2SM_DIV_20
+ * @arg @ref LL_RCC_PLLI2SM_DIV_21
+ * @arg @ref LL_RCC_PLLI2SM_DIV_22
+ * @arg @ref LL_RCC_PLLI2SM_DIV_23
+ * @arg @ref LL_RCC_PLLI2SM_DIV_24
+ * @arg @ref LL_RCC_PLLI2SM_DIV_25
+ * @arg @ref LL_RCC_PLLI2SM_DIV_26
+ * @arg @ref LL_RCC_PLLI2SM_DIV_27
+ * @arg @ref LL_RCC_PLLI2SM_DIV_28
+ * @arg @ref LL_RCC_PLLI2SM_DIV_29
+ * @arg @ref LL_RCC_PLLI2SM_DIV_30
+ * @arg @ref LL_RCC_PLLI2SM_DIV_31
+ * @arg @ref LL_RCC_PLLI2SM_DIV_32
+ * @arg @ref LL_RCC_PLLI2SM_DIV_33
+ * @arg @ref LL_RCC_PLLI2SM_DIV_34
+ * @arg @ref LL_RCC_PLLI2SM_DIV_35
+ * @arg @ref LL_RCC_PLLI2SM_DIV_36
+ * @arg @ref LL_RCC_PLLI2SM_DIV_37
+ * @arg @ref LL_RCC_PLLI2SM_DIV_38
+ * @arg @ref LL_RCC_PLLI2SM_DIV_39
+ * @arg @ref LL_RCC_PLLI2SM_DIV_40
+ * @arg @ref LL_RCC_PLLI2SM_DIV_41
+ * @arg @ref LL_RCC_PLLI2SM_DIV_42
+ * @arg @ref LL_RCC_PLLI2SM_DIV_43
+ * @arg @ref LL_RCC_PLLI2SM_DIV_44
+ * @arg @ref LL_RCC_PLLI2SM_DIV_45
+ * @arg @ref LL_RCC_PLLI2SM_DIV_46
+ * @arg @ref LL_RCC_PLLI2SM_DIV_47
+ * @arg @ref LL_RCC_PLLI2SM_DIV_48
+ * @arg @ref LL_RCC_PLLI2SM_DIV_49
+ * @arg @ref LL_RCC_PLLI2SM_DIV_50
+ * @arg @ref LL_RCC_PLLI2SM_DIV_51
+ * @arg @ref LL_RCC_PLLI2SM_DIV_52
+ * @arg @ref LL_RCC_PLLI2SM_DIV_53
+ * @arg @ref LL_RCC_PLLI2SM_DIV_54
+ * @arg @ref LL_RCC_PLLI2SM_DIV_55
+ * @arg @ref LL_RCC_PLLI2SM_DIV_56
+ * @arg @ref LL_RCC_PLLI2SM_DIV_57
+ * @arg @ref LL_RCC_PLLI2SM_DIV_58
+ * @arg @ref LL_RCC_PLLI2SM_DIV_59
+ * @arg @ref LL_RCC_PLLI2SM_DIV_60
+ * @arg @ref LL_RCC_PLLI2SM_DIV_61
+ * @arg @ref LL_RCC_PLLI2SM_DIV_62
+ * @arg @ref LL_RCC_PLLI2SM_DIV_63
+ * @param __PLLI2SN__ Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLI2SQ_R__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+ (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
+#else
+#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+ (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
+
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
+
+#if defined(SPDIFRX)
+/**
+ * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
+ * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+ * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SM_DIV_2
+ * @arg @ref LL_RCC_PLLI2SM_DIV_3
+ * @arg @ref LL_RCC_PLLI2SM_DIV_4
+ * @arg @ref LL_RCC_PLLI2SM_DIV_5
+ * @arg @ref LL_RCC_PLLI2SM_DIV_6
+ * @arg @ref LL_RCC_PLLI2SM_DIV_7
+ * @arg @ref LL_RCC_PLLI2SM_DIV_8
+ * @arg @ref LL_RCC_PLLI2SM_DIV_9
+ * @arg @ref LL_RCC_PLLI2SM_DIV_10
+ * @arg @ref LL_RCC_PLLI2SM_DIV_11
+ * @arg @ref LL_RCC_PLLI2SM_DIV_12
+ * @arg @ref LL_RCC_PLLI2SM_DIV_13
+ * @arg @ref LL_RCC_PLLI2SM_DIV_14
+ * @arg @ref LL_RCC_PLLI2SM_DIV_15
+ * @arg @ref LL_RCC_PLLI2SM_DIV_16
+ * @arg @ref LL_RCC_PLLI2SM_DIV_17
+ * @arg @ref LL_RCC_PLLI2SM_DIV_18
+ * @arg @ref LL_RCC_PLLI2SM_DIV_19
+ * @arg @ref LL_RCC_PLLI2SM_DIV_20
+ * @arg @ref LL_RCC_PLLI2SM_DIV_21
+ * @arg @ref LL_RCC_PLLI2SM_DIV_22
+ * @arg @ref LL_RCC_PLLI2SM_DIV_23
+ * @arg @ref LL_RCC_PLLI2SM_DIV_24
+ * @arg @ref LL_RCC_PLLI2SM_DIV_25
+ * @arg @ref LL_RCC_PLLI2SM_DIV_26
+ * @arg @ref LL_RCC_PLLI2SM_DIV_27
+ * @arg @ref LL_RCC_PLLI2SM_DIV_28
+ * @arg @ref LL_RCC_PLLI2SM_DIV_29
+ * @arg @ref LL_RCC_PLLI2SM_DIV_30
+ * @arg @ref LL_RCC_PLLI2SM_DIV_31
+ * @arg @ref LL_RCC_PLLI2SM_DIV_32
+ * @arg @ref LL_RCC_PLLI2SM_DIV_33
+ * @arg @ref LL_RCC_PLLI2SM_DIV_34
+ * @arg @ref LL_RCC_PLLI2SM_DIV_35
+ * @arg @ref LL_RCC_PLLI2SM_DIV_36
+ * @arg @ref LL_RCC_PLLI2SM_DIV_37
+ * @arg @ref LL_RCC_PLLI2SM_DIV_38
+ * @arg @ref LL_RCC_PLLI2SM_DIV_39
+ * @arg @ref LL_RCC_PLLI2SM_DIV_40
+ * @arg @ref LL_RCC_PLLI2SM_DIV_41
+ * @arg @ref LL_RCC_PLLI2SM_DIV_42
+ * @arg @ref LL_RCC_PLLI2SM_DIV_43
+ * @arg @ref LL_RCC_PLLI2SM_DIV_44
+ * @arg @ref LL_RCC_PLLI2SM_DIV_45
+ * @arg @ref LL_RCC_PLLI2SM_DIV_46
+ * @arg @ref LL_RCC_PLLI2SM_DIV_47
+ * @arg @ref LL_RCC_PLLI2SM_DIV_48
+ * @arg @ref LL_RCC_PLLI2SM_DIV_49
+ * @arg @ref LL_RCC_PLLI2SM_DIV_50
+ * @arg @ref LL_RCC_PLLI2SM_DIV_51
+ * @arg @ref LL_RCC_PLLI2SM_DIV_52
+ * @arg @ref LL_RCC_PLLI2SM_DIV_53
+ * @arg @ref LL_RCC_PLLI2SM_DIV_54
+ * @arg @ref LL_RCC_PLLI2SM_DIV_55
+ * @arg @ref LL_RCC_PLLI2SM_DIV_56
+ * @arg @ref LL_RCC_PLLI2SM_DIV_57
+ * @arg @ref LL_RCC_PLLI2SM_DIV_58
+ * @arg @ref LL_RCC_PLLI2SM_DIV_59
+ * @arg @ref LL_RCC_PLLI2SM_DIV_60
+ * @arg @ref LL_RCC_PLLI2SM_DIV_61
+ * @arg @ref LL_RCC_PLLI2SM_DIV_62
+ * @arg @ref LL_RCC_PLLI2SM_DIV_63
+ * @param __PLLI2SN__ Between 50 and 432
+ * @param __PLLI2SP__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SP_DIV_2
+ * @arg @ref LL_RCC_PLLI2SP_DIV_4
+ * @arg @ref LL_RCC_PLLI2SP_DIV_6
+ * @arg @ref LL_RCC_PLLI2SP_DIV_8
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+ ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
+
+#endif /* SPDIFRX */
+
+/**
+ * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
+ * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+ * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SM_DIV_2
+ * @arg @ref LL_RCC_PLLI2SM_DIV_3
+ * @arg @ref LL_RCC_PLLI2SM_DIV_4
+ * @arg @ref LL_RCC_PLLI2SM_DIV_5
+ * @arg @ref LL_RCC_PLLI2SM_DIV_6
+ * @arg @ref LL_RCC_PLLI2SM_DIV_7
+ * @arg @ref LL_RCC_PLLI2SM_DIV_8
+ * @arg @ref LL_RCC_PLLI2SM_DIV_9
+ * @arg @ref LL_RCC_PLLI2SM_DIV_10
+ * @arg @ref LL_RCC_PLLI2SM_DIV_11
+ * @arg @ref LL_RCC_PLLI2SM_DIV_12
+ * @arg @ref LL_RCC_PLLI2SM_DIV_13
+ * @arg @ref LL_RCC_PLLI2SM_DIV_14
+ * @arg @ref LL_RCC_PLLI2SM_DIV_15
+ * @arg @ref LL_RCC_PLLI2SM_DIV_16
+ * @arg @ref LL_RCC_PLLI2SM_DIV_17
+ * @arg @ref LL_RCC_PLLI2SM_DIV_18
+ * @arg @ref LL_RCC_PLLI2SM_DIV_19
+ * @arg @ref LL_RCC_PLLI2SM_DIV_20
+ * @arg @ref LL_RCC_PLLI2SM_DIV_21
+ * @arg @ref LL_RCC_PLLI2SM_DIV_22
+ * @arg @ref LL_RCC_PLLI2SM_DIV_23
+ * @arg @ref LL_RCC_PLLI2SM_DIV_24
+ * @arg @ref LL_RCC_PLLI2SM_DIV_25
+ * @arg @ref LL_RCC_PLLI2SM_DIV_26
+ * @arg @ref LL_RCC_PLLI2SM_DIV_27
+ * @arg @ref LL_RCC_PLLI2SM_DIV_28
+ * @arg @ref LL_RCC_PLLI2SM_DIV_29
+ * @arg @ref LL_RCC_PLLI2SM_DIV_30
+ * @arg @ref LL_RCC_PLLI2SM_DIV_31
+ * @arg @ref LL_RCC_PLLI2SM_DIV_32
+ * @arg @ref LL_RCC_PLLI2SM_DIV_33
+ * @arg @ref LL_RCC_PLLI2SM_DIV_34
+ * @arg @ref LL_RCC_PLLI2SM_DIV_35
+ * @arg @ref LL_RCC_PLLI2SM_DIV_36
+ * @arg @ref LL_RCC_PLLI2SM_DIV_37
+ * @arg @ref LL_RCC_PLLI2SM_DIV_38
+ * @arg @ref LL_RCC_PLLI2SM_DIV_39
+ * @arg @ref LL_RCC_PLLI2SM_DIV_40
+ * @arg @ref LL_RCC_PLLI2SM_DIV_41
+ * @arg @ref LL_RCC_PLLI2SM_DIV_42
+ * @arg @ref LL_RCC_PLLI2SM_DIV_43
+ * @arg @ref LL_RCC_PLLI2SM_DIV_44
+ * @arg @ref LL_RCC_PLLI2SM_DIV_45
+ * @arg @ref LL_RCC_PLLI2SM_DIV_46
+ * @arg @ref LL_RCC_PLLI2SM_DIV_47
+ * @arg @ref LL_RCC_PLLI2SM_DIV_48
+ * @arg @ref LL_RCC_PLLI2SM_DIV_49
+ * @arg @ref LL_RCC_PLLI2SM_DIV_50
+ * @arg @ref LL_RCC_PLLI2SM_DIV_51
+ * @arg @ref LL_RCC_PLLI2SM_DIV_52
+ * @arg @ref LL_RCC_PLLI2SM_DIV_53
+ * @arg @ref LL_RCC_PLLI2SM_DIV_54
+ * @arg @ref LL_RCC_PLLI2SM_DIV_55
+ * @arg @ref LL_RCC_PLLI2SM_DIV_56
+ * @arg @ref LL_RCC_PLLI2SM_DIV_57
+ * @arg @ref LL_RCC_PLLI2SM_DIV_58
+ * @arg @ref LL_RCC_PLLI2SM_DIV_59
+ * @arg @ref LL_RCC_PLLI2SM_DIV_60
+ * @arg @ref LL_RCC_PLLI2SM_DIV_61
+ * @arg @ref LL_RCC_PLLI2SM_DIV_62
+ * @arg @ref LL_RCC_PLLI2SM_DIV_63
+ * @param __PLLI2SN__ Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLI2SR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SR_DIV_2
+ * @arg @ref LL_RCC_PLLI2SR_DIV_3
+ * @arg @ref LL_RCC_PLLI2SR_DIV_4
+ * @arg @ref LL_RCC_PLLI2SR_DIV_5
+ * @arg @ref LL_RCC_PLLI2SR_DIV_6
+ * @arg @ref LL_RCC_PLLI2SR_DIV_7
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+ ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+ * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
+ * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+ * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SM_DIV_2
+ * @arg @ref LL_RCC_PLLI2SM_DIV_3
+ * @arg @ref LL_RCC_PLLI2SM_DIV_4
+ * @arg @ref LL_RCC_PLLI2SM_DIV_5
+ * @arg @ref LL_RCC_PLLI2SM_DIV_6
+ * @arg @ref LL_RCC_PLLI2SM_DIV_7
+ * @arg @ref LL_RCC_PLLI2SM_DIV_8
+ * @arg @ref LL_RCC_PLLI2SM_DIV_9
+ * @arg @ref LL_RCC_PLLI2SM_DIV_10
+ * @arg @ref LL_RCC_PLLI2SM_DIV_11
+ * @arg @ref LL_RCC_PLLI2SM_DIV_12
+ * @arg @ref LL_RCC_PLLI2SM_DIV_13
+ * @arg @ref LL_RCC_PLLI2SM_DIV_14
+ * @arg @ref LL_RCC_PLLI2SM_DIV_15
+ * @arg @ref LL_RCC_PLLI2SM_DIV_16
+ * @arg @ref LL_RCC_PLLI2SM_DIV_17
+ * @arg @ref LL_RCC_PLLI2SM_DIV_18
+ * @arg @ref LL_RCC_PLLI2SM_DIV_19
+ * @arg @ref LL_RCC_PLLI2SM_DIV_20
+ * @arg @ref LL_RCC_PLLI2SM_DIV_21
+ * @arg @ref LL_RCC_PLLI2SM_DIV_22
+ * @arg @ref LL_RCC_PLLI2SM_DIV_23
+ * @arg @ref LL_RCC_PLLI2SM_DIV_24
+ * @arg @ref LL_RCC_PLLI2SM_DIV_25
+ * @arg @ref LL_RCC_PLLI2SM_DIV_26
+ * @arg @ref LL_RCC_PLLI2SM_DIV_27
+ * @arg @ref LL_RCC_PLLI2SM_DIV_28
+ * @arg @ref LL_RCC_PLLI2SM_DIV_29
+ * @arg @ref LL_RCC_PLLI2SM_DIV_30
+ * @arg @ref LL_RCC_PLLI2SM_DIV_31
+ * @arg @ref LL_RCC_PLLI2SM_DIV_32
+ * @arg @ref LL_RCC_PLLI2SM_DIV_33
+ * @arg @ref LL_RCC_PLLI2SM_DIV_34
+ * @arg @ref LL_RCC_PLLI2SM_DIV_35
+ * @arg @ref LL_RCC_PLLI2SM_DIV_36
+ * @arg @ref LL_RCC_PLLI2SM_DIV_37
+ * @arg @ref LL_RCC_PLLI2SM_DIV_38
+ * @arg @ref LL_RCC_PLLI2SM_DIV_39
+ * @arg @ref LL_RCC_PLLI2SM_DIV_40
+ * @arg @ref LL_RCC_PLLI2SM_DIV_41
+ * @arg @ref LL_RCC_PLLI2SM_DIV_42
+ * @arg @ref LL_RCC_PLLI2SM_DIV_43
+ * @arg @ref LL_RCC_PLLI2SM_DIV_44
+ * @arg @ref LL_RCC_PLLI2SM_DIV_45
+ * @arg @ref LL_RCC_PLLI2SM_DIV_46
+ * @arg @ref LL_RCC_PLLI2SM_DIV_47
+ * @arg @ref LL_RCC_PLLI2SM_DIV_48
+ * @arg @ref LL_RCC_PLLI2SM_DIV_49
+ * @arg @ref LL_RCC_PLLI2SM_DIV_50
+ * @arg @ref LL_RCC_PLLI2SM_DIV_51
+ * @arg @ref LL_RCC_PLLI2SM_DIV_52
+ * @arg @ref LL_RCC_PLLI2SM_DIV_53
+ * @arg @ref LL_RCC_PLLI2SM_DIV_54
+ * @arg @ref LL_RCC_PLLI2SM_DIV_55
+ * @arg @ref LL_RCC_PLLI2SM_DIV_56
+ * @arg @ref LL_RCC_PLLI2SM_DIV_57
+ * @arg @ref LL_RCC_PLLI2SM_DIV_58
+ * @arg @ref LL_RCC_PLLI2SM_DIV_59
+ * @arg @ref LL_RCC_PLLI2SM_DIV_60
+ * @arg @ref LL_RCC_PLLI2SM_DIV_61
+ * @arg @ref LL_RCC_PLLI2SM_DIV_62
+ * @arg @ref LL_RCC_PLLI2SM_DIV_63
+ * @param __PLLI2SN__ Between 50 and 432
+ * @param __PLLI2SQ__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_2
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_3
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_4
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_5
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_6
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_7
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_8
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_9
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_10
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_11
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_12
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_13
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_14
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_15
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+ ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
+
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+/**
+ * @brief Helper macro to calculate the HCLK frequency
+ * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+ * @param __AHBPRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval HCLK clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB1PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB2PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+ * @{
+ */
+
+/**
+ * @brief Enable the Clock Security System.
+ * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Enable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Disable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Enable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Disable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Check if HSE oscillator Ready
+ * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+ * @{
+ */
+
+/**
+ * @brief Enable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Disable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Check if HSI clock is ready
+ * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+ * @brief Get HSI Calibration value
+ * @note When HSITRIM is written, HSICAL is updated with the sum of
+ * HSITRIM and the factory trim value
+ * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
+}
+
+/**
+ * @brief Set HSI Calibration trimming
+ * @note user-programmable trimming value that is added to the HSICAL
+ * @note Default value is 16, which, when added to the HSICAL value,
+ * should trim the HSI to 16 MHz +/- 1 %
+ * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
+ * @param Value Between Min_Data = 0 and Max_Data = 31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
+}
+
+/**
+ * @brief Get HSI Calibration trimming
+ * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
+ * @retval Between Min_Data = 0 and Max_Data = 31
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+ * @{
+ */
+
+/**
+ * @brief Enable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Disable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Enable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Disable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Check if LSE oscillator Ready
+ * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+}
+
+#if defined(RCC_BDCR_LSEMOD)
+/**
+ * @brief Enable LSE high drive mode.
+ * @note LSE high drive mode can be enabled only when the LSE clock is disabled
+ * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+}
+
+/**
+ * @brief Disable LSE high drive mode.
+ * @note LSE high drive mode can be disabled only when the LSE clock is disabled
+ * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+}
+#endif /* RCC_BDCR_LSEMOD */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+ * @{
+ */
+
+/**
+ * @brief Enable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Disable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Check if LSI is Ready
+ * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_System System
+ * @{
+ */
+
+/**
+ * @brief Configure the system clock source
+ * @rmtoll CFGR SW LL_RCC_SetSysClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+ * @brief Get the system clock source
+ * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+ * @brief Set AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+ * @brief Set APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+ * @brief Set APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+ * @brief Get AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+ * @brief Get APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+ * @brief Get APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+ * @{
+ */
+
+#if defined(RCC_CFGR_MCO1EN)
+/**
+ * @brief Enable MCO1 output
+ * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MCO1_Enable(void)
+{
+ SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
+}
+
+/**
+ * @brief Disable MCO1 output
+ * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MCO1_Disable(void)
+{
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
+}
+#endif /* RCC_CFGR_MCO1EN */
+
+#if defined(RCC_CFGR_MCO2EN)
+/**
+ * @brief Enable MCO2 output
+ * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MCO2_Enable(void)
+{
+ SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
+}
+
+/**
+ * @brief Disable MCO2 output
+ * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MCO2_Disable(void)
+{
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
+}
+#endif /* RCC_CFGR_MCO2EN */
+
+/**
+ * @brief Configure MCOx
+ * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
+ * CFGR MCO1PRE LL_RCC_ConfigMCO\n
+ * CFGR MCO2 LL_RCC_ConfigMCO\n
+ * CFGR MCO2PRE LL_RCC_ConfigMCO
+ * @param MCOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI
+ * @arg @ref LL_RCC_MCO1SOURCE_LSE
+ * @arg @ref LL_RCC_MCO1SOURCE_HSE
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+ * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
+ * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
+ * @arg @ref LL_RCC_MCO2SOURCE_HSE
+ * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
+ * @param MCOxPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1_DIV_1
+ * @arg @ref LL_RCC_MCO1_DIV_2
+ * @arg @ref LL_RCC_MCO1_DIV_3
+ * @arg @ref LL_RCC_MCO1_DIV_4
+ * @arg @ref LL_RCC_MCO1_DIV_5
+ * @arg @ref LL_RCC_MCO2_DIV_1
+ * @arg @ref LL_RCC_MCO2_DIV_2
+ * @arg @ref LL_RCC_MCO2_DIV_3
+ * @arg @ref LL_RCC_MCO2_DIV_4
+ * @arg @ref LL_RCC_MCO2_DIV_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+ MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+ * @{
+ */
+#if defined(FMPI2C1)
+/**
+ * @brief Configure FMPI2C clock source
+ * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
+ * @param FMPI2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
+{
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
+}
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+/**
+ * @brief Configure LPTIMx clock source
+ * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
+ * @param LPTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+{
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
+}
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/**
+ * @brief Configure SAIx clock source
+ * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
+ * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
+ * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
+ * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
+ * @param SAIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+{
+ MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
+}
+#endif /* SAI1 */
+
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+/**
+ * @brief Configure SDIO clock source
+ * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
+ * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
+ * @param SDIOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
+ * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
+{
+#if defined(RCC_DCKCFGR_SDIOSEL)
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
+#else
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
+#endif /* RCC_DCKCFGR_SDIOSEL */
+}
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/**
+ * @brief Configure 48Mhz domain clock source
+ * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
+ * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
+ * @param CK48MxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
+#else
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+
+#if defined(RNG)
+/**
+ * @brief Configure RNG clock source
+ * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
+ * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
+ * @param RNGxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
+#else
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/**
+ * @brief Configure USB clock source
+ * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
+ * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
+#else
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(CEC)
+/**
+ * @brief Configure CEC clock source
+ * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
+}
+#endif /* CEC */
+
+/**
+ * @brief Configure I2S clock source
+ * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
+ * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
+ * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
+ * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
+{
+#if defined(RCC_CFGR_I2SSRC)
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
+#else
+ MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
+#endif /* RCC_CFGR_I2SSRC */
+}
+
+#if defined(DSI)
+/**
+ * @brief Configure DSI clock source
+ * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
+}
+#endif /* DSI */
+
+#if defined(DFSDM1_Channel0)
+/**
+ * @brief Configure DFSDM Audio clock source
+ * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
+ * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
+ * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
+ * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
+}
+
+/**
+ * @brief Configure DFSDM Kernel clock source
+ * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(SPDIFRX)
+/**
+ * @brief Configure SPDIFRX clock source
+ * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
+ * @param SPDIFRXxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
+{
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
+}
+#endif /* SPDIFRX */
+
+#if defined(FMPI2C1)
+/**
+ * @brief Get FMPI2C clock source
+ * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
+ * @param FMPI2Cx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
+}
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+/**
+ * @brief Get LPTIMx clock source
+ * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
+ * @param LPTIMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
+}
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/**
+ * @brief Get SAIx clock source
+ * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
+ * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
+ * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
+ * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
+ * @param SAIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
+}
+#endif /* SAI1 */
+
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+/**
+ * @brief Get SDIOx clock source
+ * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
+ * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
+ * @param SDIOx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDIO_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
+ * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
+{
+#if defined(RCC_DCKCFGR_SDIOSEL)
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
+#else
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
+#endif /* RCC_DCKCFGR_SDIOSEL */
+}
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/**
+ * @brief Get 48Mhz domain clock source
+ * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
+ * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
+ * @param CK48Mx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CK48M_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
+#else
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+
+#if defined(RNG)
+/**
+ * @brief Get RNGx clock source
+ * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
+ * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
+ * @param RNGx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
+#else
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/**
+ * @brief Get USBx clock source
+ * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
+ * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
+ * @param USBx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
+#else
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(CEC)
+/**
+ * @brief Get CEC Clock Source
+ * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
+ * @param CECx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
+}
+#endif /* CEC */
+
+/**
+ * @brief Get I2S Clock Source
+ * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
+ * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
+ * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
+ * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
+ * @param I2Sx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+#if defined(RCC_CFGR_I2SSRC)
+ return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
+#else
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
+#endif /* RCC_CFGR_I2SSRC */
+}
+
+#if defined(DFSDM1_Channel0)
+/**
+ * @brief Get DFSDM Audio Clock Source
+ * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
+ * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
+ * @param DFSDMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+ * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
+ * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
+ * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
+}
+
+/**
+ * @brief Get DFSDM Audio Clock Source
+ * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
+ * @param DFSDMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+ * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(SPDIFRX)
+/**
+ * @brief Get SPDIFRX clock source
+ * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
+ * @param SPDIFRXx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
+}
+#endif /* SPDIFRX */
+
+#if defined(DSI)
+/**
+ * @brief Get DSI Clock Source
+ * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
+ * @param DSIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
+}
+#endif /* DSI */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+ * @{
+ */
+
+/**
+ * @brief Set RTC Clock Source
+ * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+ * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+ * set). The BDRST bit can be used to reset them.
+ * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+ * @brief Get RTC Clock Source
+ * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+ * @brief Enable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Disable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Check if RTC has been enabled or not
+ * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+}
+
+/**
+ * @brief Force the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @brief Release the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @brief Set HSE Prescalers for RTC Clock
+ * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RTC_NOCLOCK
+ * @arg @ref LL_RCC_RTC_HSE_DIV_2
+ * @arg @ref LL_RCC_RTC_HSE_DIV_3
+ * @arg @ref LL_RCC_RTC_HSE_DIV_4
+ * @arg @ref LL_RCC_RTC_HSE_DIV_5
+ * @arg @ref LL_RCC_RTC_HSE_DIV_6
+ * @arg @ref LL_RCC_RTC_HSE_DIV_7
+ * @arg @ref LL_RCC_RTC_HSE_DIV_8
+ * @arg @ref LL_RCC_RTC_HSE_DIV_9
+ * @arg @ref LL_RCC_RTC_HSE_DIV_10
+ * @arg @ref LL_RCC_RTC_HSE_DIV_11
+ * @arg @ref LL_RCC_RTC_HSE_DIV_12
+ * @arg @ref LL_RCC_RTC_HSE_DIV_13
+ * @arg @ref LL_RCC_RTC_HSE_DIV_14
+ * @arg @ref LL_RCC_RTC_HSE_DIV_15
+ * @arg @ref LL_RCC_RTC_HSE_DIV_16
+ * @arg @ref LL_RCC_RTC_HSE_DIV_17
+ * @arg @ref LL_RCC_RTC_HSE_DIV_18
+ * @arg @ref LL_RCC_RTC_HSE_DIV_19
+ * @arg @ref LL_RCC_RTC_HSE_DIV_20
+ * @arg @ref LL_RCC_RTC_HSE_DIV_21
+ * @arg @ref LL_RCC_RTC_HSE_DIV_22
+ * @arg @ref LL_RCC_RTC_HSE_DIV_23
+ * @arg @ref LL_RCC_RTC_HSE_DIV_24
+ * @arg @ref LL_RCC_RTC_HSE_DIV_25
+ * @arg @ref LL_RCC_RTC_HSE_DIV_26
+ * @arg @ref LL_RCC_RTC_HSE_DIV_27
+ * @arg @ref LL_RCC_RTC_HSE_DIV_28
+ * @arg @ref LL_RCC_RTC_HSE_DIV_29
+ * @arg @ref LL_RCC_RTC_HSE_DIV_30
+ * @arg @ref LL_RCC_RTC_HSE_DIV_31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
+}
+
+/**
+ * @brief Get HSE Prescalers for RTC Clock
+ * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RTC_NOCLOCK
+ * @arg @ref LL_RCC_RTC_HSE_DIV_2
+ * @arg @ref LL_RCC_RTC_HSE_DIV_3
+ * @arg @ref LL_RCC_RTC_HSE_DIV_4
+ * @arg @ref LL_RCC_RTC_HSE_DIV_5
+ * @arg @ref LL_RCC_RTC_HSE_DIV_6
+ * @arg @ref LL_RCC_RTC_HSE_DIV_7
+ * @arg @ref LL_RCC_RTC_HSE_DIV_8
+ * @arg @ref LL_RCC_RTC_HSE_DIV_9
+ * @arg @ref LL_RCC_RTC_HSE_DIV_10
+ * @arg @ref LL_RCC_RTC_HSE_DIV_11
+ * @arg @ref LL_RCC_RTC_HSE_DIV_12
+ * @arg @ref LL_RCC_RTC_HSE_DIV_13
+ * @arg @ref LL_RCC_RTC_HSE_DIV_14
+ * @arg @ref LL_RCC_RTC_HSE_DIV_15
+ * @arg @ref LL_RCC_RTC_HSE_DIV_16
+ * @arg @ref LL_RCC_RTC_HSE_DIV_17
+ * @arg @ref LL_RCC_RTC_HSE_DIV_18
+ * @arg @ref LL_RCC_RTC_HSE_DIV_19
+ * @arg @ref LL_RCC_RTC_HSE_DIV_20
+ * @arg @ref LL_RCC_RTC_HSE_DIV_21
+ * @arg @ref LL_RCC_RTC_HSE_DIV_22
+ * @arg @ref LL_RCC_RTC_HSE_DIV_23
+ * @arg @ref LL_RCC_RTC_HSE_DIV_24
+ * @arg @ref LL_RCC_RTC_HSE_DIV_25
+ * @arg @ref LL_RCC_RTC_HSE_DIV_26
+ * @arg @ref LL_RCC_RTC_HSE_DIV_27
+ * @arg @ref LL_RCC_RTC_HSE_DIV_28
+ * @arg @ref LL_RCC_RTC_HSE_DIV_29
+ * @arg @ref LL_RCC_RTC_HSE_DIV_30
+ * @arg @ref LL_RCC_RTC_HSE_DIV_31
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(RCC_DCKCFGR_TIMPRE)
+/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+ * @{
+ */
+
+/**
+ * @brief Set Timers Clock Prescalers
+ * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+ * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
+}
+
+/**
+ * @brief Get Timers Clock Prescalers
+ * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+ * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_DCKCFGR_TIMPRE */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+ * @{
+ */
+
+/**
+ * @brief Enable PLL
+ * @rmtoll CR PLLON LL_RCC_PLL_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Disable PLL
+ * @note Cannot be disabled if the PLL clock is used as the system clock
+ * @rmtoll CR PLLON LL_RCC_PLL_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Check if PLL Ready
+ * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+/**
+ * @brief Configure PLL used for SYSCLK Domain
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI(*) are disabled
+ * @note PLLN/PLLP can be written only when PLL is disabled
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param PLLN Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param PLLP_R This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ * @arg @ref LL_RCC_PLLR_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLR_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLR_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLR_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLR_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLR_DIV_7 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
+ Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+}
+
+/**
+ * @brief Configure PLL used for 48Mhz domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI(*) are disabled
+ * @note PLLN/PLLQ can be written only when PLL is disabled
+ * @note This can be selected for USB, RNG, SDIO
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
+ * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param PLLN Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLQ_DIV_2
+ * @arg @ref LL_RCC_PLLQ_DIV_3
+ * @arg @ref LL_RCC_PLLQ_DIV_4
+ * @arg @ref LL_RCC_PLLQ_DIV_5
+ * @arg @ref LL_RCC_PLLQ_DIV_6
+ * @arg @ref LL_RCC_PLLQ_DIV_7
+ * @arg @ref LL_RCC_PLLQ_DIV_8
+ * @arg @ref LL_RCC_PLLQ_DIV_9
+ * @arg @ref LL_RCC_PLLQ_DIV_10
+ * @arg @ref LL_RCC_PLLQ_DIV_11
+ * @arg @ref LL_RCC_PLLQ_DIV_12
+ * @arg @ref LL_RCC_PLLQ_DIV_13
+ * @arg @ref LL_RCC_PLLQ_DIV_14
+ * @arg @ref LL_RCC_PLLQ_DIV_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
+ Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
+}
+
+#if defined(DSI)
+/**
+ * @brief Configure PLL used for DSI clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI are disabled
+ * @note PLLN/PLLR can be written only when PLL is disabled
+ * @note This can be selected for DSI
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
+ * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param PLLN Between 50 and 432
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+ Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* DSI */
+
+#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
+/**
+ * @brief Configure PLL used for I2S clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI are disabled
+ * @note PLLN/PLLR can be written only when PLL is disabled
+ * @note This can be selected for I2S
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
+ * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param PLLN Between 50 and 432
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+ Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
+
+#if defined(SPDIFRX)
+/**
+ * @brief Configure PLL used for SPDIFRX clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI are disabled
+ * @note PLLN/PLLR can be written only when PLL is disabled
+ * @note This can be selected for SPDIFRX
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
+ * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param PLLN Between 50 and 432
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+ Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* SPDIFRX */
+
+#if defined(RCC_PLLCFGR_PLLR)
+#if defined(SAI1)
+/**
+ * @brief Configure PLL used for SAI clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI are disabled
+ * @note PLLN/PLLR can be written only when PLL is disabled
+ * @note This can be selected for SAI
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
+ * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
+ * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ * @param PLLN Between 50 and 432
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ * @param PLLDIVR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
+ * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+#if defined(RCC_DCKCFGR_PLLDIVR)
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
+#else
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+#endif /* RCC_DCKCFGR_PLLDIVR */
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+ Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+#if defined(RCC_DCKCFGR_PLLDIVR)
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
+#endif /* RCC_DCKCFGR_PLLDIVR */
+}
+#endif /* SAI1 */
+#endif /* RCC_PLLCFGR_PLLR */
+
+/**
+ * @brief Configure PLL clock source
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
+ * @param PLLSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
+ * @brief Get Main PLL multiplication factor for VCO
+ * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
+ * @retval Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+}
+
+/**
+ * @brief Get Main PLL division factor for PLLP
+ * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
+}
+
+/**
+ * @brief Get Main PLL division factor for PLLQ
+ * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
+ * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLQ_DIV_2
+ * @arg @ref LL_RCC_PLLQ_DIV_3
+ * @arg @ref LL_RCC_PLLQ_DIV_4
+ * @arg @ref LL_RCC_PLLQ_DIV_5
+ * @arg @ref LL_RCC_PLLQ_DIV_6
+ * @arg @ref LL_RCC_PLLQ_DIV_7
+ * @arg @ref LL_RCC_PLLQ_DIV_8
+ * @arg @ref LL_RCC_PLLQ_DIV_9
+ * @arg @ref LL_RCC_PLLQ_DIV_10
+ * @arg @ref LL_RCC_PLLQ_DIV_11
+ * @arg @ref LL_RCC_PLLQ_DIV_12
+ * @arg @ref LL_RCC_PLLQ_DIV_13
+ * @arg @ref LL_RCC_PLLQ_DIV_14
+ * @arg @ref LL_RCC_PLLQ_DIV_15
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+}
+
+#if defined(RCC_PLLCFGR_PLLR)
+/**
+ * @brief Get Main PLL division factor for PLLR
+ * @note used for PLLCLK (system clock)
+ * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_3
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_5
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_7
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+}
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_DCKCFGR_PLLDIVR)
+/**
+ * @brief Get Main PLL division factor for PLLDIVR
+ * @note used for PLLSAICLK (SAI1 and SAI2 clock)
+ * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLDIVR_DIV_1
+ * @arg @ref LL_RCC_PLLDIVR_DIV_2
+ * @arg @ref LL_RCC_PLLDIVR_DIV_3
+ * @arg @ref LL_RCC_PLLDIVR_DIV_4
+ * @arg @ref LL_RCC_PLLDIVR_DIV_5
+ * @arg @ref LL_RCC_PLLDIVR_DIV_6
+ * @arg @ref LL_RCC_PLLDIVR_DIV_7
+ * @arg @ref LL_RCC_PLLDIVR_DIV_8
+ * @arg @ref LL_RCC_PLLDIVR_DIV_9
+ * @arg @ref LL_RCC_PLLDIVR_DIV_10
+ * @arg @ref LL_RCC_PLLDIVR_DIV_11
+ * @arg @ref LL_RCC_PLLDIVR_DIV_12
+ * @arg @ref LL_RCC_PLLDIVR_DIV_13
+ * @arg @ref LL_RCC_PLLDIVR_DIV_14
+ * @arg @ref LL_RCC_PLLDIVR_DIV_15
+ * @arg @ref LL_RCC_PLLDIVR_DIV_16
+ * @arg @ref LL_RCC_PLLDIVR_DIV_17
+ * @arg @ref LL_RCC_PLLDIVR_DIV_18
+ * @arg @ref LL_RCC_PLLDIVR_DIV_19
+ * @arg @ref LL_RCC_PLLDIVR_DIV_20
+ * @arg @ref LL_RCC_PLLDIVR_DIV_21
+ * @arg @ref LL_RCC_PLLDIVR_DIV_22
+ * @arg @ref LL_RCC_PLLDIVR_DIV_23
+ * @arg @ref LL_RCC_PLLDIVR_DIV_24
+ * @arg @ref LL_RCC_PLLDIVR_DIV_25
+ * @arg @ref LL_RCC_PLLDIVR_DIV_26
+ * @arg @ref LL_RCC_PLLDIVR_DIV_27
+ * @arg @ref LL_RCC_PLLDIVR_DIV_28
+ * @arg @ref LL_RCC_PLLDIVR_DIV_29
+ * @arg @ref LL_RCC_PLLDIVR_DIV_30
+ * @arg @ref LL_RCC_PLLDIVR_DIV_31
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
+}
+#endif /* RCC_DCKCFGR_PLLDIVR */
+
+/**
+ * @brief Get Division factor for the main PLL and other PLL
+ * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9
+ * @arg @ref LL_RCC_PLLM_DIV_10
+ * @arg @ref LL_RCC_PLLM_DIV_11
+ * @arg @ref LL_RCC_PLLM_DIV_12
+ * @arg @ref LL_RCC_PLLM_DIV_13
+ * @arg @ref LL_RCC_PLLM_DIV_14
+ * @arg @ref LL_RCC_PLLM_DIV_15
+ * @arg @ref LL_RCC_PLLM_DIV_16
+ * @arg @ref LL_RCC_PLLM_DIV_17
+ * @arg @ref LL_RCC_PLLM_DIV_18
+ * @arg @ref LL_RCC_PLLM_DIV_19
+ * @arg @ref LL_RCC_PLLM_DIV_20
+ * @arg @ref LL_RCC_PLLM_DIV_21
+ * @arg @ref LL_RCC_PLLM_DIV_22
+ * @arg @ref LL_RCC_PLLM_DIV_23
+ * @arg @ref LL_RCC_PLLM_DIV_24
+ * @arg @ref LL_RCC_PLLM_DIV_25
+ * @arg @ref LL_RCC_PLLM_DIV_26
+ * @arg @ref LL_RCC_PLLM_DIV_27
+ * @arg @ref LL_RCC_PLLM_DIV_28
+ * @arg @ref LL_RCC_PLLM_DIV_29
+ * @arg @ref LL_RCC_PLLM_DIV_30
+ * @arg @ref LL_RCC_PLLM_DIV_31
+ * @arg @ref LL_RCC_PLLM_DIV_32
+ * @arg @ref LL_RCC_PLLM_DIV_33
+ * @arg @ref LL_RCC_PLLM_DIV_34
+ * @arg @ref LL_RCC_PLLM_DIV_35
+ * @arg @ref LL_RCC_PLLM_DIV_36
+ * @arg @ref LL_RCC_PLLM_DIV_37
+ * @arg @ref LL_RCC_PLLM_DIV_38
+ * @arg @ref LL_RCC_PLLM_DIV_39
+ * @arg @ref LL_RCC_PLLM_DIV_40
+ * @arg @ref LL_RCC_PLLM_DIV_41
+ * @arg @ref LL_RCC_PLLM_DIV_42
+ * @arg @ref LL_RCC_PLLM_DIV_43
+ * @arg @ref LL_RCC_PLLM_DIV_44
+ * @arg @ref LL_RCC_PLLM_DIV_45
+ * @arg @ref LL_RCC_PLLM_DIV_46
+ * @arg @ref LL_RCC_PLLM_DIV_47
+ * @arg @ref LL_RCC_PLLM_DIV_48
+ * @arg @ref LL_RCC_PLLM_DIV_49
+ * @arg @ref LL_RCC_PLLM_DIV_50
+ * @arg @ref LL_RCC_PLLM_DIV_51
+ * @arg @ref LL_RCC_PLLM_DIV_52
+ * @arg @ref LL_RCC_PLLM_DIV_53
+ * @arg @ref LL_RCC_PLLM_DIV_54
+ * @arg @ref LL_RCC_PLLM_DIV_55
+ * @arg @ref LL_RCC_PLLM_DIV_56
+ * @arg @ref LL_RCC_PLLM_DIV_57
+ * @arg @ref LL_RCC_PLLM_DIV_58
+ * @arg @ref LL_RCC_PLLM_DIV_59
+ * @arg @ref LL_RCC_PLLM_DIV_60
+ * @arg @ref LL_RCC_PLLM_DIV_61
+ * @arg @ref LL_RCC_PLLM_DIV_62
+ * @arg @ref LL_RCC_PLLM_DIV_63
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+}
+
+/**
+ * @brief Configure Spread Spectrum used for PLL
+ * @note These bits must be written before enabling PLL
+ * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
+ * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
+ * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
+ * @param Mod Between Min_Data=0 and Max_Data=8191
+ * @param Inc Between Min_Data=0 and Max_Data=32767
+ * @param Sel This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+ * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
+{
+ MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
+}
+
+/**
+ * @brief Get Spread Spectrum Modulation Period for PLL
+ * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
+ * @retval Between Min_Data=0 and Max_Data=8191
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
+{
+ return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
+}
+
+/**
+ * @brief Get Spread Spectrum Incrementation Step for PLL
+ * @note Must be written before enabling PLL
+ * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
+ * @retval Between Min_Data=0 and Max_Data=32767
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
+{
+ return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
+}
+
+/**
+ * @brief Get Spread Spectrum Selection for PLL
+ * @note Must be written before enabling PLL
+ * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+ * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
+{
+ return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
+}
+
+/**
+ * @brief Enable Spread Spectrum for PLL.
+ * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
+{
+ SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+}
+
+/**
+ * @brief Disable Spread Spectrum for PLL.
+ * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
+{
+ CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+}
+
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
+ * @{
+ */
+
+/**
+ * @brief Enable PLLI2S
+ * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
+}
+
+/**
+ * @brief Disable PLLI2S
+ * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+}
+
+/**
+ * @brief Check if PLLI2S Ready
+ * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
+}
+
+#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
+/**
+ * @brief Configure PLLI2S used for SAI domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI(*) are disabled
+ * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
+ * @note This can be selected for SAI
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
+ * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
+ * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
+ * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
+ * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
+ * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
+ * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
+ * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+ *
+ * (*) value not defined in all devices.
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SM_DIV_2
+ * @arg @ref LL_RCC_PLLI2SM_DIV_3
+ * @arg @ref LL_RCC_PLLI2SM_DIV_4
+ * @arg @ref LL_RCC_PLLI2SM_DIV_5
+ * @arg @ref LL_RCC_PLLI2SM_DIV_6
+ * @arg @ref LL_RCC_PLLI2SM_DIV_7
+ * @arg @ref LL_RCC_PLLI2SM_DIV_8
+ * @arg @ref LL_RCC_PLLI2SM_DIV_9
+ * @arg @ref LL_RCC_PLLI2SM_DIV_10
+ * @arg @ref LL_RCC_PLLI2SM_DIV_11
+ * @arg @ref LL_RCC_PLLI2SM_DIV_12
+ * @arg @ref LL_RCC_PLLI2SM_DIV_13
+ * @arg @ref LL_RCC_PLLI2SM_DIV_14
+ * @arg @ref LL_RCC_PLLI2SM_DIV_15
+ * @arg @ref LL_RCC_PLLI2SM_DIV_16
+ * @arg @ref LL_RCC_PLLI2SM_DIV_17
+ * @arg @ref LL_RCC_PLLI2SM_DIV_18
+ * @arg @ref LL_RCC_PLLI2SM_DIV_19
+ * @arg @ref LL_RCC_PLLI2SM_DIV_20
+ * @arg @ref LL_RCC_PLLI2SM_DIV_21
+ * @arg @ref LL_RCC_PLLI2SM_DIV_22
+ * @arg @ref LL_RCC_PLLI2SM_DIV_23
+ * @arg @ref LL_RCC_PLLI2SM_DIV_24
+ * @arg @ref LL_RCC_PLLI2SM_DIV_25
+ * @arg @ref LL_RCC_PLLI2SM_DIV_26
+ * @arg @ref LL_RCC_PLLI2SM_DIV_27
+ * @arg @ref LL_RCC_PLLI2SM_DIV_28
+ * @arg @ref LL_RCC_PLLI2SM_DIV_29
+ * @arg @ref LL_RCC_PLLI2SM_DIV_30
+ * @arg @ref LL_RCC_PLLI2SM_DIV_31
+ * @arg @ref LL_RCC_PLLI2SM_DIV_32
+ * @arg @ref LL_RCC_PLLI2SM_DIV_33
+ * @arg @ref LL_RCC_PLLI2SM_DIV_34
+ * @arg @ref LL_RCC_PLLI2SM_DIV_35
+ * @arg @ref LL_RCC_PLLI2SM_DIV_36
+ * @arg @ref LL_RCC_PLLI2SM_DIV_37
+ * @arg @ref LL_RCC_PLLI2SM_DIV_38
+ * @arg @ref LL_RCC_PLLI2SM_DIV_39
+ * @arg @ref LL_RCC_PLLI2SM_DIV_40
+ * @arg @ref LL_RCC_PLLI2SM_DIV_41
+ * @arg @ref LL_RCC_PLLI2SM_DIV_42
+ * @arg @ref LL_RCC_PLLI2SM_DIV_43
+ * @arg @ref LL_RCC_PLLI2SM_DIV_44
+ * @arg @ref LL_RCC_PLLI2SM_DIV_45
+ * @arg @ref LL_RCC_PLLI2SM_DIV_46
+ * @arg @ref LL_RCC_PLLI2SM_DIV_47
+ * @arg @ref LL_RCC_PLLI2SM_DIV_48
+ * @arg @ref LL_RCC_PLLI2SM_DIV_49
+ * @arg @ref LL_RCC_PLLI2SM_DIV_50
+ * @arg @ref LL_RCC_PLLI2SM_DIV_51
+ * @arg @ref LL_RCC_PLLI2SM_DIV_52
+ * @arg @ref LL_RCC_PLLI2SM_DIV_53
+ * @arg @ref LL_RCC_PLLI2SM_DIV_54
+ * @arg @ref LL_RCC_PLLI2SM_DIV_55
+ * @arg @ref LL_RCC_PLLI2SM_DIV_56
+ * @arg @ref LL_RCC_PLLI2SM_DIV_57
+ * @arg @ref LL_RCC_PLLI2SM_DIV_58
+ * @arg @ref LL_RCC_PLLI2SM_DIV_59
+ * @arg @ref LL_RCC_PLLI2SM_DIV_60
+ * @arg @ref LL_RCC_PLLI2SM_DIV_61
+ * @arg @ref LL_RCC_PLLI2SM_DIV_62
+ * @arg @ref LL_RCC_PLLI2SM_DIV_63
+ * @param PLLN Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param PLLQ_R This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param PLLDIVQ_R This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+ MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
+#else
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+}
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+ * @brief Configure PLLI2S used for 48Mhz domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI(*) are disabled
+ * @note PLLN/PLLQ can be written only when PLLI2S is disabled
+ * @note This can be selected for RNG, USB, SDIO
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
+ * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
+ * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
+ * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
+ * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
+ * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+ *
+ * (*) value not defined in all devices.
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SM_DIV_2
+ * @arg @ref LL_RCC_PLLI2SM_DIV_3
+ * @arg @ref LL_RCC_PLLI2SM_DIV_4
+ * @arg @ref LL_RCC_PLLI2SM_DIV_5
+ * @arg @ref LL_RCC_PLLI2SM_DIV_6
+ * @arg @ref LL_RCC_PLLI2SM_DIV_7
+ * @arg @ref LL_RCC_PLLI2SM_DIV_8
+ * @arg @ref LL_RCC_PLLI2SM_DIV_9
+ * @arg @ref LL_RCC_PLLI2SM_DIV_10
+ * @arg @ref LL_RCC_PLLI2SM_DIV_11
+ * @arg @ref LL_RCC_PLLI2SM_DIV_12
+ * @arg @ref LL_RCC_PLLI2SM_DIV_13
+ * @arg @ref LL_RCC_PLLI2SM_DIV_14
+ * @arg @ref LL_RCC_PLLI2SM_DIV_15
+ * @arg @ref LL_RCC_PLLI2SM_DIV_16
+ * @arg @ref LL_RCC_PLLI2SM_DIV_17
+ * @arg @ref LL_RCC_PLLI2SM_DIV_18
+ * @arg @ref LL_RCC_PLLI2SM_DIV_19
+ * @arg @ref LL_RCC_PLLI2SM_DIV_20
+ * @arg @ref LL_RCC_PLLI2SM_DIV_21
+ * @arg @ref LL_RCC_PLLI2SM_DIV_22
+ * @arg @ref LL_RCC_PLLI2SM_DIV_23
+ * @arg @ref LL_RCC_PLLI2SM_DIV_24
+ * @arg @ref LL_RCC_PLLI2SM_DIV_25
+ * @arg @ref LL_RCC_PLLI2SM_DIV_26
+ * @arg @ref LL_RCC_PLLI2SM_DIV_27
+ * @arg @ref LL_RCC_PLLI2SM_DIV_28
+ * @arg @ref LL_RCC_PLLI2SM_DIV_29
+ * @arg @ref LL_RCC_PLLI2SM_DIV_30
+ * @arg @ref LL_RCC_PLLI2SM_DIV_31
+ * @arg @ref LL_RCC_PLLI2SM_DIV_32
+ * @arg @ref LL_RCC_PLLI2SM_DIV_33
+ * @arg @ref LL_RCC_PLLI2SM_DIV_34
+ * @arg @ref LL_RCC_PLLI2SM_DIV_35
+ * @arg @ref LL_RCC_PLLI2SM_DIV_36
+ * @arg @ref LL_RCC_PLLI2SM_DIV_37
+ * @arg @ref LL_RCC_PLLI2SM_DIV_38
+ * @arg @ref LL_RCC_PLLI2SM_DIV_39
+ * @arg @ref LL_RCC_PLLI2SM_DIV_40
+ * @arg @ref LL_RCC_PLLI2SM_DIV_41
+ * @arg @ref LL_RCC_PLLI2SM_DIV_42
+ * @arg @ref LL_RCC_PLLI2SM_DIV_43
+ * @arg @ref LL_RCC_PLLI2SM_DIV_44
+ * @arg @ref LL_RCC_PLLI2SM_DIV_45
+ * @arg @ref LL_RCC_PLLI2SM_DIV_46
+ * @arg @ref LL_RCC_PLLI2SM_DIV_47
+ * @arg @ref LL_RCC_PLLI2SM_DIV_48
+ * @arg @ref LL_RCC_PLLI2SM_DIV_49
+ * @arg @ref LL_RCC_PLLI2SM_DIV_50
+ * @arg @ref LL_RCC_PLLI2SM_DIV_51
+ * @arg @ref LL_RCC_PLLI2SM_DIV_52
+ * @arg @ref LL_RCC_PLLI2SM_DIV_53
+ * @arg @ref LL_RCC_PLLI2SM_DIV_54
+ * @arg @ref LL_RCC_PLLI2SM_DIV_55
+ * @arg @ref LL_RCC_PLLI2SM_DIV_56
+ * @arg @ref LL_RCC_PLLI2SM_DIV_57
+ * @arg @ref LL_RCC_PLLI2SM_DIV_58
+ * @arg @ref LL_RCC_PLLI2SM_DIV_59
+ * @arg @ref LL_RCC_PLLI2SM_DIV_60
+ * @arg @ref LL_RCC_PLLI2SM_DIV_61
+ * @arg @ref LL_RCC_PLLI2SM_DIV_62
+ * @arg @ref LL_RCC_PLLI2SM_DIV_63
+ * @param PLLN Between 50 and 432
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_2
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_3
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_4
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_5
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_6
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_7
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_8
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_9
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_10
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_11
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_12
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_13
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_14
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+ MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(SPDIFRX)
+/**
+ * @brief Configure PLLI2S used for SPDIFRX domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI(*) are disabled
+ * @note PLLN/PLLP can be written only when PLLI2S is disabled
+ * @note This can be selected for SPDIFRX
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+ * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+ * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+ * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+ * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SM_DIV_2
+ * @arg @ref LL_RCC_PLLI2SM_DIV_3
+ * @arg @ref LL_RCC_PLLI2SM_DIV_4
+ * @arg @ref LL_RCC_PLLI2SM_DIV_5
+ * @arg @ref LL_RCC_PLLI2SM_DIV_6
+ * @arg @ref LL_RCC_PLLI2SM_DIV_7
+ * @arg @ref LL_RCC_PLLI2SM_DIV_8
+ * @arg @ref LL_RCC_PLLI2SM_DIV_9
+ * @arg @ref LL_RCC_PLLI2SM_DIV_10
+ * @arg @ref LL_RCC_PLLI2SM_DIV_11
+ * @arg @ref LL_RCC_PLLI2SM_DIV_12
+ * @arg @ref LL_RCC_PLLI2SM_DIV_13
+ * @arg @ref LL_RCC_PLLI2SM_DIV_14
+ * @arg @ref LL_RCC_PLLI2SM_DIV_15
+ * @arg @ref LL_RCC_PLLI2SM_DIV_16
+ * @arg @ref LL_RCC_PLLI2SM_DIV_17
+ * @arg @ref LL_RCC_PLLI2SM_DIV_18
+ * @arg @ref LL_RCC_PLLI2SM_DIV_19
+ * @arg @ref LL_RCC_PLLI2SM_DIV_20
+ * @arg @ref LL_RCC_PLLI2SM_DIV_21
+ * @arg @ref LL_RCC_PLLI2SM_DIV_22
+ * @arg @ref LL_RCC_PLLI2SM_DIV_23
+ * @arg @ref LL_RCC_PLLI2SM_DIV_24
+ * @arg @ref LL_RCC_PLLI2SM_DIV_25
+ * @arg @ref LL_RCC_PLLI2SM_DIV_26
+ * @arg @ref LL_RCC_PLLI2SM_DIV_27
+ * @arg @ref LL_RCC_PLLI2SM_DIV_28
+ * @arg @ref LL_RCC_PLLI2SM_DIV_29
+ * @arg @ref LL_RCC_PLLI2SM_DIV_30
+ * @arg @ref LL_RCC_PLLI2SM_DIV_31
+ * @arg @ref LL_RCC_PLLI2SM_DIV_32
+ * @arg @ref LL_RCC_PLLI2SM_DIV_33
+ * @arg @ref LL_RCC_PLLI2SM_DIV_34
+ * @arg @ref LL_RCC_PLLI2SM_DIV_35
+ * @arg @ref LL_RCC_PLLI2SM_DIV_36
+ * @arg @ref LL_RCC_PLLI2SM_DIV_37
+ * @arg @ref LL_RCC_PLLI2SM_DIV_38
+ * @arg @ref LL_RCC_PLLI2SM_DIV_39
+ * @arg @ref LL_RCC_PLLI2SM_DIV_40
+ * @arg @ref LL_RCC_PLLI2SM_DIV_41
+ * @arg @ref LL_RCC_PLLI2SM_DIV_42
+ * @arg @ref LL_RCC_PLLI2SM_DIV_43
+ * @arg @ref LL_RCC_PLLI2SM_DIV_44
+ * @arg @ref LL_RCC_PLLI2SM_DIV_45
+ * @arg @ref LL_RCC_PLLI2SM_DIV_46
+ * @arg @ref LL_RCC_PLLI2SM_DIV_47
+ * @arg @ref LL_RCC_PLLI2SM_DIV_48
+ * @arg @ref LL_RCC_PLLI2SM_DIV_49
+ * @arg @ref LL_RCC_PLLI2SM_DIV_50
+ * @arg @ref LL_RCC_PLLI2SM_DIV_51
+ * @arg @ref LL_RCC_PLLI2SM_DIV_52
+ * @arg @ref LL_RCC_PLLI2SM_DIV_53
+ * @arg @ref LL_RCC_PLLI2SM_DIV_54
+ * @arg @ref LL_RCC_PLLI2SM_DIV_55
+ * @arg @ref LL_RCC_PLLI2SM_DIV_56
+ * @arg @ref LL_RCC_PLLI2SM_DIV_57
+ * @arg @ref LL_RCC_PLLI2SM_DIV_58
+ * @arg @ref LL_RCC_PLLI2SM_DIV_59
+ * @arg @ref LL_RCC_PLLI2SM_DIV_60
+ * @arg @ref LL_RCC_PLLI2SM_DIV_61
+ * @arg @ref LL_RCC_PLLI2SM_DIV_62
+ * @arg @ref LL_RCC_PLLI2SM_DIV_63
+ * @param PLLN Between 50 and 432
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SP_DIV_2
+ * @arg @ref LL_RCC_PLLI2SP_DIV_4
+ * @arg @ref LL_RCC_PLLI2SP_DIV_6
+ * @arg @ref LL_RCC_PLLI2SP_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
+}
+#endif /* SPDIFRX */
+
+/**
+ * @brief Configure PLLI2S used for I2S1 domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI(*) are disabled
+ * @note PLLN/PLLR can be written only when PLLI2S is disabled
+ * @note This can be selected for I2S
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
+ * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
+ * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
+ * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
+ * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
+ * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+ *
+ * (*) value not defined in all devices.
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SM_DIV_2
+ * @arg @ref LL_RCC_PLLI2SM_DIV_3
+ * @arg @ref LL_RCC_PLLI2SM_DIV_4
+ * @arg @ref LL_RCC_PLLI2SM_DIV_5
+ * @arg @ref LL_RCC_PLLI2SM_DIV_6
+ * @arg @ref LL_RCC_PLLI2SM_DIV_7
+ * @arg @ref LL_RCC_PLLI2SM_DIV_8
+ * @arg @ref LL_RCC_PLLI2SM_DIV_9
+ * @arg @ref LL_RCC_PLLI2SM_DIV_10
+ * @arg @ref LL_RCC_PLLI2SM_DIV_11
+ * @arg @ref LL_RCC_PLLI2SM_DIV_12
+ * @arg @ref LL_RCC_PLLI2SM_DIV_13
+ * @arg @ref LL_RCC_PLLI2SM_DIV_14
+ * @arg @ref LL_RCC_PLLI2SM_DIV_15
+ * @arg @ref LL_RCC_PLLI2SM_DIV_16
+ * @arg @ref LL_RCC_PLLI2SM_DIV_17
+ * @arg @ref LL_RCC_PLLI2SM_DIV_18
+ * @arg @ref LL_RCC_PLLI2SM_DIV_19
+ * @arg @ref LL_RCC_PLLI2SM_DIV_20
+ * @arg @ref LL_RCC_PLLI2SM_DIV_21
+ * @arg @ref LL_RCC_PLLI2SM_DIV_22
+ * @arg @ref LL_RCC_PLLI2SM_DIV_23
+ * @arg @ref LL_RCC_PLLI2SM_DIV_24
+ * @arg @ref LL_RCC_PLLI2SM_DIV_25
+ * @arg @ref LL_RCC_PLLI2SM_DIV_26
+ * @arg @ref LL_RCC_PLLI2SM_DIV_27
+ * @arg @ref LL_RCC_PLLI2SM_DIV_28
+ * @arg @ref LL_RCC_PLLI2SM_DIV_29
+ * @arg @ref LL_RCC_PLLI2SM_DIV_30
+ * @arg @ref LL_RCC_PLLI2SM_DIV_31
+ * @arg @ref LL_RCC_PLLI2SM_DIV_32
+ * @arg @ref LL_RCC_PLLI2SM_DIV_33
+ * @arg @ref LL_RCC_PLLI2SM_DIV_34
+ * @arg @ref LL_RCC_PLLI2SM_DIV_35
+ * @arg @ref LL_RCC_PLLI2SM_DIV_36
+ * @arg @ref LL_RCC_PLLI2SM_DIV_37
+ * @arg @ref LL_RCC_PLLI2SM_DIV_38
+ * @arg @ref LL_RCC_PLLI2SM_DIV_39
+ * @arg @ref LL_RCC_PLLI2SM_DIV_40
+ * @arg @ref LL_RCC_PLLI2SM_DIV_41
+ * @arg @ref LL_RCC_PLLI2SM_DIV_42
+ * @arg @ref LL_RCC_PLLI2SM_DIV_43
+ * @arg @ref LL_RCC_PLLI2SM_DIV_44
+ * @arg @ref LL_RCC_PLLI2SM_DIV_45
+ * @arg @ref LL_RCC_PLLI2SM_DIV_46
+ * @arg @ref LL_RCC_PLLI2SM_DIV_47
+ * @arg @ref LL_RCC_PLLI2SM_DIV_48
+ * @arg @ref LL_RCC_PLLI2SM_DIV_49
+ * @arg @ref LL_RCC_PLLI2SM_DIV_50
+ * @arg @ref LL_RCC_PLLI2SM_DIV_51
+ * @arg @ref LL_RCC_PLLI2SM_DIV_52
+ * @arg @ref LL_RCC_PLLI2SM_DIV_53
+ * @arg @ref LL_RCC_PLLI2SM_DIV_54
+ * @arg @ref LL_RCC_PLLI2SM_DIV_55
+ * @arg @ref LL_RCC_PLLI2SM_DIV_56
+ * @arg @ref LL_RCC_PLLI2SM_DIV_57
+ * @arg @ref LL_RCC_PLLI2SM_DIV_58
+ * @arg @ref LL_RCC_PLLI2SM_DIV_59
+ * @arg @ref LL_RCC_PLLI2SM_DIV_60
+ * @arg @ref LL_RCC_PLLI2SM_DIV_61
+ * @arg @ref LL_RCC_PLLI2SM_DIV_62
+ * @arg @ref LL_RCC_PLLI2SM_DIV_63
+ * @param PLLN Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SR_DIV_2
+ * @arg @ref LL_RCC_PLLI2SR_DIV_3
+ * @arg @ref LL_RCC_PLLI2SR_DIV_4
+ * @arg @ref LL_RCC_PLLI2SR_DIV_5
+ * @arg @ref LL_RCC_PLLI2SR_DIV_6
+ * @arg @ref LL_RCC_PLLI2SR_DIV_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+ MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+ MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
+}
+
+/**
+ * @brief Get I2SPLL multiplication factor for VCO
+ * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
+ * @retval Between 50/192(*) and 432
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+}
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+/**
+ * @brief Get I2SPLL division factor for PLLI2SQ
+ * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_2
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_3
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_4
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_5
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_6
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_7
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_8
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_9
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_10
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_11
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_12
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_13
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_14
+ * @arg @ref LL_RCC_PLLI2SQ_DIV_15
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+/**
+ * @brief Get I2SPLL division factor for PLLI2SR
+ * @note used for PLLI2SCLK (I2S clock)
+ * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SR_DIV_2
+ * @arg @ref LL_RCC_PLLI2SR_DIV_3
+ * @arg @ref LL_RCC_PLLI2SR_DIV_4
+ * @arg @ref LL_RCC_PLLI2SR_DIV_5
+ * @arg @ref LL_RCC_PLLI2SR_DIV_6
+ * @arg @ref LL_RCC_PLLI2SR_DIV_7
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
+}
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+/**
+ * @brief Get I2SPLL division factor for PLLI2SP
+ * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
+ * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SP_DIV_2
+ * @arg @ref LL_RCC_PLLI2SP_DIV_4
+ * @arg @ref LL_RCC_PLLI2SP_DIV_6
+ * @arg @ref LL_RCC_PLLI2SP_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+ * @brief Get I2SPLL division factor for PLLI2SDIVQ
+ * @note used PLLSAICLK selected (SAI clock)
+ * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+ * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
+}
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVR)
+/**
+ * @brief Get I2SPLL division factor for PLLI2SDIVR
+ * @note used PLLSAICLK selected (SAI clock)
+ * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
+ * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
+}
+#endif /* RCC_DCKCFGR_PLLI2SDIVR */
+
+/**
+ * @brief Get division factor for PLLI2S input clock
+ * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
+ * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2SM_DIV_2
+ * @arg @ref LL_RCC_PLLI2SM_DIV_3
+ * @arg @ref LL_RCC_PLLI2SM_DIV_4
+ * @arg @ref LL_RCC_PLLI2SM_DIV_5
+ * @arg @ref LL_RCC_PLLI2SM_DIV_6
+ * @arg @ref LL_RCC_PLLI2SM_DIV_7
+ * @arg @ref LL_RCC_PLLI2SM_DIV_8
+ * @arg @ref LL_RCC_PLLI2SM_DIV_9
+ * @arg @ref LL_RCC_PLLI2SM_DIV_10
+ * @arg @ref LL_RCC_PLLI2SM_DIV_11
+ * @arg @ref LL_RCC_PLLI2SM_DIV_12
+ * @arg @ref LL_RCC_PLLI2SM_DIV_13
+ * @arg @ref LL_RCC_PLLI2SM_DIV_14
+ * @arg @ref LL_RCC_PLLI2SM_DIV_15
+ * @arg @ref LL_RCC_PLLI2SM_DIV_16
+ * @arg @ref LL_RCC_PLLI2SM_DIV_17
+ * @arg @ref LL_RCC_PLLI2SM_DIV_18
+ * @arg @ref LL_RCC_PLLI2SM_DIV_19
+ * @arg @ref LL_RCC_PLLI2SM_DIV_20
+ * @arg @ref LL_RCC_PLLI2SM_DIV_21
+ * @arg @ref LL_RCC_PLLI2SM_DIV_22
+ * @arg @ref LL_RCC_PLLI2SM_DIV_23
+ * @arg @ref LL_RCC_PLLI2SM_DIV_24
+ * @arg @ref LL_RCC_PLLI2SM_DIV_25
+ * @arg @ref LL_RCC_PLLI2SM_DIV_26
+ * @arg @ref LL_RCC_PLLI2SM_DIV_27
+ * @arg @ref LL_RCC_PLLI2SM_DIV_28
+ * @arg @ref LL_RCC_PLLI2SM_DIV_29
+ * @arg @ref LL_RCC_PLLI2SM_DIV_30
+ * @arg @ref LL_RCC_PLLI2SM_DIV_31
+ * @arg @ref LL_RCC_PLLI2SM_DIV_32
+ * @arg @ref LL_RCC_PLLI2SM_DIV_33
+ * @arg @ref LL_RCC_PLLI2SM_DIV_34
+ * @arg @ref LL_RCC_PLLI2SM_DIV_35
+ * @arg @ref LL_RCC_PLLI2SM_DIV_36
+ * @arg @ref LL_RCC_PLLI2SM_DIV_37
+ * @arg @ref LL_RCC_PLLI2SM_DIV_38
+ * @arg @ref LL_RCC_PLLI2SM_DIV_39
+ * @arg @ref LL_RCC_PLLI2SM_DIV_40
+ * @arg @ref LL_RCC_PLLI2SM_DIV_41
+ * @arg @ref LL_RCC_PLLI2SM_DIV_42
+ * @arg @ref LL_RCC_PLLI2SM_DIV_43
+ * @arg @ref LL_RCC_PLLI2SM_DIV_44
+ * @arg @ref LL_RCC_PLLI2SM_DIV_45
+ * @arg @ref LL_RCC_PLLI2SM_DIV_46
+ * @arg @ref LL_RCC_PLLI2SM_DIV_47
+ * @arg @ref LL_RCC_PLLI2SM_DIV_48
+ * @arg @ref LL_RCC_PLLI2SM_DIV_49
+ * @arg @ref LL_RCC_PLLI2SM_DIV_50
+ * @arg @ref LL_RCC_PLLI2SM_DIV_51
+ * @arg @ref LL_RCC_PLLI2SM_DIV_52
+ * @arg @ref LL_RCC_PLLI2SM_DIV_53
+ * @arg @ref LL_RCC_PLLI2SM_DIV_54
+ * @arg @ref LL_RCC_PLLI2SM_DIV_55
+ * @arg @ref LL_RCC_PLLI2SM_DIV_56
+ * @arg @ref LL_RCC_PLLI2SM_DIV_57
+ * @arg @ref LL_RCC_PLLI2SM_DIV_58
+ * @arg @ref LL_RCC_PLLI2SM_DIV_59
+ * @arg @ref LL_RCC_PLLI2SM_DIV_60
+ * @arg @ref LL_RCC_PLLI2SM_DIV_61
+ * @arg @ref LL_RCC_PLLI2SM_DIV_62
+ * @arg @ref LL_RCC_PLLI2SM_DIV_63
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
+{
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+ return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
+#else
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+}
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
+ * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
+{
+#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
+ register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+ register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
+ register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
+ return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
+#else
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
+ * @{
+ */
+
+/**
+ * @brief Enable PLLSAI
+ * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLSAION);
+}
+
+/**
+ * @brief Disable PLLSAI
+ * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+}
+
+/**
+ * @brief Check if PLLSAI Ready
+ * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
+}
+
+/**
+ * @brief Configure PLLSAI used for SAI domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI(*) are disabled
+ * @note PLLN/PLLQ can be written only when PLLSAI is disabled
+ * @note This can be selected for SAI
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
+ * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
+ * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
+ * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
+ * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIM_DIV_2
+ * @arg @ref LL_RCC_PLLSAIM_DIV_3
+ * @arg @ref LL_RCC_PLLSAIM_DIV_4
+ * @arg @ref LL_RCC_PLLSAIM_DIV_5
+ * @arg @ref LL_RCC_PLLSAIM_DIV_6
+ * @arg @ref LL_RCC_PLLSAIM_DIV_7
+ * @arg @ref LL_RCC_PLLSAIM_DIV_8
+ * @arg @ref LL_RCC_PLLSAIM_DIV_9
+ * @arg @ref LL_RCC_PLLSAIM_DIV_10
+ * @arg @ref LL_RCC_PLLSAIM_DIV_11
+ * @arg @ref LL_RCC_PLLSAIM_DIV_12
+ * @arg @ref LL_RCC_PLLSAIM_DIV_13
+ * @arg @ref LL_RCC_PLLSAIM_DIV_14
+ * @arg @ref LL_RCC_PLLSAIM_DIV_15
+ * @arg @ref LL_RCC_PLLSAIM_DIV_16
+ * @arg @ref LL_RCC_PLLSAIM_DIV_17
+ * @arg @ref LL_RCC_PLLSAIM_DIV_18
+ * @arg @ref LL_RCC_PLLSAIM_DIV_19
+ * @arg @ref LL_RCC_PLLSAIM_DIV_20
+ * @arg @ref LL_RCC_PLLSAIM_DIV_21
+ * @arg @ref LL_RCC_PLLSAIM_DIV_22
+ * @arg @ref LL_RCC_PLLSAIM_DIV_23
+ * @arg @ref LL_RCC_PLLSAIM_DIV_24
+ * @arg @ref LL_RCC_PLLSAIM_DIV_25
+ * @arg @ref LL_RCC_PLLSAIM_DIV_26
+ * @arg @ref LL_RCC_PLLSAIM_DIV_27
+ * @arg @ref LL_RCC_PLLSAIM_DIV_28
+ * @arg @ref LL_RCC_PLLSAIM_DIV_29
+ * @arg @ref LL_RCC_PLLSAIM_DIV_30
+ * @arg @ref LL_RCC_PLLSAIM_DIV_31
+ * @arg @ref LL_RCC_PLLSAIM_DIV_32
+ * @arg @ref LL_RCC_PLLSAIM_DIV_33
+ * @arg @ref LL_RCC_PLLSAIM_DIV_34
+ * @arg @ref LL_RCC_PLLSAIM_DIV_35
+ * @arg @ref LL_RCC_PLLSAIM_DIV_36
+ * @arg @ref LL_RCC_PLLSAIM_DIV_37
+ * @arg @ref LL_RCC_PLLSAIM_DIV_38
+ * @arg @ref LL_RCC_PLLSAIM_DIV_39
+ * @arg @ref LL_RCC_PLLSAIM_DIV_40
+ * @arg @ref LL_RCC_PLLSAIM_DIV_41
+ * @arg @ref LL_RCC_PLLSAIM_DIV_42
+ * @arg @ref LL_RCC_PLLSAIM_DIV_43
+ * @arg @ref LL_RCC_PLLSAIM_DIV_44
+ * @arg @ref LL_RCC_PLLSAIM_DIV_45
+ * @arg @ref LL_RCC_PLLSAIM_DIV_46
+ * @arg @ref LL_RCC_PLLSAIM_DIV_47
+ * @arg @ref LL_RCC_PLLSAIM_DIV_48
+ * @arg @ref LL_RCC_PLLSAIM_DIV_49
+ * @arg @ref LL_RCC_PLLSAIM_DIV_50
+ * @arg @ref LL_RCC_PLLSAIM_DIV_51
+ * @arg @ref LL_RCC_PLLSAIM_DIV_52
+ * @arg @ref LL_RCC_PLLSAIM_DIV_53
+ * @arg @ref LL_RCC_PLLSAIM_DIV_54
+ * @arg @ref LL_RCC_PLLSAIM_DIV_55
+ * @arg @ref LL_RCC_PLLSAIM_DIV_56
+ * @arg @ref LL_RCC_PLLSAIM_DIV_57
+ * @arg @ref LL_RCC_PLLSAIM_DIV_58
+ * @arg @ref LL_RCC_PLLSAIM_DIV_59
+ * @arg @ref LL_RCC_PLLSAIM_DIV_60
+ * @arg @ref LL_RCC_PLLSAIM_DIV_61
+ * @arg @ref LL_RCC_PLLSAIM_DIV_62
+ * @arg @ref LL_RCC_PLLSAIM_DIV_63
+ * @param PLLN Between 49/50(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_2
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_3
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_4
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_5
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_6
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_7
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_8
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_9
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_10
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_11
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_12
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_13
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_14
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_15
+ * @param PLLDIVQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+ MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
+#else
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+ MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
+}
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+ * @brief Configure PLLSAI used for 48Mhz domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI(*) are disabled
+ * @note PLLN/PLLP can be written only when PLLSAI is disabled
+ * @note This can be selected for USB, RNG, SDIO
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
+ * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
+ * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
+ * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIM_DIV_2
+ * @arg @ref LL_RCC_PLLSAIM_DIV_3
+ * @arg @ref LL_RCC_PLLSAIM_DIV_4
+ * @arg @ref LL_RCC_PLLSAIM_DIV_5
+ * @arg @ref LL_RCC_PLLSAIM_DIV_6
+ * @arg @ref LL_RCC_PLLSAIM_DIV_7
+ * @arg @ref LL_RCC_PLLSAIM_DIV_8
+ * @arg @ref LL_RCC_PLLSAIM_DIV_9
+ * @arg @ref LL_RCC_PLLSAIM_DIV_10
+ * @arg @ref LL_RCC_PLLSAIM_DIV_11
+ * @arg @ref LL_RCC_PLLSAIM_DIV_12
+ * @arg @ref LL_RCC_PLLSAIM_DIV_13
+ * @arg @ref LL_RCC_PLLSAIM_DIV_14
+ * @arg @ref LL_RCC_PLLSAIM_DIV_15
+ * @arg @ref LL_RCC_PLLSAIM_DIV_16
+ * @arg @ref LL_RCC_PLLSAIM_DIV_17
+ * @arg @ref LL_RCC_PLLSAIM_DIV_18
+ * @arg @ref LL_RCC_PLLSAIM_DIV_19
+ * @arg @ref LL_RCC_PLLSAIM_DIV_20
+ * @arg @ref LL_RCC_PLLSAIM_DIV_21
+ * @arg @ref LL_RCC_PLLSAIM_DIV_22
+ * @arg @ref LL_RCC_PLLSAIM_DIV_23
+ * @arg @ref LL_RCC_PLLSAIM_DIV_24
+ * @arg @ref LL_RCC_PLLSAIM_DIV_25
+ * @arg @ref LL_RCC_PLLSAIM_DIV_26
+ * @arg @ref LL_RCC_PLLSAIM_DIV_27
+ * @arg @ref LL_RCC_PLLSAIM_DIV_28
+ * @arg @ref LL_RCC_PLLSAIM_DIV_29
+ * @arg @ref LL_RCC_PLLSAIM_DIV_30
+ * @arg @ref LL_RCC_PLLSAIM_DIV_31
+ * @arg @ref LL_RCC_PLLSAIM_DIV_32
+ * @arg @ref LL_RCC_PLLSAIM_DIV_33
+ * @arg @ref LL_RCC_PLLSAIM_DIV_34
+ * @arg @ref LL_RCC_PLLSAIM_DIV_35
+ * @arg @ref LL_RCC_PLLSAIM_DIV_36
+ * @arg @ref LL_RCC_PLLSAIM_DIV_37
+ * @arg @ref LL_RCC_PLLSAIM_DIV_38
+ * @arg @ref LL_RCC_PLLSAIM_DIV_39
+ * @arg @ref LL_RCC_PLLSAIM_DIV_40
+ * @arg @ref LL_RCC_PLLSAIM_DIV_41
+ * @arg @ref LL_RCC_PLLSAIM_DIV_42
+ * @arg @ref LL_RCC_PLLSAIM_DIV_43
+ * @arg @ref LL_RCC_PLLSAIM_DIV_44
+ * @arg @ref LL_RCC_PLLSAIM_DIV_45
+ * @arg @ref LL_RCC_PLLSAIM_DIV_46
+ * @arg @ref LL_RCC_PLLSAIM_DIV_47
+ * @arg @ref LL_RCC_PLLSAIM_DIV_48
+ * @arg @ref LL_RCC_PLLSAIM_DIV_49
+ * @arg @ref LL_RCC_PLLSAIM_DIV_50
+ * @arg @ref LL_RCC_PLLSAIM_DIV_51
+ * @arg @ref LL_RCC_PLLSAIM_DIV_52
+ * @arg @ref LL_RCC_PLLSAIM_DIV_53
+ * @arg @ref LL_RCC_PLLSAIM_DIV_54
+ * @arg @ref LL_RCC_PLLSAIM_DIV_55
+ * @arg @ref LL_RCC_PLLSAIM_DIV_56
+ * @arg @ref LL_RCC_PLLSAIM_DIV_57
+ * @arg @ref LL_RCC_PLLSAIM_DIV_58
+ * @arg @ref LL_RCC_PLLSAIM_DIV_59
+ * @arg @ref LL_RCC_PLLSAIM_DIV_60
+ * @arg @ref LL_RCC_PLLSAIM_DIV_61
+ * @arg @ref LL_RCC_PLLSAIM_DIV_62
+ * @arg @ref LL_RCC_PLLSAIM_DIV_63
+ * @param PLLN Between 50 and 432
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIP_DIV_2
+ * @arg @ref LL_RCC_PLLSAIP_DIV_4
+ * @arg @ref LL_RCC_PLLSAIP_DIV_6
+ * @arg @ref LL_RCC_PLLSAIP_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+ MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
+#else
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+ MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+#if defined(LTDC)
+/**
+ * @brief Configure PLLSAI used for LTDC domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLI2S and PLLSAI(*) are disabled
+ * @note PLLN/PLLR can be written only when PLLSAI is disabled
+ * @note This can be selected for LTDC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+ * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+ * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+ * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIM_DIV_2
+ * @arg @ref LL_RCC_PLLSAIM_DIV_3
+ * @arg @ref LL_RCC_PLLSAIM_DIV_4
+ * @arg @ref LL_RCC_PLLSAIM_DIV_5
+ * @arg @ref LL_RCC_PLLSAIM_DIV_6
+ * @arg @ref LL_RCC_PLLSAIM_DIV_7
+ * @arg @ref LL_RCC_PLLSAIM_DIV_8
+ * @arg @ref LL_RCC_PLLSAIM_DIV_9
+ * @arg @ref LL_RCC_PLLSAIM_DIV_10
+ * @arg @ref LL_RCC_PLLSAIM_DIV_11
+ * @arg @ref LL_RCC_PLLSAIM_DIV_12
+ * @arg @ref LL_RCC_PLLSAIM_DIV_13
+ * @arg @ref LL_RCC_PLLSAIM_DIV_14
+ * @arg @ref LL_RCC_PLLSAIM_DIV_15
+ * @arg @ref LL_RCC_PLLSAIM_DIV_16
+ * @arg @ref LL_RCC_PLLSAIM_DIV_17
+ * @arg @ref LL_RCC_PLLSAIM_DIV_18
+ * @arg @ref LL_RCC_PLLSAIM_DIV_19
+ * @arg @ref LL_RCC_PLLSAIM_DIV_20
+ * @arg @ref LL_RCC_PLLSAIM_DIV_21
+ * @arg @ref LL_RCC_PLLSAIM_DIV_22
+ * @arg @ref LL_RCC_PLLSAIM_DIV_23
+ * @arg @ref LL_RCC_PLLSAIM_DIV_24
+ * @arg @ref LL_RCC_PLLSAIM_DIV_25
+ * @arg @ref LL_RCC_PLLSAIM_DIV_26
+ * @arg @ref LL_RCC_PLLSAIM_DIV_27
+ * @arg @ref LL_RCC_PLLSAIM_DIV_28
+ * @arg @ref LL_RCC_PLLSAIM_DIV_29
+ * @arg @ref LL_RCC_PLLSAIM_DIV_30
+ * @arg @ref LL_RCC_PLLSAIM_DIV_31
+ * @arg @ref LL_RCC_PLLSAIM_DIV_32
+ * @arg @ref LL_RCC_PLLSAIM_DIV_33
+ * @arg @ref LL_RCC_PLLSAIM_DIV_34
+ * @arg @ref LL_RCC_PLLSAIM_DIV_35
+ * @arg @ref LL_RCC_PLLSAIM_DIV_36
+ * @arg @ref LL_RCC_PLLSAIM_DIV_37
+ * @arg @ref LL_RCC_PLLSAIM_DIV_38
+ * @arg @ref LL_RCC_PLLSAIM_DIV_39
+ * @arg @ref LL_RCC_PLLSAIM_DIV_40
+ * @arg @ref LL_RCC_PLLSAIM_DIV_41
+ * @arg @ref LL_RCC_PLLSAIM_DIV_42
+ * @arg @ref LL_RCC_PLLSAIM_DIV_43
+ * @arg @ref LL_RCC_PLLSAIM_DIV_44
+ * @arg @ref LL_RCC_PLLSAIM_DIV_45
+ * @arg @ref LL_RCC_PLLSAIM_DIV_46
+ * @arg @ref LL_RCC_PLLSAIM_DIV_47
+ * @arg @ref LL_RCC_PLLSAIM_DIV_48
+ * @arg @ref LL_RCC_PLLSAIM_DIV_49
+ * @arg @ref LL_RCC_PLLSAIM_DIV_50
+ * @arg @ref LL_RCC_PLLSAIM_DIV_51
+ * @arg @ref LL_RCC_PLLSAIM_DIV_52
+ * @arg @ref LL_RCC_PLLSAIM_DIV_53
+ * @arg @ref LL_RCC_PLLSAIM_DIV_54
+ * @arg @ref LL_RCC_PLLSAIM_DIV_55
+ * @arg @ref LL_RCC_PLLSAIM_DIV_56
+ * @arg @ref LL_RCC_PLLSAIM_DIV_57
+ * @arg @ref LL_RCC_PLLSAIM_DIV_58
+ * @arg @ref LL_RCC_PLLSAIM_DIV_59
+ * @arg @ref LL_RCC_PLLSAIM_DIV_60
+ * @arg @ref LL_RCC_PLLSAIM_DIV_61
+ * @arg @ref LL_RCC_PLLSAIM_DIV_62
+ * @arg @ref LL_RCC_PLLSAIM_DIV_63
+ * @param PLLN Between 49/50(*) and 432
+ *
+ * (*) value not defined in all devices.
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIR_DIV_2
+ * @arg @ref LL_RCC_PLLSAIR_DIV_3
+ * @arg @ref LL_RCC_PLLSAIR_DIV_4
+ * @arg @ref LL_RCC_PLLSAIR_DIV_5
+ * @arg @ref LL_RCC_PLLSAIR_DIV_6
+ * @arg @ref LL_RCC_PLLSAIR_DIV_7
+ * @param PLLDIVR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
+ MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
+}
+#endif /* LTDC */
+
+/**
+ * @brief Get division factor for PLLSAI input clock
+ * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
+ * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIM_DIV_2
+ * @arg @ref LL_RCC_PLLSAIM_DIV_3
+ * @arg @ref LL_RCC_PLLSAIM_DIV_4
+ * @arg @ref LL_RCC_PLLSAIM_DIV_5
+ * @arg @ref LL_RCC_PLLSAIM_DIV_6
+ * @arg @ref LL_RCC_PLLSAIM_DIV_7
+ * @arg @ref LL_RCC_PLLSAIM_DIV_8
+ * @arg @ref LL_RCC_PLLSAIM_DIV_9
+ * @arg @ref LL_RCC_PLLSAIM_DIV_10
+ * @arg @ref LL_RCC_PLLSAIM_DIV_11
+ * @arg @ref LL_RCC_PLLSAIM_DIV_12
+ * @arg @ref LL_RCC_PLLSAIM_DIV_13
+ * @arg @ref LL_RCC_PLLSAIM_DIV_14
+ * @arg @ref LL_RCC_PLLSAIM_DIV_15
+ * @arg @ref LL_RCC_PLLSAIM_DIV_16
+ * @arg @ref LL_RCC_PLLSAIM_DIV_17
+ * @arg @ref LL_RCC_PLLSAIM_DIV_18
+ * @arg @ref LL_RCC_PLLSAIM_DIV_19
+ * @arg @ref LL_RCC_PLLSAIM_DIV_20
+ * @arg @ref LL_RCC_PLLSAIM_DIV_21
+ * @arg @ref LL_RCC_PLLSAIM_DIV_22
+ * @arg @ref LL_RCC_PLLSAIM_DIV_23
+ * @arg @ref LL_RCC_PLLSAIM_DIV_24
+ * @arg @ref LL_RCC_PLLSAIM_DIV_25
+ * @arg @ref LL_RCC_PLLSAIM_DIV_26
+ * @arg @ref LL_RCC_PLLSAIM_DIV_27
+ * @arg @ref LL_RCC_PLLSAIM_DIV_28
+ * @arg @ref LL_RCC_PLLSAIM_DIV_29
+ * @arg @ref LL_RCC_PLLSAIM_DIV_30
+ * @arg @ref LL_RCC_PLLSAIM_DIV_31
+ * @arg @ref LL_RCC_PLLSAIM_DIV_32
+ * @arg @ref LL_RCC_PLLSAIM_DIV_33
+ * @arg @ref LL_RCC_PLLSAIM_DIV_34
+ * @arg @ref LL_RCC_PLLSAIM_DIV_35
+ * @arg @ref LL_RCC_PLLSAIM_DIV_36
+ * @arg @ref LL_RCC_PLLSAIM_DIV_37
+ * @arg @ref LL_RCC_PLLSAIM_DIV_38
+ * @arg @ref LL_RCC_PLLSAIM_DIV_39
+ * @arg @ref LL_RCC_PLLSAIM_DIV_40
+ * @arg @ref LL_RCC_PLLSAIM_DIV_41
+ * @arg @ref LL_RCC_PLLSAIM_DIV_42
+ * @arg @ref LL_RCC_PLLSAIM_DIV_43
+ * @arg @ref LL_RCC_PLLSAIM_DIV_44
+ * @arg @ref LL_RCC_PLLSAIM_DIV_45
+ * @arg @ref LL_RCC_PLLSAIM_DIV_46
+ * @arg @ref LL_RCC_PLLSAIM_DIV_47
+ * @arg @ref LL_RCC_PLLSAIM_DIV_48
+ * @arg @ref LL_RCC_PLLSAIM_DIV_49
+ * @arg @ref LL_RCC_PLLSAIM_DIV_50
+ * @arg @ref LL_RCC_PLLSAIM_DIV_51
+ * @arg @ref LL_RCC_PLLSAIM_DIV_52
+ * @arg @ref LL_RCC_PLLSAIM_DIV_53
+ * @arg @ref LL_RCC_PLLSAIM_DIV_54
+ * @arg @ref LL_RCC_PLLSAIM_DIV_55
+ * @arg @ref LL_RCC_PLLSAIM_DIV_56
+ * @arg @ref LL_RCC_PLLSAIM_DIV_57
+ * @arg @ref LL_RCC_PLLSAIM_DIV_58
+ * @arg @ref LL_RCC_PLLSAIM_DIV_59
+ * @arg @ref LL_RCC_PLLSAIM_DIV_60
+ * @arg @ref LL_RCC_PLLSAIM_DIV_61
+ * @arg @ref LL_RCC_PLLSAIM_DIV_62
+ * @arg @ref LL_RCC_PLLSAIM_DIV_63
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
+{
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+ return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
+#else
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+}
+
+/**
+ * @brief Get SAIPLL multiplication factor for VCO
+ * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
+ * @retval Between 49/50(*) and 432
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+}
+
+/**
+ * @brief Get SAIPLL division factor for PLLSAIQ
+ * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_2
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_3
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_4
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_5
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_6
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_7
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_8
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_9
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_10
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_11
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_12
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_13
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_14
+ * @arg @ref LL_RCC_PLLSAIQ_DIV_15
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
+}
+
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+/**
+ * @brief Get SAIPLL division factor for PLLSAIR
+ * @note used for PLLSAICLK (SAI clock)
+ * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIR_DIV_2
+ * @arg @ref LL_RCC_PLLSAIR_DIV_3
+ * @arg @ref LL_RCC_PLLSAIR_DIV_4
+ * @arg @ref LL_RCC_PLLSAIR_DIV_5
+ * @arg @ref LL_RCC_PLLSAIR_DIV_6
+ * @arg @ref LL_RCC_PLLSAIR_DIV_7
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+ * @brief Get SAIPLL division factor for PLLSAIP
+ * @note used for PLL48MCLK (48M domain clock)
+ * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIP_DIV_2
+ * @arg @ref LL_RCC_PLLSAIP_DIV_4
+ * @arg @ref LL_RCC_PLLSAIP_DIV_6
+ * @arg @ref LL_RCC_PLLSAIP_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+/**
+ * @brief Get SAIPLL division factor for PLLSAIDIVQ
+ * @note used PLLSAICLK selected (SAI clock)
+ * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+ * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
+}
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVR)
+/**
+ * @brief Get SAIPLL division factor for PLLSAIDIVR
+ * @note used for LTDC domain clock
+ * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+ * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
+}
+#endif /* RCC_DCKCFGR_PLLSAIDIVR */
+
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear LSI ready interrupt flag
+ * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
+}
+
+/**
+ * @brief Clear LSE ready interrupt flag
+ * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
+}
+
+/**
+ * @brief Clear HSI ready interrupt flag
+ * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
+}
+
+/**
+ * @brief Clear HSE ready interrupt flag
+ * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
+}
+
+/**
+ * @brief Clear PLL ready interrupt flag
+ * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Clear PLLI2S ready interrupt flag
+ * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+ * @brief Clear PLLSAI ready interrupt flag
+ * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+}
+
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+ * @brief Clear Clock security system interrupt flag
+ * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_CSSC);
+}
+
+/**
+ * @brief Check if LSI ready interrupt occurred or not
+ * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
+}
+
+/**
+ * @brief Check if LSE ready interrupt occurred or not
+ * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
+}
+
+/**
+ * @brief Check if HSI ready interrupt occurred or not
+ * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
+}
+
+/**
+ * @brief Check if HSE ready interrupt occurred or not
+ * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
+}
+
+/**
+ * @brief Check if PLL ready interrupt occurred or not
+ * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Check if PLLI2S ready interrupt occurred or not
+ * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+ * @brief Check if PLLSAI ready interrupt occurred or not
+ * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
+}
+
+/**
+ * @brief Check if RCC flag Independent Watchdog reset is set or not.
+ * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Low Power reset is set or not.
+ * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Pin reset is set or not.
+ * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+ * @brief Check if RCC flag POR/PDR reset is set or not.
+ * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Software reset is set or not.
+ * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Window Watchdog reset is set or not.
+ * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+#if defined(RCC_CSR_BORRSTF)
+/**
+ * @brief Check if RCC flag BOR reset is set or not.
+ * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
+}
+#endif /* RCC_CSR_BORRSTF */
+
+/**
+ * @brief Set RMVF bit to clear the reset flags.
+ * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Enable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Enable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Enable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Enable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Enable PLLI2S ready interrupt
+ * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+ * @brief Enable PLLSAI ready interrupt
+ * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+ * @brief Disable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Disable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Disable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Disable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Disable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Disable PLLI2S ready interrupt
+ * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+ * @brief Disable PLLSAI ready interrupt
+ * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+ * @brief Checks if LSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
+}
+
+/**
+ * @brief Checks if LSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
+}
+
+/**
+ * @brief Checks if HSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
+}
+
+/**
+ * @brief Checks if HSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
+}
+
+/**
+ * @brief Checks if PLL ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+ * @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+ * @{
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+#if defined(FMPI2C1)
+uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
+#endif /* FMPI2C1 */
+#if defined(LPTIM1)
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+#endif /* LPTIM1 */
+#if defined(SAI1)
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+#endif /* SAI1 */
+#if defined(SDIO)
+uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
+#endif /* SDIO */
+#if defined(RNG)
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+#endif /* RNG */
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB_OTG_HS */
+#if defined(DFSDM1_Channel0)
+uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
+#endif /* DFSDM1_Channel0 */
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#if defined(CEC)
+uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
+#endif /* CEC */
+#if defined(LTDC)
+uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
+#endif /* LTDC */
+#if defined(SPDIFRX)
+uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
+#endif /* SPDIFRX */
+#if defined(DSI)
+uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
+#endif /* DSI */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,122 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_rng.c
+ * @author MCD Application Team
+ * @brief RNG LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_rng.h"
+#include "stm32f4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (RNG)
+
+/** @addtogroup RNG_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RNG_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RNG_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize RNG registers (Registers restored to their default values).
+ * @param RNGx RNG Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RNG registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
+{
+ /* Check the parameters */
+ assert_param(IS_RNG_ALL_INSTANCE(RNGx));
+
+#if !defined (RCC_AHB2_SUPPORT)
+ /* Enable RNG reset state */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG);
+
+ /* Release RNG from reset state */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG);
+#else
+ /* Enable RNG reset state */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
+
+ /* Release RNG from reset state */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
+#endif
+
+ return (SUCCESS);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (RNG) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,353 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_rng.h
+ * @author MCD Application Team
+ * @brief Header file of RNG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_RNG_H
+#define __STM32F4xx_LL_RNG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RNG)
+
+/** @defgroup RNG_LL RNG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
+ * @{
+ */
+
+/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RNG_ReadReg function
+ * @{
+ */
+#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
+#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
+#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
+#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
+#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
+ * @{
+ */
+#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
+ * @{
+ */
+
+/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RNG register
+ * @param __INSTANCE__ RNG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RNG register
+ * @param __INSTANCE__ RNG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
+ * @{
+ */
+/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Enable Random Number Generation
+ * @rmtoll CR RNGEN LL_RNG_Enable
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
+{
+ SET_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+ * @brief Disable Random Number Generation
+ * @rmtoll CR RNGEN LL_RNG_Disable
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
+{
+ CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+ * @brief Check if Random Number Generator is enabled
+ * @rmtoll CR RNGEN LL_RNG_IsEnabled
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
+{
+ return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Indicate if the RNG Data ready Flag is set or not
+ * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
+{
+ return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
+}
+
+/**
+ * @brief Indicate if the Clock Error Current Status Flag is set or not
+ * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
+{
+ return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
+}
+
+/**
+ * @brief Indicate if the Seed Error Current Status Flag is set or not
+ * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
+{
+ return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
+}
+
+/**
+ * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
+ * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
+{
+ return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
+}
+
+/**
+ * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
+ * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
+{
+ return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
+}
+
+/**
+ * @brief Clear Clock Error interrupt Status (CEIS) Flag
+ * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
+{
+ WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
+}
+
+/**
+ * @brief Clear Seed Error interrupt Status (SEIS) Flag
+ * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
+{
+ WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable Random Number Generator Interrupt
+ * (applies for either Seed error, Clock Error or Data ready interrupts)
+ * @rmtoll CR IE LL_RNG_EnableIT
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
+{
+ SET_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+ * @brief Disable Random Number Generator Interrupt
+ * (applies for either Seed error, Clock Error or Data ready interrupts)
+ * @rmtoll CR IE LL_RNG_DisableIT
+ * @param RNGx RNG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
+{
+ CLEAR_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+ * @brief Check if Random Number Generator Interrupt is enabled
+ * (applies for either Seed error, Clock Error or Data ready interrupts)
+ * @rmtoll CR IE LL_RNG_IsEnabledIT
+ * @param RNGx RNG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
+{
+ return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_LL_EF_Data_Management Data Management
+ * @{
+ */
+
+/**
+ * @brief Return32-bit Random Number value
+ * @rmtoll DR RNDATA LL_RNG_ReadRandData32
+ * @param RNGx RNG Instance
+ * @retval Generated 32-bit random value
+ */
+__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
+{
+ return (uint32_t)(READ_REG(RNGx->DR));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RNG) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_RNG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,892 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_rtc.c
+ * @author MCD Application Team
+ * @brief RTC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_rtc.h"
+#include "stm32f4xx_ll_cortex.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+ * @{
+ */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
+#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
+ || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
+
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+ || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
+ || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
+
+#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
+#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
+
+#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
+
+#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
+
+#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
+ || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
+ || ((__VALUE__) == LL_RTC_MONTH_MAY) \
+ || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
+ || ((__VALUE__) == LL_RTC_MONTH_JULY) \
+ || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
+ || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+
+#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
+
+#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
+
+
+#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
+ ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
+ ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
+
+
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initializes the RTC registers to their default reset values.
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are de-initialized
+ * - ERROR: RTC registers are not de-initialized
+ */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Reset TR, DR and CR registers */
+ LL_RTC_WriteReg(RTCx, TR, 0x00000000U);
+#if defined(RTC_WAKEUP_SUPPORT)
+ LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT);
+#endif /* RTC_WAKEUP_SUPPORT */
+ LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+ /* Reset All CR bits except CR[2:0] */
+#if defined(RTC_WAKEUP_SUPPORT)
+ LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
+#else
+ LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
+#endif /* RTC_WAKEUP_SUPPORT */
+ LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+ LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, CALR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
+
+ /* Reset ISR register and exit initialization mode */
+ LL_RTC_WriteReg(RTCx, ISR, 0x00000000U);
+
+ /* Reset Tamper and alternate functions configuration register */
+ LL_RTC_WriteReg(RTCx, TAFCR, 0x00000000U);
+
+ /* Wait till the RTC RSF flag is set */
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTCx RTC Instance
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
+ assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+ assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Set Hour Format */
+ LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
+
+ /* Configure Synchronous and Asynchronous prescaler factor */
+ LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
+ LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_InitTypeDef field to default value.
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ /* Set RTC_InitStruct fields to default values */
+ RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR;
+ RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+ RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT;
+}
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+ * the time configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ }
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
+ RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
+ }
+ else
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTC);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
+ RTC_TimeStruct->Hours = 0U;
+ RTC_TimeStruct->Minutes = 0U;
+ RTC_TimeStruct->Seconds = 0U;
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
+ * the date configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Day register is configured
+ * - ERROR: RTC Day register is not configured
+ */
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
+ {
+ RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+ }
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
+ assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
+ assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
+ assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
+ }
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
+ }
+ else
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTC);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
+ * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
+ RTC_DateStruct->Day = 1U;
+ RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY;
+ RTC_DateStruct->Year = 0U;
+}
+
+/**
+ * @brief Set the RTC Alarm A.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use @ref LL_RTC_ALMA_Disable function).
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARMA registers are configured
+ * - ERROR: ALARMA registers are not configured
+ */
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+ assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Select weekday selection */
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ /* Set the date for ALARM */
+ LL_RTC_ALMA_DisableWeekday(RTCx);
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+ else
+ {
+ LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ /* Set the week day for ALARM */
+ LL_RTC_ALMA_EnableWeekday(RTCx);
+ LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+
+ /* Configure the Alarm register */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+ RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+ }
+ else
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ /* Set ALARM mask */
+ LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the RTC Alarm B.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (@ref LL_RTC_ALMB_Disable function).
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARMB registers are configured
+ * - ERROR: ALARMB registers are not configured
+ */
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+ assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Select weekday selection */
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ /* Set the date for ALARM */
+ LL_RTC_ALMB_DisableWeekday(RTCx);
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+ else
+ {
+ LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ /* Set the week day for ALARM */
+ LL_RTC_ALMB_EnableWeekday(RTCx);
+ LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+
+ /* Configure the Alarm register */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+ RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+ }
+ else
+ {
+ LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ /* Set ALARM mask */
+ LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+
+ /* Alarm Day Settings : Day = 1st day of the month */
+ RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
+ RTC_AlarmStruct->AlarmDateWeekDay = 1U;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+
+ /* Alarm Day Settings : Day = 1st day of the month */
+ RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
+ RTC_AlarmStruct->AlarmDateWeekDay = 1U;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE;
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Check if the Initialization mode is set */
+ if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
+ {
+ /* Set the Initialization mode */
+ LL_RTC_EnableInitMode(RTCx);
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout --;
+ }
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC exited from in Init mode
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Clear RSF flag */
+ LL_RTC_ClearFlag_RS(RTCx);
+
+ /* Wait the registers to be synchronised */
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 0U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+
+ if (status != ERROR)
+ {
+ timeout = RTC_SYNCHRO_TIMEOUT;
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,3848 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_rtc.h
+ * @author MCD Application Team
+ * @brief Header file of RTC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_RTC_H
+#define __STM32F4xx_LL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @defgroup RTC_LL RTC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_LL_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_INIT_MASK 0xFFFFFFFFU
+#define RTC_RSF_MASK 0xFFFFFF5FU
+
+/* Write protection defines */
+#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
+#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
+#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
+
+/* Defines used to combine date & time */
+#define RTC_OFFSET_WEEKDAY 24U
+#define RTC_OFFSET_DAY 16U
+#define RTC_OFFSET_MONTH 8U
+#define RTC_OFFSET_HOUR 16U
+#define RTC_OFFSET_MINUTE 8U
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_Private_Macros RTC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hours Format.
+ This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetHourFormat(). */
+
+ uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetAsynchPrescaler(). */
+
+ uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetSynchPrescaler(). */
+} LL_RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
+
+ uint8_t Hours; /*!< Specifies the RTC Time Hours.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
+} LL_RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month.
+ This parameter can be a value of @ref RTC_LL_EC_MONTH
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
+
+ uint8_t Day; /*!< Specifies the RTC Date Day.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
+} LL_RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
+ or @ref LL_RTC_ALMB_SetMask() for ALARM B
+ */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
+ for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
+ */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay.
+ If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
+ for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
+
+ If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
+ for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
+ */
+} LL_RTC_AlarmTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EC_FORMAT FORMAT
+ * @{
+ */
+#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
+ * @{
+ */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
+ * @{
+ */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RTC_ReadReg function
+ * @{
+ */
+#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
+#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
+#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
+#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
+#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
+#define LL_RTC_ISR_TSF RTC_ISR_TSF
+#define LL_RTC_ISR_WUTF RTC_ISR_WUTF
+#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
+#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
+#define LL_RTC_ISR_INITF RTC_ISR_INITF
+#define LL_RTC_ISR_RSF RTC_ISR_RSF
+#define LL_RTC_ISR_INITS RTC_ISR_INITS
+#define LL_RTC_ISR_SHPF RTC_ISR_SHPF
+#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
+#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
+#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions
+ * @{
+ */
+#define LL_RTC_CR_TSIE RTC_CR_TSIE
+#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
+#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
+#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
+#define LL_RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY
+ * @{
+ */
+#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */
+#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */
+#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */
+#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */
+#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */
+#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */
+#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_MONTH MONTH
+ * @{
+ */
+#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */
+#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */
+#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */
+#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */
+#define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */
+#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */
+#define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */
+#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */
+#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */
+#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */
+#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */
+#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT
+ * @{
+ */
+#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */
+#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT
+ * @{
+ */
+#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */
+#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */
+#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */
+#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
+ * @{
+ */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_RTC_PIN_PC13 RTC_TAFCR_PC13MODE /*!< PC13 is forced to push-pull output if all RTC alternate functions are disabled */
+#define LL_RTC_PIN_PC14 RTC_TAFCR_PC14MODE /*!< PC14 is forced to push-pull output if LSE is disabled */
+#define LL_RTC_PIN_PC15 RTC_TAFCR_PC15MODE /*!< PC15 is forced to push-pull output if LSE is disabled */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
+ * @{
+ */
+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
+#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
+ * @{
+ */
+#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND
+ * @{
+ */
+#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
+#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK
+ * @{
+ */
+#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/
+#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT
+ * @{
+ */
+#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK
+ * @{
+ */
+#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/
+#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT
+ * @{
+ */
+#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
+ * @{
+ */
+#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT
+ * @{
+ */
+#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER TAMPER
+ * @{
+ */
+#define LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E /*!< RTC_TAMP1 input detection */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_2 RTC_TAFCR_TAMP2E /*!< RTC_TAMP2 input detection */
+#endif /* RTC_TAMPER2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
+ * @{
+ */
+#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
+#endif /* RTC_TAMPER2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
+ * @{
+ */
+#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
+#endif /* RTC_TAMPER2_SUPPORT */
+/**
+ * @}
+ */
+
+#if defined(RTC_TAFCR_TAMPPRCH)
+/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
+ * @{
+ */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
+#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
+/**
+ * @}
+ */
+#endif /* RTC_TAFCR_TAMPPRCH */
+
+#if defined(RTC_TAFCR_TAMPFLT)
+/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
+ * @{
+ */
+#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */
+/**
+ * @}
+ */
+#endif /* RTC_TAFCR_TAMPFLT */
+
+#if defined(RTC_TAFCR_TAMPFREQ)
+/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
+ * @{
+ */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */
+/**
+ * @}
+ */
+#endif /* RTC_TAFCR_TAMPFREQ */
+
+/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
+ * @{
+ */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV
+ * @{
+ */
+#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usually 1 Hz) clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_BKP BACKUP
+ * @{
+ */
+#define LL_RTC_BKP_DR0 0x00000000U
+#define LL_RTC_BKP_DR1 0x00000001U
+#define LL_RTC_BKP_DR2 0x00000002U
+#define LL_RTC_BKP_DR3 0x00000003U
+#define LL_RTC_BKP_DR4 0x00000004U
+#if RTC_BKP_NUMBER > 5
+#define LL_RTC_BKP_DR5 0x00000005U
+#define LL_RTC_BKP_DR6 0x00000006U
+#define LL_RTC_BKP_DR7 0x00000007U
+#define LL_RTC_BKP_DR8 0x00000008U
+#define LL_RTC_BKP_DR9 0x00000009U
+#define LL_RTC_BKP_DR10 0x0000000AU
+#define LL_RTC_BKP_DR11 0x0000000BU
+#define LL_RTC_BKP_DR12 0x0000000CU
+#define LL_RTC_BKP_DR13 0x0000000DU
+#define LL_RTC_BKP_DR14 0x0000000EU
+#define LL_RTC_BKP_DR15 0x0000000FU
+#endif /* RTC_BKP_NUMBER > 5 */
+
+#if RTC_BKP_NUMBER > 16
+#define LL_RTC_BKP_DR16 0x00000010U
+#define LL_RTC_BKP_DR17 0x00000011U
+#define LL_RTC_BKP_DR18 0x00000012U
+#define LL_RTC_BKP_DR19 0x00000013U
+#endif /* RTC_BKP_NUMBER > 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output
+ * @{
+ */
+#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */
+#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
+#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_SIGN Coarse digital calibration sign
+ * @{
+ */
+#define LL_RTC_CALIB_SIGN_POSITIVE 0x00000000U /*!< Positive calibration: calendar update frequency is increased */
+#define LL_RTC_CALIB_SIGN_NEGATIVE RTC_CALIBR_DCS /*!< Negative calibration: calendar update frequency is decreased */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
+ * @{
+ */
+#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */
+#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period
+ * @{
+ */
+#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TSINSEL TIMESTAMP mapping
+ * @{
+ */
+#define LL_RTC_TimeStampPin_Default 0x00000000U /*!< Use RTC_AF1 as TIMESTAMP */
+#if defined(RTC_AF2_SUPPORT)
+#define LL_RTC_TimeStampPin_Pos1 RTC_TAFCR_TSINSEL /*!< Use RTC_AF2 as TIMESTAMP */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMP1INSEL TAMPER1 mapping
+ * @{
+ */
+#define LL_RTC_TamperPin_Default 0x00000000U /*!< Use RTC_AF1 as TAMPER1 */
+#if defined(RTC_AF2_SUPPORT)
+#define LL_RTC_TamperPin_Pos1 RTC_TAFCR_TAMP1INSEL /*!< Use RTC_AF2 as TAMPER1 */
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Convert Convert helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to convert a value from 2 digit decimal format to BCD format
+ * @param __VALUE__ Byte to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
+
+/**
+ * @brief Helper macro to convert a value from BCD format to 2 digit decimal format
+ * @param __VALUE__ BCD value to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Date Date helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to retrieve weekday.
+ * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Year in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Year in BCD format (0x00 . . . 0x99)
+ */
+#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Month in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Day in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Day in BCD format (0x01 . . . 0x31)
+ */
+#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Time Time helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to retrieve hour in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
+ */
+#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve minute in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Minutes in BCD format (0x00. . .0x59)
+ */
+#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve second in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Seconds in format (0x00. . .0x59)
+ */
+#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Set Hours format (24 hour/day or AM/PM hour format)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR FMT LL_RTC_SetHourFormat
+ * @param RTCx RTC Instance
+ * @param HourFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_HOURFORMAT_24HOUR
+ * @arg @ref LL_RTC_HOURFORMAT_AMPM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
+}
+
+/**
+ * @brief Get Hours format (24 hour/day or AM/PM hour format)
+ * @rmtoll CR FMT LL_RTC_GetHourFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_HOURFORMAT_24HOUR
+ * @arg @ref LL_RTC_HOURFORMAT_AMPM
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
+}
+
+/**
+ * @brief Select the flag to be routed to RTC_ALARM output
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent
+ * @param RTCx RTC Instance
+ * @param AlarmOutput This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALARMOUT_DISABLE
+ * @arg @ref LL_RTC_ALARMOUT_ALMA
+ * @arg @ref LL_RTC_ALARMOUT_ALMB
+ * @arg @ref LL_RTC_ALARMOUT_WAKEUP
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
+}
+
+/**
+ * @brief Get the flag to be routed to RTC_ALARM output
+ * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALARMOUT_DISABLE
+ * @arg @ref LL_RTC_ALARMOUT_ALMA
+ * @arg @ref LL_RTC_ALARMOUT_ALMB
+ * @arg @ref LL_RTC_ALARMOUT_WAKEUP
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
+}
+
+/**
+ * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
+ * @note Used only when RTC_ALARM is mapped on PC13
+ * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
+ * PC13 output data
+ * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_SetAlarmOutputType
+ * @param RTCx RTC Instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE, Output);
+}
+
+/**
+ * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
+ * @note used only when RTC_ALARM is mapped on PC13
+ * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
+ * PC13 output data
+ * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_GetAlarmOutputType
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE));
+}
+
+/**
+ * @brief Enable push-pull output on PC13, PC14 and/or PC15
+ * @note PC13 forced to push-pull output if all RTC alternate functions are disabled
+ * @note PC14 and PC15 forced to push-pull output if LSE is disabled
+ * @rmtoll TAFCR PC13MODE LL_RTC_EnablePushPullMode\n
+ * @rmtoll TAFCR PC14MODE LL_RTC_EnablePushPullMode\n
+ * @rmtoll TAFCR PC15MODE LL_RTC_EnablePushPullMode
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC13
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnablePushPullMode(RTC_TypeDef *RTCx, uint32_t PinMask)
+{
+ SET_BIT(RTCx->TAFCR, PinMask);
+}
+
+/**
+ * @brief Disable push-pull output on PC13, PC14 and/or PC15
+ * @note PC13, PC14 and/or PC15 are controlled by the GPIO configuration registers.
+ * Consequently PC13, PC14 and/or PC15 are floating in Standby mode.
+ * @rmtoll TAFCR PC13MODE LL_RTC_DisablePushPullMode\n
+ * TAFCR PC14MODE LL_RTC_DisablePushPullMode\n
+ * TAFCR PC15MODE LL_RTC_DisablePushPullMode
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC13
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisablePushPullMode(RTC_TypeDef* RTCx, uint32_t PinMask)
+{
+ CLEAR_BIT(RTCx->TAFCR, PinMask);
+}
+
+/**
+ * @brief Set PC14 and/or PC15 to high level.
+ * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
+ * @rmtoll TAFCR PC14VALUE LL_RTC_SetOutputPin\n
+ * TAFCR PC15VALUE LL_RTC_SetOutputPin
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
+{
+ SET_BIT(RTCx->TAFCR, (PinMask >> 1));
+}
+
+/**
+ * @brief Set PC14 and/or PC15 to low level.
+ * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
+ * @rmtoll TAFCR PC14VALUE LL_RTC_ResetOutputPin\n
+ * TAFCR PC15VALUE LL_RTC_ResetOutputPin
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ResetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
+{
+ CLEAR_BIT(RTCx->TAFCR, (PinMask >> 1));
+}
+
+/**
+ * @brief Enable initialization mode
+ * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
+ * and prescaler register (RTC_PRER).
+ * Counters are stopped and start counting from the new value when INIT is reset.
+ * @rmtoll ISR INIT LL_RTC_EnableInitMode
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
+{
+ /* Set the Initialization mode */
+ WRITE_REG(RTCx->ISR, RTC_INIT_MASK);
+}
+
+/**
+ * @brief Disable initialization mode (Free running mode)
+ * @rmtoll ISR INIT LL_RTC_DisableInitMode
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
+{
+ /* Exit Initialization mode */
+ WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
+}
+
+/**
+ * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR POL LL_RTC_SetOutputPolarity
+ * @param RTCx RTC Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
+}
+
+/**
+ * @brief Get Output polarity
+ * @rmtoll CR POL LL_RTC_GetOutputPolarity
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
+}
+
+/**
+ * @brief Enable Bypass the shadow registers
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR BYPSHAD LL_RTC_EnableShadowRegBypass
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+ * @brief Disable Bypass the shadow registers
+ * @rmtoll CR BYPSHAD LL_RTC_DisableShadowRegBypass
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+ * @brief Check if Shadow registers bypass is enabled or not.
+ * @rmtoll CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
+}
+
+/**
+ * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR REFCKON LL_RTC_EnableRefClock
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+ * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR REFCKON LL_RTC_DisableRefClock
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+ * @brief Set Asynchronous prescaler factor
+ * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler
+ * @param RTCx RTC Instance
+ * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
+{
+ MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+ * @brief Set Synchronous prescaler factor
+ * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler
+ * @param RTCx RTC Instance
+ * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
+{
+ MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
+}
+
+/**
+ * @brief Get Asynchronous prescaler factor
+ * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0x7F
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+ * @brief Get Synchronous prescaler factor
+ * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
+}
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @rmtoll WPR KEY LL_RTC_EnableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
+}
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @rmtoll WPR KEY LL_RTC_DisableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Time Time
+ * @{
+ */
+
+/**
+ * @brief Set time format (AM/24-hour or PM notation)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll TR PM LL_RTC_TIME_SetFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get time format (AM or PM notation)
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @rmtoll TR PM LL_RTC_TIME_GetFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
+}
+
+/**
+ * @brief Set Hours in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
+ * @rmtoll TR HT LL_RTC_TIME_SetHour\n
+ * TR HU LL_RTC_TIME_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
+ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
+}
+
+/**
+ * @brief Get Hours in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
+ * Binary format
+ * @rmtoll TR HT LL_RTC_TIME_GetHour\n
+ * TR HU LL_RTC_TIME_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
+ return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
+}
+
+/**
+ * @brief Set Minutes in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n
+ * TR MNU LL_RTC_TIME_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
+ (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
+}
+
+/**
+ * @brief Get Minutes in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
+ * to Binary format
+ * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n
+ * TR MNU LL_RTC_TIME_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
+ return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
+}
+
+/**
+ * @brief Set Seconds in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll TR ST LL_RTC_TIME_SetSecond\n
+ * TR SU LL_RTC_TIME_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
+ (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
+}
+
+/**
+ * @brief Get Seconds in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
+ * to Binary format
+ * @rmtoll TR ST LL_RTC_TIME_GetSecond\n
+ * TR SU LL_RTC_TIME_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
+ return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
+}
+
+/**
+ * @brief Set time (hour, minute and second) in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note TimeFormat and Hours should follow the same format
+ * @rmtoll TR PM LL_RTC_TIME_Config\n
+ * TR HT LL_RTC_TIME_Config\n
+ * TR HU LL_RTC_TIME_Config\n
+ * TR MNT LL_RTC_TIME_Config\n
+ * TR MNU LL_RTC_TIME_Config\n
+ * TR ST LL_RTC_TIME_Config\n
+ * TR SU LL_RTC_TIME_Config
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+ register uint32_t temp = 0U;
+
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
+ (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
+ MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
+}
+
+/**
+ * @brief Get time (hour, minute and second) in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll TR HT LL_RTC_TIME_Get\n
+ * TR HU LL_RTC_TIME_Get\n
+ * TR MNT LL_RTC_TIME_Get\n
+ * TR MNU LL_RTC_TIME_Get\n
+ * TR ST LL_RTC_TIME_Get\n
+ * TR SU LL_RTC_TIME_Get
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
+ return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
+ (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
+ ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
+}
+
+/**
+ * @brief Memorize whether the daylight saving time change has been performed
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+ * @brief Disable memorization whether the daylight saving time change has been performed.
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+ * @brief Check if RTC Day Light Saving stored operation has been enabled or not
+ * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
+}
+
+/**
+ * @brief Subtract 1 hour (winter time change)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR SUB1H LL_RTC_TIME_DecHour
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_SUB1H);
+}
+
+/**
+ * @brief Add 1 hour (summer time change)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ADD1H LL_RTC_TIME_IncHour
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ADD1H);
+}
+
+/**
+ * @brief Get Sub second value in the synchronous prescaler counter.
+ * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
+ * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
+ * SubSeconds value in second fraction ratio with time unit following
+ * generic formula:
+ * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending
+ * (ie. SHFP=0) when PREDIV_S >= SS.
+ * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Sub second value (number between 0 and 65535)
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
+}
+
+/**
+ * @brief Synchronize to a remote clock with a high degree of precision.
+ * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @rmtoll SHIFTR ADD1S LL_RTC_TIME_Synchronize\n
+ * SHIFTR SUBFS LL_RTC_TIME_Synchronize
+ * @param RTCx RTC Instance
+ * @param ShiftSecond This parameter can be one of the following values:
+ * @arg @ref LL_RTC_SHIFT_SECOND_DELAY
+ * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
+ * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
+{
+ WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Date Date
+ * @{
+ */
+
+/**
+ * @brief Set Year in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
+ * @rmtoll DR YT LL_RTC_DATE_SetYear\n
+ * DR YU LL_RTC_DATE_SetYear
+ * @param RTCx RTC Instance
+ * @param Year Value between Min_Data=0x00 and Max_Data=0x99
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
+ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
+}
+
+/**
+ * @brief Get Year in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
+ * @rmtoll DR YT LL_RTC_DATE_GetYear\n
+ * DR YU LL_RTC_DATE_GetYear
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x99
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
+ return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
+}
+
+/**
+ * @brief Set Week day
+ * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
+}
+
+/**
+ * @brief Get Week day
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
+}
+
+/**
+ * @brief Set Month in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
+ * @rmtoll DR MT LL_RTC_DATE_SetMonth\n
+ * DR MU LL_RTC_DATE_SetMonth
+ * @param RTCx RTC Instance
+ * @param Month This parameter can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
+ (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
+}
+
+/**
+ * @brief Get Month in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+ * @rmtoll DR MT LL_RTC_DATE_GetMonth\n
+ * DR MU LL_RTC_DATE_GetMonth
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
+ return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
+}
+
+/**
+ * @brief Set Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll DR DT LL_RTC_DATE_SetDay\n
+ * DR DU LL_RTC_DATE_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
+ (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
+}
+
+/**
+ * @brief Get Day in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll DR DT LL_RTC_DATE_GetDay\n
+ * DR DU LL_RTC_DATE_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
+ return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
+}
+
+/**
+ * @brief Set date (WeekDay, Day, Month and Year) in BCD format
+ * @rmtoll DR WDU LL_RTC_DATE_Config\n
+ * DR MT LL_RTC_DATE_Config\n
+ * DR MU LL_RTC_DATE_Config\n
+ * DR DT LL_RTC_DATE_Config\n
+ * DR DU LL_RTC_DATE_Config\n
+ * DR YT LL_RTC_DATE_Config\n
+ * DR YU LL_RTC_DATE_Config
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @param Month This parameter can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ * @param Year Value between Min_Data=0x00 and Max_Data=0x99
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
+{
+ register uint32_t temp = 0U;
+
+ temp = (WeekDay << RTC_DR_WDU_Pos) | \
+ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
+ (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
+ (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
+
+ MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
+}
+
+/**
+ * @brief Get date (WeekDay, Day, Month and Year) in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
+ * and __LL_RTC_GET_DAY are available to get independently each parameter.
+ * @rmtoll DR WDU LL_RTC_DATE_Get\n
+ * DR MT LL_RTC_DATE_Get\n
+ * DR MU LL_RTC_DATE_Get\n
+ * DR DT LL_RTC_DATE_Get\n
+ * DR DU LL_RTC_DATE_Get\n
+ * DR YT LL_RTC_DATE_Get\n
+ * DR YU LL_RTC_DATE_Get
+ * @param RTCx RTC Instance
+ * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
+ return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
+ (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
+ (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
+ ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_ALARMA ALARMA
+ * @{
+ */
+
+/**
+ * @brief Enable Alarm A
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAE LL_RTC_ALMA_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+ * @brief Disable Alarm A
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAE LL_RTC_ALMA_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+ * @brief Specify the Alarm A masks.
+ * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n
+ * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n
+ * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n
+ * ALRMAR MSK1 LL_RTC_ALMA_SetMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMA_MASK_NONE
+ * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMA_MASK_HOURS
+ * @arg @ref LL_RTC_ALMA_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMA_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMA_MASK_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
+}
+
+/**
+ * @brief Get the Alarm A masks.
+ * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n
+ * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n
+ * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n
+ * ALRMAR MSK1 LL_RTC_ALMA_GetMask
+ * @param RTCx RTC Instance
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMA_MASK_NONE
+ * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMA_MASK_HOURS
+ * @arg @ref LL_RTC_ALMA_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMA_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMA_MASK_ALL
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
+}
+
+/**
+ * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+ * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+ * @brief Disable AlarmA Week day selection (DU[3:0] represents the date )
+ * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+ * @brief Set ALARM A Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n
+ * ALRMAR DU LL_RTC_ALMA_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
+ (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n
+ * ALRMAR DU LL_RTC_ALMA_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
+ return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
+}
+
+/**
+ * @brief Set ALARM A Weekday
+ * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
+}
+
+/**
+ * @brief Get ALARM A Weekday
+ * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
+}
+
+/**
+ * @brief Set Alarm A time format (AM/24-hour or PM notation)
+ * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get Alarm A time format (AM or PM notation)
+ * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
+}
+
+/**
+ * @brief Set ALARM A Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+ * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n
+ * ALRMAR HU LL_RTC_ALMA_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
+ (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n
+ * ALRMAR HU LL_RTC_ALMA_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
+ return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
+}
+
+/**
+ * @brief Set ALARM A Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n
+ * ALRMAR MNU LL_RTC_ALMA_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
+ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n
+ * ALRMAR MNU LL_RTC_ALMA_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
+ return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
+}
+
+/**
+ * @brief Set ALARM A Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n
+ * ALRMAR SU LL_RTC_ALMA_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
+ (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
+}
+
+/**
+ * @brief Get ALARM A Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n
+ * ALRMAR SU LL_RTC_ALMA_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+ return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
+}
+
+/**
+ * @brief Set Alarm A Time (hour, minute and second) in BCD format
+ * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR HT LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR HU LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR ST LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR SU LL_RTC_ALMA_ConfigTime
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+ register uint32_t temp = 0U;
+
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
+ (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
+
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
+}
+
+/**
+ * @brief Get Alarm B Time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n
+ * ALRMAR HU LL_RTC_ALMA_GetTime\n
+ * ALRMAR MNT LL_RTC_ALMA_GetTime\n
+ * ALRMAR MNU LL_RTC_ALMA_GetTime\n
+ * ALRMAR ST LL_RTC_ALMA_GetTime\n
+ * ALRMAR SU LL_RTC_ALMA_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
+}
+
+/**
+ * @brief Set Alarm A Mask the most-significant bits starting at this bit
+ * @note This register can be written only when ALRAE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
+ * @param RTCx RTC Instance
+ * @param Mask Value between Min_Data=0x00 and Max_Data=0xF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Get Alarm A Mask the most-significant bits starting at this bit
+ * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Set Alarm A Sub seconds value
+ * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond
+ * @param RTCx RTC Instance
+ * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+ MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
+}
+
+/**
+ * @brief Get Alarm A Sub seconds value
+ * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_ALARMB ALARMB
+ * @{
+ */
+
+/**
+ * @brief Enable Alarm B
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBE LL_RTC_ALMB_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+ * @brief Disable Alarm B
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBE LL_RTC_ALMB_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+ * @brief Specify the Alarm B masks.
+ * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n
+ * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n
+ * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n
+ * ALRMBR MSK1 LL_RTC_ALMB_SetMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMB_MASK_NONE
+ * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMB_MASK_HOURS
+ * @arg @ref LL_RTC_ALMB_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMB_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMB_MASK_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
+}
+
+/**
+ * @brief Get the Alarm B masks.
+ * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n
+ * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n
+ * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n
+ * ALRMBR MSK1 LL_RTC_ALMB_GetMask
+ * @param RTCx RTC Instance
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMB_MASK_NONE
+ * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMB_MASK_HOURS
+ * @arg @ref LL_RTC_ALMB_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMB_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMB_MASK_ALL
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
+}
+
+/**
+ * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+ * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+ * @brief Disable AlarmB Week day selection (DU[3:0] represents the date )
+ * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+ * @brief Set ALARM B Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n
+ * ALRMBR DU LL_RTC_ALMB_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
+ (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n
+ * ALRMBR DU LL_RTC_ALMB_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
+ return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
+}
+
+/**
+ * @brief Set ALARM B Weekday
+ * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
+}
+
+/**
+ * @brief Get ALARM B Weekday
+ * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
+}
+
+/**
+ * @brief Set ALARM B time format (AM/24-hour or PM notation)
+ * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get ALARM B time format (AM or PM notation)
+ * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
+}
+
+/**
+ * @brief Set ALARM B Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+ * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n
+ * ALRMBR HU LL_RTC_ALMB_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
+ (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n
+ * ALRMBR HU LL_RTC_ALMB_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
+ return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
+}
+
+/**
+ * @brief Set ALARM B Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n
+ * ALRMBR MNU LL_RTC_ALMB_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
+ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n
+ * ALRMBR MNU LL_RTC_ALMB_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
+ return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
+}
+
+/**
+ * @brief Set ALARM B Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n
+ * ALRMBR SU LL_RTC_ALMB_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
+ (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
+}
+
+/**
+ * @brief Get ALARM B Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n
+ * ALRMBR SU LL_RTC_ALMB_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
+ return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
+}
+
+/**
+ * @brief Set Alarm B Time (hour, minute and second) in BCD format
+ * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR HT LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR HU LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR ST LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR SU LL_RTC_ALMB_ConfigTime
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+ register uint32_t temp = 0U;
+
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
+ (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
+
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
+}
+
+/**
+ * @brief Get Alarm B Time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n
+ * ALRMBR HU LL_RTC_ALMB_GetTime\n
+ * ALRMBR MNT LL_RTC_ALMB_GetTime\n
+ * ALRMBR MNU LL_RTC_ALMB_GetTime\n
+ * ALRMBR ST LL_RTC_ALMB_GetTime\n
+ * ALRMBR SU LL_RTC_ALMB_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
+}
+
+/**
+ * @brief Set Alarm B Mask the most-significant bits starting at this bit
+ * @note This register can be written only when ALRBE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
+ * @param RTCx RTC Instance
+ * @param Mask Value between Min_Data=0x00 and Max_Data=0xF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Get Alarm B Mask the most-significant bits starting at this bit
+ * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+ * @brief Set Alarm B Sub seconds value
+ * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
+ * @param RTCx RTC Instance
+ * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+ MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
+}
+
+/**
+ * @brief Get Alarm B Sub seconds value
+ * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Timestamp Timestamp
+ * @{
+ */
+
+/**
+ * @brief Enable Timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSE LL_RTC_TS_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+ * @brief Disable Timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSE LL_RTC_TS_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+ * @brief Set Time-stamp event active edge
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
+ * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge
+ * @param RTCx RTC Instance
+ * @param Edge This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
+}
+
+/**
+ * @brief Get Time-stamp event active edge
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
+}
+
+/**
+ * @brief Get Timestamp AM/PM notation (AM or 24-hour format)
+ * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TS_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_TS_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
+}
+
+/**
+ * @brief Get Timestamp Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll TSTR HT LL_RTC_TS_GetHour\n
+ * TSTR HU LL_RTC_TS_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n
+ * TSTR MNU LL_RTC_TS_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n
+ * TSTR SU LL_RTC_TS_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+ * @brief Get Timestamp time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll TSTR HT LL_RTC_TS_GetTime\n
+ * TSTR HU LL_RTC_TS_GetTime\n
+ * TSTR MNT LL_RTC_TS_GetTime\n
+ * TSTR MNU LL_RTC_TS_GetTime\n
+ * TSTR ST LL_RTC_TS_GetTime\n
+ * TSTR SU LL_RTC_TS_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR,
+ RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+ * @brief Get Timestamp Week day
+ * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Month in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+ * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n
+ * TSDR MU LL_RTC_TS_GetMonth
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
+}
+
+/**
+ * @brief Get Timestamp Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll TSDR DT LL_RTC_TS_GetDay\n
+ * TSDR DU LL_RTC_TS_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+ * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format
+ * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
+ * and __LL_RTC_GET_DAY are available to get independently each parameter.
+ * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n
+ * TSDR MT LL_RTC_TS_GetDate\n
+ * TSDR MU LL_RTC_TS_GetDate\n
+ * TSDR DT LL_RTC_TS_GetDate\n
+ * TSDR DU LL_RTC_TS_GetDate
+ * @param RTCx RTC Instance
+ * @retval Combination of Weekday, Day and Month
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+ * @brief Get time-stamp sub second value
+ * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
+}
+
+#if defined(RTC_TAFCR_TAMPTS)
+/**
+ * @brief Activate timestamp on tamper detection event
+ * @rmtoll TAFCR TAMPTS LL_RTC_TS_EnableOnTamper
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
+}
+
+/**
+ * @brief Disable timestamp on tamper detection event
+ * @rmtoll TAFCR TAMPTS LL_RTC_TS_DisableOnTamper
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
+}
+#endif /* RTC_TAFCR_TAMPTS */
+
+/**
+ * @brief Set timestamp Pin
+ * @rmtoll TAFCR TSINSEL LL_RTC_TS_SetPin
+ * @param RTCx RTC Instance
+ * @param TSPin specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp.
+ * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp. (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_SetPin(RTC_TypeDef *RTCx, uint32_t TSPin)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TSINSEL , TSPin);
+}
+
+/**
+ * @brief Get timestamp Pin
+ * @rmtoll TAFCR TSINSEL LL_RTC_TS_GetPin
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp Pin.
+ * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp Pin. (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+
+__STATIC_INLINE uint32_t LL_RTC_TS_GetPin(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TSINSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Tamper Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable RTC_TAMPx input detection
+ * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Enable\n
+ * TAFCR TAMP2E LL_RTC_TAMPER_Enable\n
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_1
+ * @arg @ref LL_RTC_TAMPER_2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ SET_BIT(RTCx->TAFCR, Tamper);
+}
+
+/**
+ * @brief Clear RTC_TAMPx input detection
+ * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Disable\n
+ * TAFCR TAMP2E LL_RTC_TAMPER_Disable\n
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_1
+ * @arg @ref LL_RTC_TAMPER_2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ CLEAR_BIT(RTCx->TAFCR, Tamper);
+}
+
+#if defined(RTC_TAFCR_TAMPPUDIS)
+/**
+ * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
+ * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
+}
+
+/**
+ * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
+ * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
+}
+#endif /* RTC_TAFCR_TAMPPUDIS */
+
+#if defined(RTC_TAFCR_TAMPPRCH)
+/**
+ * @brief Set RTC_TAMPx precharge duration
+ * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
+ * @param RTCx RTC Instance
+ * @param Duration This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH, Duration);
+}
+
+/**
+ * @brief Get RTC_TAMPx precharge duration
+ * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH));
+}
+#endif /* RTC_TAFCR_TAMPPRCH */
+
+#if defined(RTC_TAFCR_TAMPFLT)
+/**
+ * @brief Set RTC_TAMPx filter count
+ * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
+ * @param RTCx RTC Instance
+ * @param FilterCount This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFLT, FilterCount);
+}
+
+/**
+ * @brief Get RTC_TAMPx filter count
+ * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT));
+}
+#endif /* RTC_TAFCR_TAMPFLT */
+
+#if defined(RTC_TAFCR_TAMPFREQ)
+/**
+ * @brief Set Tamper sampling frequency
+ * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
+ * @param RTCx RTC Instance
+ * @param SamplingFreq This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ, SamplingFreq);
+}
+
+/**
+ * @brief Get Tamper sampling frequency
+ * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ));
+}
+#endif /* RTC_TAFCR_TAMPFREQ */
+
+/**
+ * @brief Enable Active level for Tamper input
+ * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n
+ * TAFCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ SET_BIT(RTCx->TAFCR, Tamper);
+}
+
+/**
+ * @brief Disable Active level for Tamper input
+ * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n
+ * TAFCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ CLEAR_BIT(RTCx->TAFCR, Tamper);
+}
+
+/**
+ * @brief Set Tamper Pin
+ * @rmtoll TAFCR TAMP1INSEL LL_RTC_TAMPER_SetPin
+ * @param RTCx RTC Instance
+ * @param TamperPin specifies the RTC Tamper Pin.
+ * This parameter can be one of the following values:
+ * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper.
+ * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper. (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetPin(RTC_TypeDef *RTCx, uint32_t TamperPin)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL , TamperPin);
+}
+
+/**
+ * @brief Get Tamper Pin
+ * @rmtoll TAFCR TAMP1INSEL LL_RTC_TAMPER_GetPin
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin.
+ * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper Pin. (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPin(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Wakeup Wakeup
+ * @{
+ */
+
+/**
+ * @brief Enable Wakeup timer
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+ * @brief Disable Wakeup timer
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+ * @brief Check if Wakeup timer is enabled or not
+ * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
+}
+
+/**
+ * @brief Select Wakeup clock
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
+ * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock
+ * @param RTCx RTC Instance
+ * @param WakeupClock This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
+}
+
+/**
+ * @brief Get Wakeup clock
+ * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
+}
+
+/**
+ * @brief Set Wakeup auto-reload value
+ * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
+ * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload
+ * @param RTCx RTC Instance
+ * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
+{
+ MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
+}
+
+/**
+ * @brief Get Wakeup auto-reload value
+ * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
+ * @{
+ */
+
+/**
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister
+ * @param RTCx RTC Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4
+ * @arg @ref LL_RTC_BKP_DR5
+ * @arg @ref LL_RTC_BKP_DR6
+ * @arg @ref LL_RTC_BKP_DR7
+ * @arg @ref LL_RTC_BKP_DR8
+ * @arg @ref LL_RTC_BKP_DR9
+ * @arg @ref LL_RTC_BKP_DR10
+ * @arg @ref LL_RTC_BKP_DR11
+ * @arg @ref LL_RTC_BKP_DR12
+ * @arg @ref LL_RTC_BKP_DR13
+ * @arg @ref LL_RTC_BKP_DR14
+ * @arg @ref LL_RTC_BKP_DR15
+ * @arg @ref LL_RTC_BKP_DR16
+ * @arg @ref LL_RTC_BKP_DR17
+ * @arg @ref LL_RTC_BKP_DR18
+ * @arg @ref LL_RTC_BKP_DR19
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
+{
+ register uint32_t tmp = 0U;
+
+ tmp = (uint32_t)(&(RTCx->BKP0R));
+ tmp += (BackupRegister * 4U);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @rmtoll BKPxR BKP LL_RTC_BAK_GetRegister
+ * @param RTCx RTC Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4
+ * @arg @ref LL_RTC_BKP_DR5
+ * @arg @ref LL_RTC_BKP_DR6
+ * @arg @ref LL_RTC_BKP_DR7
+ * @arg @ref LL_RTC_BKP_DR8
+ * @arg @ref LL_RTC_BKP_DR9
+ * @arg @ref LL_RTC_BKP_DR10
+ * @arg @ref LL_RTC_BKP_DR11
+ * @arg @ref LL_RTC_BKP_DR12
+ * @arg @ref LL_RTC_BKP_DR13
+ * @arg @ref LL_RTC_BKP_DR14
+ * @arg @ref LL_RTC_BKP_DR15
+ * @arg @ref LL_RTC_BKP_DR16
+ * @arg @ref LL_RTC_BKP_DR17
+ * @arg @ref LL_RTC_BKP_DR18
+ * @arg @ref LL_RTC_BKP_DR19
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
+{
+ register uint32_t tmp = 0U;
+
+ tmp = (uint32_t)(&(RTCx->BKP0R));
+ tmp += (BackupRegister * 4U);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Calibration Calibration
+ * @{
+ */
+
+/**
+ * @brief Set Calibration output frequency (1 Hz or 512 Hz)
+ * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n
+ * CR COSEL LL_RTC_CAL_SetOutputFreq
+ * @param RTCx RTC Instance
+ * @param Frequency This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
+}
+
+/**
+ * @brief Get Calibration output frequency (1 Hz or 512 Hz)
+ * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n
+ * CR COSEL LL_RTC_CAL_GetOutputFreq
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
+}
+
+/**
+ * @brief Enable Coarse digital calibration
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR DCE LL_RTC_CAL_EnableCoarseDigital
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_EnableCoarseDigital(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_DCE);
+}
+
+/**
+ * @brief Disable Coarse digital calibration
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR DCE LL_RTC_CAL_DisableCoarseDigital
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_DisableCoarseDigital(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_DCE);
+}
+
+/**
+ * @brief Set the coarse digital calibration
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CALIBR DCS LL_RTC_CAL_ConfigCoarseDigital\n
+ * CALIBR DC LL_RTC_CAL_ConfigCoarseDigital
+ * @param RTCx RTC Instance
+ * @param Sign This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_SIGN_POSITIVE
+ * @arg @ref LL_RTC_CALIB_SIGN_NEGATIVE
+ * @param Value value of coarse calibration expressed in ppm (coded on 5 bits)
+ * @note This Calibration value should be between 0 and 63 when using negative sign with a 2-ppm step.
+ * @note This Calibration value should be between 0 and 126 when using positive sign with a 4-ppm step.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_ConfigCoarseDigital(RTC_TypeDef* RTCx, uint32_t Sign, uint32_t Value)
+{
+ MODIFY_REG(RTCx->CALIBR, RTC_CALIBR_DCS | RTC_CALIBR_DC, Sign | Value);
+}
+
+/**
+ * @brief Get the coarse digital calibration value
+ * @rmtoll CALIBR DC LL_RTC_CAL_GetCoarseDigitalValue
+ * @param RTCx RTC Instance
+ * @retval value of coarse calibration expressed in ppm (coded on 5 bits)
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalValue(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALIBR, RTC_CALIBR_DC));
+}
+
+/**
+ * @brief Get the coarse digital calibration sign
+ * @rmtoll CALIBR DCS LL_RTC_CAL_GetCoarseDigitalSign
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_SIGN_POSITIVE
+ * @arg @ref LL_RTC_CALIB_SIGN_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalSign(RTC_TypeDef* RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALIBR, RTC_CALIBR_DCS));
+}
+
+/**
+ * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @rmtoll CALR CALP LL_RTC_CAL_SetPulse
+ * @param RTCx RTC Instance
+ * @param Pulse This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
+ * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
+}
+
+/**
+ * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
+ * @rmtoll CALR CALP LL_RTC_CAL_IsPulseInserted
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
+}
+
+/**
+ * @brief Set the calibration cycle period
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n
+ * CALR CALW16 LL_RTC_CAL_SetPeriod
+ * @param RTCx RTC Instance
+ * @param Period This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
+}
+
+/**
+ * @brief Get the calibration cycle period
+ * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n
+ * CALR CALW16 LL_RTC_CAL_GetPeriod
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
+}
+
+/**
+ * @brief Set Calibration minus
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @rmtoll CALR CALM LL_RTC_CAL_SetMinus
+ * @param RTCx RTC Instance
+ * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
+}
+
+/**
+ * @brief Get Calibration minus
+ * @rmtoll CALR CALM LL_RTC_CAL_GetMinus
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Recalibration pending Flag
+ * @rmtoll ISR RECALPF LL_RTC_IsActiveFlag_RECALP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
+}
+
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+ * @brief Get RTC_TAMP2 detection flag
+ * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+/**
+ * @brief Get RTC_TAMP1 detection flag
+ * @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
+}
+
+/**
+ * @brief Get Time-stamp overflow flag
+ * @rmtoll ISR TSOVF LL_RTC_IsActiveFlag_TSOV
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
+}
+
+/**
+ * @brief Get Time-stamp flag
+ * @rmtoll ISR TSF LL_RTC_IsActiveFlag_TS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
+}
+
+/**
+ * @brief Get Wakeup timer flag
+ * @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
+}
+
+/**
+ * @brief Get Alarm B flag
+ * @rmtoll ISR ALRBF LL_RTC_IsActiveFlag_ALRB
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
+}
+
+/**
+ * @brief Get Alarm A flag
+ * @rmtoll ISR ALRAF LL_RTC_IsActiveFlag_ALRA
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
+}
+
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+ * @brief Clear RTC_TAMP2 detection flag
+ * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+/**
+ * @brief Clear RTC_TAMP1 detection flag
+ * @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Clear Time-stamp overflow flag
+ * @rmtoll ISR TSOVF LL_RTC_ClearFlag_TSOV
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Clear Time-stamp flag
+ * @rmtoll ISR TSF LL_RTC_ClearFlag_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Clear Wakeup timer flag
+ * @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Clear Alarm B flag
+ * @rmtoll ISR ALRBF LL_RTC_ClearFlag_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Clear Alarm A flag
+ * @rmtoll ISR ALRAF LL_RTC_ClearFlag_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Get Initialization flag
+ * @rmtoll ISR INITF LL_RTC_IsActiveFlag_INIT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
+}
+
+/**
+ * @brief Get Registers synchronization flag
+ * @rmtoll ISR RSF LL_RTC_IsActiveFlag_RS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
+}
+
+/**
+ * @brief Clear Registers synchronization flag
+ * @rmtoll ISR RSF LL_RTC_ClearFlag_RS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Get Initialization status flag
+ * @rmtoll ISR INITS LL_RTC_IsActiveFlag_INITS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
+}
+
+/**
+ * @brief Get Shift operation pending flag
+ * @rmtoll ISR SHPF LL_RTC_IsActiveFlag_SHP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
+}
+
+/**
+ * @brief Get Wakeup timer write flag
+ * @rmtoll ISR WUTWF LL_RTC_IsActiveFlag_WUTW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
+}
+
+/**
+ * @brief Get Alarm B write flag
+ * @rmtoll ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
+}
+
+/**
+ * @brief Get Alarm A write flag
+ * @rmtoll ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Time-stamp interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSIE LL_RTC_EnableIT_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+ * @brief Disable Time-stamp interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSIE LL_RTC_DisableIT_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+ * @brief Enable Wakeup timer interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTIE LL_RTC_EnableIT_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+ * @brief Disable Wakeup timer interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTIE LL_RTC_DisableIT_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+ * @brief Enable Alarm B interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBIE LL_RTC_EnableIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+ * @brief Disable Alarm B interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBIE LL_RTC_DisableIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+ * @brief Enable Alarm A interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAIE LL_RTC_EnableIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+ * @brief Disable Alarm A interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAIE LL_RTC_DisableIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+ * @brief Enable all Tamper Interrupt
+ * @rmtoll TAFCR TAMPIE LL_RTC_EnableIT_TAMP
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
+}
+
+/**
+ * @brief Disable all Tamper Interrupt
+ * @rmtoll TAFCR TAMPIE LL_RTC_DisableIT_TAMP
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
+}
+
+/**
+ * @brief Check if Time-stamp interrupt is enabled or not
+ * @rmtoll CR TSIE LL_RTC_IsEnabledIT_TS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
+}
+
+/**
+ * @brief Check if Wakeup timer interrupt is enabled or not
+ * @rmtoll CR WUTIE LL_RTC_IsEnabledIT_WUT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
+}
+
+/**
+ * @brief Check if Alarm B interrupt is enabled or not
+ * @rmtoll CR ALRBIE LL_RTC_IsEnabledIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
+}
+
+/**
+ * @brief Check if Alarm A interrupt is enabled or not
+ * @rmtoll CR ALRAIE LL_RTC_IsEnabledIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
+}
+
+/**
+ * @brief Check if all the TAMPER interrupts are enabled or not
+ * @rmtoll TAFCR TAMPIE LL_RTC_IsEnabledIT_TAMP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->TAFCR,
+ RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1507 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_sdmmc.c
+ * @author MCD Application Team
+ * @brief SDMMC Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the SDMMC peripheral:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SDMMC peripheral features #####
+ ==============================================================================
+ [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
+ peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
+ devices.
+
+ [..] The SDMMC features include the following:
+ (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
+ for three different databus modes: 1-bit (default), 4-bit and 8-bit
+ (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
+ (+) Full compliance with SD Memory Card Specifications Version 2.0
+ (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
+ different data bus modes: 1-bit (default) and 4-bit
+ (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
+ Rev1.1)
+ (+) Data transfer up to 48 MHz for the 8 bit mode
+ (+) Data and command output enable signals to control external bidirectional drivers.
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a considered as a driver of service for external devices drivers
+ that interfaces with the SDMMC peripheral.
+ According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
+ is used in the device's driver to perform SDMMC operations and functionalities.
+
+ This driver is almost transparent for the final user, it is only used to implement other
+ functionalities of the external device.
+
+ [..]
+ (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL
+ (PLL48CLK). Before start working with SDMMC peripheral make sure that the
+ PLL is well configured.
+ The SDMMC peripheral uses two clock signals:
+ (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
+ (++) APB2 bus clock (PCLK2)
+
+ -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
+ Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
+
+ (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
+ peripheral.
+
+ (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
+ function and disable it using the function SDIO_PowerState_ON(SDIOx).
+
+ (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
+
+ (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hSDIO, IT)
+ and __SDIO_DISABLE_IT(hSDIO, IT) if you need to use interrupt mode.
+
+ (+) When using the DMA mode
+ (++) Configure the DMA in the MSP layer of the external device
+ (++) Active the needed channel Request
+ (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
+ __SDIO_DMA_DISABLE().
+
+ (+) To control the CPSM (Command Path State Machine) and send
+ commands to the card use the SDIO_SendCommand(),
+ SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
+ to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
+ to the selected command to be sent.
+ The parameters that should be filled are:
+ (++) Command Argument
+ (++) Command Index
+ (++) Command Response type
+ (++) Command Wait
+ (++) CPSM Status (Enable or Disable).
+
+ -@@- To check if the command is well received, read the SDIO_CMDRESP
+ register using the SDIO_GetCommandResponse().
+ The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the
+ SDIO_GetResponse() function.
+
+ (+) To control the DPSM (Data Path State Machine) and send/receive
+ data to/from the card use the SDIO_ConfigData(), SDIO_GetDataCounter(),
+ SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
+
+ *** Read Operations ***
+ =======================
+ [..]
+ (#) First, user has to fill the data structure (pointer to
+ SDIO_DataInitTypeDef) according to the selected data type to be received.
+ The parameters that should be filled are:
+ (++) Data TimeOut
+ (++) Data Length
+ (++) Data Block size
+ (++) Data Transfer direction: should be from card (To SDMMC)
+ (++) Data Transfer mode
+ (++) DPSM Status (Enable or Disable)
+
+ (#) Configure the SDMMC resources to receive the data from the card
+ according to selected transfer mode (Refer to Step 8, 9 and 10).
+
+ (#) Send the selected Read command (refer to step 11).
+
+ (#) Use the SDIO flags/interrupts to check the transfer status.
+
+ *** Write Operations ***
+ ========================
+ [..]
+ (#) First, user has to fill the data structure (pointer to
+ SDIO_DataInitTypeDef) according to the selected data type to be received.
+ The parameters that should be filled are:
+ (++) Data TimeOut
+ (++) Data Length
+ (++) Data Block size
+ (++) Data Transfer direction: should be to card (To CARD)
+ (++) Data Transfer mode
+ (++) DPSM Status (Enable or Disable)
+
+ (#) Configure the SDMMC resources to send the data to the card according to
+ selected transfer mode.
+
+ (#) Send the selected Write command.
+
+ (#) Use the SDIO flags/interrupts to check the transfer status.
+
+ *** Command management operations ***
+ =====================================
+ [..]
+ (#) The commands used for Read/Write/Erase operations are managed in
+ separate functions.
+ Each function allows to send the needed command with the related argument,
+ then check the response.
+ By the same approach, you could implement a command and check the response.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SDMMC_LL SDMMC Low Layer
+ * @brief Low layer module for SD
+ * @{
+ */
+
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
+static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization/de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SDMMC according to the specified
+ * parameters in the SDMMC_InitTypeDef and create the associated handle.
+ * @param SDIOx Pointer to SDMMC register base
+ * @param Init SDMMC initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
+ assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
+ assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+ assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+ assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
+
+ /* Set SDMMC configuration parameters */
+ tmpreg |= (Init.ClockEdge |\
+ Init.ClockBypass |\
+ Init.ClockPowerSave |\
+ Init.BusWide |\
+ Init.HardwareFlowControl |\
+ Init.ClockDiv
+ );
+
+ /* Write to SDMMC CLKCR */
+ MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### I/O operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SDMMC data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read data (word) from Rx FIFO in blocking mode (polling)
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
+{
+ /* Read data from Rx FIFO */
+ return (SDIOx->FIFO);
+}
+
+/**
+ * @brief Write data (word) to Tx FIFO in blocking mode (polling)
+ * @param SDIOx Pointer to SDMMC register base
+ * @param pWriteData pointer to data to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
+{
+ /* Write data to FIFO */
+ SDIOx->FIFO = *pWriteData;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SDMMC data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set SDMMC Power state to ON.
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
+{
+ /* Set power state to ON */
+ SDIOx->POWER = SDIO_POWER_PWRCTRL;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set SDMMC Power state to OFF.
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
+{
+ /* Set power state to OFF */
+ SDIOx->POWER = 0x00000000U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get SDMMC Power state.
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval Power status of the controller. The returned value can be one of the
+ * following values:
+ * - 0x00: Power OFF
+ * - 0x02: Power UP
+ * - 0x03: Power ON
+ */
+uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
+{
+ return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
+}
+
+/**
+ * @brief Configure the SDMMC command path according to the specified parameters in
+ * SDIO_CmdInitTypeDef structure and send the command
+ * @param SDIOx Pointer to SDMMC register base
+ * @param Command pointer to a SDIO_CmdInitTypeDef structure that contains
+ * the configuration information for the SDMMC command
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));
+ assert_param(IS_SDIO_RESPONSE(Command->Response));
+ assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));
+ assert_param(IS_SDIO_CPSM(Command->CPSM));
+
+ /* Set the SDMMC Argument value */
+ SDIOx->ARG = Command->Argument;
+
+ /* Set SDMMC command parameters */
+ tmpreg |= (uint32_t)(Command->CmdIndex |\
+ Command->Response |\
+ Command->WaitForInterrupt |\
+ Command->CPSM);
+
+ /* Write to SDMMC CMD register */
+ MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Return the command index of last command for which response received
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval Command index of the last command response received
+ */
+uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
+{
+ return (uint8_t)(SDIOx->RESPCMD);
+}
+
+
+/**
+ * @brief Return the response received from the card for the last command
+ * @param SDIOx Pointer to SDMMC register base
+ * @param Response Specifies the SDMMC response register.
+ * This parameter can be one of the following values:
+ * @arg SDIO_RESP1: Response Register 1
+ * @arg SDIO_RESP1: Response Register 2
+ * @arg SDIO_RESP1: Response Register 3
+ * @arg SDIO_RESP1: Response Register 4
+ * @retval The Corresponding response register value
+ */
+uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
+{
+ __IO uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_RESP(Response));
+
+ /* Get the response */
+ tmp = (uint32_t)&(SDIOx->RESP1) + Response;
+
+ return (*(__IO uint32_t *) tmp);
+}
+
+/**
+ * @brief Configure the SDMMC data path according to the specified
+ * parameters in the SDIO_DataInitTypeDef.
+ * @param SDIOx Pointer to SDMMC register base
+ * @param Data pointer to a SDIO_DataInitTypeDef structure
+ * that contains the configuration information for the SDMMC data.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));
+ assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize));
+ assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir));
+ assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));
+ assert_param(IS_SDIO_DPSM(Data->DPSM));
+
+ /* Set the SDMMC Data TimeOut value */
+ SDIOx->DTIMER = Data->DataTimeOut;
+
+ /* Set the SDMMC DataLength value */
+ SDIOx->DLEN = Data->DataLength;
+
+ /* Set the SDMMC data configuration parameters */
+ tmpreg |= (uint32_t)(Data->DataBlockSize |\
+ Data->TransferDir |\
+ Data->TransferMode |\
+ Data->DPSM);
+
+ /* Write to SDMMC DCTRL */
+ MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Returns number of remaining data bytes to be transferred.
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval Number of remaining data bytes to be transferred
+ */
+uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
+{
+ return (SDIOx->DCOUNT);
+}
+
+/**
+ * @brief Get the FIFO data
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval Data received
+ */
+uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
+{
+ return (SDIOx->FIFO);
+}
+
+/**
+ * @brief Sets one of the two options of inserting read wait interval.
+ * @param SDIOx Pointer to SDMMC register base
+ * @param SDIO_ReadWaitMode SDMMC Read Wait operation mode.
+ * This parameter can be:
+ * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+ * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
+ * @retval None
+ */
+HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+
+ /* Set SDMMC read wait mode */
+ MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Commands management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the needed commands.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send the Data Block Lenght command and check the response
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Read Single Block command and check the response
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Read Multi Block command and check the response
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Write Single Block command and check the response
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Write Multi Block command and check the response
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Start Address Erase command for SD and check the response
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the End Address Erase command for SD and check the response
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Start Address Erase command and check the response
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the End Address Erase command and check the response
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Erase command and check the response
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Stop Transfer command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD12 STOP_TRANSMISSION */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, 100000000U);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Select Deselect command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @param addr Address of the card to be selected
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+ sdmmc_cmdinit.Argument = (uint32_t)Addr;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Go Idle State command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_NO;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdError(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Operating Condition command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD8 to verify SD card interface operating condition */
+ /* Argument: - [31:12]: Reserved (shall be set to '0')
+ - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+ - [7:0]: Check Pattern (recommended 0xAA) */
+ /* CMD Response: R7 */
+ sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp7(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Application command to verify that that the next command
+ * is an application specific com-mand rather than a standard command
+ * and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ /* If there is a HAL_ERROR, it is a MMC card, else
+ it is a SD card: SD card 2.0 (voltage range mismatch)
+ or SD card 1.x */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the command asking the accessed card to send its operating
+ * condition register (OCR)
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp3(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Bus Width command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send SCR command and check the response.
+ * @param SDIOx Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD51 SD_APP_SEND_SCR */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send CID command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD2 ALL_SEND_CID */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp2(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send CSD command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD9 SEND_CSD */
+ sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp2(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send CSD command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD3 SD_CMD_SET_REL_ADDR */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Status command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Status register command and check the response.
+ * @param SDIOx Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Sends host capacity support information and activates the card's
+ * initialization process. Send SDMMC_CMD_SEND_OP_COND command
+ * @param SDIOx Pointer to SDIO register base
+ * @parame Argument Argument used for the command
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp3(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
+ * @param SDIOx Pointer to SDIO register base
+ * @parame Argument Argument used for the command
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @}
+ */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Checks for error conditions for CMD0.
+ * @param hsd SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));
+
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Checks for error conditions for R1 response.
+ * @param hsd SD handle
+ * @param SD_CMD The sent command index
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
+{
+ uint32_t response_r1;
+
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The Timeout is expressed in ms */
+ register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* Check response received is of desired command */
+ if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
+ {
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+
+ /* We have received response, retrieve it for analysis */
+ response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
+
+ if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+ {
+ return SDMMC_ERROR_NONE;
+ }
+ else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+ {
+ return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+ }
+ else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+ {
+ return SDMMC_ERROR_ADDR_MISALIGNED;
+ }
+ else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+ {
+ return SDMMC_ERROR_BLOCK_LEN_ERR;
+ }
+ else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+ {
+ return SDMMC_ERROR_ERASE_SEQ_ERR;
+ }
+ else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+ {
+ return SDMMC_ERROR_BAD_ERASE_PARAM;
+ }
+ else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+ {
+ return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+ }
+ else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+ {
+ return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+ }
+ else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+ {
+ return SDMMC_ERROR_COM_CRC_FAILED;
+ }
+ else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+ {
+ return SDMMC_ERROR_ILLEGAL_CMD;
+ }
+ else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+ {
+ return SDMMC_ERROR_CARD_ECC_FAILED;
+ }
+ else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+ {
+ return SDMMC_ERROR_CC_ERR;
+ }
+ else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+ {
+ return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+ }
+ else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+ {
+ return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+ }
+ else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+ {
+ return SDMMC_ERROR_CID_CSD_OVERWRITE;
+ }
+ else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+ {
+ return SDMMC_ERROR_WP_ERASE_SKIP;
+ }
+ else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+ {
+ return SDMMC_ERROR_CARD_ECC_DISABLED;
+ }
+ else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+ {
+ return SDMMC_ERROR_ERASE_RESET;
+ }
+ else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+ {
+ return SDMMC_ERROR_AKE_SEQ_ERR;
+ }
+ else
+ {
+ return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+}
+
+/**
+ * @brief Checks for error conditions for R2 (CID or CSD) response.
+ * @param hsd SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+ else
+ {
+ /* No error flag set */
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+ }
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Checks for error conditions for R3 (OCR) response.
+ * @param hsd SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else
+
+ {
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+ }
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Checks for error conditions for R6 (RCA) response.
+ * @param hsd SD handle
+ * @param SD_CMD The sent command index
+ * @param pRCA Pointer to the variable that will contain the SD card relative
+ * address RCA
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+ uint32_t response_r1;
+
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* Check response received is of desired command */
+ if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
+ {
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+
+ /* We have received response, retrieve it. */
+ response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
+
+ if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+ {
+ *pRCA = (uint16_t) (response_r1 >> 16);
+
+ return SDMMC_ERROR_NONE;
+ }
+ else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+ {
+ return SDMMC_ERROR_ILLEGAL_CMD;
+ }
+ else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+ {
+ return SDMMC_ERROR_COM_CRC_FAILED;
+ }
+ else
+ {
+ return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+}
+
+/**
+ * @brief Checks for error conditions for R7 response.
+ * @param hsd SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDIO_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ /* Card is SD V2.0 compliant */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))
+ {
+ /* Card is SD V2.0 compliant */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
+ }
+
+ return SDMMC_ERROR_NONE;
+
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1133 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_sdmmc.h
+ * @author MCD Application Team
+ * @brief Header file of SDMMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_SDMMC_H
+#define __STM32F4xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_Driver
+ * @{
+ */
+
+/** @addtogroup SDMMC_LL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief SDMMC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
+
+ uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
+ enabled or disabled.
+ This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
+
+ uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
+
+ uint32_t BusWide; /*!< Specifies the SDMMC bus width.
+ This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
+
+ uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+}SDIO_InitTypeDef;
+
+
+/**
+ * @brief SDMMC Command Control structure
+ */
+typedef struct
+{
+ uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register. */
+
+ uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
+ Max_Data = 64 */
+
+ uint32_t Response; /*!< Specifies the SDMMC response type.
+ This parameter can be a value of @ref SDMMC_LL_Response_Type */
+
+ uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
+ enabled or disabled.
+ This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
+
+ uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDMMC_LL_CPSM_State */
+}SDIO_CmdInitTypeDef;
+
+
+/**
+ * @brief SDMMC Data Control structure
+ */
+typedef struct
+{
+ uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
+
+ uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
+
+ uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
+
+ uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDMMC_LL_DPSM_State */
+}SDIO_DataInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
+ * @{
+ */
+#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
+#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
+#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
+#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
+#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
+#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
+#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
+#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
+#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
+#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
+#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
+#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
+#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
+#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
+#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
+#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
+#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
+#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
+#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
+#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
+
+/**
+ * @brief SDMMC Commands Index
+ */
+#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
+#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
+#define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+ operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+ and asks the card whether card supports voltage. */
+#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
+#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
+#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
+#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */
+#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
+#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+ (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
+ for SDHS and SDXC. */
+#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
+ STOP_TRANSMISSION command. */
+#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
+#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
+#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
+#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
+#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
+#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
+#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
+ system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
+ Reserved for each command system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
+#define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+ the SET_BLOCK_LEN command. */
+#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
+ than a standard command. */
+#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
+ for general purpose/application specific commands. */
+#define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */
+
+/**
+ * @brief Following commands are SD Card Specific commands.
+ * SDMMC_APP_CMD should be sent before sending these commands.
+ */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+ widths are given in SCR register. */
+#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+ 32bit+CRC data block. */
+#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+ send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
+#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
+#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
+
+/**
+ * @brief Following commands are SD Card Specific security commands.
+ * SDMMC_CMD_APP_CMD should be sent before sending these commands.
+ */
+#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
+#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
+#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
+#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
+#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
+#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
+#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
+
+/**
+ * @brief Masks for errors Card Status R1 (OCR Register)
+ */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
+#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
+#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
+#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
+#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
+#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
+#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
+#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
+#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
+#define SDMMC_OCR_CC_ERROR 0x00100000U
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
+#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
+#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
+#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
+#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
+#define SDMMC_OCR_ERASE_RESET 0x00002000U
+#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
+#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
+
+/**
+ * @brief Masks for R6 Response
+ */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
+#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
+#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
+
+#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
+#define SDMMC_HIGH_CAPACITY 0x40000000U
+#define SDMMC_STD_CAPACITY 0x00000000U
+#define SDMMC_CHECK_PATTERN 0x000001AAU
+
+#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
+
+#define SDMMC_MAX_TRIAL 0x0000FFFFU
+
+#define SDMMC_ALLZERO 0x00000000U
+
+#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
+#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
+#define SDMMC_CARD_LOCKED 0x02000000U
+
+#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
+
+#define SDMMC_0TO7BITS 0x000000FFU
+#define SDMMC_8TO15BITS 0x0000FF00U
+#define SDMMC_16TO23BITS 0x00FF0000U
+#define SDMMC_24TO31BITS 0xFF000000U
+#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
+
+#define SDMMC_HALFFIFO 0x00000008U
+#define SDMMC_HALFFIFOBYTES 0x00000020U
+
+/**
+ * @brief Command Class supported
+ */
+#define SDIO_CCCC_ERASE 0x00000020U
+
+#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
+#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
+
+
+/** @defgroup SDIO_LL_Clock_Edge Clock Edge
+ * @{
+ */
+#define SDIO_CLOCK_EDGE_RISING 0x00000000U
+#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
+
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
+ ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
+ * @{
+ */
+#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
+#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
+
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
+ ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
+ * @{
+ */
+#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
+#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
+
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
+ ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Bus_Wide Bus Width
+ * @{
+ */
+#define SDIO_BUS_WIDE_1B 0x00000000U
+#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
+#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
+
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
+ ((WIDE) == SDIO_BUS_WIDE_4B) || \
+ ((WIDE) == SDIO_BUS_WIDE_8B))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
+ * @{
+ */
+#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
+#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
+
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
+ ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Clock_Division Clock Division
+ * @{
+ */
+#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Command_Index Command Index
+ * @{
+ */
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Response_Type Response Type
+ * @{
+ */
+#define SDIO_RESPONSE_NO 0x00000000U
+#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
+#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
+
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
+ ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
+ ((RESPONSE) == SDIO_RESPONSE_LONG))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
+ * @{
+ */
+#define SDIO_WAIT_NO 0x00000000U
+#define SDIO_WAIT_IT SDIO_CMD_WAITINT
+#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
+
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
+ ((WAIT) == SDIO_WAIT_IT) || \
+ ((WAIT) == SDIO_WAIT_PEND))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_CPSM_State CPSM State
+ * @{
+ */
+#define SDIO_CPSM_DISABLE 0x00000000U
+#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
+
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
+ ((CPSM) == SDIO_CPSM_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Response_Registers Response Register
+ * @{
+ */
+#define SDIO_RESP1 0x00000000U
+#define SDIO_RESP2 0x00000004U
+#define SDIO_RESP3 0x00000008U
+#define SDIO_RESP4 0x0000000CU
+
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
+ ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || \
+ ((RESP) == SDIO_RESP4))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Data_Length Data Lenght
+ * @{
+ */
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
+ * @{
+ */
+#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
+#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
+#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
+#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
+#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
+#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
+#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
+#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
+#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
+#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
+
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
+ * @{
+ */
+#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
+#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
+
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
+ ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Transfer_Type Transfer Type
+ * @{
+ */
+#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
+#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
+
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
+ ((MODE) == SDIO_TRANSFER_MODE_STREAM))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_DPSM_State DPSM State
+ * @{
+ */
+#define SDIO_DPSM_DISABLE 0x00000000U
+#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
+
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
+ ((DPSM) == SDIO_DPSM_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
+ * @{
+ */
+#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
+#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
+
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
+ ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
+ * @{
+ */
+#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
+#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
+#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
+#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
+#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
+#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
+#define SDIO_IT_CMDREND SDIO_STA_CMDREND
+#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
+#define SDIO_IT_DATAEND SDIO_STA_DATAEND
+#define SDIO_IT_STBITERR SDIO_STA_STBITERR
+#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
+#define SDIO_IT_CMDACT SDIO_STA_CMDACT
+#define SDIO_IT_TXACT SDIO_STA_TXACT
+#define SDIO_IT_RXACT SDIO_STA_RXACT
+#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
+#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
+#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
+#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
+#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
+#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
+#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
+#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
+#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
+#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Flags Flags
+ * @{
+ */
+#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
+#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
+#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
+#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
+#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
+#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
+#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
+#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
+#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
+#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
+#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
+#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
+#define SDIO_FLAG_TXACT SDIO_STA_TXACT
+#define SDIO_FLAG_RXACT SDIO_STA_RXACT
+#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
+#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
+#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
+#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
+#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
+#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
+#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
+#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
+#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
+#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
+#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
+ SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
+ SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
+ SDIO_FLAG_DBCKEND))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
+ * @{
+ */
+
+/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
+ * @{
+ */
+/* ------------ SDIO registers bit address in the alias region -------------- */
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
+#define CLKEN_BITNUMBER 0x08U
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
+
+/* --- CMD Register ---*/
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
+#define SDIOSUSPEND_BITNUMBER 0x0BU
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BITNUMBER 0x0CU
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BITNUMBER 0x0DU
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BITNUMBER 0x0EU
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
+
+/* --- DCTRL Register ---*/
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
+#define DMAEN_BITNUMBER 0x03U
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BITNUMBER 0x08U
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BITNUMBER 0x09U
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BITNUMBER 0x0AU
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BITNUMBER 0x0BU
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
+ * @brief SDIO_LL registers bit address in the alias region
+ * @{
+ */
+/* ---------------------- SDIO registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
+ SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
+ SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
+
+/* --- DCTRL Register ---*/
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
+ SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
+ SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
+ SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
+
+/* SDIO Initialization Frequency (400KHz max) */
+#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
+
+/* SDIO Data Transfer Frequency (25MHz max) */
+#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the SDIO device.
+ * @param __INSTANCE__ SDIO Instance
+ * @retval None
+ */
+#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
+
+/**
+ * @brief Disable the SDIO device.
+ * @param __INSTANCE__ SDIO Instance
+ * @retval None
+ */
+#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
+
+/**
+ * @brief Enable the SDIO DMA transfer.
+ * @param __INSTANCE__ SDIO Instance
+ * @retval None
+ */
+#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
+/**
+ * @brief Disable the SDIO DMA transfer.
+ * @param __INSTANCE__ SDIO Instance
+ * @retval None
+ */
+#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
+
+/**
+ * @brief Enable the SDIO device interrupt.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INTERRUPT__ specifies the SDIO interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the SDIO device interrupt.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INTERRUPT__ specifies the SDIO interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified SDIO flag is set or not.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval The new state of SDIO_FLAG (SET or RESET).
+ */
+#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+
+
+/**
+ * @brief Clears the SDIO pending flags.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval None
+ */
+#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INTERRUPT__ specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval The new state of SDIO_IT (SET or RESET).
+ */
+#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Clears the SDIO's interrupt pending bits.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+ * @brief Enable Start the SD I/O Read Wait operation.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @retval None
+ */
+#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
+
+/**
+ * @brief Disable Start the SD I/O Read Wait operations.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @retval None
+ */
+#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
+
+/**
+ * @brief Enable Start the SD I/O Read Wait operation.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @retval None
+ */
+#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
+
+/**
+ * @brief Disable Stop the SD I/O Read Wait operations.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @retval None
+ */
+#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
+
+/**
+ * @brief Enable the SD I/O Mode Operation.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @retval None
+ */
+#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
+
+/**
+ * @brief Disable the SD I/O Mode Operation.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @retval None
+ */
+#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
+
+/**
+ * @brief Enable the SD I/O Suspend command sending.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @retval None
+ */
+#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
+
+/**
+ * @brief Disable the SD I/O Suspend command sending.
+ * @param __INSTANCE__ Pointer to SDIO register base
+ * @retval None
+ */
+#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/**
+ * @brief Enable the command completion signal.
+ * @retval None
+ */
+#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
+
+/**
+ * @brief Disable the command completion signal.
+ * @retval None
+ */
+#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
+
+/**
+ * @brief Enable the CE-ATA interrupt.
+ * @retval None
+ */
+#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
+
+/**
+ * @brief Disable the CE-ATA interrupt.
+ * @retval None
+ */
+#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
+
+/**
+ * @brief Enable send CE-ATA command (CMD61).
+ * @retval None
+ */
+#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
+
+/**
+ * @brief Disable send CE-ATA command (CMD61).
+ * @retval None
+ */
+#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\
+ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDMMC_LL_Exported_Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+/** @addtogroup HAL_SDMMC_LL_Group1
+ * @{
+ */
+HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
+/**
+ * @}
+ */
+
+/* I/O operation functions *****************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group2
+ * @{
+ */
+uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group3
+ * @{
+ */
+HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
+uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
+uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
+uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
+uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
+uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
+
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
+
+/* SDMMC Commands management functions */
+uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
+uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
+
+uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_SDMMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,640 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_spi.c
+ * @author MCD Application Team
+ * @brief SPI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_spi.h"
+#include "stm32f4xx_ll_bus.h"
+#include "stm32f4xx_ll_rcc.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
+
+/** @addtogroup SPI_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+ * @{
+ */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
+ SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
+ SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
+ SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
+ SPI_CR1_BIDIMODE)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+ * @{
+ */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
+ || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+ || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+ || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+ || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+ || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+ if (SPIx == SPI1)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ status = SUCCESS;
+ }
+#endif /* SPI1 */
+#if defined(SPI2)
+ if (SPIx == SPI2)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ status = SUCCESS;
+ }
+#endif /* SPI2 */
+#if defined(SPI3)
+ if (SPIx == SPI3)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ status = SUCCESS;
+ }
+#endif /* SPI3 */
+#if defined(SPI4)
+ if (SPIx == SPI4)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+ status = SUCCESS;
+ }
+#endif /* SPI4 */
+#if defined(SPI5)
+ if (SPIx == SPI5)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
+
+ status = SUCCESS;
+ }
+#endif /* SPI5 */
+#if defined(SPI6)
+ if (SPIx == SPI6)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
+
+ status = SUCCESS;
+ }
+#endif /* SPI6 */
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the SPI Instance SPIx*/
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+ /* Check the SPI parameters from SPI_InitStruct*/
+ assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+ assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+ assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+ assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+ assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+ assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+ assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+ assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+ if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx CR1 Configuration ------------------------
+ * Configure SPIx CR1 with parameters:
+ * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+ * - Master/Slave Mode: SPI_CR1_MSTR bit
+ * - DataWidth: SPI_CR1_DFF bit
+ * - ClockPolarity: SPI_CR1_CPOL bit
+ * - ClockPhase: SPI_CR1_CPHA bit
+ * - NSS management: SPI_CR1_SSM bit
+ * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+ * - BitOrder: SPI_CR1_LSBFIRST bit
+ * - CRCCalculation: SPI_CR1_CRCEN bit
+ */
+ MODIFY_REG(SPIx->CR1,
+ SPI_CR1_CLEAR_MASK,
+ SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
+ SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+ SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+ SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+ /*---------------------------- SPIx CR2 Configuration ------------------------
+ * Configure SPIx CR2 with parameters:
+ * - NSS management: SSOE bit
+ */
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
+
+ /*---------------------------- SPIx CRCPR Configuration ----------------------
+ * Configure SPIx CRCPR with parameters:
+ * - CRCPoly: CRCPOLY[15:0] bits
+ */
+ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+ LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ }
+ status = SUCCESS;
+ }
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ /* Set SPI_InitStruct fields to default values */
+ SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
+ SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
+ SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct->CRCPoly = 7U;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+ * @{
+ */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK 0x0002U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+ * @{
+ */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
+ || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
+ || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+ || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
+ && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+ || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI/I2S registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_DeInit(SPIx);
+}
+
+/**
+ * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are Initialized
+ * - ERROR: SPI registers are not Initialized
+ */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+ uint32_t tmp = 0U;
+ uint32_t sourceclock = 0U;
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+ assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(SPIx->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD);
+
+ /*---------------------------- SPIx I2SPR Configuration ----------------------
+ * Configure SPIx I2SPR with parameters:
+ * - MCLKOutput: SPI_I2SPR_MCKOE bit
+ * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+ */
+
+ /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+ * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
+ */
+ if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing)
+ * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+ */
+ if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2U;
+ }
+
+ /* If an external I2S clock has to be used, the specific define should be set
+ in the project configuration or in the stm32f4xx_ll_rcc.h file */
+ /* Get the I2S source clock value */
+ sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t)(i2sodd << 8U);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
+ I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
+ I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
+ I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
+ I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
+ I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
+}
+
+/**
+ * @brief Set linear and parity prescaler.
+ * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+ * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+ assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+ /* Write to SPIx I2SPR */
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+/**
+ * @brief Configures the full duplex mode for the I2Sx peripheral using its extension
+ * I2Sxext according to the specified parameters in the I2S_InitStruct.
+ * @note The structure pointed by I2S_InitStruct parameter should be the same
+ * used for the master I2S peripheral. In this case, if the master is
+ * configured as transmitter, the slave will be receiver and vice versa.
+ * Or you can force a different mode by modifying the field I2S_Mode to the
+ * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
+ * @param I2Sxext SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2Sxext registers are Initialized
+ * - ERROR: I2Sxext registers are not Initialized
+ */
+ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint16_t mode = 0U;
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Reset I2SPR registers */
+ WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
+
+ /* Get the mode to be configured for the extended I2S */
+ if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
+ {
+ mode = LL_I2S_MODE_SLAVE_RX;
+ }
+ else
+ {
+ if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
+ {
+ mode = LL_I2S_MODE_SLAVE_TX;
+ }
+ }
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(I2Sxext->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD | mode);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2036 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_SPI_H
+#define __STM32F4xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
+
+/** @defgroup SPI_LL SPI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief SPI Init structures definition
+ */
+typedef struct
+{
+ uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+ uint32_t DataWidth; /*!< Specifies the SPI data width.
+ This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+ @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+ This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_SPI_ReadReg function
+ * @{
+ */
+#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
+#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
+#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
+#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
+#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
+#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+ * @{
+ */
+#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
+#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ * @{
+ */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+ * @{
+ */
+#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ * @{
+ */
+#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
+#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
+#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+ * @{
+ */
+#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
+#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
+#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
+#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ * @{
+ */
+#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable SPI peripheral
+ * @rmtoll CR1 SPE LL_SPI_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Disable SPI peripheral
+ * @note When disabling the SPI, follow the procedure described in the Reference Manual.
+ * @rmtoll CR1 SPE LL_SPI_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Check if SPI peripheral is enabled
+ * @rmtoll CR1 SPE LL_SPI_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
+}
+
+/**
+ * @brief Set SPI operation mode to Master or Slave
+ * @note This bit should not be changed when communication is ongoing.
+ * @rmtoll CR1 MSTR LL_SPI_SetMode\n
+ * CR1 SSI LL_SPI_SetMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+ * @brief Get SPI operation mode (Master or Slave)
+ * @rmtoll CR1 MSTR LL_SPI_GetMode\n
+ * CR1 SSI LL_SPI_GetMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+/**
+ * @brief Set serial protocol used
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR2 FRF LL_SPI_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+}
+
+/**
+ * @brief Get serial protocol used
+ * @rmtoll CR2 FRF LL_SPI_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+}
+
+/**
+ * @brief Set clock phase
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
+ * @param SPIx SPI Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Get clock phase
+ * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+ * @brief Set clock polarity
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Get clock polarity
+ * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+ * @brief Set baud rate prescaler
+ * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+ * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @param BaudRate This parameter can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+ * @brief Get baud rate prescaler
+ * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+ * @brief Set transfer bit order
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Get transfer bit order
+ * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+ * @brief Set transfer direction mode
+ * @note For Half-Duplex mode, Rx Direction is set by default.
+ * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+ * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_SetTransferDirection
+ * @param SPIx SPI Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+ * @brief Get transfer direction mode
+ * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_GetTransferDirection
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+ * @brief Set frame data width
+ * @rmtoll CR1 DFF LL_SPI_SetDataWidth
+ * @param SPIx SPI Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
+}
+
+/**
+ * @brief Get frame data width
+ * @rmtoll CR1 DFF LL_SPI_GetDataWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+ * @{
+ */
+
+/**
+ * @brief Enable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Disable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Check if CRC is enabled
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
+}
+
+/**
+ * @brief Set CRCNext to transfer CRC on the line
+ * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
+ * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+ * @brief Set polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+ WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+ * @brief Get polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+ * @brief Get Rx CRC
+ * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+ * @brief Get Tx CRC
+ * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+ * @{
+ */
+
+/**
+ * @brief Set NSS mode
+ * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+ * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
+ * @param SPIx SPI Instance
+ * @param NSS This parameter can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+ * @brief Get NSS mode
+ * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+ register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
+ return (Ssm | Ssoe);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
+}
+
+/**
+ * @brief Get CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
+}
+
+/**
+ * @brief Get mode fault error flag
+ * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
+}
+
+/**
+ * @brief Get busy flag
+ * @note The BSY flag is cleared under any one of the following conditions:
+ * -When the SPI is correctly disabled
+ * -When a fault is detected in Master mode (MODF bit set to 1)
+ * -In Master mode, when it finishes a data transmission and no new data is ready to be
+ * sent
+ * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+ * each data transfer.
+ * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
+}
+
+/**
+ * @brief Clear CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+ * @brief Clear mode fault error flag
+ * @note Clearing this flag is done by a read access to the SPIx_SR
+ * register followed by a write access to the SPIx_CR1 register
+ * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+ tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @note Clearing this flag is done by a read access to the SPIx_DR
+ * register followed by a read access to the SPIx_SR register
+ * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->DR;
+ (void) tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @note Clearing this flag is done by reading SPIx_SR register
+ * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Enable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Enable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Disable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Disable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Disable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Check if error interrupt is enabled
+ * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
+}
+
+/**
+ * @brief Check if Rx buffer not empty interrupt is enabled
+ * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
+}
+
+/**
+ * @brief Check if Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
+ * @param SPIx SPI Instance
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+ return (uint32_t) & (SPIx->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData8
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+ return (uint8_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Read 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Write 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData8
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+ SPIx->DR = TxData;
+}
+
+/**
+ * @brief Write 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+ SPIx->DR = TxData;
+}
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL I2S
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_LL_EC_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
+
+ This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+
+ Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
+ and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+
+
+ uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_LL_EC_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+ * @{
+ */
+
+/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2S_ReadReg function
+ * @{
+ */
+#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
+#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
+#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
+#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+ * @{
+ */
+#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
+#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_STANDARD I2s Standard
+ * @{
+ */
+#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
+#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
+#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
+#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
+#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
+#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
+#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
+#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+ * @{
+ */
+#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
+#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+ * @{
+ */
+#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+ * @{
+ */
+
+#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
+#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
+#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
+#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
+#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
+#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
+#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
+#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
+#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
+#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Select I2S mode and Enable I2S peripheral
+ * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
+ * I2SCFGR I2SE LL_I2S_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Disable I2S peripheral
+ * @rmtoll I2SCFGR I2SE LL_I2S_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Check if I2S peripheral is enabled
+ * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
+}
+
+/**
+ * @brief Set I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_SetDataFormat
+ * @param SPIx SPI Instance
+ * @param DataFormat This parameter can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
+}
+
+/**
+ * @brief Get I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_GetDataFormat
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
+}
+
+/**
+ * @brief Set I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ SET_BIT(SPIx->I2SCFGR, ClockPolarity);
+}
+
+/**
+ * @brief Get I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+ * @brief Set I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+ * @brief Get I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+ * @brief Set I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
+}
+
+/**
+ * @brief Get I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+ * @brief Set I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
+}
+
+/**
+ * @brief Get I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
+}
+
+/**
+ * @brief Set I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
+ * @param SPIx SPI Instance
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
+}
+
+/**
+ * @brief Get I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
+}
+
+/**
+ * @brief Enable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Disable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Check if the master clock ouput (Pin MCK) is enabled
+ * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
+}
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+/**
+ * @brief Enable asynchronous start
+ * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+ * @brief Disable asynchronous start
+ * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+ * @brief Check if asynchronous start is enabled
+ * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
+}
+#endif /* SPI_I2SCFGR_ASTRTEN */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_FLAG FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_TXE(SPIx);
+}
+
+/**
+ * @brief Get busy flag
+ * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_BSY(SPIx);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Get underrun error flag
+ * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_FRE(SPIx);
+}
+
+/**
+ * @brief Get channel side flag.
+ * @note 0: Channel Left has to be transmitted or has been received\n
+ * 1: Channel Right has to be transmitted or has been received\n
+ * It has no significance in PCM mode.
+ * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Clear underrun error flag
+ * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void)tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_FRE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_IT Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Enable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Enable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Disable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Disable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Disable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Check if ERR IT is enabled
+ * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_ERR(SPIx);
+}
+
+/**
+ * @brief Check if RXNE IT is enabled
+ * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if TXE IT is enabled
+ * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_TXE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DMA DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DATA DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+ * @brief Write 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+ LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1726 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_system.h
+ * @author MCD Application Team
+ * @brief Header file of SYSTEM LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL SYSTEM driver contains a set of generic APIs that can be
+ used by user:
+ (+) Some of the FLASH features need to be handled in the SYSTEM file.
+ (+) Access to DBGCMU registers
+ (+) Access to SYSCFG registers
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_SYSTEM_H
+#define __STM32F4xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+* @{
+*/
+#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
+#if defined(FSMC_Bank1)
+#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */
+#endif /* FSMC_Bank1 */
+#if defined(FMC_Bank1)
+#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /*!< FMC/SDRAM mapped at 0x00000000 */
+#endif /* FMC_Bank1 */
+#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
+
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_PMC_MII_RMII_SEL)
+ /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
+* @{
+*/
+#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /*!< ETH Media MII interface */
+#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */
+
+/**
+ * @}
+ */
+#endif /* SYSCFG_PMC_MII_RMII_SEL */
+
+
+
+#if defined(SYSCFG_MEMRMP_UFB_MODE)
+/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
+ * @{
+ */
+#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
+ and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
+#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
+ and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
+/**
+ * @}
+ */
+#endif /* SYSCFG_MEMRMP_UFB_MODE */
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+ * @{
+ */
+#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/
+#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+ * @{
+ */
+#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */
+#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */
+#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */
+#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */
+#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */
+#if defined(GPIOF)
+#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */
+#endif /* GPIOG */
+#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /*!< EXTI PORT H */
+#if defined(GPIOI)
+#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /*!< EXTI PORT I */
+#endif /* GPIOI */
+#if defined(GPIOJ)
+#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /*!< EXTI PORT J */
+#endif /* GPIOJ */
+#if defined(GPIOK)
+#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /*!< EXTI PORT k */
+#endif /* GPIOK */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+ * @{
+ */
+#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+ * @{
+ */
+#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
+#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4
+ with Break Input of TIM1/8 */
+#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input
+ and also the PVDE and PLS bits of the Power Control Interface */
+#endif /* SYSCFG_CFGR2_CLL */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
+ * @{
+ */
+#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
+#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN
+ * @{
+ */
+#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN
+#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL
+#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL
+
+#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)
+#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL
+#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL
+
+#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)
+#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
+ * @{
+ */
+#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
+ * @{
+ */
+#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
+/**
+ * @}
+ */
+/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
+ * @{
+ */
+#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
+/**
+ * @}
+ */
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ * @{
+ */
+#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ * @{
+ */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
+#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /*!< LPTIM counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
+#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
+#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
+#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
+#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
+#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ * @{
+ */
+#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
+#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
+#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
+#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
+#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
+#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
+#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
+#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
+#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
+#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+ * @{
+ */
+/**
+ * @brief Set memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
+ * @param Memory This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FSMC (*)
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
+{
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
+}
+
+/**
+ * @brief Get memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FSMC (*)
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
+}
+
+#if defined(SYSCFG_MEMRMP_SWP_FMC)
+/**
+ * @brief Enables the FMC Memory Mapping Swapping
+ * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
+ * @note SDRAM is accessible at 0x60000000 and NOR/RAM
+ * is accessible at 0xC0000000
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
+{
+ SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
+}
+
+/**
+ * @brief Disables the FMC Memory Mapping Swapping
+ * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
+ * @note SDRAM is accessible at 0xC0000000 (default mapping)
+ * and NOR/RAM is accessible at 0x60000000 (default mapping)
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
+{
+ CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
+}
+
+#endif /* SYSCFG_MEMRMP_SWP_FMC */
+/**
+ * @brief Enables the Compensation cell Power Down
+ * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
+ * @note The I/O compensation cell can be used only when the device supply
+ * voltage ranges from 2.4 to 3.6 V
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
+{
+ SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+}
+
+/**
+ * @brief Disables the Compensation cell Power Down
+ * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
+ * @note The I/O compensation cell can be used only when the device supply
+ * voltage ranges from 2.4 to 3.6 V
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
+{
+ CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+}
+
+/**
+ * @brief Get Compensation Cell ready Flag
+ * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
+{
+ return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
+}
+
+#if defined(SYSCFG_PMC_MII_RMII_SEL)
+/**
+ * @brief Select Ethernet PHY interface
+ * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
+ * @param Interface This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_PMC_ETHMII
+ * @arg @ref LL_SYSCFG_PMC_ETHRMII
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
+{
+ MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
+}
+
+/**
+ * @brief Get Ethernet PHY interface
+ * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_PMC_ETHMII
+ * @arg @ref LL_SYSCFG_PMC_ETHRMII
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
+}
+#endif /* SYSCFG_PMC_MII_RMII_SEL */
+
+
+
+#if defined(SYSCFG_MEMRMP_UFB_MODE)
+/**
+ * @brief Select Flash bank mode (Bank flashed at 0x08000000)
+ * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode
+ * @param Bank This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK1
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK2
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
+{
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
+}
+
+/**
+ * @brief Get Flash bank mode (Bank flashed at 0x08000000)
+ * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK1
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK2
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
+}
+#endif /* SYSCFG_MEMRMP_UFB_MODE */
+
+#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
+}
+#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
+
+/**
+ * @brief Configure source input for the EXTI external interrupt.
+ * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE
+ * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTH
+ *
+ * (*) value not defined in all devices
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+ MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
+}
+
+/**
+ * @brief Get the configured defined for specific EXTI Line
+ * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE
+ * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTH
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
+}
+
+#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
+/**
+ * @brief Set connections to TIM1/8 break inputs
+ * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
+ * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
+ * @param Break This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+ MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);
+}
+
+/**
+ * @brief Get connections to TIM1/8 Break inputs
+ * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
+ * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));
+}
+#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+/**
+ * @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
+ * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
+ * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
+}
+/**
+ * @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
+ * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
+ * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
+}
+/**
+ * @brief Enables the DFSDM1 or DFSDM2 Delay clock
+ * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock
+ * @param MCHDLY This paramater can be one of the following values
+ * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
+ * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
+{
+ SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
+}
+
+/**
+ * @brief Disables the DFSDM1 or the DFSDM2 Delay clock
+ * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock
+ * @param MCHDLY This paramater can be one of the following values
+ * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
+ * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
+{
+ CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
+}
+
+/**
+ * @brief Select the source for DFSDM1 or DFSDM2 DatIn0
+ * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
+}
+/**
+ * @brief Get the source for DFSDM1 or DFSDM2 DatIn0.
+ * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn0
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn0
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
+}
+/**
+ * @brief Select the source for DFSDM1 or DFSDM2 DatIn2
+ * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
+}
+/**
+ * @brief Get the source for DFSDM1 or DFSDM2 DatIn2.
+ * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn2
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
+ * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
+}
+
+/**
+ * @brief Select the distribution of the bitsream lock gated by TIM4 OC2
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
+ * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
+}
+/**
+ * @brief Get the distribution of the bitsream lock gated by TIM4 OC2
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
+ * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
+}
+
+/**
+ * @brief Select the distribution of the bitsream lock gated by TIM4 OC1
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
+ * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
+}
+/**
+ * @brief Get the distribution of the bitsream lock gated by TIM4 OC1
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
+ * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
+}
+
+/**
+ * @brief Select the DFSDM1 Clock In
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
+ * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
+}
+/**
+ * @brief GET the DFSDM1 Clock In
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
+ * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
+}
+
+/**
+ * @brief Select the DFSDM1 Clock Out
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_CKOUT
+ * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
+}
+/**
+ * @brief GET the DFSDM1 Clock Out
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM1_CKOUT
+ * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
+}
+
+/**
+ * @brief Enables the DFSDM2 Delay clock
+ * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
+{
+ SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
+}
+
+/**
+ * @brief Disables the DFSDM2 Delay clock
+ * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
+{
+ CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
+}
+/**
+ * @brief Select the source for DFSDM2 DatIn0
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
+}
+/**
+ * @brief Get the source for DFSDM2 DatIn0.
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
+}
+
+/**
+ * @brief Select the source for DFSDM2 DatIn2
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
+}
+/**
+ * @brief Get the source for DFSDM2 DatIn2.
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
+}
+
+/**
+ * @brief Select the source for DFSDM2 DatIn4
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
+}
+/**
+ * @brief Get the source for DFSDM2 DatIn4.
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
+}
+
+/**
+ * @brief Select the source for DFSDM2 DatIn6
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
+}
+/**
+ * @brief Get the source for DFSDM2 DatIn6.
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
+}
+
+/**
+ * @brief Select the distribution of the bitsream lock gated by TIM3 OC4
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
+}
+/**
+ * @brief Get the distribution of the bitsream lock gated by TIM3 OC4
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
+}
+
+/**
+ * @brief Select the distribution of the bitsream lock gated by TIM3 OC3
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
+}
+/**
+ * @brief Get the distribution of the bitsream lock gated by TIM3 OC4
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
+}
+
+/**
+ * @brief Select the distribution of the bitsream lock gated by TIM3 OC2
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
+}
+/**
+ * @brief Get the distribution of the bitsream lock gated by TIM3 OC2
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
+}
+
+/**
+ * @brief Select the distribution of the bitsream lock gated by TIM3 OC1
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
+}
+/**
+ * @brief Get the distribution of the bitsream lock gated by TIM3 OC1
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
+ * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
+}
+
+/**
+ * @brief Select the DFSDM2 Clock In
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
+}
+/**
+ * @brief GET the DFSDM2 Clock In
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
+ * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
+}
+
+/**
+ * @brief Select the DFSDM2 Clock Out
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_CKOUT
+ * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
+{
+ MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
+}
+/**
+ * @brief GET the DFSDM2 Clock Out
+ * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_DFSDM2_CKOUT
+ * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
+}
+
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
+/**
+ * @}
+ */
+
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ * @{
+ */
+
+/**
+ * @brief Return the device identifier
+ * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
+ * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
+ * @note For STM32F401xx devices, the device ID is 0x423
+ * @note For STM32F401xx devices, the device ID is 0x433
+ * @note For STM32F411xx devices, the device ID is 0x431
+ * @note For STM32F410xx devices, the device ID is 0x458
+ * @note For STM32F412xx devices, the device ID is 0x441
+ * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
+ * @note For STM32F446xx devices, the device ID is 0x421
+ * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
+ * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+ * @brief Return the device revision identifier
+ * @note This field indicates the revision of the device.
+ For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
+ For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
+ For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
+ For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
+ For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
+ For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
+ * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Set Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
+ * @param PinAssignment This parameter can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+ MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+ * @brief Get Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+ * @brief Freeze APB2 peripherals
+ * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB2 peripherals
+ * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ * @{
+ */
+
+/**
+ * @brief Set FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
+ * @param Latency This parameter can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @arg @ref LL_FLASH_LATENCY_3
+ * @arg @ref LL_FLASH_LATENCY_4
+ * @arg @ref LL_FLASH_LATENCY_5
+ * @arg @ref LL_FLASH_LATENCY_6
+ * @arg @ref LL_FLASH_LATENCY_7
+ * @arg @ref LL_FLASH_LATENCY_8
+ * @arg @ref LL_FLASH_LATENCY_9
+ * @arg @ref LL_FLASH_LATENCY_10
+ * @arg @ref LL_FLASH_LATENCY_11
+ * @arg @ref LL_FLASH_LATENCY_12
+ * @arg @ref LL_FLASH_LATENCY_13
+ * @arg @ref LL_FLASH_LATENCY_14
+ * @arg @ref LL_FLASH_LATENCY_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+ * @brief Get FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @arg @ref LL_FLASH_LATENCY_3
+ * @arg @ref LL_FLASH_LATENCY_4
+ * @arg @ref LL_FLASH_LATENCY_5
+ * @arg @ref LL_FLASH_LATENCY_6
+ * @arg @ref LL_FLASH_LATENCY_7
+ * @arg @ref LL_FLASH_LATENCY_8
+ * @arg @ref LL_FLASH_LATENCY_9
+ * @arg @ref LL_FLASH_LATENCY_10
+ * @arg @ref LL_FLASH_LATENCY_11
+ * @arg @ref LL_FLASH_LATENCY_12
+ * @arg @ref LL_FLASH_LATENCY_13
+ * @arg @ref LL_FLASH_LATENCY_14
+ * @arg @ref LL_FLASH_LATENCY_15
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+ * @brief Enable Prefetch
+ * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+ * @brief Disable Prefetch
+ * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+ * @brief Check if Prefetch buffer is enabled
+ * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
+}
+
+/**
+ * @brief Enable Instruction cache
+ * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+ * @brief Disable Instruction cache
+ * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+ * @brief Enable Data cache
+ * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+ * @brief Disable Data cache
+ * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+ * @brief Enable Instruction cache reset
+ * @note bit can be written only when the instruction cache is disabled
+ * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+ * @brief Disable Instruction cache reset
+ * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+ * @brief Enable Data cache reset
+ * @note bit can be written only when the data cache is disabled
+ * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+ * @brief Disable Data cache reset
+ * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_SYSTEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1196 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_tim.c
+ * @author MCD Application Team
+ * @brief TIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_tim.h"
+#include "stm32f4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
+
+/** @addtogroup TIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+ * @{
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set TIMx registers to their reset values.
+ * @param TIMx Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: invalid TIMx instance
+ */
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+ }
+#if defined(TIM2)
+ else if (TIMx == TIM2)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+ }
+#endif
+#if defined(TIM3)
+ else if (TIMx == TIM3)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+ }
+#endif
+#if defined(TIM4)
+ else if (TIMx == TIM4)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+ }
+#endif
+#if defined(TIM5)
+ else if (TIMx == TIM5)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+ }
+#endif
+#if defined(TIM6)
+ else if (TIMx == TIM6)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+ }
+#endif
+#if defined (TIM7)
+ else if (TIMx == TIM7)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+ }
+#endif
+#if defined(TIM8)
+ else if (TIMx == TIM8)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+ }
+#endif
+#if defined(TIM9)
+ else if (TIMx == TIM9)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
+ }
+#endif
+#if defined(TIM10)
+ else if (TIMx == TIM10)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
+ }
+#endif
+#if defined(TIM11)
+ else if (TIMx == TIM11)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
+ }
+#endif
+#if defined(TIM12)
+ else if (TIMx == TIM12)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
+ }
+#endif
+#if defined(TIM13)
+ else if (TIMx == TIM13)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
+ }
+#endif
+#if defined(TIM14)
+ else if (TIMx == TIM14)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
+ }
+#endif
+ else
+ {
+ result = ERROR;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the time base unit configuration data structure
+ * to their default values.
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+ * @retval None
+ */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
+ TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
+ TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
+ TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
+}
+
+/**
+ * @brief Configure the TIMx time base unit.
+ * @param TIMx Timer Instance
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ uint32_t tmpcr1 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+ assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+ tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+ }
+
+ /* Write to TIMx CR1 */
+ LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+ /* Set the Autoreload value */
+ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+ /* Set the Prescaler value */
+ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter value (if applicable) immediately */
+ LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx output channel configuration data
+ * structure to their default values.
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
+ TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->CompareValue = 0x00000000U;
+ TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
+ TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+ * @brief Configure the TIMx output channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = OC1Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = OC2Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = OC3Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = OC4Config(TIMx, TIM_OC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the TIMx input channel configuration data
+ * structure to their default values.
+ * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the TIMx input channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = IC1Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = IC2Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = IC3Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = IC4Config(TIMx, TIM_IC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Fills each TIM_EncoderInitStruct field with its default value
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
+ * @retval None
+ */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ /* Set the default configuration */
+ TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
+ TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the encoder interface of the timer instance.
+ * @param TIMx Timer Instance
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Configure TI1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure TI2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+ /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Set encoder mode */
+ LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx Hall sensor interface configuration data
+ * structure to their default values.
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
+ * @retval None
+ */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ /* Set the default configuration */
+ TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_HallSensorInitStruct->CommutationDelay = 0U;
+}
+
+/**
+ * @brief Configure the Hall sensor interface of the timer instance.
+ * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+ * to the TI1 input channel
+ * @note TIMx slave mode controller is configured in reset mode.
+ Selected internal trigger is TI1F_ED.
+ * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+ * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+ * between 2 changes on the inputs. It gives information about motor speed.
+ * @note Channel 2 is configured in output PWM 2 mode.
+ * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+ * @note OC2REF is selected as trigger output on TRGO.
+ * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+ * when TIMx operates in Hall sensor interface mode.
+ * @param TIMx Timer Instance
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpsmcr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+ /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+ tmpcr2 |= TIM_CR2_TI1S;
+
+ /* OC2REF signal is used as trigger output (TRGO) */
+ tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+ /* Configure the slave mode controller */
+ tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+ tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+ /* Configure input channel 1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure input channel 2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
+ tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+ /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx SMCR */
+ LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ /* Write to TIMx CCR2 */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the Break and Dead Time configuration data structure
+ * to their default values.
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @retval None
+ */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
+ TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
+ TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
+ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+ * @brief Configure the Break and Dead Time feature of the timer instance.
+ * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
+ * depending on the LOCK configuration, it can be necessary to configure all of
+ * them during the first write access to the TIMx_BDTR register.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @param TIMx Timer Instance
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Break and Dead Time is initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ uint32_t tmpbdtr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+ assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+ assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+ assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+
+ /* Set TIMx_BDTR */
+ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+ return SUCCESS;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ * @brief Private functions
+ * @{
+ */
+/**
+ * @brief Configure the TIMx output channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+ /* Set the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+
+/**
+ * @brief Configure the TIMx input channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+ (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+ ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC3E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+ ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+ ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+ return SUCCESS;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,3969 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_TIM_H
+#define __STM32F4xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
+
+/** @defgroup TIM_LL TIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+ * @{
+ */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+ 0x00U, /* 0: TIMx_CH1 */
+ 0x00U, /* 1: TIMx_CH1N */
+ 0x00U, /* 2: TIMx_CH2 */
+ 0x00U, /* 3: TIMx_CH2N */
+ 0x04U, /* 4: TIMx_CH3 */
+ 0x04U, /* 5: TIMx_CH3N */
+ 0x04U /* 6: TIMx_CH4 */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+ 0U, /* 0: OC1M, OC1FE, OC1PE */
+ 0U, /* 1: - NA */
+ 8U, /* 2: OC2M, OC2FE, OC2PE */
+ 0U, /* 3: - NA */
+ 0U, /* 4: OC3M, OC3FE, OC3PE */
+ 0U, /* 5: - NA */
+ 8U /* 6: OC4M, OC4FE, OC4PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+ 0U, /* 0: CC1S, IC1PSC, IC1F */
+ 0U, /* 1: - NA */
+ 8U, /* 2: CC2S, IC2PSC, IC2F */
+ 0U, /* 3: - NA */
+ 0U, /* 4: CC3S, IC3PSC, IC3F */
+ 0U, /* 5: - NA */
+ 8U /* 6: CC4S, IC4PSC, IC4F */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+ 0U, /* 0: CC1P */
+ 2U, /* 1: CC1NP */
+ 4U, /* 2: CC2P */
+ 6U, /* 3: CC2NP */
+ 8U, /* 4: CC3P */
+ 10U, /* 5: CC3NP */
+ 12U /* 6: CC4P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+ 0U, /* 0: OIS1 */
+ 1U, /* 1: OIS1N */
+ 2U, /* 2: OIS2 */
+ 3U, /* 3: OIS2N */
+ 4U, /* 4: OIS3 */
+ 5U, /* 5: OIS3N */
+ 6U /* 6: OIS4 */
+};
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ * @{
+ */
+
+
+/* Remap mask definitions */
+#define TIMx_OR_RMP_SHIFT 16U
+#define TIMx_OR_RMP_MASK 0x0000FFFFU
+#define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
+#define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
+#define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7FU)
+#define DT_DELAY_2 ((uint8_t)0x3FU)
+#define DT_DELAY_3 ((uint8_t)0x1FU)
+#define DT_DELAY_4 ((uint8_t)0x1FU)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00U)
+#define DT_RANGE_2 ((uint8_t)0x80U)
+#define DT_RANGE_3 ((uint8_t)0xC0U)
+#define DT_RANGE_4 ((uint8_t)0xE0U)
+
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ * @{
+ */
+/** @brief Convert channel id into channel index.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval none
+ */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
+
+/** @brief Calculate the deadtime sampling period(in ps).
+ * @param __TIMCLK__ timer input clock frequency (in Hz).
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval none
+ */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base configuration structure definition.
+ */
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
+
+ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+ Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
+
+ uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the output mode.
+ This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
+
+ uint32_t OCState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture configuration structure definition.
+ */
+
+typedef struct
+{
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t ICActiveInput; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+ * @brief TIM Encoder interface configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
+ This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+ * @brief TIM Hall sensor interface configuration structure definition.
+ */
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ Prescaler must be set to get a maximum counter period longer than the
+ time interval between 2 consecutive changes on the Hall inputs.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+ A positive pulse (TRGO event) is generated with a programmable delay every time
+ a change occurs on the Hall inputs.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+ * @brief BDTR (Break and Dead Time) structure definition
+ */
+typedef struct
+{
+ uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+ uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+ @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
+ has been written, their content is frozen until the next reset.*/
+
+ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
+
+ @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
+
+ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_TIM_ReadReg function.
+ * @{
+ */
+#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
+#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ * @{
+ */
+#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ * @{
+ */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
+ * @{
+ */
+#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ * @{
+ */
+#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ * @{
+ */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ * @{
+ */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+ * @{
+ */
+#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+ * @{
+ */
+#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
+ * @{
+ */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+ * @{
+ */
+#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+ * @{
+ */
+#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+ * @{
+ */
+#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+ * @{
+ */
+#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+ * @{
+ */
+#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+ * @{
+ */
+#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+ * @{
+ */
+#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+ * @{
+ */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+ * @{
+ */
+#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+ * @{
+ */
+#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+ * @{
+ */
+#define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+ * @{
+ */
+#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+ * @{
+ */
+#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+ * @{
+ */
+#define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+ * @{
+ */
+#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+ * @{
+ */
+#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+ * @{
+ */
+#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+ * @{
+ */
+#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+ * @{
+ */
+#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+ * @{
+ */
+#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
+/**
+ * @}
+ */
+
+
+
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+ * @{
+ */
+#define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+ * @{
+ */
+#define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+ * @{
+ */
+#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+ * @{
+ */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
+ * @{
+ */
+#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
+#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
+#define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
+ * @{
+ */
+#define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */
+#define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */
+#define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */
+#define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
+ * @{
+ */
+#define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
+#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
+#define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
+#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+/**
+ * @brief Write a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+ * @{
+ */
+
+/**
+ * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+ * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @param __DT__ deadtime duration (in ns)
+ * @retval DTG[0:7]
+ */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
+ 0U)
+
+/**
+ * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+ * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CNTCLK__ counter clock frequency (in Hz)
+ * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
+ ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+ * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
+ * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
+((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
+ * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro retrieving the ratio of the input capture prescaler
+ * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+ * @param __ICPSC__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+ */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+ * @{
+ */
+/**
+ * @brief Enable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_EnableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Disable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_DisableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Indicates whether the timer counter is enabled.
+ * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
+}
+
+/**
+ * @brief Enable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Disable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Indicates whether update event generation is enabled.
+ * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
+ * @param TIMx Timer instance
+ * @retval Inverted state of bit (0 or 1).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
+}
+
+/**
+ * @brief Set update event source
+ * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+ * generate an update interrupt or DMA request if enabled:
+ * - Counter overflow/underflow
+ * - Setting the UG bit
+ * - Update generation through the slave mode controller
+ * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+ * overflow/underflow generates an update interrupt or DMA request if enabled.
+ * @rmtoll CR1 URS LL_TIM_SetUpdateSource
+ * @param TIMx Timer instance
+ * @param UpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+ * @brief Get actual event update source
+ * @rmtoll CR1 URS LL_TIM_GetUpdateSource
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+ * @brief Set one pulse mode (one shot v.s. repetitive).
+ * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
+ * @param TIMx Timer instance
+ * @param OnePulseMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+ * @brief Get actual one pulse mode.
+ * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+ * @brief Set the timer counter counting mode.
+ * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
+ * CR1 CMS LL_TIM_SetCounterMode
+ * @param TIMx Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
+}
+
+/**
+ * @brief Get actual counter mode.
+ * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
+ * CR1 CMS LL_TIM_GetCounterMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+}
+
+/**
+ * @brief Enable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Disable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Indicates whether auto-reload (ARR) preload is enabled.
+ * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
+}
+
+/**
+ * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_SetClockDivision
+ * @param TIMx Timer instance
+ * @param ClockDivision This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+ * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_GetClockDivision
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+ * @brief Set the counter value.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @rmtoll CNT CNT LL_TIM_SetCounter
+ * @param TIMx Timer instance
+ * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+ WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+ * @brief Get the counter value.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @rmtoll CNT CNT LL_TIM_GetCounter
+ * @param TIMx Timer instance
+ * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+ * @brief Get the current direction of the counter
+ * @rmtoll CR1 DIR LL_TIM_GetDirection
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERDIRECTION_UP
+ * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+ * @brief Set the prescaler value.
+ * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+ * @note The prescaler can be changed on the fly as this control register is buffered. The new
+ * prescaler ratio is taken into account at the next update event.
+ * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+ * @rmtoll PSC PSC LL_TIM_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Prescaler between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+ WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+ * @brief Get the prescaler value.
+ * @rmtoll PSC PSC LL_TIM_GetPrescaler
+ * @param TIMx Timer instance
+ * @retval Prescaler value between Min_Data=0 and Max_Data=65535
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+ * @brief Set the auto-reload value.
+ * @note The counter is blocked while the auto-reload value is null.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+ * @rmtoll ARR ARR LL_TIM_SetAutoReload
+ * @param TIMx Timer instance
+ * @param AutoReload between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+ WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+ * @brief Get the auto-reload value.
+ * @rmtoll ARR ARR LL_TIM_GetAutoReload
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @param TIMx Timer instance
+ * @retval Auto-reload value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+ * @brief Set the repetition counter value.
+ * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
+ * @param TIMx Timer instance
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+ WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+ * @brief Get the repetition counter value.
+ * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
+ * @param TIMx Timer instance
+ * @retval Repetition counter value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+ * @{
+ */
+/**
+ * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+ * they are updated only when a commutation event (COM) occurs.
+ * @note Only on channels that have a complementary output.
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
+ * @param TIMx Timer instance
+ * @param CCUpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+ * @brief Set the trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @param DMAReqTrigger This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+ * @brief Get actual trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+ * @brief Set the lock level to freeze the
+ * configuration of several capture/compare parameters.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * the lock mechanism is supported by a timer instance.
+ * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
+ * @param TIMx Timer instance
+ * @param LockLevel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_LOCKLEVEL_OFF
+ * @arg @ref LL_TIM_LOCKLEVEL_1
+ * @arg @ref LL_TIM_LOCKLEVEL_2
+ * @arg @ref LL_TIM_LOCKLEVEL_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+ * @brief Enable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
+ * CCER CC1NE LL_TIM_CC_EnableChannel\n
+ * CCER CC2E LL_TIM_CC_EnableChannel\n
+ * CCER CC2NE LL_TIM_CC_EnableChannel\n
+ * CCER CC3E LL_TIM_CC_EnableChannel\n
+ * CCER CC3NE LL_TIM_CC_EnableChannel\n
+ * CCER CC4E LL_TIM_CC_EnableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Disable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
+ * CCER CC1NE LL_TIM_CC_DisableChannel\n
+ * CCER CC2E LL_TIM_CC_DisableChannel\n
+ * CCER CC2NE LL_TIM_CC_DisableChannel\n
+ * CCER CC3E LL_TIM_CC_DisableChannel\n
+ * CCER CC3NE LL_TIM_CC_DisableChannel\n
+ * CCER CC4E LL_TIM_CC_DisableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Indicate whether channel(s) is(are) enabled.
+ * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC4E LL_TIM_CC_IsEnabledChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ return (READ_BIT(TIMx->CCER, Channels) == (Channels));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+ * @{
+ */
+/**
+ * @brief Configure an output channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
+ * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
+ * CCER CC1P LL_TIM_OC_ConfigOutput\n
+ * CCER CC2P LL_TIM_OC_ConfigOutput\n
+ * CCER CC3P LL_TIM_OC_ConfigOutput\n
+ * CCER CC4P LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS4 LL_TIM_OC_ConfigOutput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+ (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Define the behavior of the output reference signal OCxREF from which
+ * OCx and OCxN (when relevant) are derived.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
+ * CCMR1 OC2M LL_TIM_OC_SetMode\n
+ * CCMR2 OC3M LL_TIM_OC_SetMode\n
+ * CCMR2 OC4M LL_TIM_OC_SetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Get the output compare mode of an output channel.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
+ * CCMR1 OC2M LL_TIM_OC_GetMode\n
+ * CCMR2 OC3M LL_TIM_OC_GetMode\n
+ * CCMR2 OC4M LL_TIM_OC_GetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Set the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
+ * CCER CC1NP LL_TIM_OC_SetPolarity\n
+ * CCER CC2P LL_TIM_OC_SetPolarity\n
+ * CCER CC2NP LL_TIM_OC_SetPolarity\n
+ * CCER CC3P LL_TIM_OC_SetPolarity\n
+ * CCER CC3NP LL_TIM_OC_SetPolarity\n
+ * CCER CC4P LL_TIM_OC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
+ * CCER CC1NP LL_TIM_OC_GetPolarity\n
+ * CCER CC2P LL_TIM_OC_GetPolarity\n
+ * CCER CC2NP LL_TIM_OC_GetPolarity\n
+ * CCER CC3P LL_TIM_OC_GetPolarity\n
+ * CCER CC3NP LL_TIM_OC_GetPolarity\n
+ * CCER CC4P LL_TIM_OC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the IDLE state of an output channel
+ * @note This function is significant only for the timer instances
+ * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+ * can be used to check whether or not a timer instance provides
+ * a break input.
+ * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS1N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_SetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param IdleState This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Get the IDLE state of an output channel
+ * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS1N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_GetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Enable fast mode for the output channel.
+ * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_EnableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Disable fast mode for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_DisableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Indicates whether fast mode is enabled for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_EnablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_DisablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Enable clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_EnableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable clearing the output channel on an external event.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_DisableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
+ * @note This function enables clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * dead-time insertion feature is supported by a timer instance.
+ * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+ * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
+ * @param TIMx Timer instance
+ * @param DeadTime between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+ * @brief Set compare value for output channel 1 (TIMx_CCR1).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 2 (TIMx_CCR2).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 3 (TIMx_CCR3).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 4 (TIMx_CCR4).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR1) set for output channel 1.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR2) set for output channel 2.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR3) set for output channel 3.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR4) set for output channel 4.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+ * @{
+ */
+/**
+ * @brief Configure input channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
+ * CCMR1 IC1PSC LL_TIM_IC_Config\n
+ * CCMR1 IC1F LL_TIM_IC_Config\n
+ * CCMR1 CC2S LL_TIM_IC_Config\n
+ * CCMR1 IC2PSC LL_TIM_IC_Config\n
+ * CCMR1 IC2F LL_TIM_IC_Config\n
+ * CCMR2 CC3S LL_TIM_IC_Config\n
+ * CCMR2 IC3PSC LL_TIM_IC_Config\n
+ * CCMR2 IC3F LL_TIM_IC_Config\n
+ * CCMR2 CC4S LL_TIM_IC_Config\n
+ * CCMR2 IC4PSC LL_TIM_IC_Config\n
+ * CCMR2 IC4F LL_TIM_IC_Config\n
+ * CCER CC1P LL_TIM_IC_Config\n
+ * CCER CC1NP LL_TIM_IC_Config\n
+ * CCER CC2P LL_TIM_IC_Config\n
+ * CCER CC2NP LL_TIM_IC_Config\n
+ * CCER CC3P LL_TIM_IC_Config\n
+ * CCER CC3NP LL_TIM_IC_Config\n
+ * CCER CC4P LL_TIM_IC_Config\n
+ * CCER CC4NP LL_TIM_IC_Config
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+ * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+ ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_SetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICActiveInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_GetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the prescaler of input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current prescaler value acting on an input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_SetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_GetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
+ * CCER CC1NP LL_TIM_IC_SetPolarity\n
+ * CCER CC2P LL_TIM_IC_SetPolarity\n
+ * CCER CC2NP LL_TIM_IC_SetPolarity\n
+ * CCER CC3P LL_TIM_IC_SetPolarity\n
+ * CCER CC3NP LL_TIM_IC_SetPolarity\n
+ * CCER CC4P LL_TIM_IC_SetPolarity\n
+ * CCER CC4NP LL_TIM_IC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the current input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
+ * CCER CC1NP LL_TIM_IC_GetPolarity\n
+ * CCER CC2P LL_TIM_IC_GetPolarity\n
+ * CCER CC2NP LL_TIM_IC_GetPolarity\n
+ * CCER CC3P LL_TIM_IC_GetPolarity\n
+ * CCER CC3NP LL_TIM_IC_GetPolarity\n
+ * CCER CC4P LL_TIM_IC_GetPolarity\n
+ * CCER CC4NP LL_TIM_IC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+ SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
+}
+
+/**
+ * @brief Get captured value for input channel 1.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get captured value for input channel 2.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get captured value for input channel 3.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get captured value for input channel 4.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+ * @{
+ */
+/**
+ * @brief Enable external clock mode 2.
+ * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Disable external clock mode 2.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Indicate whether external clock mode 2 is enabled.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
+}
+
+/**
+ * @brief Set the clock source of the counter clock.
+ * @note when selected clock source is external clock mode 1, the timer input
+ * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+ * function. This timer input must be configured by calling
+ * the @ref LL_TIM_IC_Config() function.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode1.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
+ * SMCR ECE LL_TIM_SetClockSource
+ * @param TIMx Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+ * @brief Set the encoder interface mode.
+ * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the encoder mode.
+ * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
+ * @param TIMx Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+ * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+ * @{
+ */
+/**
+ * @brief Set the trigger output (TRGO) used for timer synchronization .
+ * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can operate as a master timer.
+ * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
+ * @param TIMx Timer instance
+ * @param TimerSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO_RESET
+ * @arg @ref LL_TIM_TRGO_ENABLE
+ * @arg @ref LL_TIM_TRGO_UPDATE
+ * @arg @ref LL_TIM_TRGO_CC1IF
+ * @arg @ref LL_TIM_TRGO_OC1REF
+ * @arg @ref LL_TIM_TRGO_OC2REF
+ * @arg @ref LL_TIM_TRGO_OC3REF
+ * @arg @ref LL_TIM_TRGO_OC4REF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+ * @brief Set the synchronization mode of a slave timer.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
+ * @param TIMx Timer instance
+ * @param SlaveMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_SLAVEMODE_DISABLED
+ * @arg @ref LL_TIM_SLAVEMODE_RESET
+ * @arg @ref LL_TIM_SLAVEMODE_GATED
+ * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+ * @brief Set the selects the trigger input to be used to synchronize the counter.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR TS LL_TIM_SetTriggerInput
+ * @param TIMx Timer instance
+ * @param TriggerInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TS_ITR0
+ * @arg @ref LL_TIM_TS_ITR1
+ * @arg @ref LL_TIM_TS_ITR2
+ * @arg @ref LL_TIM_TS_ITR3
+ * @arg @ref LL_TIM_TS_TI1F_ED
+ * @arg @ref LL_TIM_TS_TI1FP1
+ * @arg @ref LL_TIM_TS_TI2FP2
+ * @arg @ref LL_TIM_TS_ETRF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+ * @brief Enable the Master/Slave mode.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Disable the Master/Slave mode.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Indicates whether the Master/Slave mode is enabled.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
+}
+
+/**
+ * @brief Configure the external trigger (ETR) input.
+ * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an external trigger input.
+ * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
+ * SMCR ETPS LL_TIM_ConfigETR\n
+ * SMCR ETF LL_TIM_ConfigETR
+ * @param TIMx Timer instance
+ * @param ETRPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+ * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+ * @param ETRPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+ * @param ETRFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+ uint32_t ETRFilter)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+ * @{
+ */
+/**
+ * @brief Enable the break function.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKE LL_TIM_EnableBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Disable the break function.
+ * @rmtoll BDTR BKE LL_TIM_DisableBRK
+ * @param TIMx Timer instance
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Configure the break input.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
+}
+
+/**
+ * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
+ * BDTR OSSR LL_TIM_SetOffStates
+ * @param TIMx Timer instance
+ * @param OffStateIdle This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSI_DISABLE
+ * @arg @ref LL_TIM_OSSI_ENABLE
+ * @param OffStateRun This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSR_DISABLE
+ * @arg @ref LL_TIM_OSSR_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+ * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Disable automatic output (MOE can be set only by software).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Indicate whether automatic output is enabled.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
+}
+
+/**
+ * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Indicates whether outputs are enabled.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+ * @{
+ */
+/**
+ * @brief Configures the timer DMA burst feature.
+ * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports the DMA burst mode.
+ * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
+ * DCR DBA LL_TIM_ConfigDMABurst
+ * @param TIMx Timer instance
+ * @param DMABurstBaseAddress This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+ * @param DMABurstLength This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+ * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+ MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+ * @{
+ */
+/**
+ * @brief Remap TIM inputs (input channel, internal/external triggers).
+ * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * a some timer inputs can be remapped.
+ * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
+ * TIM5_OR TI4_RMP LL_TIM_SetRemap\n
+ * TIM11_OR TI1_RMP LL_TIM_SetRemap
+ * @param TIMx Timer instance
+ * @param Remap Remap param depends on the TIMx. Description available only
+ * in CHM version of the User Manual (not in .pdf).
+ * Otherwise see Reference Manual description of OR registers.
+ *
+ * Below description summarizes "Timer Instance" and "Remap" param combinations:
+ *
+ * TIM2: one of the following values
+ *
+ * ITR1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
+ * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
+ * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
+ *
+ * TIM5: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
+ * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
+ * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
+ * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
+ *
+ * TIM11: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1
+ * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
+ * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
+ *
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+ MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+ * @{
+ */
+/**
+ * @brief Clear the update interrupt flag (UIF).
+ * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+ * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
+ * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
+ * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+ * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
+ * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+ * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
+ * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+ * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
+}
+
+/**
+ * @brief Clear the commutation interrupt flag (COMIF).
+ * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+ * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+ * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
+}
+
+/**
+ * @brief Clear the trigger interrupt flag (TIF).
+ * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+ * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+ * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
+}
+
+/**
+ * @brief Clear the break interrupt flag (BIF).
+ * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+ * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+ * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+ * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+ * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+ * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+ * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+ * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+ * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+ * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+ * @{
+ */
+/**
+ * @brief Enable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Disable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Indicates whether the update interrupt (UIE) is enabled.
+ * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
+}
+
+/**
+ * @brief Enable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Disable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+ * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
+}
+
+/**
+ * @brief Enable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Disable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+ * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
+}
+
+/**
+ * @brief Enable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Disable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+ * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
+}
+
+/**
+ * @brief Enable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Disable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+ * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
+}
+
+/**
+ * @brief Enable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Disable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
+ * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
+}
+
+/**
+ * @brief Enable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TIE) is enabled.
+ * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
+}
+
+/**
+ * @brief Enable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Disable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Indicates whether the break interrupt (BIE) is enabled.
+ * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
+ * @{
+ */
+/**
+ * @brief Enable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Disable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Indicates whether the update DMA request (UDE) is enabled.
+ * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
+}
+
+/**
+ * @brief Enable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Disable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+ * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
+}
+
+/**
+ * @brief Enable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Disable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+ * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
+}
+
+/**
+ * @brief Enable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Disable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+ * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
+}
+
+/**
+ * @brief Enable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Disable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+ * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
+}
+
+/**
+ * @brief Enable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Disable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
+ * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
+}
+
+/**
+ * @brief Enable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TDE) is enabled.
+ * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+ * @{
+ */
+/**
+ * @brief Generate an update event.
+ * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+ * @brief Generate Capture/Compare 1 event.
+ * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+ * @brief Generate Capture/Compare 2 event.
+ * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+ * @brief Generate Capture/Compare 3 event.
+ * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+ * @brief Generate Capture/Compare 4 event.
+ * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+ * @brief Generate commutation event.
+ * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+ * @brief Generate trigger event.
+ * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+ * @brief Generate break event.
+ * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_TIM_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,523 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_usart.c
+ * @author MCD Application Team
+ * @brief USART LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usart.h"
+#include "stm32f4xx_ll_rcc.h"
+#include "stm32f4xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
+
+/** @addtogroup USART_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+ * @{
+ */
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ * divided by the smallest oversampling used on the USART (i.e. 8) */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
+#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize USART registers (Registers restored to their default values).
+ * @param USARTx USART Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are de-initialized
+ * - ERROR: USART registers are not de-initialized
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+
+ if (USARTx == USART1)
+ {
+ /* Force reset of USART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+ /* Release reset of USART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+ }
+ else if (USARTx == USART2)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+ }
+#if defined(USART3)
+ else if (USARTx == USART3)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+ }
+#endif /* USART3 */
+#if defined(USART6)
+ else if (USARTx == USART6)
+ {
+ /* Force reset of USART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
+
+ /* Release reset of USART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
+ }
+#endif /* USART6 */
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+ }
+#endif /* UART5 */
+#if defined(UART7)
+ else if (USARTx == UART7)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
+ }
+#endif /* UART7 */
+#if defined(UART8)
+ else if (USARTx == UART8)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
+ }
+#endif /* UART8 */
+#if defined(UART9)
+ else if (USARTx == UART9)
+ {
+ /* Force reset of UART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
+
+ /* Release reset of UART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
+ }
+#endif /* UART9 */
+#if defined(UART10)
+ else if (USARTx == UART10)
+ {
+ /* Force reset of UART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART10);
+
+ /* Release reset of UART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART10);
+ }
+#endif /* UART10 */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize USART registers according to the specified
+ * parameters in USART_InitStruct.
+ * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+ * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+ * @param USARTx USART Instance
+ * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are initialized according to USART_InitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ LL_RCC_ClocksTypeDef rcc_clocks;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+ assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+ assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+ assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR1 Configuration -----------------------
+ * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+ * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
+ * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+ * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+ * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+ */
+ MODIFY_REG(USARTx->CR1,
+ (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+ USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Stop bits) with parameters:
+ * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+ * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+ */
+ LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+ /*---------------------------- USART CR3 Configuration -----------------------
+ * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+ */
+ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+ /*---------------------------- USART BRR Configuration -----------------------
+ * Retrieve Clock frequency used for USART Peripheral
+ */
+ LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+ if (USARTx == USART1)
+ {
+ periphclk = rcc_clocks.PCLK2_Frequency;
+ }
+ else if (USARTx == USART2)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#if defined(USART3)
+ else if (USARTx == USART3)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* USART3 */
+#if defined(USART6)
+ else if (USARTx == USART6)
+ {
+ periphclk = rcc_clocks.PCLK2_Frequency;
+ }
+#endif /* USART6 */
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* UART5 */
+#if defined(UART7)
+ else if (USARTx == UART7)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* UART7 */
+#if defined(UART8)
+ else if (USARTx == UART8)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* UART8 */
+#if defined(UART9)
+ else if (USARTx == UART9)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* UART9 */
+#if defined(UART10)
+ else if (USARTx == UART10)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* UART10 */
+ else
+ {
+ /* Nothing to do, as error code is already assigned to ERROR value */
+ }
+
+ /* Configure the USART Baud Rate :
+ - valid baud rate value (different from 0) is required
+ - Peripheral clock as returned by RCC service, should be valid (different from 0).
+ */
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ && (USART_InitStruct->BaudRate != 0U))
+ {
+ status = SUCCESS;
+ LL_USART_SetBaudRate(USARTx,
+ periphclk,
+ USART_InitStruct->OverSampling,
+ USART_InitStruct->BaudRate);
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
+ }
+ }
+ /* Endif (=> USART not in Disabled state => return ERROR) */
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+ * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+ /* Set USART_InitStruct fields to default values */
+ USART_InitStruct->BaudRate = 9600U;
+ USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
+ USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
+ USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
+ USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
+ USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+ * @brief Initialize USART Clock related settings according to the
+ * specified parameters in the USART_ClockInitStruct.
+ * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+ * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param USARTx USART Instance
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * that contains the Clock configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check USART Instance and Clock signal output parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR2 Configuration -----------------------*/
+ /* If Clock signal has to be output */
+ if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+ {
+ /* Deactivate Clock signal delivery :
+ * - Disable Clock Output: USART_CR2_CLKEN cleared
+ */
+ LL_USART_DisableSCLKOutput(USARTx);
+ }
+ else
+ {
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
+
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Enable Clock Output: USART_CR2_CLKEN set
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+ }
+ }
+ /* Else (USART not in Disabled state => return ERROR */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ /* Set LL_USART_ClockInitStruct fields with default values */
+ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,2537 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_usart.h
+ * @author MCD Application Team
+ * @brief Header file of USART LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_USART_H
+#define __STM32F4xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
+
+/** @defgroup USART_LL USART
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+ * @{
+ */
+
+/* Defines used for the bit position in the register and perform offsets*/
+#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
+ This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+ * @brief LL USART Clock Init Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+ USART HW configuration can be modified afterwards using unitary functions
+ @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+ For more details, refer to description of this function. */
+
+ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+ For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_USART_ReadReg function
+ * @{
+ */
+#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */
+#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */
+#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */
+#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */
+#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */
+#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */
+#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */
+#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */
+#define LL_USART_SR_LBD USART_SR_LBD /*!< LIN break detection flag */
+#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
+ * @{
+ */
+#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
+#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
+#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ * @{
+ */
+#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+ * @{
+ */
+#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+ * @{
+ */
+#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ * @{
+ */
+#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+ * @{
+ */
+
+#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ * @{
+ */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ * @{
+ */
+#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ * @{
+ */
+#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ * @{
+ */
+#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ * @{
+ */
+#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ * @{
+ */
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+ */
+#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
+#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
+#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
+/* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
+ ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
+ (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+ */
+#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
+#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
+#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
+/* USART BRR = mantissa + overflow + fraction
+ = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
+ (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
+ (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief USART Enable
+ * @rmtoll CR1 UE LL_USART_Enable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief USART Disable (all USART prescalers and outputs are disabled)
+ * @note When USART is disabled, USART prescalers and outputs are stopped immediately,
+ * and current operations are discarded. The configuration of the USART is kept, but all the status
+ * flags, in the USARTx_SR are set to their default values.
+ * @rmtoll CR1 UE LL_USART_Disable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief Indicate if USART is enabled
+ * @rmtoll CR1 UE LL_USART_IsEnabled
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+ * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ * @rmtoll CR1 RE LL_USART_EnableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Receiver Disable
+ * @rmtoll CR1 RE LL_USART_DisableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Transmitter Enable
+ * @rmtoll CR1 TE LL_USART_EnableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Transmitter Disable
+ * @rmtoll CR1 TE LL_USART_DisableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Configure simultaneously enabled/disabled states
+ * of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
+ * CR1 TE LL_USART_SetTransferDirection
+ * @param USARTx USART Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+ * @brief Return enabled/disabled states of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
+ * CR1 TE LL_USART_GetTransferDirection
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+ * @brief Configure Parity (enabled/disabled and parity mode if enabled).
+ * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
+ * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+ * (9th or 8th bit depending on data width) and parity is checked on the received data.
+ * @rmtoll CR1 PS LL_USART_SetParity\n
+ * CR1 PCE LL_USART_SetParity
+ * @param USARTx USART Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+ * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
+ * @rmtoll CR1 PS LL_USART_GetParity\n
+ * CR1 PCE LL_USART_GetParity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+ * @brief Set Receiver Wake Up method from Mute mode.
+ * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
+ * @param USARTx USART Instance
+ * @param Method This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+ * @brief Return Receiver Wake Up method from Mute mode
+ * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+ * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M LL_USART_SetDataWidth
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+ * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M LL_USART_GetDataWidth
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+ * @brief Set Oversampling to 8-bit or 16-bit mode
+ * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
+ * @param USARTx USART Instance
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+ * @brief Return Oversampling mode
+ * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+ * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @param LastBitClockPulse This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+ * @brief Retrieve Clock pulse of the last data bit output configuration
+ * (Last bit Clock pulse output to the SCLK pin or not)
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+ * @brief Select the phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_SetClockPhase
+ * @param USARTx USART Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Return phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_GetClockPhase
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+ * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
+ * @param USARTx USART Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Return polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+ * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+ * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+ * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+ * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
+ * CR2 CPOL LL_USART_ConfigClock\n
+ * CR2 LBCL LL_USART_ConfigClock
+ * @param USARTx USART Instance
+ * @param Phase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @param LBCPOutput This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+ * @brief Enable Clock output on SCLK pin
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Disable Clock output on SCLK pin
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Indicate if Clock output on SCLK pin is enabled
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+}
+
+/**
+ * @brief Set the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
+ * @param USARTx USART Instance
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Retrieve the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+ * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Data Width configuration using @ref LL_USART_SetDataWidth() function
+ * - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+ * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+ * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
+ * CR1 PCE LL_USART_ConfigCharacter\n
+ * CR1 M LL_USART_ConfigCharacter\n
+ * CR2 STOP LL_USART_ConfigCharacter
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+ uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Set Address of the USART node.
+ * @note This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with address mark detection.
+ * @rmtoll CR2 ADD LL_USART_SetNodeAddress
+ * @param USARTx USART Instance
+ * @param NodeAddress 4 bit Address of the USART node.
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
+}
+
+/**
+ * @brief Return 4 bit Address of the USART node as set in ADD field of CR2.
+ * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+ * @rmtoll CR2 ADD LL_USART_GetNodeAddress
+ * @param USARTx USART Instance
+ * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
+}
+
+/**
+ * @brief Enable RTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Disable RTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Enable CTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Disable CTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Configure HW Flow Control mode (both CTS and RTS)
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_SetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @param HardwareFlowControl This parameter can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+ * @brief Return HW Flow Control configuration (both CTS and RTS)
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_GetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+ * @brief Enable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Disable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Indicate if One bit sampling method is enabled
+ * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+}
+
+/**
+ * @brief Configure USART BRR register for achieving expected Baud Rate value.
+ * @note Compute and set USARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+ * @note Peripheral clock and Baud rate values provided as function parameters should be valid
+ * (Baud rate value != 0)
+ * @rmtoll BRR BRR LL_USART_SetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+ uint32_t BaudRate)
+{
+ if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+ }
+ else
+ {
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+ }
+}
+
+/**
+ * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
+ * (full BRR content), and to used Peripheral Clock and Oversampling mode values
+ * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+ * @rmtoll BRR BRR LL_USART_GetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval Baud Rate
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+{
+ register uint32_t usartdiv = 0x0U;
+ register uint32_t brrresult = 0x0U;
+
+ usartdiv = USARTx->BRR;
+
+ if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ if ((usartdiv & 0xFFF7U) != 0U)
+ {
+ usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+ brrresult = (PeriphClk * 2U) / usartdiv;
+ }
+ }
+ else
+ {
+ if ((usartdiv & 0xFFFFU) != 0U)
+ {
+ brrresult = PeriphClk / usartdiv;
+ }
+ }
+ return (brrresult);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+ * @{
+ */
+
+/**
+ * @brief Enable IrDA mode
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_EnableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Disable IrDA mode
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_DisableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Indicate if IrDA mode is enabled
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+}
+
+/**
+ * @brief Configure IrDA Power Mode (Normal or Low Power)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_IRDA_POWER_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+ * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+ * @brief Set Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+ * @brief Return Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+ * @{
+ */
+
+/**
+ * @brief Enable Smartcard NACK transmission
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Disable Smartcard NACK transmission
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Indicate if Smartcard NACK transmission is enabled
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+}
+
+/**
+ * @brief Enable Smartcard mode
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Disable Smartcard mode
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Indicate if Smartcard mode is enabled
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+}
+
+/**
+ * @brief Set Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+ * @brief Return Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
+}
+
+/**
+ * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+ * @{
+ */
+
+/**
+ * @brief Enable Single Wire Half-Duplex mode
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Disable Single Wire Half-Duplex mode
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Indicate if Single Wire Half-Duplex mode is enabled
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+ * @{
+ */
+
+/**
+ * @brief Set LIN Break Detection Length
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @param LINBDLength This parameter can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+ * @brief Return LIN Break Detection Length
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+ * @brief Enable LIN mode
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_EnableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Disable LIN mode
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_DisableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Indicate if LIN mode is enabled
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+ * @{
+ */
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+ * @note In UART mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Asynchronous Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
+ * CR2 CLKEN LL_USART_ConfigAsyncMode\n
+ * CR3 SCEN LL_USART_ConfigAsyncMode\n
+ * CR3 IREN LL_USART_ConfigAsyncMode\n
+ * CR3 HDSEL LL_USART_ConfigAsyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+ /* In Asynchronous mode, the following bits must be kept cleared:
+ - LINEN, CLKEN bits in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Synchronous Mode
+ * @note In Synchronous mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the USART in Synchronous mode.
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * @note Other remaining configurations items related to Synchronous Mode
+ * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
+ * CR2 CLKEN LL_USART_ConfigSyncMode\n
+ * CR3 SCEN LL_USART_ConfigSyncMode\n
+ * CR3 IREN LL_USART_ConfigSyncMode\n
+ * CR3 HDSEL LL_USART_ConfigSyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+ /* set the UART/USART in Synchronous mode */
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in LIN Mode
+ * @note In LIN mode, the following bits must be kept cleared:
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also set the UART/USART in LIN mode.
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+ * @note Other remaining configurations items related to LIN Mode
+ * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
+ * CR2 STOP LL_USART_ConfigLINMode\n
+ * CR2 LINEN LL_USART_ConfigLINMode\n
+ * CR3 IREN LL_USART_ConfigLINMode\n
+ * CR3 SCEN LL_USART_ConfigLINMode\n
+ * CR3 HDSEL LL_USART_ConfigLINMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+ /* In LIN mode, the following bits must be kept cleared:
+ - STOP and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* Set the UART/USART in LIN mode */
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
+ * @note In Half Duplex mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * This function also sets the UART/USART in Half Duplex mode.
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+ * @note Other remaining configurations items related to Half Duplex Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
+ * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
+ * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 IREN LL_USART_ConfigHalfDuplexMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+ /* In Half Duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+ /* set the UART/USART in Half Duplex mode */
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Smartcard Mode
+ * @note In Smartcard mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also configures Stop bits to 1.5 bits and
+ * sets the USART in Smartcard mode (SCEN bit).
+ * Clock Output is also enabled (CLKEN).
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+ * @note Other remaining configurations items related to Smartcard Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
+ * CR2 STOP LL_USART_ConfigSmartcardMode\n
+ * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
+ * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
+ * CR3 SCEN LL_USART_ConfigSmartcardMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+ /* In Smartcard mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+ /* Configure Stop bits to 1.5 bits */
+ /* Synchronous mode is activated by default */
+ SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+ /* set the UART/USART in Smartcard mode */
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Irda Mode
+ * @note In IRDA mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the UART/USART in IRDA mode (IREN bit).
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+ * @note Other remaining configurations items related to Irda Mode
+ * (as Baud Rate, Word length, Power mode, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
+ * CR2 CLKEN LL_USART_ConfigIrdaMode\n
+ * CR2 STOP LL_USART_ConfigIrdaMode\n
+ * CR3 SCEN LL_USART_ConfigIrdaMode\n
+ * CR3 HDSEL LL_USART_ConfigIrdaMode\n
+ * CR3 IREN LL_USART_ConfigIrdaMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* set the UART/USART in IRDA mode */
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Multi processor Mode
+ * (several USARTs connected in a network, one of the USARTs can be the master,
+ * its TX output connected to the RX inputs of the other slaves USARTs).
+ * @note In MultiProcessor mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Multi processor Mode
+ * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
+ * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
+ * CR3 IREN LL_USART_ConfigMultiProcessMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+ /* In Multi Processor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the USART Parity Error Flag is set or not
+ * @rmtoll SR PE LL_USART_IsActiveFlag_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
+}
+
+/**
+ * @brief Check if the USART Framing Error Flag is set or not
+ * @rmtoll SR FE LL_USART_IsActiveFlag_FE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
+}
+
+/**
+ * @brief Check if the USART Noise error detected Flag is set or not
+ * @rmtoll SR NF LL_USART_IsActiveFlag_NE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
+}
+
+/**
+ * @brief Check if the USART OverRun Error Flag is set or not
+ * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
+}
+
+/**
+ * @brief Check if the USART IDLE line detected Flag is set or not
+ * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
+}
+
+/**
+ * @brief Check if the USART Read Data Register Not Empty Flag is set or not
+ * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Flag is set or not
+ * @rmtoll SR TC LL_USART_IsActiveFlag_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
+}
+
+/**
+ * @brief Check if the USART Transmit Data Register Empty Flag is set or not
+ * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Flag is set or not
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
+}
+
+/**
+ * @brief Check if the USART CTS Flag is set or not
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
+}
+
+/**
+ * @brief Check if the USART Send Break Flag is set or not
+ * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
+}
+
+/**
+ * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
+ * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
+}
+
+/**
+ * @brief Clear Parity Error Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * NE, FE, ORE, IDLE would also be cleared.
+ * @rmtoll SR PE LL_USART_ClearFlag_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear Framing Error Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * PE, NE, ORE, IDLE would also be cleared.
+ * @rmtoll SR FE LL_USART_ClearFlag_FE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear Noise detected Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * PE, FE, ORE, IDLE would also be cleared.
+ * @rmtoll SR NF LL_USART_ClearFlag_NE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear OverRun Error Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * PE, NE, FE, IDLE would also be cleared.
+ * @rmtoll SR ORE LL_USART_ClearFlag_ORE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear IDLE line detected Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * PE, NE, FE, ORE would also be cleared.
+ * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear Transmission Complete Flag
+ * @rmtoll SR TC LL_USART_ClearFlag_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->SR , ~(USART_SR_TC));
+}
+
+/**
+ * @brief Clear RX Not Empty Flag
+ * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));
+}
+
+/**
+ * @brief Clear LIN Break Detection Flag
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll SR LBD LL_USART_ClearFlag_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->SR , ~(USART_SR_LBD));
+}
+
+/**
+ * @brief Clear CTS Interrupt Flag
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll SR CTS LL_USART_ClearFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->SR , ~(USART_SR_CTS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+ * @brief Enable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+ * @brief Enable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+ * @brief Enable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+ * @brief Enable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Enable LIN Break Detection Interrupt
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Enable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
+ * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Enable CTS Interrupt
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Disable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+ * @brief Disable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+ * @brief Disable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+ * @brief Disable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+ * @brief Disable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Disable LIN Break Detection Interrupt
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Disable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
+ * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Disable CTS Interrupt
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
+ * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+ * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+ * @brief Check if the USART TX Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+ * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
+ * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+}
+
+/**
+ * @brief Check if the USART Error Interrupt is enabled or disabled.
+ * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+ * @brief Check if the USART CTS Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Disable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for reception
+ * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+ * @brief Enable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Disable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for transmission
+ * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll DR DR LL_USART_DMA_GetRegAddr
+ * @note Address of Data Register is valid for both Transmit and Receive transfers.
+ * @param USARTx USART Instance
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
+{
+ /* return address of DR register */
+ return ((uint32_t) &(USARTx->DR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 8 bits)
+ * @rmtoll DR DR LL_USART_ReceiveData8
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+ return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
+}
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 9 bits)
+ * @rmtoll DR DR LL_USART_ReceiveData9
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+ */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+ return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
+ * @rmtoll DR DR LL_USART_TransmitData8
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+ USARTx->DR = Value;
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
+ * @rmtoll DR DR LL_USART_TransmitData9
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+ USARTx->DR = Value & 0x1FFU;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Execution Execution
+ * @{
+ */
+
+/**
+ * @brief Request Break sending
+ * @rmtoll CR1 SBK LL_USART_RequestBreakSending
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_SBK);
+}
+
+/**
+ * @brief Put USART in Mute mode
+ * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RWU);
+}
+
+/**
+ * @brief Put USART in Active mode
+ * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1817 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_usb.c
+ * @author MCD Application Team
+ * @brief USB Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_LL_USB_DRIVER
+ * @{
+ */
+
+#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
+ * @{
+ */
+
+/** @defgroup LL_USB_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization/de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the USB Core
+ * @param USBx USB Instance
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+ if (cfg.phy_itface == USB_OTG_ULPI_PHY)
+ {
+
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+
+ /* Init The ULPI Interface */
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+
+ /* Select vbus source */
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+ if(cfg.use_external_vbus == 1U)
+ {
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
+ }
+ /* Reset after a PHY select */
+ USB_CoreReset(USBx);
+ }
+ else /* FS interface (embedded Phy) */
+ {
+ /* Select FS Embedded PHY */
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+
+ /* Reset after a PHY select and set Host mode */
+ USB_CoreReset(USBx);
+
+ /* Deactivate the power down*/
+ USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
+ }
+
+ if(cfg.dma_enable == ENABLE)
+ {
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EnableGlobalInt
+ * Enables the controller's Global Int in the AHB Config reg
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+ return HAL_OK;
+}
+
+
+/**
+ * @brief USB_DisableGlobalInt
+ * Disable the controller's Global Int in the AHB Config reg
+ * @param USBx Selected device
+ * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+ USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetCurrentMode : Set functional mode
+ * @param USBx Selected device
+ * @param mode current core mode
+ * This parameter can be one of these values:
+ * @arg USB_OTG_DEVICE_MODE: Peripheral mode
+ * @arg USB_OTG_HOST_MODE: Host mode
+ * @arg USB_OTG_DRD_MODE: Dual Role Device mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
+{
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
+
+ if ( mode == USB_OTG_HOST_MODE)
+ {
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+ }
+ else if ( mode == USB_OTG_DEVICE_MODE)
+ {
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+ }
+ HAL_Delay(50U);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevInit : Initializes the USB_OTG controller registers
+ * for device mode
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+ uint32_t i = 0U;
+
+ /*Activate VBUS Sensing B */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+
+ if (cfg.vbus_sensing_enable == 0U)
+ {
+ /* Deactivate VBUS Sensing B */
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+ /* B-peripheral session valid override enable*/
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+ }
+#else
+ if (cfg.vbus_sensing_enable == 0U)
+ {
+ USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+ }
+ else
+ {
+ /* Enable VBUS */
+ USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+ }
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+ /* Restart the Phy Clock */
+ USBx_PCGCCTL = 0U;
+
+ /* Device mode configuration */
+ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
+
+ if(cfg.phy_itface == USB_OTG_ULPI_PHY)
+ {
+ if(cfg.speed == USB_OTG_SPEED_HIGH)
+ {
+ /* Set High speed phy */
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
+ }
+ else
+ {
+ /* set High speed phy in Full speed mode */
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
+ }
+ }
+ else
+ {
+ /* Set Full speed phy */
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
+ }
+
+ /* Flush the FIFOs */
+ USB_FlushTxFifo(USBx , 0x10U); /* all Tx FIFOs */
+ USB_FlushRxFifo(USBx);
+
+ /* Clear all pending Device Interrupts */
+ USBx_DEVICE->DIEPMSK = 0U;
+ USBx_DEVICE->DOEPMSK = 0U;
+ USBx_DEVICE->DAINT = 0xFFFFFFFFU;
+ USBx_DEVICE->DAINTMSK = 0U;
+
+ for (i = 0U; i < cfg.dev_endpoints; i++)
+ {
+ if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
+ }
+ else
+ {
+ USBx_INEP(i)->DIEPCTL = 0U;
+ }
+
+ USBx_INEP(i)->DIEPTSIZ = 0U;
+ USBx_INEP(i)->DIEPINT = 0xFFU;
+ }
+
+ for (i = 0U; i < cfg.dev_endpoints; i++)
+ {
+ if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
+ }
+ else
+ {
+ USBx_OUTEP(i)->DOEPCTL = 0U;
+ }
+
+ USBx_OUTEP(i)->DOEPTSIZ = 0U;
+ USBx_OUTEP(i)->DOEPINT = 0xFFU;
+ }
+
+ USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
+
+ if (cfg.dma_enable == 1U)
+ {
+ /*Set threshold parameters */
+ USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
+ USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
+
+ i= USBx_DEVICE->DTHRCTL;
+ }
+
+ /* Disable all interrupts. */
+ USBx->GINTMSK = 0U;
+
+ /* Clear any pending interrupts */
+ USBx->GINTSTS = 0xBFFFFFFFU;
+
+ /* Enable the common interrupts */
+ if (cfg.dma_enable == DISABLE)
+ {
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+ }
+
+ /* Enable interrupts matching to the Device mode ONLY */
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
+ USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
+ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
+
+ if(cfg.Sof_enable)
+ {
+ USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+ }
+
+ if (cfg.vbus_sensing_enable == ENABLE)
+ {
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
+ * @param USBx Selected device
+ * @param num FIFO number
+ * This parameter can be a value from 1 to 15
+ 15 means Flush all Tx FIFOs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
+{
+ uint32_t count = 0;
+
+ USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
+
+ do
+ {
+ if (++count > 200000)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t count = 0;
+
+ USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
+
+ do
+ {
+ if (++count > 200000)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
+ * depending the PHY type and the enumeration speed of the device.
+ * @param USBx Selected device
+ * @param speed device speed
+ * This parameter can be one of these values:
+ * @arg USB_OTG_SPEED_HIGH: High speed mode
+ * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
+ * @arg USB_OTG_SPEED_FULL: Full speed mode
+ * @arg USB_OTG_SPEED_LOW: Low speed mode
+ * @retval Hal status
+ */
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
+{
+ USBx_DEVICE->DCFG |= speed;
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_GetDevSpeed :Return the Dev Speed
+ * @param USBx Selected device
+ * @retval speed : device speed
+ * This parameter can be one of these values:
+ * @arg USB_OTG_SPEED_HIGH: High speed mode
+ * @arg USB_OTG_SPEED_FULL: Full speed mode
+ * @arg USB_OTG_SPEED_LOW: Low speed mode
+ */
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint8_t speed = 0U;
+
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+ {
+ speed = USB_OTG_SPEED_HIGH;
+ }
+ else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
+ ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
+ {
+ speed = USB_OTG_SPEED_FULL;
+ }
+ else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+ {
+ speed = USB_OTG_SPEED_LOW;
+ }
+
+ return speed;
+}
+
+/**
+ * @brief Activate and configure an endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ if (ep->is_in == 1U)
+ {
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num)));
+
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
+ {
+ USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
+ ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
+ }
+ }
+ else
+ {
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U);
+
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+ {
+ USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
+ (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
+ }
+ }
+ return HAL_OK;
+}
+/**
+ * @brief Activate and configure a dedicated endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ static __IO uint32_t debug = 0U;
+
+ /* Read DEPCTLn register */
+ if (ep->is_in == 1U)
+ {
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
+ {
+ USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
+ ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
+ }
+
+
+ debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
+ ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
+
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num)));
+ }
+ else
+ {
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+ {
+ USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
+ ((ep->num) << 22U) | (USB_OTG_DOEPCTL_USBAEP));
+
+ debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0U)*USB_OTG_EP_REG_SIZE);
+ debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
+ debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
+ ((ep->num) << 22U) | (USB_OTG_DOEPCTL_USBAEP));
+ }
+
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U);
+ }
+
+ return HAL_OK;
+}
+/**
+ * @brief De-activate and de-initialize an endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ uint32_t count = 0U;
+
+ /* Disable the IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_USBAEP;
+
+ /* sets the NAK bit for the IN endpoint */
+ USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
+
+ /* Disable IN endpoint */
+ USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS;
+
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*Wait for EPDISD endpoint disabled interrupt*/
+ while ((USBx_INEP(ep->num)->DIEPINT & USB_OTG_DIEPCTL_EPDIS) == USB_OTG_DIEPCTL_EPDIS);
+
+
+ /* Flush any data remaining in the TxFIFO */
+ USB_FlushTxFifo(USBx , 0x10U);
+
+ /* Disable endpoint interrupts */
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
+
+ }
+ else /* Disable the OUT endpoint */
+ {
+
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+
+ /* sets the NAK bit for the OUT endpoint */
+ USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
+
+ /* Disable OUT endpoint */
+ USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS;
+
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*Wait for EPDISD endpoint disabled interrupt*/
+ while ((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS);
+
+ /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
+
+ /* Disable endpoint interrupts */
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief De-activate and de-initialize a dedicated endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ uint32_t count = 0U;
+
+ /* Disable the IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_USBAEP;
+
+ /* sets the NAK bit for the IN endpoint */
+ USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
+
+ /* Disable IN endpoint */
+ USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS;
+
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*Wait for EPDISD endpoint disabled interrupt*/
+ while ((USBx_INEP(ep->num)->DIEPINT & USB_OTG_DIEPCTL_EPDIS) == USB_OTG_DIEPCTL_EPDIS);
+
+
+ /* Flush any data remaining in the TxFIFO */
+ USB_FlushTxFifo(USBx , 0x10U);
+
+ /* Disable endpoint interrupts */
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
+
+ }
+ else /* Disable the OUT endpoint */
+ {
+
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+
+ /* sets the NAK bit for the OUT endpoint */
+ USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
+
+ /* Disable OUT endpoint */
+ USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS;
+
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*Wait for EPDISD endpoint disabled interrupt*/
+ while ((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS);
+
+ /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
+
+ /* Disable endpoint interrupts */
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
+ }
+ return HAL_OK;
+
+}
+
+/**
+ * @brief USB_EPStartXfer : setup and starts a transfer over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+ uint16_t pktcnt = 0U;
+
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U)
+ {
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ }
+ else
+ {
+ /* Program the transfer size and packet count
+ * as follows: xfersize = N * maxpacket +
+ * short_packet pktcnt = N + (short_packet
+ * exist ? 1 : 0)
+ */
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket) << 19U)) ;
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29U));
+ }
+ }
+
+ if (dma == 1U)
+ {
+ USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ }
+ else
+ {
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Enable the Tx FIFO Empty Interrupt for this EP */
+ if (ep->xfer_len > 0U)
+ {
+/* MBED */
+ atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << ep->num);
+/* MBED */
+ }
+ }
+ }
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U)
+ {
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+ }
+ else
+ {
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+ }
+ }
+
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
+ }
+ }
+ else /* OUT endpoint */
+ {
+ /* Program the transfer size and packet count as follows:
+ * pktcnt = N
+ * xfersize = N * maxpacket
+ */
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+ if (ep->xfer_len == 0U)
+ {
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U));
+ }
+ else
+ {
+ pktcnt = (ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket;
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19U));
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
+ }
+
+ if (dma == 1U)
+ {
+ USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
+ }
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U)
+ {
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+ }
+ else
+ {
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+ }
+ }
+ /* EP enable */
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U)
+ {
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ }
+ else
+ {
+ /* Program the transfer size and packet count
+ * as follows: xfersize = N * maxpacket +
+ * short_packet pktcnt = N + (short_packet
+ * exist ? 1 : 0)
+ */
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+
+ if(ep->xfer_len > ep->maxpacket)
+ {
+ ep->xfer_len = ep->maxpacket;
+ }
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+
+ }
+
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+ if (dma == 1)
+ {
+ USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ }
+ else
+ {
+ /* Enable the Tx FIFO Empty Interrupt for this EP */
+ if (ep->xfer_len > 0U)
+ {
+/* MBED */
+ atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << (ep->num));
+/* MBED */
+ }
+ }
+ }
+
+ else /* OUT endpoint */
+ {
+ /* Program the transfer size and packet count as follows:
+ * pktcnt = N
+ * xfersize = N * maxpacket
+ */
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+ if (ep->xfer_len > 0U)
+ {
+ ep->xfer_len = ep->maxpacket;
+ }
+
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U));
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
+
+
+ if (dma == 1U)
+ {
+ USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+ }
+
+ /* EP enable */
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
+ * with the EP/channel
+ * @param USBx Selected device
+ * @param src pointer to source buffer
+ * @param ch_ep_num endpoint or host channel number
+ * @param len Number of bytes to write
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
+{
+ uint32_t count32b = 0U , i = 0U;
+
+ if (dma == 0U)
+ {
+ count32b = (len + 3U) / 4U;
+ for (i = 0U; i < count32b; i++, src += 4U)
+ {
+ USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
+ * with the EP/channel
+ * @param USBx Selected device
+ * @param src source pointer
+ * @param ch_ep_num endpoint or host channel number
+ * @param len Number of bytes to read
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @retval pointer to destination buffer
+ */
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+ uint32_t i=0U;
+ uint32_t count32b = (len + 3U) / 4U;
+
+ for ( i = 0U; i < count32b; i++, dest += 4U )
+ {
+ *(__packed uint32_t *)dest = USBx_DFIFO(0U);
+
+ }
+ return ((void *)dest);
+}
+
+/**
+ * @brief USB_EPSetStall : set a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
+{
+ if (ep->is_in == 1U)
+ {
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0U)
+ {
+ USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
+ }
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+ }
+ else
+ {
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0U)
+ {
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
+ }
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief USB_EPClearStall : Clear a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ if (ep->is_in == 1U)
+ {
+ USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+ if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+ {
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+ }
+ }
+ else
+ {
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+ if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+ {
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_StopDevice : Stop the usb device mode
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t i;
+
+ /* Clear Pending interrupt */
+ for (i = 0U; i < 15U ; i++)
+ {
+ USBx_INEP(i)->DIEPINT = 0xFFU;
+ USBx_OUTEP(i)->DOEPINT = 0xFFU;
+ }
+ USBx_DEVICE->DAINT = 0xFFFFFFFFU;
+
+ /* Clear interrupt masks */
+ USBx_DEVICE->DIEPMSK = 0U;
+ USBx_DEVICE->DOEPMSK = 0U;
+ USBx_DEVICE->DAINTMSK = 0U;
+
+ /* Flush the FIFO */
+ USB_FlushRxFifo(USBx);
+ USB_FlushTxFifo(USBx , 0x10U);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetDevAddress : Stop the usb device mode
+ * @param USBx Selected device
+ * @param address new device address to be assigned
+ * This parameter can be a value from 0 to 255
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+{
+ USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
+ USBx_DEVICE->DCFG |= (address << 4U) & USB_OTG_DCFG_DAD ;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
+{
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
+ HAL_Delay(3U);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
+{
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
+ HAL_Delay(3U);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ReadInterrupts: return the global USB interrupt status
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t v = 0U;
+
+ v = USBx->GINTSTS;
+ v &= USBx->GINTMSK;
+ return v;
+}
+
+/**
+ * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t v;
+ v = USBx_DEVICE->DAINT;
+ v &= USBx_DEVICE->DAINTMSK;
+ return ((v & 0xffff0000U) >> 16U);
+}
+
+/**
+ * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t v;
+ v = USBx_DEVICE->DAINT;
+ v &= USBx_DEVICE->DAINTMSK;
+ return ((v & 0xFFFFU));
+}
+
+/**
+ * @brief Returns Device OUT EP Interrupt register
+ * @param USBx Selected device
+ * @param epnum endpoint number
+ * This parameter can be a value from 0 to 15
+ * @retval Device OUT EP Interrupt register
+ */
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+{
+ uint32_t v;
+ v = USBx_OUTEP(epnum)->DOEPINT;
+ v &= USBx_DEVICE->DOEPMSK;
+ return v;
+}
+
+/**
+ * @brief Returns Device IN EP Interrupt register
+ * @param USBx Selected device
+ * @param epnum endpoint number
+ * This parameter can be a value from 0 to 15
+ * @retval Device IN EP Interrupt register
+ */
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+{
+ uint32_t v, msk, emp;
+
+ msk = USBx_DEVICE->DIEPMSK;
+ emp = USBx_DEVICE->DIEPEMPMSK;
+ msk |= ((emp >> epnum) & 0x1U) << 7U;
+ v = USBx_INEP(epnum)->DIEPINT & msk;
+ return v;
+}
+
+/**
+ * @brief USB_ClearInterrupts: clear a USB interrupt
+ * @param USBx Selected device
+ * @param interrupt interrupt flag
+ * @retval None
+ */
+void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+{
+ USBx->GINTSTS |= interrupt;
+}
+
+/**
+ * @brief Returns USB core mode
+ * @param USBx Selected device
+ * @retval return core mode : Host or Device
+ * This parameter can be one of these values:
+ * 0 : Host
+ * 1 : Device
+ */
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+{
+ return ((USBx->GINTSTS ) & 0x1U);
+}
+
+
+/**
+ * @brief Activate EP0 for Setup transactions
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
+{
+ /* Set the MPS of the IN EP based on the enumeration speed */
+ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
+
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+ {
+ USBx_INEP(0U)->DIEPCTL |= 3U;
+ }
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Prepare the EP0 to start the first control setup
+ * @param USBx Selected device
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @param psetup pointer to setup packet
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+{
+ USBx_OUTEP(0U)->DOEPTSIZ = 0U;
+ USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U)) ;
+ USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
+ USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
+
+ if (dma == 1U)
+ {
+ USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
+ /* EP enable */
+ USBx_OUTEP(0U)->DOEPCTL = 0x80008000U;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Reset the USB Core (needed after USB clock settings change)
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t count = 0U;
+
+ /* Wait for AHB master IDLE state. */
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+ /* Core Soft Reset */
+ count = 0U;
+ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief USB_HostInit : Initializes the USB OTG controller registers
+ * for Host mode
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+ uint32_t i;
+
+ /* Restart the Phy Clock */
+ USBx_PCGCCTL = 0U;
+
+ /* Activate VBUS Sensing B */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+#else
+ USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
+ USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
+ USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+ /* Disable the FS/LS support mode only */
+ if((cfg.speed == USB_OTG_SPEED_FULL)&&
+ (USBx != USB_OTG_FS))
+ {
+ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+ }
+ else
+ {
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+ }
+
+ /* Make sure the FIFOs are flushed. */
+ USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
+ USB_FlushRxFifo(USBx);
+
+ /* Clear all pending HC Interrupts */
+ for (i = 0U; i < cfg.Host_channels; i++)
+ {
+ USBx_HC(i)->HCINT = 0xFFFFFFFFU;
+ USBx_HC(i)->HCINTMSK = 0U;
+ }
+
+ /* Enable VBUS driving */
+ USB_DriveVbus(USBx, 1U);
+
+ HAL_Delay(200U);
+
+ /* Disable all interrupts. */
+ USBx->GINTMSK = 0U;
+
+ /* Clear any pending interrupts */
+ USBx->GINTSTS = 0xFFFFFFFFU;
+
+ if(USBx == USB_OTG_FS)
+ {
+ /* set Rx FIFO size */
+ USBx->GRXFSIZ = 0x80U;
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60U << 16U)& USB_OTG_NPTXFD) | 0x80U);
+ USBx->HPTXFSIZ = (uint32_t )(((0x40U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
+ }
+ else
+ {
+ /* set Rx FIFO size */
+ USBx->GRXFSIZ = 0x200U;
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100U << 16U)& USB_OTG_NPTXFD) | 0x200U);
+ USBx->HPTXFSIZ = (uint32_t )(((0xE0U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
+ }
+
+ /* Enable the common interrupts */
+ if (cfg.dma_enable == DISABLE)
+ {
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+ }
+
+ /* Enable interrupts matching to the Host mode ONLY */
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
+ USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
+ * HCFG register on the PHY type and set the right frame interval
+ * @param USBx Selected device
+ * @param freq clock frequency
+ * This parameter can be one of these values:
+ * HCFG_48_MHZ : Full Speed 48 MHz Clock
+ * HCFG_6_MHZ : Low Speed 6 MHz Clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
+{
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
+ USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
+
+ if (freq == HCFG_48_MHZ)
+ {
+ USBx_HOST->HFIR = 48000U;
+ }
+ else if (freq == HCFG_6_MHZ)
+ {
+ USBx_HOST->HFIR = 6000U;
+ }
+ return HAL_OK;
+}
+
+/**
+* @brief USB_OTG_ResetPort : Reset Host Port
+ * @param USBx Selected device
+ * @retval HAL status
+ * @note (1)The application must wait at least 10 ms
+ * before clearing the reset bit.
+ */
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+{
+ __IO uint32_t hprt0;
+
+ hprt0 = USBx_HPRT0;
+
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+
+ USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
+ HAL_Delay (10U); /* See Note #1 */
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DriveVbus : activate or de-activate vbus
+ * @param state VBUS state
+ * This parameter can be one of these values:
+ * 0 : VBUS Active
+ * 1 : VBUS Inactive
+ * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+{
+ __IO uint32_t hprt0;
+
+ hprt0 = USBx_HPRT0;
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
+ {
+ USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
+ }
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
+ {
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Return Host Core speed
+ * @param USBx Selected device
+ * @retval speed : Host speed
+ * This parameter can be one of these values:
+ * @arg USB_OTG_SPEED_HIGH: High speed mode
+ * @arg USB_OTG_SPEED_FULL: Full speed mode
+ * @arg USB_OTG_SPEED_LOW: Low speed mode
+ */
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
+{
+ __IO uint32_t hprt0;
+
+ hprt0 = USBx_HPRT0;
+ return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17U);
+}
+
+/**
+ * @brief Return Host Current Frame number
+ * @param USBx Selected device
+ * @retval current frame number
+*/
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
+{
+ return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
+}
+
+/**
+ * @brief Initialize a host channel
+ * @param USBx Selected device
+ * @param ch_num Channel number
+ * This parameter can be a value from 1 to 15
+ * @param epnum Endpoint number
+ * This parameter can be a value from 1 to 15
+ * @param dev_address Current device address
+ * This parameter can be a value from 0 to 255
+ * @param speed Current device speed
+ * This parameter can be one of these values:
+ * @arg USB_OTG_SPEED_HIGH: High speed mode
+ * @arg USB_OTG_SPEED_FULL: Full speed mode
+ * @arg USB_OTG_SPEED_LOW: Low speed mode
+ * @param ep_type Endpoint Type
+ * This parameter can be one of these values:
+ * @arg EP_TYPE_CTRL: Control type
+ * @arg EP_TYPE_ISOC: Isochronous type
+ * @arg EP_TYPE_BULK: Bulk type
+ * @arg EP_TYPE_INTR: Interrupt type
+ * @param mps Max Packet Size
+ * This parameter can be a value from 0 to32K
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps)
+{
+
+ /* Clear old interrupt conditions for this host channel. */
+ USBx_HC(ch_num)->HCINT = 0xFFFFFFFFU;
+
+ /* Enable channel interrupts required for this transfer. */
+ switch (ep_type)
+ {
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
+
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
+ USB_OTG_HCINTMSK_STALLM |\
+ USB_OTG_HCINTMSK_TXERRM |\
+ USB_OTG_HCINTMSK_DTERRM |\
+ USB_OTG_HCINTMSK_AHBERR |\
+ USB_OTG_HCINTMSK_NAKM ;
+
+ if (epnum & 0x80U)
+ {
+ USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+ }
+ else
+ {
+ if(USBx != USB_OTG_FS)
+ {
+ USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+ }
+ }
+ break;
+
+ case EP_TYPE_INTR:
+
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
+ USB_OTG_HCINTMSK_STALLM |\
+ USB_OTG_HCINTMSK_TXERRM |\
+ USB_OTG_HCINTMSK_DTERRM |\
+ USB_OTG_HCINTMSK_NAKM |\
+ USB_OTG_HCINTMSK_AHBERR |\
+ USB_OTG_HCINTMSK_FRMORM ;
+
+ if (epnum & 0x80U)
+ {
+ USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+ }
+
+ break;
+ case EP_TYPE_ISOC:
+
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
+ USB_OTG_HCINTMSK_ACKM |\
+ USB_OTG_HCINTMSK_AHBERR |\
+ USB_OTG_HCINTMSK_FRMORM ;
+
+ if (epnum & 0x80U)
+ {
+ USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+ }
+ break;
+ }
+
+ /* Enable the top level host channel interrupt. */
+ USBx_HOST->HAINTMSK |= (1 << ch_num);
+
+ /* Make sure host channel interrupts are enabled. */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
+
+ /* Program the HCCHAR register */
+ USBx_HC(ch_num)->HCCHAR = (((dev_address << 22U) & USB_OTG_HCCHAR_DAD) |\
+ (((epnum & 0x7FU)<< 11U) & USB_OTG_HCCHAR_EPNUM)|\
+ ((((epnum & 0x80U) == 0x80U)<< 15U) & USB_OTG_HCCHAR_EPDIR)|\
+ (((speed == USB_OTG_SPEED_LOW)<< 17U) & USB_OTG_HCCHAR_LSDEV)|\
+ ((ep_type << 18U) & USB_OTG_HCCHAR_EPTYP)|\
+ (mps & USB_OTG_HCCHAR_MPSIZ));
+
+ if (ep_type == EP_TYPE_INTR)
+ {
+ USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start a transfer over a host channel
+ * @param USBx Selected device
+ * @param hc pointer to host channel structure
+ * @param dma USB dma enabled or disabled
+ * This parameter can be one of these values:
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @retval HAL state
+ */
+#if defined (__CC_ARM) /*!< ARM Compiler */
+#pragma O0
+#elif defined (__GNUC__) /*!< GNU Compiler */
+#pragma GCC optimize ("O0")
+#endif /* __CC_ARM */
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
+{
+ uint8_t is_oddframe = 0;
+ uint16_t len_words = 0;
+ uint16_t num_packets = 0;
+ uint16_t max_hc_pkt_count = 256;
+ uint32_t tmpreg = 0U;
+
+ if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
+ {
+ if((dma == 0) && (hc->do_ping == 1U))
+ {
+ USB_DoPing(USBx, hc->ch_num);
+ return HAL_OK;
+ }
+ else if(dma == 1)
+ {
+ USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+ hc->do_ping = 0U;
+ }
+ }
+
+ /* Compute the expected number of packets associated to the transfer */
+ if (hc->xfer_len > 0U)
+ {
+ num_packets = (hc->xfer_len + hc->max_packet - 1U) / hc->max_packet;
+
+ if (num_packets > max_hc_pkt_count)
+ {
+ num_packets = max_hc_pkt_count;
+ hc->xfer_len = num_packets * hc->max_packet;
+ }
+ }
+ else
+ {
+ num_packets = 1;
+ }
+ if (hc->ep_is_in)
+ {
+ hc->xfer_len = num_packets * hc->max_packet;
+ }
+
+ /* Initialize the HCTSIZn register */
+ USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
+ ((num_packets << 19U) & USB_OTG_HCTSIZ_PKTCNT) |\
+ (((hc->data_pid) << 29U) & USB_OTG_HCTSIZ_DPID);
+
+ if (dma)
+ {
+ /* xfer_buff MUST be 32-bits aligned */
+ USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+ }
+
+ is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
+ USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+ USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
+
+ /* Set host channel enable */
+ tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
+
+ if (dma == 0) /* Slave mode */
+ {
+ if((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+ {
+ switch(hc->ep_type)
+ {
+ /* Non periodic transfer */
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
+
+ len_words = (hc->xfer_len + 3) / 4;
+
+ /* check if there is enough space in FIFO space */
+ if(len_words > (USBx->HNPTXSTS & 0xFFFF))
+ {
+ /* need to process data in nptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+ }
+ break;
+ /* Periodic transfer */
+ case EP_TYPE_INTR:
+ case EP_TYPE_ISOC:
+ len_words = (hc->xfer_len + 3) / 4;
+ /* check if there is enough space in FIFO space */
+ if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
+ {
+ /* need to process data in ptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Write packet into the Tx FIFO. */
+ USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
+/* MBED */
+ hc->xfer_count = hc->xfer_len;
+/* MBED */
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read all host channel interrupts status
+ * @param USBx Selected device
+ * @retval HAL state
+ */
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
+{
+ return ((USBx_HOST->HAINT) & 0xFFFFU);
+}
+
+/**
+ * @brief Halt a host channel
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
+ * This parameter can be a value from 1 to 15
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
+{
+ uint32_t count = 0U;
+
+ /* Check for space in the request queue to issue the halt. */
+ if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) || (((((USBx_HC(hc_num)->HCCHAR) &
+ USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK)))
+ {
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+ if ((USBx->HNPTXSTS & 0xFF0000U) == 0U)
+ {
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ do
+ {
+ if (++count > 1000U)
+ {
+ break;
+ }
+ }
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ }
+ else
+ {
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ }
+ }
+ else
+ {
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+ if ((USBx_HOST->HPTXSTS & 0xFFFFU) == 0U)
+ {
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ do
+ {
+ if (++count > 1000U)
+ {
+ break;
+ }
+ }
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ }
+ else
+ {
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initiate Do Ping protocol
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
+ * This parameter can be a value from 1 to 15
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
+{
+ uint8_t num_packets = 1U;
+ uint32_t tmpreg = 0U;
+
+ USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19U) & USB_OTG_HCTSIZ_PKTCNT) |\
+ USB_OTG_HCTSIZ_DOPING;
+
+ /* Set host channel enable */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop Host Core
+ * @param USBx Selected device
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint8_t i;
+ uint32_t count = 0U;
+ uint32_t value;
+
+ USB_DisableGlobalInt(USBx);
+
+ /* Flush FIFO */
+ USB_FlushTxFifo(USBx, 0x10U);
+ USB_FlushRxFifo(USBx);
+
+ /* Flush out any leftover queued requests. */
+ for (i = 0; i <= 15; i++)
+ {
+
+ value = USBx_HC(i)->HCCHAR ;
+ value |= USB_OTG_HCCHAR_CHDIS;
+ value &= ~USB_OTG_HCCHAR_CHENA;
+ value &= ~USB_OTG_HCCHAR_EPDIR;
+ USBx_HC(i)->HCCHAR = value;
+ }
+
+ /* Halt all channels to put them into a known state. */
+ for (i = 0; i <= 15; i++)
+ {
+ value = USBx_HC(i)->HCCHAR ;
+
+ value |= USB_OTG_HCCHAR_CHDIS;
+ value |= USB_OTG_HCCHAR_CHENA;
+ value &= ~USB_OTG_HCCHAR_EPDIR;
+
+ USBx_HC(i)->HCCHAR = value;
+ do
+ {
+ if (++count > 1000U)
+ {
+ break;
+ }
+ }
+ while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ }
+
+ /* Clear any pending Host interrupts */
+ USBx_HOST->HAINT = 0xFFFFFFFFU;
+ USBx->GINTSTS = 0xFFFFFFFFU;
+ USB_EnableGlobalInt(USBx);
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+ STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,475 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_usb.h
+ * @author MCD Application Team
+ * @brief Header file of USB Core HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_USB_H
+#define __STM32F4xx_LL_USB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+ defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+ * @{
+ */
+
+/** @addtogroup USB_Core
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief USB Mode definition
+ */
+typedef enum
+{
+ USB_OTG_DEVICE_MODE = 0U,
+ USB_OTG_HOST_MODE = 1U,
+ USB_OTG_DRD_MODE = 2U
+
+}USB_OTG_ModeTypeDef;
+
+/**
+ * @brief URB States definition
+ */
+typedef enum {
+ URB_IDLE = 0U,
+ URB_DONE,
+ URB_NOTREADY,
+ URB_NYET,
+ URB_ERROR,
+ URB_STALL
+
+}USB_OTG_URBStateTypeDef;
+
+/**
+ * @brief Host channel States definition
+ */
+typedef enum {
+ HC_IDLE = 0U,
+ HC_XFRC,
+ HC_HALTED,
+ HC_NAK,
+ HC_NYET,
+ HC_STALL,
+ HC_XACTERR,
+ HC_BBLERR,
+ HC_DATATGLERR
+
+}USB_OTG_HCStateTypeDef;
+
+/**
+ * @brief PCD Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t Host_channels; /*!< Host Channels number.
+ This parameter Depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
+
+ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */
+
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
+ This parameter can be any value of @ref USB_EP0_MPS_ */
+
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref USB_Core_PHY_ */
+
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+
+ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+
+ uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
+
+ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
+
+ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+
+}USB_OTG_CfgTypeDef;
+
+/**
+ * @brief OTG End Point Initialization Structure definition
+ */
+typedef struct
+{
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_EP_Type_ */
+
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t even_odd_frame; /*!< IFrame parity
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint16_t tx_fifo_num; /*!< Transmission FIFO number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
+
+ uint32_t xfer_len; /*!< Current transfer length */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+
+}USB_OTG_EPTypeDef;
+
+/**
+ * @brief OTG HC Initialization Structure definition
+ */
+typedef struct
+{
+ uint8_t dev_addr ; /*!< USB device address.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
+
+ uint8_t ch_num; /*!< Host channel number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t ep_num; /*!< Endpoint number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t ep_is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t speed; /*!< USB Host speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
+
+ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
+
+ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
+
+ uint8_t ep_type; /*!< Endpoint Type.
+ This parameter can be any value of @ref USB_EP_Type_ */
+
+ uint16_t max_packet; /*!< Endpoint Max packet size.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t data_pid; /*!< Initial data PID.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
+
+ uint32_t xfer_len; /*!< Current transfer length. */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
+
+ uint8_t toggle_in; /*!< IN transfer current toggle flag.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t toggle_out; /*!< OUT transfer current toggle flag
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
+
+ uint32_t ErrCnt; /*!< Host channel error count.*/
+
+ USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
+ This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+
+ USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
+ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
+
+}USB_OTG_HCTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+/** @defgroup USB_Core_Mode_ USB Core Mode
+ * @{
+ */
+#define USB_OTG_MODE_DEVICE 0U
+#define USB_OTG_MODE_HOST 1U
+#define USB_OTG_MODE_DRD 2U
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_Speed_ USB Core Speed
+ * @{
+ */
+#define USB_OTG_SPEED_HIGH 0U
+#define USB_OTG_SPEED_HIGH_IN_FULL 1U
+#define USB_OTG_SPEED_LOW 2U
+#define USB_OTG_SPEED_FULL 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_PHY_ USB Core PHY
+ * @{
+ */
+#define USB_OTG_ULPI_PHY 1U
+#define USB_OTG_EMBEDDED_PHY 2U
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_MPS_ USB Core MPS
+ * @{
+ */
+#define USB_OTG_HS_MAX_PACKET_SIZE 512U
+#define USB_OTG_FS_MAX_PACKET_SIZE 64U
+#define USB_OTG_MAX_EP0_SIZE 64U
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency
+ * @{
+ */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1U)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1U)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1U)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1U)
+/**
+ * @}
+ */
+
+/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval
+ * @{
+ */
+#define DCFG_FRAME_INTERVAL_80 0U
+#define DCFG_FRAME_INTERVAL_85 1U
+#define DCFG_FRAME_INTERVAL_90 2U
+#define DCFG_FRAME_INTERVAL_95 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP0_MPS_ USB EP0 MPS
+ * @{
+ */
+#define DEP0CTL_MPS_64 0U
+#define DEP0CTL_MPS_32 1U
+#define DEP0CTL_MPS_16 2U
+#define DEP0CTL_MPS_8 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP_Speed_ USB EP Speed
+ * @{
+ */
+#define EP_SPEED_LOW 0U
+#define EP_SPEED_FULL 1U
+#define EP_SPEED_HIGH 2U
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP_Type_ USB EP Type
+ * @{
+ */
+#define EP_TYPE_CTRL 0U
+#define EP_TYPE_ISOC 1U
+#define EP_TYPE_BULK 2U
+#define EP_TYPE_INTR 3U
+#define EP_TYPE_MSK 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_STS_Defines_ USB STS Defines
+ * @{
+ */
+#define STS_GOUT_NAK 1U
+#define STS_DATA_UPDT 2U
+#define STS_XFER_COMP 3U
+#define STS_SETUP_COMP 4U
+#define STS_SETUP_UPDT 6U
+/**
+ * @}
+ */
+
+/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
+ * @{
+ */
+#define HCFG_30_60_MHZ 0U
+#define HCFG_48_MHZ 1U
+#define HCFG_6_MHZ 2U
+/**
+ * @}
+ */
+
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
+ * @{
+ */
+#define HPRT0_PRTSPD_HIGH_SPEED 0U
+#define HPRT0_PRTSPD_FULL_SPEED 1U
+#define HPRT0_PRTSPD_LOW_SPEED 2U
+/**
+ * @}
+ */
+
+#define HCCHAR_CTRL 0U
+#define HCCHAR_ISOC 1U
+#define HCCHAR_BULK 2U
+#define HCCHAR_INTR 3U
+
+#define HC_PID_DATA0 0U
+#define HC_PID_DATA2 1U
+#define HC_PID_DATA1 2U
+#define HC_PID_SETUP 3U
+
+#define GRXSTS_PKTSTS_IN 2U
+#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
+#define GRXSTS_PKTSTS_CH_HALTED 7U
+
+#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
+#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
+#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
+
+#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
+#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+ STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+ STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_LL_USB_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,751 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_utils.c
+ * @author MCD Application Team
+ * @brief UTILS LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_utils.h"
+#include "stm32f4xx_ll_rcc.h"
+#include "stm32f4xx_ll_system.h"
+#include "stm32f4xx_ll_pwr.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup UTILS_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+ * @{
+ */
+#if defined(RCC_MAX_FREQUENCY_SCALE1)
+#define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
+#endif /*RCC_MAX_FREQUENCY_SCALE1 */
+#define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */
+#if defined(RCC_MAX_FREQUENCY_SCALE3)
+#define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */
+#endif /* MAX_FREQUENCY_SCALE3 */
+
+/* Defines used for PLL range */
+#define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */
+#define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */
+#define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */
+#define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#if defined(FLASH_SCALE1_LATENCY1_FREQ)
+#define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#endif
+#if defined(FLASH_SCALE1_LATENCY2_FREQ)
+#define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#endif
+#if defined(FLASH_SCALE1_LATENCY3_FREQ)
+#define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#endif
+#if defined(FLASH_SCALE1_LATENCY4_FREQ)
+#define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#endif
+#if defined(FLASH_SCALE1_LATENCY5_FREQ)
+#define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
+#endif
+#define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#if defined(FLASH_SCALE2_LATENCY3_FREQ)
+#define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#endif
+#if defined(FLASH_SCALE2_LATENCY4_FREQ)
+#define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
+#endif
+#if defined(FLASH_SCALE2_LATENCY5_FREQ)
+#define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
+#endif
+#if defined(FLASH_SCALE3_LATENCY1_FREQ)
+#define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#endif
+#if defined(FLASH_SCALE3_LATENCY2_FREQ)
+#define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+#endif
+#if defined(FLASH_SCALE3_LATENCY3_FREQ)
+#define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
+#endif
+#if defined(FLASH_SCALE3_LATENCY4_FREQ)
+#define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
+#endif
+#if defined(FLASH_SCALE3_LATENCY5_FREQ)
+#define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */
+#endif
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
+
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))
+
+#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
+ || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
+ || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
+ || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
+
+#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
+
+#if !defined(RCC_MAX_FREQUENCY_SCALE1)
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
+ ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
+
+#elif defined(RCC_MAX_FREQUENCY_SCALE3)
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+ (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
+ ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
+
+#else
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+ ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
+
+#endif /* RCC_MAX_FREQUENCY_SCALE1*/
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+ * @{
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
+ * @note When a RTOS is used, it is recommended to avoid changing the Systick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param HCLKFrequency HCLK frequency in Hz
+ * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+ * @retval None
+ */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+ /* Use frequency provided in argument */
+ LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on SysTick counter flag
+ * @note When a RTOS is used, it is recommended to avoid using blocking delay
+ * and use rather osDelay service.
+ * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+ * will configure Systick to 1ms
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+void LL_mDelay(uint32_t Delay)
+{
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ /* Add this code to indicate that local variable is not used */
+ ((void)tmp);
+
+ /* Add a period to guaranty minimum wait */
+ if(Delay < LL_MAX_DELAY)
+ {
+ Delay++;
+ }
+
+ while (Delay)
+ {
+ if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ {
+ Delay--;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.
+ @endverbatim
+ @internal
+ Depending on the device voltage range, the maximum frequency should be
+ adapted accordingly to the Refenece manual.
+ @endinternal
+ * @{
+ */
+
+/**
+ * @brief This function sets directly SystemCoreClock CMSIS variable.
+ * @note Variable can be calculated also through SystemCoreClockUpdate function.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @retval None
+ */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+ /* HCLK clock frequency */
+ SystemCoreClock = HCLKFrequency;
+}
+
+/**
+ * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
+ * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
+ * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check if one of the PLL is enabled */
+ if(UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+ /* Enable HSI if not enabled */
+ if(LL_RCC_HSI_IsReady() != 1U)
+ {
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1U)
+ {
+ /* Wait for HSI ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+ UTILS_PLLInitStruct->PLLP);
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock with HSE as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
+ * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
+ * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
+ * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
+ * @param HSEBypass This parameter can be one of the following values:
+ * @arg @ref LL_UTILS_HSEBYPASS_ON
+ * @arg @ref LL_UTILS_HSEBYPASS_OFF
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+ assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+ /* Check if one of the PLL is enabled */
+ if(UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+ /* Enable HSE if not enabled */
+ if(LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Check if need to enable HSE bypass feature or not */
+ if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
+ {
+ LL_RCC_HSE_EnableBypass();
+ }
+ else
+ {
+ LL_RCC_HSE_DisableBypass();
+ }
+
+ /* Enable HSE */
+ LL_RCC_HSE_Enable();
+ while (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Wait for HSE ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+ UTILS_PLLInitStruct->PLLP);
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
+/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
+ * @param HCLK_Frequency HCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
+{
+ ErrorStatus status = SUCCESS;
+
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+ /* Frequency cannot be equal to 0 */
+ if(HCLK_Frequency == 0U)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+ {
+#if defined (UTILS_SCALE1_LATENCY5_FREQ)
+ if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_5;
+ }
+#endif /*UTILS_SCALE1_LATENCY5_FREQ */
+#if defined (UTILS_SCALE1_LATENCY4_FREQ)
+ if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_4;
+ }
+#endif /* UTILS_SCALE1_LATENCY4_FREQ */
+#if defined (UTILS_SCALE1_LATENCY3_FREQ)
+ if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_3;
+ }
+#endif /* UTILS_SCALE1_LATENCY3_FREQ */
+#if defined (UTILS_SCALE1_LATENCY2_FREQ)
+ if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_1;
+ }
+ }
+#endif /* UTILS_SCALE1_LATENCY2_FREQ */
+ }
+ if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
+ {
+#if defined (UTILS_SCALE2_LATENCY5_FREQ)
+ if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_5;
+ }
+#endif /*UTILS_SCALE1_LATENCY5_FREQ */
+#if defined (UTILS_SCALE2_LATENCY4_FREQ)
+ if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_4;
+ }
+#endif /*UTILS_SCALE1_LATENCY4_FREQ */
+#if defined (UTILS_SCALE2_LATENCY3_FREQ)
+ if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_3;
+ }
+#endif /*UTILS_SCALE1_LATENCY3_FREQ */
+ if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_1;
+ }
+ }
+ }
+#if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
+ if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
+ {
+#if defined (UTILS_SCALE3_LATENCY3_FREQ)
+ if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_3;
+ }
+#endif /*UTILS_SCALE1_LATENCY3_FREQ */
+#if defined (UTILS_SCALE3_LATENCY2_FREQ)
+ if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
+ {
+ latency = LL_FLASH_LATENCY_1;
+ }
+ }
+ }
+#endif /*UTILS_SCALE1_LATENCY2_FREQ */
+#endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
+
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(LL_FLASH_GetLatency() != latency)
+ {
+ status = ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @param PLL_InputFrequency PLL input frequency (in Hz)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @retval PLL output frequency (in Hz)
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+ assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+ assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
+
+ /* Check different PLL parameters according to RM */
+ /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */
+ pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
+ assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
+
+ /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/
+ pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
+ assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
+
+ /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */
+ pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
+ assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+ return pllfreq;
+}
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PLL modification can be done
+ * - ERROR: PLL is busy
+ */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check if PLL is busy*/
+ if(LL_RCC_PLL_IsReady() != 0U)
+ {
+ /* PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+#if defined(RCC_PLLSAI_SUPPORT)
+ /* Check if PLLSAI is busy*/
+ if(LL_RCC_PLLSAI_IsReady() != 0U)
+ {
+ /* PLLSAI1 configuration cannot be modified */
+ status = ERROR;
+ }
+#endif /*RCC_PLLSAI_SUPPORT*/
+#if defined(RCC_PLLI2S_SUPPORT)
+ /* Check if PLLI2S is busy*/
+ if(LL_RCC_PLLI2S_IsReady() != 0U)
+ {
+ /* PLLI2S configuration cannot be modified */
+ status = ERROR;
+ }
+#endif /*RCC_PLLI2S_SUPPORT*/
+ return status;
+}
+
+/**
+ * @brief Function to enable PLL and switch system clock to PLL
+ * @param SYSCLK_Frequency SYSCLK frequency
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: No problem to switch system to PLL
+ * - ERROR: Problem to switch system to PLL
+ */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t hclk_frequency = 0U;
+
+ assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+ assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+ assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+
+ /* Calculate HCLK frequency */
+ hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if(SystemCoreClock < hclk_frequency)
+ {
+ /* Set FLASH latency to highest latency */
+ status = UTILS_SetFlashLatency(hclk_frequency);
+ }
+
+ /* Update system clock configuration */
+ if(status == SUCCESS)
+ {
+ /* Enable PLL */
+ LL_RCC_PLL_Enable();
+ while (LL_RCC_PLL_IsReady() != 1U)
+ {
+ /* Wait for PLL ready */
+ }
+
+ /* Sysclk activation on the main PLL */
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ {
+ /* Wait for system clock switch to PLL */
+ }
+
+ /* Set APB1 & APB2 prescaler*/
+ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(SystemCoreClock > hclk_frequency)
+ {
+ /* Set FLASH latency to lowest latency */
+ status = UTILS_SetFlashLatency(hclk_frequency);
+ }
+
+ /* Update SystemCoreClock variable */
+ if(status == SUCCESS)
+ {
+ LL_SetSystemCoreClock(hclk_frequency);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,325 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_utils.h
+ * @author MCD Application Team
+ * @brief Header file of UTILS LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL UTILS driver contains a set of generic APIs that can be
+ used by user:
+ (+) Device electronic signature
+ (+) Timing functions
+ (+) PLL configuration functions
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_UTILS_H
+#define __STM32F4xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UTILS_LL UTILS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+ * @{
+ */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY 0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+ * @{
+ */
+/**
+ * @brief UTILS PLL structure definition
+ */
+typedef struct
+{
+ uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE
+ and Max_Data = @ref RCC_PLLN_MIN_VALUE
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t PLLP; /*!< Division for the main system clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+ * @brief UTILS System, AHB and APB buses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAHBPrescaler(). */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB1Prescaler(). */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+ * @{
+ */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+ * @{
+ */
+#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
+#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+ * @{
+ */
+#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type */
+#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type */
+#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 0x00000500U /*!< LQFP208 or TFBGA216 package type */
+#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+ * @{
+ */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+ * @{
+ */
+
+/**
+ * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[31:0]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+ * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[63:32]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+ * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[95:64]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+ * @brief Get Flash memory size
+ * @note This bitfield indicates the size of the device Flash memory expressed in
+ * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ * @retval FLASH_SIZE[15:0]: Flash memory size
+ */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+ return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+/**
+ * @brief Get Package type
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+ return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source of the time base.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @note When a RTOS is used, it is recommended to avoid changing the SysTick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param Ticks Number of ticks
+ * @retval None
+ */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+ /* Configure the SysTick to have interrupt in 1ms time base */
+ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
+}
+
+void LL_Init1msTick(uint32_t HCLKFrequency);
+void LL_mDelay(uint32_t Delay);
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+ * @{
+ */
+
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_UTILS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_wwdg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_wwdg.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,340 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_wwdg.h
+ * @author MCD Application Team
+ * @brief Header file of WWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_WWDG_H
+#define __STM32F4xx_LL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (WWDG)
+
+/** @defgroup WWDG_LL WWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+
+/** @defgroup WWDG_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
+ * @{
+ */
+#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
+* @{
+*/
+#define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
+ * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
+ * then it cannot be disabled again except by a reset.
+ * This bit is set by software and only cleared by hardware after a reset.
+ * When WDGA = 1, the watchdog can generate a reset.
+ * @rmtoll CR WDGA LL_WWDG_Enable
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
+}
+
+/**
+ * @brief Checks if Window Watchdog is enabled
+ * @rmtoll CR WDGA LL_WWDG_IsEnabled
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
+}
+
+/**
+ * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
+ * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
+ * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
+ * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
+ * @rmtoll CR T LL_WWDG_SetCounter
+ * @param WWDGx WWDG Instance
+ * @param Counter 0..0x7F (7 bit counter value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
+{
+ MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
+}
+
+/**
+ * @brief Return current Watchdog Counter Value (7 bits counter value)
+ * @rmtoll CR T LL_WWDG_GetCounter
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Counter value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
+}
+
+/**
+ * @brief Set the time base of the prescaler (WDGTB).
+ * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
+ * is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
+ * @param WWDGx WWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
+}
+
+/**
+ * @brief Return current Watchdog Prescaler Value
+ * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
+ * @param WWDGx WWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+}
+
+/**
+ * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
+ * @note This window value defines when write in the WWDG_CR register
+ * to program Watchdog counter is allowed.
+ * Watchdog counter value update must occur only when the counter value
+ * is lower than the Watchdog window register value.
+ * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
+ * (in the control register) is refreshed before the downcounter has reached
+ * the watchdog window register value.
+ * Physically is possible to set the Window lower then 0x40 but it is not recommended.
+ * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
+ * @rmtoll CFR W LL_WWDG_SetWindow
+ * @param WWDGx WWDG Instance
+ * @param Window 0x00..0x7F (7 bit Window value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
+}
+
+/**
+ * @brief Return current Watchdog Window Value (7 bits value)
+ * @rmtoll CFR W LL_WWDG_GetWindow
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Window value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+/**
+ * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
+ * @note This bit is set by hardware when the counter has reached the value 0x40.
+ * It must be cleared by software by writing 0.
+ * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
+ * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
+}
+
+/**
+ * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
+ * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_IT_Management IT_Management
+ * @{
+ */
+/**
+ * @brief Enable the Early Wakeup Interrupt.
+ * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
+ * This interrupt is only cleared by hardware after a reset
+ * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
+}
+
+/**
+ * @brief Check if Early Wakeup Interrupt is enabled
+ * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* WWDG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,769 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Includes
+ * @{
+ */
+
+
+#include "stm32f4xx.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+ STM32F412Zx || STM32F412Vx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+ * @{
+ */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+ * depends on the application requirements), user has to ensure that HSE_VALUE
+ * is same as the real frequency of the crystal used. Otherwise, this function
+ * may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_P
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ SystemCoreClock = pllvco/pllp;
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK frequency --------------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmp = 0x00;
+
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+ RCC->AHB1ENR |= 0x000001F8;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xCCCCCCCC;
+ GPIOF->AFR[1] = 0xCCCCCCCC;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xCCCCCCCC;
+ GPIOG->AFR[1] = 0xCCCCCCCC;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xAAAAAAAA;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xAAAAAAAA;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+
+/*-- FMC Configuration -------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+ FMC_Bank5_6->SDCR[0] = 0x000019E4;
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+ FMC_Bank5_6->SDCMR = 0x00000073;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+ FMC_Bank5_6->SDCMR = 0x00046014;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001091;
+ FMC_Bank1->BTCR[3] = 0x00110212;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+
+ (void)(tmp);
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmp = 0x00;
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (DATA_IN_ExtSDRAM)
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+#if defined(STM32F446xx)
+ /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+ clock */
+ RCC->AHB1ENR |= 0x0000007D;
+#else
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ clock */
+ RCC->AHB1ENR |= 0x000001F8;
+#endif /* STM32F446xx */
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+#if defined(STM32F446xx)
+ /* Connect PAx pins to FMC Alternate function */
+ GPIOA->AFR[0] |= 0xC0000000;
+ GPIOA->AFR[1] |= 0x00000000;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOA->MODER |= 0x00008000;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOA->OSPEEDR |= 0x00008000;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOA->OTYPER |= 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOA->PUPDR |= 0x00000000;
+
+ /* Connect PCx pins to FMC Alternate function */
+ GPIOC->AFR[0] |= 0x00CC0000;
+ GPIOC->AFR[1] |= 0x00000000;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOC->MODER |= 0x00000A00;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOC->OSPEEDR |= 0x00000A00;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOC->OTYPER |= 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOC->PUPDR |= 0x00000000;
+#endif /* STM32F446xx */
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xA02A000A;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOD->OSPEEDR = 0xA02A000A;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 50 MHz */
+ GPIOE->OSPEEDR = 0xAAAA800A;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xCCCCCCCC;
+ GPIOF->AFR[1] = 0xCCCCCCCC;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xCCCCCCCC;
+ GPIOG->AFR[1] = 0xCCCCCCCC;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xAAAAAAAA;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xAAAAAAAA;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/*-- FMC Configuration -------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+ /* Configure and enable SDRAM bank1 */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCR[0] = 0x00001954;
+#else
+ FMC_Bank5_6->SDCR[0] = 0x000019E4;
+#endif /* STM32F446xx */
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCMR = 0x000000F3;
+#else
+ FMC_Bank5_6->SDCMR = 0x00000073;
+#endif /* STM32F446xx */
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCMR = 0x00044014;
+#else
+ FMC_Bank5_6->SDCMR = 0x00046014;
+#endif /* STM32F446xx */
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
+#else
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+#endif /* STM32F446xx */
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB1ENR |= 0x00000078;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x000000C0;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00085AAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x000CAFFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
+ /* Enable the FMC/FSMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001091;
+ FMC_Bank1->BTCR[3] = 0x00110212;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+ || defined(STM32F412Zx) || defined(STM32F412Vx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FSMC_Bank1->BTCR[2] = 0x00001011;
+ FSMC_Bank1->BTCR[3] = 0x00000201;
+ FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
+ (void)(tmp);
+}
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/flash_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/flash_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,233 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#if DEVICE_FLASH
+#include "flash_api.h"
+#include "flash_data.h"
+#include "platform/mbed_critical.h"
+
+// This file is automatically generated
+
+
+static uint32_t GetSector(uint32_t Address);
+static uint32_t GetSectorSize(uint32_t Sector);
+
+int32_t flash_init(flash_t *obj)
+{
+ return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+ return 0;
+}
+
+static int32_t flash_unlock(void)
+{
+ /* Allow Access to Flash control registers and user Falsh */
+ if (HAL_FLASH_Unlock()) {
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+static int32_t flash_lock(void)
+{
+ /* Disable the Flash option control register access (recommended to protect
+ the option Bytes against possible unwanted operations) */
+ if (HAL_FLASH_Lock()) {
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+ /*Variable used for Erase procedure*/
+ static FLASH_EraseInitTypeDef EraseInitStruct;
+ uint32_t FirstSector;
+ uint32_t SectorError = 0;
+ int32_t status = 0;
+
+ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+ return -1;
+ }
+
+ if (flash_unlock() != HAL_OK) {
+ return -1;
+ }
+
+ /* Get the 1st sector to erase */
+ FirstSector = GetSector(address);
+
+ /* Fill EraseInit structure*/
+ EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;
+ EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3;
+ EraseInitStruct.Sector = FirstSector;
+ EraseInitStruct.NbSectors = 1;
+ if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) {
+ status = -1;
+ }
+
+ flash_lock();
+
+ return status;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+ int32_t status = 0;
+
+ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+ return -1;
+ }
+
+ if (flash_unlock() != HAL_OK) {
+ return -1;
+ }
+
+ /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+ you have to make sure that these data are rewritten before they are accessed during code
+ execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+ DCRST and ICRST bits in the FLASH_CR register. */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+
+ __HAL_FLASH_DATA_CACHE_RESET();
+ __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ __HAL_FLASH_DATA_CACHE_ENABLE();
+
+ while ((size > 0) && (status == 0)) {
+ if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, address, (uint64_t)*data) != HAL_OK) {
+ status = -1;
+ } else {
+ size--;
+ address++;
+ data++;
+ }
+ }
+
+ flash_lock();
+
+ return status;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+ return MBED_FLASH_INVALID_SIZE;
+ }
+
+ return (GetSectorSize(GetSector(address)));
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+ // Flash of STM32F4 devices can be programed 1 byte at a time
+ return (1);
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+ return FLASH_BASE;
+}
+uint32_t flash_get_size(const flash_t *obj)
+{
+ return FLASH_SIZE;
+}
+
+/**
+ * @brief Gets the sector of a given address
+ * @param None
+ * @retval The sector of a given address
+ */
+static uint32_t GetSector(uint32_t address)
+{
+ uint32_t sector = 0;
+ uint32_t tmp = address - ADDR_FLASH_SECTOR_0;
+ /* This function supports 1Mb and 2Mb flash sizes */
+#if defined(ADDR_FLASH_SECTOR_16)
+ if (address & 0x100000) { // handle 2nd bank
+ /* Sector will be at least 12 */
+ sector = FLASH_SECTOR_12;
+ tmp -= 0x100000;
+ address -= 0x100000;
+ }
+#endif
+ if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize
+ sector += tmp >> 14;
+ }
+#if defined(ADDR_FLASH_SECTOR_5)
+ else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size
+ sector += FLASH_SECTOR_4;
+ } else {
+ sector += 4 + (tmp >> 17);
+ }
+#else
+ // In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one.
+ else { //64k sector size
+ sector += FLASH_SECTOR_4;
+ }
+#endif
+ return sector;
+}
+
+/**
+ * @brief Gets sector Size
+ * @param None
+ * @retval The size of a given sector
+ */
+static uint32_t GetSectorSize(uint32_t Sector)
+{
+ uint32_t sectorsize = 0x00;
+#if defined(FLASH_SECTOR_16)
+ if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \
+ (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) || \
+ (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
+ sectorsize = 16 * 1024;
+ } else if ((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) {
+#else
+ if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \
+ (Sector == FLASH_SECTOR_3)) {
+ sectorsize = 16 * 1024;
+ } else if (Sector == FLASH_SECTOR_4) {
+#endif
+ sectorsize = 64 * 1024;
+ } else {
+ sectorsize = 128 * 1024;
+ }
+ return sectorsize;
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_device.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_device.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis.h"
+#include "gpio_irq_device.h"
+
+// Used to return the index for channels array.
+const exti_lines_t pin_lines_desc[16] = {
+ // EXTI0
+ {.gpio_idx = 0, .irq_index = 0, .irq_n = EXTI0_IRQn}, // pin 0
+ // EXTI1
+ {.gpio_idx = 0, .irq_index = 1, .irq_n = EXTI1_IRQn}, // pin 1
+ // EXTI2
+ {.gpio_idx = 0, .irq_index = 2, .irq_n = EXTI2_IRQn}, // pin 2
+ // EXTI3
+ {.gpio_idx = 0, .irq_index = 3, .irq_n = EXTI3_IRQn}, // pin 3
+ // EXTI4
+ {.gpio_idx = 0, .irq_index = 4, .irq_n = EXTI4_IRQn}, // pin 4
+ // EXTI5_9
+ {.gpio_idx = 0, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 5
+ {.gpio_idx = 1, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 6
+ {.gpio_idx = 2, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 7
+ {.gpio_idx = 3, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 8
+ {.gpio_idx = 4, .irq_index = 5, .irq_n = EXTI9_5_IRQn},// pin 9
+ // EXTI10_15
+ {.gpio_idx = 0, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 10
+ {.gpio_idx = 1, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 11
+ {.gpio_idx = 2, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 12
+ {.gpio_idx = 3, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 13
+ {.gpio_idx = 4, .irq_index = 6, .irq_n = EXTI15_10_IRQn},// pin 14
+ {.gpio_idx = 5, .irq_index = 6, .irq_n = EXTI15_10_IRQn}// pin 15
+};
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_device.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_device.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_IRQ_DEVICE_H
+#define MBED_GPIO_IRQ_DEVICE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stm32f4xx_ll_exti.h"
+
+// Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15)
+#define CHANNEL_NUM (7)
+
+#define EXTI_IRQ0_NUM_LINES 1
+#define EXTI_IRQ1_NUM_LINES 1
+#define EXTI_IRQ2_NUM_LINES 1
+#define EXTI_IRQ3_NUM_LINES 1
+#define EXTI_IRQ4_NUM_LINES 1
+#define EXTI_IRQ5_NUM_LINES 5
+#define EXTI_IRQ6_NUM_LINES 6
+
+// Max pins for one line (max with EXTI10_15)
+#define MAX_PIN_LINE (EXTI_IRQ6_NUM_LINES)
+
+/* Structure to describe how the HW EXTI lines are defined in this HW */
+typedef struct exti_lines {
+ uint32_t gpio_idx; // an index entry for each EXIT line
+ uint32_t irq_index; // the IRQ index
+ IRQn_Type irq_n; // the corresponding EXTI IRQn
+} exti_lines_t;
+
+// Used to return the index for channels array.
+extern const exti_lines_t pin_lines_desc[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015-2015, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "stm32f4xx_hal.h"
+
+HAL_StatusTypeDef HAL_InitPre(void);
+
+/* this function is needed to peform hardware initialization that must happen
+ * before the uVisor; the whole SystemInit function for the STM32F4 cannot be
+ * put here as it depends on some APIs that need uVisor to be enabled */
+HAL_StatusTypeDef HAL_InitPre(void)
+{
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Return function status */
+ return HAL_OK;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/i2c_device.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/i2c_device.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_I2C_DEVICE_H
+#define MBED_I2C_DEVICE_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef DEVICE_I2C
+
+/* Define IP version */
+#define I2C_IP_VERSION_V1
+
+#define I2C_IT_ALL (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR)
+
+#endif // DEVICE_I2C
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/pin_device.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/pin_device.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PIN_DEVICE_H
+#define MBED_PIN_DEVICE_H
+
+#include "cmsis.h"
+
+// when LL is available, below include can be used
+// #include "stm32f4xx_ll_gpio.h"
+// until then let's define locally the required functions
+#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
+
+#define LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
+
+#define LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
+
+#define LL_GPIO_PULL_NO ((uint32_t)0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
+
+#define LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Select I/O low output speed */
+#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
+
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[0], (0xFU << (POSITION_VAL(Pin) * 4U)),
+ (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[1], (0xFU << (POSITION_VAL(Pin >> 8U) * 4U)),
+ (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+ MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
+}
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+ MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
+{
+ MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
+ (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+// Above lines shall be defined in LL when available
+
+extern const uint32_t ll_pin_defines[16];
+
+/* Family specific implementations */
+static inline void stm_pin_DisconnectDebug(PinName pin)
+{
+ /* empty for now */
+}
+
+static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
+{
+ switch (pull_config) {
+ case GPIO_PULLUP:
+ LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP);
+ break;
+ case GPIO_PULLDOWN:
+ LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN);
+ break;
+ default:
+ LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_NO);
+ break;
+ }
+}
+
+static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
+{
+ uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
+
+ if (STM_PIN(pin) > 7) {
+ LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
+ } else {
+ LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
+ }
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis.h"
+#include "pwmout_api.h"
+#include "pwmout_device.h"
+
+#ifdef DEVICE_PWMOUT
+
+const pwm_apb_map_t pwm_apb_map_table[] = {
+#if defined(TIM2_BASE)
+ {PWM_2, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM3_BASE)
+ {PWM_3, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM4_BASE)
+ {PWM_4, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM5_BASE)
+ {PWM_5, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM12_BASE)
+ {PWM_12, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM13_BASE)
+ {PWM_13, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM14_BASE)
+ {PWM_14, PWMOUT_ON_APB1},
+#endif
+#if defined(TIM1_BASE)
+ {PWM_1, PWMOUT_ON_APB2},
+#endif
+#if defined(TIM8_BASE)
+ {PWM_8, PWMOUT_ON_APB2},
+#endif
+#if defined(TIM9_BASE)
+ {PWM_9, PWMOUT_ON_APB2},
+#endif
+#if defined(TIM10_BASE)
+ {PWM_10, PWMOUT_ON_APB2},
+#endif
+#if defined(TIM11_BASE)
+ {PWM_11, PWMOUT_ON_APB2},
+#endif
+ {(PWMName) 0, PWMOUT_UNKNOWN}
+};
+
+#endif // DEVICE_PWMOUT
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PWMOUT_DEVICE_H
+#define MBED_PWMOUT_DEVICE_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef DEVICE_PWMOUT
+
+typedef enum {
+ PWMOUT_ON_APB1 = 0,
+ PWMOUT_ON_APB2 = 1,
+ PWMOUT_UNKNOWN = 2
+} PwmoutApb;
+
+/* Structure to describe Timers to APB */
+typedef struct pwm_apb_map {
+ PWMName pwm; // an index entry for each EXIT line
+ PwmoutApb pwmoutApb;
+} pwm_apb_map_t;
+
+extern const pwm_apb_map_t pwm_apb_map_table[];
+
+#endif // DEVICE_PWMOUT
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/serial_device.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/serial_device.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,790 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#if DEVICE_SERIAL
+
+#include "serial_api_hal.h"
+
+#if defined (TARGET_STM32F401xC) || defined (TARGET_STM32F401xE) || defined (TARGET_STM32F410xB) || defined (TARGET_STM32F411xE)
+#define UART_NUM (3)
+#elif defined (TARGET_STM32F412xG)
+#define UART_NUM (4)
+#elif defined (TARGET_STM32F407xG) || defined (TARGET_STM32F446xE)
+#define UART_NUM (6)
+#elif defined (TARGET_STM32F429xI) || defined (TARGET_STM32F439xI) || defined (TARGET_STM32F437xG) || defined (TARGET_STM32F469xI)
+#define UART_NUM (8)
+#else
+#define UART_NUM (10) // max value // TARGET_STM32F413xH
+#endif
+
+uint32_t serial_irq_ids[UART_NUM] = {0};
+UART_HandleTypeDef uart_handlers[UART_NUM];
+
+static uart_irq_handler irq_handler;
+
+// Defined in serial_api.c
+extern int8_t get_uart_index(UARTName uart_name);
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+static void uart_irq(UARTName uart_name)
+{
+ int8_t id = get_uart_index(uart_name);
+
+ if (id >= 0) {
+ UART_HandleTypeDef *huart = &uart_handlers[id];
+ if (serial_irq_ids[id] != 0) {
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+ if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
+ irq_handler(serial_irq_ids[id], TxIrq);
+ }
+ }
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
+ if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) {
+ irq_handler(serial_irq_ids[id], RxIrq);
+ /* Flag has been cleared when reading the content */
+ }
+ }
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
+ if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
+ volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
+ }
+ }
+ }
+ }
+}
+
+#if defined(USART1_BASE)
+static void uart1_irq(void)
+{
+ uart_irq(UART_1);
+}
+#endif
+
+#if defined(USART2_BASE)
+static void uart2_irq(void)
+{
+ uart_irq(UART_2);
+}
+#endif
+
+#if defined(USART3_BASE)
+static void uart3_irq(void)
+{
+ uart_irq(UART_3);
+}
+#endif
+
+#if defined(UART4_BASE)
+static void uart4_irq(void)
+{
+ uart_irq(UART_4);
+}
+#endif
+
+#if defined(UART5_BASE)
+static void uart5_irq(void)
+{
+ uart_irq(UART_5);
+}
+#endif
+
+#if defined(USART6_BASE)
+static void uart6_irq(void)
+{
+ uart_irq(UART_6);
+}
+#endif
+
+#if defined(UART7_BASE)
+static void uart7_irq(void)
+{
+ uart_irq(UART_7);
+}
+#endif
+
+#if defined(UART8_BASE)
+static void uart8_irq(void)
+{
+ uart_irq(UART_8);
+}
+#endif
+
+#if defined(UART9_BASE)
+static void uart9_irq(void)
+{
+ uart_irq(UART_9);
+}
+#endif
+
+#if defined(UART10_BASE)
+static void uart10_irq(void)
+{
+ uart_irq(UART_10);
+}
+#endif
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+
+ irq_handler = handler;
+ serial_irq_ids[obj_s->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+
+ switch (obj_s->uart) {
+#if defined(USART1_BASE)
+ case UART_1:
+ irq_n = USART1_IRQn;
+ vector = (uint32_t)&uart1_irq;
+ break;
+#endif
+#if defined(USART2_BASE)
+ case UART_2:
+ irq_n = USART2_IRQn;
+ vector = (uint32_t)&uart2_irq;
+ break;
+#endif
+#if defined(USART3_BASE)
+ case UART_3:
+ irq_n = USART3_IRQn;
+ vector = (uint32_t)&uart3_irq;
+ break;
+#endif
+#if defined(UART4_BASE)
+ case UART_4:
+ irq_n = UART4_IRQn;
+ vector = (uint32_t)&uart4_irq;
+ break;
+#endif
+#if defined(UART5_BASE)
+ case UART_5:
+ irq_n = UART5_IRQn;
+ vector = (uint32_t)&uart5_irq;
+ break;
+#endif
+#if defined(USART6_BASE)
+ case UART_6:
+ irq_n = USART6_IRQn;
+ vector = (uint32_t)&uart6_irq;
+ break;
+#endif
+#if defined(UART7_BASE)
+ case UART_7:
+ irq_n = UART7_IRQn;
+ vector = (uint32_t)&uart7_irq;
+ break;
+#endif
+#if defined(UART8_BASE)
+ case UART_8:
+ irq_n = UART8_IRQn;
+ vector = (uint32_t)&uart8_irq;
+ break;
+#endif
+#if defined(UART9_BASE)
+ case UART_9:
+ irq_n = UART9_IRQn;
+ vector = (uint32_t)&uart9_irq;
+ break;
+#endif
+#if defined(UART10_BASE)
+ case UART_10:
+ irq_n = UART10_IRQn;
+ vector = (uint32_t)&uart10_irq;
+ break;
+#endif
+ }
+
+ if (enable) {
+ if (irq == RxIrq) {
+ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+ } else { // TxIrq
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+ }
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ } else { // disable
+ int all_disabled = 0;
+ if (irq == RxIrq) {
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+ // Check if TxIrq is disabled too
+ if ((huart->Instance->CR1 & USART_CR1_TXEIE) == 0) {
+ all_disabled = 1;
+ }
+ } else { // TxIrq
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+ // Check if RxIrq is disabled too
+ if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
+ all_disabled = 1;
+ }
+ }
+
+ if (all_disabled) {
+ NVIC_DisableIRQ(irq_n);
+ }
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+
+int serial_getc(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ while (!serial_readable(obj));
+ return (int)(huart->Instance->DR & 0x1FF);
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ while (!serial_writable(obj));
+ huart->Instance->DR = (uint32_t)(c & 0x1FF);
+}
+
+void serial_clear(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ huart->TxXferCount = 0;
+ huart->RxXferCount = 0;
+}
+
+void serial_break_set(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ HAL_LIN_SendBreak(huart);
+}
+
+#if DEVICE_SERIAL_ASYNCH
+
+/******************************************************************************
+ * LOCAL HELPER FUNCTIONS
+ ******************************************************************************/
+
+/**
+ * Configure the TX buffer for an asynchronous write serial transaction
+ *
+ * @param obj The serial object.
+ * @param tx The buffer for sending.
+ * @param tx_length The number of words to transmit.
+ */
+static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width)
+{
+ (void)width;
+
+ // Exit if a transmit is already on-going
+ if (serial_tx_active(obj)) {
+ return;
+ }
+
+ obj->tx_buff.buffer = tx;
+ obj->tx_buff.length = tx_length;
+ obj->tx_buff.pos = 0;
+}
+
+/**
+ * Configure the RX buffer for an asynchronous write serial transaction
+ *
+ * @param obj The serial object.
+ * @param tx The buffer for sending.
+ * @param tx_length The number of words to transmit.
+ */
+static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width)
+{
+ (void)width;
+
+ // Exit if a reception is already on-going
+ if (serial_rx_active(obj)) {
+ return;
+ }
+
+ obj->rx_buff.buffer = rx;
+ obj->rx_buff.length = rx_length;
+ obj->rx_buff.pos = 0;
+}
+
+/**
+ * Configure events
+ *
+ * @param obj The serial object
+ * @param event The logical OR of the events to configure
+ * @param enable Set to non-zero to enable events, or zero to disable them
+ */
+static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+
+ // Shouldn't have to enable interrupt here, just need to keep track of the requested events.
+ if (enable) {
+ obj_s->events |= event;
+ } else {
+ obj_s->events &= ~event;
+ }
+}
+
+
+/**
+* Get index of serial object TX IRQ, relating it to the physical peripheral.
+*
+* @param uart_name i.e. UART_1, UART_2, ...
+* @return internal NVIC TX IRQ index of U(S)ART peripheral
+*/
+static IRQn_Type serial_get_irq_n(UARTName uart_name)
+{
+ IRQn_Type irq_n;
+
+ switch (uart_name) {
+#if defined(USART1_BASE)
+ case UART_1:
+ irq_n = USART1_IRQn;
+ break;
+#endif
+#if defined(USART2_BASE)
+ case UART_2:
+ irq_n = USART2_IRQn;
+ break;
+#endif
+#if defined(USART3_BASE)
+ case UART_3:
+ irq_n = USART3_IRQn;
+ break;
+#endif
+#if defined(UART4_BASE)
+ case UART_4:
+ irq_n = UART4_IRQn;
+ break;
+#endif
+#if defined(UART5_BASE)
+ case UART_5:
+ irq_n = UART5_IRQn;
+ break;
+#endif
+#if defined(USART6_BASE)
+ case UART_6:
+ irq_n = USART6_IRQn;
+ break;
+#endif
+#if defined(UART7_BASE)
+ case UART_7:
+ irq_n = UART7_IRQn;
+ break;
+#endif
+#if defined(UART8_BASE)
+ case UART_8:
+ irq_n = UART8_IRQn;
+ break;
+#endif
+#if defined(UART9_BASE)
+ case UART_9:
+ irq_n = UART9_IRQn;
+ break;
+#endif
+#if defined(UART10_BASE)
+ case UART_10:
+ irq_n = UART10_IRQn;
+ break;
+#endif
+ default:
+ irq_n = (IRQn_Type)0;
+ }
+
+ return irq_n;
+}
+
+/******************************************************************************
+ * MBED API FUNCTIONS
+ ******************************************************************************/
+
+/**
+ * Begin asynchronous TX transfer. The used buffer is specified in the serial
+ * object, tx_buff
+ *
+ * @param obj The serial object
+ * @param tx The buffer for sending
+ * @param tx_length The number of words to transmit
+ * @param tx_width The bit width of buffer word
+ * @param handler The serial handler
+ * @param event The logical OR of events to be registered
+ * @param hint A suggestion for how to use DMA with this transfer
+ * @return Returns number of data transfered, or 0 otherwise
+ */
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ // TODO: DMA usage is currently ignored
+ (void) hint;
+
+ // Check buffer is ok
+ MBED_ASSERT(tx != (void *)0);
+ MBED_ASSERT(tx_width == 8); // support only 8b width
+
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ if (tx_length == 0) {
+ return 0;
+ }
+
+ // Set up buffer
+ serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
+
+ // Set up events
+ serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
+ serial_enable_event(obj, event, 1); // Set only the wanted events
+
+ // Enable interrupt
+ IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_DisableIRQ(irq_n);
+ NVIC_SetPriority(irq_n, 1);
+ NVIC_SetVector(irq_n, (uint32_t)handler);
+ NVIC_EnableIRQ(irq_n);
+
+ // the following function will enable UART_IT_TXE and error interrupts
+ if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
+ return 0;
+ }
+
+ return tx_length;
+}
+
+/**
+ * Begin asynchronous RX transfer (enable interrupt for data collecting)
+ * The used buffer is specified in the serial object, rx_buff
+ *
+ * @param obj The serial object
+ * @param rx The buffer for sending
+ * @param rx_length The number of words to transmit
+ * @param rx_width The bit width of buffer word
+ * @param handler The serial handler
+ * @param event The logical OR of events to be registered
+ * @param handler The serial handler
+ * @param char_match A character in range 0-254 to be matched
+ * @param hint A suggestion for how to use DMA with this transfer
+ */
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+ // TODO: DMA usage is currently ignored
+ (void) hint;
+
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ MBED_ASSERT(rx != (void *)0);
+ MBED_ASSERT(rx_width == 8); // support only 8b width
+
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
+ serial_enable_event(obj, event, 1);
+
+ // set CharMatch
+ obj->char_match = char_match;
+
+ serial_rx_buffer_set(obj, rx, rx_length, rx_width);
+
+ IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_DisableIRQ(irq_n);
+ NVIC_SetPriority(irq_n, 0);
+ NVIC_SetVector(irq_n, (uint32_t)handler);
+ NVIC_EnableIRQ(irq_n);
+
+ // following HAL function will enable the RXNE interrupt + error interrupts
+ HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
+}
+
+/**
+ * Attempts to determine if the serial peripheral is already in use for TX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the TX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_tx_active(serial_t *obj)
+{
+ MBED_ASSERT(obj);
+
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ return (((HAL_UART_GetState(huart) & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
+}
+
+/**
+ * Attempts to determine if the serial peripheral is already in use for RX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_rx_active(serial_t *obj)
+{
+ MBED_ASSERT(obj);
+
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ return (((HAL_UART_GetState(huart) & HAL_UART_STATE_BUSY_RX) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
+ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+ }
+}
+
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
+ volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
+ } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
+ volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear FE flag
+ } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
+ volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear NE flag
+ } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
+ volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
+ }
+}
+
+/**
+ * The asynchronous TX and RX handler.
+ *
+ * @param obj The serial object
+ * @return Returns event flags if a TX/RX transfer termination condition was met or 0 otherwise
+ */
+int serial_irq_handler_asynch(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ volatile int return_event = 0;
+ uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
+ uint8_t i = 0;
+
+ // TX PART:
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
+ if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
+ // Return event SERIAL_EVENT_TX_COMPLETE if requested
+ if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
+ return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
+ }
+ }
+ }
+
+ // Handle error events
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
+ if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
+ return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
+ }
+ }
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
+ if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
+ return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
+ }
+ }
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
+ if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
+ return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
+ }
+ }
+
+ HAL_UART_IRQHandler(huart);
+
+ // Abort if an error occurs
+ if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+ (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+ (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
+ return return_event;
+ }
+
+ //RX PART
+ if (huart->RxXferSize != 0) {
+ obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
+ }
+ if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
+ return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
+ }
+
+ // Check if char_match is present
+ if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
+ if (buf != NULL) {
+ for (i = 0; i < obj->rx_buff.pos; i++) {
+ if (buf[i] == obj->char_match) {
+ obj->rx_buff.pos = i;
+ return_event |= (SERIAL_EVENT_RX_CHARACTER_MATCH & obj_s->events);
+ serial_rx_abort_asynch(obj);
+ break;
+ }
+ }
+ }
+ }
+
+ return return_event;
+}
+
+/**
+ * Abort the ongoing TX transaction. It disables the enabled interupt for TX and
+ * flush TX hardware buffer if TX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_tx_abort_asynch(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+
+ // clear flags
+ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+
+ // reset states
+ huart->TxXferCount = 0;
+ // update handle state
+ if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
+ huart->gState = HAL_UART_STATE_BUSY_RX;
+ } else {
+ huart->gState = HAL_UART_STATE_READY;
+ }
+}
+
+/**
+ * Abort the ongoing RX transaction It disables the enabled interrupt for RX and
+ * flush RX hardware buffer if RX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_rx_abort_asynch(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ // disable interrupts
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ // clear flags
+ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+ volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag
+
+ // reset states
+ huart->RxXferCount = 0;
+ // update handle state
+ if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
+ huart->RxState = HAL_UART_STATE_BUSY_TX;
+ } else {
+ huart->RxState = HAL_UART_STATE_READY;
+ }
+}
+
+#endif /* DEVICE_SERIAL_ASYNCH */
+
+#if DEVICE_SERIAL_FC
+
+/**
+ * Set HW Control Flow
+ * @param obj The serial object
+ * @param type The Control Flow type (FlowControlNone, FlowControlRTS, FlowControlCTS, FlowControlRTSCTS)
+ * @param rxflow Pin for the rxflow
+ * @param txflow Pin for the txflow
+ */
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+
+ // Determine the UART to use (UART_1, UART_2, ...)
+ UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
+ UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
+
+ // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+ obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
+ MBED_ASSERT(obj_s->uart != (UARTName)NC);
+
+ if (type == FlowControlNone) {
+ // Disable hardware flow control
+ obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
+ }
+ if (type == FlowControlRTS) {
+ // Enable RTS
+ MBED_ASSERT(uart_rts != (UARTName)NC);
+ obj_s->hw_flow_ctl = UART_HWCONTROL_RTS;
+ obj_s->pin_rts = rxflow;
+ // Enable the pin for RTS function
+ pinmap_pinout(rxflow, PinMap_UART_RTS);
+ }
+ if (type == FlowControlCTS) {
+ // Enable CTS
+ MBED_ASSERT(uart_cts != (UARTName)NC);
+ obj_s->hw_flow_ctl = UART_HWCONTROL_CTS;
+ obj_s->pin_cts = txflow;
+ // Enable the pin for CTS function
+ pinmap_pinout(txflow, PinMap_UART_CTS);
+ }
+ if (type == FlowControlRTSCTS) {
+ // Enable CTS & RTS
+ MBED_ASSERT(uart_rts != (UARTName)NC);
+ MBED_ASSERT(uart_cts != (UARTName)NC);
+ obj_s->hw_flow_ctl = UART_HWCONTROL_RTS_CTS;
+ obj_s->pin_rts = rxflow;
+ obj_s->pin_cts = txflow;
+ // Enable the pin for CTS function
+ pinmap_pinout(txflow, PinMap_UART_CTS);
+ // Enable the pin for RTS function
+ pinmap_pinout(rxflow, PinMap_UART_RTS);
+ }
+
+ init_uart(obj);
+}
+
+#endif /* DEVICE_SERIAL_FC */
+
+#endif /* DEVICE_SERIAL */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/spi_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/spi_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "spi_api.h"
+
+#if DEVICE_SPI
+#include <stdbool.h>
+#include <math.h>
+#include <string.h>
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+#if DEVICE_SPI_ASYNCH
+#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
+#else
+#define SPI_S(obj) (( struct spi_s *)(obj))
+#endif
+
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ int spi_hz = 0;
+
+ /* Get source clock depending on SPI instance */
+ switch ((int)spiobj->spi) {
+ case SPI_1:
+#if defined SPI4_BASE
+ case SPI_4:
+#endif
+#if defined SPI5_BASE
+ case SPI_5:
+#endif
+#if defined SPI6_BASE
+ case SPI_6:
+#endif
+ /* SPI_1, SPI_4, SPI_5 and SPI_6. Source CLK is PCKL2 */
+ spi_hz = HAL_RCC_GetPCLK2Freq();
+ break;
+ case SPI_2:
+#if defined SPI3_BASE
+ case SPI_3:
+#endif
+ /* SPI_2 and SPI_3. Source CLK is PCKL1 */
+ spi_hz = HAL_RCC_GetPCLK1Freq();
+ break;
+ default:
+ error("CLK: SPI instance not set");
+ break;
+ }
+ return spi_hz;
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/spi_device.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/spi_device.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,35 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_SPI_DEVICE_H +#define MBED_SPI_DEVICE_H + +#include "stm32f4xx_ll_spi.h" + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/analogin_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/analogin_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+uint16_t adc_read(analogin_t *obj);
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ uint16_t value = adc_read(obj);
+ // 12-bit to 16-bit conversion
+ value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
+ return value;
+}
+
+float analogin_read(analogin_t *obj)
+{
+ uint16_t value = adc_read(obj);
+ return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/analogout_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/analogout_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogout_api.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+#define DAC_RANGE (0xFFF) // 12 bits
+#define DAC_NB_BITS (12)
+
+static inline void dac_write(dac_t *obj, int value)
+{
+ HAL_DAC_SetValue(&obj->handle, obj->channel, DAC_ALIGN_12B_R, (value & DAC_RANGE));
+ HAL_DAC_Start(&obj->handle, obj->channel);
+}
+
+static inline int dac_read(dac_t *obj)
+{
+ return (int)HAL_DAC_GetValue(&obj->handle, obj->channel);
+}
+
+void analogout_write(dac_t *obj, float value)
+{
+ if (value < 0.0f) {
+ dac_write(obj, 0); // Min value
+ } else if (value > 1.0f) {
+ dac_write(obj, (int)DAC_RANGE); // Max value
+ } else {
+ dac_write(obj, (int)(value * (float)DAC_RANGE));
+ }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value)
+{
+ dac_write(obj, value >> (16 - DAC_NB_BITS));
+}
+
+float analogout_read(dac_t *obj)
+{
+ uint32_t value = dac_read(obj);
+ return (float)value * (1.0f / (float)DAC_RANGE);
+}
+
+uint16_t analogout_read_u16(dac_t *obj)
+{
+ uint32_t value = dac_read(obj);
+ return (value << 4) | ((value >> 8) & 0x000F); // Conversion from 12 to 16 bits
+}
+
+#endif // DEVICE_ANALOGOUT
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/can_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/can_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,719 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "can_api.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "mbed_error.h"
+#include "can_device.h" // Specific to STM32 serie
+#include <math.h>
+#include <string.h>
+
+static uint32_t can_irq_ids[CAN_NUM] = {0};
+static can_irq_handler irq_handler;
+
+static void can_registers_init(can_t *obj)
+{
+ if (HAL_CAN_Init(&obj->CanHandle) != HAL_OK) {
+ error("Cannot initialize CAN");
+ }
+
+ // Set initial CAN frequency to specified frequency
+ if (can_frequency(obj, obj->hz) != 1) {
+ error("Can frequency could not be set\n");
+ }
+}
+
+void can_init(can_t *obj, PinName rd, PinName td)
+{
+ can_init_freq(obj, rd, td, 100000);
+}
+
+void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
+{
+ CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+ CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+ CANName can = (CANName)pinmap_merge(can_rd, can_td);
+
+ MBED_ASSERT((int)can != NC);
+
+ if (can == CAN_1) {
+ __HAL_RCC_CAN1_CLK_ENABLE();
+ obj->index = 0;
+ }
+#if defined(CAN2_BASE) && (CAN_NUM > 1)
+ else if (can == CAN_2) {
+ __HAL_RCC_CAN1_CLK_ENABLE(); // needed to set filters
+ __HAL_RCC_CAN2_CLK_ENABLE();
+ obj->index = 1;
+ }
+#endif
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
+ else if (can == CAN_3) {
+ __HAL_RCC_CAN3_CLK_ENABLE();
+ obj->index = 2;
+ }
+#endif
+ else {
+ return;
+ }
+
+ // Configure the CAN pins
+ pinmap_pinout(rd, PinMap_CAN_RD);
+ pinmap_pinout(td, PinMap_CAN_TD);
+ if (rd != NC) {
+ pin_mode(rd, PullUp);
+ }
+ if (td != NC) {
+ pin_mode(td, PullUp);
+ }
+
+ /* Use default values for rist init */
+ obj->CanHandle.Instance = (CAN_TypeDef *)can;
+ obj->CanHandle.Init.TTCM = DISABLE;
+ obj->CanHandle.Init.ABOM = DISABLE;
+ obj->CanHandle.Init.AWUM = DISABLE;
+ obj->CanHandle.Init.NART = DISABLE;
+ obj->CanHandle.Init.RFLM = DISABLE;
+ obj->CanHandle.Init.TXFP = DISABLE;
+ obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
+ obj->CanHandle.Init.SJW = CAN_SJW_1TQ;
+ obj->CanHandle.Init.BS1 = CAN_BS1_6TQ;
+ obj->CanHandle.Init.BS2 = CAN_BS2_8TQ;
+ obj->CanHandle.Init.Prescaler = 2;
+
+ /* Store frequency to be restored in case of reset */
+ obj->hz = hz;
+
+ can_registers_init(obj);
+
+ /* Bits 27:14 are available for dual CAN configuration and are reserved for
+ single CAN configuration: */
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
+ uint32_t filter_number = (can == CAN_1 || can == CAN_3) ? 0 : 14;
+#else
+ uint32_t filter_number = (can == CAN_1) ? 0 : 14;
+#endif
+ can_filter(obj, 0, 0, CANStandard, filter_number);
+}
+
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
+{
+ irq_handler = handler;
+ can_irq_ids[obj->index] = id;
+}
+
+void can_irq_free(can_t *obj)
+{
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+
+ can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \
+ CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF);
+ can_irq_ids[obj->index] = 0;
+}
+
+void can_free(can_t *obj)
+{
+ CANName can = (CANName) obj->CanHandle.Instance;
+ // Reset CAN and disable clock
+ if (can == CAN_1) {
+ __HAL_RCC_CAN1_FORCE_RESET();
+ __HAL_RCC_CAN1_RELEASE_RESET();
+ __HAL_RCC_CAN1_CLK_DISABLE();
+ }
+#if defined(CAN2_BASE) && (CAN_NUM > 1)
+ if (can == CAN_2) {
+ __HAL_RCC_CAN2_FORCE_RESET();
+ __HAL_RCC_CAN2_RELEASE_RESET();
+ __HAL_RCC_CAN2_CLK_DISABLE();
+ }
+#endif
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
+ if (can == CAN_3) {
+ __HAL_RCC_CAN3_FORCE_RESET();
+ __HAL_RCC_CAN3_RELEASE_RESET();
+ __HAL_RCC_CAN3_CLK_DISABLE();
+ }
+#endif
+}
+
+// The following table is used to program bit_timing. It is an adjustment of the sample
+// point by synchronizing on the start-bit edge and resynchronizing on the following edges.
+// This table has the sampling points as close to 75% as possible (most commonly used).
+// The first value is TSEG1, the second TSEG2.
+static const int timing_pts[23][2] = {
+ {0x0, 0x0}, // 2, 50%
+ {0x1, 0x0}, // 3, 67%
+ {0x2, 0x0}, // 4, 75%
+ {0x3, 0x0}, // 5, 80%
+ {0x3, 0x1}, // 6, 67%
+ {0x4, 0x1}, // 7, 71%
+ {0x5, 0x1}, // 8, 75%
+ {0x6, 0x1}, // 9, 78%
+ {0x6, 0x2}, // 10, 70%
+ {0x7, 0x2}, // 11, 73%
+ {0x8, 0x2}, // 12, 75%
+ {0x9, 0x2}, // 13, 77%
+ {0x9, 0x3}, // 14, 71%
+ {0xA, 0x3}, // 15, 73%
+ {0xB, 0x3}, // 16, 75%
+ {0xC, 0x3}, // 17, 76%
+ {0xD, 0x3}, // 18, 78%
+ {0xD, 0x4}, // 19, 74%
+ {0xE, 0x4}, // 20, 75%
+ {0xF, 0x4}, // 21, 76%
+ {0xF, 0x5}, // 22, 73%
+ {0xF, 0x6}, // 23, 70%
+ {0xF, 0x7}, // 24, 67%
+};
+
+static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw)
+{
+ uint32_t btr;
+ uint16_t brp = 0;
+ uint32_t calcbit;
+ uint32_t bitwidth;
+ int hit = 0;
+ int bits;
+
+ bitwidth = (pclk / cclk);
+
+ brp = bitwidth / 0x18;
+ while ((!hit) && (brp < bitwidth / 4)) {
+ brp++;
+ for (bits = 22; bits > 0; bits--) {
+ calcbit = (bits + 3) * (brp + 1);
+ if (calcbit == bitwidth) {
+ hit = 1;
+ break;
+ }
+ }
+ }
+
+ if (hit) {
+ btr = ((timing_pts[bits][1] << CAN_BTR_TS2_Pos) & CAN_BTR_TS2) |
+ ((timing_pts[bits][0] << CAN_BTR_TS1_Pos) & CAN_BTR_TS1) |
+ ((psjw << CAN_BTR_SJW_Pos) & CAN_BTR_SJW) |
+ ((brp << CAN_BTR_BRP_Pos) & CAN_BTR_BRP);
+ } else {
+ btr = 0xFFFFFFFF;
+ }
+
+ return btr;
+
+}
+
+int can_frequency(can_t *obj, int f)
+{
+ int pclk = HAL_RCC_GetPCLK1Freq();
+ int btr = can_speed(pclk, (unsigned int)f, 1);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+ uint32_t tickstart = 0;
+ int status = 1;
+
+ if (btr > 0) {
+ can->MCR |= CAN_MCR_INRQ ;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
+ if ((HAL_GetTick() - tickstart) > 2) {
+ status = 0;
+ break;
+ }
+ }
+ if (status != 0) {
+ /* Do not erase all BTR registers (e.g. silent mode), only the
+ * ones calculated in can_speed */
+ can->BTR &= ~(CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_SJW | CAN_BTR_BRP);
+ can->BTR |= btr;
+
+ can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
+ if ((HAL_GetTick() - tickstart) > 2) {
+ status = 0;
+ break;
+ }
+ }
+ if (status == 0) {
+ error("can ESR 0x%04x.%04x + timeout status %d", (can->ESR & 0xFFFF0000) >> 16, (can->ESR & 0xFFFF), status);
+ }
+ } else {
+ error("can init request timeout\n");
+ }
+ } else {
+ status = 0;
+ }
+ return status;
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+
+ /* Select one empty transmit mailbox */
+ if ((can->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
+ transmitmailbox = 0;
+ } else if ((can->TSR & CAN_TSR_TME1) == CAN_TSR_TME1) {
+ transmitmailbox = 1;
+ } else if ((can->TSR & CAN_TSR_TME2) == CAN_TSR_TME2) {
+ transmitmailbox = 2;
+ } else {
+ return 0;
+ }
+
+ can->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (!(msg.format)) {
+ can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | (msg.type << 1));
+ } else {
+ can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | (msg.type << 1));
+ }
+
+ /* Set up the DLC */
+ can->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ can->sTxMailBox[transmitmailbox].TDTR |= (msg.len & (uint8_t)0x0000000F);
+
+ /* Set up the data field */
+ can->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)msg.data[3] << 24) |
+ ((uint32_t)msg.data[2] << 16) |
+ ((uint32_t)msg.data[1] << 8) |
+ ((uint32_t)msg.data[0]));
+ can->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)msg.data[7] << 24) |
+ ((uint32_t)msg.data[6] << 16) |
+ ((uint32_t)msg.data[5] << 8) |
+ ((uint32_t)msg.data[4]));
+ /* Request transmission */
+ can->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ return 1;
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle)
+{
+ //handle is the FIFO number
+
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+
+ // check FPM0 which holds the pending message count in FIFO 0
+ // if no message is pending, return 0
+ if ((can->RF0R & CAN_RF0R_FMP0) == 0) {
+ return 0;
+ }
+
+ /* Get the Id */
+ msg->format = (CANFormat)(((uint8_t)0x04 & can->sFIFOMailBox[handle].RIR) >> 2);
+ if (!msg->format) {
+ msg->id = (uint32_t)0x000007FF & (can->sFIFOMailBox[handle].RIR >> 21);
+ } else {
+ msg->id = (uint32_t)0x1FFFFFFF & (can->sFIFOMailBox[handle].RIR >> 3);
+ }
+
+ msg->type = (CANType)(((uint8_t)0x02 & can->sFIFOMailBox[handle].RIR) >> 1);
+ /* Get the DLC */
+ msg->len = (uint8_t)0x0F & can->sFIFOMailBox[handle].RDTR;
+ /* Get the FMI */
+ // msg->FMI = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDTR >> 8);
+ /* Get the data field */
+ msg->data[0] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDLR;
+ msg->data[1] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 8);
+ msg->data[2] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 16);
+ msg->data[3] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 24);
+ msg->data[4] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDHR;
+ msg->data[5] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 8);
+ msg->data[6] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 16);
+ msg->data[7] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 24);
+
+ /* Release the FIFO */
+ if (handle == CAN_FIFO0) {
+ /* Release FIFO0 */
+ can->RF0R |= CAN_RF0R_RFOM0;
+ } else { /* FIFONumber == CAN_FIFO1 */
+ /* Release FIFO1 */
+ can->RF1R |= CAN_RF1R_RFOM1;
+ }
+
+ return 1;
+}
+
+void can_reset(can_t *obj)
+{
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+
+ /* Reset IP and delete errors */
+ can->MCR |= CAN_MCR_RESET;
+ can->ESR = 0x0;
+
+ /* restore registers state as saved in obj context */
+ can_registers_init(obj);
+}
+
+unsigned char can_rderror(can_t *obj)
+{
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+ return (can->ESR >> 24) & 0xFF;
+}
+
+unsigned char can_tderror(can_t *obj)
+{
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+ return (can->ESR >> 16) & 0xFF;
+}
+
+void can_monitor(can_t *obj, int silent)
+{
+ CanMode mode = MODE_NORMAL;
+ /* Update current state w/ or w/o silent */
+ if (silent) {
+ switch (obj->CanHandle.Init.Mode) {
+ case CAN_MODE_LOOPBACK:
+ case CAN_MODE_SILENT_LOOPBACK:
+ mode = MODE_TEST_SILENT;
+ break;
+ default:
+ mode = MODE_SILENT;
+ break;
+ }
+ } else {
+ switch (obj->CanHandle.Init.Mode) {
+ case CAN_MODE_LOOPBACK:
+ case CAN_MODE_SILENT_LOOPBACK:
+ mode = MODE_TEST_LOCAL;
+ break;
+ default:
+ mode = MODE_NORMAL;
+ break;
+ }
+ }
+
+ can_mode(obj, mode);
+}
+
+int can_mode(can_t *obj, CanMode mode)
+{
+ int success = 0;
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+
+ can->MCR |= CAN_MCR_INRQ ;
+ while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
+ }
+
+ switch (mode) {
+ case MODE_NORMAL:
+ obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
+ can->BTR &= ~(CAN_BTR_SILM | CAN_BTR_LBKM);
+ success = 1;
+ break;
+ case MODE_SILENT:
+ obj->CanHandle.Init.Mode = CAN_MODE_SILENT;
+ can->BTR |= CAN_BTR_SILM;
+ can->BTR &= ~CAN_BTR_LBKM;
+ success = 1;
+ break;
+ case MODE_TEST_GLOBAL:
+ case MODE_TEST_LOCAL:
+ obj->CanHandle.Init.Mode = CAN_MODE_LOOPBACK;
+ can->BTR |= CAN_BTR_LBKM;
+ can->BTR &= ~CAN_BTR_SILM;
+ success = 1;
+ break;
+ case MODE_TEST_SILENT:
+ obj->CanHandle.Init.Mode = CAN_MODE_SILENT_LOOPBACK;
+ can->BTR |= (CAN_BTR_SILM | CAN_BTR_LBKM);
+ success = 1;
+ break;
+ default:
+ success = 0;
+ break;
+ }
+
+ can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+ while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
+ }
+
+ return success;
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
+{
+ int retval = 0;
+
+ // filter for CANAny format cannot be configured for STM32
+ if ((format == CANStandard) || (format == CANExtended)) {
+ CAN_FilterConfTypeDef sFilterConfig;
+ sFilterConfig.FilterNumber = handle;
+ sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
+ sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT;
+
+ if (format == CANStandard) {
+ sFilterConfig.FilterIdHigh = id << 5;
+ sFilterConfig.FilterIdLow = 0x0;
+ sFilterConfig.FilterMaskIdHigh = mask << 5;
+ sFilterConfig.FilterMaskIdLow = 0x0; // allows both remote and data frames
+ } else { // format == CANExtended
+ sFilterConfig.FilterIdHigh = id >> 13; // EXTID[28:13]
+ sFilterConfig.FilterIdLow = (0xFFFF & (id << 3)) | (1 << 2); // EXTID[12:0] + IDE
+ sFilterConfig.FilterMaskIdHigh = mask >> 13;
+ sFilterConfig.FilterMaskIdLow = (0xFFFF & (mask << 3)) | (1 << 2);
+ }
+
+ sFilterConfig.FilterFIFOAssignment = 0;
+ sFilterConfig.FilterActivation = ENABLE;
+ sFilterConfig.BankNumber = 14 + handle;
+
+ HAL_CAN_ConfigFilter(&obj->CanHandle, &sFilterConfig);
+ retval = handle;
+ }
+ return retval;
+}
+
+static void can_irq(CANName name, int id)
+{
+ uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+ CAN_HandleTypeDef CanHandle;
+ CanHandle.Instance = (CAN_TypeDef *)name;
+
+ if (__HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_TME)) {
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_0);
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_1);
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_2);
+ if (tmp1) {
+ __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP0);
+ }
+ if (tmp2) {
+ __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP1);
+ }
+ if (tmp3) {
+ __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP2);
+ }
+ if (tmp1 || tmp2 || tmp3) {
+ irq_handler(can_irq_ids[id], IRQ_TX);
+ }
+ }
+
+ tmp1 = __HAL_CAN_MSG_PENDING(&CanHandle, CAN_FIFO0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_FMP0);
+
+ if ((tmp1 != 0) && tmp2) {
+ irq_handler(can_irq_ids[id], IRQ_RX);
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_EPV);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_EPV);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
+
+ if (tmp1 && tmp2 && tmp3) {
+ irq_handler(can_irq_ids[id], IRQ_PASSIVE);
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_BOF);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_BOF);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
+ if (tmp1 && tmp2 && tmp3) {
+ irq_handler(can_irq_ids[id], IRQ_BUS);
+ }
+
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
+ if (tmp1 && tmp2 && tmp3) {
+ irq_handler(can_irq_ids[id], IRQ_ERROR);
+ }
+}
+
+#if defined(TARGET_STM32F0)
+void CAN_IRQHandler(void)
+{
+ can_irq(CAN_1, 0);
+}
+#elif defined(TARGET_STM32F3)
+void CAN_RX0_IRQHandler(void)
+{
+ can_irq(CAN_1, 0);
+}
+void CAN_TX_IRQHandler(void)
+{
+ can_irq(CAN_1, 0);
+}
+void CAN_SCE_IRQHandler(void)
+{
+ can_irq(CAN_1, 0);
+}
+#else
+void CAN1_RX0_IRQHandler(void)
+{
+ can_irq(CAN_1, 0);
+}
+void CAN1_TX_IRQHandler(void)
+{
+ can_irq(CAN_1, 0);
+}
+void CAN1_SCE_IRQHandler(void)
+{
+ can_irq(CAN_1, 0);
+}
+#if defined(CAN2_BASE) && (CAN_NUM > 1)
+void CAN2_RX0_IRQHandler(void)
+{
+ can_irq(CAN_2, 1);
+}
+void CAN2_TX_IRQHandler(void)
+{
+ can_irq(CAN_2, 1);
+}
+void CAN2_SCE_IRQHandler(void)
+{
+ can_irq(CAN_2, 1);
+}
+#endif
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
+void CAN3_RX0_IRQHandler(void)
+{
+ can_irq(CAN_3, 2);
+}
+void CAN3_TX_IRQHandler(void)
+{
+ can_irq(CAN_3, 2);
+}
+void CAN3_SCE_IRQHandler(void)
+{
+ can_irq(CAN_3, 2);
+}
+#endif
+#endif // else
+
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
+{
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ uint32_t ier;
+
+ if ((CANName) can == CAN_1) {
+ switch (type) {
+ case IRQ_RX:
+ ier = CAN_IT_FMP0;
+ irq_n = CAN1_IRQ_RX_IRQN;
+ vector = (uint32_t)&CAN1_IRQ_RX_VECT;
+ break;
+ case IRQ_TX:
+ ier = CAN_IT_TME;
+ irq_n = CAN1_IRQ_TX_IRQN;
+ vector = (uint32_t)&CAN1_IRQ_TX_VECT;
+ break;
+ case IRQ_ERROR:
+ ier = CAN_IT_ERR;
+ irq_n = CAN1_IRQ_ERROR_IRQN;
+ vector = (uint32_t)&CAN1_IRQ_ERROR_VECT;
+ break;
+ case IRQ_PASSIVE:
+ ier = CAN_IT_EPV;
+ irq_n = CAN1_IRQ_PASSIVE_IRQN;
+ vector = (uint32_t)&CAN1_IRQ_PASSIVE_VECT;
+ break;
+ case IRQ_BUS:
+ ier = CAN_IT_BOF;
+ irq_n = CAN1_IRQ_BUS_IRQN;
+ vector = (uint32_t)&CAN1_IRQ_BUS_VECT;
+ break;
+ default:
+ return;
+ }
+ }
+#if defined(CAN2_BASE) && (CAN_NUM > 1)
+ else if ((CANName) can == CAN_2) {
+ switch (type) {
+ case IRQ_RX:
+ ier = CAN_IT_FMP0;
+ irq_n = CAN2_IRQ_RX_IRQN;
+ vector = (uint32_t)&CAN2_IRQ_RX_VECT;
+ break;
+ case IRQ_TX:
+ ier = CAN_IT_TME;
+ irq_n = CAN2_IRQ_TX_IRQN;
+ vector = (uint32_t)&CAN2_IRQ_TX_VECT;
+ break;
+ case IRQ_ERROR:
+ ier = CAN_IT_ERR;
+ irq_n = CAN2_IRQ_ERROR_IRQN;
+ vector = (uint32_t)&CAN2_IRQ_ERROR_VECT;
+ break;
+ case IRQ_PASSIVE:
+ ier = CAN_IT_EPV;
+ irq_n = CAN2_IRQ_PASSIVE_IRQN;
+ vector = (uint32_t)&CAN2_IRQ_PASSIVE_VECT;
+ break;
+ case IRQ_BUS:
+ ier = CAN_IT_BOF;
+ irq_n = CAN2_IRQ_BUS_IRQN;
+ vector = (uint32_t)&CAN2_IRQ_BUS_VECT;
+ break;
+ default:
+ return;
+ }
+ }
+#endif
+#if defined(CAN3_BASE) && (CAN_NUM > 2)
+ else if ((CANName) can == CAN_3) {
+ switch (type) {
+ case IRQ_RX:
+ ier = CAN_IT_FMP0;
+ irq_n = CAN3_IRQ_RX_IRQN;
+ vector = (uint32_t)&CAN3_IRQ_RX_VECT;
+ break;
+ case IRQ_TX:
+ ier = CAN_IT_TME;
+ irq_n = CAN3_IRQ_TX_IRQN;
+ vector = (uint32_t)&CAN3_IRQ_TX_VECT;
+ break;
+ case IRQ_ERROR:
+ ier = CAN_IT_ERR;
+ irq_n = CAN3_IRQ_ERROR_IRQN;
+ vector = (uint32_t)&CAN3_IRQ_ERROR_VECT;
+ break;
+ case IRQ_PASSIVE:
+ ier = CAN_IT_EPV;
+ irq_n = CAN3_IRQ_PASSIVE_IRQN;
+ vector = (uint32_t)&CAN3_IRQ_PASSIVE_VECT;
+ break;
+ case IRQ_BUS:
+ ier = CAN_IT_BOF;
+ irq_n = CAN3_IRQ_BUS_IRQN;
+ vector = (uint32_t)&CAN3_IRQ_BUS_VECT;
+ break;
+ default:
+ return;
+ }
+ }
+#endif
+ else {
+ return;
+ }
+
+ if (enable) {
+ can->IER |= ier;
+ } else {
+ can->IER &= ~ier;
+ }
+
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+}
+
+#endif // DEVICE_CAN
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/gpio_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/gpio_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,164 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "pin_device.h"
+
+extern const uint32_t ll_pin_defines[16];
+
+// Enable GPIO clock and return GPIO base address
+GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx)
+{
+ uint32_t gpio_add = 0;
+ switch (port_idx) {
+ case PortA:
+ gpio_add = GPIOA_BASE;
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ break;
+ case PortB:
+ gpio_add = GPIOB_BASE;
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ break;
+#if defined(GPIOC_BASE)
+ case PortC:
+ gpio_add = GPIOC_BASE;
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ break;
+#endif
+#if defined GPIOD_BASE
+ case PortD:
+ gpio_add = GPIOD_BASE;
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ break;
+#endif
+#if defined GPIOE_BASE
+ case PortE:
+ gpio_add = GPIOE_BASE;
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ break;
+#endif
+#if defined GPIOF_BASE
+ case PortF:
+ gpio_add = GPIOF_BASE;
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+ break;
+#endif
+#if defined GPIOG_BASE
+ case PortG:
+#if defined TARGET_STM32L4
+ __HAL_RCC_PWR_CLK_ENABLE();
+ HAL_PWREx_EnableVddIO2();
+#endif
+ gpio_add = GPIOG_BASE;
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ break;
+#endif
+#if defined GPIOH_BASE
+ case PortH:
+ gpio_add = GPIOH_BASE;
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ break;
+#endif
+#if defined GPIOI_BASE
+ case PortI:
+ gpio_add = GPIOI_BASE;
+ __HAL_RCC_GPIOI_CLK_ENABLE();
+ break;
+#endif
+#if defined GPIOJ_BASE
+ case PortJ:
+ gpio_add = GPIOJ_BASE;
+ __HAL_RCC_GPIOJ_CLK_ENABLE();
+ break;
+#endif
+#if defined GPIOK_BASE
+ case PortK:
+ gpio_add = GPIOK_BASE;
+ __HAL_RCC_GPIOK_CLK_ENABLE();
+ break;
+#endif
+ default:
+ error("Pinmap error: wrong port number.");
+ break;
+ }
+ return (GPIO_TypeDef *) gpio_add;
+}
+
+uint32_t gpio_set(PinName pin)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+
+ pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+ return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
+}
+
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+ obj->pin = pin;
+ if (pin == (PinName)NC) {
+ return;
+ }
+
+ uint32_t port_index = STM_PORT(pin);
+
+ // Enable GPIO clock
+ GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
+
+ // Fill GPIO object structure for future use
+ obj->mask = gpio_set(pin);
+ obj->gpio = gpio;
+ obj->ll_pin = ll_pin_defines[STM_PIN(obj->pin)];
+ obj->reg_in = &gpio->IDR;
+ obj->reg_set = &gpio->BSRR;
+#ifdef GPIO_IP_WITHOUT_BRR
+ obj->reg_clr = &gpio->BSRR;
+#else
+ obj->reg_clr = &gpio->BRR;
+#endif
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ pin_mode(obj->pin, mode);
+}
+
+inline void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ if (direction == PIN_INPUT) {
+ LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_INPUT);
+ } else {
+ LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_OUTPUT);
+ }
+}
+
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/gpio_irq_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/gpio_irq_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,334 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "gpio_irq_device.h"
+
+#define EDGE_NONE (0)
+#define EDGE_RISE (1)
+#define EDGE_FALL (2)
+#define EDGE_BOTH (3)
+
+
+typedef struct gpio_channel {
+ uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts
+ uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance
+ GPIO_TypeDef *channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
+ uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group
+} gpio_channel_t;
+
+static gpio_irq_handler irq_handler;
+
+static gpio_channel_t channels[CHANNEL_NUM] = {
+#ifdef EXTI_IRQ0_NUM_LINES
+ {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ1_NUM_LINES
+ {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ2_NUM_LINES
+ {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ3_NUM_LINES
+ {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ4_NUM_LINES
+ {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ5_NUM_LINES
+ {.pin_mask = 0},
+#endif
+#ifdef EXTI_IRQ6_NUM_LINES
+ {.pin_mask = 0}
+#endif
+};
+
+static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
+{
+ gpio_channel_t *gpio_channel = &channels[irq_index];
+ uint32_t gpio_idx;
+
+ for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
+ uint32_t current_mask = (1 << gpio_idx);
+
+ if (gpio_channel->pin_mask & current_mask) {
+ // Retrieve the gpio and pin that generate the irq
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
+ uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
+
+ // Clear interrupt flag
+ if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
+ __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
+
+ if (gpio_channel->channel_ids[gpio_idx] == 0) {
+ continue;
+ }
+
+ // Trying to discern which edge caused the IRQ
+ gpio_irq_event event = IRQ_NONE;
+ if (LL_EXTI_IsEnabledFallingTrig_0_31(pin) && !LL_EXTI_IsEnabledRisingTrig_0_31(pin)) {
+ // Only the fall handler is active, so this must be a falling edge
+ event = IRQ_FALL;
+ } else if (LL_EXTI_IsEnabledRisingTrig_0_31(pin) && !LL_EXTI_IsEnabledFallingTrig_0_31(pin)) {
+ // Only the rise handler is active, so this must be a rising edge
+ event = IRQ_RISE;
+ } else {
+ // Ambiguous as to which edge caused the IRQ
+ //
+ // The state of the pin could/should indicate which edge
+ // has occurred but this can go wrong if the IRQ caused a
+ // transition from a low power mode. In some circumstances
+ // only the trailing edge callback will be called.
+ if ((gpio->IDR & pin) == 0) {
+ event = IRQ_FALL;
+ } else {
+ event = IRQ_RISE;
+ }
+ }
+
+ irq_handler(gpio_channel->channel_ids[gpio_idx], event);
+
+ return;
+ }
+ }
+ }
+ error("Unexpected Spurious interrupt, index %d\r\n", irq_index);
+}
+
+
+#ifdef EXTI_IRQ0_NUM_LINES
+// EXTI line 0
+static void gpio_irq0(void)
+{
+ handle_interrupt_in(0, EXTI_IRQ0_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ1_NUM_LINES
+// EXTI line 1
+static void gpio_irq1(void)
+{
+ handle_interrupt_in(1, EXTI_IRQ1_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ2_NUM_LINES
+// EXTI line 2
+static void gpio_irq2(void)
+{
+ handle_interrupt_in(2, EXTI_IRQ2_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ3_NUM_LINES
+// EXTI line 3
+static void gpio_irq3(void)
+{
+ handle_interrupt_in(3, EXTI_IRQ3_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ4_NUM_LINES
+// EXTI line 4
+static void gpio_irq4(void)
+{
+ handle_interrupt_in(4, EXTI_IRQ4_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ5_NUM_LINES
+// EXTI lines 5 to 9
+static void gpio_irq5(void)
+{
+ handle_interrupt_in(5, EXTI_IRQ5_NUM_LINES);
+}
+#endif
+#ifdef EXTI_IRQ6_NUM_LINES
+// EXTI lines 10 to 15
+static void gpio_irq6(void)
+{
+ handle_interrupt_in(6, EXTI_IRQ6_NUM_LINES);
+}
+#endif
+
+extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx);
+extern void pin_function_gpiomode(PinName pin, uint32_t gpiomode);
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+ uint32_t vector = 0;
+ uint32_t irq_index;
+ gpio_channel_t *gpio_channel;
+ uint32_t gpio_idx;
+
+ if (pin == NC) {
+ return -1;
+ }
+
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+ irq_index = pin_lines_desc[pin_index].irq_index;
+
+ switch (irq_index) {
+#ifdef EXTI_IRQ0_NUM_LINES
+ case 0:
+ vector = (uint32_t)&gpio_irq0;
+ break;
+#endif
+#ifdef EXTI_IRQ1_NUM_LINES
+ case 1:
+ vector = (uint32_t)&gpio_irq1;
+ break;
+#endif
+#ifdef EXTI_IRQ2_NUM_LINES
+ case 2:
+ vector = (uint32_t)&gpio_irq2;
+ break;
+#endif
+#ifdef EXTI_IRQ3_NUM_LINES
+ case 3:
+ vector = (uint32_t)&gpio_irq3;
+ break;
+#endif
+#ifdef EXTI_IRQ4_NUM_LINES
+ case 4:
+ vector = (uint32_t)&gpio_irq4;
+ break;
+#endif
+#ifdef EXTI_IRQ5_NUM_LINES
+ case 5:
+ vector = (uint32_t)&gpio_irq5;
+ break;
+#endif
+#ifdef EXTI_IRQ6_NUM_LINES
+ case 6:
+ vector = (uint32_t)&gpio_irq6;
+ break;
+#endif
+ default:
+ error("InterruptIn error: pin not supported.\n");
+ return -1;
+ }
+
+ // Enable GPIO clock
+ GPIO_TypeDef *gpio_add = Set_GPIO_Clock(port_index);
+
+ // Save informations for future use
+ obj->irq_n = pin_lines_desc[pin_index].irq_n;
+ obj->irq_index = pin_lines_desc[pin_index].irq_index;
+ obj->event = EDGE_NONE;
+ obj->pin = pin;
+
+ gpio_channel = &channels[irq_index];
+ gpio_idx = pin_lines_desc[pin_index].gpio_idx;
+ gpio_channel->pin_mask |= (1 << gpio_idx);
+ gpio_channel->channel_ids[gpio_idx] = id;
+ gpio_channel->channel_gpio[gpio_idx] = gpio_add;
+ gpio_channel->channel_pin[gpio_idx] = pin_index;
+
+ irq_handler = handler;
+
+ // Enable EXTI interrupt
+ NVIC_SetVector(obj->irq_n, vector);
+ gpio_irq_enable(obj);
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ uint32_t gpio_idx = pin_lines_desc[STM_PIN(obj->pin)].gpio_idx;
+ gpio_channel_t *gpio_channel = &channels[obj->irq_index];
+
+ gpio_irq_disable(obj);
+ gpio_channel->pin_mask &= ~(1 << gpio_idx);
+ gpio_channel->channel_ids[gpio_idx] = 0;
+ gpio_channel->channel_gpio[gpio_idx] = 0;
+ gpio_channel->channel_pin[gpio_idx] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ /* Enable / Disable Edge triggered interrupt and store event */
+ if (event == IRQ_RISE) {
+ if (enable) {
+ LL_EXTI_EnableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+ obj->event |= IRQ_RISE;
+ } else {
+ LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+ obj->event &= ~IRQ_RISE;
+ }
+ }
+ if (event == IRQ_FALL) {
+ if (enable) {
+ LL_EXTI_EnableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+ obj->event |= IRQ_FALL;
+ } else {
+ LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+ obj->event &= ~IRQ_FALL;
+ }
+ }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+ uint32_t temp = 0;
+ uint32_t port_index = STM_PORT(obj->pin);
+ uint32_t pin_index = STM_PIN(obj->pin);
+
+ /* Select Source */
+ temp = SYSCFG->EXTICR[pin_index >> 2];
+ CLEAR_BIT(temp, (0x0FU) << (4U * (pin_index & 0x03U)));
+ SET_BIT(temp, port_index << (4U * (pin_index & 0x03U)));
+ SYSCFG->EXTICR[pin_index >> 2] = temp;
+
+ LL_EXTI_EnableIT_0_31(1 << pin_index);
+
+ /* Restore previous edge interrupt configuration if applicable */
+ if (obj->event & IRQ_RISE) {
+ LL_EXTI_EnableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+ }
+ if (obj->event & IRQ_FALL) {
+ LL_EXTI_EnableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+ }
+
+ NVIC_EnableIRQ(obj->irq_n);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+ /* Clear EXTI line configuration */
+ LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+ LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+ LL_EXTI_DisableIT_0_31(1 << STM_PIN(obj->pin));
+ NVIC_DisableIRQ(obj->irq_n);
+ NVIC_ClearPendingIRQ(obj->irq_n);
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/gpio_object.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/gpio_object.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Note: reg_clr might actually be same as reg_set.
+ * Depends on family whether BRR is available on top of BSRR
+ * if BRR does not exist, family shall define GPIO_IP_WITHOUT_BRR
+ */
+typedef struct {
+ uint32_t mask;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ PinName pin;
+ GPIO_TypeDef *gpio;
+ uint32_t ll_pin;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ if (value) {
+ *obj->reg_set = obj->mask;
+ } else {
+#ifdef GPIO_IP_WITHOUT_BRR
+ *obj->reg_clr = obj->mask << 16;
+#else
+ *obj->reg_clr = obj->mask;
+#endif
+ }
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+ return obj->pin != (PinName)NC;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/hal_tick_overrides.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/hal_tick_overrides.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/us_ticker_api.h"
+#include "us_ticker_data.h"
+
+// This variable is set to 1 at the of mbed_sdk_init function.
+// The ticker_read_us function must not be called until the mbed_sdk_init is terminated.
+extern int mbed_sdk_inited;
+
+// Defined in us_ticker.c
+void init_16bit_timer(void);
+void init_32bit_timer(void);
+
+#if TIM_MST_BIT_WIDTH == 16
+// Variables also reset in us_ticker_init()
+uint32_t prev_time = 0;
+uint32_t elapsed_time = 0;
+#endif
+
+// Overwrite default HAL functions defined as "weak"
+
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+#if TIM_MST_BIT_WIDTH == 16
+ init_16bit_timer();
+#else
+ init_32bit_timer();
+#endif
+ return HAL_OK;
+}
+
+uint32_t HAL_GetTick()
+{
+#if TIM_MST_BIT_WIDTH == 16
+ uint32_t new_time;
+ if (mbed_sdk_inited) {
+ // Apply the latest time recorded just before the sdk is inited
+ new_time = ticker_read_us(get_us_ticker_data()) + prev_time;
+ prev_time = 0; // Use this time only once
+ return (new_time / 1000);
+ }
+ else {
+ new_time = us_ticker_read();
+ elapsed_time += (new_time - prev_time) & 0xFFFF; // Only use the lower 16 bits
+ prev_time = new_time;
+ return (elapsed_time / 1000);
+ }
+#else // 32-bit timer
+ if (mbed_sdk_inited) {
+ return (ticker_read_us(get_us_ticker_data()) / 1000);
+ }
+ else {
+ return (us_ticker_read() / 1000);
+ }
+#endif
+}
+
+void HAL_SuspendTick(void)
+{
+ // Do nothing
+}
+
+void HAL_ResumeTick(void)
+{
+ // Do nothing
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/i2c_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/i2c_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,1185 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+
+#include "mbed_assert.h"
+#include "i2c_api.h"
+#include "platform/mbed_wait_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "i2c_device.h" // family specific defines
+
+#ifndef DEBUG_STDIO
+# define DEBUG_STDIO 0
+#endif
+
+#if DEBUG_STDIO
+# include <stdio.h>
+# define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
+#else
+# define DEBUG_PRINTF(...) {}
+#endif
+
+#if DEVICE_I2C_ASYNCH
+#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
+#else
+#define I2C_S(obj) (struct i2c_s *) (obj)
+#endif
+
+/* Family specific description for I2C */
+#define I2C_NUM (5)
+static I2C_HandleTypeDef *i2c_handles[I2C_NUM];
+
+/* Timeout values are based on core clock and I2C clock.
+ The BYTE_TIMEOUT is computed as twice the number of cycles it would
+ take to send 10 bits over I2C. Most Flags should take less than that.
+ This is for immediate FLAG or ACK check.
+*/
+#define BYTE_TIMEOUT ((SystemCoreClock / obj_s->hz) * 2 * 10)
+/* Timeout values based on I2C clock.
+ The BYTE_TIMEOUT_US is computed as 3x the time in us it would
+ take to send 10 bits over I2C. Most Flags should take less than that.
+ This is for complete transfers check.
+*/
+#define BYTE_TIMEOUT_US ((SystemCoreClock / obj_s->hz) * 3 * 10)
+/* Timeout values for flags and events waiting loops. These timeouts are
+ not based on accurate values, they just guarantee that the application will
+ not remain stuck if the I2C communication is corrupted.
+*/
+#define FLAG_TIMEOUT ((int)0x1000)
+
+/* GENERIC INIT and HELPERS FUNCTIONS */
+
+#if defined(I2C1_BASE)
+static void i2c1_irq(void)
+{
+ I2C_HandleTypeDef *handle = i2c_handles[0];
+ HAL_I2C_EV_IRQHandler(handle);
+ HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+#if defined(I2C2_BASE)
+static void i2c2_irq(void)
+{
+ I2C_HandleTypeDef *handle = i2c_handles[1];
+ HAL_I2C_EV_IRQHandler(handle);
+ HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+#if defined(I2C3_BASE)
+static void i2c3_irq(void)
+{
+ I2C_HandleTypeDef *handle = i2c_handles[2];
+ HAL_I2C_EV_IRQHandler(handle);
+ HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+#if defined(I2C4_BASE)
+static void i2c4_irq(void)
+{
+ I2C_HandleTypeDef *handle = i2c_handles[3];
+ HAL_I2C_EV_IRQHandler(handle);
+ HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+#if defined(FMPI2C1_BASE)
+static void i2c5_irq(void)
+{
+ I2C_HandleTypeDef *handle = i2c_handles[4];
+ HAL_I2C_EV_IRQHandler(handle);
+ HAL_I2C_ER_IRQHandler(handle);
+}
+#endif
+
+void i2c_ev_err_enable(i2c_t *obj, uint32_t handler)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
+ IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
+ /* default prio in master case is set to 2 */
+ uint32_t prio = 2;
+
+ /* Set up ITs using IRQ and handler tables */
+ NVIC_SetVector(irq_event_n, handler);
+ NVIC_SetVector(irq_error_n, handler);
+
+#if DEVICE_I2CSLAVE
+ /* Set higher priority to slave device than master.
+ * In case a device makes use of both master and slave, the
+ * slave needs higher responsiveness.
+ */
+ if (obj_s->slave) {
+ prio = 1;
+ }
+#endif
+
+ NVIC_SetPriority(irq_event_n, prio);
+ NVIC_SetPriority(irq_error_n, prio);
+ NVIC_EnableIRQ(irq_event_n);
+ NVIC_EnableIRQ(irq_error_n);
+}
+
+void i2c_ev_err_disable(i2c_t *obj)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
+ IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
+
+ HAL_NVIC_DisableIRQ(irq_event_n);
+ HAL_NVIC_DisableIRQ(irq_error_n);
+}
+
+uint32_t i2c_get_irq_handler(i2c_t *obj)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ uint32_t handler = 0;
+
+ switch (obj_s->index) {
+#if defined(I2C1_BASE)
+ case 0:
+ handler = (uint32_t)&i2c1_irq;
+ break;
+#endif
+#if defined(I2C2_BASE)
+ case 1:
+ handler = (uint32_t)&i2c2_irq;
+ break;
+#endif
+#if defined(I2C3_BASE)
+ case 2:
+ handler = (uint32_t)&i2c3_irq;
+ break;
+#endif
+#if defined(I2C4_BASE)
+ case 3:
+ handler = (uint32_t)&i2c4_irq;
+ break;
+#endif
+#if defined(FMPI2C1_BASE)
+ case 4:
+ handler = (uint32_t)&i2c5_irq;
+ break;
+#endif
+ }
+
+ i2c_handles[obj_s->index] = handle;
+ return handler;
+}
+
+void i2c_hw_reset(i2c_t *obj)
+{
+ int timeout;
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
+
+ // wait before reset
+ timeout = BYTE_TIMEOUT;
+ while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
+#if defined I2C1_BASE
+ if (obj_s->i2c == I2C_1) {
+ __HAL_RCC_I2C1_FORCE_RESET();
+ __HAL_RCC_I2C1_RELEASE_RESET();
+ }
+#endif
+#if defined I2C2_BASE
+ if (obj_s->i2c == I2C_2) {
+ __HAL_RCC_I2C2_FORCE_RESET();
+ __HAL_RCC_I2C2_RELEASE_RESET();
+ }
+#endif
+#if defined I2C3_BASE
+ if (obj_s->i2c == I2C_3) {
+ __HAL_RCC_I2C3_FORCE_RESET();
+ __HAL_RCC_I2C3_RELEASE_RESET();
+ }
+#endif
+#if defined I2C4_BASE
+ if (obj_s->i2c == I2C_4) {
+ __HAL_RCC_I2C4_FORCE_RESET();
+ __HAL_RCC_I2C4_RELEASE_RESET();
+ }
+#endif
+#if defined FMPI2C1_BASE
+ if (obj_s->i2c == FMPI2C_1) {
+ __HAL_RCC_FMPI2C1_FORCE_RESET();
+ __HAL_RCC_FMPI2C1_RELEASE_RESET();
+ }
+#endif
+}
+
+void i2c_sw_reset(i2c_t *obj)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ /* SW reset procedure:
+ * PE must be kept low during at least 3 APB clock cycles
+ * in order to perform the software reset.
+ * This is ensured by writing the following software sequence:
+ * - Write PE=0
+ * - Check PE=0
+ * - Write PE=1.
+ */
+ handle->Instance->CR1 &= ~I2C_CR1_PE;
+ while (handle->Instance->CR1 & I2C_CR1_PE);
+ handle->Instance->CR1 |= I2C_CR1_PE;
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+
+ struct i2c_s *obj_s = I2C_S(obj);
+
+ // Determine the I2C to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj_s->sda = sda;
+ obj_s->scl = scl;
+
+ obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+ MBED_ASSERT(obj_s->i2c != (I2CName)NC);
+
+#if defined I2C1_BASE
+ // Enable I2C1 clock and pinout if not done
+ if (obj_s->i2c == I2C_1) {
+ obj_s->index = 0;
+ __HAL_RCC_I2C1_CLK_ENABLE();
+ // Configure I2C pins
+ obj_s->event_i2cIRQ = I2C1_EV_IRQn;
+ obj_s->error_i2cIRQ = I2C1_ER_IRQn;
+ }
+#endif
+#if defined I2C2_BASE
+ // Enable I2C2 clock and pinout if not done
+ if (obj_s->i2c == I2C_2) {
+ obj_s->index = 1;
+ __HAL_RCC_I2C2_CLK_ENABLE();
+ obj_s->event_i2cIRQ = I2C2_EV_IRQn;
+ obj_s->error_i2cIRQ = I2C2_ER_IRQn;
+ }
+#endif
+#if defined I2C3_BASE
+ // Enable I2C3 clock and pinout if not done
+ if (obj_s->i2c == I2C_3) {
+ obj_s->index = 2;
+ __HAL_RCC_I2C3_CLK_ENABLE();
+ obj_s->event_i2cIRQ = I2C3_EV_IRQn;
+ obj_s->error_i2cIRQ = I2C3_ER_IRQn;
+ }
+#endif
+#if defined I2C4_BASE
+ // Enable I2C3 clock and pinout if not done
+ if (obj_s->i2c == I2C_4) {
+ obj_s->index = 3;
+ __HAL_RCC_I2C4_CLK_ENABLE();
+ obj_s->event_i2cIRQ = I2C4_EV_IRQn;
+ obj_s->error_i2cIRQ = I2C4_ER_IRQn;
+ }
+#endif
+#if defined FMPI2C1_BASE
+ // Enable I2C3 clock and pinout if not done
+ if (obj_s->i2c == FMPI2C_1) {
+ obj_s->index = 4;
+ __HAL_RCC_FMPI2C1_CLK_ENABLE();
+ obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
+ obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
+ }
+#endif
+
+ // Configure I2C pins
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(sda, OpenDrainNoPull);
+ pin_mode(scl, OpenDrainNoPull);
+
+ // I2C configuration
+ // Default hz value used for timeout computation
+ if (!obj_s->hz) {
+ obj_s->hz = 100000; // 100 kHz per default
+ }
+
+ // Reset to clear pending flags if any
+ i2c_hw_reset(obj);
+ i2c_frequency(obj, obj_s->hz);
+
+#if DEVICE_I2CSLAVE
+ // I2C master by default
+ obj_s->slave = 0;
+ obj_s->pending_slave_tx_master_rx = 0;
+ obj_s->pending_slave_rx_maxter_tx = 0;
+#endif
+
+ // I2C Xfer operation init
+ obj_s->event = 0;
+ obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
+#ifdef I2C_IP_VERSION_V2
+ obj_s->pending_start = 0;
+#endif
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+ int timeout;
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ // wait before init
+ timeout = BYTE_TIMEOUT;
+ while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
+
+#ifdef I2C_IP_VERSION_V1
+ handle->Init.ClockSpeed = hz;
+ handle->Init.DutyCycle = I2C_DUTYCYCLE_2;
+#endif
+#ifdef I2C_IP_VERSION_V2
+ /* Only predefined timing for below frequencies are supported */
+ MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
+ handle->Init.Timing = get_i2c_timing(hz);
+
+ // Enable the Fast Mode Plus capability
+ if (hz == 1000000) {
+#if defined(I2C1_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C1)
+ if (obj_s->i2c == I2C_1) {
+ HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
+ }
+#endif
+#if defined(I2C2_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C2)
+ if (obj_s->i2c == I2C_2) {
+ HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C2);
+ }
+#endif
+#if defined(I2C3_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C3)
+ if (obj_s->i2c == I2C_3) {
+ HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3);
+ }
+#endif
+#if defined(I2C4_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C4)
+ if (obj_s->i2c == I2C_4) {
+ HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C4);
+ }
+#endif
+ }
+#endif //I2C_IP_VERSION_V2
+
+ /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
+#if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)
+ if (obj_s->i2c == I2C_1) {
+ __HAL_RCC_I2C1_CONFIG(I2CAPI_I2C1_CLKSRC);
+ }
+#endif
+#if defined(I2C2_BASE) && defined(__HAL_RCC_I2C2_CONFIG)
+ if (obj_s->i2c == I2C_2) {
+ __HAL_RCC_I2C2_CONFIG(I2CAPI_I2C2_CLKSRC);
+ }
+#endif
+#if defined(I2C3_BASE) && defined(__HAL_RCC_I2C3_CONFIG)
+ if (obj_s->i2c == I2C_3) {
+ __HAL_RCC_I2C3_CONFIG(I2CAPI_I2C3_CLKSRC);
+ }
+#endif
+#if defined(I2C4_BASE) && defined(__HAL_RCC_I2C4_CONFIG)
+ if (obj_s->i2c == I2C_4) {
+ __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
+ }
+#endif
+
+#ifdef I2C_ANALOGFILTER_ENABLE
+ /* Enable the Analog I2C Filter */
+ HAL_I2CEx_ConfigAnalogFilter(handle, I2C_ANALOGFILTER_ENABLE);
+#endif
+
+ // I2C configuration
+ handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+ handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+ handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+ handle->Init.OwnAddress1 = 0;
+ handle->Init.OwnAddress2 = 0;
+ HAL_I2C_Init(handle);
+
+ /* store frequency for timeout computation */
+ obj_s->hz = hz;
+}
+
+i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c)
+{
+ /* Aim of the function is to get i2c_s pointer using hi2c pointer */
+ /* Highly inspired from magical linux kernel's "container_of" */
+ /* (which was not directly used since not compatible with IAR toolchain) */
+ struct i2c_s *obj_s;
+ i2c_t *obj;
+
+ obj_s = (struct i2c_s *)((char *)hi2c - offsetof(struct i2c_s, handle));
+ obj = (i2c_t *)((char *)obj_s - offsetof(i2c_t, i2c));
+
+ return (obj);
+}
+
+void i2c_reset(i2c_t *obj)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ /* As recommended in i2c_api.h, mainly send stop */
+ i2c_stop(obj);
+ /* then re-init */
+ i2c_init(obj, obj_s->sda, obj_s->scl);
+}
+
+/*
+ * UNITARY APIS.
+ * For very basic operations, direct registers access is needed
+ * There are 2 different IPs version that need to be supported
+ */
+#ifdef I2C_IP_VERSION_V1
+int i2c_start(i2c_t *obj)
+{
+
+ int timeout;
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ // Clear Acknowledge failure flag
+ __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
+
+ // Wait the STOP condition has been previously correctly sent
+ // This timeout can be avoid in some specific cases by simply clearing the STOP bit
+ timeout = FLAG_TIMEOUT;
+ while ((handle->Instance->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) {
+ if ((timeout--) == 0) {
+ return 1;
+ }
+ }
+
+ // Generate the START condition
+ handle->Instance->CR1 |= I2C_CR1_START;
+
+ // Wait the START condition has been correctly sent
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
+ if ((timeout--) == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+int i2c_stop(i2c_t *obj)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
+
+ // Generate the STOP condition
+ i2c->CR1 |= I2C_CR1_STOP;
+
+ /* In case of mixed usage of the APIs (unitary + SYNC)
+ * re-init HAL state
+ */
+ if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
+ i2c_init(obj, obj_s->sda, obj_s->scl);
+ }
+
+ return 0;
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+
+ int timeout;
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ if (last) {
+ // Don't acknowledge the last byte
+ handle->Instance->CR1 &= ~I2C_CR1_ACK;
+ } else {
+ // Acknowledge the byte
+ handle->Instance->CR1 |= I2C_CR1_ACK;
+ }
+
+ // Wait until the byte is received
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
+ if ((timeout--) == 0) {
+ return -1;
+ }
+ }
+
+ return (int)handle->Instance->DR;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+
+ int timeout;
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ handle->Instance->DR = (uint8_t)data;
+
+ // Wait until the byte (might be the address) is transmitted
+ timeout = FLAG_TIMEOUT;
+ while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
+ (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
+ (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) {
+ if ((timeout--) == 0) {
+ return 2;
+ }
+ }
+
+ if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET) {
+ __HAL_I2C_CLEAR_ADDRFLAG(handle);
+ }
+
+ return 1;
+}
+#endif //I2C_IP_VERSION_V1
+#ifdef I2C_IP_VERSION_V2
+
+int i2c_start(i2c_t *obj)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ /* This I2C IP doesn't */
+ obj_s->pending_start = 1;
+ return 0;
+}
+
+int i2c_stop(i2c_t *obj)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ int timeout = FLAG_TIMEOUT;
+#if DEVICE_I2CSLAVE
+ if (obj_s->slave) {
+ /* re-init slave when stop is requested */
+ i2c_init(obj, obj_s->sda, obj_s->scl);
+ return 0;
+ }
+#endif
+ // Disable reload mode
+ handle->Instance->CR2 &= (uint32_t)~I2C_CR2_RELOAD;
+ // Generate the STOP condition
+ handle->Instance->CR2 |= I2C_CR2_STOP;
+
+ timeout = FLAG_TIMEOUT;
+ while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_STOPF)) {
+ if ((timeout--) == 0) {
+ return I2C_ERROR_BUS_BUSY;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_STOPF);
+
+ /* Erase slave address, this wiil be used as a marker
+ * to know when we need to prepare next start */
+ handle->Instance->CR2 &= ~I2C_CR2_SADD;
+
+ /*
+ * V2 IP is meant for automatic STOP, not user STOP
+ * SW reset the IP state machine before next transaction
+ */
+ i2c_sw_reset(obj);
+
+ /* In case of mixed usage of the APIs (unitary + SYNC)
+ * re-init HAL state */
+ if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
+ i2c_init(obj, obj_s->sda, obj_s->scl);
+ }
+
+ return 0;
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ int timeout = FLAG_TIMEOUT;
+ uint32_t tmpreg = handle->Instance->CR2;
+ char data;
+#if DEVICE_I2CSLAVE
+ if (obj_s->slave) {
+ return i2c_slave_read(obj, &data, 1);
+ }
+#endif
+ /* Then send data when there's room in the TX fifo */
+ if ((tmpreg & I2C_CR2_RELOAD) != 0) {
+ while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
+ if ((timeout--) == 0) {
+ DEBUG_PRINTF("timeout in byte_read\r\n");
+ return -1;
+ }
+ }
+ }
+
+ /* Enable reload mode as we don't know how many bytes will be sent */
+ /* and set transfer size to 1 */
+ tmpreg |= I2C_CR2_RELOAD | (I2C_CR2_NBYTES & (1 << 16));
+ /* Set the prepared configuration */
+ handle->Instance->CR2 = tmpreg;
+
+ timeout = FLAG_TIMEOUT;
+ while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE)) {
+ if ((timeout--) == 0) {
+ return -1;
+ }
+ }
+
+ /* Then Get Byte */
+ data = handle->Instance->RXDR;
+
+ if (last) {
+ /* Disable Address Acknowledge */
+ handle->Instance->CR2 |= I2C_CR2_NACK;
+ }
+
+ return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ int timeout = FLAG_TIMEOUT;
+ uint32_t tmpreg = handle->Instance->CR2;
+#if DEVICE_I2CSLAVE
+ if (obj_s->slave) {
+ return i2c_slave_write(obj, (char *) &data, 1);
+ }
+#endif
+ if (obj_s->pending_start) {
+ obj_s->pending_start = 0;
+ //* First byte after the start is the address */
+ tmpreg |= (uint32_t)((uint32_t)data & I2C_CR2_SADD);
+ if (data & 0x01) {
+ tmpreg |= I2C_CR2_START | I2C_CR2_RD_WRN;
+ } else {
+ tmpreg |= I2C_CR2_START;
+ tmpreg &= ~I2C_CR2_RD_WRN;
+ }
+ /* Disable reload first to use it later */
+ tmpreg &= ~I2C_CR2_RELOAD;
+ /* Disable Autoend */
+ tmpreg &= ~I2C_CR2_AUTOEND;
+ /* Do not set any transfer size for now */
+ tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
+ /* Set the prepared configuration */
+ handle->Instance->CR2 = tmpreg;
+ } else {
+ /* Set the prepared configuration */
+ tmpreg = handle->Instance->CR2;
+
+ /* Then send data when there's room in the TX fifo */
+ if ((tmpreg & I2C_CR2_RELOAD) != 0) {
+ while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
+ if ((timeout--) == 0) {
+ DEBUG_PRINTF("timeout in byte_write\r\n");
+ return 2;
+ }
+ }
+ }
+ /* Enable reload mode as we don't know how many bytes will eb sent */
+ tmpreg |= I2C_CR2_RELOAD;
+ /* Set transfer size to 1 */
+ tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
+ /* Set the prepared configuration */
+ handle->Instance->CR2 = tmpreg;
+ /* Prepare next write */
+ timeout = FLAG_TIMEOUT;
+ while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE)) {
+ if ((timeout--) == 0) {
+ return 2;
+ }
+ }
+ /* Write byte */
+ handle->Instance->TXDR = data;
+ }
+
+ return 1;
+}
+#endif //I2C_IP_VERSION_V2
+
+/*
+ * SYNC APIS
+ */
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ int count = I2C_ERROR_BUS_BUSY, ret = 0;
+ uint32_t timeout = 0;
+
+ // Trick to remove compiler warning "left and right operands are identical" in some cases
+ uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+ uint32_t op2 = I2C_LAST_FRAME;
+ if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
+ if (stop) {
+ obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
+ } else {
+ obj_s->XferOperation = I2C_FIRST_FRAME;
+ }
+ } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
+ (obj_s->XferOperation == I2C_NEXT_FRAME)) {
+ if (stop) {
+ obj_s->XferOperation = I2C_LAST_FRAME;
+ } else {
+ obj_s->XferOperation = I2C_NEXT_FRAME;
+ }
+ }
+
+ obj_s->event = 0;
+
+ /* Activate default IRQ handlers for sync mode
+ * which would be overwritten in async mode
+ */
+ i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
+
+ ret = HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
+
+ if (ret == HAL_OK) {
+ timeout = BYTE_TIMEOUT_US * (length + 1);
+ /* transfer started : wait completion or timeout */
+ while (!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
+ wait_us(1);
+ }
+
+ i2c_ev_err_disable(obj);
+
+ if ((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
+ DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n");
+ /* re-init IP to try and get back in a working state */
+ i2c_init(obj, obj_s->sda, obj_s->scl);
+ } else {
+ count = length;
+ }
+ } else {
+ DEBUG_PRINTF("ERROR in i2c_read:%d\r\n", ret);
+ }
+
+ return count;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ int count = I2C_ERROR_BUS_BUSY, ret = 0;
+ uint32_t timeout = 0;
+
+ // Trick to remove compiler warning "left and right operands are identical" in some cases
+ uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+ uint32_t op2 = I2C_LAST_FRAME;
+ if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
+ if (stop) {
+ obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
+ } else {
+ obj_s->XferOperation = I2C_FIRST_FRAME;
+ }
+ } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
+ (obj_s->XferOperation == I2C_NEXT_FRAME)) {
+ if (stop) {
+ obj_s->XferOperation = I2C_LAST_FRAME;
+ } else {
+ obj_s->XferOperation = I2C_NEXT_FRAME;
+ }
+ }
+
+ obj_s->event = 0;
+
+ i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
+
+ ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
+
+ if (ret == HAL_OK) {
+ timeout = BYTE_TIMEOUT_US * (length + 1);
+ /* transfer started : wait completion or timeout */
+ while (!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
+ wait_us(1);
+ }
+
+ i2c_ev_err_disable(obj);
+
+ if ((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
+ DEBUG_PRINTF(" TIMEOUT or error in i2c_write\r\n");
+ /* re-init IP to try and get back in a working state */
+ i2c_init(obj, obj_s->sda, obj_s->scl);
+ } else {
+ count = length;
+ }
+ } else {
+ DEBUG_PRINTF("ERROR in i2c_read\r\n");
+ }
+
+ return count;
+}
+
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Get object ptr based on handler ptr */
+ i2c_t *obj = get_i2c_obj(hi2c);
+ struct i2c_s *obj_s = I2C_S(obj);
+
+#if DEVICE_I2C_ASYNCH
+ /* Handle potential Tx/Rx use case */
+ if ((obj->tx_buff.length) && (obj->rx_buff.length)) {
+ if (obj_s->stop) {
+ obj_s->XferOperation = I2C_LAST_FRAME;
+ } else {
+ obj_s->XferOperation = I2C_NEXT_FRAME;
+ }
+
+ HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t *)obj->rx_buff.buffer, obj->rx_buff.length, obj_s->XferOperation);
+ } else
+#endif
+ {
+ /* Set event flag */
+ obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
+ }
+}
+
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Get object ptr based on handler ptr */
+ i2c_t *obj = get_i2c_obj(hi2c);
+ struct i2c_s *obj_s = I2C_S(obj);
+
+ /* Set event flag */
+ obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
+}
+
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Get object ptr based on handler ptr */
+ i2c_t *obj = get_i2c_obj(hi2c);
+ struct i2c_s *obj_s = I2C_S(obj);
+#if DEVICE_I2CSLAVE
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ uint32_t address = 0;
+ /* Store address to handle it after reset */
+ if (obj_s->slave) {
+ address = handle->Init.OwnAddress1;
+ }
+#endif
+
+ DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index);
+
+ /* re-init IP to try and get back in a working state */
+ i2c_init(obj, obj_s->sda, obj_s->scl);
+
+#if DEVICE_I2CSLAVE
+ /* restore slave address */
+ if (address != 0) {
+ obj_s->slave = 1;
+ i2c_slave_address(obj, 0, address, 0);
+ }
+#endif
+
+ /* Keep Set event flag */
+ obj_s->event = I2C_EVENT_ERROR;
+}
+
+#if DEVICE_I2CSLAVE
+/* SLAVE API FUNCTIONS */
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ // I2C configuration
+ handle->Init.OwnAddress1 = address;
+ HAL_I2C_Init(handle);
+
+ i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
+
+ HAL_I2C_EnableListen_IT(handle);
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ if (enable_slave) {
+ obj_s->slave = 1;
+ HAL_I2C_EnableListen_IT(handle);
+ } else {
+ obj_s->slave = 0;
+ HAL_I2C_DisableListen_IT(handle);
+ }
+}
+
+// See I2CSlave.h
+#define NoData 0 // the slave has not been addressed
+#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral 2 // the master is writing to all slave
+#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
+
+
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Get object ptr based on handler ptr */
+ i2c_t *obj = get_i2c_obj(hi2c);
+ struct i2c_s *obj_s = I2C_S(obj);
+
+ /* Transfer direction in HAL is from Master point of view */
+ if (TransferDirection == I2C_DIRECTION_RECEIVE) {
+ obj_s->pending_slave_tx_master_rx = 1;
+ }
+
+ if (TransferDirection == I2C_DIRECTION_TRANSMIT) {
+ obj_s->pending_slave_rx_maxter_tx = 1;
+ }
+}
+
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+ /* Get object ptr based on handler ptr */
+ i2c_t *obj = get_i2c_obj(I2cHandle);
+ struct i2c_s *obj_s = I2C_S(obj);
+ obj_s->pending_slave_tx_master_rx = 0;
+}
+
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle)
+{
+ /* Get object ptr based on handler ptr */
+ i2c_t *obj = get_i2c_obj(I2cHandle);
+ struct i2c_s *obj_s = I2C_S(obj);
+ obj_s->pending_slave_rx_maxter_tx = 0;
+}
+
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* restart listening for master requests */
+ HAL_I2C_EnableListen_IT(hi2c);
+}
+
+int i2c_slave_receive(i2c_t *obj)
+{
+
+ struct i2c_s *obj_s = I2C_S(obj);
+ int retValue = NoData;
+
+ if (obj_s->pending_slave_rx_maxter_tx) {
+ retValue = WriteAddressed;
+ }
+
+ if (obj_s->pending_slave_tx_master_rx) {
+ retValue = ReadAddressed;
+ }
+
+ return (retValue);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ int count = 0;
+ int ret = 0;
+ uint32_t timeout = 0;
+
+ /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
+ ret = HAL_I2C_Slave_Sequential_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
+
+ if (ret == HAL_OK) {
+ timeout = BYTE_TIMEOUT_US * (length + 1);
+ while (obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) {
+ wait_us(1);
+ }
+
+ if (timeout != 0) {
+ count = length;
+ } else {
+ DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n");
+ }
+ }
+ return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+ int count = 0;
+ int ret = 0;
+ uint32_t timeout = 0;
+
+ /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
+ ret = HAL_I2C_Slave_Sequential_Transmit_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
+
+ if (ret == HAL_OK) {
+ timeout = BYTE_TIMEOUT_US * (length + 1);
+ while (obj_s->pending_slave_tx_master_rx && (--timeout != 0)) {
+ wait_us(1);
+ }
+
+ if (timeout != 0) {
+ count = length;
+ } else {
+ DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n");
+ }
+ }
+
+ return count;
+}
+#endif // DEVICE_I2CSLAVE
+
+#if DEVICE_I2C_ASYNCH
+/* ASYNCH MASTER API FUNCTIONS */
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Get object ptr based on handler ptr */
+ i2c_t *obj = get_i2c_obj(hi2c);
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ /* Disable IT. Not always done before calling macro */
+ __HAL_I2C_DISABLE_IT(handle, I2C_IT_ALL);
+ i2c_ev_err_disable(obj);
+
+ /* Set event flag */
+ obj_s->event = I2C_EVENT_ERROR;
+}
+
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+
+ // TODO: DMA usage is currently ignored by this way
+ (void) hint;
+
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ /* Update object */
+ obj->tx_buff.buffer = (void *)tx;
+ obj->tx_buff.length = tx_length;
+ obj->tx_buff.pos = 0;
+ obj->tx_buff.width = 8;
+
+ obj->rx_buff.buffer = (void *)rx;
+ obj->rx_buff.length = rx_length;
+ obj->rx_buff.pos = SIZE_MAX;
+ obj->rx_buff.width = 8;
+
+ obj_s->available_events = event;
+ obj_s->event = 0;
+ obj_s->address = address;
+ obj_s->stop = stop;
+
+ i2c_ev_err_enable(obj, handler);
+
+ /* Set operation step depending if stop sending required or not */
+ if ((tx_length && !rx_length) || (!tx_length && rx_length)) {
+ // Trick to remove compiler warning "left and right operands are identical" in some cases
+ uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+ uint32_t op2 = I2C_LAST_FRAME;
+ if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
+ if (stop) {
+ obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
+ } else {
+ obj_s->XferOperation = I2C_FIRST_FRAME;
+ }
+ } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
+ (obj_s->XferOperation == I2C_NEXT_FRAME)) {
+ if (stop) {
+ obj_s->XferOperation = I2C_LAST_FRAME;
+ } else {
+ obj_s->XferOperation = I2C_NEXT_FRAME;
+ }
+ }
+
+ if (tx_length > 0) {
+ HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, obj_s->XferOperation);
+ }
+ if (rx_length > 0) {
+ HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *)rx, rx_length, obj_s->XferOperation);
+ }
+ } else if (tx_length && rx_length) {
+ /* Two steps operation, don't modify XferOperation, keep it for next step */
+ // Trick to remove compiler warning "left and right operands are identical" in some cases
+ uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+ uint32_t op2 = I2C_LAST_FRAME;
+ if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
+ HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, I2C_FIRST_FRAME);
+ } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
+ (obj_s->XferOperation == I2C_NEXT_FRAME)) {
+ HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, I2C_NEXT_FRAME);
+ }
+ }
+}
+
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj)
+{
+
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ HAL_I2C_EV_IRQHandler(handle);
+ HAL_I2C_ER_IRQHandler(handle);
+
+ /* Return I2C event status */
+ return (obj_s->event & obj_s->available_events);
+}
+
+uint8_t i2c_active(i2c_t *obj)
+{
+
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ if (handle->State == HAL_I2C_STATE_READY) {
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+void i2c_abort_asynch(i2c_t *obj)
+{
+
+ struct i2c_s *obj_s = I2C_S(obj);
+ I2C_HandleTypeDef *handle = &(obj_s->handle);
+
+ /* Abort HAL requires DevAddress, but is not used. Use Dummy */
+ uint16_t Dummy_DevAddress = 0x00;
+
+ HAL_I2C_Master_Abort_IT(handle, Dummy_DevAddress);
+}
+
+#endif // DEVICE_I2C_ASYNCH
+
+#endif // DEVICE_I2C
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/lp_ticker.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/lp_ticker.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,284 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#if DEVICE_LPTICKER
+
+/***********************************************************************/
+/* lpticker_lptim config is 1 in json config file */
+/* LPTICKER is based on LPTIM feature from ST drivers. RTC is not used */
+#if MBED_CONF_TARGET_LPTICKER_LPTIM
+
+#include "lp_ticker_api.h"
+#include "mbed_error.h"
+
+LPTIM_HandleTypeDef LptimHandle;
+
+const ticker_info_t *lp_ticker_get_info()
+{
+ static const ticker_info_t info = {
+#if MBED_CONF_TARGET_LSE_AVAILABLE
+ LSE_VALUE,
+#else
+ LSI_VALUE,
+#endif
+ 16
+ };
+ return &info;
+}
+
+volatile uint8_t lp_Fired = 0;
+
+static void LPTIM1_IRQHandler(void);
+static void (*irq_handler)(void);
+
+void lp_ticker_init(void)
+{
+ /* Check if LPTIM is already configured */
+ if (__HAL_RCC_LPTIM1_IS_CLK_ENABLED()) {
+ lp_ticker_disable_interrupt();
+ return;
+ }
+
+ RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
+
+ /* Enable LSE clock */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+
+ /* Select the LSE clock as LPTIM peripheral clock */
+ RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1;
+#if (TARGET_STM32L0)
+ RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSE;
+#else
+ RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSE;
+#endif
+
+#else /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
+ /* Enable LSI clock */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+
+ /* Select the LSI clock as LPTIM peripheral clock */
+ RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1;
+#if (TARGET_STM32L0)
+ RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSI;
+#else
+ RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI;
+#endif
+
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("HAL_RCC_OscConfig ERROR\n");
+ return;
+ }
+
+ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) {
+ error("HAL_RCCEx_PeriphCLKConfig ERROR\n");
+ return;
+ }
+
+ __HAL_RCC_LPTIM1_CLK_ENABLE();
+ __HAL_RCC_LPTIM1_FORCE_RESET();
+ __HAL_RCC_LPTIM1_RELEASE_RESET();
+
+ /* Initialize the LPTIM peripheral */
+ LptimHandle.Instance = LPTIM1;
+ LptimHandle.State = HAL_LPTIM_STATE_RESET;
+ LptimHandle.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
+ LptimHandle.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;
+
+ LptimHandle.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
+ LptimHandle.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
+ LptimHandle.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
+ LptimHandle.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL;
+#if (TARGET_STM32L4)
+ LptimHandle.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO;
+ LptimHandle.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO;
+#endif /* TARGET_STM32L4 */
+
+ if (HAL_LPTIM_Init(&LptimHandle) != HAL_OK) {
+ error("HAL_LPTIM_Init ERROR\n");
+ return;
+ }
+
+ NVIC_SetVector(LPTIM1_IRQn, (uint32_t)LPTIM1_IRQHandler);
+
+#if !(TARGET_STM32L4)
+ /* EXTI lines are not configured by default */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+#endif
+
+ __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_CMPM);
+ HAL_LPTIM_Counter_Start(&LptimHandle, 0xFFFF);
+
+ /* Need to write a compare value in order to get LPTIM_FLAG_CMPOK in set_interrupt */
+ __HAL_LPTIM_COMPARE_SET(&LptimHandle, 0);
+}
+
+static void LPTIM1_IRQHandler(void)
+{
+ LptimHandle.Instance = LPTIM1;
+
+ if (lp_Fired) {
+ lp_Fired = 0;
+ if (irq_handler) {
+ irq_handler();
+ }
+ }
+
+ /* Compare match interrupt */
+ if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPM) != RESET) {
+ if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_CMPM) != RESET) {
+ /* Clear Compare match flag */
+ __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM);
+
+ if (irq_handler) {
+ irq_handler();
+ }
+ }
+ }
+
+#if !(TARGET_STM32L4)
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+#endif
+}
+
+uint32_t lp_ticker_read(void)
+{
+ uint32_t lp_time = LPTIM1->CNT;
+ /* Reading the LPTIM_CNT register may return unreliable values.
+ It is necessary to perform two consecutive read accesses and verify that the two returned values are identical */
+ while (lp_time != LPTIM1->CNT) {
+ lp_time = LPTIM1->CNT;
+ }
+ return lp_time;
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+ LptimHandle.Instance = LPTIM1;
+ irq_handler = (void (*)(void))lp_ticker_irq_handler;
+
+ /* CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed */
+ /* Any successive write before the CMPOK flag be set, will lead to unpredictable results */
+ while (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == RESET) {
+ }
+
+ __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK);
+ __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM);
+ __HAL_LPTIM_COMPARE_SET(&LptimHandle, timestamp);
+
+ NVIC_EnableIRQ(LPTIM1_IRQn);
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+ lp_Fired = 1;
+ NVIC_SetPendingIRQ(LPTIM1_IRQn);
+ NVIC_EnableIRQ(LPTIM1_IRQn);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+ NVIC_DisableIRQ(LPTIM1_IRQn);
+ LptimHandle.Instance = LPTIM1;
+ /* Waiting last write operation completion */
+ while (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == RESET) {
+ }
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+ LptimHandle.Instance = LPTIM1;
+ __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM);
+ NVIC_ClearPendingIRQ(LPTIM1_IRQn);
+}
+
+
+
+/*****************************************************************/
+/* lpticker_lptim config is 0 or not defined in json config file */
+/* LPTICKER is based on RTC wake up feature from ST drivers */
+#else /* MBED_CONF_TARGET_LPTICKER_LPTIM */
+
+#include "rtc_api_hal.h"
+
+const ticker_info_t *lp_ticker_get_info()
+{
+ static const ticker_info_t info = {
+ RTC_CLOCK / 4, // RTC_WAKEUPCLOCK_RTCCLK_DIV4
+ 32
+ };
+ return &info;
+}
+
+void lp_ticker_init(void)
+{
+ rtc_init();
+ lp_ticker_disable_interrupt();
+}
+
+uint32_t lp_ticker_read(void)
+{
+ return rtc_read_lp();
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+ lp_ticker_disable_interrupt();
+ rtc_set_wake_up_timer(timestamp);
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+ rtc_fire_interrupt();
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+ rtc_deactivate_wake_up_timer();
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+ NVIC_DisableIRQ(RTC_WKUP_IRQn);
+}
+
+#endif /* MBED_CONF_TARGET_LPTICKER_LPTIM */
+
+#endif /* DEVICE_LPTICKER */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/mbed_crc_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/mbed_crc_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,70 @@
+#include "crc_api.h"
+#include "device.h"
+
+#include "platform/mbed_assert.h"
+
+#ifdef DEVICE_CRC
+
+static CRC_HandleTypeDef current_state;
+static uint32_t final_xor;
+
+bool hal_crc_is_supported(const crc_mbed_config_t *config)
+{
+ if (config == NULL) {
+ return false;
+ }
+
+ if (config->polynomial != POLY_32BIT_ANSI) {
+ return false;
+ }
+
+ if (config->width != 32) {
+ return false;
+ }
+
+ if ((config->final_xor != 0xFFFFFFFFU) && (config->final_xor != 0)) {
+ return false;
+ }
+
+ return true;
+}
+
+void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
+{
+ MBED_ASSERT(hal_crc_is_supported(config));
+
+ __HAL_RCC_CRC_CLK_ENABLE();
+
+ final_xor = config->final_xor;
+
+ current_state.Instance = CRC;
+ current_state.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
+ current_state.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
+ current_state.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE;
+ current_state.Init.InitValue = config->initial_xor;
+ current_state.Init.CRCLength = CRC_POLYLENGTH_32B;
+ current_state.Init.InputDataInversionMode =
+ config->reflect_in ? CRC_INPUTDATA_INVERSION_BYTE
+ : CRC_INPUTDATA_INVERSION_NONE;
+ current_state.Init.OutputDataInversionMode =
+ config->reflect_out ? CRC_OUTPUTDATA_INVERSION_ENABLE
+ : CRC_OUTPUTDATA_INVERSION_DISABLE;
+
+ HAL_CRC_Init(¤t_state);
+}
+
+void hal_crc_compute_partial(const uint8_t *data, const size_t size)
+{
+ if (data && size) {
+ HAL_CRC_Accumulate(¤t_state, (uint32_t *)data, size);
+ }
+}
+
+uint32_t hal_crc_get_result(void)
+{
+ const uint32_t result = current_state.Instance->DR;
+
+ return (final_xor == 0xFFFFFFFFU) ? ~result : result;
+}
+
+#endif // DEVICE_CRC
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/mbed_overrides.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/mbed_overrides.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "cmsis.h"
+
+int mbed_sdk_inited = 0;
+
+// This function is called after RAM initialization and before main.
+void mbed_sdk_init()
+{
+#if TARGET_STM32F7
+ // The mbed_sdk_init can be called either during cold boot or during
+ // application boot after bootloader has been executed.
+ // In case the bootloader has already enabled the cache,
+ // is is needed to not enable it again.
+ if ((SCB->CCR & (uint32_t)SCB_CCR_IC_Msk) == 0) { // If ICache is disabled
+ SCB_EnableICache();
+ }
+ if ((SCB->CCR & (uint32_t)SCB_CCR_DC_Msk) == 0) { // If DCache is disabled
+ SCB_EnableDCache();
+ }
+#endif /* TARGET_STM32F7 */
+
+ // Update the SystemCoreClock variable.
+ SystemCoreClockUpdate();
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+ SystemCoreClockUpdate();
+
+ mbed_sdk_inited = 1;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/mbed_rtx.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/mbed_rtx.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,139 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#include <stdint.h> + +#ifndef INITIAL_SP + +#if (defined(TARGET_STM32L475VG) ||\ + defined(TARGET_STM32L476RG) ||\ + defined(TARGET_STM32L476JG) ||\ + defined(TARGET_STM32L476VG) ||\ + defined(TARGET_STM32L486RG)) +/* only GCC_ARM and IAR toolchains have the stack on SRAM2 */ +#if (((defined(__GNUC__) && !defined(__CC_ARM)) ||\ + defined(__IAR_SYSTEMS_ICC__ )) &&\ + defined(TWO_RAM_REGIONS)) +#define INITIAL_SP (0x10008000UL) +#else +#define INITIAL_SP (0x20018000UL) +#endif /* toolchains */ + +#elif (defined(TARGET_STM32F051R8) ||\ + defined(TARGET_STM32F100RB) ||\ + defined(TARGET_STM32L031K6) ||\ + defined(TARGET_STM32L053C8) ||\ + defined(TARGET_STM32L053R8)) +#define INITIAL_SP (0x20002000UL) + +#elif (defined(TARGET_STM32F303K8) ||\ + defined(TARGET_STM32F334C8) ||\ + defined(TARGET_STM32F334R8)) +#define INITIAL_SP (0x20003000UL) + +#elif (defined(TARGET_STM32F070RB) ||\ + defined(TARGET_STM32F072RB) ||\ + defined(TARGET_STM32F302R8)) +#define INITIAL_SP (0x20004000UL) + +#elif (defined(TARGET_STM32F103RB) ||\ + defined(TARGET_STM32F103C8) ||\ + defined(TARGET_STM32L072CZ) ||\ + defined(TARGET_STM32L073RZ) ||\ + defined(TARGET_STM32L0x2xZ)) +#define INITIAL_SP (0x20005000UL) + +#elif (defined(TARGET_STM32F091RC) ||\ + defined(TARGET_STM32F410RB) ||\ + defined(TARGET_STM32L151CBA)||\ + defined(TARGET_STM32L151CC) ||\ + defined(TARGET_STM32L151RC) ||\ + defined(TARGET_STM32L152RC)) +#define INITIAL_SP (0x20008000UL) + +#elif defined(TARGET_STM32F303VC) +#define INITIAL_SP (0x2000A000UL) + +#elif defined(TARGET_STM32L443RC) +#define INITIAL_SP (0x2000C000UL) + +#elif defined(TARGET_STM32L432KC) ||\ + defined (TARGET_STM32L433RC) +#define INITIAL_SP (0x20010000UL) + +#elif (defined(TARGET_STM32F303RE) ||\ + defined(TARGET_STM32F303ZE) ||\ + defined(TARGET_STM32F401VC)) +#define INITIAL_SP (0x20010000UL) + +#elif defined(TARGET_STM32L152RE) +#define INITIAL_SP (0x20014000UL) + +#elif (defined(TARGET_STM32F401RE) ||\ + defined(TARGET_STM32F401VE)) +#define INITIAL_SP (0x20018000UL) + +#elif (defined(TARGET_STM32F207ZG) ||\ + defined(TARGET_STM32F405RG) ||\ + defined(TARGET_STM32F407VG) ||\ + defined(TARGET_STM32F411RE) ||\ + defined(TARGET_STM32F446RE) ||\ + defined(TARGET_STM32F446VE) ||\ + defined(TARGET_STM32F446ZE)) +#define INITIAL_SP (0x20020000UL) + +#elif (defined(TARGET_STM32F429ZI) ||\ + defined(TARGET_STM32F437VG) ||\ + defined(TARGET_STM32F439VI) ||\ + defined(TARGET_STM32F439ZI)) +#define INITIAL_SP (0x20030000UL) + +#elif defined(TARGET_STM32F412ZG) +#define INITIAL_SP (0x20040000UL) + +#elif (defined(TARGET_STM32F413ZH) ||\ + defined(TARGET_STM32F469NI) ||\ + defined(TARGET_STM32F746NG) ||\ + defined(TARGET_STM32F746ZG) ||\ + defined(TARGET_STM32F756ZG) ||\ + defined(TARGET_STM32L496AG) ||\ + defined(TARGET_STM32L496ZG)) +#define INITIAL_SP (0x20050000UL) + +#elif (defined(TARGET_STM32F767ZI) ||\ + defined(TARGET_STM32F769NI)) +#define INITIAL_SP (0x20080000UL) + +#else +#error "INITIAL_SP is not defined for this target in the mbed_rtx.h file" +#endif + +#endif // INITIAL_SP +#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS)) +extern uint32_t __StackLimit[]; +extern uint32_t __StackTop[]; +extern uint32_t __end__[]; +extern uint32_t __HeapLimit[]; +#define HEAP_START ((unsigned char*)__end__) +#define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) +#define ISR_STACK_START ((unsigned char*)__StackLimit) +#define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) +#endif + +#endif // MBED_MBED_RTX_H
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/nvic_addr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/nvic_addr.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef NVIC_ADDR_H
+#define NVIC_ADDR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ICCARM__)
+#pragma section=".intvec"
+#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
+#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+extern uint32_t Load$$LR$$LR_IROM1$$Base[];
+#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
+#elif defined(__GNUC__)
+extern uint32_t g_pfnVectors[];
+#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors)
+#else
+#error "Flash vector address not set for this toolchain"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/pinmap.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/pinmap.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,159 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "PortNames.h"
+#include "mbed_error.h"
+#include "pin_device.h"
+
+extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx);
+
+const uint32_t ll_pin_defines[16] = {
+ LL_GPIO_PIN_0,
+ LL_GPIO_PIN_1,
+ LL_GPIO_PIN_2,
+ LL_GPIO_PIN_3,
+ LL_GPIO_PIN_4,
+ LL_GPIO_PIN_5,
+ LL_GPIO_PIN_6,
+ LL_GPIO_PIN_7,
+ LL_GPIO_PIN_8,
+ LL_GPIO_PIN_9,
+ LL_GPIO_PIN_10,
+ LL_GPIO_PIN_11,
+ LL_GPIO_PIN_12,
+ LL_GPIO_PIN_13,
+ LL_GPIO_PIN_14,
+ LL_GPIO_PIN_15
+};
+
+/**
+ * Configure pin (mode, speed, output type and pull-up/pull-down)
+ */
+void pin_function(PinName pin, int data)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+
+ // Get the pin informations
+ uint32_t mode = STM_PIN_FUNCTION(data);
+ uint32_t afnum = STM_PIN_AFNUM(data);
+ uint32_t port = STM_PORT(pin);
+ uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
+ uint32_t ll_mode = 0;
+
+ // Enable GPIO clock
+ GPIO_TypeDef *gpio = Set_GPIO_Clock(port);
+
+ /* Set default speed to high.
+ * For most families there are dedicated registers so it is
+ * not so important, register can be set at any time.
+ * But for families like F1, speed only applies to output.
+ */
+#if defined (TARGET_STM32F1)
+ if (mode == STM_PIN_OUTPUT) {
+#endif
+ LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH);
+#if defined (TARGET_STM32F1)
+ }
+#endif
+
+ switch (mode) {
+ case STM_PIN_INPUT:
+ ll_mode = LL_GPIO_MODE_INPUT;
+ break;
+ case STM_PIN_OUTPUT:
+ ll_mode = LL_GPIO_MODE_OUTPUT;
+ break;
+ case STM_PIN_ALTERNATE:
+ ll_mode = LL_GPIO_MODE_ALTERNATE;
+ // In case of ALT function, also set he afnum
+ stm_pin_SetAFPin(gpio, pin, afnum);
+ break;
+ case STM_PIN_ANALOG:
+ ll_mode = LL_GPIO_MODE_ANALOG;
+ break;
+ default:
+ MBED_ASSERT(0);
+ break;
+ }
+ LL_GPIO_SetPinMode(gpio, ll_pin, ll_mode);
+
+#if defined(GPIO_ASCR_ASC0)
+ /* For families where Analog Control ASC0 register is present */
+ if (STM_PIN_ANALOG_CONTROL(data)) {
+ LL_GPIO_EnablePinAnalogControl(gpio, ll_pin);
+ } else {
+ LL_GPIO_DisablePinAnalogControl(gpio, ll_pin);
+ }
+#endif
+
+ /* For now by default use Speed HIGH for output or alt modes */
+ if ((mode == STM_PIN_OUTPUT) || (mode == STM_PIN_ALTERNATE)) {
+ if (STM_PIN_OD(data)) {
+ LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_OPENDRAIN);
+ } else {
+ LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_PUSHPULL);
+ }
+ }
+
+ stm_pin_PullConfig(gpio, ll_pin, STM_PIN_PUPD(data));
+
+ stm_pin_DisconnectDebug(pin);
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
+ // Enable GPIO clock
+ GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
+ uint32_t function = LL_GPIO_GetPinMode(gpio, ll_pin);
+
+ if ((function == LL_GPIO_MODE_OUTPUT) || (function == LL_GPIO_MODE_ALTERNATE)) {
+ if ((mode == OpenDrainNoPull) || (mode == OpenDrainPullUp) || (mode == OpenDrainPullDown)) {
+ LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_OPENDRAIN);
+ } else {
+ LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_PUSHPULL);
+ }
+ }
+
+ if ((mode == OpenDrainPullUp) || (mode == PullUp)) {
+ stm_pin_PullConfig(gpio, ll_pin, GPIO_PULLUP);
+ } else if ((mode == OpenDrainPullDown) || (mode == PullDown)) {
+ stm_pin_PullConfig(gpio, ll_pin, GPIO_PULLDOWN);
+ } else {
+ stm_pin_PullConfig(gpio, ll_pin, GPIO_NOPULL);
+ }
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/port_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/port_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "mbed_error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx);
+
+// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
+// low nibble = pin number
+PinName port_pin(PortName port, int pin_n)
+{
+ return (PinName)(pin_n + (port << 4));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+ uint32_t port_index = (uint32_t)port;
+
+ // Enable GPIO clock
+ GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
+
+ // Fill PORT object structure for future use
+ obj->port = port;
+ obj->mask = mask;
+ obj->direction = dir;
+ obj->reg_in = &gpio->IDR;
+ obj->reg_out = &gpio->ODR;
+
+ port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+ uint32_t i;
+ obj->direction = dir;
+ for (i = 0; i < 16; i++) { // Process all pins
+ if (obj->mask & (1 << i)) { // If the pin is used
+ if (dir == PIN_OUTPUT) {
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+ } else { // PIN_INPUT
+ pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ }
+ }
+ }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+ uint32_t i;
+ for (i = 0; i < 16; i++) { // Process all pins
+ if (obj->mask & (1 << i)) { // If the pin is used
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_write(port_t *obj, int value)
+{
+ *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj)
+{
+ if (obj->direction == PIN_OUTPUT) {
+ return (*obj->reg_out & obj->mask);
+ } else { // PIN_INPUT
+ return (*obj->reg_in & obj->mask);
+ }
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/pwmout_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/pwmout_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,344 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include "pwmout_device.h"
+
+static TIM_HandleTypeDef TimHandle;
+
+void pwmout_init(pwmout_t *obj, PinName pin)
+{
+ // Get the peripheral name from the pin and assign it to the object
+ obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+ MBED_ASSERT(obj->pwm != (PWMName)NC);
+
+ // Get the functions (timer channel, (non)inverted) from the pin and assign it to the object
+ uint32_t function = pinmap_function(pin, PinMap_PWM);
+ MBED_ASSERT(function != (uint32_t)NC);
+ obj->channel = STM_PIN_CHANNEL(function);
+ obj->inverted = STM_PIN_INVERTED(function);
+
+ // Enable TIM clock
+#if defined(TIM1_BASE)
+ if (obj->pwm == PWM_1) {
+ __HAL_RCC_TIM1_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM2_BASE)
+ if (obj->pwm == PWM_2) {
+ __HAL_RCC_TIM2_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM3_BASE)
+ if (obj->pwm == PWM_3) {
+ __HAL_RCC_TIM3_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM4_BASE)
+ if (obj->pwm == PWM_4) {
+ __HAL_RCC_TIM4_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM5_BASE)
+ if (obj->pwm == PWM_5) {
+ __HAL_RCC_TIM5_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM8_BASE)
+ if (obj->pwm == PWM_8) {
+ __HAL_RCC_TIM8_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM9_BASE)
+ if (obj->pwm == PWM_9) {
+ __HAL_RCC_TIM9_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM10_BASE)
+ if (obj->pwm == PWM_10) {
+ __HAL_RCC_TIM10_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM11_BASE)
+ if (obj->pwm == PWM_11) {
+ __HAL_RCC_TIM11_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM12_BASE)
+ if (obj->pwm == PWM_12) {
+ __HAL_RCC_TIM12_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM13_BASE)
+ if (obj->pwm == PWM_13) {
+ __HAL_RCC_TIM13_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM14_BASE)
+ if (obj->pwm == PWM_14) {
+ __HAL_RCC_TIM14_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM15_BASE)
+ if (obj->pwm == PWM_15) {
+ __HAL_RCC_TIM15_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM16_BASE)
+ if (obj->pwm == PWM_16) {
+ __HAL_RCC_TIM16_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM17_BASE)
+ if (obj->pwm == PWM_17) {
+ __HAL_RCC_TIM17_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM18_BASE)
+ if (obj->pwm == PWM_18) {
+ __HAL_RCC_TIM18_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM19_BASE)
+ if (obj->pwm == PWM_19) {
+ __HAL_RCC_TIM19_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM20_BASE)
+ if (obj->pwm == PWM_20) {
+ __HAL_RCC_TIM20_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM21_BASE)
+ if (obj->pwm == PWM_21) {
+ __HAL_RCC_TIM21_CLK_ENABLE();
+ }
+#endif
+#if defined(TIM22_BASE)
+ if (obj->pwm == PWM_22) {
+ __HAL_RCC_TIM22_CLK_ENABLE();
+ }
+#endif
+ // Configure GPIO
+ pinmap_pinout(pin, PinMap_PWM);
+
+ obj->pin = pin;
+ obj->period = 0;
+ obj->pulse = 0;
+ obj->prescaler = 1;
+
+ pwmout_period_us(obj, 20000); // 20 ms per default
+}
+
+void pwmout_free(pwmout_t *obj)
+{
+ // Configure GPIO
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+void pwmout_write(pwmout_t *obj, float value)
+{
+ TIM_OC_InitTypeDef sConfig;
+ int channel = 0;
+
+ TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+
+ if (value < (float)0.0) {
+ value = 0.0;
+ } else if (value > (float)1.0) {
+ value = 1.0;
+ }
+
+ obj->pulse = (uint32_t)((float)obj->period * value);
+
+ // Configure channels
+ sConfig.OCMode = TIM_OCMODE_PWM1;
+ sConfig.Pulse = obj->pulse / obj->prescaler;
+ sConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
+ sConfig.OCFastMode = TIM_OCFAST_DISABLE;
+#if defined(TIM_OCIDLESTATE_RESET)
+ sConfig.OCIdleState = TIM_OCIDLESTATE_RESET;
+#endif
+#if defined(TIM_OCNIDLESTATE_RESET)
+ sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+#endif
+
+ switch (obj->channel) {
+ case 1:
+ channel = TIM_CHANNEL_1;
+ break;
+ case 2:
+ channel = TIM_CHANNEL_2;
+ break;
+ case 3:
+ channel = TIM_CHANNEL_3;
+ break;
+ case 4:
+ channel = TIM_CHANNEL_4;
+ break;
+ default:
+ return;
+ }
+
+ if (HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel) != HAL_OK) {
+ error("Cannot initialize PWM\n");
+ }
+
+#if !defined(PWMOUT_INVERTED_NOT_SUPPORTED)
+ if (obj->inverted) {
+ HAL_TIMEx_PWMN_Start(&TimHandle, channel);
+ } else
+#endif
+ {
+ HAL_TIM_PWM_Start(&TimHandle, channel);
+ }
+}
+
+float pwmout_read(pwmout_t *obj)
+{
+ float value = 0;
+ if (obj->period > 0) {
+ value = (float)(obj->pulse) / (float)(obj->period);
+ }
+ return ((value > (float)1.0) ? (float)(1.0) : (value));
+}
+
+void pwmout_period(pwmout_t *obj, float seconds)
+{
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t *obj, int ms)
+{
+ pwmout_period_us(obj, ms * 1000);
+}
+
+void pwmout_period_us(pwmout_t *obj, int us)
+{
+ TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ uint32_t PclkFreq = 0;
+ uint32_t APBxCLKDivider = RCC_HCLK_DIV1;
+ float dc = pwmout_read(obj);
+ uint8_t i = 0;
+
+ __HAL_TIM_DISABLE(&TimHandle);
+
+ // Get clock configuration
+ // Note: PclkFreq contains here the Latency (not used after)
+ HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq);
+
+ /* Parse the pwm / apb mapping table to find the right entry */
+ while (pwm_apb_map_table[i].pwm != obj->pwm) {
+ i++;
+ }
+
+ if (pwm_apb_map_table[i].pwm == 0) {
+ error("Unknown PWM instance");
+ }
+
+ if (pwm_apb_map_table[i].pwmoutApb == PWMOUT_ON_APB1) {
+ PclkFreq = HAL_RCC_GetPCLK1Freq();
+ APBxCLKDivider = RCC_ClkInitStruct.APB1CLKDivider;
+ } else {
+#if !defined(PWMOUT_APB2_NOT_SUPPORTED)
+ PclkFreq = HAL_RCC_GetPCLK2Freq();
+ APBxCLKDivider = RCC_ClkInitStruct.APB2CLKDivider;
+#endif
+ }
+
+
+ /* By default use, 1us as SW pre-scaler */
+ obj->prescaler = 1;
+ // TIMxCLK = PCLKx when the APB prescaler = 1 else TIMxCLK = 2 * PCLKx
+ if (APBxCLKDivider == RCC_HCLK_DIV1) {
+ TimHandle.Init.Prescaler = (((PclkFreq) / 1000000)) - 1; // 1 us tick
+ } else {
+ TimHandle.Init.Prescaler = (((PclkFreq * 2) / 1000000)) - 1; // 1 us tick
+ }
+ TimHandle.Init.Period = (us - 1);
+
+ /* In case period or pre-scalers are out of range, loop-in to get valid values */
+ while ((TimHandle.Init.Period > 0xFFFF) || (TimHandle.Init.Prescaler > 0xFFFF)) {
+ obj->prescaler = obj->prescaler * 2;
+ if (APBxCLKDivider == RCC_HCLK_DIV1) {
+ TimHandle.Init.Prescaler = (((PclkFreq) / 1000000) * obj->prescaler) - 1;
+ } else {
+ TimHandle.Init.Prescaler = (((PclkFreq * 2) / 1000000) * obj->prescaler) - 1;
+ }
+ TimHandle.Init.Period = (us - 1) / obj->prescaler;
+ /* Period decreases and prescaler increases over loops, so check for
+ * possible out of range cases */
+ if ((TimHandle.Init.Period < 0xFFFF) && (TimHandle.Init.Prescaler > 0xFFFF)) {
+ error("Cannot initialize PWM\n");
+ break;
+ }
+ }
+
+ TimHandle.Init.ClockDivision = 0;
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+
+ if (HAL_TIM_PWM_Init(&TimHandle) != HAL_OK) {
+ error("Cannot initialize PWM\n");
+ }
+
+ // Save for future use
+ obj->period = us;
+
+ // Set duty cycle again
+ pwmout_write(obj, dc);
+
+ __HAL_TIM_ENABLE(&TimHandle);
+}
+
+void pwmout_pulsewidth(pwmout_t *obj, float seconds)
+{
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
+{
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t *obj, int us)
+{
+ float value = (float)us / (float)obj->period;
+ pwmout_write(obj, value);
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/rtc_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/rtc_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,422 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#if DEVICE_RTC
+
+#include "rtc_api_hal.h"
+#include "mbed_mktime.h"
+#include "mbed_error.h"
+#include "mbed_critical.h"
+
+#if DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM
+volatile uint32_t LP_continuous_time = 0;
+volatile uint32_t LP_last_RTC_time = 0;
+#endif
+
+static int RTC_inited = 0;
+
+static RTC_HandleTypeDef RtcHandle;
+
+void rtc_init(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ if (RTC_inited) {
+ return;
+ }
+ RTC_inited = 1;
+
+ // Enable access to Backup domain
+ __HAL_RCC_PWR_CLK_ENABLE();
+ HAL_PWR_EnableBkUpAccess();
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("Cannot initialize RTC with LSE\n");
+ }
+
+ __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ error("PeriphClkInitStruct RTC failed with LSE\n");
+ }
+#else /* MBED_CONF_TARGET_LSE_AVAILABLE */
+ // Reset Backup domain
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ // Enable LSI clock
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("Cannot initialize RTC with LSI\n");
+ }
+
+ __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ error("PeriphClkInitStruct RTC failed with LSI\n");
+ }
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
+ // Enable RTC
+ __HAL_RCC_RTC_ENABLE();
+
+ RtcHandle.Instance = RTC;
+ RtcHandle.State = HAL_RTC_STATE_RESET;
+
+#if TARGET_STM32F1
+ RtcHandle.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
+#else /* TARGET_STM32F1 */
+ RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
+ RtcHandle.Init.AsynchPrediv = PREDIV_A_VALUE;
+ RtcHandle.Init.SynchPrediv = PREDIV_S_VALUE;
+ RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+#endif /* TARGET_STM32F1 */
+
+ if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+ error("RTC initialization failed");
+ }
+
+#if !(TARGET_STM32F1) && !(TARGET_STM32F2)
+ /* STM32F1 : there are no shadow registers */
+ /* STM32F2 : shadow registers can not be bypassed */
+ if (HAL_RTCEx_EnableBypassShadow(&RtcHandle) != HAL_OK) {
+ error("EnableBypassShadow error");
+ }
+#endif /* TARGET_STM32F1 || TARGET_STM32F2 */
+}
+
+void rtc_free(void)
+{
+ /* RTC clock can not be reset */
+}
+
+
+/*
+Information about STM32F0, STM32F2, STM32F3, STM32F4, STM32F7, STM32L0, STM32L1, STM32L4:
+BCD format is used to store the date in the RTC. The year is store on 2 * 4 bits.
+Because the first year is reserved to see if the RTC is init, the supposed range is 01-99.
+1st point is to cover the standard range from 1970 to 2038 (limited by the 32 bits of time_t).
+2nd point is to keep the year 1970 and the leap years synchronized.
+
+So by moving it 68 years forward from 1970, it become 1969-2067 which include 1970-2038.
+68 is also a multiple of 4 so it let the leap year synchronized.
+
+Information about STM32F1:
+32bit register is used (no BCD format) for the seconds.
+For date, there is no specific register, only a software structure.
+It is then not a problem to not use shifts.
+*/
+#if TARGET_STM32F1
+time_t rtc_read(void)
+{
+ RTC_DateTypeDef dateStruct = {0};
+ RTC_TimeTypeDef timeStruct = {0};
+ struct tm timeinfo;
+
+ RtcHandle.Instance = RTC;
+
+ // Read actual date and time
+ // Warning: the time must be read first!
+ HAL_RTC_GetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN);
+ HAL_RTC_GetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN);
+
+ /* date information is null before first write procedure */
+ /* set 01/01/1970 as default values */
+ if (dateStruct.Year == 0) {
+ dateStruct.Year = 2 ;
+ dateStruct.Month = 1 ;
+ dateStruct.Date = 1 ;
+ }
+
+ // Setup a tm structure based on the RTC
+ /* tm_wday information is ignored by _rtc_maketime */
+ /* tm_isdst information is ignored by _rtc_maketime */
+ timeinfo.tm_mon = dateStruct.Month - 1;
+ timeinfo.tm_mday = dateStruct.Date;
+ timeinfo.tm_year = dateStruct.Year + 68;
+ timeinfo.tm_hour = timeStruct.Hours;
+ timeinfo.tm_min = timeStruct.Minutes;
+ timeinfo.tm_sec = timeStruct.Seconds;
+
+ // Convert to timestamp
+ time_t t;
+ if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
+ return 0;
+ }
+
+ return t;
+}
+
+#else /* TARGET_STM32F1 */
+
+time_t rtc_read(void)
+{
+ struct tm timeinfo;
+
+ /* Since the shadow registers are bypassed we have to read the time twice and compare them until both times are the same */
+ uint32_t Read_time = RTC->TR & RTC_TR_RESERVED_MASK;
+ uint32_t Read_date = RTC->DR & RTC_DR_RESERVED_MASK;
+
+ while ((Read_time != (RTC->TR & RTC_TR_RESERVED_MASK)) || (Read_date != (RTC->DR & RTC_DR_RESERVED_MASK))) {
+ Read_time = RTC->TR & RTC_TR_RESERVED_MASK;
+ Read_date = RTC->DR & RTC_DR_RESERVED_MASK;
+ }
+
+ /* Setup a tm structure based on the RTC
+ struct tm :
+ tm_sec seconds after the minute 0-61
+ tm_min minutes after the hour 0-59
+ tm_hour hours since midnight 0-23
+ tm_mday day of the month 1-31
+ tm_mon months since January 0-11
+ tm_year years since 1900
+ tm_yday information is ignored by _rtc_maketime
+ tm_wday information is ignored by _rtc_maketime
+ tm_isdst information is ignored by _rtc_maketime
+ */
+ timeinfo.tm_mday = RTC_Bcd2ToByte((uint8_t)(Read_date & (RTC_DR_DT | RTC_DR_DU)));
+ timeinfo.tm_mon = RTC_Bcd2ToByte((uint8_t)((Read_date & (RTC_DR_MT | RTC_DR_MU)) >> 8)) - 1;
+ timeinfo.tm_year = RTC_Bcd2ToByte((uint8_t)((Read_date & (RTC_DR_YT | RTC_DR_YU)) >> 16)) + 68;
+ timeinfo.tm_hour = RTC_Bcd2ToByte((uint8_t)((Read_time & (RTC_TR_HT | RTC_TR_HU)) >> 16));
+ timeinfo.tm_min = RTC_Bcd2ToByte((uint8_t)((Read_time & (RTC_TR_MNT | RTC_TR_MNU)) >> 8));
+ timeinfo.tm_sec = RTC_Bcd2ToByte((uint8_t)((Read_time & (RTC_TR_ST | RTC_TR_SU)) >> 0));
+
+ // Convert to timestamp
+ time_t t;
+ if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
+ return 0;
+ }
+
+ return t;
+}
+
+#endif /* TARGET_STM32F1 */
+
+void rtc_write(time_t t)
+{
+ RTC_DateTypeDef dateStruct = {0};
+ RTC_TimeTypeDef timeStruct = {0};
+
+ core_util_critical_section_enter();
+ RtcHandle.Instance = RTC;
+
+ // Convert the time into a tm
+ struct tm timeinfo;
+ if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
+ return;
+ }
+
+ // Fill RTC structures
+ if (timeinfo.tm_wday == 0) { /* Sunday specific case */
+ dateStruct.WeekDay = RTC_WEEKDAY_SUNDAY;
+ } else {
+ dateStruct.WeekDay = timeinfo.tm_wday;
+ }
+ dateStruct.Month = timeinfo.tm_mon + 1;
+ dateStruct.Date = timeinfo.tm_mday;
+ dateStruct.Year = timeinfo.tm_year - 68;
+ timeStruct.Hours = timeinfo.tm_hour;
+ timeStruct.Minutes = timeinfo.tm_min;
+ timeStruct.Seconds = timeinfo.tm_sec;
+
+#if !(TARGET_STM32F1)
+ timeStruct.TimeFormat = RTC_HOURFORMAT_24;
+ timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
+ timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
+#endif /* TARGET_STM32F1 */
+
+#if DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM
+ /* Need to update LP_continuous_time value before new RTC time */
+ rtc_read_lp();
+
+ /* LP_last_RTC_time value is updated with the new RTC time */
+ LP_last_RTC_time = timeStruct.Seconds + timeStruct.Minutes * 60 + timeStruct.Hours * 60 * 60;
+
+ /* Save current SSR */
+ uint32_t Read_SubSeconds = (uint32_t)(RTC->SSR);
+#endif /* DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM */
+
+ // Change the RTC current date/time
+ if (HAL_RTC_SetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN) != HAL_OK) {
+ error("HAL_RTC_SetDate error\n");
+ }
+ if (HAL_RTC_SetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN) != HAL_OK) {
+ error("HAL_RTC_SetTime error\n");
+ }
+
+#if DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM
+ while (Read_SubSeconds != (RTC->SSR)) {
+ }
+#endif /* DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM */
+
+ core_util_critical_section_exit();
+}
+
+int rtc_isenabled(void)
+{
+#if !(TARGET_STM32F1)
+ return ((RTC->ISR & RTC_ISR_INITS) == RTC_ISR_INITS);
+#else /* TARGET_STM32F1 */
+ return ((RTC->CRL & RTC_CRL_RSF) == RTC_CRL_RSF);
+#endif /* TARGET_STM32F1 */
+}
+
+
+#if DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM
+
+static void RTC_IRQHandler(void);
+static void (*irq_handler)(void);
+
+volatile uint8_t lp_Fired = 0;
+
+static void RTC_IRQHandler(void)
+{
+ /* Update HAL state */
+ RtcHandle.Instance = RTC;
+ if (__HAL_RTC_WAKEUPTIMER_GET_IT(&RtcHandle, RTC_IT_WUT)) {
+ /* Get the status of the Interrupt */
+ if ((uint32_t)(RTC->CR & RTC_IT_WUT) != (uint32_t)RESET) {
+ /* Clear the WAKEUPTIMER interrupt pending bit */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&RtcHandle, RTC_FLAG_WUTF);
+
+ lp_Fired = 0;
+ if (irq_handler) {
+ irq_handler();
+ }
+ }
+ }
+
+ if (lp_Fired) {
+ lp_Fired = 0;
+ if (irq_handler) {
+ irq_handler();
+ }
+ }
+
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+}
+
+uint32_t rtc_read_lp(void)
+{
+ struct tm timeinfo;
+
+ /* Since the shadow registers are bypassed we have to read the time twice and compare them until both times are the same */
+ /* We don't have to read date as we bypass shadow registers */
+ uint32_t Read_SecondFraction = (uint32_t)(RTC->PRER & RTC_PRER_PREDIV_S);
+ uint32_t Read_time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
+ uint32_t Read_SubSeconds = (uint32_t)(RTC->SSR);
+
+ while ((Read_time != (RTC->TR & RTC_TR_RESERVED_MASK)) || (Read_SubSeconds != (RTC->SSR))) {
+ Read_time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
+ Read_SubSeconds = (uint32_t)(RTC->SSR);
+ }
+
+ timeinfo.tm_hour = RTC_Bcd2ToByte((uint8_t)((Read_time & (RTC_TR_HT | RTC_TR_HU)) >> 16));
+ timeinfo.tm_min = RTC_Bcd2ToByte((uint8_t)((Read_time & (RTC_TR_MNT | RTC_TR_MNU)) >> 8));
+ timeinfo.tm_sec = RTC_Bcd2ToByte((uint8_t)((Read_time & (RTC_TR_ST | RTC_TR_SU)) >> 0));
+
+ uint32_t RTC_time_s = timeinfo.tm_sec + timeinfo.tm_min * 60 + timeinfo.tm_hour * 60 * 60; // Max 0x0001-517F => * 8191 + 8191 = 0x2A2E-AE80
+
+ if (LP_last_RTC_time <= RTC_time_s) {
+ LP_continuous_time += (RTC_time_s - LP_last_RTC_time);
+ } else {
+ /* Add 24h */
+ LP_continuous_time += (24 * 60 * 60 + RTC_time_s - LP_last_RTC_time);
+ }
+ LP_last_RTC_time = RTC_time_s;
+
+ return LP_continuous_time * PREDIV_S_VALUE + Read_SecondFraction - Read_SubSeconds;
+}
+
+void rtc_set_wake_up_timer(timestamp_t timestamp)
+{
+ uint32_t WakeUpCounter;
+ uint32_t current_lp_time;
+
+ current_lp_time = rtc_read_lp();
+
+ if (timestamp < current_lp_time) {
+ WakeUpCounter = 0xFFFFFFFF - current_lp_time + timestamp;
+ } else {
+ WakeUpCounter = timestamp - current_lp_time;
+ }
+
+ if (WakeUpCounter > 0xFFFF) {
+ WakeUpCounter = 0xFFFF;
+ }
+
+ RtcHandle.Instance = RTC;
+ if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, WakeUpCounter, RTC_WAKEUPCLOCK_RTCCLK_DIV4) != HAL_OK) {
+ error("rtc_set_wake_up_timer init error\n");
+ }
+
+ NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)RTC_IRQHandler);
+ irq_handler = (void (*)(void))lp_ticker_irq_handler;
+ NVIC_EnableIRQ(RTC_WKUP_IRQn);
+}
+
+void rtc_fire_interrupt(void)
+{
+ lp_Fired = 1;
+ NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)RTC_IRQHandler);
+ irq_handler = (void (*)(void))lp_ticker_irq_handler;
+ NVIC_SetPendingIRQ(RTC_WKUP_IRQn);
+ NVIC_EnableIRQ(RTC_WKUP_IRQn);
+}
+
+void rtc_deactivate_wake_up_timer(void)
+{
+ RtcHandle.Instance = RTC;
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&RtcHandle);
+ __HAL_RTC_WAKEUPTIMER_DISABLE(&RtcHandle);
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&RtcHandle, RTC_IT_WUT);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&RtcHandle);
+ NVIC_DisableIRQ(RTC_WKUP_IRQn);
+}
+
+#endif /* DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM */
+
+#endif /* DEVICE_RTC */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/rtc_api_hal.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/rtc_api_hal.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+*******************************************************************************
+* Copyright (c) 2018, STMicroelectronics
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 3. Neither the name of STMicroelectronics nor the names of its contributors
+* may be used to endorse or promote products derived from this software
+* without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+*/
+
+#ifndef MBED_RTC_API_HAL_H
+#define MBED_RTC_API_HAL_H
+
+#include "rtc_api.h"
+#include "lp_ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
+#define RTC_CLOCK LSE_VALUE
+#else
+#define RTC_CLOCK LSI_VALUE
+#endif
+
+#if DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM
+/* PREDIV_A : 7-bit asynchronous prescaler */
+/* PREDIV_A is set to set LPTICKER frequency to RTC_CLOCK/4 */
+#define PREDIV_A_VALUE 3
+
+/** Read RTC counter with sub second precision
+ *
+ * @return LP ticker counter
+ */
+uint32_t rtc_read_lp(void);
+
+/** Program a wake up timer event
+ *
+ * @param timestamp: counter to set
+ */
+void rtc_set_wake_up_timer(timestamp_t timestamp);
+
+/** Call RTC Wake Up IT
+ */
+void rtc_fire_interrupt(void);
+
+/** Disable the wake up timer event.
+ *
+ * The wake up timer use auto reload, you have to deactivate it manually.
+ */
+void rtc_deactivate_wake_up_timer(void);
+
+#else /* DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM */
+
+/* PREDIV_A : 7-bit asynchronous prescaler */
+/* PREDIV_A is set to the maximum value to improve the consumption */
+#define PREDIV_A_VALUE 127
+
+#endif /* DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM */
+
+/* PREDIV_S : 15-bit synchronous prescaler */
+/* PREDIV_S is set in order to get a 1 Hz clock */
+#define PREDIV_S_VALUE RTC_CLOCK / (PREDIV_A_VALUE + 1) - 1
+
+/** Synchronise the RTC shadow registers.
+ *
+ * Must be called after a deepsleep.
+ */
+void rtc_synchronize(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/serial_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/serial_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,764 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#if DEVICE_SERIAL
+
+#include "serial_api_hal.h"
+
+// Possible choices of the LPUART_CLOCK_SOURCE configuration set in json file
+#define USE_LPUART_CLK_LSE 0x01
+#define USE_LPUART_CLK_PCLK1 0x02
+#define USE_LPUART_CLK_HSI 0x04
+
+int stdio_uart_inited = 0; // used in platform/mbed_board.c and platform/mbed_retarget.cpp
+serial_t stdio_uart;
+
+extern UART_HandleTypeDef uart_handlers[];
+extern uint32_t serial_irq_ids[];
+
+// Utility functions
+HAL_StatusTypeDef init_uart(serial_t *obj);
+int8_t get_uart_index(UARTName uart_name);
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ uint8_t stdio_config = 0;
+
+ // Determine the UART to use (UART_1, UART_2, ...)
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+
+ // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+ obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+ MBED_ASSERT(obj_s->uart != (UARTName)NC);
+
+ if ((tx == STDIO_UART_TX) || (rx == STDIO_UART_RX)) {
+ stdio_config = 1;
+ } else {
+ if (uart_tx == pinmap_peripheral(STDIO_UART_TX, PinMap_UART_TX)) {
+ error("Error: new serial object is using same UART as STDIO");
+ }
+ }
+
+ // Reset and enable clock
+#if defined(USART1_BASE)
+ if (obj_s->uart == UART_1) {
+ __HAL_RCC_USART1_CLK_ENABLE();
+ }
+#endif
+
+#if defined (USART2_BASE)
+ if (obj_s->uart == UART_2) {
+ __HAL_RCC_USART2_CLK_ENABLE();
+ }
+#endif
+
+#if defined(USART3_BASE)
+ if (obj_s->uart == UART_3) {
+ __HAL_RCC_USART3_CLK_ENABLE();
+ }
+#endif
+
+#if defined(UART4_BASE)
+ if (obj_s->uart == UART_4) {
+ __HAL_RCC_UART4_CLK_ENABLE();
+ }
+#endif
+
+#if defined(USART4_BASE)
+ if (obj_s->uart == UART_4) {
+ __HAL_RCC_USART4_CLK_ENABLE();
+ }
+#endif
+
+#if defined(UART5_BASE)
+ if (obj_s->uart == UART_5) {
+ __HAL_RCC_UART5_CLK_ENABLE();
+ }
+#endif
+
+#if defined(USART5_BASE)
+ if (obj_s->uart == UART_5) {
+ __HAL_RCC_USART5_CLK_ENABLE();
+ }
+#endif
+
+#if defined(USART6_BASE)
+ if (obj_s->uart == UART_6) {
+ __HAL_RCC_USART6_CLK_ENABLE();
+ }
+#endif
+
+#if defined(UART7_BASE)
+ if (obj_s->uart == UART_7) {
+ __HAL_RCC_UART7_CLK_ENABLE();
+ }
+#endif
+
+#if defined(USART7_BASE)
+ if (obj_s->uart == UART_7) {
+ __HAL_RCC_USART7_CLK_ENABLE();
+ }
+#endif
+
+#if defined(UART8_BASE)
+ if (obj_s->uart == UART_8) {
+ __HAL_RCC_UART8_CLK_ENABLE();
+ }
+#endif
+
+#if defined(USART8_BASE)
+ if (obj_s->uart == UART_8) {
+ __HAL_RCC_USART8_CLK_ENABLE();
+ }
+#endif
+
+#if defined(UART9_BASE)
+ if (obj_s->uart == UART_9) {
+ __HAL_RCC_UART9_CLK_ENABLE();
+ }
+#endif
+
+#if defined(UART10_BASE)
+ if (obj_s->uart == UART_10) {
+ __HAL_RCC_UART10_CLK_ENABLE();
+ }
+#endif
+
+#if defined(LPUART1_BASE)
+ if (obj_s->uart == LPUART_1) {
+ __HAL_RCC_LPUART1_CLK_ENABLE();
+ }
+#endif
+
+ // Assign serial object index
+ obj_s->index = get_uart_index(obj_s->uart);
+ MBED_ASSERT(obj_s->index >= 0);
+
+ // Configure UART pins
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ if (tx != NC) {
+ pin_mode(tx, PullUp);
+ }
+ if (rx != NC) {
+ pin_mode(rx, PullUp);
+ }
+
+ // Configure UART
+ obj_s->baudrate = 9600; // baudrate default value
+ if (stdio_config) {
+#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE
+ obj_s->baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json
+#endif /* MBED_CONF_PLATFORM_STDIO_BAUD_RATE */
+ } else {
+#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE
+ obj_s->baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json
+#endif /* MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE */
+ }
+ obj_s->databits = UART_WORDLENGTH_8B;
+ obj_s->stopbits = UART_STOPBITS_1;
+ obj_s->parity = UART_PARITY_NONE;
+
+#if DEVICE_SERIAL_FC
+ obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
+#endif
+
+ obj_s->pin_tx = tx;
+ obj_s->pin_rx = rx;
+
+ init_uart(obj); /* init_uart will be called again in serial_baud function, so don't worry if init_uart returns HAL_ERROR */
+
+ // For stdio management in platform/mbed_board.c and platform/mbed_retarget.cpp
+ if (stdio_config) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+
+ // Reset UART and disable clock
+#if defined(USART1_BASE)
+ if (obj_s->uart == UART_1) {
+ __HAL_RCC_USART1_FORCE_RESET();
+ __HAL_RCC_USART1_RELEASE_RESET();
+ __HAL_RCC_USART1_CLK_DISABLE();
+ }
+#endif
+
+#if defined(USART2_BASE)
+ if (obj_s->uart == UART_2) {
+ __HAL_RCC_USART2_FORCE_RESET();
+ __HAL_RCC_USART2_RELEASE_RESET();
+ __HAL_RCC_USART2_CLK_DISABLE();
+ }
+#endif
+
+#if defined(USART3_BASE)
+ if (obj_s->uart == UART_3) {
+ __HAL_RCC_USART3_FORCE_RESET();
+ __HAL_RCC_USART3_RELEASE_RESET();
+ __HAL_RCC_USART3_CLK_DISABLE();
+ }
+#endif
+
+#if defined(UART4_BASE)
+ if (obj_s->uart == UART_4) {
+ __HAL_RCC_UART4_FORCE_RESET();
+ __HAL_RCC_UART4_RELEASE_RESET();
+ __HAL_RCC_UART4_CLK_DISABLE();
+ }
+#endif
+
+#if defined(USART4_BASE)
+ if (obj_s->uart == UART_4) {
+ __HAL_RCC_USART4_FORCE_RESET();
+ __HAL_RCC_USART4_RELEASE_RESET();
+ __HAL_RCC_USART4_CLK_DISABLE();
+ }
+#endif
+
+#if defined(UART5_BASE)
+ if (obj_s->uart == UART_5) {
+ __HAL_RCC_UART5_FORCE_RESET();
+ __HAL_RCC_UART5_RELEASE_RESET();
+ __HAL_RCC_UART5_CLK_DISABLE();
+ }
+#endif
+
+#if defined(USART5_BASE)
+ if (obj_s->uart == UART_5) {
+ __HAL_RCC_USART5_FORCE_RESET();
+ __HAL_RCC_USART5_RELEASE_RESET();
+ __HAL_RCC_USART5_CLK_DISABLE();
+ }
+#endif
+
+#if defined(USART6_BASE)
+ if (obj_s->uart == UART_6) {
+ __HAL_RCC_USART6_FORCE_RESET();
+ __HAL_RCC_USART6_RELEASE_RESET();
+ __HAL_RCC_USART6_CLK_DISABLE();
+ }
+#endif
+
+#if defined(UART7_BASE)
+ if (obj_s->uart == UART_7) {
+ __HAL_RCC_UART7_FORCE_RESET();
+ __HAL_RCC_UART7_RELEASE_RESET();
+ __HAL_RCC_UART7_CLK_DISABLE();
+ }
+#endif
+
+#if defined(USART7_BASE)
+ if (obj_s->uart == UART_7) {
+ __HAL_RCC_USART7_FORCE_RESET();
+ __HAL_RCC_USART7_RELEASE_RESET();
+ __HAL_RCC_USART7_CLK_DISABLE();
+ }
+#endif
+
+#if defined(UART8_BASE)
+ if (obj_s->uart == UART_8) {
+ __HAL_RCC_UART8_FORCE_RESET();
+ __HAL_RCC_UART8_RELEASE_RESET();
+ __HAL_RCC_UART8_CLK_DISABLE();
+ }
+#endif
+
+#if defined(USART8_BASE)
+ if (obj_s->uart == UART_8) {
+ __HAL_RCC_USART8_FORCE_RESET();
+ __HAL_RCC_USART8_RELEASE_RESET();
+ __HAL_RCC_USART8_CLK_DISABLE();
+ }
+#endif
+
+#if defined(UART9_BASE)
+ if (obj_s->uart == UART_9) {
+ __HAL_RCC_UART9_FORCE_RESET();
+ __HAL_RCC_UART9_RELEASE_RESET();
+ __HAL_RCC_UART9_CLK_DISABLE();
+ }
+#endif
+
+#if defined(UART10_BASE)
+ if (obj_s->uart == UART_10) {
+ __HAL_RCC_UART10_FORCE_RESET();
+ __HAL_RCC_UART10_RELEASE_RESET();
+ __HAL_RCC_UART10_CLK_DISABLE();
+ }
+#endif
+
+#if defined(LPUART1_BASE)
+ if (obj_s->uart == LPUART_1) {
+ __HAL_RCC_LPUART1_FORCE_RESET();
+ __HAL_RCC_LPUART1_RELEASE_RESET();
+ __HAL_RCC_LPUART1_CLK_DISABLE();
+ }
+#endif
+
+ // Configure GPIOs
+ pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+ serial_irq_ids[obj_s->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+
+ obj_s->baudrate = baudrate;
+
+#if defined(LPUART1_BASE)
+ /* Note that LPUART clock source must be in the range [3 x baud rate, 4096 x baud rate], check Ref Manual */
+ if (obj_s->uart == LPUART_1) {
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+#if ((MBED_CONF_TARGET_LPUART_CLOCK_SOURCE) & USE_LPUART_CLK_LSE)
+ if (baudrate <= 9600) {
+ // Enable LSE in case it is not already done
+ if (!__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) {
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.HSIState = RCC_LSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+ }
+ // Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) {
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ if (init_uart(obj) == HAL_OK) {
+ return;
+ }
+ }
+ }
+#endif
+#if ((MBED_CONF_TARGET_LPUART_CLOCK_SOURCE) & USE_LPUART_CLK_PCLK1)
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ if (init_uart(obj) == HAL_OK) {
+ return;
+ }
+#endif
+#if ((MBED_CONF_TARGET_LPUART_CLOCK_SOURCE) & USE_LPUART_CLK_HSI)
+ // Enable HSI in case it is not already done
+ if (!__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY)) {
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+ }
+ // Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY)) {
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ if (init_uart(obj) == HAL_OK) {
+ return;
+ }
+ }
+#endif
+ // Last chance using SYSCLK
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ }
+#endif /* LPUART1_BASE */
+
+ if (init_uart(obj) != HAL_OK) {
+ debug("Cannot initialize UART with baud rate %u\n", baudrate);
+ }
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+
+ switch (parity) {
+ case ParityOdd:
+ obj_s->parity = UART_PARITY_ODD;
+ break;
+ case ParityEven:
+ obj_s->parity = UART_PARITY_EVEN;
+ break;
+ default: // ParityNone
+ case ParityForced0: // unsupported!
+ case ParityForced1: // unsupported!
+ obj_s->parity = UART_PARITY_NONE;
+ break;
+ }
+
+ switch (data_bits) {
+ case 7:
+ if (parity != UART_PARITY_NONE) {
+ obj_s->databits = UART_WORDLENGTH_8B;
+ } else {
+#if defined UART_WORDLENGTH_7B
+ obj_s->databits = UART_WORDLENGTH_7B;
+#else
+ error("7-bit data format without parity is not supported");
+#endif
+ }
+ break;
+ case 8:
+ if (parity != UART_PARITY_NONE) {
+ obj_s->databits = UART_WORDLENGTH_9B;
+ } else {
+ obj_s->databits = UART_WORDLENGTH_8B;
+ }
+ break;
+ case 9:
+ if (parity != UART_PARITY_NONE) {
+ error("Parity is not supported with 9-bit data format");
+ } else {
+ obj_s->databits = UART_WORDLENGTH_9B;
+ }
+ break;
+ default:
+ error("Only 7, 8 or 9-bit data formats are supported");
+ break;
+ }
+
+ if (stop_bits == 2) {
+ obj_s->stopbits = UART_STOPBITS_2;
+ } else {
+ obj_s->stopbits = UART_STOPBITS_1;
+ }
+
+ init_uart(obj);
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+
+int serial_readable(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+ /* To avoid a target blocking case, let's check for
+ * possible OVERRUN error and discard it
+ */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE)) {
+ __HAL_UART_CLEAR_OREFLAG(huart);
+ }
+ // Check if data is received
+ return (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) ? 1 : 0;
+}
+
+int serial_writable(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+
+ // Check if data is transmitted
+ return (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) ? 1 : 0;
+}
+
+void serial_pinout_tx(PinName tx)
+{
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_clear(serial_t *obj)
+{
+ (void)obj;
+}
+
+/******************************************************************************
+ * UTILITY FUNCTIONS
+ ******************************************************************************/
+
+HAL_StatusTypeDef init_uart(serial_t *obj)
+{
+ struct serial_s *obj_s = SERIAL_S(obj);
+ UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
+ huart->Instance = (USART_TypeDef *)(obj_s->uart);
+
+ huart->Init.BaudRate = obj_s->baudrate;
+ huart->Init.WordLength = obj_s->databits;
+ huart->Init.StopBits = obj_s->stopbits;
+ huart->Init.Parity = obj_s->parity;
+#if DEVICE_SERIAL_FC
+ huart->Init.HwFlowCtl = obj_s->hw_flow_ctl;
+#else
+ huart->Init.HwFlowCtl = UART_HWCONTROL_NONE;
+#endif
+ huart->Init.OverSampling = UART_OVERSAMPLING_16;
+ huart->TxXferCount = 0;
+ huart->TxXferSize = 0;
+ huart->RxXferCount = 0;
+ huart->RxXferSize = 0;
+
+ if (obj_s->pin_rx == NC) {
+ huart->Init.Mode = UART_MODE_TX;
+ } else if (obj_s->pin_tx == NC) {
+ huart->Init.Mode = UART_MODE_RX;
+ } else {
+ huart->Init.Mode = UART_MODE_TX_RX;
+ }
+
+#if defined(LPUART1_BASE)
+ if (huart->Instance == LPUART1) {
+ if (obj_s->baudrate <= 9600) {
+ HAL_UARTEx_EnableClockStopMode(huart);
+ HAL_UARTEx_EnableStopMode(huart);
+ } else {
+ HAL_UARTEx_DisableClockStopMode(huart);
+ HAL_UARTEx_DisableStopMode(huart);
+ }
+ }
+#endif
+
+ return HAL_UART_Init(huart);
+}
+
+int8_t get_uart_index(UARTName uart_name)
+{
+ uint8_t index = 0;
+
+#if defined(USART1_BASE)
+ if (uart_name == UART_1) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(USART2_BASE)
+ if (uart_name == UART_2) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(USART3_BASE)
+ if (uart_name == UART_3) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(UART4_BASE)
+ if (uart_name == UART_4) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(USART4_BASE)
+ if (uart_name == UART_4) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(UART5_BASE)
+ if (uart_name == UART_5) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(USART5_BASE)
+ if (uart_name == UART_5) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(USART6_BASE)
+ if (uart_name == UART_6) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(UART7_BASE)
+ if (uart_name == UART_7) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(USART7_BASE)
+ if (uart_name == UART_7) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(UART8_BASE)
+ if (uart_name == UART_8) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(USART8_BASE)
+ if (uart_name == UART_8) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(UART9_BASE)
+ if (uart_name == UART_9) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(UART10_BASE)
+ if (uart_name == UART_10) {
+ return index;
+ }
+ index++;
+#endif
+
+#if defined(LPUART1_BASE)
+ if (uart_name == LPUART_1) {
+ return index;
+ }
+ index++;
+#endif
+
+ return -1;
+}
+
+/* Function to protect deep sleep while a seral Tx is ongoing on not complete
+ * yet. Returns 1 if there is at least 1 serial instance with ongoing ransfer
+ * 0 otherwise.
+ */
+int serial_is_tx_ongoing(void) {
+ int TxOngoing = 0;
+
+#if defined(USART1_BASE)
+ if (LL_USART_IsEnabled(USART1) && !LL_USART_IsActiveFlag_TC(USART1)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(USART2_BASE)
+ if (LL_USART_IsEnabled(USART2) && !LL_USART_IsActiveFlag_TC(USART2)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(USART3_BASE)
+ if (LL_USART_IsEnabled(USART3) && !LL_USART_IsActiveFlag_TC(USART3)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(UART4_BASE)
+ if (LL_USART_IsEnabled(UART4) && !LL_USART_IsActiveFlag_TC(UART4)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(USART4_BASE)
+ if (LL_USART_IsEnabled(USART4) && !LL_USART_IsActiveFlag_TC(USART4)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(UART5_BASE)
+ if (LL_USART_IsEnabled(UART5) && !LL_USART_IsActiveFlag_TC(UART5)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(USART5_BASE)
+ if (LL_USART_IsEnabled(USART5) && !LL_USART_IsActiveFlag_TC(USART5)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(USART6_BASE)
+ if (LL_USART_IsEnabled(USART6) && !LL_USART_IsActiveFlag_TC(USART6)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(UART7_BASE)
+ if (LL_USART_IsEnabled(UART7) && !LL_USART_IsActiveFlag_TC(UART7)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(USART7_BASE)
+ if (LL_USART_IsEnabled(USART7) && !LL_USART_IsActiveFlag_TC(USART7)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(UART8_BASE)
+ if (LL_USART_IsEnabled(UART8) && !LL_USART_IsActiveFlag_TC(UART8)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(USART8_BASE)
+ if (LL_USART_IsEnabled(USART8) && !LL_USART_IsActiveFlag_TC(USART8)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(UART9_BASE)
+ if (LL_USART_IsEnabled(UART9) && !LL_USART_IsActiveFlag_TC(UART9)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(UART10_BASE)
+ if (LL_USART_IsEnabled(UART10) && !LL_USART_IsActiveFlag_TC(UART10)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+#if defined(LPUART1_BASE)
+ if (LL_USART_IsEnabled(LPUART1) && !LL_USART_IsActiveFlag_TC(LPUART1)) {
+ TxOngoing |= 1;
+ }
+#endif
+
+ /* If Tx is ongoing, then transfer is */
+ return TxOngoing;
+}
+
+#endif /* DEVICE_SERIAL */
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/serial_api_hal.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/serial_api_hal.h Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+*******************************************************************************
+* Copyright (c) 2016, STMicroelectronics
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 3. Neither the name of STMicroelectronics nor the names of its contributors
+* may be used to endorse or promote products derived from this software
+* without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+*/
+
+#ifndef MBED_SERIAL_API_HAL_H
+#define MBED_SERIAL_API_HAL_H
+
+#include "serial_api.h"
+#include <string.h>
+#include "mbed_assert.h"
+#include "mbed_debug.h"
+#include "mbed_error.h"
+
+#include "PeripheralPins.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Extend serial_api.h
+ */
+
+#if DEVICE_SERIAL_ASYNCH
+#define SERIAL_S(obj) (&((obj)->serial))
+#else
+#define SERIAL_S(obj) (obj)
+#endif
+
+
+/** Initialize and configure the UART peripheral
+ *
+ * @param obj The serial object containing the configuration
+ */
+HAL_StatusTypeDef init_uart(serial_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/sleep.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/sleep.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,221 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#if DEVICE_SLEEP
+
+#include "sleep_api.h"
+#include "us_ticker_api.h"
+#include "us_ticker_data.h"
+#include "mbed_critical.h"
+#include "mbed_error.h"
+
+extern void save_timer_ctx(void);
+extern void restore_timer_ctx(void);
+
+/* Wait loop - assuming tick is 1 us */
+static void wait_loop(uint32_t timeout)
+{
+ uint32_t t1, t2, elapsed = 0;
+ t1 = us_ticker_read();
+ do {
+ t2 = us_ticker_read();
+ elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t)t2 + 0xFFFFFFFF - t1 + 1);
+ } while (elapsed < timeout);
+ return;
+}
+
+
+// On L4 platforms we've seen unstable PLL CLK configuraiton
+// when DEEP SLEEP exits just few µs after being entered
+// So we need to force MSI usage before setting clocks again
+static void ForcePeriphOutofDeepSleep(void)
+{
+ uint32_t pFLatency = 0;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+#if (TARGET_STM32L4 || TARGET_STM32L1) /* MSI used for L4 */
+ /* Get the Clocks configuration according to the internal RCC registers */
+ HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
+
+ // Select HSI ss system clock source as a first step
+#ifdef RCC_CLOCKTYPE_PCLK2
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+#else
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
+ | RCC_CLOCKTYPE_PCLK1);
+#endif
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
+ error("clock issue\r\n");
+ }
+#else /* HSI used on others */
+ /* Get the Clocks configuration according to the internal RCC registers */
+ HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
+
+ /**Initializes the CPU, AHB and APB busses clocks
+ */
+#ifdef RCC_CLOCKTYPE_PCLK2
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+#else
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1);
+#endif
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
+ error("clock issue");
+ }
+#endif // TARGET_STM32L4
+}
+
+static void ForceOscOutofDeepSleep(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+ /* Enable Power Control clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Get the Oscillators configuration according to the internal RCC registers */
+ HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
+
+#if (TARGET_STM32L4 || TARGET_STM32L1) /* MSI used for L4 */
+ /**Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4; // Intermediate freq, 1MHz range
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("clock issue\r\n");
+ }
+#else /* HSI used on others */
+ /**Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("clock issue");
+ }
+#endif // TARGET_STM32L4
+}
+
+/* The content of this function has been split into 2 separate functions
+ so that the involved structures are not allocated on the stack in parallel.
+ This will reduce the maximum stack usage in case on non-optimized / debug
+ compilers settings */
+static void ForceClockOutofDeepSleep(void)
+{
+ ForceOscOutofDeepSleep();
+ ForcePeriphOutofDeepSleep();
+}
+
+void hal_sleep(void)
+{
+ // Disable IRQs
+ core_util_critical_section_enter();
+
+ // Request to enter SLEEP mode
+ HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+
+ // Enable IRQs
+ core_util_critical_section_exit();
+}
+
+extern int serial_is_tx_ongoing(void);
+
+void hal_deepsleep(void)
+{
+ /* WORKAROUND:
+ * MBED serial driver does not handle deepsleep lock
+ * to prevent entering deepsleep until HW serial FIFO is empty.
+ * This is tracked in mbed issue 4408.
+ * For now, we're checking all Serial HW FIFO. If any transfer is ongoing
+ * we're not entering deep sleep and returning immediately. */
+ if(serial_is_tx_ongoing()) {
+ return;
+ }
+
+ // Disable IRQs
+ core_util_critical_section_enter();
+
+ save_timer_ctx();
+
+ // Request to enter STOP mode with regulator in low power mode
+#if TARGET_STM32L4
+ int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED();
+ int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR;
+
+ if (!pwrClockEnabled) {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ }
+ if (lowPowerModeEnabled) {
+ HAL_PWREx_DisableLowPowerRunMode();
+ }
+
+ HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
+
+ if (lowPowerModeEnabled) {
+ HAL_PWREx_EnableLowPowerRunMode();
+ }
+ if (!pwrClockEnabled) {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
+#else /* TARGET_STM32L4 */
+ HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+#endif /* TARGET_STM32L4 */
+
+ // Verify Clock Out of Deep Sleep
+ ForceClockOutofDeepSleep();
+
+ // After wake-up from STOP reconfigure the PLL
+ SetSysClock();
+
+ /* Wait for clock to be stabilized.
+ * TO DO: a better way of doing this, would be to rely on
+ * HW Flag. At least this ensures proper operation out of
+ * deep sleep */
+ wait_loop(500);
+
+ restore_timer_ctx();
+
+ // Enable IRQs
+ core_util_critical_section_exit();
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/stm32_assert.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-dev-master/targets/TARGET_STM/stm32_assert.h Wed Sep 16 01:11:49 2020 +0000 @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef STM32_ASSERT_H +#define STM32_ASSERT_H +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#include "mbed_assert.h" +#define assert_param(expr) MBED_ASSERT(expr) + +#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/stm_spi_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/stm_spi_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,689 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "mbed_debug.h"
+#include "spi_api.h"
+
+#if DEVICE_SPI
+#include <stdbool.h>
+#include <math.h>
+#include <string.h>
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "spi_device.h"
+
+#if DEVICE_SPI_ASYNCH
+#define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
+#else
+#define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
+#endif
+
+#if DEVICE_SPI_ASYNCH
+#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
+#else
+#define SPI_S(obj) (( struct spi_s *)(obj))
+#endif
+
+#ifndef DEBUG_STDIO
+# define DEBUG_STDIO 0
+#endif
+
+#if DEBUG_STDIO
+# include <stdio.h>
+# define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
+#else
+# define DEBUG_PRINTF(...) {}
+#endif
+
+/* Consider 10ms as the default timeout for sending/receving 1 byte */
+#define TIMEOUT_1_BYTE 10
+
+#if defined(SPI_FLAG_FRLVL) // STM32F0 STM32F3 STM32F7 STM32L4
+extern HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+#endif
+
+void init_spi(spi_t *obj)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ __HAL_SPI_DISABLE(handle);
+
+ DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
+ if (HAL_SPI_Init(handle) != HAL_OK) {
+ error("Cannot initialize SPI");
+ }
+
+ /* In case of standard 4 wires SPI,PI can be kept enabled all time
+ * and SCK will only be generated during the write operations. But in case
+ * of 3 wires, it should be only enabled during rd/wr unitary operations,
+ * which is handled inside STM32 HAL layer.
+ */
+ if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
+ __HAL_SPI_ENABLE(handle);
+ }
+}
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ // Determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+ spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+ MBED_ASSERT(spiobj->spi != (SPIName)NC);
+
+#if defined SPI1_BASE
+ // Enable SPI clock
+ if (spiobj->spi == SPI_1) {
+ __HAL_RCC_SPI1_CLK_ENABLE();
+ spiobj->spiIRQ = SPI1_IRQn;
+ }
+#endif
+
+#if defined SPI2_BASE
+ if (spiobj->spi == SPI_2) {
+ __HAL_RCC_SPI2_CLK_ENABLE();
+ spiobj->spiIRQ = SPI2_IRQn;
+ }
+#endif
+
+#if defined SPI3_BASE
+ if (spiobj->spi == SPI_3) {
+ __HAL_RCC_SPI3_CLK_ENABLE();
+ spiobj->spiIRQ = SPI3_IRQn;
+ }
+#endif
+
+#if defined SPI4_BASE
+ if (spiobj->spi == SPI_4) {
+ __HAL_RCC_SPI4_CLK_ENABLE();
+ spiobj->spiIRQ = SPI4_IRQn;
+ }
+#endif
+
+#if defined SPI5_BASE
+ if (spiobj->spi == SPI_5) {
+ __HAL_RCC_SPI5_CLK_ENABLE();
+ spiobj->spiIRQ = SPI5_IRQn;
+ }
+#endif
+
+#if defined SPI6_BASE
+ if (spiobj->spi == SPI_6) {
+ __HAL_RCC_SPI6_CLK_ENABLE();
+ spiobj->spiIRQ = SPI6_IRQn;
+ }
+#endif
+
+ // Configure the SPI pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ spiobj->pin_miso = miso;
+ spiobj->pin_mosi = mosi;
+ spiobj->pin_sclk = sclk;
+ spiobj->pin_ssel = ssel;
+ if (ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ handle->Init.NSS = SPI_NSS_HARD_OUTPUT;
+ } else {
+ handle->Init.NSS = SPI_NSS_SOFT;
+ }
+
+ /* Fill default value */
+ handle->Instance = SPI_INST(obj);
+ handle->Init.Mode = SPI_MODE_MASTER;
+ handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
+
+ if (miso != NC) {
+ handle->Init.Direction = SPI_DIRECTION_2LINES;
+ } else {
+ handle->Init.Direction = SPI_DIRECTION_1LINE;
+ }
+
+ handle->Init.CLKPhase = SPI_PHASE_1EDGE;
+ handle->Init.CLKPolarity = SPI_POLARITY_LOW;
+ handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+ handle->Init.CRCPolynomial = 7;
+ handle->Init.DataSize = SPI_DATASIZE_8BIT;
+ handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
+ handle->Init.TIMode = SPI_TIMODE_DISABLE;
+
+ init_spi(obj);
+}
+
+void spi_free(spi_t *obj)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ DEBUG_PRINTF("spi_free\r\n");
+
+ __HAL_SPI_DISABLE(handle);
+ HAL_SPI_DeInit(handle);
+
+#if defined SPI1_BASE
+ // Reset SPI and disable clock
+ if (spiobj->spi == SPI_1) {
+ __HAL_RCC_SPI1_FORCE_RESET();
+ __HAL_RCC_SPI1_RELEASE_RESET();
+ __HAL_RCC_SPI1_CLK_DISABLE();
+ }
+#endif
+#if defined SPI2_BASE
+ if (spiobj->spi == SPI_2) {
+ __HAL_RCC_SPI2_FORCE_RESET();
+ __HAL_RCC_SPI2_RELEASE_RESET();
+ __HAL_RCC_SPI2_CLK_DISABLE();
+ }
+#endif
+
+#if defined SPI3_BASE
+ if (spiobj->spi == SPI_3) {
+ __HAL_RCC_SPI3_FORCE_RESET();
+ __HAL_RCC_SPI3_RELEASE_RESET();
+ __HAL_RCC_SPI3_CLK_DISABLE();
+ }
+#endif
+
+#if defined SPI4_BASE
+ if (spiobj->spi == SPI_4) {
+ __HAL_RCC_SPI4_FORCE_RESET();
+ __HAL_RCC_SPI4_RELEASE_RESET();
+ __HAL_RCC_SPI4_CLK_DISABLE();
+ }
+#endif
+
+#if defined SPI5_BASE
+ if (spiobj->spi == SPI_5) {
+ __HAL_RCC_SPI5_FORCE_RESET();
+ __HAL_RCC_SPI5_RELEASE_RESET();
+ __HAL_RCC_SPI5_CLK_DISABLE();
+ }
+#endif
+
+#if defined SPI6_BASE
+ if (spiobj->spi == SPI_6) {
+ __HAL_RCC_SPI6_FORCE_RESET();
+ __HAL_RCC_SPI6_RELEASE_RESET();
+ __HAL_RCC_SPI6_CLK_DISABLE();
+ }
+#endif
+
+ // Configure GPIOs
+ pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ if (handle->Init.NSS != SPI_NSS_SOFT) {
+ pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ }
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
+
+ // Save new values
+ handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
+
+ switch (mode) {
+ case 0:
+ handle->Init.CLKPolarity = SPI_POLARITY_LOW;
+ handle->Init.CLKPhase = SPI_PHASE_1EDGE;
+ break;
+ case 1:
+ handle->Init.CLKPolarity = SPI_POLARITY_LOW;
+ handle->Init.CLKPhase = SPI_PHASE_2EDGE;
+ break;
+ case 2:
+ handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
+ handle->Init.CLKPhase = SPI_PHASE_1EDGE;
+ break;
+ default:
+ handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
+ handle->Init.CLKPhase = SPI_PHASE_2EDGE;
+ break;
+ }
+
+ if (handle->Init.NSS != SPI_NSS_SOFT) {
+ handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
+ }
+
+ handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
+
+ if (slave && (handle->Init.Direction == SPI_DIRECTION_1LINE)) {
+ /* SPI slave implemtation in MBED does not support the 3 wires SPI.
+ * (e.g. when MISO is not connected). So we're forcing slave in
+ * 2LINES mode. As MISO is not connected, slave will only read
+ * from master, and cannot write to it. Inform user.
+ */
+ debug("3 wires SPI slave not supported - slave will only read\r\n");
+ handle->Init.Direction = SPI_DIRECTION_2LINES;
+ }
+
+ init_spi(obj);
+}
+
+/*
+ * Only the IP clock input is family dependant so it computed
+ * separately in spi_get_clock_freq
+ */
+extern int spi_get_clock_freq(spi_t *obj);
+
+static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
+ SPI_BAUDRATEPRESCALER_4,
+ SPI_BAUDRATEPRESCALER_8,
+ SPI_BAUDRATEPRESCALER_16,
+ SPI_BAUDRATEPRESCALER_32,
+ SPI_BAUDRATEPRESCALER_64,
+ SPI_BAUDRATEPRESCALER_128,
+ SPI_BAUDRATEPRESCALER_256
+ };
+
+void spi_frequency(spi_t *obj, int hz)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ int spi_hz = 0;
+ uint8_t prescaler_rank = 0;
+ uint8_t last_index = (sizeof(baudrate_prescaler_table) / sizeof(baudrate_prescaler_table[0])) - 1;
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */
+ spi_hz = spi_get_clock_freq(obj) / 2;
+
+ /* Define pre-scaler in order to get highest available frequency below requested frequency */
+ while ((spi_hz > hz) && (prescaler_rank < last_index)) {
+ spi_hz = spi_hz / 2;
+ prescaler_rank++;
+ }
+
+ /* Use the best fit pre-scaler */
+ handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank];
+
+ /* In case maximum pre-scaler still gives too high freq, raise an error */
+ if (spi_hz > hz) {
+ DEBUG_PRINTF("WARNING: lowest SPI freq (%d) higher than requested (%d)\r\n", spi_hz, hz);
+ }
+
+ DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz);
+
+ init_spi(obj);
+}
+
+static inline int ssp_readable(spi_t *obj)
+{
+ int status;
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ // Check if data is received
+ status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
+ return status;
+}
+
+static inline int ssp_writeable(spi_t *obj)
+{
+ int status;
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ // Check if data is transmitted
+ status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
+ return status;
+}
+
+static inline int ssp_busy(spi_t *obj)
+{
+ int status;
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+ status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
+ return status;
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ if (handle->Init.Direction == SPI_DIRECTION_1LINE) {
+ return HAL_SPI_Transmit(handle, (uint8_t *)&value, 1, TIMEOUT_1_BYTE);
+ }
+
+#if defined(LL_SPI_RX_FIFO_TH_HALF)
+ /* Configure the default data size */
+ if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
+ LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_HALF);
+ } else {
+ LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_QUARTER);
+ }
+#endif
+
+ /* Here we're using LL which means direct registers access
+ * There is no error management, so we may end up looping
+ * infinitely here in case of faulty device for insatnce,
+ * but this will increase performances significantly
+ */
+
+ /* Wait TXE flag to transmit data */
+ while (!LL_SPI_IsActiveFlag_TXE(SPI_INST(obj)));
+
+ if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
+ LL_SPI_TransmitData16(SPI_INST(obj), value);
+ } else {
+ LL_SPI_TransmitData8(SPI_INST(obj), (uint8_t) value);
+ }
+
+ /* Then wait RXE flag before reading */
+ while (!LL_SPI_IsActiveFlag_RXNE(SPI_INST(obj)));
+
+ if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
+ return LL_SPI_ReceiveData16(SPI_INST(obj));
+ } else {
+ return LL_SPI_ReceiveData8(SPI_INST(obj));
+ }
+}
+
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+ char *rx_buffer, int rx_length, char write_fill)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+ int total = (tx_length > rx_length) ? tx_length : rx_length;
+ int i = 0;
+ if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
+ for (i = 0; i < total; i++) {
+ char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+ char in = spi_master_write(obj, out);
+ if (i < rx_length) {
+ rx_buffer[i] = in;
+ }
+ }
+ } else {
+ /* In case of 1 WIRE only, first handle TX, then Rx */
+ if (tx_length != 0) {
+ if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t *)tx_buffer, tx_length, tx_length * TIMEOUT_1_BYTE)) {
+ /* report an error */
+ total = 0;
+ }
+ }
+ if (rx_length != 0) {
+ if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t *)rx_buffer, rx_length, rx_length * TIMEOUT_1_BYTE)) {
+ /* report an error */
+ total = 0;
+ }
+ }
+ }
+
+ return total;
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+ return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
+};
+
+int spi_slave_read(spi_t *obj)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+ while (!ssp_readable(obj));
+ if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
+ return LL_SPI_ReceiveData16(SPI_INST(obj));
+ } else {
+ return LL_SPI_ReceiveData8(SPI_INST(obj));
+ }
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+ SPI_TypeDef *spi = SPI_INST(obj);
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+ while (!ssp_writeable(obj));
+ if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
+ // Force 8-bit access to the data register
+ uint8_t *p_spi_dr = 0;
+ p_spi_dr = (uint8_t *) & (spi->DR);
+ *p_spi_dr = (uint8_t)value;
+ } else { // SPI_DATASIZE_16BIT
+ spi->DR = (uint16_t)value;
+ }
+}
+
+int spi_busy(spi_t *obj)
+{
+ return ssp_busy(obj);
+}
+
+#ifdef DEVICE_SPI_ASYNCH
+typedef enum {
+ SPI_TRANSFER_TYPE_NONE = 0,
+ SPI_TRANSFER_TYPE_TX = 1,
+ SPI_TRANSFER_TYPE_RX = 2,
+ SPI_TRANSFER_TYPE_TXRX = 3,
+} transfer_type_t;
+
+
+/// @returns the number of bytes transferred, or `0` if nothing transferred
+static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+ bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
+ // the HAL expects number of transfers instead of number of bytes
+ // so for 16 bit transfer width the count needs to be halved
+ size_t words;
+
+ DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
+
+ obj->spi.transfer_type = transfer_type;
+
+ if (is16bit) {
+ words = length / 2;
+ } else {
+ words = length;
+ }
+
+ // enable the interrupt
+ IRQn_Type irq_n = spiobj->spiIRQ;
+ NVIC_DisableIRQ(irq_n);
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_SetPriority(irq_n, 1);
+ NVIC_EnableIRQ(irq_n);
+
+ // flush FIFO
+#if defined(SPI_FLAG_FRLVL) // STM32F0 STM32F3 STM32F7 STM32L4
+ HAL_SPIEx_FlushRxFifo(handle);
+#endif
+
+ // enable the right hal transfer
+ int rc = 0;
+ switch (transfer_type) {
+ case SPI_TRANSFER_TYPE_TXRX:
+ rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t *)tx, (uint8_t *)rx, words);
+ break;
+ case SPI_TRANSFER_TYPE_TX:
+ rc = HAL_SPI_Transmit_IT(handle, (uint8_t *)tx, words);
+ break;
+ case SPI_TRANSFER_TYPE_RX:
+ // the receive function also "transmits" the receive buffer so in order
+ // to guarantee that 0xff is on the line, we explicitly memset it here
+ memset(rx, SPI_FILL_WORD, length);
+ rc = HAL_SPI_Receive_IT(handle, (uint8_t *)rx, words);
+ break;
+ default:
+ length = 0;
+ }
+
+ if (rc) {
+ DEBUG_PRINTF("SPI: RC=%u\n", rc);
+ length = 0;
+ }
+
+ return length;
+}
+
+// asynchronous API
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ // TODO: DMA usage is currently ignored
+ (void) hint;
+
+ // check which use-case we have
+ bool use_tx = (tx != NULL && tx_length > 0);
+ bool use_rx = (rx != NULL && rx_length > 0);
+ bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
+
+ // don't do anything, if the buffers aren't valid
+ if (!use_tx && !use_rx) {
+ return;
+ }
+
+ // copy the buffers to the SPI object
+ obj->tx_buff.buffer = (void *) tx;
+ obj->tx_buff.length = tx_length;
+ obj->tx_buff.pos = 0;
+ obj->tx_buff.width = is16bit ? 16 : 8;
+
+ obj->rx_buff.buffer = rx;
+ obj->rx_buff.length = rx_length;
+ obj->rx_buff.pos = 0;
+ obj->rx_buff.width = obj->tx_buff.width;
+
+ obj->spi.event = event;
+
+ DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
+
+ // register the thunking handler
+ IRQn_Type irq_n = spiobj->spiIRQ;
+ NVIC_SetVector(irq_n, (uint32_t)handler);
+
+ // enable the right hal transfer
+ if (use_tx && use_rx) {
+ // we cannot manage different rx / tx sizes, let's use smaller one
+ size_t size = (tx_length < rx_length) ? tx_length : rx_length;
+ if (tx_length != rx_length) {
+ DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
+ obj->tx_buff.length = size;
+ obj->rx_buff.length = size;
+ }
+ spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
+ } else if (use_tx) {
+ spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
+ } else if (use_rx) {
+ spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
+ }
+}
+
+inline uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+ int event = 0;
+
+ // call the CubeF4 handler, this will update the handle
+ HAL_SPI_IRQHandler(&obj->spi.handle);
+
+ if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
+ // When HAL SPI is back to READY state, check if there was an error
+ int error = obj->spi.handle.ErrorCode;
+ if (error != HAL_SPI_ERROR_NONE) {
+ // something went wrong and the transfer has definitely completed
+ event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+
+ if (error & HAL_SPI_ERROR_OVR) {
+ // buffer overrun
+ event |= SPI_EVENT_RX_OVERFLOW;
+ }
+ } else {
+ // else we're done
+ event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+ }
+ // enable the interrupt
+ NVIC_DisableIRQ(obj->spi.spiIRQ);
+ NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
+ }
+
+
+ return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+ HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
+
+ switch (state) {
+ case HAL_SPI_STATE_RESET:
+ case HAL_SPI_STATE_READY:
+ case HAL_SPI_STATE_ERROR:
+ return 0;
+ default:
+ return 1;
+ }
+}
+
+void spi_abort_asynch(spi_t *obj)
+{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+ // disable interrupt
+ IRQn_Type irq_n = spiobj->spiIRQ;
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_DisableIRQ(irq_n);
+
+ // clean-up
+ __HAL_SPI_DISABLE(handle);
+ HAL_SPI_DeInit(handle);
+ HAL_SPI_Init(handle);
+ __HAL_SPI_ENABLE(handle);
+}
+
+#endif //DEVICE_SPI_ASYNCH
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/trng_api.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/trng_api.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,100 @@
+/*
+ * Hardware entropy collector for the STM32 families
+ *
+ * Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#if defined(DEVICE_TRNG)
+
+#include <stdlib.h>
+#include "cmsis.h"
+#include "trng_api.h"
+#include "mbed_error.h"
+#include "mbed_critical.h"
+
+static uint8_t users = 0;
+
+void trng_init(trng_t *obj)
+{
+ uint32_t dummy;
+
+ /* We're only supporting a single user of RNG */
+ if (core_util_atomic_incr_u8(&users, 1) > 1) {
+ error("Only 1 RNG instance supported\r\n");
+ }
+
+#if defined(TARGET_STM32L4)
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /*Select PLLQ output as RNG clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
+ PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+#endif
+
+ /* RNG Peripheral clock enable */
+ __HAL_RCC_RNG_CLK_ENABLE();
+
+ /* Initialize RNG instance */
+ obj->handle.Instance = RNG;
+ obj->handle.State = HAL_RNG_STATE_RESET;
+ obj->handle.Lock = HAL_UNLOCKED;
+
+ HAL_RNG_Init(&obj->handle);
+
+ /* first random number generated after setting the RNGEN bit should not be used */
+ HAL_RNG_GenerateRandomNumber(&obj->handle, &dummy);
+}
+
+void trng_free(trng_t *obj)
+{
+ /*Disable the RNG peripheral */
+ HAL_RNG_DeInit(&obj->handle);
+ /* RNG Peripheral clock disable - assume we're the only users of RNG */
+ __HAL_RCC_RNG_CLK_DISABLE();
+
+ users = 0;
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+ int ret = 0;
+ volatile uint8_t random[4];
+ *output_length = 0;
+
+ /* Get Random byte */
+ while ((*output_length < length) && (ret == 0)) {
+ if (HAL_RNG_GenerateRandomNumber(&obj->handle, (uint32_t *)random) != HAL_OK) {
+ ret = -1;
+ } else {
+ for (uint8_t i = 0; (i < 4) && (*output_length < length) ; i++) {
+ *output++ = random[i];
+ *output_length += 1;
+ random[i] = 0;
+ }
+ }
+ }
+
+ /* Just be extra sure that we didn't do it wrong */
+ if ((__HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS))) != 0) {
+ ret = -1;
+ }
+
+ return (ret);
+}
+
+#endif
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/TARGET_STM/us_ticker.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/us_ticker.c Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,258 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+#include "us_ticker_data.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+
+uint32_t timer_cnt_reg;
+uint32_t timer_ccr1_reg;
+uint32_t timer_dier_reg;
+
+const ticker_info_t *us_ticker_get_info()
+{
+ static const ticker_info_t info = {
+ 1000000,
+ TIM_MST_BIT_WIDTH
+ };
+ return &info;
+}
+
+void us_ticker_irq_handler(void);
+
+// ************************************ 16-bit timer ************************************
+#if TIM_MST_BIT_WIDTH == 16
+
+extern uint32_t prev_time;
+extern uint32_t elapsed_time;
+
+#if defined(TARGET_STM32F0)
+void timer_update_irq_handler(void)
+{
+#else
+void timer_irq_handler(void)
+{
+#endif
+ TimMasterHandle.Instance = TIM_MST;
+
+#if defined(TARGET_STM32F0)
+} // end timer_update_irq_handler function
+
+void timer_oc_irq_handler(void)
+{
+ TimMasterHandle.Instance = TIM_MST;
+#endif
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+ if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC1) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+ us_ticker_irq_handler();
+ }
+ }
+}
+
+void init_16bit_timer(void)
+{
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+#if !defined(TARGET_STM32L0) && !defined(TARGET_STM32L1)
+ TimMasterHandle.Init.RepetitionCounter = 0;
+#endif
+#ifdef TIM_AUTORELOAD_PRELOAD_DISABLE
+ TimMasterHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+#endif
+ HAL_TIM_Base_Init(&TimMasterHandle);
+
+ // Configure output compare channel 1 for mbed timeout (enabled later when used)
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Output compare channel 1 interrupt for mbed timeout
+#if defined(TARGET_STM32F0)
+ NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_UP_IRQ);
+ NVIC_SetPriority(TIM_MST_UP_IRQ, 0);
+ NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_OC_IRQ);
+ NVIC_SetPriority(TIM_MST_OC_IRQ, 1);
+#else
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+#endif
+
+ // Enable timer
+ HAL_TIM_Base_Start(&TimMasterHandle);
+
+ // Freeze timer on stop/breakpoint
+ // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example
+#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE)
+ TIM_MST_DBGMCU_FREEZE;
+#endif
+
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+
+ // Used by HAL_GetTick()
+ prev_time = 0;
+ elapsed_time = 0;
+}
+
+// ************************************ 32-bit timer ************************************
+#else
+
+void timer_irq_handler(void)
+{
+ TimMasterHandle.Instance = TIM_MST;
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+ if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC1) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+ us_ticker_irq_handler();
+ }
+ }
+}
+
+void init_32bit_timer(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ uint32_t PclkFreq;
+
+ // Get clock configuration
+ // Note: PclkFreq contains here the Latency (not used after)
+ HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq);
+
+ // Get timer clock value
+#if TIM_MST_PCLK == 1
+ PclkFreq = HAL_RCC_GetPCLK1Freq();
+#else
+ PclkFreq = HAL_RCC_GetPCLK2Freq();
+#endif
+
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+
+ // TIMxCLK = PCLKx when the APB prescaler = 1 else TIMxCLK = 2 * PCLKx
+#if TIM_MST_PCLK == 1
+ if (RCC_ClkInitStruct.APB1CLKDivider == RCC_HCLK_DIV1) {
+#else
+ if (RCC_ClkInitStruct.APB2CLKDivider == RCC_HCLK_DIV1) {
+#endif
+ TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq) / 1000000) - 1; // 1 us tick
+ } else {
+ TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq * 2) / 1000000) - 1; // 1 us tick
+ }
+
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+#if !TARGET_STM32L1
+ TimMasterHandle.Init.RepetitionCounter = 0;
+#endif
+#ifdef TIM_AUTORELOAD_PRELOAD_DISABLE
+ TimMasterHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+#endif
+ HAL_TIM_OC_Init(&TimMasterHandle);
+
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Channel 1 for mbed timeout
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Freeze timer on stop/breakpoint
+ // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example
+#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE)
+ TIM_MST_DBGMCU_FREEZE;
+#endif
+
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+#endif // 16-bit/32-bit timer
+
+void us_ticker_init(void)
+{
+ // Timer is already initialized in HAL_InitTick()
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+uint32_t us_ticker_read()
+{
+ return TIM_MST->CNT;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ // NOTE: This function must be called with interrupts disabled to keep our
+ // timer interrupt setup atomic
+ // Set new output compare value
+ __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp);
+ // Ensure the compare event starts clear
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+ // Enable IT
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_fire_interrupt(void)
+{
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+ LL_TIM_GenerateEvent_CC1(TimMasterHandle.Instance);
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+/* NOTE: must be called with interrupts disabled! */
+void us_ticker_clear_interrupt(void)
+{
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+}
+
+void save_timer_ctx(void)
+{
+ timer_cnt_reg = __HAL_TIM_GET_COUNTER(&TimMasterHandle);
+ timer_ccr1_reg = __HAL_TIM_GET_COMPARE(&TimMasterHandle, TIM_CHANNEL_1);
+ timer_dier_reg = TIM_MST->DIER;
+}
+
+void restore_timer_ctx(void)
+{
+ __HAL_TIM_SET_COUNTER(&TimMasterHandle, timer_cnt_reg);
+ __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_1, timer_ccr1_reg);
+ TIM_MST->DIER = timer_dier_reg;
+}
diff -r 000000000000 -r bb348c97df44 mbed-dev-master/targets/targets.json
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/targets.json Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,4479 @@
+{
+ "Target": {
+ "core": null,
+ "default_toolchain": "ARM",
+ "supported_toolchains": null,
+ "extra_labels": [],
+ "is_disk_virtual": false,
+ "macros": [],
+ "device_has": [],
+ "features": [],
+ "detect_code": [],
+ "public": false,
+ "default_lib": "std",
+ "bootloader_supported": false,
+ "config": {
+ "console-uart-flow-control": {
+ "help": "Console hardware flow control. Options: null, RTS, CTS, RTSCTS.",
+ "value": null
+ },
+ "network-default-interface-type": {
+ "help": "Default network interface type. Typical options: null, ETHERNET, WIFI, CELLULAR, MESH",
+ "value": null
+ }
+ }
+ },
+ "CM4_UARM": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "default_toolchain": "uARM",
+ "public": false,
+ "supported_toolchains": ["uARM"],
+ "default_lib": "small"
+ },
+ "CM4_ARM": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "public": false,
+ "supported_toolchains": ["ARM"]
+ },
+ "CM4F_UARM": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "default_toolchain": "uARM",
+ "public": false,
+ "supported_toolchains": ["uARM"],
+ "default_lib": "small"
+ },
+ "CM4F_ARM": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "public": false,
+ "supported_toolchains": ["ARM"]
+ },
+ "LPCTarget": {
+ "inherits": ["Target"],
+ "post_binary_hook": {"function": "LPCTargetCode.lpc_patch"},
+ "public": false
+ },
+ "LPC11C24": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"],
+ "OUTPUT_EXT": "hex",
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_name": "LPC11C24FBD48/301"
+ },
+ "LPC1114": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC1114FN28/102"
+ },
+ "LPC11U24": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "LPC11U24_401"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "detect_code": ["1040"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U24FBD48/401"
+ },
+ "OC_MBUINO": {
+ "inherits": ["LPC11U24"],
+ "macros": ["TARGET_LPC11U24", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2"]
+ },
+ "LPC11U24_301": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_name": "LPC11U24FHI33/301"
+ },
+ "LPC11U34_421": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "device_name": "LPC11U34FBD48/311"
+ },
+ "MICRONFCBOARD": {
+ "inherits": ["LPC11U34_421"],
+ "macros_add": ["LPC11U34_421", "APPNEARME_MICRONFCBOARD"],
+ "extra_labels_add": ["APPNEARME_MICRONFCBOARD"],
+ "release_versions": ["2"],
+ "device_name": "LPC11U34FBD48/311"
+ },
+ "LPC11U35_401": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U35FBD48/401"
+ },
+ "LPC11U35_501": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U35FHI33/501"
+ },
+ "LPC11U35_501_IBDAP": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "device_name": "LPC11U35FHI33/501"
+ },
+ "XADOW_M0": {
+ "inherits": ["LPC11U35_501"]
+ },
+ "LPC11U35_Y5_MBUG": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "device_name": "LPC11U35FHI33/501"
+ },
+ "LPC11U37_501": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "default_lib": "small",
+ "device_name": "LPC11U37FBD64/501"
+ },
+ "LPCCAPPUCCINO": {
+ "inherits": ["LPC11U37_501"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_name": "LPC11U37FBD64/501"
+ },
+ "ARCH_GPRS": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX", "LPC11U37_501"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "inherits": ["LPCTarget"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U37FBD64/501"
+ },
+ "LPC11U68": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11U6X"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_CR", "GCC_ARM", "IAR"],
+ "inherits": ["LPCTarget"],
+ "detect_code": ["1168"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U68JBD100"
+ },
+ "LPC1347": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M3",
+ "extra_labels": ["NXP", "LPC13XX"],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2"],
+ "device_name": "LPC1347FBD48"
+ },
+ "LPC1549": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M3",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC15XX"],
+ "supported_toolchains": ["uARM", "GCC_CR", "GCC_ARM", "IAR"],
+ "inherits": ["LPCTarget"],
+ "detect_code": ["1549"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC1549JBD64"
+ },
+ "LPC1768": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M3",
+ "extra_labels": ["NXP", "LPC176X", "MBED_LPC1768", "NXP_EMAC"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "detect_code": ["1010"],
+ "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "release_versions": ["2", "5"],
+ "features": ["LWIP"],
+ "device_name": "LPC1768",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "LPC1769": {
+ "inherits": ["LPC1768"],
+ "device_name": "LPC1769"
+ },
+ "ARCH_PRO": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
+ "macros": ["TARGET_LPC1768"],
+ "inherits": ["LPCTarget"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "release_versions": ["2", "5"],
+ "features": ["LWIP"],
+ "device_name": "LPC1768",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "UBLOX_C027": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
+ "config": {
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "macros": ["TARGET_LPC1768"],
+ "inherits": ["LPCTarget"],
+ "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "release_versions": ["2", "5"],
+ "features": ["LWIP"],
+ "device_name": "LPC1768",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "CELLULAR"
+ }
+ },
+ "XBED_LPC1768": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "extra_labels": ["NXP", "LPC176X", "XBED_LPC1768"],
+ "macros": ["TARGET_LPC1768"],
+ "detect_code": ["1010"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "device_name": "LPC1768"
+ },
+ "LPC810": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC81X"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
+ "device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "device_name": "LPC810M021FN8"
+ },
+ "LPC812": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC81X"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
+ "inherits": ["LPCTarget"],
+ "detect_code": ["1050"],
+ "device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC812M101JDH20"
+ },
+ "LPC824": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC82X"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "inherits": ["LPCTarget"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC824M201JDH20"
+ },
+ "SSCI824": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC82X"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["uARM", "GCC_ARM"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "release_versions": ["2"]
+ },
+ "MCU_LPC4088": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["NXP", "LPC408X", "NXP_EMAC"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_CR", "GCC_ARM", "IAR"],
+ "post_binary_hook": {
+ "function": "LPC4088Code.binary_hook"
+ },
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "features": ["LWIP"],
+ "device_name": "LPC4088FBD144",
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "LPC4088": {
+ "inherits": ["MCU_LPC4088"],
+ "release_versions": ["2", "5"]
+ },
+ "LPC4088_DM": {
+ "inherits": ["MCU_LPC4088"],
+ "release_versions": ["2", "5"]
+ },
+ "LPC4330_M4": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
+ "supported_toolchains": ["ARM", "GCC_CR", "IAR", "GCC_ARM"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_name": "LPC4330"
+ },
+ "LPC4330_M0": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M0",
+ "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
+ "supported_toolchains": ["ARM", "GCC_CR", "IAR"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
+ },
+ "LPC4337": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["NXP", "LPC43XX", "LPC4337"],
+ "supported_toolchains": ["ARM"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2"],
+ "device_name": "LPC4337"
+ },
+ "LPC1800": {
+ "inherits": ["LPCTarget"],
+ "core": "Cortex-M3",
+ "extra_labels": ["NXP", "LPC43XX"],
+ "public": false,
+ "supported_toolchains": ["ARM", "GCC_CR", "IAR"]
+ },
+ "LPC11U37H_401": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC11UXX"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR"],
+ "inherits": ["LPCTarget"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "LPC11U37HFBD64/401"
+ },
+ "ELEKTOR_COCORICO": {
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["NXP", "LPC81X"],
+ "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
+ "inherits": ["LPCTarget"],
+ "is_disk_virtual": true,
+ "detect_code": ["C000"],
+ "default_lib": "small",
+ "device_name": "LPC812M101JDH16"
+ },
+ "KL05Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "extra_labels": ["Freescale", "KLXX"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "MKL05Z32xxx4"
+ },
+ "KL25Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "extra_labels": ["Freescale", "KLXX"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "detect_code": ["0200"],
+ "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2", "5"],
+ "device_name": "MKL25Z128xxx4"
+ },
+ "KL26Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "extra_labels": ["Freescale", "KLXX"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_name": "MKL26Z128xxx4"
+ },
+ "KL46Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "extra_labels": ["Freescale", "KLXX", "FLASH_CMSIS_ALGO"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "inherits": ["Target"],
+ "detect_code": ["0220"],
+ "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "MKL46Z256xxx4",
+ "bootloader_supported": true
+ },
+ "K20D50M": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "extra_labels": ["Freescale", "K20XX"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "detect_code": ["0230"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2"],
+ "device_name": "MK20DX128xxx5"
+ },
+ "TEENSY3_1": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "extra_labels": ["Freescale", "K20XX", "K20DX256"],
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM"],
+ "post_binary_hook": {
+ "function": "TEENSY3_1Code.binary_hook",
+ "toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
+ },
+ "detect_code": ["0230"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2"],
+ "device_name": "MK20DX256xxx7"
+ },
+ "MCU_K22F512": {
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "MCU_K22F", "MCU_K22F512", "FRDM", "KPSDK_MCUS", "KPSDK_CODE"],
+ "is_disk_virtual": true,
+ "public": false,
+ "macros": ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0231"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "device_name": "MK22DN512xxx5"
+ },
+ "K22F": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_K22F512"],
+ "release_versions": ["2", "5"],
+ "extra_labels_add": ["FRDM"]
+ },
+ "KL27Z": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "macros": ["CPU_MKL27Z64VLH4", "FSL_RTOS_MBED"],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "supported_form_factors": ["ARDUINO"],
+ "is_disk_virtual": true,
+ "default_toolchain": "ARM",
+ "detect_code": ["0261"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "default_lib": "std",
+ "release_versions": ["2"],
+ "device_name": "MKL27Z64xxx4"
+ },
+ "KL43Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "macros": ["CPU_MKL43Z256VLH4", "FSL_RTOS_MBED"],
+ "is_disk_virtual": true,
+ "inherits": ["Target"],
+ "detect_code": ["0262"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2", "5"],
+ "device_name": "MKL43Z256xxx4"
+ },
+ "KL82Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "macros": ["CPU_MKL82Z128VLK7", "FSL_RTOS_MBED"],
+ "is_disk_virtual": true,
+ "inherits": ["Target"],
+ "detect_code": ["0218"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "release_versions": ["2", "5"],
+ "device_name": "MKL82Z128xxx7"
+ },
+ "USENSE": {
+ "inherits": ["KL82Z"],
+ "extra_labels_remove": ["FRDM"],
+ "supported_form_factors": []
+ },
+ "KW24D": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MKW24D512VHA5", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0250"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "MKW24D512xxx5",
+ "bootloader_supported": true
+ },
+ "KW41Z": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0+",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MKW41Z512VHT4", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0201"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "TRNG", "STDIO_MESSAGES"],
+ "release_versions": ["2", "5"],
+ "device_name": "MKW41Z512xxx4"
+ },
+ "MCU_K24F1M": {
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "MCU_K24F", "KPSDK_MCUS", "KPSDK_CODE"],
+ "is_disk_virtual": true,
+ "public": false,
+ "macros": ["CPU_MK24FN1M0VDC12", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "device_name": "MK24FN1M0xxx12"
+ },
+ "RO359B": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_K24F1M"],
+ "detect_code": ["1022"],
+ "release_versions": ["2", "5"]
+ },
+ "K64F": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F", "Freescale_EMAC"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0240"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "CRC", "ANALOGIN", "ANALOGOUT", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG", "FLASH"],
+ "features": ["LWIP", "STORAGE"],
+ "release_versions": ["2", "5"],
+ "device_name": "MK64FN1M0xxx12",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "EV_COG_AD4050LZ": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"],
+ "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ", "FLASH_CMSIS_ALGO"],
+ "device_has": ["FLASH", "USTICKER", "RTC", "SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "SPI", "I2C", "ANALOGIN"],
+ "device_name": "ADuCM4050",
+ "detect_code": ["0603"],
+ "release_versions": ["5"],
+ "bootloader_supported": true
+ },
+ "EV_COG_AD3029LZ": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "macros": ["__ADUCM3029__", "EV_COG_AD3029LZ"],
+ "extra_labels": ["Analog_Devices", "ADUCM302X", "ADUCM3029", "EV_COG_AD3029LZ", "FLASH_CMSIS_ALGO"],
+ "device_has": ["FLASH", "USTICKER", "RTC", "SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "SPI", "I2C", "ANALOGIN"],
+ "device_name": "ADuCM3029",
+ "detect_code": ["0602"],
+ "release_versions": ["5"],
+ "bootloader_supported": true
+ },
+ "MTS_GAMBIT": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "device_name": "MK64FN1M0xxx12"
+ },
+ "HEXIWEAR": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "MCU_K64F"],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
+ "is_disk_virtual": true,
+ "default_toolchain": "ARM",
+ "detect_code": ["0214"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "default_lib": "std",
+ "release_versions": ["2", "5"],
+ "device_name": "MK64FN1M0xxx12",
+ "bootloader_supported": true
+ },
+ "K66F": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "Freescale_EMAC"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0311"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "features": ["LWIP"],
+ "release_versions": ["2", "5"],
+ "device_name": "MK66FN2M0xxx18",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "K82F": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["0217"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "MK82FN256xxx15"
+ },
+ "UBRIDGE": {
+ "inherits": ["K82F"],
+ "extra_labels_remove": ["FRDM"],
+ "supported_form_factors": []
+ },
+ "FAMILY_STM32": {
+ "inherits": ["Target"],
+ "public": false,
+ "extra_labels": ["STM"],
+ "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
+ "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+ "config": {
+ "lse_available": {
+ "help": "Define if a Low Speed External xtal (LSE) is available on the board (0 = No, 1 = Yes). If Yes, the LSE will be used to clock the RTC, LPUART, ... otherwise the Low Speed Internal clock (LSI) will be used",
+ "value": "1"
+ },
+ "lpuart_clock_source": {
+ "help": "Define the LPUART clock source. Mask values: USE_LPUART_CLK_LSE, USE_LPUART_CLK_PCLK1, USE_LPUART_CLK_HSI",
+ "value": "USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1"
+ },
+ "stdio_uart_tx": {
+ "help": "default TX STDIO pins is defined in PinNames.h file, but it can be overridden"
+ },
+ "stdio_uart_rx": {
+ "help": "default RX STDIO pins is defined in PinNames.h file, but it can be overridden"
+ }
+ },
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"]
+ },
+ "MIMXRT1050_EVK": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M7FD",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["NXP", "MCUXpresso_MCUS", "EVK", "MIMXRT1050", "IMX"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_MIMXRT1052DVL6B", "FSL_RTOS_MBED", "XIP_BOOT_HEADER_ENABLE=1", "XIP_EXTERNAL_FLASH=1", "XIP_BOOT_HEADER_DCD_ENABLE=1", "SKIP_SYSCLK_INIT"],
+ "inherits": ["Target"],
+ "detect_code": ["0227"],
+ "device_has": ["SLEEP", "USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2CSLAVE", "ERROR_RED", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2", "5"],
+ "device_name": "MIMXRT1052"
+ },
+ "LPC54114": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+ "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPC54114_M4", "LPCXpresso", "LPC"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_LPC54114J256BD64_cm4", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "detect_code": ["1054"],
+ "device_has": ["USTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name" : "LPC54114J256BD64"
+ },
+ "MCU_LPC546XX": {
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+ "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPCXpresso", "LPC", "LPC546XX", "NXP_EMAC"],
+ "is_disk_virtual": true,
+ "macros": ["CPU_LPC54628J512ET180", "FSL_RTOS_MBED"],
+ "inherits": ["Target"],
+ "device_has": ["USTICKER", "RTC", "ANALOGIN", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH", "TRNG"],
+ "features": ["LWIP"],
+ "device_name" : "LPC54628J512ET180",
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "LPC546XX": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_LPC546XX"],
+ "detect_code": ["1056"],
+ "release_versions": ["2", "5"]
+ },
+ "FF_LPC546XX": {
+ "inherits": ["MCU_LPC546XX"],
+ "extra_labels_remove" : ["LPCXpresso"],
+ "detect_code": ["8081"],
+ "release_versions": ["2", "5"]
+ },
+ "NUCLEO_F030R8": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F030R8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0725"],
+ "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "device_has_add": ["CRC", "SERIAL_FC"],
+ "device_has_remove": ["LPTICKER"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F030R8"
+ },
+ "NUCLEO_F031K6": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels_add": ["STM32F0", "STM32F031K6"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0791"],
+ "overrides": {"lse_available": 0},
+ "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "device_has_add": ["CRC", "SERIAL_FC"],
+ "device_has_remove": ["LPTICKER"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F031K6"
+ },
+ "NUCLEO_F042K6": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "default_toolchain": "uARM",
+ "extra_labels_add": ["STM32F0", "STM32F042K6"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0785"],
+ "overrides": {"lse_available": 0},
+ "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "device_has_add": ["CAN", "CRC", "SERIAL_FC"],
+ "device_has_remove": ["LPTICKER"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F042K6"
+ },
+ "NUCLEO_F070RB": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F070RB"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_delay_ticks": {
+ "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
+ "value": 1,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0755"],
+ "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "device_has_add": ["CRC", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F070RB"
+ },
+ "NUCLEO_F072RB": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F072RB"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_delay_ticks": {
+ "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
+ "value": 1,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0730"],
+ "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F072RB"
+ },
+ "NUCLEO_F091RC": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F091RC"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_delay_ticks": {
+ "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
+ "value": 1,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0750"],
+ "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F091RC"
+ },
+ "NUCLEO_F103RB": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M3",
+ "extra_labels_add": ["STM32F1", "STM32F103RB"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (SYSCLK=72 MHz) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI (SYSCLK=64 MHz)",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "In case of HSI clock source, to get 48 Mhz USB, SYSCLK has to be reduced from 64 to 48 MHz (set 0 for the max SYSCLK value)",
+ "value": "0",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "detect_code": ["0700"],
+ "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
+ "device_has_remove": ["LPTICKER"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F103RB"
+ },
+ "NUCLEO_F207ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M3",
+ "extra_labels_add": ["STM32F2", "STM32F207ZG", "STM_EMAC"],
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0835"],
+ "macros_add": ["USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "device_has_remove": ["LPTICKER"],
+ "features": ["LWIP"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F207ZG",
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F302R8": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F302x8", "STM32F302R8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0705"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F302R8"
+ },
+ "NUCLEO_F303K8": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F303x8", "STM32F303K8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": {"lse_available": 0},
+ "detect_code": ["0775"],
+ "default_lib": "small",
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_FC"],
+ "release_versions": ["2"],
+ "device_name": "STM32F303K8"
+ },
+ "NUCLEO_F303RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303RE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0745"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "release_versions": ["2", "5"],
+ "bootloader_supported": true,
+ "device_name": "STM32F303RE"
+ },
+ "NUCLEO_F303ZE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303ZE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0747"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F303ZE"
+ },
+ "NUCLEO_F334R8": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F334x8", "STM32F334R8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0735"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F334R8"
+ },
+ "NUCLEO_F401RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401RE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0720"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F401RE"
+ },
+ "STEVAL_3DP001V1": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401VE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "HSE_VALUE=25000000"],
+ "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "overrides": {"lse_available": 0},
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F401VE"
+ },
+ "NUCLEO_F410RB": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F410RB","STM32F410xB", "STM32F410Rx"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0744"],
+ "device_has_add": ["ANALOGOUT", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F410RB"
+ },
+ "NUCLEO_F411RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
+ "detect_code": ["0740"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 100 to 96 MHz (set 0 for the max SYSCLK value)",
+ "value": "0",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F411RE",
+ "bootloader_supported": true
+ },
+ "NUCLEO_F412ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0826"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F412ZG",
+ "bootloader_supported": true
+ },
+ "MTB_MXCHIP_EMW3166": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG", "WICED", "CYW43362"],
+ "features": ["LWIP"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["5"],
+ "device_name": "STM32F412ZG",
+ "bootloader_supported": true,
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "USI_WM_BN_BM_22": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG", "WICED", "CYW4343X", "CORDIO"],
+ "features": ["BLE", "LWIP"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["5"],
+ "device_name": "STM32F412ZG",
+ "bootloader_supported": true,
+ "public": false,
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "MTB_USI_WM_BN_BM_22": {
+ "overrides": {
+ "lse_available": 0
+ },
+ "inherits": ["USI_WM_BN_BM_22"]
+ },
+ "MTB_ADV_WISE_1530": {
+ "inherits": ["USI_WM_BN_BM_22"],
+ "config": {
+ "led1": "PA_4",
+ "led2": "PC_12",
+ "led3": "NC"
+ },
+ "overrides": {
+ "stdio_uart_tx": "PB_10",
+ "stdio_uart_rx": "PC_11"
+ }
+ },
+ "DISCO_F413ZH": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F413xx", "STM32F413ZH", "STM32F413xH"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0743"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F413ZH"
+ },
+ "NUCLEO_F413ZH": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F413xx", "STM32F413ZH", "STM32F413xH"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0743"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F413ZH"
+ },
+ "ELMO_F411RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "default_toolchain": "uARM",
+ "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+ "detect_code": ["----"],
+ "device_has_add": [],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F411RE"
+ },
+ "NUCLEO_F429ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+ "value": "1",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "STM32F429xI", "STM_EMAC"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "detect_code": ["0796"],
+ "features": ["LWIP"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F429ZI",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F439ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+ "value": "1",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI", "STM32F439xx", "STM32F439xI", "STM_EMAC"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_FC", "TRNG", "FLASH"],
+ "detect_code": ["0797"],
+ "features": ["LWIP"],
+ "release_versions": ["2", "5"],
+ "device_name" : "STM32F439ZI",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F446RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446RE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0777"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F446RE",
+ "bootloader_supported": true
+ },
+ "NUCLEO_F446ZE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446ZE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0778"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F446ZE"
+ },
+ "B96B_F446VE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446VE"],
+ "detect_code": ["0840"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name":"STM32F446VE"
+ },
+ "NUCLEO_F746ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7F",
+ "extra_labels_add": ["STM32F7", "STM32F746", "STM32F746xG", "STM32F746ZG", "STM_EMAC"],
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "macros_add": ["USBHOST_OTHER"],
+ "supported_form_factors": ["ARDUINO"],
+ "detect_code": ["0816"],
+ "features": ["LWIP"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F746ZG",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F756ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7F",
+ "extra_labels_add": ["STM32F7", "STM32F756", "STM32F756xG", "STM32F756ZG", "STM_EMAC"],
+ "config": {
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "macros_add": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
+ "supported_form_factors": ["ARDUINO"],
+ "detect_code": ["0819"],
+ "features": ["LWIP"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F756ZG",
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_F767ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7FD",
+ "extra_labels_add": ["STM32F7", "STM32F767", "STM32F767xI", "STM32F767ZI", "STM_EMAC"],
+ "config": {
+ "flash_dual_bank": {
+ "help": "Default board configuration is Single Bank Flash. If you enable Dual Bank with ST Link Utility, set value to 1",
+ "value": "0"
+ },
+ "d11_configuration": {
+ "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
+ "value": "PA_7",
+ "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "supported_form_factors": ["ARDUINO"],
+ "macros_add": ["USBHOST_OTHER"],
+ "detect_code": ["0818"],
+ "features": ["LWIP"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F767ZI",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NUCLEO_L011K4": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L011K4"],
+ "supported_toolchains": ["uARM"],
+ "default_toolchain": "uARM",
+ "supported_form_factors": ["ARDUINO"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0780"],
+ "device_has_add": ["CRC", "SERIAL_FC", "FLASH"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32L011K4"
+ },
+ "NUCLEO_L031K6": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L031K6"],
+ "default_toolchain": "uARM",
+ "supported_form_factors": ["ARDUINO"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0790"],
+ "device_has_add": ["CRC", "SERIAL_FC", "FLASH"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32L031K6"
+ },
+ "NUCLEO_L053R8": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053R8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0715"],
+ "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32L053R8"
+ },
+ "NUCLEO_L073RZ": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L073RZ", "STM32L073xx"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0760"],
+ "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L073RZ"
+ },
+ "NUCLEO_L152RE": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M3",
+ "extra_labels_add": ["STM32L1", "STM32L152RE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_delay_ticks": {
+ "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
+ "value": 1,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0710"],
+ "device_has_add": ["ANALOGOUT", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L152RE"
+ },
+ "NUCLEO_L432KC": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L432xC", "STM32L432KC"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0770"],
+ "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L432KC",
+ "bootloader_supported": true
+ },
+ "NUCLEO_L433RC_P": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L433xC", "STM32L433RC"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0779"],
+ "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L433RC",
+ "bootloader_supported": true
+ },
+ "MTB_ADV_WISE_1510": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L443xC", "STM32L443RC"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": {"lse_available": 0},
+ "release_versions": ["5"],
+ "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"],
+ "device_has_remove": ["LPTICKER"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+ "device_name" : "STM32L443RC",
+ "detect_code": ["0458"],
+ "bootloader_supported": true
+ },
+ "NUCLEO_L476RG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L476RG", "STM32L476xG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0765"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L476RG",
+ "bootloader_supported": true
+ },
+ "SILICA_SENSOR_NODE": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "default_toolchain": "GCC_ARM",
+ "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476JG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0766"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["5"],
+ "device_name": "STM32L476JG"
+ },
+ "NUCLEO_L486RG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0827"],
+ "macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT", "TWO_RAM_REGIONS"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L486RG"
+ },
+ "MTB_ADV_WISE_1570": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG", "WISE_1570"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_HSE_XTAL",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": {"lpuart_clock_source": "USE_LPUART_CLK_HSI"},
+ "detect_code": ["0460"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "WISE_1570", "TWO_RAM_REGIONS"],
+ "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_remove": ["LPTICKER"],
+ "release_versions": ["5"],
+ "device_name": "STM32L486RG",
+ "bootloader_supported": true,
+ "OUTPUT_EXT": "hex"
+ },
+ "ARCH_MAX": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+ "program_cycle_s": 2,
+ "extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"],
+ "device_has_add": ["ANALOGOUT"],
+ "release_versions": ["2"],
+ "device_name": "STM32F407VG"
+ },
+ "WIO_3G": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+ "value": "1",
+ "macro_name": "CLOCK_SOURCE_USB"
+ },
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439VI", "STM32F439xx", "STM32F439xI"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+ "detect_code": ["9014"],
+ "features": ["LWIP"],
+ "release_versions": ["2", "5"],
+ "device_name" : "STM32F439VI",
+ "bootloader_supported": true
+ },
+ "DISCO_F051R8": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0",
+ "extra_labels_add": ["STM32F0", "STM32F051", "STM32F051R8"],
+ "supported_toolchains": ["GCC_ARM"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "device_has_add": ["CRC", "SERIAL_FC"],
+ "device_has_remove": ["LPTICKER"],
+ "device_name": "STM32F051R8"
+ },
+ "DISCO_F100RB": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "extra_labels_add": ["STM32F1", "STM32F100RB"],
+ "supported_toolchains": ["GCC_ARM"],
+ "device_has_add": [],
+ "device_has_remove": ["LPTICKER"],
+ "device_name": "STM32F100RB"
+ },
+ "DISCO_F303VC": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F303", "STM32F303xC", "STM32F303VC"],
+ "overrides": {"lse_available": 0},
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_FC"],
+ "device_name": "STM32F303VC"
+ },
+ "DISCO_F334C8": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F3", "STM32F334x8","STM32F334C8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "overrides": {"lse_available": 0},
+ "detect_code": ["0810"],
+ "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_ASYNCH", "SERIAL_FC"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32F334C8"
+ },
+ "DISCO_F407VG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "macros_add": ["USB_STM_HAL"],
+ "overrides": {"lse_available": 0},
+ "device_has_add": ["ANALOGOUT"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F407VG"
+ },
+ "DISCO_F429ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xI", "STM32F429xx"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "clock_source_usb": {
+ "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+ "value": "1",
+ "macro_name": "CLOCK_SOURCE_USB"
+ }
+ },
+ "overrides": {"lse_available": 0},
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F429ZI",
+ "bootloader_supported": true
+ },
+ "DISCO_F469NI": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F469", "STM32F469NI", "STM32F469xI", "STM32F469xx"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "detect_code": ["0788"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F469NI"
+ },
+ "DISCO_L053C8": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053C8"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "overrides": {"lse_available": 0},
+ "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "FLASH"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32L053C8"
+ },
+ "DISCO_L072CZ_LRWAN1": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L072CZ", "STM32L072xZ", "STM32L072xx"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0833"],
+ "device_has_add": ["ANALOGOUT", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L072CZ"
+ },
+ "MTB_MURATA_ABZ": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M0+",
+ "extra_labels_add": ["STM32L0", "STM32L0x2xZ", "STM32L082CZ", "STM32L082xx"],
+ "detect_code": ["0456"],
+ "device_has_add": ["ANALOGOUT", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "device_has_remove": ["LPTICKER"],
+ "release_versions": ["5"],
+ "device_name": "STM32L082CZ"
+ },
+ "DISCO_F746NG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7F",
+ "extra_labels_add": ["STM32F7", "STM32F746", "STM32F746xG", "STM32F746NG", "STM_EMAC"],
+ "supported_form_factors": ["ARDUINO"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "usb_speed": {
+ "help": "Select the USB speed/connector (0=FullSpeed, 1=HighSpeed)",
+ "value": "1"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0815"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "features": ["LWIP"],
+ "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F746NG",
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "DISCO_F769NI": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M7FD",
+ "extra_labels_add": ["STM32F7", "STM32F769", "STM32F769xI", "STM32F769NI", "STM_EMAC"],
+ "supported_form_factors": ["ARDUINO"],
+ "config": {
+ "flash_dual_bank": {
+ "help": "Default board configuration is Single Bank Flash. If you enable Dual Bank with ST Link Utility, set value to 1",
+ "value": "0"
+ },
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0817"],
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+ "features": ["LWIP"],
+ "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F769NI",
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "DISCO_L475VG_IOT01A": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L475xG", "STM32L475VG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "supported_form_factors": ["ARDUINO"],
+ "detect_code": ["0764"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L475VG",
+ "bootloader_supported": true
+ },
+ "DISCO_L476VG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0820"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L476VG",
+ "bootloader_supported": true
+ },
+ "MTS_MDOT_F405RG": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F405RG"],
+ "is_disk_virtual": true,
+ "macros_add": ["HSE_VALUE=26000000"],
+ "device_has_add": ["ANALOGOUT"],
+ "release_versions": ["2"],
+ "device_name": "STM32F405RG"
+ },
+ "MTS_MDOT_F411RE": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411RE"],
+ "macros_add": ["HSE_VALUE=26000000", "USE_PLL_HSE_EXTC=0", "VECT_TAB_OFFSET=0x00010000"],
+ "post_binary_hook": {
+ "function": "MTSCode.combine_bins_mts_dot",
+ "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
+ },
+ "device_has_add": [],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F411RE"
+ },
+ "MTS_DRAGONFLY_F411RE": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411RE"],
+ "config": {
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "overrides": {"lse_available": 0},
+ "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
+ "post_binary_hook": {
+ "function": "MTSCode.combine_bins_mts_dragonfly",
+ "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
+ },
+ "device_has_add": [],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F411RE"
+ },
+ "MTB_MTS_DRAGONFLY": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411RE"],
+ "config": {
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "overrides": {
+ "lse_available": 0
+ },
+ "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
+ "post_binary_hook": {
+ "function": "MTSCode.combine_bins_mtb_mts_dragonfly",
+ "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
+ },
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F411RE",
+ "bootloader_supported": true
+ },
+ "XDOT_L151CC": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "ARM",
+ "extra_labels_add": ["STM32L1", "STM32L151CC"],
+ "config": {
+ "hse_value": {
+ "value": "24000000",
+ "macro_name": "HSE_VALUE"
+ }
+ },
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "device_has_add": ["ANALOGOUT", "FLASH"],
+ "release_versions": ["5"],
+ "device_name": "STM32L151CC",
+ "bootloader_supported": true
+ },
+ "FF1705_L151CC": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["XDOT_L151CC"],
+ "detect_code": ["8080"]
+ },
+ "MTB_MTS_XDOT": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "ARM",
+ "extra_labels_add": ["STM32L1", "STM32L151CC"],
+ "config": {
+ "hse_value": {
+ "value": "24000000",
+ "macro_name": "HSE_VALUE"
+ }
+ },
+ "overrides": {
+ "stdio_uart_tx": "PA_2",
+ "stdio_uart_rx": "PA_3"
+ },
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "device_has_add": ["ANALOGOUT", "FLASH"],
+ "release_versions": ["5"],
+ "device_name": "STM32L151CC",
+ "bootloader_supported": true
+ },
+ "MTB_RAK811": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "ARM",
+ "extra_labels_add": ["STM32L1", "STM32L151xBA", "STM32L151CBA"],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "device_has_add": ["ANALOGOUT"],
+ "release_versions": ["5"],
+ "device_name": "STM32L151CBxxA",
+ "bootloader_supported": true
+ },
+ "MOTE_L152RC": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "uARM",
+ "extra_labels_add": ["STM32L1", "STM32L152RC"],
+ "overrides": {"lse_available": 0},
+ "detect_code": ["4100"],
+ "device_has_add": ["ANALOGOUT"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "STM32L152RC"
+ },
+ "DISCO_F401VC": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "default_toolchain": "GCC_ARM",
+ "extra_labels_add": ["STM32F4", "STM32F401", "STM32F401xC", "STM32F401VC"],
+ "supported_toolchains": ["GCC_ARM"],
+ "device_has_add": [],
+ "device_name": "STM32F401VC"
+ },
+ "MODULE_UBLOX_ODIN_W2": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI", "STM_EMAC"],
+ "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","CB_FEATURE_802DOT11W","CB_FEATURE_802DOT11R","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"],
+ "device_has_add": ["CAN", "EMAC", "TRNG", "FLASH", "WIFI"],
+ "device_has_remove": [],
+ "features": ["LWIP"],
+ "device_name": "STM32F439ZI",
+ "public": false,
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "UBLOX_EVK_ODIN_W2": {
+ "inherits": ["MODULE_UBLOX_ODIN_W2"],
+ "supported_form_factors": ["ARDUINO"],
+ "release_versions": ["5"],
+ "device_has_remove": [],
+ "config": {
+ "stdio_uart_tx_help": {
+ "help": "Value: D8(default) or D1"
+ },
+ "stdio_uart_rx_help": {
+ "help": "Value: D2(default) or D0"
+ }
+ },
+ "overrides": {
+ "stdio_uart_tx": "D8",
+ "stdio_uart_rx": "D2"
+ }
+ },
+ "MBED_CONNECT_ODIN": {
+ "inherits": ["MODULE_UBLOX_ODIN_W2"],
+ "release_versions": ["5"],
+ "config": {
+ "stdio_uart_tx_help": {
+ "help": "Value: PA_9(default) or PD_8"
+ },
+ "stdio_uart_rx_help": {
+ "help": "Value: PA_10(default) or PD_9"
+ }
+ },
+ "overrides": {
+ "stdio_uart_tx": "PA_9",
+ "stdio_uart_rx": "PA_10"
+ }
+ },
+ "MTB_UBLOX_ODIN_W2": {
+ "inherits": ["MODULE_UBLOX_ODIN_W2"],
+ "device_has_add": [],
+ "release_versions": ["5"]
+ },
+ "UBLOX_C030": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "extra_labels_add": ["STM32F4", "STM32F437", "STM32F437VG", "STM32F437xx", "STM32F437xG", "STM_EMAC"],
+ "config": {
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
+ "overrides": {"lse_available": 0},
+ "device_has_add": ["ANALOGOUT", "EMAC", "SERIAL_FC", "TRNG", "FLASH"],
+ "features": ["LWIP"],
+ "public": false,
+ "device_name": "STM32F437VG",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "UBLOX_C030_U201": {
+ "inherits": ["UBLOX_C030"],
+ "release_versions": ["5"]
+ },
+ "UBLOX_C030_N211": {
+ "inherits": ["UBLOX_C030"],
+ "release_versions": ["5"]
+ },
+ "UBLOX_C030_R410M": {
+ "inherits": ["UBLOX_C030"],
+ "release_versions": ["5"]
+ },
+ "NZ32_SC151": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "uARM",
+ "program_cycle_s": 1.5,
+ "extra_labels_add": ["STM32L1", "STM32L151RC"],
+ "overrides": {"lse_available": 0},
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+ "device_has_add": ["ANALOGOUT"],
+ "default_lib": "small",
+ "device_name": "STM32L151RC"
+ },
+ "MCU_NRF51": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
+ "macros": ["NRF51", "TARGET_NRF51822", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "MERGE_BOOTLOADER": false,
+ "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822"],
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_ARM"],
+ "public": false,
+ "MERGE_SOFT_DEVICE": true,
+ "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+ {
+ "boot": "s130_nrf51_1.0.0_bootloader.hex",
+ "name": "s130_nrf51_1.0.0_softdevice.hex",
+ "offset": 114688
+ },
+ {
+ "boot": "s110_nrf51822_8.0.0_bootloader.hex",
+ "name": "s110_nrf51822_8.0.0_softdevice.hex",
+ "offset": 98304
+ },
+ {
+ "boot": "s110_nrf51822_7.1.0_bootloader.hex",
+ "name": "s110_nrf51822_7.1.0_softdevice.hex",
+ "offset": 90112
+ },
+ {
+ "boot": "s110_nrf51822_7.0.0_bootloader.hex",
+ "name": "s110_nrf51822_7.0.0_softdevice.hex",
+ "offset": 90112
+ },
+ {
+ "boot": "s110_nrf51822_6.0.0_bootloader.hex",
+ "name": "s110_nrf51822_6.0.0_softdevice.hex",
+ "offset": 81920
+ }
+ ],
+ "detect_code": ["1070"],
+ "post_binary_hook": {
+ "function": "MCU_NRF51Code.binary_hook",
+ "toolchains": ["ARM_STD", "GCC_ARM"]
+ },
+ "program_cycle_s": 6,
+ "features": ["BLE"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
+ },
+ "MCU_NRF51_16K_BASE": {
+ "inherits": ["MCU_NRF51"],
+ "extra_labels_add": ["MCU_NORDIC_16K", "MCU_NRF51_16K"],
+ "macros_add": ["TARGET_MCU_NORDIC_16K", "TARGET_MCU_NRF51_16K"],
+ "public": false,
+ "default_lib": "small"
+ },
+ "MCU_NRF51_16K_BOOT_BASE": {
+ "inherits": ["MCU_NRF51_16K_BASE"],
+ "MERGE_BOOTLOADER": true,
+ "extra_labels_add": ["MCU_NRF51_16K_BOOT"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_BOOT", "TARGET_OTA_ENABLED"],
+ "public": false
+ },
+ "MCU_NRF51_16K_OTA_BASE": {
+ "inherits": ["MCU_NRF51_16K_BASE"],
+ "public": false,
+ "extra_labels_add": ["MCU_NRF51_16K_OTA"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_OTA", "TARGET_OTA_ENABLED"],
+ "MERGE_SOFT_DEVICE": false
+ },
+ "MCU_NRF51_16K": {
+ "inherits": ["MCU_NRF51_16K_BASE"],
+ "extra_labels_add": ["MCU_NRF51_16K_S130"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
+ "public": false
+ },
+ "MCU_NRF51_S110": {
+ "extra_labels_add": ["MCU_NRF51_16K_S110"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_S110"],
+ "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+ {
+ "name": "s110_nrf51822_8.0.0_softdevice.hex",
+ "boot": "s110_nrf51822_8.0.0_bootloader.hex",
+ "offset": 98304
+ },
+ {
+ "name": "s110_nrf51822_7.1.0_softdevice.hex",
+ "boot": "s110_nrf51822_7.1.0_bootloader.hex",
+ "offset": 90112
+ }
+ ],
+ "public": false
+ },
+ "MCU_NRF51_16K_S110": {
+ "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_BASE"],
+ "public": false
+ },
+ "MCU_NRF51_16K_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT_BASE"],
+ "extra_labels_add": ["MCU_NRF51_16K_S130"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
+ "public": false
+ },
+ "MCU_NRF51_16K_BOOT_S110": {
+ "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_BOOT_BASE"],
+ "public": false
+ },
+ "MCU_NRF51_16K_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA_BASE"],
+ "extra_labels_add": ["MCU_NRF51_16K_S130"],
+ "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
+ "public": false
+ },
+ "MCU_NRF51_16K_OTA_S110": {
+ "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_OTA_BASE"],
+ "public": false
+ },
+ "MCU_NRF51_32K": {
+ "inherits": ["MCU_NRF51"],
+ "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
+ "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
+ "public": false
+ },
+ "MCU_NRF51_32K_BOOT": {
+ "inherits": ["MCU_NRF51_32K"],
+ "MERGE_BOOTLOADER": true,
+ "extra_labels_add": ["MCU_NRF51_32K_BOOT"],
+ "macros_add": ["TARGET_MCU_NRF51_32K_BOOT", "TARGET_OTA_ENABLED"],
+ "public": false
+ },
+ "MCU_NRF51_32K_OTA": {
+ "inherits": ["MCU_NRF51_32K"],
+ "public": false,
+ "extra_labels_add": ["MCU_NRF51_32K_OTA"],
+ "macros_add": ["TARGET_MCU_NRF51_32K_OTA", "TARGET_OTA_ENABLED"],
+ "MERGE_SOFT_DEVICE": false
+ },
+ "NRF51822": {
+ "inherits": ["MCU_NRF51_16K"],
+ "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
+ "macros_add": ["TARGET_NRF51822_MKIT"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "NRF51822_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
+ "macros_add": ["TARGET_NRF51822_MKIT"]
+ },
+ "NRF51822_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
+ "macros_add": ["TARGET_NRF51822_MKIT"]
+ },
+ "ARCH_BLE": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "ARCH_BLE_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["ARCH_BLE"],
+ "macros_add": ["TARGET_ARCH_BLE"]
+ },
+ "ARCH_BLE_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["ARCH_BLE"],
+ "macros_add": ["TARGET_ARCH_BLE"]
+ },
+ "ARCH_LINK": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K"],
+ "extra_labels_add": ["ARCH_BLE"],
+ "macros_add": ["TARGET_ARCH_BLE"]
+ },
+ "ARCH_LINK_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
+ "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
+ },
+ "ARCH_LINK_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
+ "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
+ },
+ "SEEED_TINY_BLE": {
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "SEEED_TINY_BLE_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["SEEED_TINY_BLE"],
+ "macros_add": ["TARGET_SEEED_TINY_BLE"]
+ },
+ "SEEED_TINY_BLE_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["SEEED_TINY_BLE"],
+ "macros_add": ["TARGET_SEEED_TINY_BLE"]
+ },
+ "HRM1017": {
+ "inherits": ["MCU_NRF51_16K"],
+ "macros_add": ["TARGET_NRF_LFCLK_RC"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "HRM1017_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["HRM1017"],
+ "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
+ },
+ "HRM1017_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["HRM1017"],
+ "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
+ },
+ "RBLAB_NRF51822": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "RBLAB_NRF51822_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["RBLAB_NRF51822"],
+ "macros_add": ["TARGET_RBLAB_NRF51822"]
+ },
+ "RBLAB_NRF51822_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["RBLAB_NRF51822"],
+ "macros_add": ["TARGET_RBLAB_NRF51822"]
+ },
+ "RBLAB_BLENANO": {
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"]
+ },
+ "RBLAB_BLENANO_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["RBLAB_BLENANO"],
+ "macros_add": ["TARGET_RBLAB_BLENANO"]
+ },
+ "RBLAB_BLENANO_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["RBLAB_BLENANO"],
+ "macros_add": ["TARGET_RBLAB_BLENANO"]
+ },
+ "RBLAB_BLENANO2": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "NRF51822_Y5_MBUG": {
+ "inherits": ["MCU_NRF51_16K"]
+ },
+ "WALLBOT_BLE": {
+ "inherits": ["MCU_NRF51_16K"],
+ "release_versions": ["2"]
+ },
+ "WALLBOT_BLE_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["WALLBOT_BLE"],
+ "macros_add": ["TARGET_WALLBOT_BLE"]
+ },
+ "WALLBOT_BLE_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["WALLBOT_BLE"],
+ "macros_add": ["TARGET_WALLBOT_BLE"]
+ },
+ "DELTA_DFCM_NNN40": {
+ "inherits": ["MCU_NRF51_32K"],
+ "program_cycle_s": 10,
+ "macros_add": ["TARGET_NRF_LFCLK_RC"],
+ "device_has": ["ANALOGIN", "DEBUG_AWARENESS", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "DELTA_DFCM_NNN40_BOOT": {
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "program_cycle_s": 10,
+ "extra_labels_add": ["DELTA_DFCM_NNN40"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
+ },
+ "DELTA_DFCM_NNN40_OTA": {
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "program_cycle_s": 10,
+ "extra_labels_add": ["DELTA_DFCM_NNN40"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
+ },
+ "DELTA_DFCM_NNN50": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_name": "nRF51822_xxAC"
+ },
+ "DELTA_DFCM_NNN50_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["DELTA_DFCM_NNN50"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
+ },
+ "DELTA_DFCM_NNN50_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["DELTA_DFCM_NNN50"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
+ },
+ "NRF51_DK_LEGACY": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K"],
+ "extra_labels_add": ["NRF51_DK"]
+ },
+ "NRF51_DK_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["NRF51_DK"],
+ "macros_add": ["TARGET_NRF51_DK"]
+ },
+ "NRF51_DK_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["NRF51_DK"],
+ "macros_add": ["TARGET_NRF51_DK"]
+ },
+ "NRF51_DONGLE_LEGACY": {
+ "inherits": ["MCU_NRF51_32K"],
+ "extra_labels_add": ["NRF51_DONGLE"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "NRF51_DONGLE_BOOT": {
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["NRF51_DONGLE"],
+ "macros_add": ["TARGET_NRF51_DONGLE"]
+ },
+ "NRF51_DONGLE_OTA": {
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["NRF51_DONGLE"],
+ "macros_add": ["TARGET_NRF51_DONGLE"]
+ },
+ "NRF51_MICROBIT": {
+ "inherits": ["MCU_NRF51_16K_S110"],
+ "macros_add": ["TARGET_NRF_LFCLK_RC"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "NRF51_MICROBIT_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT_S110"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+ },
+ "NRF51_MICROBIT_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA_S110"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+ },
+ "NRF51_MICROBIT_B": {
+ "inherits": ["MCU_NRF51_16K"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"],
+ "release_versions": ["2"]
+ },
+ "NRF51_MICROBIT_B_BOOT": {
+ "inherits": ["MCU_NRF51_16K_BOOT"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+ },
+ "NRF51_MICROBIT_B_OTA": {
+ "inherits": ["MCU_NRF51_16K_OTA"],
+ "extra_labels_add": ["NRF51_MICROBIT"],
+ "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
+ },
+ "MTM_MTCONNECT04S": {
+ "inherits": ["MCU_NRF51_32K"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "MTM_MTCONNECT04S_BOOT": {
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["MTM_CONNECT04S"],
+ "macros_add": ["TARGET_MTM_CONNECT04S"]
+ },
+ "MTM_MTCONNECT04S_OTA": {
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["MTM_CONNECT04S"],
+ "macros_add": ["TARGET_MTM_CONNECT04S"]
+ },
+ "MTB_LAIRD_BL600": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_name": "nRF51822_xxAA",
+ "release_versions" : ["5"],
+ "extra_labels_add": ["MTB_LAIRD_BL600"],
+ "config": {
+ "usb_tx": {
+ "help": "Value SIO_21",
+ "value": "SIO_21"
+ },
+ "usb_rx": {
+ "help": "Value SIO_22",
+ "value": "SIO_22"
+ },
+ "stdio_uart": {
+ "help": "Value: UART_0",
+ "value": "UART_0",
+ "macro_name": "STDIO_UART"
+ }
+ },
+ "overrides": {
+ "uart_hwfc": 0
+ }
+ },
+ "TY51822R3": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "macros_add": ["TARGET_NRF_32MHZ_XTAL"],
+ "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "detect_code": ["1019"],
+ "release_versions": ["2", "5"],
+ "overrides": {"uart_hwfc": 0},
+ "device_name": "nRF51822_xxAA"
+ },
+ "TY51822R3_BOOT": {
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["TY51822R3"],
+ "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
+ },
+ "TY51822R3_OTA": {
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["NRF51_DK"],
+ "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
+ },
+ "ARM_MPS2_Target": {
+ "inherits": ["Target"],
+ "public": false,
+ "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
+ },
+ "ARM_MPS2_M0": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M0",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"],
+ "macros": ["CMSDK_CM0", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+ "release_versions": ["2"]
+ },
+ "ARM_MPS2_M0P": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M0+",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0P"],
+ "macros": ["CMSDK_CM0plus"],
+ "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+ "release_versions": ["2"]
+ },
+ "ARM_MPS2_M3": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M3"],
+ "macros": ["CMSDK_CM3"],
+ "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+ "release_versions": ["2"]
+ },
+ "ARM_MPS2_M4": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M4F",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M4"],
+ "macros": ["CMSDK_CM4"],
+ "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+ "release_versions": ["2"]
+ },
+ "ARM_MPS2_M7": {
+ "inherits": ["ARM_MPS2_Target"],
+ "core": "Cortex-M7",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M7"],
+ "macros": ["CMSDK_CM7"],
+ "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+ "release_versions": ["2"]
+ },
+ "ARM_IOTSS_Target": {
+ "inherits": ["Target"],
+ "public": false,
+ "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
+ },
+ "ARM_IOTSS_BEID": {
+ "inherits": ["ARM_IOTSS_Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM"],
+ "extra_labels": ["ARM_SSG", "IOTSS", "IOTSS_BEID"],
+ "macros": ["CMSDK_BEID"],
+ "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
+ "release_versions": ["2"]
+ },
+ "ARM_CM3DS_MPS2": {
+ "inherits": ["ARM_IOTSS_Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
+ "OUTPUT_EXT": "elf",
+ "macros": ["CMSDK_CM3DS"],
+ "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "copy_method": "mps2",
+ "reset_method": "reboot.txt"
+ },
+ "ARM_BEETLE_SOC": {
+ "inherits": ["ARM_IOTSS_Target"],
+ "core": "Cortex-M3",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "default_toolchain": "ARM",
+ "extra_labels": ["ARM_SSG", "BEETLE"],
+ "macros": ["CMSDK_BEETLE", "WSF_MS_PER_TICK=20", "WSF_TOKEN_ENABLED=FALSE", "WSF_TRACE_ENABLED=TRUE", "WSF_ASSERT_ENABLED=FALSE", "WSF_PRINTF_MAX_LEN=128", "ASIC", "CONFIG_HOST_REV=0x20", "CONFIG_ALLOW_DEEP_SLEEP=FALSE", "HCI_VS_TARGET", "CONFIG_ALLOW_SETTING_WRITE=TRUE", "WSF_MAX_HANDLERS=20", "NO_LEDS"],
+ "device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI"],
+ "features": ["BLE"],
+ "release_versions": ["2", "5"]
+ },
+ "RZ_A1XX": {
+ "inherits": ["Target"],
+ "core": "Cortex-A9",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "extra_labels": ["RENESAS", "RZ_A1XX"],
+ "device_has": ["SLEEP", "USTICKER", "RTC", "ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "features": ["LWIP"],
+ "program_cycle_s": 2,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "RZ_A1H": {
+ "inherits": ["RZ_A1XX"],
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["RZA1H", "MBRZA1H", "RZ_A1_EMAC"],
+ "device_has_add": ["EMAC", "FLASH", "LPTICKER"],
+ "release_versions": ["2", "5"],
+ "device_name": "R7S72100",
+ "bootloader_supported": true
+ },
+ "VK_RZ_A1H": {
+ "inherits": ["RZ_A1XX"],
+ "extra_labels_add": ["RZA1H", "VKRZA1H", "RZ_A1_EMAC"],
+ "device_has_add": ["EMAC"],
+ "release_versions": ["2", "5"]
+ },
+ "GR_LYCHEE": {
+ "inherits": ["RZ_A1XX"],
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["RZA1UL", "MBRZA1LU"],
+ "device_has_add": ["TRNG", "FLASH", "LPTICKER"],
+ "device_has_remove": ["ETHERNET"],
+ "features_remove": ["LWIP"],
+ "release_versions": ["2", "5"],
+ "device_name": "R7S72103",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": null
+ }
+ },
+ "MAXWSNENV": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "macros": ["__SYSTEM_HFX=24000000"],
+ "extra_labels": ["Maxim", "MAX32610"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+ "features": ["BLE"],
+ "release_versions": []
+ },
+ "MAX32600MBED": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "macros": ["__SYSTEM_HFX=24000000"],
+ "extra_labels": ["Maxim", "MAX32600"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+ "release_versions": ["2", "5"]
+ },
+ "MAX32620HSP": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["Maxim", "MAX32620"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "features": ["BLE"],
+ "release_versions": []
+ },
+ "MAX32620FTHR": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32620","TARGET_REV=0x4332","OPEN_DRAIN_LEDS"],
+ "extra_labels": ["Maxim", "MAX32620C"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
+ "release_versions": ["2", "5"]
+ },
+ "MAX32625_BASE": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": ["TARGET=MAX32625","TARGET_REV=0x4132", "OPEN_DRAIN_LEDS"],
+ "extra_labels": ["Maxim", "MAX32625"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
+ "release_versions": ["2", "5"],
+ "public": false
+ },
+ "MAX32625_BOOT": {
+ "inherits": ["MAX32625_BASE"],
+ "extra_labels_add": ["MAX32625_BOOT"],
+ "public": false
+ },
+ "MAX32625_NO_BOOT": {
+ "inherits": ["MAX32625_BASE"],
+ "extra_labels_add": ["MAX32625_NO_BOOT"],
+ "public": false
+ },
+ "MAX32625MBED": {
+ "inherits": ["MAX32625_NO_BOOT"]
+ },
+ "MAX32625PICO": {
+ "inherits": ["MAX32625_BOOT"],
+ "extra_labels_add": ["MAX32625PICO_BASE"]
+ },
+ "MAX32625PICO_NO_BOOT": {
+ "inherits": ["MAX32625_NO_BOOT"],
+ "extra_labels_add": ["MAX32625PICO_BASE"]
+ },
+ "MAX32625NEXPAQ": {
+ "inherits": ["MAX32625_BASE"],
+ "extra_labels_add": ["MAX32625NEXPAQ"]
+ },
+ "MAX32630FTHR": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": ["__SYSTEM_HFX=96000000", "TARGET=MAX32630", "TARGET_REV=0x4132", "BLE_HCI_UART", "OPEN_DRAIN_LEDS"],
+ "extra_labels": ["Maxim", "MAX32630"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "STDIO_MESSAGES", "USTICKER"],
+ "features": ["BLE"],
+ "release_versions": ["2", "5"]
+ },
+ "EFM32": {
+ "inherits": ["Target"],
+ "extra_labels": ["Silicon_Labs", "EFM32"],
+ "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "MBED_TICKLESS", "EM_MSC_RUN_FROM_FLASH"],
+ "public": false
+ },
+ "EFM32GG990F1024": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"],
+ "core": "Cortex-M3",
+ "macros_add": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32GG990F1024",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32GG_STK3700": {
+ "inherits": ["EFM32GG990F1024"],
+ "progen": {"target": "efm32gg-stk"},
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH", "ITM"],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "48000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PF7",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32LG990F256": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32LG", "256K", "SL_AES"],
+ "core": "Cortex-M3",
+ "macros_add": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32LG990F256",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32LG_STK3600": {
+ "inherits": ["EFM32LG990F256"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
+ "forced_reset_timeout": 2,
+ "device_name": "EFM32LG990F256",
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "48000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PF7",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32WG990F256": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32WG", "256K", "SL_AES"],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32WG990F256",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32WG_STK3800": {
+ "inherits": ["EFM32WG990F256"],
+ "progen": {"target": "efm32wg-stk"},
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "48000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PF7",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32ZG222F32": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "macros_add": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+ "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "EFM32ZG222F32",
+ "public": false
+ },
+ "EFM32ZG_STK3200": {
+ "inherits": ["EFM32ZG222F32"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER"],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "24000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA9",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32HG322F64": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32HG", "64K", "SL_AES"],
+ "core": "Cortex-M0+",
+ "default_toolchain": "uARM",
+ "macros_add": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+ "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
+ "default_lib": "small",
+ "release_versions": ["2"],
+ "device_name": "EFM32HG322F64",
+ "public": false
+ },
+ "EFM32HG_STK3400": {
+ "inherits": ["EFM32HG322F64"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER"],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "24000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "21000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA9",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFM32PG1B100F256GM32": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32PG1B100F256GM32",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32PG_STK3401": {
+ "inherits": ["EFM32PG1B100F256GM32"],
+ "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "40000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA5",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFR32MG1P132F256GM48": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFR32MG1", "EFR32_1", "256K", "SL_RAIL", "SL_CRYPTO"],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFR32MG1P132F256GM48",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFR32MG1P233F256GM48": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFR32MG1", "EFR32_1", "256K", "SL_RAIL", "SL_CRYPTO"],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFR32MG1_BRD4150": {
+ "inherits": ["EFR32MG1P132F256GM48"],
+ "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "38400000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA5",
+ "macro_name": "EFM_BC_EN"
+ }
+ },
+ "public": false
+ },
+ "TB_SENSE_1": {
+ "inherits": ["EFR32MG1P233F256GM48"],
+ "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
+ "forced_reset_timeout": 5,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "38400000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ }
+ }
+ },
+ "EFM32PG12B500F1024GL125": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32PG12B500F1024GL125",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32PG12_STK3402": {
+ "inherits": ["EFM32PG12B500F1024GL125"],
+ "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
+ "forced_reset_timeout": 2,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "40000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PA5",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "EFR32MG12P332F1024GL125": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFR32MG12", "EFR32_12", "1024K", "SL_RAIL", "SL_CRYPTO"],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFR32MG12P332F1024GL125",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "TB_SENSE_12": {
+ "inherits": ["EFR32MG12P332F1024GL125"],
+ "device_name": "EFR32MG12P332F1024GL125",
+ "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
+ "forced_reset_timeout": 5,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "38400000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ }
+ }
+ },
+ "EFM32GG11B820F2048GL192": {
+ "inherits": ["EFM32"],
+ "extra_labels_add": ["EFM32GG11", "2048K", "SL_CRYPTO"],
+ "core": "Cortex-M4F",
+ "macros_add": ["EFM32GG11B820F2048GL192", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+ "release_versions": ["2", "5"],
+ "device_name": "EFM32GG11B820F2048GL192",
+ "public": false,
+ "bootloader_supported": true
+ },
+ "EFM32GG11_STK3701": {
+ "inherits": ["EFM32GG11B820F2048GL192"],
+ "device_name": "EFM32GG11B820F2048GL192",
+ "device_has": ["ANALOGIN", "CRC", "EMAC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
+ "features": ["LWIP"],
+ "forced_reset_timeout": 5,
+ "config": {
+ "hf_clock_src": {
+ "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+ "value": "HFXO",
+ "macro_name": "CORE_CLOCK_SOURCE"
+ },
+ "hfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "50000000",
+ "macro_name": "HFXO_FREQUENCY"
+ },
+ "lf_clock_src": {
+ "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+ "value": "LFXO",
+ "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+ },
+ "lfxo_clock_freq": {
+ "help": "Value: External crystal frequency in hertz",
+ "value": "32768",
+ "macro_name": "LFXO_FREQUENCY"
+ },
+ "hfrco_clock_freq": {
+ "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+ "value": "32000000",
+ "macro_name": "HFRCO_FREQUENCY"
+ },
+ "hfrco_band_select": {
+ "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+ "value": "cmuHFRCOFreq_32M0Hz",
+ "macro_name": "HFRCO_FREQUENCY_ENUM"
+ },
+ "board_controller_enable": {
+ "help": "Pin to pull high for enabling the USB serial port",
+ "value": "PE1",
+ "macro_name": "EFM_BC_EN"
+ }
+ }
+ },
+ "WIZWIKI_W7500": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2", "5"]
+ },
+ "WIZWIKI_W7500P": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M0",
+ "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2", "5"]
+ },
+ "WIZWIKI_W7500ECO": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "release_versions": ["2", "5"]
+ },
+ "SAMR21G18A": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "macros": ["__SAMR21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+ "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMR21"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+ "release_versions": ["2"],
+ "device_name": "ATSAMR21G18A"
+ },
+ "SAMD21J18A": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "macros": ["__SAMD21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+ "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+ "release_versions": ["2"],
+ "device_name": "ATSAMD21J18A"
+ },
+ "SAMD21G18A": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "macros": ["__SAMD21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+ "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+ "release_versions": ["2"],
+ "device_name": "ATSAMD21G18A"
+ },
+ "SAML21J18A": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0+",
+ "macros": ["__SAML21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+ "extra_labels": ["Atmel", "SAM_CortexM0P", "SAML21"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+ "device_name": "ATSAML21J18A"
+ },
+ "SAMG55J19": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "extra_labels": ["Atmel", "SAM_CortexM4", "SAMG55"],
+ "macros": ["__SAMG55J19__", "BOARD=75", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
+ "default_toolchain": "ARM",
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+ "default_lib": "std",
+ "device_name": "ATSAMG55J19"
+ },
+ "MCU_NRF51_UNIFIED": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
+ "macros": [
+ "NRF51",
+ "TARGET_NRF51822",
+ "BLE_STACK_SUPPORT_REQD",
+ "SOFTDEVICE_PRESENT",
+ "S130",
+ "TARGET_MCU_NRF51822",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+ "NO_SYSTICK",
+ "MBED_TICKLESS"
+ ],
+ "MERGE_BOOTLOADER": false,
+ "extra_labels": [
+ "NORDIC",
+ "MCU_NRF51",
+ "MCU_NRF51822_UNIFIED",
+ "NRF5x",
+ "NRF51",
+ "SDK_11"
+ ],
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "public": false,
+ "MERGE_SOFT_DEVICE": true,
+ "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+ {
+ "boot": "",
+ "name": "s130_nrf51_2.0.0_softdevice.hex",
+ "offset": 110592
+ }
+ ],
+ "detect_code": ["1070"],
+ "post_binary_hook": {
+ "function": "MCU_NRF51Code.binary_hook",
+ "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+ },
+ "program_cycle_s": 6,
+ "features": ["BLE"],
+ "config": {
+ "lf_clock_src": {
+ "value": "NRF_LF_SRC_XTAL",
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
+ },
+ "uart_hwfc": {
+ "help": "Value: 1 for enable, 0 for disable",
+ "value": 1,
+ "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
+ }
+ },
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
+ },
+ "MCU_NRF51_16K_UNIFIED_S130": {
+ "inherits": ["MCU_NRF51_UNIFIED"],
+ "extra_labels_add": ["MCU_NORDIC_16K", "MCU_NRF51_16K_S130", "MCU_NRF51_16K"],
+ "macros_add": ["TARGET_MCU_NORDIC_16K", "TARGET_MCU_NRF51_16K_S130", "TARGET_MCU_NRF51_16K"],
+ "public": false
+ },
+ "MCU_NRF51_32K_UNIFIED": {
+ "inherits": ["MCU_NRF51_UNIFIED"],
+ "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
+ "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
+ "public": false
+ },
+ "NRF51_DK": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "release_versions": ["2", "5"],
+ "device_name": "nRF51822_xxAA"
+ },
+ "NRF51_DONGLE": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "progen": {"target": "nrf51-dongle"},
+ "device_has": ["USTICKER", "LPTICKER", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "release_versions": ["2", "5"]
+ },
+ "OSHCHIP": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "overrides": {"lf_clock_src": "NRF_LF_SRC_RC"},
+ "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_name": "nRF51822_xxAC"
+ },
+ "MCU_NRF52832": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": [
+ "BOARD_PCA10040",
+ "NRF52",
+ "TARGET_NRF52832",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+ "MBED_TICKLESS"
+ ],
+ "device_has": [
+ "ANALOGIN",
+ "FLASH",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "ITM",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "STCLK_OFF_DURING_SLEEP",
+ "TRNG",
+ "USTICKER"
+ ],
+ "extra_labels": [
+ "NORDIC",
+ "NRF5x",
+ "NRF52",
+ "SDK_14_2",
+ "SOFTDEVICE_COMMON",
+ "SOFTDEVICE_S132_FULL"
+ ],
+ "config": {
+ "lf_clock_src": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC",
+ "help": "Select Low Frequency clock source. Options: NRF_LF_SRC_XTAL, NRF_LF_SRC_SYNTH, and NRF_LF_SRC_RC",
+ "value": "NRF_LF_SRC_XTAL"
+ },
+ "lf_clock_rc_calib_timer_interval": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL",
+ "value": 16
+ },
+ "lf_clock_rc_calib_mode_config": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG",
+ "value": 0
+ }
+ },
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "public": false,
+ "detect_code": ["1101"],
+ "program_cycle_s": 6,
+ "bootloader_supported": true
+ },
+ "NRF52_DK": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "UBLOX_EVA_NINA": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "UBLOX_EVK_NINA_B1": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "MTB_UBLOX_NINA_B1": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "MTB_LAIRD_BL652": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "DELTA_DFBM_NQ620": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "MCU_NRF52840": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": [
+ "BOARD_PCA10056",
+ "NRF52840_XXAA",
+ "TARGET_NRF52840",
+ "CMSIS_VECTAB_VIRTUAL",
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+ "MBED_TICKLESS",
+ "MBEDTLS_CONFIG_HW_SUPPORT"
+ ],
+ "features": ["CRYPTOCELL310"],
+ "device_has": [
+ "ANALOGIN",
+ "FLASH",
+ "I2C",
+ "I2C_ASYNCH",
+ "INTERRUPTIN",
+ "ITM",
+ "LPTICKER",
+ "PORTIN",
+ "PORTINOUT",
+ "PORTOUT",
+ "PWMOUT",
+ "SERIAL",
+ "SERIAL_ASYNCH",
+ "SERIAL_FC",
+ "SLEEP",
+ "SPI",
+ "SPI_ASYNCH",
+ "STCLK_OFF_DURING_SLEEP",
+ "TRNG",
+ "USTICKER"
+ ],
+ "extra_labels": [
+ "NORDIC",
+ "NRF5x",
+ "NRF52",
+ "SDK_14_2",
+ "SOFTDEVICE_COMMON",
+ "SOFTDEVICE_S140_FULL"
+ ],
+ "config": {
+ "lf_clock_src": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC",
+ "help": "Select Low Frequency clock source. Options: NRF_LF_SRC_XTAL, NRF_LF_SRC_SYNTH, and NRF_LF_SRC_RC",
+ "value": "NRF_LF_SRC_XTAL"
+ },
+ "lf_clock_rc_calib_timer_interval": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL",
+ "value": 16
+ },
+ "lf_clock_rc_calib_mode_config": {
+ "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG",
+ "value": 0
+ }
+ },
+ "OUTPUT_EXT": "hex",
+ "is_disk_virtual": true,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "public": false,
+ "detect_code": ["1101"],
+ "program_cycle_s": 6,
+ "bootloader_supported": true
+ },
+ "NRF52840_DK": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52840"],
+ "release_versions": ["5"],
+ "device_name": "nRF52840_xxAA"
+ },
+ "BLUEPILL_F103C8": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M3",
+ "default_toolchain": "GCC_ARM",
+ "extra_labels_add": ["STM32F1", "STM32F103C8"],
+ "supported_toolchains": ["GCC_ARM"],
+ "device_has_add": [],
+ "device_has_remove": ["STDIO_MESSAGES", "LPTICKER"]
+ },
+ "NUMAKER_PFM_NUC472": {
+ "core": "Cortex-M4F",
+ "default_toolchain": "ARM",
+ "extra_labels": ["NUVOTON", "NUC472", "NU_XRAM_SUPPORTED", "FLASH_CMSIS_ALGO", "NUVOTON_EMAC"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
+ "value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+ "value": "GPIO_DBCTL_DBCLKSEL_16"
+ }
+ },
+ "inherits": ["Target"],
+ "features": ["LWIP"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN", "FLASH", "EMAC"],
+ "release_versions": ["5"],
+ "device_name": "NUC472HI8AE",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "NCS36510": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "extra_labels": ["ONSEMI"],
+ "config": {
+ "mac-addr-low": {
+ "help": "Lower 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
+ "value": "0xFFFFFFFF"
+ },
+ "mac-addr-high": {
+ "help": "Higher 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
+ "value": "0xFFFFFFFF"
+ },
+ "32KHz-clk-trim": {
+ "help": "32KHz clock trim",
+ "value": "0x39"
+ },
+ "32MHz-clk-trim": {
+ "help": "32MHz clock trim",
+ "value": "0x17"
+ },
+ "rssi-trim": {
+ "help": "RSSI trim",
+ "value": "0x3D"
+ },
+ "txtune-trim": {
+ "help": "TX tune trim",
+ "value": "0xFFFFFFFF"
+ }
+ },
+ "OUTPUT_EXT": "hex",
+ "post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
+ "macros": ["CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "TRNG", "SPISLAVE"],
+ "release_versions": ["2", "5"]
+ },
+ "NUMAKER_PFM_M453": {
+ "core": "Cortex-M4F",
+ "default_toolchain": "ARM",
+ "extra_labels": ["NUVOTON", "M451", "NUMAKER_PFM_M453", "FLASH_CMSIS_ALGO"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+ "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+ "value": "GPIO_DBCTL_DBCLKSEL_16"
+ }
+ },
+ "inherits": ["Target"],
+ "macros_add": ["LPTICKER_DELAY_TICKS=3"],
+ "progen": {"target": "numaker-pfm-m453"},
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "CAN", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "M453VG6AE",
+ "bootloader_supported": true
+ },
+ "NUMAKER_PFM_NANO130": {
+ "core": "Cortex-M0",
+ "default_toolchain": "ARM",
+ "extra_labels": ["NUVOTON", "NANO100", "NANO130KE3BN"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_IRC10K",
+ "value": "GPIO_DBCLKSRC_IRC10K"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768",
+ "value": "GPIO_DBCLKSEL_16"
+ },
+ "clock-pll": {
+ "help": "Choose clock source to clock PLL: NU_HXT_PLL or NU_HIRC_PLL",
+ "macro_name": "NU_CLOCK_PLL",
+ "value": "NU_HIRC_PLL"
+ }
+ },
+ "inherits": ["Target"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"","MBED_FAULT_HANDLER_DISABLED", "LPTICKER_DELAY_TICKS=3"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+ "release_versions": ["5"],
+ "device_name": "NANO130KE3BN"
+ },
+ "HI2110": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "default_toolchain": "GCC_ARM",
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "extra_labels": ["ublox"],
+ "macros": ["TARGET_PROCESSOR_FAMILY_BOUDICA", "BOUDICA_SARA", "NDEBUG=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "public": false,
+ "target_overrides": {
+ "*": {
+ "core.stdio-flush-at-exit": false
+ }
+ },
+ "device_has": ["INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "STDIO_MESSAGES"],
+ "default_lib": "std",
+ "release_versions": []
+ },
+ "SARA_NBIOT": {
+ "inherits": ["HI2110"],
+ "extra_labels": ["ublox", "HI2110"],
+ "public": false
+ },
+ "SARA_NBIOT_EVK": {
+ "inherits": ["SARA_NBIOT"],
+ "extra_labels": ["ublox", "HI2110", "SARA_NBIOT"]
+ },
+ "REALTEK_RTL8195AM": {
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M3",
+ "default_toolchain": "GCC_ARM",
+ "inherits": ["Target"],
+ "detect_code": ["4600"],
+ "extra_labels": ["Realtek", "AMEBA", "RTL8195A", "RTW_EMAC"],
+ "macros": ["__RTL8195A__","CONFIG_PLATFORM_8195A","CONFIG_MBED_ENABLED","PLATFORM_CMSIS_RTOS","MBED_FAULT_HANDLER_DISABLED"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "features": ["LWIP"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "TRNG", "FLASH"],
+ "post_binary_hook": {
+ "function": "RTL8195ACode.binary_hook",
+ "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+ },
+ "release_versions": ["5"],
+ "overrides": {
+ "network-default-interface-type": "WIFI"
+ }
+ },
+ "VBLUNO51_LEGACY": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K"],
+ "detect_code": ["C006"],
+ "overrides": {"uart_hwfc": 0},
+ "extra_labels_add": ["VBLUNO51"]
+ },
+ "VBLUNO51_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "detect_code": ["C006"],
+ "overrides": {"uart_hwfc": 0},
+ "extra_labels_add": ["VBLUNO51"],
+ "macros_add": ["TARGET_VBLUNO51"]
+ },
+ "VBLUNO51_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "detect_code": ["C006"],
+ "overrides": {"uart_hwfc": 0},
+ "extra_labels_add": ["VBLUNO51"],
+ "macros_add": ["TARGET_VBLUNO51"]
+ },
+ "VBLUNO51": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "detect_code": ["C006"],
+ "overrides": {"uart_hwfc": 0},
+ "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "release_versions": ["2"],
+ "device_name": "nRF51822_xxAC"
+ },
+ "DISCO_L496AG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L496AG", "STM32L496xG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0822"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L496AG"
+ },
+ "NUCLEO_L496ZG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L496ZG", "STM32L496xG"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ },
+ "lpticker_delay_ticks": {
+ "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+ "value": 3,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
+ },
+ "detect_code": ["0823"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L496ZG"
+ },
+ "NUCLEO_L496ZG_P": {
+ "inherits": ["NUCLEO_L496ZG"],
+ "detect_code": ["0828"]
+ },
+ "VBLUNO52": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA"
+ },
+ "NUMAKER_PFM_M487": {
+ "core": "Cortex-M4F",
+ "default_toolchain": "ARM",
+ "extra_labels": ["NUVOTON", "M480", "FLASH_CMSIS_ALGO","NUVOTON_EMAC"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+ "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+ "value": "GPIO_DBCTL_DBCLKSEL_16"
+ },
+ "usb-device-hsusbd": {
+ "help": "Select high-speed USB device or not",
+ "value": 1
+ },
+ "ctrl01-enable": {
+ "help": "Enable control_01",
+ "value": 0
+ }
+ },
+ "inherits": ["Target"],
+ "features": ["LWIP"],
+ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH", "CAN", "EMAC"],
+ "release_versions": ["5"],
+ "device_name": "M487JIDAE",
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
+ }
+ },
+ "TMPM066": {
+ "inherits": ["Target"],
+ "core": "Cortex-M0",
+ "is_disk_virtual": true,
+ "extra_labels": ["TOSHIBA"],
+ "macros": ["__TMPM066__", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "I2C", "I2CSLAVE", "STDIO_MESSAGES", "PWMOUT"],
+ "device_name": "TMPM066FWUG",
+ "detect_code": ["7011"],
+ "release_versions": ["5"]
+ },
+ "SAKURAIO_EVB_01": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": [],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "release_versions": ["2"],
+ "device_name": "STM32F411RE"
+ },
+ "TMPM46B": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "is_disk_virtual": true,
+ "extra_labels": ["TOSHIBA"],
+ "macros": ["__TMPM46B__"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "I2C", "STDIO_MESSAGES", "TRNG", "FLASH", "SLEEP"],
+ "device_name": "TMPM46BF10FG",
+ "detect_code": ["7013"],
+ "release_versions": ["5"],
+ "bootloader_supported": true
+ },
+ "ARM_FM": {
+ "inherits": ["Target"],
+ "public": false,
+ "extra_labels": ["ARM_FM"]
+ },
+ "FVP_MPS2": {
+ "inherits": ["ARM_FM"],
+ "public": false,
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "OUTPUT_EXT": "elf",
+ "device_has": ["AACI", "ANALOGIN", "CLCD", "FLASH", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC", "USTICKER"],
+ "release_versions": ["5"]
+ },
+ "FVP_MPS2_M0": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M0",
+ "macros": ["CMSDK_CM0"]
+ },
+ "FVP_MPS2_M0P": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M0+",
+ "macros": ["CMSDK_CM0plus"]
+ },
+ "FVP_MPS2_M3": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M3",
+ "macros": ["CMSDK_CM3"]
+ },
+ "FVP_MPS2_M4": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M4",
+ "macros": ["CMSDK_CM4"]
+ },
+ "FVP_MPS2_M7": {
+ "inherits": ["FVP_MPS2"],
+ "core": "Cortex-M7",
+ "macros": ["CMSDK_CM7"]
+ },
+ "NUMAKER_PFM_M2351": {
+ "core": "Cortex-M23-NS",
+ "default_toolchain": "ARMC6",
+ "extra_labels": ["NUVOTON", "M2351", "M2351KIAAEES", "FLASH_CMSIS_ALGO"],
+ "OUTPUT_EXT": "hex",
+ "macros": ["MBED_FAULT_HANDLER_DISABLED", "MBED_TZ_DEFAULT_ACCESS=1", "LPTICKER_DELAY_TICKS=3"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARMC6"],
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+ "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+ },
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+ "value": "GPIO_DBCTL_DBCLKSEL_16"
+ }
+ },
+ "mbed_rom_start": "0x10040000",
+ "mbed_rom_size": "0x40000",
+ "mbed_ram_start": "0x30008000",
+ "mbed_ram_size": "0x10000",
+ "inherits": ["Target"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH"],
+ "detect_code": ["1305"],
+ "release_versions": ["5"],
+ "device_name": "M2351KIAAEES",
+ "bootloader_supported": true
+ },
+ "TMPM3H6": {
+ "inherits": ["Target"],
+ "core": "Cortex-M3",
+ "is_disk_virtual": true,
+ "extra_labels": ["TOSHIBA"],
+ "macros": ["__TMPM3H6__"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "I2C", "I2CSLAVE", "STDIO_MESSAGES"],
+ "device_name": "TMPM3H6FWFG",
+ "detect_code": ["7012"],
+ "release_versions": ["5"]
+ }
+}